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Clock interconnect

Tile CLK_ROOT_8PLL

Cells: 30

Bel DCS_SW0

ecp2m CLK_ROOT_8PLL bel DCS_SW0
PinDirectionWires
OUTinputCELL0.PCLK6

Bel DCS_SW1

ecp2m CLK_ROOT_8PLL bel DCS_SW1
PinDirectionWires
OUTinputCELL0.PCLK7

Bel DCS_SE0

ecp2m CLK_ROOT_8PLL bel DCS_SE0
PinDirectionWires
OUTinputCELL1.PCLK6

Bel DCS_SE1

ecp2m CLK_ROOT_8PLL bel DCS_SE1
PinDirectionWires
OUTinputCELL1.PCLK7

Bel DCS_NW0

ecp2m CLK_ROOT_8PLL bel DCS_NW0
PinDirectionWires
OUTinputCELL2.PCLK6

Bel DCS_NW1

ecp2m CLK_ROOT_8PLL bel DCS_NW1
PinDirectionWires
OUTinputCELL2.PCLK7

Bel DCS_NE0

ecp2m CLK_ROOT_8PLL bel DCS_NE0
PinDirectionWires
OUTinputCELL3.PCLK6

Bel DCS_NE1

ecp2m CLK_ROOT_8PLL bel DCS_NE1
PinDirectionWires
OUTinputCELL3.PCLK7

Bel CLK_ROOT

ecp2m CLK_ROOT_8PLL bel CLK_ROOT
PinDirectionWires
PCLK0_NEinputCELL3.PCLK0
PCLK0_NWinputCELL2.PCLK0
PCLK0_SEinputCELL1.PCLK0
PCLK0_SWinputCELL0.PCLK0
PCLK1_NEinputCELL3.PCLK1
PCLK1_NWinputCELL2.PCLK1
PCLK1_SEinputCELL1.PCLK1
PCLK1_SWinputCELL0.PCLK1
PCLK2_NEinputCELL3.PCLK2
PCLK2_NWinputCELL2.PCLK2
PCLK2_SEinputCELL1.PCLK2
PCLK2_SWinputCELL0.PCLK2
PCLK3_NEinputCELL3.PCLK3
PCLK3_NWinputCELL2.PCLK3
PCLK3_SEinputCELL1.PCLK3
PCLK3_SWinputCELL0.PCLK3
PCLK4_NEinputCELL3.PCLK4
PCLK4_NWinputCELL2.PCLK4
PCLK4_SEinputCELL1.PCLK4
PCLK4_SWinputCELL0.PCLK4
PCLK5_NEinputCELL3.PCLK5
PCLK5_NWinputCELL2.PCLK5
PCLK5_SEinputCELL1.PCLK5
PCLK5_SWinputCELL0.PCLK5
PCLK_IN_E0inputCELL6.IMUX_C3
PCLK_IN_E1inputCELL7.IMUX_C3
PCLK_IN_E2inputCELL8.IMUX_C3
PCLK_IN_E3inputCELL9.IMUX_C3
PCLK_IN_N0inputCELL12.IMUX_C3
PCLK_IN_N1inputCELL13.IMUX_C3
PCLK_IN_S0inputCELL10.IMUX_C3
PCLK_IN_S1inputCELL11.IMUX_C3
PCLK_IN_W0inputCELL4.IMUX_C3
PCLK_IN_W1inputCELL5.IMUX_C3
SCLK_IN_E0inputCELL18.IMUX_C3
SCLK_IN_E1inputCELL19.IMUX_C3
SCLK_IN_E2inputCELL20.IMUX_C3
SCLK_IN_E3inputCELL21.IMUX_C3
SCLK_IN_N0inputCELL26.IMUX_C3
SCLK_IN_N1inputCELL27.IMUX_C3
SCLK_IN_N2inputCELL28.IMUX_C3
SCLK_IN_N3inputCELL29.IMUX_C3
SCLK_IN_S0inputCELL22.IMUX_C3
SCLK_IN_S1inputCELL23.IMUX_C3
SCLK_IN_S2inputCELL24.IMUX_C3
SCLK_IN_S3inputCELL25.IMUX_C3
SCLK_IN_W0inputCELL14.IMUX_C3
SCLK_IN_W1inputCELL15.IMUX_C3
SCLK_IN_W2inputCELL16.IMUX_C3
SCLK_IN_W3inputCELL17.IMUX_C3

Bel wires

ecp2m CLK_ROOT_8PLL bel wires
WirePins
CELL0.PCLK0CLK_ROOT.PCLK0_SW
CELL0.PCLK1CLK_ROOT.PCLK1_SW
CELL0.PCLK2CLK_ROOT.PCLK2_SW
CELL0.PCLK3CLK_ROOT.PCLK3_SW
CELL0.PCLK4CLK_ROOT.PCLK4_SW
CELL0.PCLK5CLK_ROOT.PCLK5_SW
CELL0.PCLK6DCS_SW0.OUT
CELL0.PCLK7DCS_SW1.OUT
CELL1.PCLK0CLK_ROOT.PCLK0_SE
CELL1.PCLK1CLK_ROOT.PCLK1_SE
CELL1.PCLK2CLK_ROOT.PCLK2_SE
CELL1.PCLK3CLK_ROOT.PCLK3_SE
CELL1.PCLK4CLK_ROOT.PCLK4_SE
CELL1.PCLK5CLK_ROOT.PCLK5_SE
CELL1.PCLK6DCS_SE0.OUT
CELL1.PCLK7DCS_SE1.OUT
CELL2.PCLK0CLK_ROOT.PCLK0_NW
CELL2.PCLK1CLK_ROOT.PCLK1_NW
CELL2.PCLK2CLK_ROOT.PCLK2_NW
CELL2.PCLK3CLK_ROOT.PCLK3_NW
CELL2.PCLK4CLK_ROOT.PCLK4_NW
CELL2.PCLK5CLK_ROOT.PCLK5_NW
CELL2.PCLK6DCS_NW0.OUT
CELL2.PCLK7DCS_NW1.OUT
CELL3.PCLK0CLK_ROOT.PCLK0_NE
CELL3.PCLK1CLK_ROOT.PCLK1_NE
CELL3.PCLK2CLK_ROOT.PCLK2_NE
CELL3.PCLK3CLK_ROOT.PCLK3_NE
CELL3.PCLK4CLK_ROOT.PCLK4_NE
CELL3.PCLK5CLK_ROOT.PCLK5_NE
CELL3.PCLK6DCS_NE0.OUT
CELL3.PCLK7DCS_NE1.OUT
CELL4.IMUX_C3CLK_ROOT.PCLK_IN_W0
CELL5.IMUX_C3CLK_ROOT.PCLK_IN_W1
CELL6.IMUX_C3CLK_ROOT.PCLK_IN_E0
CELL7.IMUX_C3CLK_ROOT.PCLK_IN_E1
CELL8.IMUX_C3CLK_ROOT.PCLK_IN_E2
CELL9.IMUX_C3CLK_ROOT.PCLK_IN_E3
CELL10.IMUX_C3CLK_ROOT.PCLK_IN_S0
CELL11.IMUX_C3CLK_ROOT.PCLK_IN_S1
CELL12.IMUX_C3CLK_ROOT.PCLK_IN_N0
CELL13.IMUX_C3CLK_ROOT.PCLK_IN_N1
CELL14.IMUX_C3CLK_ROOT.SCLK_IN_W0
CELL15.IMUX_C3CLK_ROOT.SCLK_IN_W1
CELL16.IMUX_C3CLK_ROOT.SCLK_IN_W2
CELL17.IMUX_C3CLK_ROOT.SCLK_IN_W3
CELL18.IMUX_C3CLK_ROOT.SCLK_IN_E0
CELL19.IMUX_C3CLK_ROOT.SCLK_IN_E1
CELL20.IMUX_C3CLK_ROOT.SCLK_IN_E2
CELL21.IMUX_C3CLK_ROOT.SCLK_IN_E3
CELL22.IMUX_C3CLK_ROOT.SCLK_IN_S0
CELL23.IMUX_C3CLK_ROOT.SCLK_IN_S1
CELL24.IMUX_C3CLK_ROOT.SCLK_IN_S2
CELL25.IMUX_C3CLK_ROOT.SCLK_IN_S3
CELL26.IMUX_C3CLK_ROOT.SCLK_IN_N0
CELL27.IMUX_C3CLK_ROOT.SCLK_IN_N1
CELL28.IMUX_C3CLK_ROOT.SCLK_IN_N2
CELL29.IMUX_C3CLK_ROOT.SCLK_IN_N3

Tile ECLK_ROOT_E

Cells: 1

Bel ECLK_ROOT

ecp2m ECLK_ROOT_E bel ECLK_ROOT
PinDirectionWires
ECLK0_INinputIMUX_B2
ECLK1_INinputIMUX_B3
PAD0_OUToutputOUT_F6
PAD1_OUToutputOUT_F7

Bel wires

ecp2m ECLK_ROOT_E bel wires
WirePins
IMUX_B2ECLK_ROOT.ECLK0_IN
IMUX_B3ECLK_ROOT.ECLK1_IN
OUT_F6ECLK_ROOT.PAD0_OUT
OUT_F7ECLK_ROOT.PAD1_OUT

Tile ECLK_ROOT_N

Cells: 2

Bel ECLK_ROOT

ecp2m ECLK_ROOT_N bel ECLK_ROOT
PinDirectionWires
ECLK0_INinputCELL0.IMUX_B2
ECLK1_INinputCELL0.IMUX_B3
PAD0_OUT0outputCELL0.OUT_F6
PAD0_OUT1outputCELL1.OUT_F6
PAD1_OUT0outputCELL0.OUT_F7
PAD1_OUT1outputCELL1.OUT_F7

Bel wires

ecp2m ECLK_ROOT_N bel wires
WirePins
CELL0.IMUX_B2ECLK_ROOT.ECLK0_IN
CELL0.IMUX_B3ECLK_ROOT.ECLK1_IN
CELL0.OUT_F6ECLK_ROOT.PAD0_OUT0
CELL0.OUT_F7ECLK_ROOT.PAD1_OUT0
CELL1.OUT_F6ECLK_ROOT.PAD0_OUT1
CELL1.OUT_F7ECLK_ROOT.PAD1_OUT1

Tile ECLK_ROOT_S

Cells: 2

Bel ECLK_ROOT

ecp2m ECLK_ROOT_S bel ECLK_ROOT
PinDirectionWires
ECLK0_INinputCELL0.IMUX_B2
ECLK1_INinputCELL0.IMUX_B3
PAD0_OUT0outputCELL0.OUT_F6
PAD0_OUT1outputCELL1.OUT_F6
PAD1_OUT0outputCELL0.OUT_F7
PAD1_OUT1outputCELL1.OUT_F7

Bel wires

ecp2m ECLK_ROOT_S bel wires
WirePins
CELL0.IMUX_B2ECLK_ROOT.ECLK0_IN
CELL0.IMUX_B3ECLK_ROOT.ECLK1_IN
CELL0.OUT_F6ECLK_ROOT.PAD0_OUT0
CELL0.OUT_F7ECLK_ROOT.PAD1_OUT0
CELL1.OUT_F6ECLK_ROOT.PAD0_OUT1
CELL1.OUT_F7ECLK_ROOT.PAD1_OUT1

Tile ECLK_ROOT_W

Cells: 1

Bel ECLK_ROOT

ecp2m ECLK_ROOT_W bel ECLK_ROOT
PinDirectionWires
ECLK0_INinputIMUX_B2
ECLK1_INinputIMUX_B3
PAD0_OUToutputOUT_F6
PAD1_OUToutputOUT_F7

Bel wires

ecp2m ECLK_ROOT_W bel wires
WirePins
IMUX_B2ECLK_ROOT.ECLK0_IN
IMUX_B3ECLK_ROOT.ECLK1_IN
OUT_F6ECLK_ROOT.PAD0_OUT
OUT_F7ECLK_ROOT.PAD1_OUT

Tile ECLK_TAP

Cells: 1

Bel ECLK_TAP

ecp2m ECLK_TAP bel ECLK_TAP
PinDirectionWires
ECLK0outputOUT_F6
ECLK1outputOUT_F7

Bel wires

ecp2m ECLK_TAP bel wires
WirePins
OUT_F6ECLK_TAP.ECLK0
OUT_F7ECLK_TAP.ECLK1

Tile HSDCLK_ROOT

Cells: 8

Bel HSDCLK_ROOT

ecp2m HSDCLK_ROOT bel HSDCLK_ROOT
PinDirectionWires
OUT_E0outputCELL4.HSDCLK0
OUT_E1outputCELL5.HSDCLK0
OUT_E2outputCELL6.HSDCLK0
OUT_E3outputCELL7.HSDCLK0
OUT_E4outputCELL4.HSDCLK4
OUT_E5outputCELL5.HSDCLK4
OUT_E6outputCELL6.HSDCLK4
OUT_E7outputCELL7.HSDCLK4
OUT_W0outputCELL0.HSDCLK0
OUT_W1outputCELL1.HSDCLK0
OUT_W2outputCELL2.HSDCLK0
OUT_W3outputCELL3.HSDCLK0
OUT_W4outputCELL0.HSDCLK4
OUT_W5outputCELL1.HSDCLK4
OUT_W6outputCELL2.HSDCLK4
OUT_W7outputCELL3.HSDCLK4

Switchbox HSDCLK_SPLITTER

ecp2m HSDCLK_ROOT switchbox HSDCLK_SPLITTER
DestinationSourceKind
CELL0.HSDCLK0CELL4.HSDCLK0buffer
CELL0.HSDCLK4CELL4.HSDCLK4buffer
CELL1.HSDCLK0CELL5.HSDCLK0buffer
CELL1.HSDCLK4CELL5.HSDCLK4buffer
CELL2.HSDCLK0CELL6.HSDCLK0buffer
CELL2.HSDCLK4CELL6.HSDCLK4buffer
CELL3.HSDCLK0CELL7.HSDCLK0buffer
CELL3.HSDCLK4CELL7.HSDCLK4buffer
CELL4.HSDCLK0CELL0.HSDCLK0buffer
CELL4.HSDCLK4CELL0.HSDCLK4buffer
CELL5.HSDCLK0CELL1.HSDCLK0buffer
CELL5.HSDCLK4CELL1.HSDCLK4buffer
CELL6.HSDCLK0CELL2.HSDCLK0buffer
CELL6.HSDCLK4CELL2.HSDCLK4buffer
CELL7.HSDCLK0CELL3.HSDCLK0buffer
CELL7.HSDCLK4CELL3.HSDCLK4buffer

Bel wires

ecp2m HSDCLK_ROOT bel wires
WirePins
CELL0.HSDCLK0HSDCLK_ROOT.OUT_W0
CELL0.HSDCLK4HSDCLK_ROOT.OUT_W4
CELL1.HSDCLK0HSDCLK_ROOT.OUT_W1
CELL1.HSDCLK4HSDCLK_ROOT.OUT_W5
CELL2.HSDCLK0HSDCLK_ROOT.OUT_W2
CELL2.HSDCLK4HSDCLK_ROOT.OUT_W6
CELL3.HSDCLK0HSDCLK_ROOT.OUT_W3
CELL3.HSDCLK4HSDCLK_ROOT.OUT_W7
CELL4.HSDCLK0HSDCLK_ROOT.OUT_E0
CELL4.HSDCLK4HSDCLK_ROOT.OUT_E4
CELL5.HSDCLK0HSDCLK_ROOT.OUT_E1
CELL5.HSDCLK4HSDCLK_ROOT.OUT_E5
CELL6.HSDCLK0HSDCLK_ROOT.OUT_E2
CELL6.HSDCLK4HSDCLK_ROOT.OUT_E6
CELL7.HSDCLK0HSDCLK_ROOT.OUT_E3
CELL7.HSDCLK4HSDCLK_ROOT.OUT_E7

Tile HSDCLK_SPLITTER

Cells: 8

Switchbox HSDCLK_SPLITTER

ecp2m HSDCLK_SPLITTER switchbox HSDCLK_SPLITTER
DestinationSourceKind
CELL0.HSDCLK0CELL4.HSDCLK0buffer
CELL0.HSDCLK4CELL4.HSDCLK4buffer
CELL1.HSDCLK0CELL5.HSDCLK0buffer
CELL1.HSDCLK4CELL5.HSDCLK4buffer
CELL2.HSDCLK0CELL6.HSDCLK0buffer
CELL2.HSDCLK4CELL6.HSDCLK4buffer
CELL3.HSDCLK0CELL7.HSDCLK0buffer
CELL3.HSDCLK4CELL7.HSDCLK4buffer
CELL4.HSDCLK0CELL0.HSDCLK0buffer
CELL4.HSDCLK4CELL0.HSDCLK4buffer
CELL5.HSDCLK0CELL1.HSDCLK0buffer
CELL5.HSDCLK4CELL1.HSDCLK4buffer
CELL6.HSDCLK0CELL2.HSDCLK0buffer
CELL6.HSDCLK4CELL2.HSDCLK4buffer
CELL7.HSDCLK0CELL3.HSDCLK0buffer
CELL7.HSDCLK4CELL3.HSDCLK4buffer

Tile SCLK0_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp2m SCLK0_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK0fixed buffer
SCLK4VSDCLK1fixed buffer

Tile SCLK1_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp2m SCLK1_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK1VSDCLK0fixed buffer
SCLK5VSDCLK1fixed buffer

Tile SCLK2_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp2m SCLK2_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK2VSDCLK0fixed buffer
SCLK6VSDCLK1fixed buffer

Tile SCLK3_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp2m SCLK3_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK3VSDCLK0fixed buffer
SCLK7VSDCLK1fixed buffer