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Clock interconnect

Tile CLK_ROOT_8PLL

Cells: 30

Bel DCS_SW0

ecp2m CLK_ROOT_8PLL bel DCS_SW0
PinDirectionWires
OUTinputTCELL0:PCLK6

Bel DCS_SW1

ecp2m CLK_ROOT_8PLL bel DCS_SW1
PinDirectionWires
OUTinputTCELL0:PCLK7

Bel DCS_SE0

ecp2m CLK_ROOT_8PLL bel DCS_SE0
PinDirectionWires
OUTinputTCELL1:PCLK6

Bel DCS_SE1

ecp2m CLK_ROOT_8PLL bel DCS_SE1
PinDirectionWires
OUTinputTCELL1:PCLK7

Bel DCS_NW0

ecp2m CLK_ROOT_8PLL bel DCS_NW0
PinDirectionWires
OUTinputTCELL2:PCLK6

Bel DCS_NW1

ecp2m CLK_ROOT_8PLL bel DCS_NW1
PinDirectionWires
OUTinputTCELL2:PCLK7

Bel DCS_NE0

ecp2m CLK_ROOT_8PLL bel DCS_NE0
PinDirectionWires
OUTinputTCELL3:PCLK6

Bel DCS_NE1

ecp2m CLK_ROOT_8PLL bel DCS_NE1
PinDirectionWires
OUTinputTCELL3:PCLK7

Bel CLK_ROOT

ecp2m CLK_ROOT_8PLL bel CLK_ROOT
PinDirectionWires
PCLK0_NEinputTCELL3:PCLK0
PCLK0_NWinputTCELL2:PCLK0
PCLK0_SEinputTCELL1:PCLK0
PCLK0_SWinputTCELL0:PCLK0
PCLK1_NEinputTCELL3:PCLK1
PCLK1_NWinputTCELL2:PCLK1
PCLK1_SEinputTCELL1:PCLK1
PCLK1_SWinputTCELL0:PCLK1
PCLK2_NEinputTCELL3:PCLK2
PCLK2_NWinputTCELL2:PCLK2
PCLK2_SEinputTCELL1:PCLK2
PCLK2_SWinputTCELL0:PCLK2
PCLK3_NEinputTCELL3:PCLK3
PCLK3_NWinputTCELL2:PCLK3
PCLK3_SEinputTCELL1:PCLK3
PCLK3_SWinputTCELL0:PCLK3
PCLK4_NEinputTCELL3:PCLK4
PCLK4_NWinputTCELL2:PCLK4
PCLK4_SEinputTCELL1:PCLK4
PCLK4_SWinputTCELL0:PCLK4
PCLK5_NEinputTCELL3:PCLK5
PCLK5_NWinputTCELL2:PCLK5
PCLK5_SEinputTCELL1:PCLK5
PCLK5_SWinputTCELL0:PCLK5
PCLK_IN_E0inputTCELL6:IMUX_C3
PCLK_IN_E1inputTCELL7:IMUX_C3
PCLK_IN_E2inputTCELL8:IMUX_C3
PCLK_IN_E3inputTCELL9:IMUX_C3
PCLK_IN_N0inputTCELL12:IMUX_C3
PCLK_IN_N1inputTCELL13:IMUX_C3
PCLK_IN_S0inputTCELL10:IMUX_C3
PCLK_IN_S1inputTCELL11:IMUX_C3
PCLK_IN_W0inputTCELL4:IMUX_C3
PCLK_IN_W1inputTCELL5:IMUX_C3
SCLK_IN_E0inputTCELL18:IMUX_C3
SCLK_IN_E1inputTCELL19:IMUX_C3
SCLK_IN_E2inputTCELL20:IMUX_C3
SCLK_IN_E3inputTCELL21:IMUX_C3
SCLK_IN_N0inputTCELL26:IMUX_C3
SCLK_IN_N1inputTCELL27:IMUX_C3
SCLK_IN_N2inputTCELL28:IMUX_C3
SCLK_IN_N3inputTCELL29:IMUX_C3
SCLK_IN_S0inputTCELL22:IMUX_C3
SCLK_IN_S1inputTCELL23:IMUX_C3
SCLK_IN_S2inputTCELL24:IMUX_C3
SCLK_IN_S3inputTCELL25:IMUX_C3
SCLK_IN_W0inputTCELL14:IMUX_C3
SCLK_IN_W1inputTCELL15:IMUX_C3
SCLK_IN_W2inputTCELL16:IMUX_C3
SCLK_IN_W3inputTCELL17:IMUX_C3

Bel wires

ecp2m CLK_ROOT_8PLL bel wires
WirePins
TCELL0:PCLK0CLK_ROOT.PCLK0_SW
TCELL0:PCLK1CLK_ROOT.PCLK1_SW
TCELL0:PCLK2CLK_ROOT.PCLK2_SW
TCELL0:PCLK3CLK_ROOT.PCLK3_SW
TCELL0:PCLK4CLK_ROOT.PCLK4_SW
TCELL0:PCLK5CLK_ROOT.PCLK5_SW
TCELL0:PCLK6DCS_SW0.OUT
TCELL0:PCLK7DCS_SW1.OUT
TCELL1:PCLK0CLK_ROOT.PCLK0_SE
TCELL1:PCLK1CLK_ROOT.PCLK1_SE
TCELL1:PCLK2CLK_ROOT.PCLK2_SE
TCELL1:PCLK3CLK_ROOT.PCLK3_SE
TCELL1:PCLK4CLK_ROOT.PCLK4_SE
TCELL1:PCLK5CLK_ROOT.PCLK5_SE
TCELL1:PCLK6DCS_SE0.OUT
TCELL1:PCLK7DCS_SE1.OUT
TCELL2:PCLK0CLK_ROOT.PCLK0_NW
TCELL2:PCLK1CLK_ROOT.PCLK1_NW
TCELL2:PCLK2CLK_ROOT.PCLK2_NW
TCELL2:PCLK3CLK_ROOT.PCLK3_NW
TCELL2:PCLK4CLK_ROOT.PCLK4_NW
TCELL2:PCLK5CLK_ROOT.PCLK5_NW
TCELL2:PCLK6DCS_NW0.OUT
TCELL2:PCLK7DCS_NW1.OUT
TCELL3:PCLK0CLK_ROOT.PCLK0_NE
TCELL3:PCLK1CLK_ROOT.PCLK1_NE
TCELL3:PCLK2CLK_ROOT.PCLK2_NE
TCELL3:PCLK3CLK_ROOT.PCLK3_NE
TCELL3:PCLK4CLK_ROOT.PCLK4_NE
TCELL3:PCLK5CLK_ROOT.PCLK5_NE
TCELL3:PCLK6DCS_NE0.OUT
TCELL3:PCLK7DCS_NE1.OUT
TCELL4:IMUX_C3CLK_ROOT.PCLK_IN_W0
TCELL5:IMUX_C3CLK_ROOT.PCLK_IN_W1
TCELL6:IMUX_C3CLK_ROOT.PCLK_IN_E0
TCELL7:IMUX_C3CLK_ROOT.PCLK_IN_E1
TCELL8:IMUX_C3CLK_ROOT.PCLK_IN_E2
TCELL9:IMUX_C3CLK_ROOT.PCLK_IN_E3
TCELL10:IMUX_C3CLK_ROOT.PCLK_IN_S0
TCELL11:IMUX_C3CLK_ROOT.PCLK_IN_S1
TCELL12:IMUX_C3CLK_ROOT.PCLK_IN_N0
TCELL13:IMUX_C3CLK_ROOT.PCLK_IN_N1
TCELL14:IMUX_C3CLK_ROOT.SCLK_IN_W0
TCELL15:IMUX_C3CLK_ROOT.SCLK_IN_W1
TCELL16:IMUX_C3CLK_ROOT.SCLK_IN_W2
TCELL17:IMUX_C3CLK_ROOT.SCLK_IN_W3
TCELL18:IMUX_C3CLK_ROOT.SCLK_IN_E0
TCELL19:IMUX_C3CLK_ROOT.SCLK_IN_E1
TCELL20:IMUX_C3CLK_ROOT.SCLK_IN_E2
TCELL21:IMUX_C3CLK_ROOT.SCLK_IN_E3
TCELL22:IMUX_C3CLK_ROOT.SCLK_IN_S0
TCELL23:IMUX_C3CLK_ROOT.SCLK_IN_S1
TCELL24:IMUX_C3CLK_ROOT.SCLK_IN_S2
TCELL25:IMUX_C3CLK_ROOT.SCLK_IN_S3
TCELL26:IMUX_C3CLK_ROOT.SCLK_IN_N0
TCELL27:IMUX_C3CLK_ROOT.SCLK_IN_N1
TCELL28:IMUX_C3CLK_ROOT.SCLK_IN_N2
TCELL29:IMUX_C3CLK_ROOT.SCLK_IN_N3

Tile ECLK_ROOT_E

Cells: 1

Bel ECLK_ROOT

ecp2m ECLK_ROOT_E bel ECLK_ROOT
PinDirectionWires
ECLK0_INinputIMUX_B2
ECLK1_INinputIMUX_B3
PAD0_OUToutputOUT_F6
PAD1_OUToutputOUT_F7

Bel wires

ecp2m ECLK_ROOT_E bel wires
WirePins
IMUX_B2ECLK_ROOT.ECLK0_IN
IMUX_B3ECLK_ROOT.ECLK1_IN
OUT_F6ECLK_ROOT.PAD0_OUT
OUT_F7ECLK_ROOT.PAD1_OUT

Tile ECLK_ROOT_N

Cells: 2

Bel ECLK_ROOT

ecp2m ECLK_ROOT_N bel ECLK_ROOT
PinDirectionWires
ECLK0_INinputTCELL0:IMUX_B2
ECLK1_INinputTCELL0:IMUX_B3
PAD0_OUT0outputTCELL0:OUT_F6
PAD0_OUT1outputTCELL1:OUT_F6
PAD1_OUT0outputTCELL0:OUT_F7
PAD1_OUT1outputTCELL1:OUT_F7

Bel wires

ecp2m ECLK_ROOT_N bel wires
WirePins
TCELL0:IMUX_B2ECLK_ROOT.ECLK0_IN
TCELL0:IMUX_B3ECLK_ROOT.ECLK1_IN
TCELL0:OUT_F6ECLK_ROOT.PAD0_OUT0
TCELL0:OUT_F7ECLK_ROOT.PAD1_OUT0
TCELL1:OUT_F6ECLK_ROOT.PAD0_OUT1
TCELL1:OUT_F7ECLK_ROOT.PAD1_OUT1

Tile ECLK_ROOT_S

Cells: 2

Bel ECLK_ROOT

ecp2m ECLK_ROOT_S bel ECLK_ROOT
PinDirectionWires
ECLK0_INinputTCELL0:IMUX_B2
ECLK1_INinputTCELL0:IMUX_B3
PAD0_OUT0outputTCELL0:OUT_F6
PAD0_OUT1outputTCELL1:OUT_F6
PAD1_OUT0outputTCELL0:OUT_F7
PAD1_OUT1outputTCELL1:OUT_F7

Bel wires

ecp2m ECLK_ROOT_S bel wires
WirePins
TCELL0:IMUX_B2ECLK_ROOT.ECLK0_IN
TCELL0:IMUX_B3ECLK_ROOT.ECLK1_IN
TCELL0:OUT_F6ECLK_ROOT.PAD0_OUT0
TCELL0:OUT_F7ECLK_ROOT.PAD1_OUT0
TCELL1:OUT_F6ECLK_ROOT.PAD0_OUT1
TCELL1:OUT_F7ECLK_ROOT.PAD1_OUT1

Tile ECLK_ROOT_W

Cells: 1

Bel ECLK_ROOT

ecp2m ECLK_ROOT_W bel ECLK_ROOT
PinDirectionWires
ECLK0_INinputIMUX_B2
ECLK1_INinputIMUX_B3
PAD0_OUToutputOUT_F6
PAD1_OUToutputOUT_F7

Bel wires

ecp2m ECLK_ROOT_W bel wires
WirePins
IMUX_B2ECLK_ROOT.ECLK0_IN
IMUX_B3ECLK_ROOT.ECLK1_IN
OUT_F6ECLK_ROOT.PAD0_OUT
OUT_F7ECLK_ROOT.PAD1_OUT

Tile ECLK_TAP

Cells: 1

Bel ECLK_TAP

ecp2m ECLK_TAP bel ECLK_TAP
PinDirectionWires
ECLK0outputOUT_F6
ECLK1outputOUT_F7

Bel wires

ecp2m ECLK_TAP bel wires
WirePins
OUT_F6ECLK_TAP.ECLK0
OUT_F7ECLK_TAP.ECLK1

Tile HSDCLK_ROOT

Cells: 8

Bel HSDCLK_ROOT

ecp2m HSDCLK_ROOT bel HSDCLK_ROOT
PinDirectionWires
OUT_E0outputTCELL4:HSDCLK0
OUT_E1outputTCELL5:HSDCLK0
OUT_E2outputTCELL6:HSDCLK0
OUT_E3outputTCELL7:HSDCLK0
OUT_E4outputTCELL4:HSDCLK4
OUT_E5outputTCELL5:HSDCLK4
OUT_E6outputTCELL6:HSDCLK4
OUT_E7outputTCELL7:HSDCLK4
OUT_W0outputTCELL0:HSDCLK0
OUT_W1outputTCELL1:HSDCLK0
OUT_W2outputTCELL2:HSDCLK0
OUT_W3outputTCELL3:HSDCLK0
OUT_W4outputTCELL0:HSDCLK4
OUT_W5outputTCELL1:HSDCLK4
OUT_W6outputTCELL2:HSDCLK4
OUT_W7outputTCELL3:HSDCLK4

Bel HSDCLK_SPLITTER

Switchbox HSDCLK_SPLITTER

ecp2m HSDCLK_ROOT switchbox HSDCLK_SPLITTER
DestinationSourceKind
TCELL0_HSDCLK0TCELL4_HSDCLK0buffer
TCELL0_HSDCLK4TCELL4_HSDCLK4buffer
TCELL1_HSDCLK0TCELL5_HSDCLK0buffer
TCELL1_HSDCLK4TCELL5_HSDCLK4buffer
TCELL2_HSDCLK0TCELL6_HSDCLK0buffer
TCELL2_HSDCLK4TCELL6_HSDCLK4buffer
TCELL3_HSDCLK0TCELL7_HSDCLK0buffer
TCELL3_HSDCLK4TCELL7_HSDCLK4buffer
TCELL4_HSDCLK0TCELL0_HSDCLK0buffer
TCELL4_HSDCLK4TCELL0_HSDCLK4buffer
TCELL5_HSDCLK0TCELL1_HSDCLK0buffer
TCELL5_HSDCLK4TCELL1_HSDCLK4buffer
TCELL6_HSDCLK0TCELL2_HSDCLK0buffer
TCELL6_HSDCLK4TCELL2_HSDCLK4buffer
TCELL7_HSDCLK0TCELL3_HSDCLK0buffer
TCELL7_HSDCLK4TCELL3_HSDCLK4buffer

Bel wires

ecp2m HSDCLK_ROOT bel wires
WirePins
TCELL0:HSDCLK0HSDCLK_ROOT.OUT_W0
TCELL0:HSDCLK4HSDCLK_ROOT.OUT_W4
TCELL1:HSDCLK0HSDCLK_ROOT.OUT_W1
TCELL1:HSDCLK4HSDCLK_ROOT.OUT_W5
TCELL2:HSDCLK0HSDCLK_ROOT.OUT_W2
TCELL2:HSDCLK4HSDCLK_ROOT.OUT_W6
TCELL3:HSDCLK0HSDCLK_ROOT.OUT_W3
TCELL3:HSDCLK4HSDCLK_ROOT.OUT_W7
TCELL4:HSDCLK0HSDCLK_ROOT.OUT_E0
TCELL4:HSDCLK4HSDCLK_ROOT.OUT_E4
TCELL5:HSDCLK0HSDCLK_ROOT.OUT_E1
TCELL5:HSDCLK4HSDCLK_ROOT.OUT_E5
TCELL6:HSDCLK0HSDCLK_ROOT.OUT_E2
TCELL6:HSDCLK4HSDCLK_ROOT.OUT_E6
TCELL7:HSDCLK0HSDCLK_ROOT.OUT_E3
TCELL7:HSDCLK4HSDCLK_ROOT.OUT_E7

Tile HSDCLK_SPLITTER

Cells: 8

Bel HSDCLK_SPLITTER

Switchbox HSDCLK_SPLITTER

ecp2m HSDCLK_SPLITTER switchbox HSDCLK_SPLITTER
DestinationSourceKind
TCELL0_HSDCLK0TCELL4_HSDCLK0buffer
TCELL0_HSDCLK4TCELL4_HSDCLK4buffer
TCELL1_HSDCLK0TCELL5_HSDCLK0buffer
TCELL1_HSDCLK4TCELL5_HSDCLK4buffer
TCELL2_HSDCLK0TCELL6_HSDCLK0buffer
TCELL2_HSDCLK4TCELL6_HSDCLK4buffer
TCELL3_HSDCLK0TCELL7_HSDCLK0buffer
TCELL3_HSDCLK4TCELL7_HSDCLK4buffer
TCELL4_HSDCLK0TCELL0_HSDCLK0buffer
TCELL4_HSDCLK4TCELL0_HSDCLK4buffer
TCELL5_HSDCLK0TCELL1_HSDCLK0buffer
TCELL5_HSDCLK4TCELL1_HSDCLK4buffer
TCELL6_HSDCLK0TCELL2_HSDCLK0buffer
TCELL6_HSDCLK4TCELL2_HSDCLK4buffer
TCELL7_HSDCLK0TCELL3_HSDCLK0buffer
TCELL7_HSDCLK4TCELL3_HSDCLK4buffer

Tile SCLK0_SOURCE

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

ecp2m SCLK0_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK0fixed buffer
SCLK4VSDCLK1fixed buffer

Tile SCLK1_SOURCE

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

ecp2m SCLK1_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK1VSDCLK0fixed buffer
SCLK5VSDCLK1fixed buffer

Tile SCLK2_SOURCE

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

ecp2m SCLK2_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK2VSDCLK0fixed buffer
SCLK6VSDCLK1fixed buffer

Tile SCLK3_SOURCE

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

ecp2m SCLK3_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK3VSDCLK0fixed buffer
SCLK7VSDCLK1fixed buffer