1. Project Combine
    ❱
    1. General terminology
    2. General database structure
    3. Bitstream database
    4. Speed data
    5. FPGA grids and interconnect
  4. SiliconBlue FPGAs
  5. iCE65 and iCE40
    ❱
    1. Device geometry
    2. General interconnect
    3. Global interconnect
    4. Logic block
    5. Input / Output
      ❱
      1. I/O Interface
      2. I/O Buffers
    7. Block RAM
    8. DSP
    9. SPRAM
    10. Phase-Locked Loop
    11. SPI controller
    12. I2C controller
    13. I2C_FIFO controller
    14. I2C glitch filter
    15. Internal oscillators
    16. Led drivers
    17. Bitstream format
    18. Speed data
  8. Xilinx FPGAs
  9. XC2000
    ❱
    1. Device geometry
    2. Logic block
    3. Bidirectional buffers
  11. XC3000
    ❱
    1. Device geometry
    2. XC3000 tiles
      ❱
      1. Logic block
      2. Long line splitters
    4. XC3000A tiles
      ❱
      1. Logic block
      2. Long line splitters
  13. XC4000
    ❱
    1. Device geometry
    2. XC4000 tiles
      ❱
      1. Logic block
      2. Input / Output
      3. Corners
      4. Long line splitters
    4. XC4000A tiles
      ❱
      1. Logic block
      2. Input / Output
      3. Corners
      4. Long line splitters
    6. XC4000H tiles
      ❱
      1. Logic block
      2. Input / Output
      3. Corners
      4. Long line splitters
    8. XC4000E tiles
      ❱
      1. Logic block
      2. Input / Output
      3. Corners
      4. Long line splitters
    10. XC4000EX/XL tiles
      ❱
      1. Logic block
      2. Input / Output
      3. Corners
      4. Long line splitters
    12. XC4000XLA tiles
      ❱
      1. Logic block
      2. Input / Output
      3. Corners
      4. Long line splitters
    14. XC4000XV tiles
      ❱
      1. Logic block
      2. Input / Output
      3. Corners
      4. Long line splitters
    16. Spartan XL tiles
      ❱
      1. Logic block
      2. Input / Output
      3. Corners
      4. Long line splitters
  15. XC5200
    ❱
    1. Device geometry
    2. Logic block
    3. Input / Output
    4. Corners
    5. Long line splitters
  17. Virtex
    ❱
    1. Device geometry
    2. General interconnect
    3. Logic block
    4. Block RAM
    5. Clock interconnect
    6. Input / Output
      ❱
      1. I/O Interface
      2. I/O Buffers (Virtex)
      3. I/O Buffers (Virtex E)
    8. Delay-locked loop
    9. Hard PCI logic
    10. Corners
      ❱
      1. South-west
      2. North-west
      3. South-east
      4. North-east
    12. Configuration registers
  19. Virtex 2
    ❱
    1. Device geometry
    2. General interconnect
      ❱
      1. Interconnect tiles
      2. Terminator tiles
      3. PowerPC hole tiles
      4. Interface tiles
    4. Logic block
    5. Block RAM
    6. Clock interconnect
      ❱
      1. Global buffers
      2. Clock row distribution
      3. Clock column buffers
      4. DCM connections
    8. Input / Output
      ❱
      1. I/O Interface
      2. I/O Buffers (Virtex 2)
      3. I/O Buffers (Virtex 2 Pro)
    10. Digital Clock Managers
    11. PowerPC 405
    12. Multi-gigabit transceivers (Virtex 2 Pro)
    13. Multi-gigabit transceivers (Virtex 2 Pro X)
    14. Hard PCI logic
    15. Corners
      ❱
      1. South-west
      2. North-west
      3. South-east
      4. North-east
    17. Bitstream format
    18. Configuration registers
  21. Spartan 3
    ❱
    1. Device geometry
    2. General interconnect
      ❱
      1. Interconnect tiles
      2. Horizontal long line splitter tiles
      3. Vertical long line splitter tiles
      4. Interface tiles
    4. Logic block
    5. Block RAM
    6. DSP
    7. Clock interconnect
      ❱
      1. Primary global buffers
      2. Side global buffers
      3. Clock quadrant distribution
      4. Clock column buffers
    9. Input / Output
      ❱
      1. I/O Interface
      2. I/O Buffers (Spartan 3)
      3. I/O Buffers (Spartan 3E)
      4. I/O Buffers (Spartan 3A)
    11. Digital Clock Managers (Spartan 3)
    12. Digital Clock Managers (Spartan 3E, 3A)
    13. Hard PCI logic
    14. Corners
      ❱
      1. South-west
      2. North-west
      3. South-east
      4. North-east
    16. Configuration registers (Spartan 3, 3E)
    17. Configuration registers (Spartan 3A)
  23. FPGAcore
    ❱
    1. General interconnect
    2. Logic block
    3. Clock interconnect
      ❱
      1. Global buffers
      2. Clock quadrant distribution
      3. Clock column buffers
    5. Input / Output
    6. Corners
      ❱
      1. South-west
      2. North-west
      3. South-east
      4. North-east
    8. Configuration registers
  25. Spartan 6
    ❱
    1. Device geometry
    2. General interconnect
      ❱
      1. Interconnect tiles
      2. Interface tiles
    4. Logic block
    5. Block RAM
    6. DSP
    7. Clock interconnect
      ❱
      1. I/O clock buffers
      2. Global buffers
      3. Clock row buffers
      4. Clock column buffers
      5. Clock spine buffers
    9. Input / Output
    10. Hard PCI logic
    11. Memory Controller Block
    12. PCI Express
    13. GTP transceivers
    14. Digital Clock Managers
    15. Phase-Locked Loops
    16. Corners
      ❱
      1. South-west
      2. North-west
      3. South-east
      4. North-east
    18. Configuration registers
  27. Virtex 4
    ❱
    1. Device geometry
    2. General interconnect
    3. Logic block
    4. Block RAM
    5. DSP
    6. Clock interconnect
      ❱
      1. Clock row buffers
      2. Clock column buffers
      3. Clock I/O and DCM buffers
      4. Clock MGT buffers
      5. Clock spine multiplexers
    8. Input / Output
    9. Configuration center
    10. Digital Clock Manager
    11. Clock Companion Module
    12. System monitor
    13. PowerPC 405 and Ethernet MAC
    14. Multi-gigabit transceivers
    15. Configuration registers
  29. Virtex 5
    ❱
    1. Device geometry
    2. General interconnect
    3. Logic block
    4. Block RAM
    5. DSP
    6. Clock interconnect
      ❱
      1. Clock row buffers
      2. Clock column buffers
      3. Clock I/O and CMT buffers
      4. Clock MGT buffers
      5. Clock spine multiplexers
    8. Input / Output
    9. Configuration center
    10. Clock Management Tile
    11. PowerPC 440
    12. Ethernet MAC
    13. PCI Express
    14. GTP transceivers
    15. GTX transceivers
    16. Configuration registers
  31. Virtex 6
    ❱
    1. Device geometry
    2. General interconnect
    3. Logic block
    4. Block RAM
    5. DSP
    6. Clock interconnect
      ❱
      1. Global buffers
      2. Clock column buffers
      3. PMVIOB
    8. Input / Output
    9. Configuration center
    10. Clock Management Tile
    11. Ethernet MAC
    12. PCI Express
    13. GTX transceivers
    14. GTH transceivers
    15. Configuration registers
  33. Virtex 7
    ❱
    1. Device geometry
    2. General interconnect
    3. Logic block
    4. Block RAM
    5. DSP
    6. Clock interconnect
      ❱
      1. Global buffers
      2. Clock row buffers
      3. Clock column buffers
      4. Clock spine buffers
    8. Input / Output
    9. Configuration center
    10. Clock Management Tile
    11. PCI Express Gen 2
    12. PCI Express Gen 3
    13. GTP transceivers
    14. GTX transceivers
    15. GTH transceivers
    16. GTZ transceivers
    17. Configuration registers
  35. Ultrascale
  36. Ultrascale+
  37. Versal
  39. Xilinx CPLDs
  40. XC9500
    ❱
    1. Device structure
    2. Bitstream (XC9500)
    3. Bitstream (XC9500XL)
    4. Database
    5. JTAG
    6. Devices
      ❱
      1. XC9536
      2. XC9572
      3. XC95108
      4. XC95144
      5. XC95216
      6. XC95288
      7. XC9536XL, XA9536XL
      8. XC9572XL, XA9572XL
      9. XC95144XL, XA95144XL
      10. XC95288XL
      11. XC9536XV
      12. XC9572XV
      13. XC95144XV
      14. XC95288XV
  42. XPLA3
    ❱
    1. Device structure
    2. Bitstream
    3. Database
    4. JTAG
    5. Devices
      ❱
      1. XCR3032XL
      2. XCR3064XL
      3. XCR3128XL
      4. XCR3256XL
      5. XCR3384XL
      6. XCR3512XL
  44. Coolrunner II
    ❱
    1. Device structure
    2. Bitstream
    3. Database
    4. JTAG
    5. Devices
      ❱
      1. XC2C32
      2. XC2C32A, XA2C32A
      3. XC2C64
      4. XC2C64A, XA2C64A
      5. XC2C128, XA2C128
      6. XC2C256, XA2C256
      7. XC2C384, XA2C384
      8. XC2C512
  47. Programmers
  48. Digilent Adept
    ❱
    1. DMGT (board management)
    2. DJTG (JTAG controller)
    3. DPIO (GPIO)
    4. DEPP (EPP parallel port)
    5. DSTM (FX2 stream protocol)
    6. DSPI (SPI controller)
    7. DTWI (I2C controller)
    8. DACI (UART)
    9. Device list