Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Logic block

The CLB is identical to Spartan 3.

Bitstream

The data for a CLB is located in the same bitstream tile as the associated INT.CLB tile.

Tile CLB

Cells: 1 IRIs: 0

Bel SLICE0

fpgacore CLB bel SLICE0
PinDirectionWires
BXinputIMUX.FAN.BX0
BYinputIMUX.FAN.BY0
CEinputIMUX.CE0
CLKinputIMUX.CLK0
F1inputIMUX.DATA0
F2inputIMUX.DATA4
F3inputIMUX.DATA8
F4inputIMUX.DATA12
G1inputIMUX.DATA16
G2inputIMUX.DATA20
G3inputIMUX.DATA24
G4inputIMUX.DATA28
SRinputIMUX.SR0
XoutputOUT.FAN0
XBoutputOUT.SEC0
XQoutputOUT.SEC8
YoutputOUT.FAN4
YBoutputOUT.SEC4
YQoutputOUT.SEC12

Bel SLICE1

fpgacore CLB bel SLICE1
PinDirectionWires
BXinputIMUX.FAN.BX1
BYinputIMUX.FAN.BY1
CEinputIMUX.CE1
CLKinputIMUX.CLK1
F1inputIMUX.DATA1
F2inputIMUX.DATA5
F3inputIMUX.DATA9
F4inputIMUX.DATA13
G1inputIMUX.DATA17
G2inputIMUX.DATA21
G3inputIMUX.DATA25
G4inputIMUX.DATA29
SRinputIMUX.SR1
XoutputOUT.FAN1
XBoutputOUT.SEC1
XQoutputOUT.SEC9
YoutputOUT.FAN5
YBoutputOUT.SEC5
YQoutputOUT.SEC13

Bel SLICE2

fpgacore CLB bel SLICE2
PinDirectionWires
BXinputIMUX.FAN.BX2
BYinputIMUX.FAN.BY2
CEinputIMUX.CE2
CLKinputIMUX.CLK2
F1inputIMUX.DATA2
F2inputIMUX.DATA6
F3inputIMUX.DATA10
F4inputIMUX.DATA14
G1inputIMUX.DATA18
G2inputIMUX.DATA22
G3inputIMUX.DATA26
G4inputIMUX.DATA30
SRinputIMUX.SR2
XoutputOUT.FAN2
XBoutputOUT.SEC2
XQoutputOUT.SEC10
YoutputOUT.FAN6
YBoutputOUT.SEC6
YQoutputOUT.SEC14

Bel SLICE3

fpgacore CLB bel SLICE3
PinDirectionWires
BXinputIMUX.FAN.BX3
BYinputIMUX.FAN.BY3
CEinputIMUX.CE3
CLKinputIMUX.CLK3
F1inputIMUX.DATA3
F2inputIMUX.DATA7
F3inputIMUX.DATA11
F4inputIMUX.DATA15
G1inputIMUX.DATA19
G2inputIMUX.DATA23
G3inputIMUX.DATA27
G4inputIMUX.DATA31
SRinputIMUX.SR3
XoutputOUT.FAN3
XBoutputOUT.SEC3
XQoutputOUT.SEC11
YoutputOUT.FAN7
YBoutputOUT.SEC7
YQoutputOUT.SEC15

Bel wires

fpgacore CLB bel wires
WirePins
IMUX.SR0SLICE0.SR
IMUX.SR1SLICE1.SR
IMUX.SR2SLICE2.SR
IMUX.SR3SLICE3.SR
IMUX.CLK0SLICE0.CLK
IMUX.CLK1SLICE1.CLK
IMUX.CLK2SLICE2.CLK
IMUX.CLK3SLICE3.CLK
IMUX.CE0SLICE0.CE
IMUX.CE1SLICE1.CE
IMUX.CE2SLICE2.CE
IMUX.CE3SLICE3.CE
IMUX.FAN.BX0SLICE0.BX
IMUX.FAN.BX1SLICE1.BX
IMUX.FAN.BX2SLICE2.BX
IMUX.FAN.BX3SLICE3.BX
IMUX.FAN.BY0SLICE0.BY
IMUX.FAN.BY1SLICE1.BY
IMUX.FAN.BY2SLICE2.BY
IMUX.FAN.BY3SLICE3.BY
IMUX.DATA0SLICE0.F1
IMUX.DATA1SLICE1.F1
IMUX.DATA2SLICE2.F1
IMUX.DATA3SLICE3.F1
IMUX.DATA4SLICE0.F2
IMUX.DATA5SLICE1.F2
IMUX.DATA6SLICE2.F2
IMUX.DATA7SLICE3.F2
IMUX.DATA8SLICE0.F3
IMUX.DATA9SLICE1.F3
IMUX.DATA10SLICE2.F3
IMUX.DATA11SLICE3.F3
IMUX.DATA12SLICE0.F4
IMUX.DATA13SLICE1.F4
IMUX.DATA14SLICE2.F4
IMUX.DATA15SLICE3.F4
IMUX.DATA16SLICE0.G1
IMUX.DATA17SLICE1.G1
IMUX.DATA18SLICE2.G1
IMUX.DATA19SLICE3.G1
IMUX.DATA20SLICE0.G2
IMUX.DATA21SLICE1.G2
IMUX.DATA22SLICE2.G2
IMUX.DATA23SLICE3.G2
IMUX.DATA24SLICE0.G3
IMUX.DATA25SLICE1.G3
IMUX.DATA26SLICE2.G3
IMUX.DATA27SLICE3.G3
IMUX.DATA28SLICE0.G4
IMUX.DATA29SLICE1.G4
IMUX.DATA30SLICE2.G4
IMUX.DATA31SLICE3.G4
OUT.FAN0SLICE0.X
OUT.FAN1SLICE1.X
OUT.FAN2SLICE2.X
OUT.FAN3SLICE3.X
OUT.FAN4SLICE0.Y
OUT.FAN5SLICE1.Y
OUT.FAN6SLICE2.Y
OUT.FAN7SLICE3.Y
OUT.SEC0SLICE0.XB
OUT.SEC1SLICE1.XB
OUT.SEC2SLICE2.XB
OUT.SEC3SLICE3.XB
OUT.SEC4SLICE0.YB
OUT.SEC5SLICE1.YB
OUT.SEC6SLICE2.YB
OUT.SEC7SLICE3.YB
OUT.SEC8SLICE0.XQ
OUT.SEC9SLICE1.XQ
OUT.SEC10SLICE2.XQ
OUT.SEC11SLICE3.XQ
OUT.SEC12SLICE0.YQ
OUT.SEC13SLICE1.YQ
OUT.SEC14SLICE2.YQ
OUT.SEC15SLICE3.YQ

Bitstream

fpgacore CLB bittile 0
BitFrame
0 1 2 3 4 5
63 ~SLICE2:G[0] SLICE2:CY0G[1] SLICE3:CY0G[1] ~SLICE3:G[0] - -
62 ~SLICE2:G[1] SLICE2:CY0G[2] SLICE3:CY0G[2] ~SLICE3:G[1] - -
61 ~SLICE2:G[2] SLICE2:CY0G[0] SLICE3:CY0G[0] ~SLICE3:G[2] - -
60 ~SLICE2:G[3] SLICE2:GYMUX[1] SLICE3:GYMUX[1] ~SLICE3:G[3] - -
59 ~SLICE2:G[4] SLICE2:DYMUX[0] SLICE3:DYMUX[0] ~SLICE3:G[4] - -
58 ~SLICE2:G[5] SLICE2:DIG_MUX[0] - ~SLICE3:G[5] - -
57 ~SLICE2:G[6] SLICE2:GYMUX[0] SLICE3:GYMUX[0] ~SLICE3:G[6] - -
56 ~SLICE2:G[7] ~SLICE2:FFY_SRVAL ~SLICE3:FFY_SRVAL ~SLICE3:G[7] - -
55 ~SLICE2:G[8] SLICE2:FF_REV_ENABLE SLICE3:FF_REV_ENABLE ~SLICE3:G[8] - -
54 ~SLICE2:G[9] SLICE2:FF_LATCH SLICE3:FF_LATCH ~SLICE3:G[9] - -
53 ~SLICE2:G[10] ~SLICE2:FFY_INIT ~SLICE3:FFY_INIT ~SLICE3:G[10] - -
52 ~SLICE2:G[11] - - ~SLICE3:G[11] - -
51 ~SLICE2:G[12] SLICE2:FF_SR_SYNC SLICE3:FF_SR_SYNC ~SLICE3:G[12] - -
50 ~SLICE2:G[13] ~SLICE2:FFX_INIT ~SLICE3:FFX_INIT ~SLICE3:G[13] - -
49 ~SLICE2:G[14] ~SLICE2:FF_SR_ENABLE SLICE2:SLICEWE0USED ~SLICE3:G[14] - SLICE3:INV.BY
48 ~SLICE2:G[15] SLICE2:FXMUX[1] SLICE3:FXMUX[1] ~SLICE3:G[15] - -
47 ~SLICE2:F[0] SLICE2:DIF_MUX[0] - ~SLICE3:F[0] - -
46 ~SLICE2:F[1] ~SLICE2:FFX_SRVAL ~SLICE3:FFX_SRVAL ~SLICE3:F[1] - -
45 ~SLICE2:F[2] ~SLICE2:F_RAM - ~SLICE3:F[2] - -
44 ~SLICE2:F[3] ~SLICE2:G_RAM - ~SLICE3:F[3] - -
43 ~SLICE2:F[4] SLICE2:DXMUX[0] SLICE3:DXMUX[0] ~SLICE3:F[4] - -
42 ~SLICE2:F[5] SLICE2:CY0F[2] SLICE3:CY0F[2] ~SLICE3:F[5] - -
41 ~SLICE2:F[6] SLICE2:CY0F[0] SLICE3:CY0F[0] ~SLICE3:F[6] - -
40 ~SLICE2:F[7] ~SLICE2:F_SHIFT - ~SLICE3:F[7] - -
39 ~SLICE2:F[8] SLICE2:CY0F[1] SLICE3:CY0F[1] ~SLICE3:F[8] - -
38 ~SLICE2:F[9] ~SLICE2:G_SHIFT - ~SLICE3:F[9] - -
37 ~SLICE2:F[10] SLICE2:YBMUX[0] - ~SLICE3:F[10] - -
36 ~SLICE2:F[11] SLICE2:CYINIT[0] SLICE3:CYINIT[0] ~SLICE3:F[11] - SLICE3:INV.BX
35 ~SLICE2:F[12] SLICE2:CYSELG[0] SLICE3:CYSELG[0] ~SLICE3:F[12] - SLICE2:INV.BY
34 ~SLICE2:F[13] SLICE2:FXMUX[0] SLICE3:FXMUX[0] ~SLICE3:F[13] - -
33 ~SLICE2:F[14] SLICE2:XBMUX[0] - ~SLICE3:F[14] - -
32 ~SLICE2:F[15] SLICE2:CYSELF[0] SLICE3:CYSELF[0] ~SLICE3:F[15] - SLICE2:INV.BX
31 ~SLICE0:G[0] SLICE0:CY0G[1] SLICE1:CY0G[1] ~SLICE1:G[0] - SLICE1:INV.BY
30 ~SLICE0:G[1] SLICE0:CY0G[2] SLICE1:CY0G[2] ~SLICE1:G[1] - -
29 ~SLICE0:G[2] SLICE0:CY0G[0] SLICE1:CY0G[0] ~SLICE1:G[2] - -
28 ~SLICE0:G[3] SLICE0:GYMUX[1] SLICE1:GYMUX[1] ~SLICE1:G[3] - SLICE1:INV.BX
27 ~SLICE0:G[4] SLICE0:DYMUX[0] SLICE1:DYMUX[0] ~SLICE1:G[4] - SLICE0:INV.BY
26 ~SLICE0:G[5] SLICE0:DIG_MUX[0] - ~SLICE1:G[5] - -
25 ~SLICE0:G[6] SLICE0:GYMUX[0] SLICE1:GYMUX[0] ~SLICE1:G[6] - -
24 ~SLICE0:G[7] ~SLICE0:FFY_SRVAL ~SLICE1:FFY_SRVAL ~SLICE1:G[7] - -
23 ~SLICE0:G[8] SLICE0:FF_REV_ENABLE SLICE1:FF_REV_ENABLE ~SLICE1:G[8] - -
22 ~SLICE0:G[9] SLICE0:FF_LATCH SLICE1:FF_LATCH ~SLICE1:G[9] - -
21 ~SLICE0:G[10] ~SLICE0:FFY_INIT ~SLICE1:FFY_INIT ~SLICE1:G[10] - -
20 ~SLICE0:G[11] SLICE0:SLICEWE1USED - ~SLICE1:G[11] - -
19 ~SLICE0:G[12] SLICE0:FF_SR_SYNC SLICE1:FF_SR_SYNC ~SLICE1:G[12] - -
18 ~SLICE0:G[13] ~SLICE0:FFX_INIT ~SLICE1:FFX_INIT ~SLICE1:G[13] - -
17 ~SLICE0:G[14] ~SLICE0:FF_SR_ENABLE SLICE0:SLICEWE0USED ~SLICE1:G[14] - -
16 ~SLICE0:G[15] SLICE0:FXMUX[1] SLICE1:FXMUX[1] ~SLICE1:G[15] - -
15 ~SLICE0:F[0] SLICE0:DIF_MUX[0] - ~SLICE1:F[0] - -
14 ~SLICE0:F[1] ~SLICE0:FFX_SRVAL ~SLICE1:FFX_SRVAL ~SLICE1:F[1] - SLICE0:INV.BX
13 ~SLICE0:F[2] ~SLICE0:F_RAM - ~SLICE1:F[2] - -
12 ~SLICE0:F[3] ~SLICE0:G_RAM - ~SLICE1:F[3] - -
11 ~SLICE0:F[4] SLICE0:DXMUX[0] SLICE1:DXMUX[0] ~SLICE1:F[4] - -
10 ~SLICE0:F[5] SLICE0:CY0F[2] SLICE1:CY0F[2] ~SLICE1:F[5] - -
9 ~SLICE0:F[6] SLICE0:CY0F[0] SLICE1:CY0F[0] ~SLICE1:F[6] - -
8 ~SLICE0:F[7] ~SLICE0:F_SHIFT - ~SLICE1:F[7] - -
7 ~SLICE0:F[8] SLICE0:CY0F[1] SLICE1:CY0F[1] ~SLICE1:F[8] - -
6 ~SLICE0:F[9] ~SLICE0:G_SHIFT - ~SLICE1:F[9] - -
5 ~SLICE0:F[10] SLICE0:YBMUX[0] - ~SLICE1:F[10] - -
4 ~SLICE0:F[11] SLICE0:CYINIT[0] SLICE1:CYINIT[0] ~SLICE1:F[11] - -
3 ~SLICE0:F[12] SLICE0:CYSELG[0] SLICE1:CYSELG[0] ~SLICE1:F[12] - -
2 ~SLICE0:F[13] SLICE0:FXMUX[0] SLICE1:FXMUX[0] ~SLICE1:F[13] - -
1 ~SLICE0:F[14] SLICE0:XBMUX[0] - ~SLICE1:F[14] - -
0 ~SLICE0:F[15] SLICE0:CYSELF[0] SLICE1:CYSELF[0] ~SLICE1:F[15] - -
SLICE0:CY0F 0.1.10 0.1.7 0.1.9
SLICE1:CY0F 0.2.10 0.2.7 0.2.9
SLICE2:CY0F 0.1.42 0.1.39 0.1.41
SLICE3:CY0F 0.2.42 0.2.39 0.2.41
BX 0 0 0
F2 0 0 1
F1 0 1 1
PROD 1 0 0
1 1 0 1
0 1 1 1
SLICE0:CY0G 0.1.30 0.1.31 0.1.29
SLICE1:CY0G 0.2.30 0.2.31 0.2.29
SLICE2:CY0G 0.1.62 0.1.63 0.1.61
SLICE3:CY0G 0.2.62 0.2.63 0.2.61
BY 0 0 0
G2 0 0 1
G1 0 1 1
PROD 1 0 0
1 1 0 1
0 1 1 1
SLICE0:CYINIT 0.1.4
SLICE1:CYINIT 0.2.4
SLICE2:CYINIT 0.1.36
SLICE3:CYINIT 0.2.36
BX 0
CIN 1
SLICE0:CYSELF 0.1.0
SLICE1:CYSELF 0.2.0
SLICE2:CYSELF 0.1.32
SLICE3:CYSELF 0.2.32
1 0
F 1
SLICE0:CYSELG 0.1.3
SLICE1:CYSELG 0.2.3
SLICE2:CYSELG 0.1.35
SLICE3:CYSELG 0.2.35
1 0
G 1
SLICE0:DIF_MUX 0.1.15
SLICE2:DIF_MUX 0.1.47
ALT 0
BX 1
SLICE0:DIG_MUX 0.1.26
SLICE2:DIG_MUX 0.1.58
ALT 0
BY 1
SLICE0:DXMUX 0.1.11
SLICE1:DXMUX 0.2.11
SLICE2:DXMUX 0.1.43
SLICE3:DXMUX 0.2.43
BX 0
X 1
SLICE0:DYMUX 0.1.27
SLICE1:DYMUX 0.2.27
SLICE2:DYMUX 0.1.59
SLICE3:DYMUX 0.2.59
BY 0
Y 1
SLICE0:F 0.0.0 0.0.1 0.0.2 0.0.3 0.0.4 0.0.5 0.0.6 0.0.7 0.0.8 0.0.9 0.0.10 0.0.11 0.0.12 0.0.13 0.0.14 0.0.15
SLICE0:G 0.0.16 0.0.17 0.0.18 0.0.19 0.0.20 0.0.21 0.0.22 0.0.23 0.0.24 0.0.25 0.0.26 0.0.27 0.0.28 0.0.29 0.0.30 0.0.31
SLICE1:F 0.3.0 0.3.1 0.3.2 0.3.3 0.3.4 0.3.5 0.3.6 0.3.7 0.3.8 0.3.9 0.3.10 0.3.11 0.3.12 0.3.13 0.3.14 0.3.15
SLICE1:G 0.3.16 0.3.17 0.3.18 0.3.19 0.3.20 0.3.21 0.3.22 0.3.23 0.3.24 0.3.25 0.3.26 0.3.27 0.3.28 0.3.29 0.3.30 0.3.31
SLICE2:F 0.0.32 0.0.33 0.0.34 0.0.35 0.0.36 0.0.37 0.0.38 0.0.39 0.0.40 0.0.41 0.0.42 0.0.43 0.0.44 0.0.45 0.0.46 0.0.47
SLICE2:G 0.0.48 0.0.49 0.0.50 0.0.51 0.0.52 0.0.53 0.0.54 0.0.55 0.0.56 0.0.57 0.0.58 0.0.59 0.0.60 0.0.61 0.0.62 0.0.63
SLICE3:F 0.3.32 0.3.33 0.3.34 0.3.35 0.3.36 0.3.37 0.3.38 0.3.39 0.3.40 0.3.41 0.3.42 0.3.43 0.3.44 0.3.45 0.3.46 0.3.47
SLICE3:G 0.3.48 0.3.49 0.3.50 0.3.51 0.3.52 0.3.53 0.3.54 0.3.55 0.3.56 0.3.57 0.3.58 0.3.59 0.3.60 0.3.61 0.3.62 0.3.63
inverted ~[15] ~[14] ~[13] ~[12] ~[11] ~[10] ~[9] ~[8] ~[7] ~[6] ~[5] ~[4] ~[3] ~[2] ~[1] ~[0]
SLICE0:FFX_INIT 0.1.18
SLICE0:FFX_SRVAL 0.1.14
SLICE0:FFY_INIT 0.1.21
SLICE0:FFY_SRVAL 0.1.24
SLICE0:FF_SR_ENABLE 0.1.17
SLICE0:F_RAM 0.1.13
SLICE0:F_SHIFT 0.1.8
SLICE0:G_RAM 0.1.12
SLICE0:G_SHIFT 0.1.6
SLICE1:FFX_INIT 0.2.18
SLICE1:FFX_SRVAL 0.2.14
SLICE1:FFY_INIT 0.2.21
SLICE1:FFY_SRVAL 0.2.24
SLICE2:FFX_INIT 0.1.50
SLICE2:FFX_SRVAL 0.1.46
SLICE2:FFY_INIT 0.1.53
SLICE2:FFY_SRVAL 0.1.56
SLICE2:FF_SR_ENABLE 0.1.49
SLICE2:F_RAM 0.1.45
SLICE2:F_SHIFT 0.1.40
SLICE2:G_RAM 0.1.44
SLICE2:G_SHIFT 0.1.38
SLICE3:FFX_INIT 0.2.50
SLICE3:FFX_SRVAL 0.2.46
SLICE3:FFY_INIT 0.2.53
SLICE3:FFY_SRVAL 0.2.56
inverted ~[0]
SLICE0:FF_LATCH 0.1.22
SLICE0:FF_REV_ENABLE 0.1.23
SLICE0:FF_SR_SYNC 0.1.19
SLICE0:INV.BX 0.5.14
SLICE0:INV.BY 0.5.27
SLICE0:SLICEWE0USED 0.2.17
SLICE0:SLICEWE1USED 0.1.20
SLICE1:FF_LATCH 0.2.22
SLICE1:FF_REV_ENABLE 0.2.23
SLICE1:FF_SR_SYNC 0.2.19
SLICE1:INV.BX 0.5.28
SLICE1:INV.BY 0.5.31
SLICE2:FF_LATCH 0.1.54
SLICE2:FF_REV_ENABLE 0.1.55
SLICE2:FF_SR_SYNC 0.1.51
SLICE2:INV.BX 0.5.32
SLICE2:INV.BY 0.5.35
SLICE2:SLICEWE0USED 0.2.49
SLICE3:FF_LATCH 0.2.54
SLICE3:FF_REV_ENABLE 0.2.55
SLICE3:FF_SR_SYNC 0.2.51
SLICE3:INV.BX 0.5.36
SLICE3:INV.BY 0.5.49
non-inverted [0]
SLICE0:FXMUX 0.1.16 0.1.2
SLICE1:FXMUX 0.2.16 0.2.2
SLICE2:FXMUX 0.1.48 0.1.34
SLICE3:FXMUX 0.2.48 0.2.34
F 0 0
F5 0 1
FXOR 1 1
SLICE0:GYMUX 0.1.28 0.1.25
SLICE1:GYMUX 0.2.28 0.2.25
SLICE2:GYMUX 0.1.60 0.1.57
SLICE3:GYMUX 0.2.60 0.2.57
G 0 0
FX 0 1
GXOR 1 1
SLICE0:XBMUX 0.1.1
SLICE2:XBMUX 0.1.33
FCY 0
FMC15 1
SLICE0:YBMUX 0.1.5
SLICE2:YBMUX 0.1.37
GCY 0
GMC15 1

RESERVED_ANDOR

TODO: wtf is this even

RANDOR

This tile overlaps IOI.*.

Tile RANDOR

Cells: 1 IRIs: 0

Bel RANDOR

fpgacore RANDOR bel RANDOR
PinDirectionWires

Bitstream

RANDOR:MODE
AND
OR

RANDOR_INIT

This tile overlaps top-left interconnect tile.

Tile RANDOR_INIT

Cells: 0 IRIs: 0

Bitstream

fpgacore RANDOR_INIT bittile 0
BitFrame
0
63 RANDOR_INIT:MODE[0]
62 -
61 -
60 -
59 -
58 -
57 -
56 -
55 -
54 -
53 -
52 -
51 -
50 -
49 -
48 -
47 -
46 -
45 -
44 -
43 -
42 -
41 -
40 -
39 -
38 -
37 -
36 -
35 -
34 -
33 -
32 -
31 -
30 -
29 -
28 -
27 -
26 -
25 -
24 -
23 -
22 -
21 -
20 -
19 -
18 -
17 -
16 -
15 -
14 -
13 -
12 -
11 -
10 -
9 -
8 -
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 -
RANDOR_INIT:MODE 0.0.63
OR 0
AND 1