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Clock interconnect

Tile CLK_W

Cells: 2

Bel CLKDIV0

scm CLK_W bel CLKDIV0
PinDirectionWires
LSRinputCELL1.IMUX_LSR0

Bel CLKDIV1

scm CLK_W bel CLKDIV1
PinDirectionWires
LSRinputCELL1.IMUX_CE1

Bel CLKDIV2

scm CLK_W bel CLKDIV2
PinDirectionWires
LSRinputCELL0.IMUX_LSR0

Bel CLKDIV3

scm CLK_W bel CLKDIV3
PinDirectionWires
LSRinputCELL0.IMUX_CE1

Bel DCS0

scm CLK_W bel DCS0
PinDirectionWires
CLK0inputCELL1.IMUX_IO20
CLK1inputCELL1.IMUX_IO25
SELinputCELL1.IMUX_IO27

Bel DCS1

scm CLK_W bel DCS1
PinDirectionWires
CLK0inputCELL0.IMUX_IO20
CLK1inputCELL0.IMUX_IO25
SELinputCELL0.IMUX_IO27

Bel CLK_EDGE

scm CLK_W bel CLK_EDGE
PinDirectionWires

Bel ECLK_ROOT

scm CLK_W bel ECLK_ROOT
PinDirectionWires
CIB0inputCELL1.IMUX_CLK1
CIB1inputCELL0.IMUX_CLK1

Bel wires

scm CLK_W bel wires
WirePins
CELL0.IMUX_CLK1ECLK_ROOT.CIB1
CELL0.IMUX_LSR0CLKDIV2.LSR
CELL0.IMUX_CE1CLKDIV3.LSR
CELL0.IMUX_IO20DCS1.CLK0
CELL0.IMUX_IO25DCS1.CLK1
CELL0.IMUX_IO27DCS1.SEL
CELL1.IMUX_CLK1ECLK_ROOT.CIB0
CELL1.IMUX_LSR0CLKDIV0.LSR
CELL1.IMUX_CE1CLKDIV1.LSR
CELL1.IMUX_IO20DCS0.CLK0
CELL1.IMUX_IO25DCS0.CLK1
CELL1.IMUX_IO27DCS0.SEL

Tile CLK_E

Cells: 2

Bel CLKDIV0

scm CLK_E bel CLKDIV0
PinDirectionWires
LSRinputCELL1.IMUX_LSR3

Bel CLKDIV1

scm CLK_E bel CLKDIV1
PinDirectionWires
LSRinputCELL1.IMUX_CE2

Bel CLKDIV2

scm CLK_E bel CLKDIV2
PinDirectionWires
LSRinputCELL0.IMUX_LSR3

Bel CLKDIV3

scm CLK_E bel CLKDIV3
PinDirectionWires
LSRinputCELL0.IMUX_CE2

Bel DCS0

scm CLK_E bel DCS0
PinDirectionWires
CLK0inputCELL1.IMUX_IO20
CLK1inputCELL1.IMUX_IO25
SELinputCELL1.IMUX_IO27

Bel DCS1

scm CLK_E bel DCS1
PinDirectionWires
CLK0inputCELL0.IMUX_IO20
CLK1inputCELL0.IMUX_IO25
SELinputCELL0.IMUX_IO27

Bel CLK_EDGE

scm CLK_E bel CLK_EDGE
PinDirectionWires

Bel ECLK_ROOT

scm CLK_E bel ECLK_ROOT
PinDirectionWires
CIB0inputCELL1.IMUX_CLK2
CIB1inputCELL0.IMUX_CLK2

Bel wires

scm CLK_E bel wires
WirePins
CELL0.IMUX_CLK2ECLK_ROOT.CIB1
CELL0.IMUX_LSR3CLKDIV2.LSR
CELL0.IMUX_CE2CLKDIV3.LSR
CELL0.IMUX_IO20DCS1.CLK0
CELL0.IMUX_IO25DCS1.CLK1
CELL0.IMUX_IO27DCS1.SEL
CELL1.IMUX_CLK2ECLK_ROOT.CIB0
CELL1.IMUX_LSR3CLKDIV0.LSR
CELL1.IMUX_CE2CLKDIV1.LSR
CELL1.IMUX_IO20DCS0.CLK0
CELL1.IMUX_IO25DCS0.CLK1
CELL1.IMUX_IO27DCS0.SEL

Tile CLK_S

Cells: 2

Bel DCS0

scm CLK_S bel DCS0
PinDirectionWires
CLK0inputCELL0.IMUX_IO13
CLK1inputCELL0.IMUX_IO25
SELinputCELL0.IMUX_LSR3

Bel DCS1

scm CLK_S bel DCS1
PinDirectionWires
CLK0inputCELL1.IMUX_IO13
CLK1inputCELL1.IMUX_IO25
SELinputCELL1.IMUX_LSR3

Bel CLK_EDGE

scm CLK_S bel CLK_EDGE
PinDirectionWires

Bel wires

scm CLK_S bel wires
WirePins
CELL0.IMUX_LSR3DCS0.SEL
CELL0.IMUX_IO13DCS0.CLK0
CELL0.IMUX_IO25DCS0.CLK1
CELL1.IMUX_LSR3DCS1.SEL
CELL1.IMUX_IO13DCS1.CLK0
CELL1.IMUX_IO25DCS1.CLK1

Tile CLK_SW

Cells: 2

Bel CLKDIV0

scm CLK_SW bel CLKDIV0
PinDirectionWires
LSRinputCELL0.IMUX_LSR3

Bel CLKDIV1

scm CLK_SW bel CLKDIV1
PinDirectionWires
LSRinputCELL1.IMUX_LSR3

Bel CLKDIV2

scm CLK_SW bel CLKDIV2
PinDirectionWires
LSRinputCELL0.IMUX_CE2

Bel CLKDIV3

scm CLK_SW bel CLKDIV3
PinDirectionWires
LSRinputCELL1.IMUX_CE2

Bel ECLK_ROOT

scm CLK_SW bel ECLK_ROOT
PinDirectionWires
CIB0inputCELL0.IMUX_CLK2
CIB1inputCELL1.IMUX_CLK2

Bel wires

scm CLK_SW bel wires
WirePins
CELL0.IMUX_CLK2ECLK_ROOT.CIB0
CELL0.IMUX_LSR3CLKDIV0.LSR
CELL0.IMUX_CE2CLKDIV2.LSR
CELL1.IMUX_CLK2ECLK_ROOT.CIB1
CELL1.IMUX_LSR3CLKDIV1.LSR
CELL1.IMUX_CE2CLKDIV3.LSR

Tile CLK_SE

Cells: 2

Bel CLKDIV0

scm CLK_SE bel CLKDIV0
PinDirectionWires
LSRinputCELL1.IMUX_LSR3

Bel CLKDIV1

scm CLK_SE bel CLKDIV1
PinDirectionWires
LSRinputCELL0.IMUX_LSR3

Bel CLKDIV2

scm CLK_SE bel CLKDIV2
PinDirectionWires
LSRinputCELL1.IMUX_CE2

Bel CLKDIV3

scm CLK_SE bel CLKDIV3
PinDirectionWires
LSRinputCELL0.IMUX_CE2

Bel ECLK_ROOT

scm CLK_SE bel ECLK_ROOT
PinDirectionWires
CIB0inputCELL1.IMUX_CLK2
CIB1inputCELL0.IMUX_CLK2

Bel wires

scm CLK_SE bel wires
WirePins
CELL0.IMUX_CLK2ECLK_ROOT.CIB1
CELL0.IMUX_LSR3CLKDIV1.LSR
CELL0.IMUX_CE2CLKDIV3.LSR
CELL1.IMUX_CLK2ECLK_ROOT.CIB0
CELL1.IMUX_LSR3CLKDIV0.LSR
CELL1.IMUX_CE2CLKDIV2.LSR

Tile CLK_N

Cells: 2

Bel CLKDIV0

scm CLK_N bel CLKDIV0
PinDirectionWires
LSRinputCELL0.IMUX_LSR3

Bel CLKDIV1

scm CLK_N bel CLKDIV1
PinDirectionWires
LSRinputCELL1.IMUX_LSR3

Bel CLKDIV2

scm CLK_N bel CLKDIV2
PinDirectionWires
LSRinputCELL0.IMUX_CE2

Bel CLKDIV3

scm CLK_N bel CLKDIV3
PinDirectionWires
LSRinputCELL1.IMUX_CE2

Bel DCS0

scm CLK_N bel DCS0
PinDirectionWires
CLK0inputCELL0.IMUX_C1
CLK1inputCELL0.IMUX_B0
SELinputCELL1.IMUX_B0

Bel DCS1

scm CLK_N bel DCS1
PinDirectionWires
CLK0inputCELL0.IMUX_D4
CLK1inputCELL1.IMUX_C1
SELinputCELL1.IMUX_D4

Bel CLK_EDGE

scm CLK_N bel CLK_EDGE
PinDirectionWires

Bel ECLK_ROOT

scm CLK_N bel ECLK_ROOT
PinDirectionWires
CIB0inputCELL0.IMUX_CLK2
CIB1inputCELL1.IMUX_CLK2

Bel wires

scm CLK_N bel wires
WirePins
CELL0.IMUX_B0DCS0.CLK1
CELL0.IMUX_C1DCS0.CLK0
CELL0.IMUX_D4DCS1.CLK0
CELL0.IMUX_CLK2ECLK_ROOT.CIB0
CELL0.IMUX_LSR3CLKDIV0.LSR
CELL0.IMUX_CE2CLKDIV2.LSR
CELL1.IMUX_B0DCS0.SEL
CELL1.IMUX_C1DCS1.CLK1
CELL1.IMUX_D4DCS1.SEL
CELL1.IMUX_CLK2ECLK_ROOT.CIB1
CELL1.IMUX_LSR3CLKDIV1.LSR
CELL1.IMUX_CE2CLKDIV3.LSR

Tile CLK_ROOT

Cells: 4

Bel CLK_ROOT

scm CLK_ROOT bel CLK_ROOT
PinDirectionWires
IN_CIBLLQinputCELL0.IMUX_LSR2
IN_CIBULQinputCELL2.IMUX_LSR2
IN_CIBURQinputCELL3.IMUX_LSR0
PCLK0_NEinputCELL3.PCLK0
PCLK0_NWinputCELL2.PCLK0
PCLK0_SEinputCELL1.PCLK0
PCLK0_SWinputCELL0.PCLK0
PCLK10_NEinputCELL3.PCLK10
PCLK10_NWinputCELL2.PCLK10
PCLK10_SEinputCELL1.PCLK10
PCLK10_SWinputCELL0.PCLK10
PCLK11_NEinputCELL3.PCLK11
PCLK11_NWinputCELL2.PCLK11
PCLK11_SEinputCELL1.PCLK11
PCLK11_SWinputCELL0.PCLK11
PCLK1_NEinputCELL3.PCLK1
PCLK1_NWinputCELL2.PCLK1
PCLK1_SEinputCELL1.PCLK1
PCLK1_SWinputCELL0.PCLK1
PCLK2_NEinputCELL3.PCLK2
PCLK2_NWinputCELL2.PCLK2
PCLK2_SEinputCELL1.PCLK2
PCLK2_SWinputCELL0.PCLK2
PCLK3_NEinputCELL3.PCLK3
PCLK3_NWinputCELL2.PCLK3
PCLK3_SEinputCELL1.PCLK3
PCLK3_SWinputCELL0.PCLK3
PCLK4_NEinputCELL3.PCLK4
PCLK4_NWinputCELL2.PCLK4
PCLK4_SEinputCELL1.PCLK4
PCLK4_SWinputCELL0.PCLK4
PCLK5_NEinputCELL3.PCLK5
PCLK5_NWinputCELL2.PCLK5
PCLK5_SEinputCELL1.PCLK5
PCLK5_SWinputCELL0.PCLK5
PCLK6_NEinputCELL3.PCLK6
PCLK6_NWinputCELL2.PCLK6
PCLK6_SEinputCELL1.PCLK6
PCLK6_SWinputCELL0.PCLK6
PCLK7_NEinputCELL3.PCLK7
PCLK7_NWinputCELL2.PCLK7
PCLK7_SEinputCELL1.PCLK7
PCLK7_SWinputCELL0.PCLK7
PCLK8_NEinputCELL3.PCLK8
PCLK8_NWinputCELL2.PCLK8
PCLK8_SEinputCELL1.PCLK8
PCLK8_SWinputCELL0.PCLK8
PCLK9_NEinputCELL3.PCLK9
PCLK9_NWinputCELL2.PCLK9
PCLK9_SEinputCELL1.PCLK9
PCLK9_SWinputCELL0.PCLK9

Bel CLKTEST

scm CLK_ROOT bel CLKTEST
PinDirectionWires
CIBTESTB0inputCELL0.IMUX_LSR3
CIBTESTB1inputCELL0.IMUX_CLK2
CIBTESTB2inputCELL0.IMUX_CLK3
CIBTESTB3inputCELL1.IMUX_LSR0
CIBTESTB4inputCELL1.IMUX_LSR1
CIBTESTB5inputCELL1.IMUX_CLK0
CIBTESTT0inputCELL2.IMUX_LSR3
CIBTESTT1inputCELL2.IMUX_CLK2
CIBTESTT2inputCELL2.IMUX_CLK3
CIBTESTT3inputCELL3.IMUX_LSR1
CIBTESTT4inputCELL3.IMUX_CLK0
CIBTESTT5inputCELL3.IMUX_CLK1

Bel wires

scm CLK_ROOT bel wires
WirePins
CELL0.PCLK0CLK_ROOT.PCLK0_SW
CELL0.PCLK1CLK_ROOT.PCLK1_SW
CELL0.PCLK2CLK_ROOT.PCLK2_SW
CELL0.PCLK3CLK_ROOT.PCLK3_SW
CELL0.PCLK4CLK_ROOT.PCLK4_SW
CELL0.PCLK5CLK_ROOT.PCLK5_SW
CELL0.PCLK6CLK_ROOT.PCLK6_SW
CELL0.PCLK7CLK_ROOT.PCLK7_SW
CELL0.PCLK8CLK_ROOT.PCLK8_SW
CELL0.PCLK9CLK_ROOT.PCLK9_SW
CELL0.PCLK10CLK_ROOT.PCLK10_SW
CELL0.PCLK11CLK_ROOT.PCLK11_SW
CELL0.IMUX_CLK2CLKTEST.CIBTESTB1
CELL0.IMUX_CLK3CLKTEST.CIBTESTB2
CELL0.IMUX_LSR2CLK_ROOT.IN_CIBLLQ
CELL0.IMUX_LSR3CLKTEST.CIBTESTB0
CELL1.PCLK0CLK_ROOT.PCLK0_SE
CELL1.PCLK1CLK_ROOT.PCLK1_SE
CELL1.PCLK2CLK_ROOT.PCLK2_SE
CELL1.PCLK3CLK_ROOT.PCLK3_SE
CELL1.PCLK4CLK_ROOT.PCLK4_SE
CELL1.PCLK5CLK_ROOT.PCLK5_SE
CELL1.PCLK6CLK_ROOT.PCLK6_SE
CELL1.PCLK7CLK_ROOT.PCLK7_SE
CELL1.PCLK8CLK_ROOT.PCLK8_SE
CELL1.PCLK9CLK_ROOT.PCLK9_SE
CELL1.PCLK10CLK_ROOT.PCLK10_SE
CELL1.PCLK11CLK_ROOT.PCLK11_SE
CELL1.IMUX_CLK0CLKTEST.CIBTESTB5
CELL1.IMUX_LSR0CLKTEST.CIBTESTB3
CELL1.IMUX_LSR1CLKTEST.CIBTESTB4
CELL2.PCLK0CLK_ROOT.PCLK0_NW
CELL2.PCLK1CLK_ROOT.PCLK1_NW
CELL2.PCLK2CLK_ROOT.PCLK2_NW
CELL2.PCLK3CLK_ROOT.PCLK3_NW
CELL2.PCLK4CLK_ROOT.PCLK4_NW
CELL2.PCLK5CLK_ROOT.PCLK5_NW
CELL2.PCLK6CLK_ROOT.PCLK6_NW
CELL2.PCLK7CLK_ROOT.PCLK7_NW
CELL2.PCLK8CLK_ROOT.PCLK8_NW
CELL2.PCLK9CLK_ROOT.PCLK9_NW
CELL2.PCLK10CLK_ROOT.PCLK10_NW
CELL2.PCLK11CLK_ROOT.PCLK11_NW
CELL2.IMUX_CLK2CLKTEST.CIBTESTT1
CELL2.IMUX_CLK3CLKTEST.CIBTESTT2
CELL2.IMUX_LSR2CLK_ROOT.IN_CIBULQ
CELL2.IMUX_LSR3CLKTEST.CIBTESTT0
CELL3.PCLK0CLK_ROOT.PCLK0_NE
CELL3.PCLK1CLK_ROOT.PCLK1_NE
CELL3.PCLK2CLK_ROOT.PCLK2_NE
CELL3.PCLK3CLK_ROOT.PCLK3_NE
CELL3.PCLK4CLK_ROOT.PCLK4_NE
CELL3.PCLK5CLK_ROOT.PCLK5_NE
CELL3.PCLK6CLK_ROOT.PCLK6_NE
CELL3.PCLK7CLK_ROOT.PCLK7_NE
CELL3.PCLK8CLK_ROOT.PCLK8_NE
CELL3.PCLK9CLK_ROOT.PCLK9_NE
CELL3.PCLK10CLK_ROOT.PCLK10_NE
CELL3.PCLK11CLK_ROOT.PCLK11_NE
CELL3.IMUX_CLK0CLKTEST.CIBTESTT4
CELL3.IMUX_CLK1CLKTEST.CIBTESTT5
CELL3.IMUX_LSR0CLK_ROOT.IN_CIBURQ
CELL3.IMUX_LSR1CLKTEST.CIBTESTT3