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Clock interconnect

Tile CLK_W

Cells: 2

Bel CLKDIV0

scm CLK_W bel CLKDIV0
PinDirectionWires
LSRinputTCELL1:IMUX_LSR0

Bel CLKDIV1

scm CLK_W bel CLKDIV1
PinDirectionWires
LSRinputTCELL1:IMUX_CE1

Bel CLKDIV2

scm CLK_W bel CLKDIV2
PinDirectionWires
LSRinputTCELL0:IMUX_LSR0

Bel CLKDIV3

scm CLK_W bel CLKDIV3
PinDirectionWires
LSRinputTCELL0:IMUX_CE1

Bel DCS0

scm CLK_W bel DCS0
PinDirectionWires
CLK0inputTCELL1:IMUX_IO20
CLK1inputTCELL1:IMUX_IO25
SELinputTCELL1:IMUX_IO27

Bel DCS1

scm CLK_W bel DCS1
PinDirectionWires
CLK0inputTCELL0:IMUX_IO20
CLK1inputTCELL0:IMUX_IO25
SELinputTCELL0:IMUX_IO27

Bel CLK_EDGE

scm CLK_W bel CLK_EDGE
PinDirectionWires

Bel ECLK_ROOT

scm CLK_W bel ECLK_ROOT
PinDirectionWires
CIB0inputTCELL1:IMUX_CLK1
CIB1inputTCELL0:IMUX_CLK1

Bel wires

scm CLK_W bel wires
WirePins
TCELL0:IMUX_CLK1ECLK_ROOT.CIB1
TCELL0:IMUX_LSR0CLKDIV2.LSR
TCELL0:IMUX_CE1CLKDIV3.LSR
TCELL0:IMUX_IO20DCS1.CLK0
TCELL0:IMUX_IO25DCS1.CLK1
TCELL0:IMUX_IO27DCS1.SEL
TCELL1:IMUX_CLK1ECLK_ROOT.CIB0
TCELL1:IMUX_LSR0CLKDIV0.LSR
TCELL1:IMUX_CE1CLKDIV1.LSR
TCELL1:IMUX_IO20DCS0.CLK0
TCELL1:IMUX_IO25DCS0.CLK1
TCELL1:IMUX_IO27DCS0.SEL

Tile CLK_E

Cells: 2

Bel CLKDIV0

scm CLK_E bel CLKDIV0
PinDirectionWires
LSRinputTCELL1:IMUX_LSR3

Bel CLKDIV1

scm CLK_E bel CLKDIV1
PinDirectionWires
LSRinputTCELL1:IMUX_CE2

Bel CLKDIV2

scm CLK_E bel CLKDIV2
PinDirectionWires
LSRinputTCELL0:IMUX_LSR3

Bel CLKDIV3

scm CLK_E bel CLKDIV3
PinDirectionWires
LSRinputTCELL0:IMUX_CE2

Bel DCS0

scm CLK_E bel DCS0
PinDirectionWires
CLK0inputTCELL1:IMUX_IO20
CLK1inputTCELL1:IMUX_IO25
SELinputTCELL1:IMUX_IO27

Bel DCS1

scm CLK_E bel DCS1
PinDirectionWires
CLK0inputTCELL0:IMUX_IO20
CLK1inputTCELL0:IMUX_IO25
SELinputTCELL0:IMUX_IO27

Bel CLK_EDGE

scm CLK_E bel CLK_EDGE
PinDirectionWires

Bel ECLK_ROOT

scm CLK_E bel ECLK_ROOT
PinDirectionWires
CIB0inputTCELL1:IMUX_CLK2
CIB1inputTCELL0:IMUX_CLK2

Bel wires

scm CLK_E bel wires
WirePins
TCELL0:IMUX_CLK2ECLK_ROOT.CIB1
TCELL0:IMUX_LSR3CLKDIV2.LSR
TCELL0:IMUX_CE2CLKDIV3.LSR
TCELL0:IMUX_IO20DCS1.CLK0
TCELL0:IMUX_IO25DCS1.CLK1
TCELL0:IMUX_IO27DCS1.SEL
TCELL1:IMUX_CLK2ECLK_ROOT.CIB0
TCELL1:IMUX_LSR3CLKDIV0.LSR
TCELL1:IMUX_CE2CLKDIV1.LSR
TCELL1:IMUX_IO20DCS0.CLK0
TCELL1:IMUX_IO25DCS0.CLK1
TCELL1:IMUX_IO27DCS0.SEL

Tile CLK_S

Cells: 2

Bel DCS0

scm CLK_S bel DCS0
PinDirectionWires
CLK0inputTCELL0:IMUX_IO13
CLK1inputTCELL0:IMUX_IO25
SELinputTCELL0:IMUX_LSR3

Bel DCS1

scm CLK_S bel DCS1
PinDirectionWires
CLK0inputTCELL1:IMUX_IO13
CLK1inputTCELL1:IMUX_IO25
SELinputTCELL1:IMUX_LSR3

Bel CLK_EDGE

scm CLK_S bel CLK_EDGE
PinDirectionWires

Bel wires

scm CLK_S bel wires
WirePins
TCELL0:IMUX_LSR3DCS0.SEL
TCELL0:IMUX_IO13DCS0.CLK0
TCELL0:IMUX_IO25DCS0.CLK1
TCELL1:IMUX_LSR3DCS1.SEL
TCELL1:IMUX_IO13DCS1.CLK0
TCELL1:IMUX_IO25DCS1.CLK1

Tile CLK_SW

Cells: 2

Bel CLKDIV0

scm CLK_SW bel CLKDIV0
PinDirectionWires
LSRinputTCELL0:IMUX_LSR3

Bel CLKDIV1

scm CLK_SW bel CLKDIV1
PinDirectionWires
LSRinputTCELL1:IMUX_LSR3

Bel CLKDIV2

scm CLK_SW bel CLKDIV2
PinDirectionWires
LSRinputTCELL0:IMUX_CE2

Bel CLKDIV3

scm CLK_SW bel CLKDIV3
PinDirectionWires
LSRinputTCELL1:IMUX_CE2

Bel ECLK_ROOT

scm CLK_SW bel ECLK_ROOT
PinDirectionWires
CIB0inputTCELL0:IMUX_CLK2
CIB1inputTCELL1:IMUX_CLK2

Bel wires

scm CLK_SW bel wires
WirePins
TCELL0:IMUX_CLK2ECLK_ROOT.CIB0
TCELL0:IMUX_LSR3CLKDIV0.LSR
TCELL0:IMUX_CE2CLKDIV2.LSR
TCELL1:IMUX_CLK2ECLK_ROOT.CIB1
TCELL1:IMUX_LSR3CLKDIV1.LSR
TCELL1:IMUX_CE2CLKDIV3.LSR

Tile CLK_SE

Cells: 2

Bel CLKDIV0

scm CLK_SE bel CLKDIV0
PinDirectionWires
LSRinputTCELL1:IMUX_LSR3

Bel CLKDIV1

scm CLK_SE bel CLKDIV1
PinDirectionWires
LSRinputTCELL0:IMUX_LSR3

Bel CLKDIV2

scm CLK_SE bel CLKDIV2
PinDirectionWires
LSRinputTCELL1:IMUX_CE2

Bel CLKDIV3

scm CLK_SE bel CLKDIV3
PinDirectionWires
LSRinputTCELL0:IMUX_CE2

Bel ECLK_ROOT

scm CLK_SE bel ECLK_ROOT
PinDirectionWires
CIB0inputTCELL1:IMUX_CLK2
CIB1inputTCELL0:IMUX_CLK2

Bel wires

scm CLK_SE bel wires
WirePins
TCELL0:IMUX_CLK2ECLK_ROOT.CIB1
TCELL0:IMUX_LSR3CLKDIV1.LSR
TCELL0:IMUX_CE2CLKDIV3.LSR
TCELL1:IMUX_CLK2ECLK_ROOT.CIB0
TCELL1:IMUX_LSR3CLKDIV0.LSR
TCELL1:IMUX_CE2CLKDIV2.LSR

Tile CLK_N

Cells: 2

Bel CLKDIV0

scm CLK_N bel CLKDIV0
PinDirectionWires
LSRinputTCELL0:IMUX_LSR3

Bel CLKDIV1

scm CLK_N bel CLKDIV1
PinDirectionWires
LSRinputTCELL1:IMUX_LSR3

Bel CLKDIV2

scm CLK_N bel CLKDIV2
PinDirectionWires
LSRinputTCELL0:IMUX_CE2

Bel CLKDIV3

scm CLK_N bel CLKDIV3
PinDirectionWires
LSRinputTCELL1:IMUX_CE2

Bel DCS0

scm CLK_N bel DCS0
PinDirectionWires
CLK0inputTCELL0:IMUX_C1
CLK1inputTCELL0:IMUX_B0
SELinputTCELL1:IMUX_B0

Bel DCS1

scm CLK_N bel DCS1
PinDirectionWires
CLK0inputTCELL0:IMUX_D4
CLK1inputTCELL1:IMUX_C1
SELinputTCELL1:IMUX_D4

Bel CLK_EDGE

scm CLK_N bel CLK_EDGE
PinDirectionWires

Bel ECLK_ROOT

scm CLK_N bel ECLK_ROOT
PinDirectionWires
CIB0inputTCELL0:IMUX_CLK2
CIB1inputTCELL1:IMUX_CLK2

Bel wires

scm CLK_N bel wires
WirePins
TCELL0:IMUX_B0DCS0.CLK1
TCELL0:IMUX_C1DCS0.CLK0
TCELL0:IMUX_D4DCS1.CLK0
TCELL0:IMUX_CLK2ECLK_ROOT.CIB0
TCELL0:IMUX_LSR3CLKDIV0.LSR
TCELL0:IMUX_CE2CLKDIV2.LSR
TCELL1:IMUX_B0DCS0.SEL
TCELL1:IMUX_C1DCS1.CLK1
TCELL1:IMUX_D4DCS1.SEL
TCELL1:IMUX_CLK2ECLK_ROOT.CIB1
TCELL1:IMUX_LSR3CLKDIV1.LSR
TCELL1:IMUX_CE2CLKDIV3.LSR

Tile CLK_ROOT

Cells: 4

Bel CLK_ROOT

scm CLK_ROOT bel CLK_ROOT
PinDirectionWires
IN_CIBLLQinputTCELL0:IMUX_LSR2
IN_CIBULQinputTCELL2:IMUX_LSR2
IN_CIBURQinputTCELL3:IMUX_LSR0
PCLK0_NEinputTCELL3:PCLK0
PCLK0_NWinputTCELL2:PCLK0
PCLK0_SEinputTCELL1:PCLK0
PCLK0_SWinputTCELL0:PCLK0
PCLK10_NEinputTCELL3:PCLK10
PCLK10_NWinputTCELL2:PCLK10
PCLK10_SEinputTCELL1:PCLK10
PCLK10_SWinputTCELL0:PCLK10
PCLK11_NEinputTCELL3:PCLK11
PCLK11_NWinputTCELL2:PCLK11
PCLK11_SEinputTCELL1:PCLK11
PCLK11_SWinputTCELL0:PCLK11
PCLK1_NEinputTCELL3:PCLK1
PCLK1_NWinputTCELL2:PCLK1
PCLK1_SEinputTCELL1:PCLK1
PCLK1_SWinputTCELL0:PCLK1
PCLK2_NEinputTCELL3:PCLK2
PCLK2_NWinputTCELL2:PCLK2
PCLK2_SEinputTCELL1:PCLK2
PCLK2_SWinputTCELL0:PCLK2
PCLK3_NEinputTCELL3:PCLK3
PCLK3_NWinputTCELL2:PCLK3
PCLK3_SEinputTCELL1:PCLK3
PCLK3_SWinputTCELL0:PCLK3
PCLK4_NEinputTCELL3:PCLK4
PCLK4_NWinputTCELL2:PCLK4
PCLK4_SEinputTCELL1:PCLK4
PCLK4_SWinputTCELL0:PCLK4
PCLK5_NEinputTCELL3:PCLK5
PCLK5_NWinputTCELL2:PCLK5
PCLK5_SEinputTCELL1:PCLK5
PCLK5_SWinputTCELL0:PCLK5
PCLK6_NEinputTCELL3:PCLK6
PCLK6_NWinputTCELL2:PCLK6
PCLK6_SEinputTCELL1:PCLK6
PCLK6_SWinputTCELL0:PCLK6
PCLK7_NEinputTCELL3:PCLK7
PCLK7_NWinputTCELL2:PCLK7
PCLK7_SEinputTCELL1:PCLK7
PCLK7_SWinputTCELL0:PCLK7
PCLK8_NEinputTCELL3:PCLK8
PCLK8_NWinputTCELL2:PCLK8
PCLK8_SEinputTCELL1:PCLK8
PCLK8_SWinputTCELL0:PCLK8
PCLK9_NEinputTCELL3:PCLK9
PCLK9_NWinputTCELL2:PCLK9
PCLK9_SEinputTCELL1:PCLK9
PCLK9_SWinputTCELL0:PCLK9

Bel CLKTEST

scm CLK_ROOT bel CLKTEST
PinDirectionWires
CIBTESTB0inputTCELL0:IMUX_LSR3
CIBTESTB1inputTCELL0:IMUX_CLK2
CIBTESTB2inputTCELL0:IMUX_CLK3
CIBTESTB3inputTCELL1:IMUX_LSR0
CIBTESTB4inputTCELL1:IMUX_LSR1
CIBTESTB5inputTCELL1:IMUX_CLK0
CIBTESTT0inputTCELL2:IMUX_LSR3
CIBTESTT1inputTCELL2:IMUX_CLK2
CIBTESTT2inputTCELL2:IMUX_CLK3
CIBTESTT3inputTCELL3:IMUX_LSR1
CIBTESTT4inputTCELL3:IMUX_CLK0
CIBTESTT5inputTCELL3:IMUX_CLK1

Bel wires

scm CLK_ROOT bel wires
WirePins
TCELL0:PCLK0CLK_ROOT.PCLK0_SW
TCELL0:PCLK1CLK_ROOT.PCLK1_SW
TCELL0:PCLK2CLK_ROOT.PCLK2_SW
TCELL0:PCLK3CLK_ROOT.PCLK3_SW
TCELL0:PCLK4CLK_ROOT.PCLK4_SW
TCELL0:PCLK5CLK_ROOT.PCLK5_SW
TCELL0:PCLK6CLK_ROOT.PCLK6_SW
TCELL0:PCLK7CLK_ROOT.PCLK7_SW
TCELL0:PCLK8CLK_ROOT.PCLK8_SW
TCELL0:PCLK9CLK_ROOT.PCLK9_SW
TCELL0:PCLK10CLK_ROOT.PCLK10_SW
TCELL0:PCLK11CLK_ROOT.PCLK11_SW
TCELL0:IMUX_CLK2CLKTEST.CIBTESTB1
TCELL0:IMUX_CLK3CLKTEST.CIBTESTB2
TCELL0:IMUX_LSR2CLK_ROOT.IN_CIBLLQ
TCELL0:IMUX_LSR3CLKTEST.CIBTESTB0
TCELL1:PCLK0CLK_ROOT.PCLK0_SE
TCELL1:PCLK1CLK_ROOT.PCLK1_SE
TCELL1:PCLK2CLK_ROOT.PCLK2_SE
TCELL1:PCLK3CLK_ROOT.PCLK3_SE
TCELL1:PCLK4CLK_ROOT.PCLK4_SE
TCELL1:PCLK5CLK_ROOT.PCLK5_SE
TCELL1:PCLK6CLK_ROOT.PCLK6_SE
TCELL1:PCLK7CLK_ROOT.PCLK7_SE
TCELL1:PCLK8CLK_ROOT.PCLK8_SE
TCELL1:PCLK9CLK_ROOT.PCLK9_SE
TCELL1:PCLK10CLK_ROOT.PCLK10_SE
TCELL1:PCLK11CLK_ROOT.PCLK11_SE
TCELL1:IMUX_CLK0CLKTEST.CIBTESTB5
TCELL1:IMUX_LSR0CLKTEST.CIBTESTB3
TCELL1:IMUX_LSR1CLKTEST.CIBTESTB4
TCELL2:PCLK0CLK_ROOT.PCLK0_NW
TCELL2:PCLK1CLK_ROOT.PCLK1_NW
TCELL2:PCLK2CLK_ROOT.PCLK2_NW
TCELL2:PCLK3CLK_ROOT.PCLK3_NW
TCELL2:PCLK4CLK_ROOT.PCLK4_NW
TCELL2:PCLK5CLK_ROOT.PCLK5_NW
TCELL2:PCLK6CLK_ROOT.PCLK6_NW
TCELL2:PCLK7CLK_ROOT.PCLK7_NW
TCELL2:PCLK8CLK_ROOT.PCLK8_NW
TCELL2:PCLK9CLK_ROOT.PCLK9_NW
TCELL2:PCLK10CLK_ROOT.PCLK10_NW
TCELL2:PCLK11CLK_ROOT.PCLK11_NW
TCELL2:IMUX_CLK2CLKTEST.CIBTESTT1
TCELL2:IMUX_CLK3CLKTEST.CIBTESTT2
TCELL2:IMUX_LSR2CLK_ROOT.IN_CIBULQ
TCELL2:IMUX_LSR3CLKTEST.CIBTESTT0
TCELL3:PCLK0CLK_ROOT.PCLK0_NE
TCELL3:PCLK1CLK_ROOT.PCLK1_NE
TCELL3:PCLK2CLK_ROOT.PCLK2_NE
TCELL3:PCLK3CLK_ROOT.PCLK3_NE
TCELL3:PCLK4CLK_ROOT.PCLK4_NE
TCELL3:PCLK5CLK_ROOT.PCLK5_NE
TCELL3:PCLK6CLK_ROOT.PCLK6_NE
TCELL3:PCLK7CLK_ROOT.PCLK7_NE
TCELL3:PCLK8CLK_ROOT.PCLK8_NE
TCELL3:PCLK9CLK_ROOT.PCLK9_NE
TCELL3:PCLK10CLK_ROOT.PCLK10_NE
TCELL3:PCLK11CLK_ROOT.PCLK11_NE
TCELL3:IMUX_CLK0CLKTEST.CIBTESTT4
TCELL3:IMUX_CLK1CLKTEST.CIBTESTT5
TCELL3:IMUX_LSR0CLK_ROOT.IN_CIBURQ
TCELL3:IMUX_LSR1CLKTEST.CIBTESTT3