I/O Interface

Tile IOI_W_L04

Cells: 1

Switchbox INT

siliconblue IOI_W_L04 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H0[0]	OUT_LC[0]	MAIN[1][17]
QUAD_H0[2]	OUT_LC[1]	MAIN[5][17]
QUAD_H0[4]	OUT_LC[2]	MAIN[9][17]
QUAD_H0[6]	OUT_LC[3]	MAIN[13][17]
QUAD_H0[8]	OUT_LC[0]	MAIN[1][16]
QUAD_H0[10]	OUT_LC[1]	MAIN[5][16]
QUAD_H1[1]	OUT_LC[2]	MAIN[9][16]
QUAD_H1[3]	OUT_LC[3]	MAIN[13][16]
QUAD_H1[5]	OUT_LC[0]	MAIN[0][17]
QUAD_H1[7]	OUT_LC[1]	MAIN[4][17]
QUAD_H1[9]	OUT_LC[2]	MAIN[8][17]
QUAD_H1[11]	OUT_LC[3]	MAIN[12][17]
QUAD_H2[0]	OUT_LC[0]	MAIN[0][16]
QUAD_H2[2]	OUT_LC[1]	MAIN[4][16]
QUAD_H2[4]	OUT_LC[2]	MAIN[8][16]
QUAD_H2[6]	OUT_LC[3]	MAIN[12][16]
QUAD_H2[8]	OUT_LC[0]	MAIN[1][15]
QUAD_H2[10]	OUT_LC[1]	MAIN[5][15]
QUAD_H3[1]	OUT_LC[2]	MAIN[9][15]
QUAD_H3[3]	OUT_LC[3]	MAIN[13][15]
QUAD_H3[5]	OUT_LC[0]	MAIN[3][17]
QUAD_H3[7]	OUT_LC[1]	MAIN[7][17]
QUAD_H3[9]	OUT_LC[2]	MAIN[11][17]
QUAD_H3[11]	OUT_LC[3]	MAIN[15][17]
QUAD_V1[0]	OUT_LC[0]	MAIN[3][15]
QUAD_V1[1]	OUT_LC[1]	MAIN[7][15]
QUAD_V1[2]	OUT_LC[2]	MAIN[11][15]
QUAD_V1[3]	OUT_LC[3]	MAIN[15][15]
QUAD_V2[0]	OUT_LC[0]	MAIN[2][16]
QUAD_V2[1]	OUT_LC[1]	MAIN[6][16]
QUAD_V2[2]	OUT_LC[2]	MAIN[10][16]
QUAD_V2[3]	OUT_LC[3]	MAIN[14][16]
QUAD_V3[0]	OUT_LC[0]	MAIN[2][17]
QUAD_V3[1]	OUT_LC[1]	MAIN[6][17]
QUAD_V3[2]	OUT_LC[2]	MAIN[10][17]
QUAD_V3[3]	OUT_LC[3]	MAIN[14][17]
QUAD_V4[0]	OUT_LC[0]	MAIN[3][16]
QUAD_V4[1]	OUT_LC[1]	MAIN[7][16]
QUAD_V4[2]	OUT_LC[2]	MAIN[11][16]
QUAD_V4[3]	OUT_LC[3]	MAIN[15][16]
LONG_H0[0]	OUT_LC[0]	MAIN[1][0]
LONG_H1[1]	OUT_LC[1]	MAIN[7][1]
LONG_H2[0]	OUT_LC[2]	MAIN[9][1]
LONG_H3[1]	OUT_LC[3]	MAIN[11][0]
LONG_H4[0]	OUT_LC[0]	MAIN[2][0]
LONG_H5[1]	OUT_LC[1]	MAIN[7][0]
LONG_H6[0]	OUT_LC[2]	MAIN[9][0]
LONG_H7[1]	OUT_LC[3]	MAIN[12][0]
LONG_H8[0]	OUT_LC[0]	MAIN[5][0]
LONG_H9[1]	OUT_LC[1]	MAIN[6][1]
LONG_H10[0]	OUT_LC[2]	MAIN[8][1]
LONG_H11[1]	OUT_LC[3]	MAIN[15][0]

siliconblue IOI_W_L04 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[9][4]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[15][4]

siliconblue IOI_W_L04 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[0][3]	MAIN[0][4]	QUAD_H0[1]	-	-	-	-	-	-	-
MAIN[2][3]	MAIN[2][4]	-	QUAD_H0[7]	-	-	-	-	-	-
MAIN[6][3]	MAIN[6][4]	-	-	QUAD_H1[0]	-	-	-	-	-
MAIN[12][3]	MAIN[12][4]	-	-	-	QUAD_H1[6]	-	-	-	-
MAIN[1][5]	MAIN[1][6]	-	-	-	-	QUAD_H2[1]	-	-	-
MAIN[3][5]	MAIN[3][6]	-	-	-	-	-	QUAD_H2[7]	-	-
MAIN[7][5]	MAIN[7][6]	-	-	-	-	-	-	QUAD_H3[0]	-
MAIN[13][5]	MAIN[13][6]	-	-	-	-	-	-	-	QUAD_H3[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H2[1]	QUAD_H2[7]	QUAD_H3[0]	QUAD_H3[6]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	0	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]
1	1	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_H0[1]	QUAD_H0[7]	QUAD_H1[0]	QUAD_H1[6]

siliconblue IOI_W_L04 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[0][6]	MAIN[0][5]	QUAD_V0[0]	-	-	-	-	-	-	-
MAIN[2][6]	MAIN[2][5]	-	QUAD_V0[1]	-	-	-	-	-	-
MAIN[6][6]	MAIN[6][5]	-	-	QUAD_V0[2]	-	-	-	-	-
MAIN[12][6]	MAIN[12][5]	-	-	-	QUAD_V0[3]	-	-	-	-
MAIN[1][3]	MAIN[1][4]	-	-	-	-	QUAD_V4[0]	-	-	-
MAIN[3][3]	MAIN[3][4]	-	-	-	-	-	QUAD_V4[1]	-	-
MAIN[7][3]	MAIN[7][4]	-	-	-	-	-	-	QUAD_V4[2]	-
MAIN[13][3]	MAIN[13][4]	-	-	-	-	-	-	-	QUAD_V4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H2[1]	QUAD_H2[7]	QUAD_H3[0]	QUAD_H3[6]	QUAD_H2[1]	QUAD_H2[7]	QUAD_H3[0]	QUAD_H3[6]
1	0	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	1	QUAD_H0[1]	QUAD_H0[7]	QUAD_H1[0]	QUAD_H1[6]	QUAD_H0[1]	QUAD_H0[7]	QUAD_H1[0]	QUAD_H1[6]

siliconblue IOI_W_L04 switchbox INT muxes LOCAL
Bits					Destination
MAIN[1][12]	MAIN[1][13]	MAIN[0][13]	MAIN[1][11]	MAIN[1][10]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[0][12]	MAIN[1][9]	MAIN[0][9]	MAIN[0][11]	MAIN[0][10]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[3][12]	MAIN[3][13]	MAIN[2][13]	MAIN[3][11]	MAIN[3][10]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[2][12]	MAIN[3][9]	MAIN[2][9]	MAIN[2][11]	MAIN[2][10]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[5][12]	MAIN[5][13]	MAIN[4][13]	MAIN[5][11]	MAIN[5][10]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[4][12]	MAIN[5][9]	MAIN[4][9]	MAIN[4][11]	MAIN[4][10]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[7][12]	MAIN[7][13]	MAIN[6][13]	MAIN[7][11]	MAIN[7][10]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[6][12]	MAIN[7][9]	MAIN[6][9]	MAIN[6][11]	MAIN[6][10]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[9][12]	MAIN[9][13]	MAIN[8][13]	MAIN[9][11]	MAIN[9][10]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[8][12]	MAIN[9][9]	MAIN[8][9]	MAIN[8][11]	MAIN[8][10]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[11][12]	MAIN[11][13]	MAIN[10][13]	MAIN[11][11]	MAIN[11][10]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[10][12]	MAIN[11][9]	MAIN[10][9]	MAIN[10][11]	MAIN[10][10]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[13][12]	MAIN[13][13]	MAIN[12][13]	MAIN[13][11]	MAIN[13][10]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[12][12]	MAIN[13][9]	MAIN[12][9]	MAIN[12][11]	MAIN[12][10]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[15][12]	MAIN[15][13]	MAIN[14][13]	MAIN[15][11]	MAIN[15][10]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[14][12]	MAIN[15][9]	MAIN[14][9]	MAIN[14][11]	MAIN[14][10]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	LONG_H4[0]	LONG_H4[1]	LONG_H5[1]	LONG_H5[0]	LONG_H6[0]	LONG_H6[1]	LONG_H7[1]	LONG_H7[0]
0	0	1	0	1	OUT_LC_WS[0]	OUT_LC_WS[1]	OUT_LC_WS[2]	OUT_LC_WS[3]	OUT_LC_WS[4]	OUT_LC_WS[5]	OUT_LC_WS[6]	OUT_LC_WS[7]
0	0	1	1	1	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[4]	QUAD_H0[5]	QUAD_H0[6]	QUAD_H0[7]
0	1	0	1	1	LONG_H8[0]	LONG_H8[1]	LONG_H9[1]	LONG_H9[0]	LONG_H10[0]	LONG_H10[1]	LONG_H11[1]	LONG_H11[0]
0	1	1	0	1	OUT_LC_W[0]	OUT_LC_W[1]	OUT_LC_W[2]	OUT_LC_W[3]	OUT_LC_W[4]	OUT_LC_W[5]	OUT_LC_W[6]	OUT_LC_W[7]
0	1	1	1	1	QUAD_H0[8]	QUAD_H0[9]	QUAD_H0[10]	QUAD_H0[11]	QUAD_H1[1]	QUAD_H1[0]	QUAD_H1[3]	QUAD_H1[2]
1	0	0	0	1	OUT_LC_WN[0]	OUT_LC_WN[1]	OUT_LC_WN[2]	OUT_LC_WN[3]	OUT_LC_WN[4]	OUT_LC_WN[5]	OUT_LC_WN[6]	OUT_LC_WN[7]
1	0	0	1	1	QUAD_H1[5]	QUAD_H1[4]	QUAD_H1[7]	QUAD_H1[6]	QUAD_H1[9]	QUAD_H1[8]	QUAD_H1[11]	QUAD_H1[10]
1	0	1	0	1	QUAD_V2[0]	QUAD_V2[1]	QUAD_V2[2]	QUAD_V2[3]	QUAD_V1[0]	QUAD_V1[1]	QUAD_V1[2]	QUAD_V1[3]
1	0	1	1	1	QUAD_H2[8]	QUAD_H2[9]	QUAD_H2[10]	QUAD_H2[11]	QUAD_H3[1]	QUAD_H3[0]	QUAD_H3[3]	QUAD_H3[2]
1	1	0	0	1	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_V3[0]	QUAD_V3[1]	QUAD_V3[2]	QUAD_V3[3]
1	1	0	1	1	QUAD_H2[0]	QUAD_H2[1]	QUAD_H2[2]	QUAD_H2[3]	QUAD_H2[4]	QUAD_H2[5]	QUAD_H2[6]	QUAD_H2[7]
1	1	1	0	1	LONG_H0[0]	LONG_H0[1]	LONG_H1[1]	LONG_H1[0]	LONG_H2[0]	LONG_H2[1]	LONG_H3[1]	LONG_H3[0]
1	1	1	1	1	QUAD_H3[5]	QUAD_H3[4]	QUAD_H3[7]	QUAD_H3[6]	QUAD_H3[9]	QUAD_H3[8]	QUAD_H3[11]	QUAD_H3[10]

siliconblue IOI_W_L04 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[11][3]	MAIN[11][2]	MAIN[10][3]	MAIN[10][2]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[0]
0	0	1	1	GLOBAL[2]
0	1	0	1	GLOBAL[4]
0	1	1	1	GLOBAL[6]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_W_L04 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[4][5]	MAIN[4][4]	MAIN[5][5]	MAIN[5][4]	IMUX_IO_DOUT0[0]	-
MAIN[10][5]	MAIN[10][4]	MAIN[11][5]	MAIN[11][4]	-	IMUX_IO_DOUT0[1]
MAIN[8][6]	MAIN[8][7]	MAIN[9][7]	MAIN[9][6]	-	IMUX_IO_DOUT1[0]
MAIN[14][6]	MAIN[14][7]	MAIN[15][7]	MAIN[15][6]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_W_L04 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[4][6]	MAIN[4][7]	MAIN[5][7]	MAIN[5][6]	IMUX_IO_OE[0]	-
MAIN[10][6]	MAIN[10][7]	MAIN[11][7]	MAIN[11][6]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_W_L04 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[8][4]	MAIN[8][3]	MAIN[8][5]	MAIN[9][5]	MAIN[9][2]	IMUX_IO_ICLK	-
MAIN[14][4]	MAIN[14][3]	MAIN[14][5]	MAIN[15][5]	MAIN[15][2]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_W_L04 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[5][3]	MAIN[5][2]	MAIN[4][3]	MAIN[4][2]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_W_L04 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_W_L04 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[3][0]	MAIN[13][0]
PIN_TYPE bit 1	MAIN[3][1]	MAIN[13][1]
PIN_TYPE bit 2	MAIN[0][0]	MAIN[10][0]
PIN_TYPE bit 3	MAIN[0][1]	MAIN[10][1]
PIN_TYPE bit 4	MAIN[4][1]	MAIN[14][1]
PIN_TYPE bit 5	MAIN[4][0]	MAIN[14][0]

Bel wires

siliconblue IOI_W_L04 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_W_L04 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17
F0	IOI[0]: PIN_TYPE bit 2	IOI[0]: PIN_TYPE bit 3	-	INT: mux QUAD_H0[1] bit 1	INT: mux QUAD_H0[1] bit 0	INT: mux QUAD_V0[0] bit 0	INT: mux QUAD_V0[0] bit 1	-	-	INT: mux LOCAL_0[1] bit 2	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[0] bit 2	-	-	INT: buffer QUAD_H2[0] ← OUT_LC[0]	INT: buffer QUAD_H1[5] ← OUT_LC[0]
F1	INT: buffer LONG_H0[0] ← OUT_LC[0]	-	-	INT: mux QUAD_V4[0] bit 1	INT: mux QUAD_V4[0] bit 0	INT: mux QUAD_H2[1] bit 1	INT: mux QUAD_H2[1] bit 0	-	-	INT: mux LOCAL_0[1] bit 3	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 3	-	INT: buffer QUAD_H2[8] ← OUT_LC[0]	INT: buffer QUAD_H0[8] ← OUT_LC[0]	INT: buffer QUAD_H0[0] ← OUT_LC[0]
F2	INT: buffer LONG_H4[0] ← OUT_LC[0]	-	-	INT: mux QUAD_H0[7] bit 1	INT: mux QUAD_H0[7] bit 0	INT: mux QUAD_V0[1] bit 0	INT: mux QUAD_V0[1] bit 1	-	-	INT: mux LOCAL_0[3] bit 2	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[2] bit 2	-	-	INT: buffer QUAD_V2[0] ← OUT_LC[0]	INT: buffer QUAD_V3[0] ← OUT_LC[0]
F3	IOI[0]: PIN_TYPE bit 0	IOI[0]: PIN_TYPE bit 1	-	INT: mux QUAD_V4[1] bit 1	INT: mux QUAD_V4[1] bit 0	INT: mux QUAD_H2[7] bit 1	INT: mux QUAD_H2[7] bit 0	-	-	INT: mux LOCAL_0[3] bit 3	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 3	-	INT: buffer QUAD_V1[0] ← OUT_LC[0]	INT: buffer QUAD_V4[0] ← OUT_LC[0]	INT: buffer QUAD_H3[5] ← OUT_LC[0]
F4	IOI[0]: PIN_TYPE bit 5	IOI[0]: PIN_TYPE bit 4	INT: mux IMUX_IO_EXTRA bit 0	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_OE[0] bit 2	-	INT: mux LOCAL_0[5] bit 2	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[4] bit 2	-	-	INT: buffer QUAD_H2[2] ← OUT_LC[1]	INT: buffer QUAD_H1[7] ← OUT_LC[1]
F5	INT: buffer LONG_H8[0] ← OUT_LC[0]	-	INT: mux IMUX_IO_EXTRA bit 2	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_OE[0] bit 1	-	INT: mux LOCAL_0[5] bit 3	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 3	-	INT: buffer QUAD_H2[10] ← OUT_LC[1]	INT: buffer QUAD_H0[10] ← OUT_LC[1]	INT: buffer QUAD_H0[2] ← OUT_LC[1]
F6	-	INT: buffer LONG_H9[1] ← OUT_LC[1]	-	INT: mux QUAD_H1[0] bit 1	INT: mux QUAD_H1[0] bit 0	INT: mux QUAD_V0[2] bit 0	INT: mux QUAD_V0[2] bit 1	-	-	INT: mux LOCAL_0[7] bit 2	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[6] bit 2	-	-	INT: buffer QUAD_V2[1] ← OUT_LC[1]	INT: buffer QUAD_V3[1] ← OUT_LC[1]
F7	INT: buffer LONG_H5[1] ← OUT_LC[1]	INT: buffer LONG_H1[1] ← OUT_LC[1]	-	INT: mux QUAD_V4[2] bit 1	INT: mux QUAD_V4[2] bit 0	INT: mux QUAD_H3[0] bit 1	INT: mux QUAD_H3[0] bit 0	-	-	INT: mux LOCAL_0[7] bit 3	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 3	-	INT: buffer QUAD_V1[1] ← OUT_LC[1]	INT: buffer QUAD_V4[1] ← OUT_LC[1]	INT: buffer QUAD_H3[7] ← OUT_LC[1]
F8	-	INT: buffer LONG_H10[0] ← OUT_LC[2]	-	INT: mux IMUX_IO_ICLK bit 3	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_DOUT1[0] bit 2	-	INT: mux LOCAL_1[1] bit 2	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[0] bit 2	-	-	INT: buffer QUAD_H2[4] ← OUT_LC[2]	INT: buffer QUAD_H1[9] ← OUT_LC[2]
F9	INT: buffer LONG_H6[0] ← OUT_LC[2]	INT: buffer LONG_H2[0] ← OUT_LC[2]	INT: mux IMUX_IO_ICLK bit 0	-	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	INT: mux IMUX_IO_ICLK bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_DOUT1[0] bit 1	-	INT: mux LOCAL_1[1] bit 3	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 3	-	INT: buffer QUAD_H3[1] ← OUT_LC[2]	INT: buffer QUAD_H1[1] ← OUT_LC[2]	INT: buffer QUAD_H0[4] ← OUT_LC[2]
F10	IOI[1]: PIN_TYPE bit 2	IOI[1]: PIN_TYPE bit 3	INT: mux IMUX_CE bit 0	INT: mux IMUX_CE bit 1	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_OE[1] bit 2	-	INT: mux LOCAL_1[3] bit 2	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[2] bit 2	-	-	INT: buffer QUAD_V2[2] ← OUT_LC[2]	INT: buffer QUAD_V3[2] ← OUT_LC[2]
F11	INT: buffer LONG_H3[1] ← OUT_LC[3]	-	INT: mux IMUX_CE bit 2	INT: mux IMUX_CE bit 3	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_OE[1] bit 1	-	INT: mux LOCAL_1[3] bit 3	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 3	-	INT: buffer QUAD_V1[2] ← OUT_LC[2]	INT: buffer QUAD_V4[2] ← OUT_LC[2]	INT: buffer QUAD_H3[9] ← OUT_LC[2]
F12	INT: buffer LONG_H7[1] ← OUT_LC[3]	-	-	INT: mux QUAD_H1[6] bit 1	INT: mux QUAD_H1[6] bit 0	INT: mux QUAD_V0[3] bit 0	INT: mux QUAD_V0[3] bit 1	-	-	INT: mux LOCAL_1[5] bit 2	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[4] bit 2	-	-	INT: buffer QUAD_H2[6] ← OUT_LC[3]	INT: buffer QUAD_H1[11] ← OUT_LC[3]
F13	IOI[1]: PIN_TYPE bit 0	IOI[1]: PIN_TYPE bit 1	-	INT: mux QUAD_V4[3] bit 1	INT: mux QUAD_V4[3] bit 0	INT: mux QUAD_H3[6] bit 1	INT: mux QUAD_H3[6] bit 0	-	-	INT: mux LOCAL_1[5] bit 3	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 3	-	INT: buffer QUAD_H3[3] ← OUT_LC[3]	INT: buffer QUAD_H1[3] ← OUT_LC[3]	INT: buffer QUAD_H0[6] ← OUT_LC[3]
F14	IOI[1]: PIN_TYPE bit 5	IOI[1]: PIN_TYPE bit 4	-	INT: mux IMUX_IO_OCLK bit 3	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_DOUT1[1] bit 2	-	INT: mux LOCAL_1[7] bit 2	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[6] bit 2	-	-	INT: buffer QUAD_V2[3] ← OUT_LC[3]	INT: buffer QUAD_V3[3] ← OUT_LC[3]
F15	INT: buffer LONG_H11[1] ← OUT_LC[3]	-	INT: mux IMUX_IO_OCLK bit 0	-	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	INT: mux IMUX_IO_OCLK bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_DOUT1[1] bit 1	-	INT: mux LOCAL_1[7] bit 3	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 3	-	INT: buffer QUAD_V1[3] ← OUT_LC[3]	INT: buffer QUAD_V4[3] ← OUT_LC[3]	INT: buffer QUAD_H3[11] ← OUT_LC[3]

Tile IOI_E_L04

Cells: 1

Switchbox INT

siliconblue IOI_E_L04 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H1[0]	OUT_LC[0]	MAIN[1][0]
QUAD_H1[2]	OUT_LC[1]	MAIN[5][0]
QUAD_H1[4]	OUT_LC[2]	MAIN[9][0]
QUAD_H1[6]	OUT_LC[3]	MAIN[13][0]
QUAD_H1[8]	OUT_LC[0]	MAIN[1][1]
QUAD_H1[10]	OUT_LC[1]	MAIN[5][1]
QUAD_H2[1]	OUT_LC[2]	MAIN[9][1]
QUAD_H2[3]	OUT_LC[3]	MAIN[13][1]
QUAD_H2[5]	OUT_LC[0]	MAIN[0][0]
QUAD_H2[7]	OUT_LC[1]	MAIN[4][0]
QUAD_H2[9]	OUT_LC[2]	MAIN[8][0]
QUAD_H2[11]	OUT_LC[3]	MAIN[12][0]
QUAD_H3[0]	OUT_LC[0]	MAIN[0][1]
QUAD_H3[2]	OUT_LC[1]	MAIN[4][1]
QUAD_H3[4]	OUT_LC[2]	MAIN[8][1]
QUAD_H3[6]	OUT_LC[3]	MAIN[12][1]
QUAD_H3[8]	OUT_LC[0]	MAIN[1][2]
QUAD_H3[10]	OUT_LC[1]	MAIN[5][2]
QUAD_H4[1]	OUT_LC[2]	MAIN[9][2]
QUAD_H4[3]	OUT_LC[3]	MAIN[13][2]
QUAD_H4[5]	OUT_LC[0]	MAIN[3][0]
QUAD_H4[7]	OUT_LC[1]	MAIN[7][0]
QUAD_H4[9]	OUT_LC[2]	MAIN[11][0]
QUAD_H4[11]	OUT_LC[3]	MAIN[15][0]
QUAD_V1[0]	OUT_LC[0]	MAIN[3][2]
QUAD_V1[1]	OUT_LC[1]	MAIN[7][2]
QUAD_V1[2]	OUT_LC[2]	MAIN[11][2]
QUAD_V1[3]	OUT_LC[3]	MAIN[15][2]
QUAD_V2[0]	OUT_LC[0]	MAIN[2][1]
QUAD_V2[1]	OUT_LC[1]	MAIN[6][1]
QUAD_V2[2]	OUT_LC[2]	MAIN[10][1]
QUAD_V2[3]	OUT_LC[3]	MAIN[14][1]
QUAD_V3[0]	OUT_LC[0]	MAIN[2][0]
QUAD_V3[1]	OUT_LC[1]	MAIN[6][0]
QUAD_V3[2]	OUT_LC[2]	MAIN[10][0]
QUAD_V3[3]	OUT_LC[3]	MAIN[14][0]
QUAD_V4[0]	OUT_LC[0]	MAIN[3][1]
QUAD_V4[1]	OUT_LC[1]	MAIN[7][1]
QUAD_V4[2]	OUT_LC[2]	MAIN[11][1]
QUAD_V4[3]	OUT_LC[3]	MAIN[15][1]
LONG_H1[0]	OUT_LC[0]	MAIN[1][17]
LONG_H2[1]	OUT_LC[1]	MAIN[7][16]
LONG_H3[0]	OUT_LC[2]	MAIN[9][16]
LONG_H4[1]	OUT_LC[3]	MAIN[11][17]
LONG_H5[0]	OUT_LC[0]	MAIN[2][17]
LONG_H6[1]	OUT_LC[1]	MAIN[7][17]
LONG_H7[0]	OUT_LC[2]	MAIN[9][17]
LONG_H8[1]	OUT_LC[3]	MAIN[12][17]
LONG_H9[0]	OUT_LC[0]	MAIN[5][17]
LONG_H10[1]	OUT_LC[1]	MAIN[6][16]
LONG_H11[0]	OUT_LC[2]	MAIN[8][16]
LONG_H12[1]	OUT_LC[3]	MAIN[15][17]

siliconblue IOI_E_L04 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[9][13]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[15][13]

siliconblue IOI_E_L04 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[0][14]	MAIN[0][13]	QUAD_H1[1]	-	-	-	-	-	-	-
MAIN[2][14]	MAIN[2][13]	-	QUAD_H1[7]	-	-	-	-	-	-
MAIN[6][14]	MAIN[6][13]	-	-	QUAD_H2[0]	-	-	-	-	-
MAIN[12][14]	MAIN[12][13]	-	-	-	QUAD_H2[6]	-	-	-	-
MAIN[1][12]	MAIN[1][11]	-	-	-	-	QUAD_H3[1]	-	-	-
MAIN[3][12]	MAIN[3][11]	-	-	-	-	-	QUAD_H3[7]	-	-
MAIN[7][12]	MAIN[7][11]	-	-	-	-	-	-	QUAD_H4[0]	-
MAIN[13][12]	MAIN[13][11]	-	-	-	-	-	-	-	QUAD_H4[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H3[1]	QUAD_H3[7]	QUAD_H4[0]	QUAD_H4[6]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	0	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]
1	1	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_H1[1]	QUAD_H1[7]	QUAD_H2[0]	QUAD_H2[6]

siliconblue IOI_E_L04 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[0][11]	MAIN[0][12]	QUAD_V0[0]	-	-	-	-	-	-	-
MAIN[2][11]	MAIN[2][12]	-	QUAD_V0[1]	-	-	-	-	-	-
MAIN[6][11]	MAIN[6][12]	-	-	QUAD_V0[2]	-	-	-	-	-
MAIN[12][11]	MAIN[12][12]	-	-	-	QUAD_V0[3]	-	-	-	-
MAIN[1][14]	MAIN[1][13]	-	-	-	-	QUAD_V4[0]	-	-	-
MAIN[3][14]	MAIN[3][13]	-	-	-	-	-	QUAD_V4[1]	-	-
MAIN[7][14]	MAIN[7][13]	-	-	-	-	-	-	QUAD_V4[2]	-
MAIN[13][14]	MAIN[13][13]	-	-	-	-	-	-	-	QUAD_V4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H3[1]	QUAD_H3[7]	QUAD_H4[0]	QUAD_H4[6]	QUAD_H3[1]	QUAD_H3[7]	QUAD_H4[0]	QUAD_H4[6]
1	0	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	1	QUAD_H1[1]	QUAD_H1[7]	QUAD_H2[0]	QUAD_H2[6]	QUAD_H1[1]	QUAD_H1[7]	QUAD_H2[0]	QUAD_H2[6]

siliconblue IOI_E_L04 switchbox INT muxes LOCAL
Bits					Destination
MAIN[1][5]	MAIN[1][4]	MAIN[0][4]	MAIN[1][6]	MAIN[1][7]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[0][5]	MAIN[1][8]	MAIN[0][8]	MAIN[0][6]	MAIN[0][7]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[3][5]	MAIN[3][4]	MAIN[2][4]	MAIN[3][6]	MAIN[3][7]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[2][5]	MAIN[3][8]	MAIN[2][8]	MAIN[2][6]	MAIN[2][7]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[5][5]	MAIN[5][4]	MAIN[4][4]	MAIN[5][6]	MAIN[5][7]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[4][5]	MAIN[5][8]	MAIN[4][8]	MAIN[4][6]	MAIN[4][7]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[7][5]	MAIN[7][4]	MAIN[6][4]	MAIN[7][6]	MAIN[7][7]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[6][5]	MAIN[7][8]	MAIN[6][8]	MAIN[6][6]	MAIN[6][7]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[9][5]	MAIN[9][4]	MAIN[8][4]	MAIN[9][6]	MAIN[9][7]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[8][5]	MAIN[9][8]	MAIN[8][8]	MAIN[8][6]	MAIN[8][7]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[11][5]	MAIN[11][4]	MAIN[10][4]	MAIN[11][6]	MAIN[11][7]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[10][5]	MAIN[11][8]	MAIN[10][8]	MAIN[10][6]	MAIN[10][7]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[13][5]	MAIN[13][4]	MAIN[12][4]	MAIN[13][6]	MAIN[13][7]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[12][5]	MAIN[13][8]	MAIN[12][8]	MAIN[12][6]	MAIN[12][7]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[15][5]	MAIN[15][4]	MAIN[14][4]	MAIN[15][6]	MAIN[15][7]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[14][5]	MAIN[15][8]	MAIN[14][8]	MAIN[14][6]	MAIN[14][7]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	LONG_H5[0]	LONG_H5[1]	LONG_H6[1]	LONG_H6[0]	LONG_H7[0]	LONG_H7[1]	LONG_H8[1]	LONG_H8[0]
0	0	1	0	1	OUT_LC_ES[0]	OUT_LC_ES[1]	OUT_LC_ES[2]	OUT_LC_ES[3]	OUT_LC_ES[4]	OUT_LC_ES[5]	OUT_LC_ES[6]	OUT_LC_ES[7]
0	0	1	1	1	QUAD_H1[0]	QUAD_H1[1]	QUAD_H1[2]	QUAD_H1[3]	QUAD_H1[4]	QUAD_H1[5]	QUAD_H1[6]	QUAD_H1[7]
0	1	0	1	1	LONG_H9[0]	LONG_H9[1]	LONG_H10[1]	LONG_H10[0]	LONG_H11[0]	LONG_H11[1]	LONG_H12[1]	LONG_H12[0]
0	1	1	0	1	OUT_LC_E[0]	OUT_LC_E[1]	OUT_LC_E[2]	OUT_LC_E[3]	OUT_LC_E[4]	OUT_LC_E[5]	OUT_LC_E[6]	OUT_LC_E[7]
0	1	1	1	1	QUAD_H1[8]	QUAD_H1[9]	QUAD_H1[10]	QUAD_H1[11]	QUAD_H2[1]	QUAD_H2[0]	QUAD_H2[3]	QUAD_H2[2]
1	0	0	0	1	OUT_LC_EN[0]	OUT_LC_EN[1]	OUT_LC_EN[2]	OUT_LC_EN[3]	OUT_LC_EN[4]	OUT_LC_EN[5]	OUT_LC_EN[6]	OUT_LC_EN[7]
1	0	0	1	1	QUAD_H2[5]	QUAD_H2[4]	QUAD_H2[7]	QUAD_H2[6]	QUAD_H2[9]	QUAD_H2[8]	QUAD_H2[11]	QUAD_H2[10]
1	0	1	0	1	QUAD_V2[0]	QUAD_V2[1]	QUAD_V2[2]	QUAD_V2[3]	QUAD_V1[0]	QUAD_V1[1]	QUAD_V1[2]	QUAD_V1[3]
1	0	1	1	1	QUAD_H3[8]	QUAD_H3[9]	QUAD_H3[10]	QUAD_H3[11]	QUAD_H4[1]	QUAD_H4[0]	QUAD_H4[3]	QUAD_H4[2]
1	1	0	0	1	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_V3[0]	QUAD_V3[1]	QUAD_V3[2]	QUAD_V3[3]
1	1	0	1	1	QUAD_H3[0]	QUAD_H3[1]	QUAD_H3[2]	QUAD_H3[3]	QUAD_H3[4]	QUAD_H3[5]	QUAD_H3[6]	QUAD_H3[7]
1	1	1	0	1	LONG_H1[0]	LONG_H1[1]	LONG_H2[1]	LONG_H2[0]	LONG_H3[0]	LONG_H3[1]	LONG_H4[1]	LONG_H4[0]
1	1	1	1	1	QUAD_H4[5]	QUAD_H4[4]	QUAD_H4[7]	QUAD_H4[6]	QUAD_H4[9]	QUAD_H4[8]	QUAD_H4[11]	QUAD_H4[10]

siliconblue IOI_E_L04 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[11][14]	MAIN[11][15]	MAIN[10][14]	MAIN[10][15]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[0]
0	0	1	1	GLOBAL[2]
0	1	0	1	GLOBAL[4]
0	1	1	1	GLOBAL[6]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_E_L04 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[4][12]	MAIN[4][13]	MAIN[5][12]	MAIN[5][13]	IMUX_IO_DOUT0[0]	-
MAIN[10][12]	MAIN[10][13]	MAIN[11][12]	MAIN[11][13]	-	IMUX_IO_DOUT0[1]
MAIN[8][11]	MAIN[8][10]	MAIN[9][10]	MAIN[9][11]	-	IMUX_IO_DOUT1[0]
MAIN[14][11]	MAIN[14][10]	MAIN[15][10]	MAIN[15][11]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_E_L04 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[4][11]	MAIN[4][10]	MAIN[5][10]	MAIN[5][11]	IMUX_IO_OE[0]	-
MAIN[10][11]	MAIN[10][10]	MAIN[11][10]	MAIN[11][11]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_E_L04 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[8][13]	MAIN[8][14]	MAIN[8][12]	MAIN[9][12]	MAIN[9][15]	IMUX_IO_ICLK	-
MAIN[14][13]	MAIN[14][14]	MAIN[14][12]	MAIN[15][12]	MAIN[15][15]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_E_L04 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[5][14]	MAIN[5][15]	MAIN[4][14]	MAIN[4][15]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_E_L04 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_E_L04 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[3][17]	MAIN[13][17]
PIN_TYPE bit 1	MAIN[3][16]	MAIN[13][16]
PIN_TYPE bit 2	MAIN[0][17]	MAIN[10][17]
PIN_TYPE bit 3	MAIN[0][16]	MAIN[10][16]
PIN_TYPE bit 4	MAIN[4][16]	MAIN[14][16]
PIN_TYPE bit 5	MAIN[4][17]	MAIN[14][17]

Bel wires

siliconblue IOI_E_L04 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_E_L04 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17
F0	INT: buffer QUAD_H2[5] ← OUT_LC[0]	INT: buffer QUAD_H3[0] ← OUT_LC[0]	-	-	INT: mux LOCAL_0[0] bit 2	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 2	-	-	INT: mux QUAD_V0[0] bit 1	INT: mux QUAD_V0[0] bit 0	INT: mux QUAD_H1[1] bit 0	INT: mux QUAD_H1[1] bit 1	-	IOI[0]: PIN_TYPE bit 3	IOI[0]: PIN_TYPE bit 2
F1	INT: buffer QUAD_H1[0] ← OUT_LC[0]	INT: buffer QUAD_H1[8] ← OUT_LC[0]	INT: buffer QUAD_H3[8] ← OUT_LC[0]	-	INT: mux LOCAL_0[0] bit 3	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[1] bit 3	-	-	INT: mux QUAD_H3[1] bit 0	INT: mux QUAD_H3[1] bit 1	INT: mux QUAD_V4[0] bit 0	INT: mux QUAD_V4[0] bit 1	-	-	INT: buffer LONG_H1[0] ← OUT_LC[0]
F2	INT: buffer QUAD_V3[0] ← OUT_LC[0]	INT: buffer QUAD_V2[0] ← OUT_LC[0]	-	-	INT: mux LOCAL_0[2] bit 2	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 2	-	-	INT: mux QUAD_V0[1] bit 1	INT: mux QUAD_V0[1] bit 0	INT: mux QUAD_H1[7] bit 0	INT: mux QUAD_H1[7] bit 1	-	-	INT: buffer LONG_H5[0] ← OUT_LC[0]
F3	INT: buffer QUAD_H4[5] ← OUT_LC[0]	INT: buffer QUAD_V4[0] ← OUT_LC[0]	INT: buffer QUAD_V1[0] ← OUT_LC[0]	-	INT: mux LOCAL_0[2] bit 3	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[3] bit 3	-	-	INT: mux QUAD_H3[7] bit 0	INT: mux QUAD_H3[7] bit 1	INT: mux QUAD_V4[1] bit 0	INT: mux QUAD_V4[1] bit 1	-	IOI[0]: PIN_TYPE bit 1	IOI[0]: PIN_TYPE bit 0
F4	INT: buffer QUAD_H2[7] ← OUT_LC[1]	INT: buffer QUAD_H3[2] ← OUT_LC[1]	-	-	INT: mux LOCAL_0[4] bit 2	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 2	-	INT: mux IMUX_IO_OE[0] bit 2	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_EXTRA bit 0	IOI[0]: PIN_TYPE bit 4	IOI[0]: PIN_TYPE bit 5
F5	INT: buffer QUAD_H1[2] ← OUT_LC[1]	INT: buffer QUAD_H1[10] ← OUT_LC[1]	INT: buffer QUAD_H3[10] ← OUT_LC[1]	-	INT: mux LOCAL_0[4] bit 3	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[5] bit 3	-	INT: mux IMUX_IO_OE[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_EXTRA bit 2	-	INT: buffer LONG_H9[0] ← OUT_LC[0]
F6	INT: buffer QUAD_V3[1] ← OUT_LC[1]	INT: buffer QUAD_V2[1] ← OUT_LC[1]	-	-	INT: mux LOCAL_0[6] bit 2	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 2	-	-	INT: mux QUAD_V0[2] bit 1	INT: mux QUAD_V0[2] bit 0	INT: mux QUAD_H2[0] bit 0	INT: mux QUAD_H2[0] bit 1	-	INT: buffer LONG_H10[1] ← OUT_LC[1]	-
F7	INT: buffer QUAD_H4[7] ← OUT_LC[1]	INT: buffer QUAD_V4[1] ← OUT_LC[1]	INT: buffer QUAD_V1[1] ← OUT_LC[1]	-	INT: mux LOCAL_0[6] bit 3	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[7] bit 3	-	-	INT: mux QUAD_H4[0] bit 0	INT: mux QUAD_H4[0] bit 1	INT: mux QUAD_V4[2] bit 0	INT: mux QUAD_V4[2] bit 1	-	INT: buffer LONG_H2[1] ← OUT_LC[1]	INT: buffer LONG_H6[1] ← OUT_LC[1]
F8	INT: buffer QUAD_H2[9] ← OUT_LC[2]	INT: buffer QUAD_H3[4] ← OUT_LC[2]	-	-	INT: mux LOCAL_1[0] bit 2	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 2	-	INT: mux IMUX_IO_DOUT1[0] bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 3	-	INT: buffer LONG_H11[0] ← OUT_LC[2]	-
F9	INT: buffer QUAD_H1[4] ← OUT_LC[2]	INT: buffer QUAD_H2[1] ← OUT_LC[2]	INT: buffer QUAD_H4[1] ← OUT_LC[2]	-	INT: mux LOCAL_1[0] bit 3	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[1] bit 3	-	INT: mux IMUX_IO_DOUT1[0] bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_ICLK bit 1	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	-	INT: mux IMUX_IO_ICLK bit 0	INT: buffer LONG_H3[0] ← OUT_LC[2]	INT: buffer LONG_H7[0] ← OUT_LC[2]
F10	INT: buffer QUAD_V3[2] ← OUT_LC[2]	INT: buffer QUAD_V2[2] ← OUT_LC[2]	-	-	INT: mux LOCAL_1[2] bit 2	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 2	-	INT: mux IMUX_IO_OE[1] bit 2	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_CE bit 1	INT: mux IMUX_CE bit 0	IOI[1]: PIN_TYPE bit 3	IOI[1]: PIN_TYPE bit 2
F11	INT: buffer QUAD_H4[9] ← OUT_LC[2]	INT: buffer QUAD_V4[2] ← OUT_LC[2]	INT: buffer QUAD_V1[2] ← OUT_LC[2]	-	INT: mux LOCAL_1[2] bit 3	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[3] bit 3	-	INT: mux IMUX_IO_OE[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_CE bit 3	INT: mux IMUX_CE bit 2	-	INT: buffer LONG_H4[1] ← OUT_LC[3]
F12	INT: buffer QUAD_H2[11] ← OUT_LC[3]	INT: buffer QUAD_H3[6] ← OUT_LC[3]	-	-	INT: mux LOCAL_1[4] bit 2	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 2	-	-	INT: mux QUAD_V0[3] bit 1	INT: mux QUAD_V0[3] bit 0	INT: mux QUAD_H2[6] bit 0	INT: mux QUAD_H2[6] bit 1	-	-	INT: buffer LONG_H8[1] ← OUT_LC[3]
F13	INT: buffer QUAD_H1[6] ← OUT_LC[3]	INT: buffer QUAD_H2[3] ← OUT_LC[3]	INT: buffer QUAD_H4[3] ← OUT_LC[3]	-	INT: mux LOCAL_1[4] bit 3	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[5] bit 3	-	-	INT: mux QUAD_H4[6] bit 0	INT: mux QUAD_H4[6] bit 1	INT: mux QUAD_V4[3] bit 0	INT: mux QUAD_V4[3] bit 1	-	IOI[1]: PIN_TYPE bit 1	IOI[1]: PIN_TYPE bit 0
F14	INT: buffer QUAD_V3[3] ← OUT_LC[3]	INT: buffer QUAD_V2[3] ← OUT_LC[3]	-	-	INT: mux LOCAL_1[6] bit 2	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 2	-	INT: mux IMUX_IO_DOUT1[1] bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 3	-	IOI[1]: PIN_TYPE bit 4	IOI[1]: PIN_TYPE bit 5
F15	INT: buffer QUAD_H4[11] ← OUT_LC[3]	INT: buffer QUAD_V4[3] ← OUT_LC[3]	INT: buffer QUAD_V1[3] ← OUT_LC[3]	-	INT: mux LOCAL_1[6] bit 3	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[7] bit 3	-	INT: mux IMUX_IO_DOUT1[1] bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_OCLK bit 1	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	-	INT: mux IMUX_IO_OCLK bit 0	-	INT: buffer LONG_H12[1] ← OUT_LC[3]

Tile IOI_S_L04

Cells: 1

Switchbox INT

siliconblue IOI_S_L04 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H0[0]	OUT_LC[0]	MAIN[13][25]
QUAD_H0[1]	OUT_LC[1]	MAIN[9][25]
QUAD_H0[2]	OUT_LC[2]	MAIN[5][25]
QUAD_H0[3]	OUT_LC[3]	MAIN[1][25]
QUAD_H1[0]	OUT_LC[0]	MAIN[12][23]
QUAD_H1[1]	OUT_LC[1]	MAIN[8][23]
QUAD_H1[2]	OUT_LC[2]	MAIN[4][23]
QUAD_H1[3]	OUT_LC[3]	MAIN[0][23]
QUAD_H2[0]	OUT_LC[0]	MAIN[12][25]
QUAD_H2[1]	OUT_LC[1]	MAIN[8][25]
QUAD_H2[2]	OUT_LC[2]	MAIN[4][25]
QUAD_H2[3]	OUT_LC[3]	MAIN[0][25]
QUAD_H3[0]	OUT_LC[0]	MAIN[13][26]
QUAD_H3[1]	OUT_LC[1]	MAIN[9][26]
QUAD_H3[2]	OUT_LC[2]	MAIN[5][26]
QUAD_H3[3]	OUT_LC[3]	MAIN[1][26]
QUAD_V0[0]	OUT_LC[2]	MAIN[6][26]
QUAD_V0[2]	OUT_LC[3]	MAIN[2][26]
QUAD_V0[4]	OUT_LC[0]	MAIN[13][23]
QUAD_V0[6]	OUT_LC[1]	MAIN[9][23]
QUAD_V0[8]	OUT_LC[2]	MAIN[5][23]
QUAD_V0[10]	OUT_LC[3]	MAIN[1][23]
QUAD_V1[1]	OUT_LC[0]	MAIN[15][25]
QUAD_V1[3]	OUT_LC[1]	MAIN[11][25]
QUAD_V1[5]	OUT_LC[2]	MAIN[7][25]
QUAD_V1[7]	OUT_LC[3]	MAIN[3][25]
QUAD_V1[9]	OUT_LC[0]	MAIN[14][26]
QUAD_V1[11]	OUT_LC[1]	MAIN[10][26]
QUAD_V2[0]	OUT_LC[2]	MAIN[6][25]
QUAD_V2[2]	OUT_LC[3]	MAIN[2][25]
QUAD_V2[4]	OUT_LC[0]	MAIN[15][23]
QUAD_V2[6]	OUT_LC[1]	MAIN[11][23]
QUAD_V2[8]	OUT_LC[2]	MAIN[7][23]
QUAD_V2[10]	OUT_LC[3]	MAIN[3][23]
QUAD_V3[1]	OUT_LC[0]	MAIN[14][23]
QUAD_V3[3]	OUT_LC[1]	MAIN[10][23]
QUAD_V3[5]	OUT_LC[2]	MAIN[6][23]
QUAD_V3[7]	OUT_LC[3]	MAIN[2][23]
QUAD_V3[9]	OUT_LC[0]	MAIN[14][25]
QUAD_V3[11]	OUT_LC[1]	MAIN[10][25]
LONG_V0[0]	OUT_LC[3]	MAIN[1][5]
LONG_V1[1]	OUT_LC[2]	MAIN[7][4]
LONG_V2[0]	OUT_LC[1]	MAIN[8][4]
LONG_V3[1]	OUT_LC[0]	MAIN[10][5]
LONG_V4[0]	OUT_LC[3]	MAIN[3][5]
LONG_V5[1]	OUT_LC[2]	MAIN[6][5]
LONG_V6[0]	OUT_LC[1]	MAIN[9][5]
LONG_V7[1]	OUT_LC[0]	MAIN[12][5]
LONG_V8[0]	OUT_LC[3]	MAIN[5][5]
LONG_V9[1]	OUT_LC[2]	MAIN[6][4]
LONG_V10[0]	OUT_LC[1]	MAIN[9][4]
LONG_V11[1]	OUT_LC[0]	MAIN[14][5]

siliconblue IOI_S_L04 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[6][35]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[1][35]

siliconblue IOI_S_L04 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[14][35]	MAIN[14][36]	QUAD_H0[0]	-	-	-	-	-	-	-
MAIN[13][35]	MAIN[13][36]	-	QUAD_H0[1]	-	-	-	-	-	-
MAIN[9][35]	MAIN[9][36]	-	-	QUAD_H0[2]	-	-	-	-	-
MAIN[2][35]	MAIN[2][36]	-	-	-	QUAD_H0[3]	-	-	-	-
MAIN[15][34]	MAIN[15][33]	-	-	-	-	QUAD_H4[0]	-	-	-
MAIN[12][34]	MAIN[12][33]	-	-	-	-	-	QUAD_H4[1]	-	-
MAIN[8][34]	MAIN[8][33]	-	-	-	-	-	-	QUAD_H4[2]	-
MAIN[3][34]	MAIN[3][33]	-	-	-	-	-	-	-	QUAD_H4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H4[0]	QUAD_H4[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]
1	0	QUAD_V1[0]	QUAD_V1[6]	QUAD_V0[1]	QUAD_V0[7]	QUAD_V1[0]	QUAD_V1[6]	QUAD_V0[1]	QUAD_V0[7]
1	1	QUAD_V3[0]	QUAD_V3[6]	QUAD_V2[1]	QUAD_V2[7]	QUAD_V3[0]	QUAD_V3[6]	QUAD_V2[1]	QUAD_V2[7]

siliconblue IOI_S_L04 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[9][33]	MAIN[9][34]	QUAD_V0[1]	-	-	-	-	-	-	-
MAIN[2][33]	MAIN[2][34]	-	QUAD_V0[7]	-	-	-	-	-	-
MAIN[14][33]	MAIN[14][34]	-	-	QUAD_V1[0]	-	-	-	-	-
MAIN[13][33]	MAIN[13][34]	-	-	-	QUAD_V1[6]	-	-	-	-
MAIN[8][35]	MAIN[8][36]	-	-	-	-	QUAD_V2[1]	-	-	-
MAIN[3][35]	MAIN[3][36]	-	-	-	-	-	QUAD_V2[7]	-	-
MAIN[15][35]	MAIN[15][36]	-	-	-	-	-	-	QUAD_V3[0]	-
MAIN[12][35]	MAIN[12][36]	-	-	-	-	-	-	-	QUAD_V3[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]
1	0	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]	QUAD_V0[1]	QUAD_V0[7]	QUAD_V1[0]	QUAD_V1[6]
1	1	QUAD_V2[1]	QUAD_V2[7]	QUAD_V3[0]	QUAD_V3[6]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]

siliconblue IOI_S_L04 switchbox INT muxes LOCAL
Bits					Destination
MAIN[14][18]	MAIN[15][16]	MAIN[14][16]	MAIN[14][17]	MAIN[14][19]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[15][18]	MAIN[15][20]	MAIN[14][20]	MAIN[15][17]	MAIN[15][19]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[13][18]	MAIN[12][16]	MAIN[13][16]	MAIN[13][17]	MAIN[13][19]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[12][18]	MAIN[12][20]	MAIN[13][20]	MAIN[12][17]	MAIN[12][19]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[10][18]	MAIN[11][16]	MAIN[10][16]	MAIN[10][17]	MAIN[10][19]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[11][18]	MAIN[11][20]	MAIN[10][20]	MAIN[11][17]	MAIN[11][19]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[9][18]	MAIN[8][16]	MAIN[9][16]	MAIN[9][17]	MAIN[9][19]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[8][18]	MAIN[8][20]	MAIN[9][20]	MAIN[8][17]	MAIN[8][19]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[6][18]	MAIN[7][16]	MAIN[6][16]	MAIN[6][17]	MAIN[6][19]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[7][18]	MAIN[7][20]	MAIN[6][20]	MAIN[7][17]	MAIN[7][19]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[5][18]	MAIN[4][16]	MAIN[5][16]	MAIN[5][17]	MAIN[5][19]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[4][18]	MAIN[4][20]	MAIN[5][20]	MAIN[4][17]	MAIN[4][19]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[2][18]	MAIN[3][16]	MAIN[2][16]	MAIN[2][17]	MAIN[2][19]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[3][18]	MAIN[3][20]	MAIN[2][20]	MAIN[3][17]	MAIN[3][19]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[1][18]	MAIN[0][16]	MAIN[1][16]	MAIN[1][17]	MAIN[1][19]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[0][18]	MAIN[0][20]	MAIN[1][20]	MAIN[0][17]	MAIN[0][19]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	OUT_LC_WS[0]	OUT_LC_WS[1]	OUT_LC_WS[2]	OUT_LC_WS[3]	OUT_LC_WS[4]	OUT_LC_WS[5]	OUT_LC_WS[6]	OUT_LC_WS[7]
0	0	1	1	1	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H1[0]	QUAD_H1[1]	QUAD_H1[2]	QUAD_H1[3]
0	1	0	0	1	OUT_LC_ES[0]	OUT_LC_ES[1]	OUT_LC_ES[2]	OUT_LC_ES[3]	OUT_LC_ES[4]	OUT_LC_ES[5]	OUT_LC_ES[6]	OUT_LC_ES[7]
0	1	0	1	1	QUAD_H2[0]	QUAD_H2[1]	QUAD_H2[2]	QUAD_H2[3]	QUAD_H3[0]	QUAD_H3[1]	QUAD_H3[2]	QUAD_H3[3]
0	1	1	0	1	OUT_LC_S[0]	OUT_LC_S[1]	OUT_LC_S[2]	OUT_LC_S[3]	OUT_LC_S[4]	OUT_LC_S[5]	OUT_LC_S[6]	OUT_LC_S[7]
0	1	1	1	1	LONG_V11[1]	LONG_V11[0]	LONG_V10[0]	LONG_V10[1]	LONG_V9[1]	LONG_V9[0]	LONG_V8[0]	LONG_V8[1]
1	0	0	0	1	LONG_V7[1]	LONG_V7[0]	LONG_V6[0]	LONG_V6[1]	LONG_V5[1]	LONG_V5[0]	LONG_V4[0]	LONG_V4[1]
1	0	0	1	1	QUAD_V2[4]	QUAD_V2[5]	QUAD_V2[6]	QUAD_V2[7]	QUAD_V2[8]	QUAD_V2[9]	QUAD_V2[10]	QUAD_V2[11]
1	0	1	0	1	LONG_V3[1]	LONG_V3[0]	LONG_V2[0]	LONG_V2[1]	LONG_V1[1]	LONG_V1[0]	LONG_V0[0]	LONG_V0[1]
1	0	1	1	1	QUAD_V1[1]	QUAD_V1[0]	QUAD_V1[3]	QUAD_V1[2]	QUAD_V1[5]	QUAD_V1[4]	QUAD_V1[7]	QUAD_V1[6]
1	1	0	0	1	QUAD_V3[1]	QUAD_V3[0]	QUAD_V3[3]	QUAD_V3[2]	QUAD_V3[5]	QUAD_V3[4]	QUAD_V3[7]	QUAD_V3[6]
1	1	0	1	1	QUAD_V1[9]	QUAD_V1[8]	QUAD_V1[11]	QUAD_V1[10]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	1	1	0	1	QUAD_V3[9]	QUAD_V3[8]	QUAD_V3[11]	QUAD_V3[10]	QUAD_V2[0]	QUAD_V2[1]	QUAD_V2[2]	QUAD_V2[3]
1	1	1	1	1	QUAD_V0[4]	QUAD_V0[5]	QUAD_V0[6]	QUAD_V0[7]	QUAD_V0[8]	QUAD_V0[9]	QUAD_V0[10]	QUAD_V0[11]

siliconblue IOI_S_L04 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[5][36]	MAIN[5][37]	MAIN[4][36]	MAIN[4][37]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[0]
0	0	1	1	GLOBAL[2]
0	1	0	1	GLOBAL[4]
0	1	1	1	GLOBAL[6]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_S_L04 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[11][34]	MAIN[11][35]	MAIN[10][34]	MAIN[10][35]	IMUX_IO_DOUT0[0]	-
MAIN[4][34]	MAIN[4][35]	MAIN[5][34]	MAIN[5][35]	-	IMUX_IO_DOUT0[1]
MAIN[7][33]	MAIN[7][32]	MAIN[6][32]	MAIN[6][33]	-	IMUX_IO_DOUT1[0]
MAIN[0][33]	MAIN[0][32]	MAIN[1][32]	MAIN[1][33]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_S_L04 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[11][33]	MAIN[11][32]	MAIN[10][32]	MAIN[10][33]	IMUX_IO_OE[0]	-
MAIN[4][33]	MAIN[4][32]	MAIN[5][32]	MAIN[5][33]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_S_L04 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[7][35]	MAIN[7][36]	MAIN[7][34]	MAIN[6][34]	MAIN[6][37]	IMUX_IO_ICLK	-
MAIN[0][35]	MAIN[0][36]	MAIN[0][34]	MAIN[1][34]	MAIN[1][37]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_S_L04 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[10][36]	MAIN[10][37]	MAIN[11][36]	MAIN[11][37]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_S_L04 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_S_L04 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[13][5]	MAIN[2][5]
PIN_TYPE bit 1	MAIN[13][4]	MAIN[2][4]
PIN_TYPE bit 2	MAIN[15][5]	MAIN[4][5]
PIN_TYPE bit 3	MAIN[15][4]	MAIN[4][4]
PIN_TYPE bit 4	MAIN[11][4]	MAIN[0][4]
PIN_TYPE bit 5	MAIN[11][5]	MAIN[0][5]

Bel wires

siliconblue IOI_S_L04 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_S_L04 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17	B18	B19	B20	B21	B22	B23	B24	B25	B26	B27	B28	B29	B30	B31	B32	B33	B34	B35	B36	B37	B38	B39	B40	B41
F0	-	-	-	-	IOI[1]: PIN_TYPE bit 4	IOI[1]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 3	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 3	-	-	INT: buffer QUAD_H1[3] ← OUT_LC[3]	-	INT: buffer QUAD_H2[3] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 3	-	-	-	-	-
F1	-	-	-	-	-	INT: buffer LONG_V0[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 2	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[7] bit 2	-	-	INT: buffer QUAD_V0[10] ← OUT_LC[3]	-	INT: buffer QUAD_H0[3] ← OUT_LC[3]	INT: buffer QUAD_H3[3] ← OUT_LC[3]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_OCLK bit 1	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	-	INT: mux IMUX_IO_OCLK bit 0	-	-	-	-
F2	-	-	-	-	IOI[1]: PIN_TYPE bit 1	IOI[1]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 2	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[5] bit 2	-	-	INT: buffer QUAD_V3[7] ← OUT_LC[3]	-	INT: buffer QUAD_V2[2] ← OUT_LC[3]	INT: buffer QUAD_V0[2] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux QUAD_V0[7] bit 1	INT: mux QUAD_V0[7] bit 0	INT: mux QUAD_H0[3] bit 1	INT: mux QUAD_H0[3] bit 0	-	-	-	-	-
F3	-	-	-	-	-	INT: buffer LONG_V4[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 3	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 3	-	-	INT: buffer QUAD_V2[10] ← OUT_LC[3]	-	INT: buffer QUAD_V1[7] ← OUT_LC[3]	-	-	-	-	-	-	-	INT: mux QUAD_H4[3] bit 0	INT: mux QUAD_H4[3] bit 1	INT: mux QUAD_V2[7] bit 1	INT: mux QUAD_V2[7] bit 0	-	-	-	-	-
F4	-	-	-	-	IOI[1]: PIN_TYPE bit 3	IOI[1]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 3	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 3	-	-	INT: buffer QUAD_H1[2] ← OUT_LC[2]	-	INT: buffer QUAD_H2[2] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 2	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_CE bit 1	INT: mux IMUX_CE bit 0	-	-	-	-
F5	-	-	-	-	-	INT: buffer LONG_V8[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 2	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[3] bit 2	-	-	INT: buffer QUAD_V0[8] ← OUT_LC[2]	-	INT: buffer QUAD_H0[2] ← OUT_LC[2]	INT: buffer QUAD_H3[2] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_CE bit 3	INT: mux IMUX_CE bit 2	-	-	-	-
F6	-	-	-	-	INT: buffer LONG_V9[1] ← OUT_LC[2]	INT: buffer LONG_V5[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 2	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[1] bit 2	-	-	INT: buffer QUAD_V3[5] ← OUT_LC[2]	-	INT: buffer QUAD_V2[0] ← OUT_LC[2]	INT: buffer QUAD_V0[0] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_ICLK bit 1	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	-	INT: mux IMUX_IO_ICLK bit 0	-	-	-	-
F7	-	-	-	-	INT: buffer LONG_V1[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 3	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 3	-	-	INT: buffer QUAD_V2[8] ← OUT_LC[2]	-	INT: buffer QUAD_V1[5] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 3	-	-	-	-	-
F8	-	-	-	-	INT: buffer LONG_V2[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 3	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 3	-	-	INT: buffer QUAD_H1[1] ← OUT_LC[1]	-	INT: buffer QUAD_H2[1] ← OUT_LC[1]	-	-	-	-	-	-	-	INT: mux QUAD_H4[2] bit 0	INT: mux QUAD_H4[2] bit 1	INT: mux QUAD_V2[1] bit 1	INT: mux QUAD_V2[1] bit 0	-	-	-	-	-
F9	-	-	-	-	INT: buffer LONG_V10[0] ← OUT_LC[1]	INT: buffer LONG_V6[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 2	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[7] bit 2	-	-	INT: buffer QUAD_V0[6] ← OUT_LC[1]	-	INT: buffer QUAD_H0[1] ← OUT_LC[1]	INT: buffer QUAD_H3[1] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux QUAD_V0[1] bit 1	INT: mux QUAD_V0[1] bit 0	INT: mux QUAD_H0[2] bit 1	INT: mux QUAD_H0[2] bit 0	-	-	-	-	-
F10	-	-	-	-	-	INT: buffer LONG_V3[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 2	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[5] bit 2	-	-	INT: buffer QUAD_V3[3] ← OUT_LC[1]	-	INT: buffer QUAD_V3[11] ← OUT_LC[1]	INT: buffer QUAD_V1[11] ← OUT_LC[1]	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_EXTRA bit 2	-	-	-	-
F11	-	-	-	-	IOI[0]: PIN_TYPE bit 4	IOI[0]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 3	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 3	-	-	INT: buffer QUAD_V2[6] ← OUT_LC[1]	-	INT: buffer QUAD_V1[3] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 2	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_EXTRA bit 0	-	-	-	-
F12	-	-	-	-	-	INT: buffer LONG_V7[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 3	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 3	-	-	INT: buffer QUAD_H1[0] ← OUT_LC[0]	-	INT: buffer QUAD_H2[0] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[1] bit 0	INT: mux QUAD_H4[1] bit 1	INT: mux QUAD_V3[6] bit 1	INT: mux QUAD_V3[6] bit 0	-	-	-	-	-
F13	-	-	-	-	IOI[0]: PIN_TYPE bit 1	IOI[0]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 2	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[3] bit 2	-	-	INT: buffer QUAD_V0[4] ← OUT_LC[0]	-	INT: buffer QUAD_H0[0] ← OUT_LC[0]	INT: buffer QUAD_H3[0] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V1[6] bit 1	INT: mux QUAD_V1[6] bit 0	INT: mux QUAD_H0[1] bit 1	INT: mux QUAD_H0[1] bit 0	-	-	-	-	-
F14	-	-	-	-	-	INT: buffer LONG_V11[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 2	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[1] bit 2	-	-	INT: buffer QUAD_V3[1] ← OUT_LC[0]	-	INT: buffer QUAD_V3[9] ← OUT_LC[0]	INT: buffer QUAD_V1[9] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V1[0] bit 1	INT: mux QUAD_V1[0] bit 0	INT: mux QUAD_H0[0] bit 1	INT: mux QUAD_H0[0] bit 0	-	-	-	-	-
F15	-	-	-	-	IOI[0]: PIN_TYPE bit 3	IOI[0]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 3	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 3	-	-	INT: buffer QUAD_V2[4] ← OUT_LC[0]	-	INT: buffer QUAD_V1[1] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[0] bit 0	INT: mux QUAD_H4[0] bit 1	INT: mux QUAD_V3[0] bit 1	INT: mux QUAD_V3[0] bit 0	-	-	-	-	-

Tile IOI_N_L04

Cells: 1

Switchbox INT

siliconblue IOI_N_L04 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H0[0]	OUT_LC[0]	MAIN[2][25]
QUAD_H0[1]	OUT_LC[1]	MAIN[6][25]
QUAD_H0[2]	OUT_LC[2]	MAIN[10][25]
QUAD_H0[3]	OUT_LC[3]	MAIN[14][25]
QUAD_H1[0]	OUT_LC[0]	MAIN[3][23]
QUAD_H1[1]	OUT_LC[1]	MAIN[7][23]
QUAD_H1[2]	OUT_LC[2]	MAIN[11][23]
QUAD_H1[3]	OUT_LC[3]	MAIN[15][23]
QUAD_H2[0]	OUT_LC[0]	MAIN[3][25]
QUAD_H2[1]	OUT_LC[1]	MAIN[7][25]
QUAD_H2[2]	OUT_LC[2]	MAIN[11][25]
QUAD_H2[3]	OUT_LC[3]	MAIN[15][25]
QUAD_H3[0]	OUT_LC[0]	MAIN[2][26]
QUAD_H3[1]	OUT_LC[1]	MAIN[6][26]
QUAD_H3[2]	OUT_LC[2]	MAIN[10][26]
QUAD_H3[3]	OUT_LC[3]	MAIN[14][26]
QUAD_V1[0]	OUT_LC[2]	MAIN[9][26]
QUAD_V1[2]	OUT_LC[3]	MAIN[13][26]
QUAD_V1[4]	OUT_LC[0]	MAIN[2][23]
QUAD_V1[6]	OUT_LC[1]	MAIN[6][23]
QUAD_V1[8]	OUT_LC[2]	MAIN[10][23]
QUAD_V1[10]	OUT_LC[3]	MAIN[14][23]
QUAD_V2[1]	OUT_LC[0]	MAIN[0][25]
QUAD_V2[3]	OUT_LC[1]	MAIN[4][25]
QUAD_V2[5]	OUT_LC[2]	MAIN[8][25]
QUAD_V2[7]	OUT_LC[3]	MAIN[12][25]
QUAD_V2[9]	OUT_LC[0]	MAIN[1][26]
QUAD_V2[11]	OUT_LC[1]	MAIN[5][26]
QUAD_V3[0]	OUT_LC[2]	MAIN[9][25]
QUAD_V3[2]	OUT_LC[3]	MAIN[13][25]
QUAD_V3[4]	OUT_LC[0]	MAIN[0][23]
QUAD_V3[6]	OUT_LC[1]	MAIN[4][23]
QUAD_V3[8]	OUT_LC[2]	MAIN[8][23]
QUAD_V3[10]	OUT_LC[3]	MAIN[12][23]
QUAD_V4[1]	OUT_LC[0]	MAIN[1][23]
QUAD_V4[3]	OUT_LC[1]	MAIN[5][23]
QUAD_V4[5]	OUT_LC[2]	MAIN[9][23]
QUAD_V4[7]	OUT_LC[3]	MAIN[13][23]
QUAD_V4[9]	OUT_LC[0]	MAIN[1][25]
QUAD_V4[11]	OUT_LC[1]	MAIN[5][25]
LONG_V1[0]	OUT_LC[3]	MAIN[14][5]
LONG_V2[1]	OUT_LC[2]	MAIN[8][4]
LONG_V3[0]	OUT_LC[1]	MAIN[7][4]
LONG_V4[1]	OUT_LC[0]	MAIN[5][5]
LONG_V5[0]	OUT_LC[3]	MAIN[12][5]
LONG_V6[1]	OUT_LC[2]	MAIN[9][5]
LONG_V7[0]	OUT_LC[1]	MAIN[6][5]
LONG_V8[1]	OUT_LC[0]	MAIN[3][5]
LONG_V9[0]	OUT_LC[3]	MAIN[10][5]
LONG_V10[1]	OUT_LC[2]	MAIN[9][4]
LONG_V11[0]	OUT_LC[1]	MAIN[6][4]
LONG_V12[1]	OUT_LC[0]	MAIN[1][5]

siliconblue IOI_N_L04 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[9][35]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[14][35]

siliconblue IOI_N_L04 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[1][35]	MAIN[1][36]	QUAD_H0[0]	-	-	-	-	-	-	-
MAIN[2][35]	MAIN[2][36]	-	QUAD_H0[1]	-	-	-	-	-	-
MAIN[6][35]	MAIN[6][36]	-	-	QUAD_H0[2]	-	-	-	-	-
MAIN[13][35]	MAIN[13][36]	-	-	-	QUAD_H0[3]	-	-	-	-
MAIN[0][34]	MAIN[0][33]	-	-	-	-	QUAD_H4[0]	-	-	-
MAIN[3][34]	MAIN[3][33]	-	-	-	-	-	QUAD_H4[1]	-	-
MAIN[7][34]	MAIN[7][33]	-	-	-	-	-	-	QUAD_H4[2]	-
MAIN[12][34]	MAIN[12][33]	-	-	-	-	-	-	-	QUAD_H4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H4[0]	QUAD_H4[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]
1	0	QUAD_V2[0]	QUAD_V2[6]	QUAD_V1[1]	QUAD_V1[7]	QUAD_V2[0]	QUAD_V2[6]	QUAD_V1[1]	QUAD_V1[7]
1	1	QUAD_V4[0]	QUAD_V4[6]	QUAD_V3[1]	QUAD_V3[7]	QUAD_V4[0]	QUAD_V4[6]	QUAD_V3[1]	QUAD_V3[7]

siliconblue IOI_N_L04 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[6][33]	MAIN[6][34]	QUAD_V1[1]	-	-	-	-	-	-	-
MAIN[13][33]	MAIN[13][34]	-	QUAD_V1[7]	-	-	-	-	-	-
MAIN[1][33]	MAIN[1][34]	-	-	QUAD_V2[0]	-	-	-	-	-
MAIN[2][33]	MAIN[2][34]	-	-	-	QUAD_V2[6]	-	-	-	-
MAIN[7][35]	MAIN[7][36]	-	-	-	-	QUAD_V3[1]	-	-	-
MAIN[12][35]	MAIN[12][36]	-	-	-	-	-	QUAD_V3[7]	-	-
MAIN[0][35]	MAIN[0][36]	-	-	-	-	-	-	QUAD_V4[0]	-
MAIN[3][35]	MAIN[3][36]	-	-	-	-	-	-	-	QUAD_V4[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]
1	0	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]	QUAD_V1[1]	QUAD_V1[7]	QUAD_V2[0]	QUAD_V2[6]
1	1	QUAD_V3[1]	QUAD_V3[7]	QUAD_V4[0]	QUAD_V4[6]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]

siliconblue IOI_N_L04 switchbox INT muxes LOCAL
Bits					Destination
MAIN[1][18]	MAIN[0][16]	MAIN[1][16]	MAIN[1][17]	MAIN[1][19]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[0][18]	MAIN[0][20]	MAIN[1][20]	MAIN[0][17]	MAIN[0][19]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[2][18]	MAIN[3][16]	MAIN[2][16]	MAIN[2][17]	MAIN[2][19]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[3][18]	MAIN[3][20]	MAIN[2][20]	MAIN[3][17]	MAIN[3][19]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[5][18]	MAIN[4][16]	MAIN[5][16]	MAIN[5][17]	MAIN[5][19]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[4][18]	MAIN[4][20]	MAIN[5][20]	MAIN[4][17]	MAIN[4][19]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[6][18]	MAIN[7][16]	MAIN[6][16]	MAIN[6][17]	MAIN[6][19]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[7][18]	MAIN[7][20]	MAIN[6][20]	MAIN[7][17]	MAIN[7][19]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[9][18]	MAIN[8][16]	MAIN[9][16]	MAIN[9][17]	MAIN[9][19]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[8][18]	MAIN[8][20]	MAIN[9][20]	MAIN[8][17]	MAIN[8][19]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[10][18]	MAIN[11][16]	MAIN[10][16]	MAIN[10][17]	MAIN[10][19]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[11][18]	MAIN[11][20]	MAIN[10][20]	MAIN[11][17]	MAIN[11][19]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[13][18]	MAIN[12][16]	MAIN[13][16]	MAIN[13][17]	MAIN[13][19]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[12][18]	MAIN[12][20]	MAIN[13][20]	MAIN[12][17]	MAIN[12][19]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[14][18]	MAIN[15][16]	MAIN[14][16]	MAIN[14][17]	MAIN[14][19]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[15][18]	MAIN[15][20]	MAIN[14][20]	MAIN[15][17]	MAIN[15][19]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	OUT_LC_WN[0]	OUT_LC_WN[1]	OUT_LC_WN[2]	OUT_LC_WN[3]	OUT_LC_WN[4]	OUT_LC_WN[5]	OUT_LC_WN[6]	OUT_LC_WN[7]
0	0	1	1	1	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H1[0]	QUAD_H1[1]	QUAD_H1[2]	QUAD_H1[3]
0	1	0	0	1	OUT_LC_EN[0]	OUT_LC_EN[1]	OUT_LC_EN[2]	OUT_LC_EN[3]	OUT_LC_EN[4]	OUT_LC_EN[5]	OUT_LC_EN[6]	OUT_LC_EN[7]
0	1	0	1	1	QUAD_H2[0]	QUAD_H2[1]	QUAD_H2[2]	QUAD_H2[3]	QUAD_H3[0]	QUAD_H3[1]	QUAD_H3[2]	QUAD_H3[3]
0	1	1	0	1	OUT_LC_N[0]	OUT_LC_N[1]	OUT_LC_N[2]	OUT_LC_N[3]	OUT_LC_N[4]	OUT_LC_N[5]	OUT_LC_N[6]	OUT_LC_N[7]
0	1	1	1	1	LONG_V12[1]	LONG_V12[0]	LONG_V11[0]	LONG_V11[1]	LONG_V10[1]	LONG_V10[0]	LONG_V9[0]	LONG_V9[1]
1	0	0	0	1	LONG_V8[1]	LONG_V8[0]	LONG_V7[0]	LONG_V7[1]	LONG_V6[1]	LONG_V6[0]	LONG_V5[0]	LONG_V5[1]
1	0	0	1	1	QUAD_V3[4]	QUAD_V3[5]	QUAD_V3[6]	QUAD_V3[7]	QUAD_V3[8]	QUAD_V3[9]	QUAD_V3[10]	QUAD_V3[11]
1	0	1	0	1	LONG_V4[1]	LONG_V4[0]	LONG_V3[0]	LONG_V3[1]	LONG_V2[1]	LONG_V2[0]	LONG_V1[0]	LONG_V1[1]
1	0	1	1	1	QUAD_V2[1]	QUAD_V2[0]	QUAD_V2[3]	QUAD_V2[2]	QUAD_V2[5]	QUAD_V2[4]	QUAD_V2[7]	QUAD_V2[6]
1	1	0	0	1	QUAD_V4[1]	QUAD_V4[0]	QUAD_V4[3]	QUAD_V4[2]	QUAD_V4[5]	QUAD_V4[4]	QUAD_V4[7]	QUAD_V4[6]
1	1	0	1	1	QUAD_V2[9]	QUAD_V2[8]	QUAD_V2[11]	QUAD_V2[10]	QUAD_V1[0]	QUAD_V1[1]	QUAD_V1[2]	QUAD_V1[3]
1	1	1	0	1	QUAD_V4[9]	QUAD_V4[8]	QUAD_V4[11]	QUAD_V4[10]	QUAD_V3[0]	QUAD_V3[1]	QUAD_V3[2]	QUAD_V3[3]
1	1	1	1	1	QUAD_V1[4]	QUAD_V1[5]	QUAD_V1[6]	QUAD_V1[7]	QUAD_V1[8]	QUAD_V1[9]	QUAD_V1[10]	QUAD_V1[11]

siliconblue IOI_N_L04 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[10][36]	MAIN[10][37]	MAIN[11][36]	MAIN[11][37]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[0]
0	0	1	1	GLOBAL[2]
0	1	0	1	GLOBAL[4]
0	1	1	1	GLOBAL[6]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_N_L04 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[4][34]	MAIN[4][35]	MAIN[5][34]	MAIN[5][35]	IMUX_IO_DOUT0[0]	-
MAIN[11][34]	MAIN[11][35]	MAIN[10][34]	MAIN[10][35]	-	IMUX_IO_DOUT0[1]
MAIN[8][33]	MAIN[8][32]	MAIN[9][32]	MAIN[9][33]	-	IMUX_IO_DOUT1[0]
MAIN[15][33]	MAIN[15][32]	MAIN[14][32]	MAIN[14][33]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_N_L04 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[4][33]	MAIN[4][32]	MAIN[5][32]	MAIN[5][33]	IMUX_IO_OE[0]	-
MAIN[11][33]	MAIN[11][32]	MAIN[10][32]	MAIN[10][33]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_N_L04 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[8][35]	MAIN[8][36]	MAIN[8][34]	MAIN[9][34]	MAIN[9][37]	IMUX_IO_ICLK	-
MAIN[15][35]	MAIN[15][36]	MAIN[15][34]	MAIN[14][34]	MAIN[14][37]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_N_L04 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[5][36]	MAIN[5][37]	MAIN[4][36]	MAIN[4][37]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_N_L04 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_N_L04 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[2][5]	MAIN[13][5]
PIN_TYPE bit 1	MAIN[2][4]	MAIN[13][4]
PIN_TYPE bit 2	MAIN[0][5]	MAIN[11][5]
PIN_TYPE bit 3	MAIN[0][4]	MAIN[11][4]
PIN_TYPE bit 4	MAIN[4][4]	MAIN[15][4]
PIN_TYPE bit 5	MAIN[4][5]	MAIN[15][5]

Bel wires

siliconblue IOI_N_L04 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_N_L04 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17	B18	B19	B20	B21	B22	B23	B24	B25	B26	B27	B28	B29	B30	B31	B32	B33	B34	B35	B36	B37	B38	B39	B40	B41
F0	-	-	-	-	IOI[0]: PIN_TYPE bit 3	IOI[0]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 3	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 3	-	-	INT: buffer QUAD_V3[4] ← OUT_LC[0]	-	INT: buffer QUAD_V2[1] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[0] bit 0	INT: mux QUAD_H4[0] bit 1	INT: mux QUAD_V4[0] bit 1	INT: mux QUAD_V4[0] bit 0	-	-	-	-	-
F1	-	-	-	-	-	INT: buffer LONG_V12[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 2	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[1] bit 2	-	-	INT: buffer QUAD_V4[1] ← OUT_LC[0]	-	INT: buffer QUAD_V4[9] ← OUT_LC[0]	INT: buffer QUAD_V2[9] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V2[0] bit 1	INT: mux QUAD_V2[0] bit 0	INT: mux QUAD_H0[0] bit 1	INT: mux QUAD_H0[0] bit 0	-	-	-	-	-
F2	-	-	-	-	IOI[0]: PIN_TYPE bit 1	IOI[0]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 2	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[3] bit 2	-	-	INT: buffer QUAD_V1[4] ← OUT_LC[0]	-	INT: buffer QUAD_H0[0] ← OUT_LC[0]	INT: buffer QUAD_H3[0] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V2[6] bit 1	INT: mux QUAD_V2[6] bit 0	INT: mux QUAD_H0[1] bit 1	INT: mux QUAD_H0[1] bit 0	-	-	-	-	-
F3	-	-	-	-	-	INT: buffer LONG_V8[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 3	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 3	-	-	INT: buffer QUAD_H1[0] ← OUT_LC[0]	-	INT: buffer QUAD_H2[0] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[1] bit 0	INT: mux QUAD_H4[1] bit 1	INT: mux QUAD_V4[6] bit 1	INT: mux QUAD_V4[6] bit 0	-	-	-	-	-
F4	-	-	-	-	IOI[0]: PIN_TYPE bit 4	IOI[0]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 3	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 3	-	-	INT: buffer QUAD_V3[6] ← OUT_LC[1]	-	INT: buffer QUAD_V2[3] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 2	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_EXTRA bit 0	-	-	-	-
F5	-	-	-	-	-	INT: buffer LONG_V4[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 2	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[5] bit 2	-	-	INT: buffer QUAD_V4[3] ← OUT_LC[1]	-	INT: buffer QUAD_V4[11] ← OUT_LC[1]	INT: buffer QUAD_V2[11] ← OUT_LC[1]	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_EXTRA bit 2	-	-	-	-
F6	-	-	-	-	INT: buffer LONG_V11[0] ← OUT_LC[1]	INT: buffer LONG_V7[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 2	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[7] bit 2	-	-	INT: buffer QUAD_V1[6] ← OUT_LC[1]	-	INT: buffer QUAD_H0[1] ← OUT_LC[1]	INT: buffer QUAD_H3[1] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux QUAD_V1[1] bit 1	INT: mux QUAD_V1[1] bit 0	INT: mux QUAD_H0[2] bit 1	INT: mux QUAD_H0[2] bit 0	-	-	-	-	-
F7	-	-	-	-	INT: buffer LONG_V3[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 3	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 3	-	-	INT: buffer QUAD_H1[1] ← OUT_LC[1]	-	INT: buffer QUAD_H2[1] ← OUT_LC[1]	-	-	-	-	-	-	-	INT: mux QUAD_H4[2] bit 0	INT: mux QUAD_H4[2] bit 1	INT: mux QUAD_V3[1] bit 1	INT: mux QUAD_V3[1] bit 0	-	-	-	-	-
F8	-	-	-	-	INT: buffer LONG_V2[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 3	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 3	-	-	INT: buffer QUAD_V3[8] ← OUT_LC[2]	-	INT: buffer QUAD_V2[5] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 3	-	-	-	-	-
F9	-	-	-	-	INT: buffer LONG_V10[1] ← OUT_LC[2]	INT: buffer LONG_V6[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 2	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[1] bit 2	-	-	INT: buffer QUAD_V4[5] ← OUT_LC[2]	-	INT: buffer QUAD_V3[0] ← OUT_LC[2]	INT: buffer QUAD_V1[0] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_ICLK bit 1	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	-	INT: mux IMUX_IO_ICLK bit 0	-	-	-	-
F10	-	-	-	-	-	INT: buffer LONG_V9[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 2	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[3] bit 2	-	-	INT: buffer QUAD_V1[8] ← OUT_LC[2]	-	INT: buffer QUAD_H0[2] ← OUT_LC[2]	INT: buffer QUAD_H3[2] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_CE bit 3	INT: mux IMUX_CE bit 2	-	-	-	-
F11	-	-	-	-	IOI[1]: PIN_TYPE bit 3	IOI[1]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 3	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 3	-	-	INT: buffer QUAD_H1[2] ← OUT_LC[2]	-	INT: buffer QUAD_H2[2] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 2	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_CE bit 1	INT: mux IMUX_CE bit 0	-	-	-	-
F12	-	-	-	-	-	INT: buffer LONG_V5[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 3	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 3	-	-	INT: buffer QUAD_V3[10] ← OUT_LC[3]	-	INT: buffer QUAD_V2[7] ← OUT_LC[3]	-	-	-	-	-	-	-	INT: mux QUAD_H4[3] bit 0	INT: mux QUAD_H4[3] bit 1	INT: mux QUAD_V3[7] bit 1	INT: mux QUAD_V3[7] bit 0	-	-	-	-	-
F13	-	-	-	-	IOI[1]: PIN_TYPE bit 1	IOI[1]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 2	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[5] bit 2	-	-	INT: buffer QUAD_V4[7] ← OUT_LC[3]	-	INT: buffer QUAD_V3[2] ← OUT_LC[3]	INT: buffer QUAD_V1[2] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux QUAD_V1[7] bit 1	INT: mux QUAD_V1[7] bit 0	INT: mux QUAD_H0[3] bit 1	INT: mux QUAD_H0[3] bit 0	-	-	-	-	-
F14	-	-	-	-	-	INT: buffer LONG_V1[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 2	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[7] bit 2	-	-	INT: buffer QUAD_V1[10] ← OUT_LC[3]	-	INT: buffer QUAD_H0[3] ← OUT_LC[3]	INT: buffer QUAD_H3[3] ← OUT_LC[3]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_OCLK bit 1	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	-	INT: mux IMUX_IO_OCLK bit 0	-	-	-	-
F15	-	-	-	-	IOI[1]: PIN_TYPE bit 4	IOI[1]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 3	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 3	-	-	INT: buffer QUAD_H1[3] ← OUT_LC[3]	-	INT: buffer QUAD_H2[3] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 3	-	-	-	-	-

Tile IOI_W_L08

Cells: 1

Switchbox INT

siliconblue IOI_W_L08 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H0[0]	OUT_LC[0]	MAIN[1][17]
QUAD_H0[2]	OUT_LC[1]	MAIN[5][17]
QUAD_H0[4]	OUT_LC[2]	MAIN[9][17]
QUAD_H0[6]	OUT_LC[3]	MAIN[13][17]
QUAD_H0[8]	OUT_LC[0]	MAIN[1][16]
QUAD_H0[10]	OUT_LC[1]	MAIN[5][16]
QUAD_H1[1]	OUT_LC[2]	MAIN[9][16]
QUAD_H1[3]	OUT_LC[3]	MAIN[13][16]
QUAD_H1[5]	OUT_LC[0]	MAIN[0][17]
QUAD_H1[7]	OUT_LC[1]	MAIN[4][17]
QUAD_H1[9]	OUT_LC[2]	MAIN[8][17]
QUAD_H1[11]	OUT_LC[3]	MAIN[12][17]
QUAD_H2[0]	OUT_LC[0]	MAIN[0][16]
QUAD_H2[2]	OUT_LC[1]	MAIN[4][16]
QUAD_H2[4]	OUT_LC[2]	MAIN[8][16]
QUAD_H2[6]	OUT_LC[3]	MAIN[12][16]
QUAD_H2[8]	OUT_LC[0]	MAIN[1][15]
QUAD_H2[10]	OUT_LC[1]	MAIN[5][15]
QUAD_H3[1]	OUT_LC[2]	MAIN[9][15]
QUAD_H3[3]	OUT_LC[3]	MAIN[13][15]
QUAD_H3[5]	OUT_LC[0]	MAIN[3][17]
QUAD_H3[7]	OUT_LC[1]	MAIN[7][17]
QUAD_H3[9]	OUT_LC[2]	MAIN[11][17]
QUAD_H3[11]	OUT_LC[3]	MAIN[15][17]
QUAD_V1[0]	OUT_LC[0]	MAIN[3][15]
QUAD_V1[1]	OUT_LC[1]	MAIN[7][15]
QUAD_V1[2]	OUT_LC[2]	MAIN[11][15]
QUAD_V1[3]	OUT_LC[3]	MAIN[15][15]
QUAD_V2[0]	OUT_LC[0]	MAIN[2][16]
QUAD_V2[1]	OUT_LC[1]	MAIN[6][16]
QUAD_V2[2]	OUT_LC[2]	MAIN[10][16]
QUAD_V2[3]	OUT_LC[3]	MAIN[14][16]
QUAD_V3[0]	OUT_LC[0]	MAIN[2][17]
QUAD_V3[1]	OUT_LC[1]	MAIN[6][17]
QUAD_V3[2]	OUT_LC[2]	MAIN[10][17]
QUAD_V3[3]	OUT_LC[3]	MAIN[14][17]
QUAD_V4[0]	OUT_LC[0]	MAIN[3][16]
QUAD_V4[1]	OUT_LC[1]	MAIN[7][16]
QUAD_V4[2]	OUT_LC[2]	MAIN[11][16]
QUAD_V4[3]	OUT_LC[3]	MAIN[15][16]
LONG_H0[0]	OUT_LC[0]	MAIN[1][0]
LONG_H1[1]	OUT_LC[1]	MAIN[7][1]
LONG_H2[0]	OUT_LC[2]	MAIN[9][1]
LONG_H3[1]	OUT_LC[3]	MAIN[11][0]
LONG_H4[0]	OUT_LC[0]	MAIN[2][0]
LONG_H5[1]	OUT_LC[1]	MAIN[7][0]
LONG_H6[0]	OUT_LC[2]	MAIN[9][0]
LONG_H7[1]	OUT_LC[3]	MAIN[12][0]
LONG_H8[0]	OUT_LC[0]	MAIN[5][0]
LONG_H9[1]	OUT_LC[1]	MAIN[6][1]
LONG_H10[0]	OUT_LC[2]	MAIN[8][1]
LONG_H11[1]	OUT_LC[3]	MAIN[15][0]

siliconblue IOI_W_L08 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[9][4]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[15][4]

siliconblue IOI_W_L08 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[0][3]	MAIN[0][4]	QUAD_H0[1]	-	-	-	-	-	-	-
MAIN[2][3]	MAIN[2][4]	-	QUAD_H0[7]	-	-	-	-	-	-
MAIN[6][3]	MAIN[6][4]	-	-	QUAD_H1[0]	-	-	-	-	-
MAIN[12][3]	MAIN[12][4]	-	-	-	QUAD_H1[6]	-	-	-	-
MAIN[1][5]	MAIN[1][6]	-	-	-	-	QUAD_H2[1]	-	-	-
MAIN[3][5]	MAIN[3][6]	-	-	-	-	-	QUAD_H2[7]	-	-
MAIN[7][5]	MAIN[7][6]	-	-	-	-	-	-	QUAD_H3[0]	-
MAIN[13][5]	MAIN[13][6]	-	-	-	-	-	-	-	QUAD_H3[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H2[1]	QUAD_H2[7]	QUAD_H3[0]	QUAD_H3[6]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	0	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]
1	1	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_H0[1]	QUAD_H0[7]	QUAD_H1[0]	QUAD_H1[6]

siliconblue IOI_W_L08 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[0][6]	MAIN[0][5]	QUAD_V0[0]	-	-	-	-	-	-	-
MAIN[2][6]	MAIN[2][5]	-	QUAD_V0[1]	-	-	-	-	-	-
MAIN[6][6]	MAIN[6][5]	-	-	QUAD_V0[2]	-	-	-	-	-
MAIN[12][6]	MAIN[12][5]	-	-	-	QUAD_V0[3]	-	-	-	-
MAIN[1][3]	MAIN[1][4]	-	-	-	-	QUAD_V4[0]	-	-	-
MAIN[3][3]	MAIN[3][4]	-	-	-	-	-	QUAD_V4[1]	-	-
MAIN[7][3]	MAIN[7][4]	-	-	-	-	-	-	QUAD_V4[2]	-
MAIN[13][3]	MAIN[13][4]	-	-	-	-	-	-	-	QUAD_V4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H2[1]	QUAD_H2[7]	QUAD_H3[0]	QUAD_H3[6]	QUAD_H2[1]	QUAD_H2[7]	QUAD_H3[0]	QUAD_H3[6]
1	0	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	1	QUAD_H0[1]	QUAD_H0[7]	QUAD_H1[0]	QUAD_H1[6]	QUAD_H0[1]	QUAD_H0[7]	QUAD_H1[0]	QUAD_H1[6]

siliconblue IOI_W_L08 switchbox INT muxes LOCAL
Bits					Destination
MAIN[1][12]	MAIN[1][13]	MAIN[0][13]	MAIN[1][11]	MAIN[1][10]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[0][12]	MAIN[1][9]	MAIN[0][9]	MAIN[0][11]	MAIN[0][10]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[3][12]	MAIN[3][13]	MAIN[2][13]	MAIN[3][11]	MAIN[3][10]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[2][12]	MAIN[3][9]	MAIN[2][9]	MAIN[2][11]	MAIN[2][10]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[5][12]	MAIN[5][13]	MAIN[4][13]	MAIN[5][11]	MAIN[5][10]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[4][12]	MAIN[5][9]	MAIN[4][9]	MAIN[4][11]	MAIN[4][10]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[7][12]	MAIN[7][13]	MAIN[6][13]	MAIN[7][11]	MAIN[7][10]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[6][12]	MAIN[7][9]	MAIN[6][9]	MAIN[6][11]	MAIN[6][10]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[9][12]	MAIN[9][13]	MAIN[8][13]	MAIN[9][11]	MAIN[9][10]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[8][12]	MAIN[9][9]	MAIN[8][9]	MAIN[8][11]	MAIN[8][10]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[11][12]	MAIN[11][13]	MAIN[10][13]	MAIN[11][11]	MAIN[11][10]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[10][12]	MAIN[11][9]	MAIN[10][9]	MAIN[10][11]	MAIN[10][10]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[13][12]	MAIN[13][13]	MAIN[12][13]	MAIN[13][11]	MAIN[13][10]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[12][12]	MAIN[13][9]	MAIN[12][9]	MAIN[12][11]	MAIN[12][10]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[15][12]	MAIN[15][13]	MAIN[14][13]	MAIN[15][11]	MAIN[15][10]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[14][12]	MAIN[15][9]	MAIN[14][9]	MAIN[14][11]	MAIN[14][10]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	LONG_H4[0]	LONG_H4[1]	LONG_H5[1]	LONG_H5[0]	LONG_H6[0]	LONG_H6[1]	LONG_H7[1]	LONG_H7[0]
0	0	1	0	1	OUT_LC_WS[0]	OUT_LC_WS[1]	OUT_LC_WS[2]	OUT_LC_WS[3]	OUT_LC_WS[4]	OUT_LC_WS[5]	OUT_LC_WS[6]	OUT_LC_WS[7]
0	0	1	1	1	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[4]	QUAD_H0[5]	QUAD_H0[6]	QUAD_H0[7]
0	1	0	1	1	LONG_H8[0]	LONG_H8[1]	LONG_H9[1]	LONG_H9[0]	LONG_H10[0]	LONG_H10[1]	LONG_H11[1]	LONG_H11[0]
0	1	1	0	1	OUT_LC_W[0]	OUT_LC_W[1]	OUT_LC_W[2]	OUT_LC_W[3]	OUT_LC_W[4]	OUT_LC_W[5]	OUT_LC_W[6]	OUT_LC_W[7]
0	1	1	1	1	QUAD_H0[8]	QUAD_H0[9]	QUAD_H0[10]	QUAD_H0[11]	QUAD_H1[1]	QUAD_H1[0]	QUAD_H1[3]	QUAD_H1[2]
1	0	0	0	1	OUT_LC_WN[0]	OUT_LC_WN[1]	OUT_LC_WN[2]	OUT_LC_WN[3]	OUT_LC_WN[4]	OUT_LC_WN[5]	OUT_LC_WN[6]	OUT_LC_WN[7]
1	0	0	1	1	QUAD_H1[5]	QUAD_H1[4]	QUAD_H1[7]	QUAD_H1[6]	QUAD_H1[9]	QUAD_H1[8]	QUAD_H1[11]	QUAD_H1[10]
1	0	1	0	1	QUAD_V2[0]	QUAD_V2[1]	QUAD_V2[2]	QUAD_V2[3]	QUAD_V1[0]	QUAD_V1[1]	QUAD_V1[2]	QUAD_V1[3]
1	0	1	1	1	QUAD_H2[8]	QUAD_H2[9]	QUAD_H2[10]	QUAD_H2[11]	QUAD_H3[1]	QUAD_H3[0]	QUAD_H3[3]	QUAD_H3[2]
1	1	0	0	1	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_V3[0]	QUAD_V3[1]	QUAD_V3[2]	QUAD_V3[3]
1	1	0	1	1	QUAD_H2[0]	QUAD_H2[1]	QUAD_H2[2]	QUAD_H2[3]	QUAD_H2[4]	QUAD_H2[5]	QUAD_H2[6]	QUAD_H2[7]
1	1	1	0	1	LONG_H0[0]	LONG_H0[1]	LONG_H1[1]	LONG_H1[0]	LONG_H2[0]	LONG_H2[1]	LONG_H3[1]	LONG_H3[0]
1	1	1	1	1	QUAD_H3[5]	QUAD_H3[4]	QUAD_H3[7]	QUAD_H3[6]	QUAD_H3[9]	QUAD_H3[8]	QUAD_H3[11]	QUAD_H3[10]

siliconblue IOI_W_L08 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[11][3]	MAIN[11][2]	MAIN[10][3]	MAIN[10][2]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[1]
0	0	1	1	GLOBAL[3]
0	1	0	1	GLOBAL[5]
0	1	1	1	GLOBAL[7]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_W_L08 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[4][5]	MAIN[4][4]	MAIN[5][5]	MAIN[5][4]	IMUX_IO_DOUT0[0]	-
MAIN[10][5]	MAIN[10][4]	MAIN[11][5]	MAIN[11][4]	-	IMUX_IO_DOUT0[1]
MAIN[8][6]	MAIN[8][7]	MAIN[9][7]	MAIN[9][6]	-	IMUX_IO_DOUT1[0]
MAIN[14][6]	MAIN[14][7]	MAIN[15][7]	MAIN[15][6]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_W_L08 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[4][6]	MAIN[4][7]	MAIN[5][7]	MAIN[5][6]	IMUX_IO_OE[0]	-
MAIN[10][6]	MAIN[10][7]	MAIN[11][7]	MAIN[11][6]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_W_L08 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[8][4]	MAIN[8][3]	MAIN[8][5]	MAIN[9][5]	MAIN[9][2]	IMUX_IO_ICLK	-
MAIN[14][4]	MAIN[14][3]	MAIN[14][5]	MAIN[15][5]	MAIN[15][2]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_W_L08 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[5][3]	MAIN[5][2]	MAIN[4][3]	MAIN[4][2]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_W_L08 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_W_L08 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[3][0]	MAIN[13][0]
PIN_TYPE bit 1	MAIN[3][1]	MAIN[13][1]
PIN_TYPE bit 2	MAIN[0][0]	MAIN[10][0]
PIN_TYPE bit 3	MAIN[0][1]	MAIN[10][1]
PIN_TYPE bit 4	MAIN[4][1]	MAIN[14][1]
PIN_TYPE bit 5	MAIN[4][0]	MAIN[14][0]

Bel wires

siliconblue IOI_W_L08 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_W_L08 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17
F0	IOI[0]: PIN_TYPE bit 2	IOI[0]: PIN_TYPE bit 3	-	INT: mux QUAD_H0[1] bit 1	INT: mux QUAD_H0[1] bit 0	INT: mux QUAD_V0[0] bit 0	INT: mux QUAD_V0[0] bit 1	-	-	INT: mux LOCAL_0[1] bit 2	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[0] bit 2	-	-	INT: buffer QUAD_H2[0] ← OUT_LC[0]	INT: buffer QUAD_H1[5] ← OUT_LC[0]
F1	INT: buffer LONG_H0[0] ← OUT_LC[0]	-	-	INT: mux QUAD_V4[0] bit 1	INT: mux QUAD_V4[0] bit 0	INT: mux QUAD_H2[1] bit 1	INT: mux QUAD_H2[1] bit 0	-	-	INT: mux LOCAL_0[1] bit 3	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 3	-	INT: buffer QUAD_H2[8] ← OUT_LC[0]	INT: buffer QUAD_H0[8] ← OUT_LC[0]	INT: buffer QUAD_H0[0] ← OUT_LC[0]
F2	INT: buffer LONG_H4[0] ← OUT_LC[0]	-	-	INT: mux QUAD_H0[7] bit 1	INT: mux QUAD_H0[7] bit 0	INT: mux QUAD_V0[1] bit 0	INT: mux QUAD_V0[1] bit 1	-	-	INT: mux LOCAL_0[3] bit 2	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[2] bit 2	-	-	INT: buffer QUAD_V2[0] ← OUT_LC[0]	INT: buffer QUAD_V3[0] ← OUT_LC[0]
F3	IOI[0]: PIN_TYPE bit 0	IOI[0]: PIN_TYPE bit 1	-	INT: mux QUAD_V4[1] bit 1	INT: mux QUAD_V4[1] bit 0	INT: mux QUAD_H2[7] bit 1	INT: mux QUAD_H2[7] bit 0	-	-	INT: mux LOCAL_0[3] bit 3	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 3	-	INT: buffer QUAD_V1[0] ← OUT_LC[0]	INT: buffer QUAD_V4[0] ← OUT_LC[0]	INT: buffer QUAD_H3[5] ← OUT_LC[0]
F4	IOI[0]: PIN_TYPE bit 5	IOI[0]: PIN_TYPE bit 4	INT: mux IMUX_IO_EXTRA bit 0	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_OE[0] bit 2	-	INT: mux LOCAL_0[5] bit 2	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[4] bit 2	-	-	INT: buffer QUAD_H2[2] ← OUT_LC[1]	INT: buffer QUAD_H1[7] ← OUT_LC[1]
F5	INT: buffer LONG_H8[0] ← OUT_LC[0]	-	INT: mux IMUX_IO_EXTRA bit 2	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_OE[0] bit 1	-	INT: mux LOCAL_0[5] bit 3	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 3	-	INT: buffer QUAD_H2[10] ← OUT_LC[1]	INT: buffer QUAD_H0[10] ← OUT_LC[1]	INT: buffer QUAD_H0[2] ← OUT_LC[1]
F6	-	INT: buffer LONG_H9[1] ← OUT_LC[1]	-	INT: mux QUAD_H1[0] bit 1	INT: mux QUAD_H1[0] bit 0	INT: mux QUAD_V0[2] bit 0	INT: mux QUAD_V0[2] bit 1	-	-	INT: mux LOCAL_0[7] bit 2	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[6] bit 2	-	-	INT: buffer QUAD_V2[1] ← OUT_LC[1]	INT: buffer QUAD_V3[1] ← OUT_LC[1]
F7	INT: buffer LONG_H5[1] ← OUT_LC[1]	INT: buffer LONG_H1[1] ← OUT_LC[1]	-	INT: mux QUAD_V4[2] bit 1	INT: mux QUAD_V4[2] bit 0	INT: mux QUAD_H3[0] bit 1	INT: mux QUAD_H3[0] bit 0	-	-	INT: mux LOCAL_0[7] bit 3	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 3	-	INT: buffer QUAD_V1[1] ← OUT_LC[1]	INT: buffer QUAD_V4[1] ← OUT_LC[1]	INT: buffer QUAD_H3[7] ← OUT_LC[1]
F8	-	INT: buffer LONG_H10[0] ← OUT_LC[2]	-	INT: mux IMUX_IO_ICLK bit 3	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_DOUT1[0] bit 2	-	INT: mux LOCAL_1[1] bit 2	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[0] bit 2	-	-	INT: buffer QUAD_H2[4] ← OUT_LC[2]	INT: buffer QUAD_H1[9] ← OUT_LC[2]
F9	INT: buffer LONG_H6[0] ← OUT_LC[2]	INT: buffer LONG_H2[0] ← OUT_LC[2]	INT: mux IMUX_IO_ICLK bit 0	-	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	INT: mux IMUX_IO_ICLK bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_DOUT1[0] bit 1	-	INT: mux LOCAL_1[1] bit 3	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 3	-	INT: buffer QUAD_H3[1] ← OUT_LC[2]	INT: buffer QUAD_H1[1] ← OUT_LC[2]	INT: buffer QUAD_H0[4] ← OUT_LC[2]
F10	IOI[1]: PIN_TYPE bit 2	IOI[1]: PIN_TYPE bit 3	INT: mux IMUX_CE bit 0	INT: mux IMUX_CE bit 1	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_OE[1] bit 2	-	INT: mux LOCAL_1[3] bit 2	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[2] bit 2	-	-	INT: buffer QUAD_V2[2] ← OUT_LC[2]	INT: buffer QUAD_V3[2] ← OUT_LC[2]
F11	INT: buffer LONG_H3[1] ← OUT_LC[3]	-	INT: mux IMUX_CE bit 2	INT: mux IMUX_CE bit 3	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_OE[1] bit 1	-	INT: mux LOCAL_1[3] bit 3	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 3	-	INT: buffer QUAD_V1[2] ← OUT_LC[2]	INT: buffer QUAD_V4[2] ← OUT_LC[2]	INT: buffer QUAD_H3[9] ← OUT_LC[2]
F12	INT: buffer LONG_H7[1] ← OUT_LC[3]	-	-	INT: mux QUAD_H1[6] bit 1	INT: mux QUAD_H1[6] bit 0	INT: mux QUAD_V0[3] bit 0	INT: mux QUAD_V0[3] bit 1	-	-	INT: mux LOCAL_1[5] bit 2	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[4] bit 2	-	-	INT: buffer QUAD_H2[6] ← OUT_LC[3]	INT: buffer QUAD_H1[11] ← OUT_LC[3]
F13	IOI[1]: PIN_TYPE bit 0	IOI[1]: PIN_TYPE bit 1	-	INT: mux QUAD_V4[3] bit 1	INT: mux QUAD_V4[3] bit 0	INT: mux QUAD_H3[6] bit 1	INT: mux QUAD_H3[6] bit 0	-	-	INT: mux LOCAL_1[5] bit 3	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 3	-	INT: buffer QUAD_H3[3] ← OUT_LC[3]	INT: buffer QUAD_H1[3] ← OUT_LC[3]	INT: buffer QUAD_H0[6] ← OUT_LC[3]
F14	IOI[1]: PIN_TYPE bit 5	IOI[1]: PIN_TYPE bit 4	-	INT: mux IMUX_IO_OCLK bit 3	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_DOUT1[1] bit 2	-	INT: mux LOCAL_1[7] bit 2	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[6] bit 2	-	-	INT: buffer QUAD_V2[3] ← OUT_LC[3]	INT: buffer QUAD_V3[3] ← OUT_LC[3]
F15	INT: buffer LONG_H11[1] ← OUT_LC[3]	-	INT: mux IMUX_IO_OCLK bit 0	-	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	INT: mux IMUX_IO_OCLK bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_DOUT1[1] bit 1	-	INT: mux LOCAL_1[7] bit 3	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 3	-	INT: buffer QUAD_V1[3] ← OUT_LC[3]	INT: buffer QUAD_V4[3] ← OUT_LC[3]	INT: buffer QUAD_H3[11] ← OUT_LC[3]

Tile IOI_E_L08

Cells: 1

Switchbox INT

siliconblue IOI_E_L08 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H1[0]	OUT_LC[0]	MAIN[1][0]
QUAD_H1[2]	OUT_LC[1]	MAIN[5][0]
QUAD_H1[4]	OUT_LC[2]	MAIN[9][0]
QUAD_H1[6]	OUT_LC[3]	MAIN[13][0]
QUAD_H1[8]	OUT_LC[0]	MAIN[1][1]
QUAD_H1[10]	OUT_LC[1]	MAIN[5][1]
QUAD_H2[1]	OUT_LC[2]	MAIN[9][1]
QUAD_H2[3]	OUT_LC[3]	MAIN[13][1]
QUAD_H2[5]	OUT_LC[0]	MAIN[0][0]
QUAD_H2[7]	OUT_LC[1]	MAIN[4][0]
QUAD_H2[9]	OUT_LC[2]	MAIN[8][0]
QUAD_H2[11]	OUT_LC[3]	MAIN[12][0]
QUAD_H3[0]	OUT_LC[0]	MAIN[0][1]
QUAD_H3[2]	OUT_LC[1]	MAIN[4][1]
QUAD_H3[4]	OUT_LC[2]	MAIN[8][1]
QUAD_H3[6]	OUT_LC[3]	MAIN[12][1]
QUAD_H3[8]	OUT_LC[0]	MAIN[1][2]
QUAD_H3[10]	OUT_LC[1]	MAIN[5][2]
QUAD_H4[1]	OUT_LC[2]	MAIN[9][2]
QUAD_H4[3]	OUT_LC[3]	MAIN[13][2]
QUAD_H4[5]	OUT_LC[0]	MAIN[3][0]
QUAD_H4[7]	OUT_LC[1]	MAIN[7][0]
QUAD_H4[9]	OUT_LC[2]	MAIN[11][0]
QUAD_H4[11]	OUT_LC[3]	MAIN[15][0]
QUAD_V1[0]	OUT_LC[0]	MAIN[3][2]
QUAD_V1[1]	OUT_LC[1]	MAIN[7][2]
QUAD_V1[2]	OUT_LC[2]	MAIN[11][2]
QUAD_V1[3]	OUT_LC[3]	MAIN[15][2]
QUAD_V2[0]	OUT_LC[0]	MAIN[2][1]
QUAD_V2[1]	OUT_LC[1]	MAIN[6][1]
QUAD_V2[2]	OUT_LC[2]	MAIN[10][1]
QUAD_V2[3]	OUT_LC[3]	MAIN[14][1]
QUAD_V3[0]	OUT_LC[0]	MAIN[2][0]
QUAD_V3[1]	OUT_LC[1]	MAIN[6][0]
QUAD_V3[2]	OUT_LC[2]	MAIN[10][0]
QUAD_V3[3]	OUT_LC[3]	MAIN[14][0]
QUAD_V4[0]	OUT_LC[0]	MAIN[3][1]
QUAD_V4[1]	OUT_LC[1]	MAIN[7][1]
QUAD_V4[2]	OUT_LC[2]	MAIN[11][1]
QUAD_V4[3]	OUT_LC[3]	MAIN[15][1]
LONG_H1[0]	OUT_LC[0]	MAIN[1][17]
LONG_H2[1]	OUT_LC[1]	MAIN[7][16]
LONG_H3[0]	OUT_LC[2]	MAIN[9][16]
LONG_H4[1]	OUT_LC[3]	MAIN[11][17]
LONG_H5[0]	OUT_LC[0]	MAIN[2][17]
LONG_H6[1]	OUT_LC[1]	MAIN[7][17]
LONG_H7[0]	OUT_LC[2]	MAIN[9][17]
LONG_H8[1]	OUT_LC[3]	MAIN[12][17]
LONG_H9[0]	OUT_LC[0]	MAIN[5][17]
LONG_H10[1]	OUT_LC[1]	MAIN[6][16]
LONG_H11[0]	OUT_LC[2]	MAIN[8][16]
LONG_H12[1]	OUT_LC[3]	MAIN[15][17]

siliconblue IOI_E_L08 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[9][13]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[15][13]

siliconblue IOI_E_L08 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[0][14]	MAIN[0][13]	QUAD_H1[1]	-	-	-	-	-	-	-
MAIN[2][14]	MAIN[2][13]	-	QUAD_H1[7]	-	-	-	-	-	-
MAIN[6][14]	MAIN[6][13]	-	-	QUAD_H2[0]	-	-	-	-	-
MAIN[12][14]	MAIN[12][13]	-	-	-	QUAD_H2[6]	-	-	-	-
MAIN[1][12]	MAIN[1][11]	-	-	-	-	QUAD_H3[1]	-	-	-
MAIN[3][12]	MAIN[3][11]	-	-	-	-	-	QUAD_H3[7]	-	-
MAIN[7][12]	MAIN[7][11]	-	-	-	-	-	-	QUAD_H4[0]	-
MAIN[13][12]	MAIN[13][11]	-	-	-	-	-	-	-	QUAD_H4[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H3[1]	QUAD_H3[7]	QUAD_H4[0]	QUAD_H4[6]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	0	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]
1	1	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_H1[1]	QUAD_H1[7]	QUAD_H2[0]	QUAD_H2[6]

siliconblue IOI_E_L08 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[0][11]	MAIN[0][12]	QUAD_V0[0]	-	-	-	-	-	-	-
MAIN[2][11]	MAIN[2][12]	-	QUAD_V0[1]	-	-	-	-	-	-
MAIN[6][11]	MAIN[6][12]	-	-	QUAD_V0[2]	-	-	-	-	-
MAIN[12][11]	MAIN[12][12]	-	-	-	QUAD_V0[3]	-	-	-	-
MAIN[1][14]	MAIN[1][13]	-	-	-	-	QUAD_V4[0]	-	-	-
MAIN[3][14]	MAIN[3][13]	-	-	-	-	-	QUAD_V4[1]	-	-
MAIN[7][14]	MAIN[7][13]	-	-	-	-	-	-	QUAD_V4[2]	-
MAIN[13][14]	MAIN[13][13]	-	-	-	-	-	-	-	QUAD_V4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H3[1]	QUAD_H3[7]	QUAD_H4[0]	QUAD_H4[6]	QUAD_H3[1]	QUAD_H3[7]	QUAD_H4[0]	QUAD_H4[6]
1	0	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	1	QUAD_H1[1]	QUAD_H1[7]	QUAD_H2[0]	QUAD_H2[6]	QUAD_H1[1]	QUAD_H1[7]	QUAD_H2[0]	QUAD_H2[6]

siliconblue IOI_E_L08 switchbox INT muxes LOCAL
Bits					Destination
MAIN[1][5]	MAIN[1][4]	MAIN[0][4]	MAIN[1][6]	MAIN[1][7]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[0][5]	MAIN[1][8]	MAIN[0][8]	MAIN[0][6]	MAIN[0][7]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[3][5]	MAIN[3][4]	MAIN[2][4]	MAIN[3][6]	MAIN[3][7]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[2][5]	MAIN[3][8]	MAIN[2][8]	MAIN[2][6]	MAIN[2][7]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[5][5]	MAIN[5][4]	MAIN[4][4]	MAIN[5][6]	MAIN[5][7]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[4][5]	MAIN[5][8]	MAIN[4][8]	MAIN[4][6]	MAIN[4][7]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[7][5]	MAIN[7][4]	MAIN[6][4]	MAIN[7][6]	MAIN[7][7]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[6][5]	MAIN[7][8]	MAIN[6][8]	MAIN[6][6]	MAIN[6][7]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[9][5]	MAIN[9][4]	MAIN[8][4]	MAIN[9][6]	MAIN[9][7]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[8][5]	MAIN[9][8]	MAIN[8][8]	MAIN[8][6]	MAIN[8][7]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[11][5]	MAIN[11][4]	MAIN[10][4]	MAIN[11][6]	MAIN[11][7]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[10][5]	MAIN[11][8]	MAIN[10][8]	MAIN[10][6]	MAIN[10][7]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[13][5]	MAIN[13][4]	MAIN[12][4]	MAIN[13][6]	MAIN[13][7]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[12][5]	MAIN[13][8]	MAIN[12][8]	MAIN[12][6]	MAIN[12][7]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[15][5]	MAIN[15][4]	MAIN[14][4]	MAIN[15][6]	MAIN[15][7]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[14][5]	MAIN[15][8]	MAIN[14][8]	MAIN[14][6]	MAIN[14][7]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	LONG_H5[0]	LONG_H5[1]	LONG_H6[1]	LONG_H6[0]	LONG_H7[0]	LONG_H7[1]	LONG_H8[1]	LONG_H8[0]
0	0	1	0	1	OUT_LC_ES[0]	OUT_LC_ES[1]	OUT_LC_ES[2]	OUT_LC_ES[3]	OUT_LC_ES[4]	OUT_LC_ES[5]	OUT_LC_ES[6]	OUT_LC_ES[7]
0	0	1	1	1	QUAD_H1[0]	QUAD_H1[1]	QUAD_H1[2]	QUAD_H1[3]	QUAD_H1[4]	QUAD_H1[5]	QUAD_H1[6]	QUAD_H1[7]
0	1	0	1	1	LONG_H9[0]	LONG_H9[1]	LONG_H10[1]	LONG_H10[0]	LONG_H11[0]	LONG_H11[1]	LONG_H12[1]	LONG_H12[0]
0	1	1	0	1	OUT_LC_E[0]	OUT_LC_E[1]	OUT_LC_E[2]	OUT_LC_E[3]	OUT_LC_E[4]	OUT_LC_E[5]	OUT_LC_E[6]	OUT_LC_E[7]
0	1	1	1	1	QUAD_H1[8]	QUAD_H1[9]	QUAD_H1[10]	QUAD_H1[11]	QUAD_H2[1]	QUAD_H2[0]	QUAD_H2[3]	QUAD_H2[2]
1	0	0	0	1	OUT_LC_EN[0]	OUT_LC_EN[1]	OUT_LC_EN[2]	OUT_LC_EN[3]	OUT_LC_EN[4]	OUT_LC_EN[5]	OUT_LC_EN[6]	OUT_LC_EN[7]
1	0	0	1	1	QUAD_H2[5]	QUAD_H2[4]	QUAD_H2[7]	QUAD_H2[6]	QUAD_H2[9]	QUAD_H2[8]	QUAD_H2[11]	QUAD_H2[10]
1	0	1	0	1	QUAD_V2[0]	QUAD_V2[1]	QUAD_V2[2]	QUAD_V2[3]	QUAD_V1[0]	QUAD_V1[1]	QUAD_V1[2]	QUAD_V1[3]
1	0	1	1	1	QUAD_H3[8]	QUAD_H3[9]	QUAD_H3[10]	QUAD_H3[11]	QUAD_H4[1]	QUAD_H4[0]	QUAD_H4[3]	QUAD_H4[2]
1	1	0	0	1	QUAD_V4[0]	QUAD_V4[1]	QUAD_V4[2]	QUAD_V4[3]	QUAD_V3[0]	QUAD_V3[1]	QUAD_V3[2]	QUAD_V3[3]
1	1	0	1	1	QUAD_H3[0]	QUAD_H3[1]	QUAD_H3[2]	QUAD_H3[3]	QUAD_H3[4]	QUAD_H3[5]	QUAD_H3[6]	QUAD_H3[7]
1	1	1	0	1	LONG_H1[0]	LONG_H1[1]	LONG_H2[1]	LONG_H2[0]	LONG_H3[0]	LONG_H3[1]	LONG_H4[1]	LONG_H4[0]
1	1	1	1	1	QUAD_H4[5]	QUAD_H4[4]	QUAD_H4[7]	QUAD_H4[6]	QUAD_H4[9]	QUAD_H4[8]	QUAD_H4[11]	QUAD_H4[10]

siliconblue IOI_E_L08 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[11][14]	MAIN[11][15]	MAIN[10][14]	MAIN[10][15]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[1]
0	0	1	1	GLOBAL[3]
0	1	0	1	GLOBAL[5]
0	1	1	1	GLOBAL[7]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_E_L08 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[4][12]	MAIN[4][13]	MAIN[5][12]	MAIN[5][13]	IMUX_IO_DOUT0[0]	-
MAIN[10][12]	MAIN[10][13]	MAIN[11][12]	MAIN[11][13]	-	IMUX_IO_DOUT0[1]
MAIN[8][11]	MAIN[8][10]	MAIN[9][10]	MAIN[9][11]	-	IMUX_IO_DOUT1[0]
MAIN[14][11]	MAIN[14][10]	MAIN[15][10]	MAIN[15][11]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_E_L08 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[4][11]	MAIN[4][10]	MAIN[5][10]	MAIN[5][11]	IMUX_IO_OE[0]	-
MAIN[10][11]	MAIN[10][10]	MAIN[11][10]	MAIN[11][11]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_E_L08 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[8][13]	MAIN[8][14]	MAIN[8][12]	MAIN[9][12]	MAIN[9][15]	IMUX_IO_ICLK	-
MAIN[14][13]	MAIN[14][14]	MAIN[14][12]	MAIN[15][12]	MAIN[15][15]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_E_L08 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[5][14]	MAIN[5][15]	MAIN[4][14]	MAIN[4][15]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_E_L08 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_E_L08 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[3][17]	MAIN[13][17]
PIN_TYPE bit 1	MAIN[3][16]	MAIN[13][16]
PIN_TYPE bit 2	MAIN[0][17]	MAIN[10][17]
PIN_TYPE bit 3	MAIN[0][16]	MAIN[10][16]
PIN_TYPE bit 4	MAIN[4][16]	MAIN[14][16]
PIN_TYPE bit 5	MAIN[4][17]	MAIN[14][17]

Bel wires

siliconblue IOI_E_L08 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_E_L08 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17
F0	INT: buffer QUAD_H2[5] ← OUT_LC[0]	INT: buffer QUAD_H3[0] ← OUT_LC[0]	-	-	INT: mux LOCAL_0[0] bit 2	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 2	-	-	INT: mux QUAD_V0[0] bit 1	INT: mux QUAD_V0[0] bit 0	INT: mux QUAD_H1[1] bit 0	INT: mux QUAD_H1[1] bit 1	-	IOI[0]: PIN_TYPE bit 3	IOI[0]: PIN_TYPE bit 2
F1	INT: buffer QUAD_H1[0] ← OUT_LC[0]	INT: buffer QUAD_H1[8] ← OUT_LC[0]	INT: buffer QUAD_H3[8] ← OUT_LC[0]	-	INT: mux LOCAL_0[0] bit 3	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[1] bit 3	-	-	INT: mux QUAD_H3[1] bit 0	INT: mux QUAD_H3[1] bit 1	INT: mux QUAD_V4[0] bit 0	INT: mux QUAD_V4[0] bit 1	-	-	INT: buffer LONG_H1[0] ← OUT_LC[0]
F2	INT: buffer QUAD_V3[0] ← OUT_LC[0]	INT: buffer QUAD_V2[0] ← OUT_LC[0]	-	-	INT: mux LOCAL_0[2] bit 2	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 2	-	-	INT: mux QUAD_V0[1] bit 1	INT: mux QUAD_V0[1] bit 0	INT: mux QUAD_H1[7] bit 0	INT: mux QUAD_H1[7] bit 1	-	-	INT: buffer LONG_H5[0] ← OUT_LC[0]
F3	INT: buffer QUAD_H4[5] ← OUT_LC[0]	INT: buffer QUAD_V4[0] ← OUT_LC[0]	INT: buffer QUAD_V1[0] ← OUT_LC[0]	-	INT: mux LOCAL_0[2] bit 3	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[3] bit 3	-	-	INT: mux QUAD_H3[7] bit 0	INT: mux QUAD_H3[7] bit 1	INT: mux QUAD_V4[1] bit 0	INT: mux QUAD_V4[1] bit 1	-	IOI[0]: PIN_TYPE bit 1	IOI[0]: PIN_TYPE bit 0
F4	INT: buffer QUAD_H2[7] ← OUT_LC[1]	INT: buffer QUAD_H3[2] ← OUT_LC[1]	-	-	INT: mux LOCAL_0[4] bit 2	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 2	-	INT: mux IMUX_IO_OE[0] bit 2	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_EXTRA bit 0	IOI[0]: PIN_TYPE bit 4	IOI[0]: PIN_TYPE bit 5
F5	INT: buffer QUAD_H1[2] ← OUT_LC[1]	INT: buffer QUAD_H1[10] ← OUT_LC[1]	INT: buffer QUAD_H3[10] ← OUT_LC[1]	-	INT: mux LOCAL_0[4] bit 3	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[5] bit 3	-	INT: mux IMUX_IO_OE[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_EXTRA bit 2	-	INT: buffer LONG_H9[0] ← OUT_LC[0]
F6	INT: buffer QUAD_V3[1] ← OUT_LC[1]	INT: buffer QUAD_V2[1] ← OUT_LC[1]	-	-	INT: mux LOCAL_0[6] bit 2	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 2	-	-	INT: mux QUAD_V0[2] bit 1	INT: mux QUAD_V0[2] bit 0	INT: mux QUAD_H2[0] bit 0	INT: mux QUAD_H2[0] bit 1	-	INT: buffer LONG_H10[1] ← OUT_LC[1]	-
F7	INT: buffer QUAD_H4[7] ← OUT_LC[1]	INT: buffer QUAD_V4[1] ← OUT_LC[1]	INT: buffer QUAD_V1[1] ← OUT_LC[1]	-	INT: mux LOCAL_0[6] bit 3	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[7] bit 3	-	-	INT: mux QUAD_H4[0] bit 0	INT: mux QUAD_H4[0] bit 1	INT: mux QUAD_V4[2] bit 0	INT: mux QUAD_V4[2] bit 1	-	INT: buffer LONG_H2[1] ← OUT_LC[1]	INT: buffer LONG_H6[1] ← OUT_LC[1]
F8	INT: buffer QUAD_H2[9] ← OUT_LC[2]	INT: buffer QUAD_H3[4] ← OUT_LC[2]	-	-	INT: mux LOCAL_1[0] bit 2	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 2	-	INT: mux IMUX_IO_DOUT1[0] bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 3	-	INT: buffer LONG_H11[0] ← OUT_LC[2]	-
F9	INT: buffer QUAD_H1[4] ← OUT_LC[2]	INT: buffer QUAD_H2[1] ← OUT_LC[2]	INT: buffer QUAD_H4[1] ← OUT_LC[2]	-	INT: mux LOCAL_1[0] bit 3	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[1] bit 3	-	INT: mux IMUX_IO_DOUT1[0] bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_ICLK bit 1	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	-	INT: mux IMUX_IO_ICLK bit 0	INT: buffer LONG_H3[0] ← OUT_LC[2]	INT: buffer LONG_H7[0] ← OUT_LC[2]
F10	INT: buffer QUAD_V3[2] ← OUT_LC[2]	INT: buffer QUAD_V2[2] ← OUT_LC[2]	-	-	INT: mux LOCAL_1[2] bit 2	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 2	-	INT: mux IMUX_IO_OE[1] bit 2	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_CE bit 1	INT: mux IMUX_CE bit 0	IOI[1]: PIN_TYPE bit 3	IOI[1]: PIN_TYPE bit 2
F11	INT: buffer QUAD_H4[9] ← OUT_LC[2]	INT: buffer QUAD_V4[2] ← OUT_LC[2]	INT: buffer QUAD_V1[2] ← OUT_LC[2]	-	INT: mux LOCAL_1[2] bit 3	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[3] bit 3	-	INT: mux IMUX_IO_OE[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_CE bit 3	INT: mux IMUX_CE bit 2	-	INT: buffer LONG_H4[1] ← OUT_LC[3]
F12	INT: buffer QUAD_H2[11] ← OUT_LC[3]	INT: buffer QUAD_H3[6] ← OUT_LC[3]	-	-	INT: mux LOCAL_1[4] bit 2	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 2	-	-	INT: mux QUAD_V0[3] bit 1	INT: mux QUAD_V0[3] bit 0	INT: mux QUAD_H2[6] bit 0	INT: mux QUAD_H2[6] bit 1	-	-	INT: buffer LONG_H8[1] ← OUT_LC[3]
F13	INT: buffer QUAD_H1[6] ← OUT_LC[3]	INT: buffer QUAD_H2[3] ← OUT_LC[3]	INT: buffer QUAD_H4[3] ← OUT_LC[3]	-	INT: mux LOCAL_1[4] bit 3	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[5] bit 3	-	-	INT: mux QUAD_H4[6] bit 0	INT: mux QUAD_H4[6] bit 1	INT: mux QUAD_V4[3] bit 0	INT: mux QUAD_V4[3] bit 1	-	IOI[1]: PIN_TYPE bit 1	IOI[1]: PIN_TYPE bit 0
F14	INT: buffer QUAD_V3[3] ← OUT_LC[3]	INT: buffer QUAD_V2[3] ← OUT_LC[3]	-	-	INT: mux LOCAL_1[6] bit 2	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 2	-	INT: mux IMUX_IO_DOUT1[1] bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 3	-	IOI[1]: PIN_TYPE bit 4	IOI[1]: PIN_TYPE bit 5
F15	INT: buffer QUAD_H4[11] ← OUT_LC[3]	INT: buffer QUAD_V4[3] ← OUT_LC[3]	INT: buffer QUAD_V1[3] ← OUT_LC[3]	-	INT: mux LOCAL_1[6] bit 3	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[7] bit 3	-	INT: mux IMUX_IO_DOUT1[1] bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_OCLK bit 1	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	-	INT: mux IMUX_IO_OCLK bit 0	-	INT: buffer LONG_H12[1] ← OUT_LC[3]

Tile IOI_S_L08

Cells: 1

Switchbox INT

siliconblue IOI_S_L08 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H0[0]	OUT_LC[0]	MAIN[13][25]
QUAD_H0[1]	OUT_LC[1]	MAIN[9][25]
QUAD_H0[2]	OUT_LC[2]	MAIN[5][25]
QUAD_H0[3]	OUT_LC[3]	MAIN[1][25]
QUAD_H1[0]	OUT_LC[0]	MAIN[12][23]
QUAD_H1[1]	OUT_LC[1]	MAIN[8][23]
QUAD_H1[2]	OUT_LC[2]	MAIN[4][23]
QUAD_H1[3]	OUT_LC[3]	MAIN[0][23]
QUAD_H2[0]	OUT_LC[0]	MAIN[12][25]
QUAD_H2[1]	OUT_LC[1]	MAIN[8][25]
QUAD_H2[2]	OUT_LC[2]	MAIN[4][25]
QUAD_H2[3]	OUT_LC[3]	MAIN[0][25]
QUAD_H3[0]	OUT_LC[0]	MAIN[13][26]
QUAD_H3[1]	OUT_LC[1]	MAIN[9][26]
QUAD_H3[2]	OUT_LC[2]	MAIN[5][26]
QUAD_H3[3]	OUT_LC[3]	MAIN[1][26]
QUAD_V0[0]	OUT_LC[2]	MAIN[6][26]
QUAD_V0[2]	OUT_LC[3]	MAIN[2][26]
QUAD_V0[4]	OUT_LC[0]	MAIN[13][23]
QUAD_V0[6]	OUT_LC[1]	MAIN[9][23]
QUAD_V0[8]	OUT_LC[2]	MAIN[5][23]
QUAD_V0[10]	OUT_LC[3]	MAIN[1][23]
QUAD_V1[1]	OUT_LC[0]	MAIN[15][25]
QUAD_V1[3]	OUT_LC[1]	MAIN[11][25]
QUAD_V1[5]	OUT_LC[2]	MAIN[7][25]
QUAD_V1[7]	OUT_LC[3]	MAIN[3][25]
QUAD_V1[9]	OUT_LC[0]	MAIN[14][26]
QUAD_V1[11]	OUT_LC[1]	MAIN[10][26]
QUAD_V2[0]	OUT_LC[2]	MAIN[6][25]
QUAD_V2[2]	OUT_LC[3]	MAIN[2][25]
QUAD_V2[4]	OUT_LC[0]	MAIN[15][23]
QUAD_V2[6]	OUT_LC[1]	MAIN[11][23]
QUAD_V2[8]	OUT_LC[2]	MAIN[7][23]
QUAD_V2[10]	OUT_LC[3]	MAIN[3][23]
QUAD_V3[1]	OUT_LC[0]	MAIN[14][23]
QUAD_V3[3]	OUT_LC[1]	MAIN[10][23]
QUAD_V3[5]	OUT_LC[2]	MAIN[6][23]
QUAD_V3[7]	OUT_LC[3]	MAIN[2][23]
QUAD_V3[9]	OUT_LC[0]	MAIN[14][25]
QUAD_V3[11]	OUT_LC[1]	MAIN[10][25]
LONG_V0[0]	OUT_LC[3]	MAIN[1][5]
LONG_V1[1]	OUT_LC[2]	MAIN[7][4]
LONG_V2[0]	OUT_LC[1]	MAIN[8][4]
LONG_V3[1]	OUT_LC[0]	MAIN[10][5]
LONG_V4[0]	OUT_LC[3]	MAIN[3][5]
LONG_V5[1]	OUT_LC[2]	MAIN[6][5]
LONG_V6[0]	OUT_LC[1]	MAIN[9][5]
LONG_V7[1]	OUT_LC[0]	MAIN[12][5]
LONG_V8[0]	OUT_LC[3]	MAIN[5][5]
LONG_V9[1]	OUT_LC[2]	MAIN[6][4]
LONG_V10[0]	OUT_LC[1]	MAIN[9][4]
LONG_V11[1]	OUT_LC[0]	MAIN[14][5]

siliconblue IOI_S_L08 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[6][35]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[1][35]

siliconblue IOI_S_L08 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[14][35]	MAIN[14][36]	QUAD_H0[0]	-	-	-	-	-	-	-
MAIN[13][35]	MAIN[13][36]	-	QUAD_H0[1]	-	-	-	-	-	-
MAIN[9][35]	MAIN[9][36]	-	-	QUAD_H0[2]	-	-	-	-	-
MAIN[2][35]	MAIN[2][36]	-	-	-	QUAD_H0[3]	-	-	-	-
MAIN[15][34]	MAIN[15][33]	-	-	-	-	QUAD_H4[0]	-	-	-
MAIN[12][34]	MAIN[12][33]	-	-	-	-	-	QUAD_H4[1]	-	-
MAIN[8][34]	MAIN[8][33]	-	-	-	-	-	-	QUAD_H4[2]	-
MAIN[3][34]	MAIN[3][33]	-	-	-	-	-	-	-	QUAD_H4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H4[0]	QUAD_H4[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]
1	0	QUAD_V1[0]	QUAD_V1[6]	QUAD_V0[1]	QUAD_V0[7]	QUAD_V1[0]	QUAD_V1[6]	QUAD_V0[1]	QUAD_V0[7]
1	1	QUAD_V3[0]	QUAD_V3[6]	QUAD_V2[1]	QUAD_V2[7]	QUAD_V3[0]	QUAD_V3[6]	QUAD_V2[1]	QUAD_V2[7]

siliconblue IOI_S_L08 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[9][33]	MAIN[9][34]	QUAD_V0[1]	-	-	-	-	-	-	-
MAIN[2][33]	MAIN[2][34]	-	QUAD_V0[7]	-	-	-	-	-	-
MAIN[14][33]	MAIN[14][34]	-	-	QUAD_V1[0]	-	-	-	-	-
MAIN[13][33]	MAIN[13][34]	-	-	-	QUAD_V1[6]	-	-	-	-
MAIN[8][35]	MAIN[8][36]	-	-	-	-	QUAD_V2[1]	-	-	-
MAIN[3][35]	MAIN[3][36]	-	-	-	-	-	QUAD_V2[7]	-	-
MAIN[15][35]	MAIN[15][36]	-	-	-	-	-	-	QUAD_V3[0]	-
MAIN[12][35]	MAIN[12][36]	-	-	-	-	-	-	-	QUAD_V3[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]
1	0	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]	QUAD_V0[1]	QUAD_V0[7]	QUAD_V1[0]	QUAD_V1[6]
1	1	QUAD_V2[1]	QUAD_V2[7]	QUAD_V3[0]	QUAD_V3[6]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]

siliconblue IOI_S_L08 switchbox INT muxes LOCAL
Bits					Destination
MAIN[14][18]	MAIN[15][16]	MAIN[14][16]	MAIN[14][17]	MAIN[14][19]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[15][18]	MAIN[15][20]	MAIN[14][20]	MAIN[15][17]	MAIN[15][19]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[13][18]	MAIN[12][16]	MAIN[13][16]	MAIN[13][17]	MAIN[13][19]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[12][18]	MAIN[12][20]	MAIN[13][20]	MAIN[12][17]	MAIN[12][19]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[10][18]	MAIN[11][16]	MAIN[10][16]	MAIN[10][17]	MAIN[10][19]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[11][18]	MAIN[11][20]	MAIN[10][20]	MAIN[11][17]	MAIN[11][19]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[9][18]	MAIN[8][16]	MAIN[9][16]	MAIN[9][17]	MAIN[9][19]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[8][18]	MAIN[8][20]	MAIN[9][20]	MAIN[8][17]	MAIN[8][19]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[6][18]	MAIN[7][16]	MAIN[6][16]	MAIN[6][17]	MAIN[6][19]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[7][18]	MAIN[7][20]	MAIN[6][20]	MAIN[7][17]	MAIN[7][19]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[5][18]	MAIN[4][16]	MAIN[5][16]	MAIN[5][17]	MAIN[5][19]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[4][18]	MAIN[4][20]	MAIN[5][20]	MAIN[4][17]	MAIN[4][19]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[2][18]	MAIN[3][16]	MAIN[2][16]	MAIN[2][17]	MAIN[2][19]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[3][18]	MAIN[3][20]	MAIN[2][20]	MAIN[3][17]	MAIN[3][19]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[1][18]	MAIN[0][16]	MAIN[1][16]	MAIN[1][17]	MAIN[1][19]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[0][18]	MAIN[0][20]	MAIN[1][20]	MAIN[0][17]	MAIN[0][19]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	OUT_LC_WS[0]	OUT_LC_WS[1]	OUT_LC_WS[2]	OUT_LC_WS[3]	OUT_LC_WS[4]	OUT_LC_WS[5]	OUT_LC_WS[6]	OUT_LC_WS[7]
0	0	1	1	1	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H1[0]	QUAD_H1[1]	QUAD_H1[2]	QUAD_H1[3]
0	1	0	0	1	OUT_LC_ES[0]	OUT_LC_ES[1]	OUT_LC_ES[2]	OUT_LC_ES[3]	OUT_LC_ES[4]	OUT_LC_ES[5]	OUT_LC_ES[6]	OUT_LC_ES[7]
0	1	0	1	1	QUAD_H2[0]	QUAD_H2[1]	QUAD_H2[2]	QUAD_H2[3]	QUAD_H3[0]	QUAD_H3[1]	QUAD_H3[2]	QUAD_H3[3]
0	1	1	0	1	OUT_LC_S[0]	OUT_LC_S[1]	OUT_LC_S[2]	OUT_LC_S[3]	OUT_LC_S[4]	OUT_LC_S[5]	OUT_LC_S[6]	OUT_LC_S[7]
0	1	1	1	1	LONG_V11[1]	LONG_V11[0]	LONG_V10[0]	LONG_V10[1]	LONG_V9[1]	LONG_V9[0]	LONG_V8[0]	LONG_V8[1]
1	0	0	0	1	LONG_V7[1]	LONG_V7[0]	LONG_V6[0]	LONG_V6[1]	LONG_V5[1]	LONG_V5[0]	LONG_V4[0]	LONG_V4[1]
1	0	0	1	1	QUAD_V2[4]	QUAD_V2[5]	QUAD_V2[6]	QUAD_V2[7]	QUAD_V2[8]	QUAD_V2[9]	QUAD_V2[10]	QUAD_V2[11]
1	0	1	0	1	LONG_V3[1]	LONG_V3[0]	LONG_V2[0]	LONG_V2[1]	LONG_V1[1]	LONG_V1[0]	LONG_V0[0]	LONG_V0[1]
1	0	1	1	1	QUAD_V1[1]	QUAD_V1[0]	QUAD_V1[3]	QUAD_V1[2]	QUAD_V1[5]	QUAD_V1[4]	QUAD_V1[7]	QUAD_V1[6]
1	1	0	0	1	QUAD_V3[1]	QUAD_V3[0]	QUAD_V3[3]	QUAD_V3[2]	QUAD_V3[5]	QUAD_V3[4]	QUAD_V3[7]	QUAD_V3[6]
1	1	0	1	1	QUAD_V1[9]	QUAD_V1[8]	QUAD_V1[11]	QUAD_V1[10]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	1	1	0	1	QUAD_V3[9]	QUAD_V3[8]	QUAD_V3[11]	QUAD_V3[10]	QUAD_V2[0]	QUAD_V2[1]	QUAD_V2[2]	QUAD_V2[3]
1	1	1	1	1	QUAD_V0[4]	QUAD_V0[5]	QUAD_V0[6]	QUAD_V0[7]	QUAD_V0[8]	QUAD_V0[9]	QUAD_V0[10]	QUAD_V0[11]

siliconblue IOI_S_L08 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[5][36]	MAIN[5][37]	MAIN[4][36]	MAIN[4][37]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[1]
0	0	1	1	GLOBAL[3]
0	1	0	1	GLOBAL[5]
0	1	1	1	GLOBAL[7]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_S_L08 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[11][34]	MAIN[11][35]	MAIN[10][34]	MAIN[10][35]	IMUX_IO_DOUT0[0]	-
MAIN[4][34]	MAIN[4][35]	MAIN[5][34]	MAIN[5][35]	-	IMUX_IO_DOUT0[1]
MAIN[7][33]	MAIN[7][32]	MAIN[6][32]	MAIN[6][33]	-	IMUX_IO_DOUT1[0]
MAIN[0][33]	MAIN[0][32]	MAIN[1][32]	MAIN[1][33]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_S_L08 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[11][33]	MAIN[11][32]	MAIN[10][32]	MAIN[10][33]	IMUX_IO_OE[0]	-
MAIN[4][33]	MAIN[4][32]	MAIN[5][32]	MAIN[5][33]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_S_L08 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[7][35]	MAIN[7][36]	MAIN[7][34]	MAIN[6][34]	MAIN[6][37]	IMUX_IO_ICLK	-
MAIN[0][35]	MAIN[0][36]	MAIN[0][34]	MAIN[1][34]	MAIN[1][37]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_S_L08 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[10][36]	MAIN[10][37]	MAIN[11][36]	MAIN[11][37]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_S_L08 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_S_L08 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[13][5]	MAIN[2][5]
PIN_TYPE bit 1	MAIN[13][4]	MAIN[2][4]
PIN_TYPE bit 2	MAIN[15][5]	MAIN[4][5]
PIN_TYPE bit 3	MAIN[15][4]	MAIN[4][4]
PIN_TYPE bit 4	MAIN[11][4]	MAIN[0][4]
PIN_TYPE bit 5	MAIN[11][5]	MAIN[0][5]

Bel wires

siliconblue IOI_S_L08 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_S_L08 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17	B18	B19	B20	B21	B22	B23	B24	B25	B26	B27	B28	B29	B30	B31	B32	B33	B34	B35	B36	B37	B38	B39	B40	B41
F0	-	-	-	-	IOI[1]: PIN_TYPE bit 4	IOI[1]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 3	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 3	-	-	INT: buffer QUAD_H1[3] ← OUT_LC[3]	-	INT: buffer QUAD_H2[3] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 3	-	-	-	-	-
F1	-	-	-	-	-	INT: buffer LONG_V0[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 2	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[7] bit 2	-	-	INT: buffer QUAD_V0[10] ← OUT_LC[3]	-	INT: buffer QUAD_H0[3] ← OUT_LC[3]	INT: buffer QUAD_H3[3] ← OUT_LC[3]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_OCLK bit 1	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	-	INT: mux IMUX_IO_OCLK bit 0	-	-	-	-
F2	-	-	-	-	IOI[1]: PIN_TYPE bit 1	IOI[1]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 2	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[5] bit 2	-	-	INT: buffer QUAD_V3[7] ← OUT_LC[3]	-	INT: buffer QUAD_V2[2] ← OUT_LC[3]	INT: buffer QUAD_V0[2] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux QUAD_V0[7] bit 1	INT: mux QUAD_V0[7] bit 0	INT: mux QUAD_H0[3] bit 1	INT: mux QUAD_H0[3] bit 0	-	-	-	-	-
F3	-	-	-	-	-	INT: buffer LONG_V4[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 3	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 3	-	-	INT: buffer QUAD_V2[10] ← OUT_LC[3]	-	INT: buffer QUAD_V1[7] ← OUT_LC[3]	-	-	-	-	-	-	-	INT: mux QUAD_H4[3] bit 0	INT: mux QUAD_H4[3] bit 1	INT: mux QUAD_V2[7] bit 1	INT: mux QUAD_V2[7] bit 0	-	-	-	-	-
F4	-	-	-	-	IOI[1]: PIN_TYPE bit 3	IOI[1]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 3	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 3	-	-	INT: buffer QUAD_H1[2] ← OUT_LC[2]	-	INT: buffer QUAD_H2[2] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 2	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_CE bit 1	INT: mux IMUX_CE bit 0	-	-	-	-
F5	-	-	-	-	-	INT: buffer LONG_V8[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 2	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[3] bit 2	-	-	INT: buffer QUAD_V0[8] ← OUT_LC[2]	-	INT: buffer QUAD_H0[2] ← OUT_LC[2]	INT: buffer QUAD_H3[2] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_CE bit 3	INT: mux IMUX_CE bit 2	-	-	-	-
F6	-	-	-	-	INT: buffer LONG_V9[1] ← OUT_LC[2]	INT: buffer LONG_V5[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 2	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[1] bit 2	-	-	INT: buffer QUAD_V3[5] ← OUT_LC[2]	-	INT: buffer QUAD_V2[0] ← OUT_LC[2]	INT: buffer QUAD_V0[0] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_ICLK bit 1	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	-	INT: mux IMUX_IO_ICLK bit 0	-	-	-	-
F7	-	-	-	-	INT: buffer LONG_V1[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 3	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 3	-	-	INT: buffer QUAD_V2[8] ← OUT_LC[2]	-	INT: buffer QUAD_V1[5] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 3	-	-	-	-	-
F8	-	-	-	-	INT: buffer LONG_V2[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 3	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 3	-	-	INT: buffer QUAD_H1[1] ← OUT_LC[1]	-	INT: buffer QUAD_H2[1] ← OUT_LC[1]	-	-	-	-	-	-	-	INT: mux QUAD_H4[2] bit 0	INT: mux QUAD_H4[2] bit 1	INT: mux QUAD_V2[1] bit 1	INT: mux QUAD_V2[1] bit 0	-	-	-	-	-
F9	-	-	-	-	INT: buffer LONG_V10[0] ← OUT_LC[1]	INT: buffer LONG_V6[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 2	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[7] bit 2	-	-	INT: buffer QUAD_V0[6] ← OUT_LC[1]	-	INT: buffer QUAD_H0[1] ← OUT_LC[1]	INT: buffer QUAD_H3[1] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux QUAD_V0[1] bit 1	INT: mux QUAD_V0[1] bit 0	INT: mux QUAD_H0[2] bit 1	INT: mux QUAD_H0[2] bit 0	-	-	-	-	-
F10	-	-	-	-	-	INT: buffer LONG_V3[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 2	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[5] bit 2	-	-	INT: buffer QUAD_V3[3] ← OUT_LC[1]	-	INT: buffer QUAD_V3[11] ← OUT_LC[1]	INT: buffer QUAD_V1[11] ← OUT_LC[1]	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_EXTRA bit 2	-	-	-	-
F11	-	-	-	-	IOI[0]: PIN_TYPE bit 4	IOI[0]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 3	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 3	-	-	INT: buffer QUAD_V2[6] ← OUT_LC[1]	-	INT: buffer QUAD_V1[3] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 2	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_EXTRA bit 0	-	-	-	-
F12	-	-	-	-	-	INT: buffer LONG_V7[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 3	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 3	-	-	INT: buffer QUAD_H1[0] ← OUT_LC[0]	-	INT: buffer QUAD_H2[0] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[1] bit 0	INT: mux QUAD_H4[1] bit 1	INT: mux QUAD_V3[6] bit 1	INT: mux QUAD_V3[6] bit 0	-	-	-	-	-
F13	-	-	-	-	IOI[0]: PIN_TYPE bit 1	IOI[0]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 2	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[3] bit 2	-	-	INT: buffer QUAD_V0[4] ← OUT_LC[0]	-	INT: buffer QUAD_H0[0] ← OUT_LC[0]	INT: buffer QUAD_H3[0] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V1[6] bit 1	INT: mux QUAD_V1[6] bit 0	INT: mux QUAD_H0[1] bit 1	INT: mux QUAD_H0[1] bit 0	-	-	-	-	-
F14	-	-	-	-	-	INT: buffer LONG_V11[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 2	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[1] bit 2	-	-	INT: buffer QUAD_V3[1] ← OUT_LC[0]	-	INT: buffer QUAD_V3[9] ← OUT_LC[0]	INT: buffer QUAD_V1[9] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V1[0] bit 1	INT: mux QUAD_V1[0] bit 0	INT: mux QUAD_H0[0] bit 1	INT: mux QUAD_H0[0] bit 0	-	-	-	-	-
F15	-	-	-	-	IOI[0]: PIN_TYPE bit 3	IOI[0]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 3	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 3	-	-	INT: buffer QUAD_V2[4] ← OUT_LC[0]	-	INT: buffer QUAD_V1[1] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[0] bit 0	INT: mux QUAD_H4[0] bit 1	INT: mux QUAD_V3[0] bit 1	INT: mux QUAD_V3[0] bit 0	-	-	-	-	-

Tile IOI_N_L08

Cells: 1

Switchbox INT

siliconblue IOI_N_L08 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H0[0]	OUT_LC[0]	MAIN[2][25]
QUAD_H0[1]	OUT_LC[1]	MAIN[6][25]
QUAD_H0[2]	OUT_LC[2]	MAIN[10][25]
QUAD_H0[3]	OUT_LC[3]	MAIN[14][25]
QUAD_H1[0]	OUT_LC[0]	MAIN[3][23]
QUAD_H1[1]	OUT_LC[1]	MAIN[7][23]
QUAD_H1[2]	OUT_LC[2]	MAIN[11][23]
QUAD_H1[3]	OUT_LC[3]	MAIN[15][23]
QUAD_H2[0]	OUT_LC[0]	MAIN[3][25]
QUAD_H2[1]	OUT_LC[1]	MAIN[7][25]
QUAD_H2[2]	OUT_LC[2]	MAIN[11][25]
QUAD_H2[3]	OUT_LC[3]	MAIN[15][25]
QUAD_H3[0]	OUT_LC[0]	MAIN[2][26]
QUAD_H3[1]	OUT_LC[1]	MAIN[6][26]
QUAD_H3[2]	OUT_LC[2]	MAIN[10][26]
QUAD_H3[3]	OUT_LC[3]	MAIN[14][26]
QUAD_V1[0]	OUT_LC[2]	MAIN[9][26]
QUAD_V1[2]	OUT_LC[3]	MAIN[13][26]
QUAD_V1[4]	OUT_LC[0]	MAIN[2][23]
QUAD_V1[6]	OUT_LC[1]	MAIN[6][23]
QUAD_V1[8]	OUT_LC[2]	MAIN[10][23]
QUAD_V1[10]	OUT_LC[3]	MAIN[14][23]
QUAD_V2[1]	OUT_LC[0]	MAIN[0][25]
QUAD_V2[3]	OUT_LC[1]	MAIN[4][25]
QUAD_V2[5]	OUT_LC[2]	MAIN[8][25]
QUAD_V2[7]	OUT_LC[3]	MAIN[12][25]
QUAD_V2[9]	OUT_LC[0]	MAIN[1][26]
QUAD_V2[11]	OUT_LC[1]	MAIN[5][26]
QUAD_V3[0]	OUT_LC[2]	MAIN[9][25]
QUAD_V3[2]	OUT_LC[3]	MAIN[13][25]
QUAD_V3[4]	OUT_LC[0]	MAIN[0][23]
QUAD_V3[6]	OUT_LC[1]	MAIN[4][23]
QUAD_V3[8]	OUT_LC[2]	MAIN[8][23]
QUAD_V3[10]	OUT_LC[3]	MAIN[12][23]
QUAD_V4[1]	OUT_LC[0]	MAIN[1][23]
QUAD_V4[3]	OUT_LC[1]	MAIN[5][23]
QUAD_V4[5]	OUT_LC[2]	MAIN[9][23]
QUAD_V4[7]	OUT_LC[3]	MAIN[13][23]
QUAD_V4[9]	OUT_LC[0]	MAIN[1][25]
QUAD_V4[11]	OUT_LC[1]	MAIN[5][25]
LONG_V1[0]	OUT_LC[3]	MAIN[14][5]
LONG_V2[1]	OUT_LC[2]	MAIN[8][4]
LONG_V3[0]	OUT_LC[1]	MAIN[7][4]
LONG_V4[1]	OUT_LC[0]	MAIN[5][5]
LONG_V5[0]	OUT_LC[3]	MAIN[12][5]
LONG_V6[1]	OUT_LC[2]	MAIN[9][5]
LONG_V7[0]	OUT_LC[1]	MAIN[6][5]
LONG_V8[1]	OUT_LC[0]	MAIN[3][5]
LONG_V9[0]	OUT_LC[3]	MAIN[10][5]
LONG_V10[1]	OUT_LC[2]	MAIN[9][4]
LONG_V11[0]	OUT_LC[1]	MAIN[6][4]
LONG_V12[1]	OUT_LC[0]	MAIN[1][5]

siliconblue IOI_N_L08 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[9][35]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[14][35]

siliconblue IOI_N_L08 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[1][35]	MAIN[1][36]	QUAD_H0[0]	-	-	-	-	-	-	-
MAIN[2][35]	MAIN[2][36]	-	QUAD_H0[1]	-	-	-	-	-	-
MAIN[6][35]	MAIN[6][36]	-	-	QUAD_H0[2]	-	-	-	-	-
MAIN[13][35]	MAIN[13][36]	-	-	-	QUAD_H0[3]	-	-	-	-
MAIN[0][34]	MAIN[0][33]	-	-	-	-	QUAD_H4[0]	-	-	-
MAIN[3][34]	MAIN[3][33]	-	-	-	-	-	QUAD_H4[1]	-	-
MAIN[7][34]	MAIN[7][33]	-	-	-	-	-	-	QUAD_H4[2]	-
MAIN[12][34]	MAIN[12][33]	-	-	-	-	-	-	-	QUAD_H4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H4[0]	QUAD_H4[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]
1	0	QUAD_V2[0]	QUAD_V2[6]	QUAD_V1[1]	QUAD_V1[7]	QUAD_V2[0]	QUAD_V2[6]	QUAD_V1[1]	QUAD_V1[7]
1	1	QUAD_V4[0]	QUAD_V4[6]	QUAD_V3[1]	QUAD_V3[7]	QUAD_V4[0]	QUAD_V4[6]	QUAD_V3[1]	QUAD_V3[7]

siliconblue IOI_N_L08 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[6][33]	MAIN[6][34]	QUAD_V1[1]	-	-	-	-	-	-	-
MAIN[13][33]	MAIN[13][34]	-	QUAD_V1[7]	-	-	-	-	-	-
MAIN[1][33]	MAIN[1][34]	-	-	QUAD_V2[0]	-	-	-	-	-
MAIN[2][33]	MAIN[2][34]	-	-	-	QUAD_V2[6]	-	-	-	-
MAIN[7][35]	MAIN[7][36]	-	-	-	-	QUAD_V3[1]	-	-	-
MAIN[12][35]	MAIN[12][36]	-	-	-	-	-	QUAD_V3[7]	-	-
MAIN[0][35]	MAIN[0][36]	-	-	-	-	-	-	QUAD_V4[0]	-
MAIN[3][35]	MAIN[3][36]	-	-	-	-	-	-	-	QUAD_V4[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]
1	0	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]	QUAD_V1[1]	QUAD_V1[7]	QUAD_V2[0]	QUAD_V2[6]
1	1	QUAD_V3[1]	QUAD_V3[7]	QUAD_V4[0]	QUAD_V4[6]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]

siliconblue IOI_N_L08 switchbox INT muxes LOCAL
Bits					Destination
MAIN[1][18]	MAIN[0][16]	MAIN[1][16]	MAIN[1][17]	MAIN[1][19]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[0][18]	MAIN[0][20]	MAIN[1][20]	MAIN[0][17]	MAIN[0][19]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[2][18]	MAIN[3][16]	MAIN[2][16]	MAIN[2][17]	MAIN[2][19]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[3][18]	MAIN[3][20]	MAIN[2][20]	MAIN[3][17]	MAIN[3][19]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[5][18]	MAIN[4][16]	MAIN[5][16]	MAIN[5][17]	MAIN[5][19]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[4][18]	MAIN[4][20]	MAIN[5][20]	MAIN[4][17]	MAIN[4][19]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[6][18]	MAIN[7][16]	MAIN[6][16]	MAIN[6][17]	MAIN[6][19]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[7][18]	MAIN[7][20]	MAIN[6][20]	MAIN[7][17]	MAIN[7][19]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[9][18]	MAIN[8][16]	MAIN[9][16]	MAIN[9][17]	MAIN[9][19]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[8][18]	MAIN[8][20]	MAIN[9][20]	MAIN[8][17]	MAIN[8][19]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[10][18]	MAIN[11][16]	MAIN[10][16]	MAIN[10][17]	MAIN[10][19]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[11][18]	MAIN[11][20]	MAIN[10][20]	MAIN[11][17]	MAIN[11][19]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[13][18]	MAIN[12][16]	MAIN[13][16]	MAIN[13][17]	MAIN[13][19]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[12][18]	MAIN[12][20]	MAIN[13][20]	MAIN[12][17]	MAIN[12][19]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[14][18]	MAIN[15][16]	MAIN[14][16]	MAIN[14][17]	MAIN[14][19]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[15][18]	MAIN[15][20]	MAIN[14][20]	MAIN[15][17]	MAIN[15][19]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	OUT_LC_WN[0]	OUT_LC_WN[1]	OUT_LC_WN[2]	OUT_LC_WN[3]	OUT_LC_WN[4]	OUT_LC_WN[5]	OUT_LC_WN[6]	OUT_LC_WN[7]
0	0	1	1	1	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H1[0]	QUAD_H1[1]	QUAD_H1[2]	QUAD_H1[3]
0	1	0	0	1	OUT_LC_EN[0]	OUT_LC_EN[1]	OUT_LC_EN[2]	OUT_LC_EN[3]	OUT_LC_EN[4]	OUT_LC_EN[5]	OUT_LC_EN[6]	OUT_LC_EN[7]
0	1	0	1	1	QUAD_H2[0]	QUAD_H2[1]	QUAD_H2[2]	QUAD_H2[3]	QUAD_H3[0]	QUAD_H3[1]	QUAD_H3[2]	QUAD_H3[3]
0	1	1	0	1	OUT_LC_N[0]	OUT_LC_N[1]	OUT_LC_N[2]	OUT_LC_N[3]	OUT_LC_N[4]	OUT_LC_N[5]	OUT_LC_N[6]	OUT_LC_N[7]
0	1	1	1	1	LONG_V12[1]	LONG_V12[0]	LONG_V11[0]	LONG_V11[1]	LONG_V10[1]	LONG_V10[0]	LONG_V9[0]	LONG_V9[1]
1	0	0	0	1	LONG_V8[1]	LONG_V8[0]	LONG_V7[0]	LONG_V7[1]	LONG_V6[1]	LONG_V6[0]	LONG_V5[0]	LONG_V5[1]
1	0	0	1	1	QUAD_V3[4]	QUAD_V3[5]	QUAD_V3[6]	QUAD_V3[7]	QUAD_V3[8]	QUAD_V3[9]	QUAD_V3[10]	QUAD_V3[11]
1	0	1	0	1	LONG_V4[1]	LONG_V4[0]	LONG_V3[0]	LONG_V3[1]	LONG_V2[1]	LONG_V2[0]	LONG_V1[0]	LONG_V1[1]
1	0	1	1	1	QUAD_V2[1]	QUAD_V2[0]	QUAD_V2[3]	QUAD_V2[2]	QUAD_V2[5]	QUAD_V2[4]	QUAD_V2[7]	QUAD_V2[6]
1	1	0	0	1	QUAD_V4[1]	QUAD_V4[0]	QUAD_V4[3]	QUAD_V4[2]	QUAD_V4[5]	QUAD_V4[4]	QUAD_V4[7]	QUAD_V4[6]
1	1	0	1	1	QUAD_V2[9]	QUAD_V2[8]	QUAD_V2[11]	QUAD_V2[10]	QUAD_V1[0]	QUAD_V1[1]	QUAD_V1[2]	QUAD_V1[3]
1	1	1	0	1	QUAD_V4[9]	QUAD_V4[8]	QUAD_V4[11]	QUAD_V4[10]	QUAD_V3[0]	QUAD_V3[1]	QUAD_V3[2]	QUAD_V3[3]
1	1	1	1	1	QUAD_V1[4]	QUAD_V1[5]	QUAD_V1[6]	QUAD_V1[7]	QUAD_V1[8]	QUAD_V1[9]	QUAD_V1[10]	QUAD_V1[11]

siliconblue IOI_N_L08 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[10][36]	MAIN[10][37]	MAIN[11][36]	MAIN[11][37]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[1]
0	0	1	1	GLOBAL[3]
0	1	0	1	GLOBAL[5]
0	1	1	1	GLOBAL[7]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_N_L08 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[4][34]	MAIN[4][35]	MAIN[5][34]	MAIN[5][35]	IMUX_IO_DOUT0[0]	-
MAIN[11][34]	MAIN[11][35]	MAIN[10][34]	MAIN[10][35]	-	IMUX_IO_DOUT0[1]
MAIN[8][33]	MAIN[8][32]	MAIN[9][32]	MAIN[9][33]	-	IMUX_IO_DOUT1[0]
MAIN[15][33]	MAIN[15][32]	MAIN[14][32]	MAIN[14][33]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_N_L08 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[4][33]	MAIN[4][32]	MAIN[5][32]	MAIN[5][33]	IMUX_IO_OE[0]	-
MAIN[11][33]	MAIN[11][32]	MAIN[10][32]	MAIN[10][33]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_N_L08 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[8][35]	MAIN[8][36]	MAIN[8][34]	MAIN[9][34]	MAIN[9][37]	IMUX_IO_ICLK	-
MAIN[15][35]	MAIN[15][36]	MAIN[15][34]	MAIN[14][34]	MAIN[14][37]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_N_L08 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[5][36]	MAIN[5][37]	MAIN[4][36]	MAIN[4][37]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_N_L08 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_N_L08 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[2][5]	MAIN[13][5]
PIN_TYPE bit 1	MAIN[2][4]	MAIN[13][4]
PIN_TYPE bit 2	MAIN[0][5]	MAIN[11][5]
PIN_TYPE bit 3	MAIN[0][4]	MAIN[11][4]
PIN_TYPE bit 4	MAIN[4][4]	MAIN[15][4]
PIN_TYPE bit 5	MAIN[4][5]	MAIN[15][5]

Bel wires

siliconblue IOI_N_L08 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_N_L08 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17	B18	B19	B20	B21	B22	B23	B24	B25	B26	B27	B28	B29	B30	B31	B32	B33	B34	B35	B36	B37	B38	B39	B40	B41
F0	-	-	-	-	IOI[0]: PIN_TYPE bit 3	IOI[0]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 3	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 3	-	-	INT: buffer QUAD_V3[4] ← OUT_LC[0]	-	INT: buffer QUAD_V2[1] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[0] bit 0	INT: mux QUAD_H4[0] bit 1	INT: mux QUAD_V4[0] bit 1	INT: mux QUAD_V4[0] bit 0	-	-	-	-	-
F1	-	-	-	-	-	INT: buffer LONG_V12[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 2	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[1] bit 2	-	-	INT: buffer QUAD_V4[1] ← OUT_LC[0]	-	INT: buffer QUAD_V4[9] ← OUT_LC[0]	INT: buffer QUAD_V2[9] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V2[0] bit 1	INT: mux QUAD_V2[0] bit 0	INT: mux QUAD_H0[0] bit 1	INT: mux QUAD_H0[0] bit 0	-	-	-	-	-
F2	-	-	-	-	IOI[0]: PIN_TYPE bit 1	IOI[0]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 2	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[3] bit 2	-	-	INT: buffer QUAD_V1[4] ← OUT_LC[0]	-	INT: buffer QUAD_H0[0] ← OUT_LC[0]	INT: buffer QUAD_H3[0] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V2[6] bit 1	INT: mux QUAD_V2[6] bit 0	INT: mux QUAD_H0[1] bit 1	INT: mux QUAD_H0[1] bit 0	-	-	-	-	-
F3	-	-	-	-	-	INT: buffer LONG_V8[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 3	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 3	-	-	INT: buffer QUAD_H1[0] ← OUT_LC[0]	-	INT: buffer QUAD_H2[0] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[1] bit 0	INT: mux QUAD_H4[1] bit 1	INT: mux QUAD_V4[6] bit 1	INT: mux QUAD_V4[6] bit 0	-	-	-	-	-
F4	-	-	-	-	IOI[0]: PIN_TYPE bit 4	IOI[0]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 3	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 3	-	-	INT: buffer QUAD_V3[6] ← OUT_LC[1]	-	INT: buffer QUAD_V2[3] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 2	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_EXTRA bit 0	-	-	-	-
F5	-	-	-	-	-	INT: buffer LONG_V4[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 2	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[5] bit 2	-	-	INT: buffer QUAD_V4[3] ← OUT_LC[1]	-	INT: buffer QUAD_V4[11] ← OUT_LC[1]	INT: buffer QUAD_V2[11] ← OUT_LC[1]	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_EXTRA bit 2	-	-	-	-
F6	-	-	-	-	INT: buffer LONG_V11[0] ← OUT_LC[1]	INT: buffer LONG_V7[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 2	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[7] bit 2	-	-	INT: buffer QUAD_V1[6] ← OUT_LC[1]	-	INT: buffer QUAD_H0[1] ← OUT_LC[1]	INT: buffer QUAD_H3[1] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux QUAD_V1[1] bit 1	INT: mux QUAD_V1[1] bit 0	INT: mux QUAD_H0[2] bit 1	INT: mux QUAD_H0[2] bit 0	-	-	-	-	-
F7	-	-	-	-	INT: buffer LONG_V3[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 3	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 3	-	-	INT: buffer QUAD_H1[1] ← OUT_LC[1]	-	INT: buffer QUAD_H2[1] ← OUT_LC[1]	-	-	-	-	-	-	-	INT: mux QUAD_H4[2] bit 0	INT: mux QUAD_H4[2] bit 1	INT: mux QUAD_V3[1] bit 1	INT: mux QUAD_V3[1] bit 0	-	-	-	-	-
F8	-	-	-	-	INT: buffer LONG_V2[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 3	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 3	-	-	INT: buffer QUAD_V3[8] ← OUT_LC[2]	-	INT: buffer QUAD_V2[5] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 3	-	-	-	-	-
F9	-	-	-	-	INT: buffer LONG_V10[1] ← OUT_LC[2]	INT: buffer LONG_V6[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 2	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[1] bit 2	-	-	INT: buffer QUAD_V4[5] ← OUT_LC[2]	-	INT: buffer QUAD_V3[0] ← OUT_LC[2]	INT: buffer QUAD_V1[0] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_ICLK bit 1	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	-	INT: mux IMUX_IO_ICLK bit 0	-	-	-	-
F10	-	-	-	-	-	INT: buffer LONG_V9[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 2	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[3] bit 2	-	-	INT: buffer QUAD_V1[8] ← OUT_LC[2]	-	INT: buffer QUAD_H0[2] ← OUT_LC[2]	INT: buffer QUAD_H3[2] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_CE bit 3	INT: mux IMUX_CE bit 2	-	-	-	-
F11	-	-	-	-	IOI[1]: PIN_TYPE bit 3	IOI[1]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 3	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 3	-	-	INT: buffer QUAD_H1[2] ← OUT_LC[2]	-	INT: buffer QUAD_H2[2] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 2	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_CE bit 1	INT: mux IMUX_CE bit 0	-	-	-	-
F12	-	-	-	-	-	INT: buffer LONG_V5[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 3	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 3	-	-	INT: buffer QUAD_V3[10] ← OUT_LC[3]	-	INT: buffer QUAD_V2[7] ← OUT_LC[3]	-	-	-	-	-	-	-	INT: mux QUAD_H4[3] bit 0	INT: mux QUAD_H4[3] bit 1	INT: mux QUAD_V3[7] bit 1	INT: mux QUAD_V3[7] bit 0	-	-	-	-	-
F13	-	-	-	-	IOI[1]: PIN_TYPE bit 1	IOI[1]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 2	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[5] bit 2	-	-	INT: buffer QUAD_V4[7] ← OUT_LC[3]	-	INT: buffer QUAD_V3[2] ← OUT_LC[3]	INT: buffer QUAD_V1[2] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux QUAD_V1[7] bit 1	INT: mux QUAD_V1[7] bit 0	INT: mux QUAD_H0[3] bit 1	INT: mux QUAD_H0[3] bit 0	-	-	-	-	-
F14	-	-	-	-	-	INT: buffer LONG_V1[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 2	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[7] bit 2	-	-	INT: buffer QUAD_V1[10] ← OUT_LC[3]	-	INT: buffer QUAD_H0[3] ← OUT_LC[3]	INT: buffer QUAD_H3[3] ← OUT_LC[3]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_OCLK bit 1	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	-	INT: mux IMUX_IO_OCLK bit 0	-	-	-	-
F15	-	-	-	-	IOI[1]: PIN_TYPE bit 4	IOI[1]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 3	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 3	-	-	INT: buffer QUAD_H1[3] ← OUT_LC[3]	-	INT: buffer QUAD_H2[3] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 3	-	-	-	-	-

Tile IOI_S_T04

Cells: 1

Switchbox INT

siliconblue IOI_S_T04 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H0[0]	OUT_LC[0]	MAIN[13][25]
QUAD_H0[1]	OUT_LC[1]	MAIN[9][25]
QUAD_H0[2]	OUT_LC[2]	MAIN[5][25]
QUAD_H0[3]	OUT_LC[3]	MAIN[1][25]
QUAD_H1[0]	OUT_LC[0]	MAIN[12][23]
QUAD_H1[1]	OUT_LC[1]	MAIN[8][23]
QUAD_H1[2]	OUT_LC[2]	MAIN[4][23]
QUAD_H1[3]	OUT_LC[3]	MAIN[0][23]
QUAD_H2[0]	OUT_LC[0]	MAIN[12][25]
QUAD_H2[1]	OUT_LC[1]	MAIN[8][25]
QUAD_H2[2]	OUT_LC[2]	MAIN[4][25]
QUAD_H2[3]	OUT_LC[3]	MAIN[0][25]
QUAD_H3[0]	OUT_LC[0]	MAIN[13][26]
QUAD_H3[1]	OUT_LC[1]	MAIN[9][26]
QUAD_H3[2]	OUT_LC[2]	MAIN[5][26]
QUAD_H3[3]	OUT_LC[3]	MAIN[1][26]
QUAD_V0[0]	OUT_LC[2]	MAIN[6][26]
QUAD_V0[2]	OUT_LC[3]	MAIN[2][26]
QUAD_V0[4]	OUT_LC[0]	MAIN[13][23]
QUAD_V0[6]	OUT_LC[1]	MAIN[9][23]
QUAD_V0[8]	OUT_LC[2]	MAIN[5][23]
QUAD_V0[10]	OUT_LC[3]	MAIN[1][23]
QUAD_V1[1]	OUT_LC[0]	MAIN[15][25]
QUAD_V1[3]	OUT_LC[1]	MAIN[11][25]
QUAD_V1[5]	OUT_LC[2]	MAIN[7][25]
QUAD_V1[7]	OUT_LC[3]	MAIN[3][25]
QUAD_V1[9]	OUT_LC[0]	MAIN[14][26]
QUAD_V1[11]	OUT_LC[1]	MAIN[10][26]
QUAD_V2[0]	OUT_LC[2]	MAIN[6][25]
QUAD_V2[2]	OUT_LC[3]	MAIN[2][25]
QUAD_V2[4]	OUT_LC[0]	MAIN[15][23]
QUAD_V2[6]	OUT_LC[1]	MAIN[11][23]
QUAD_V2[8]	OUT_LC[2]	MAIN[7][23]
QUAD_V2[10]	OUT_LC[3]	MAIN[3][23]
QUAD_V3[1]	OUT_LC[0]	MAIN[14][23]
QUAD_V3[3]	OUT_LC[1]	MAIN[10][23]
QUAD_V3[5]	OUT_LC[2]	MAIN[6][23]
QUAD_V3[7]	OUT_LC[3]	MAIN[2][23]
QUAD_V3[9]	OUT_LC[0]	MAIN[14][25]
QUAD_V3[11]	OUT_LC[1]	MAIN[10][25]
LONG_V0[0]	OUT_LC[3]	MAIN[1][5]
LONG_V1[1]	OUT_LC[2]	MAIN[7][4]
LONG_V2[0]	OUT_LC[1]	MAIN[8][4]
LONG_V3[1]	OUT_LC[0]	MAIN[10][5]
LONG_V4[0]	OUT_LC[3]	MAIN[3][5]
LONG_V5[1]	OUT_LC[2]	MAIN[6][5]
LONG_V6[0]	OUT_LC[1]	MAIN[9][5]
LONG_V7[1]	OUT_LC[0]	MAIN[12][5]
LONG_V8[0]	OUT_LC[3]	MAIN[5][5]
LONG_V9[1]	OUT_LC[2]	MAIN[6][4]
LONG_V10[0]	OUT_LC[1]	MAIN[9][4]
LONG_V11[1]	OUT_LC[0]	MAIN[14][5]

siliconblue IOI_S_T04 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[6][35]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[1][35]

siliconblue IOI_S_T04 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[14][35]	MAIN[14][36]	QUAD_H0[0]	-	-	-	-	-	-	-
MAIN[13][35]	MAIN[13][36]	-	QUAD_H0[1]	-	-	-	-	-	-
MAIN[9][35]	MAIN[9][36]	-	-	QUAD_H0[2]	-	-	-	-	-
MAIN[2][35]	MAIN[2][36]	-	-	-	QUAD_H0[3]	-	-	-	-
MAIN[15][34]	MAIN[15][33]	-	-	-	-	QUAD_H4[0]	-	-	-
MAIN[12][34]	MAIN[12][33]	-	-	-	-	-	QUAD_H4[1]	-	-
MAIN[8][34]	MAIN[8][33]	-	-	-	-	-	-	QUAD_H4[2]	-
MAIN[3][34]	MAIN[3][33]	-	-	-	-	-	-	-	QUAD_H4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H4[0]	QUAD_H4[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]
1	0	QUAD_V1[0]	QUAD_V1[6]	QUAD_V0[1]	QUAD_V0[7]	QUAD_V1[0]	QUAD_V1[6]	QUAD_V0[1]	QUAD_V0[7]
1	1	QUAD_V3[0]	QUAD_V3[6]	QUAD_V2[1]	QUAD_V2[7]	QUAD_V3[0]	QUAD_V3[6]	QUAD_V2[1]	QUAD_V2[7]

siliconblue IOI_S_T04 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[9][33]	MAIN[9][34]	QUAD_V0[1]	-	-	-	-	-	-	-
MAIN[2][33]	MAIN[2][34]	-	QUAD_V0[7]	-	-	-	-	-	-
MAIN[14][33]	MAIN[14][34]	-	-	QUAD_V1[0]	-	-	-	-	-
MAIN[13][33]	MAIN[13][34]	-	-	-	QUAD_V1[6]	-	-	-	-
MAIN[8][35]	MAIN[8][36]	-	-	-	-	QUAD_V2[1]	-	-	-
MAIN[3][35]	MAIN[3][36]	-	-	-	-	-	QUAD_V2[7]	-	-
MAIN[15][35]	MAIN[15][36]	-	-	-	-	-	-	QUAD_V3[0]	-
MAIN[12][35]	MAIN[12][36]	-	-	-	-	-	-	-	QUAD_V3[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]
1	0	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]	QUAD_V0[1]	QUAD_V0[7]	QUAD_V1[0]	QUAD_V1[6]
1	1	QUAD_V2[1]	QUAD_V2[7]	QUAD_V3[0]	QUAD_V3[6]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]

siliconblue IOI_S_T04 switchbox INT muxes LOCAL
Bits					Destination
MAIN[14][18]	MAIN[15][16]	MAIN[14][16]	MAIN[14][17]	MAIN[14][19]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[15][18]	MAIN[15][20]	MAIN[14][20]	MAIN[15][17]	MAIN[15][19]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[13][18]	MAIN[12][16]	MAIN[13][16]	MAIN[13][17]	MAIN[13][19]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[12][18]	MAIN[12][20]	MAIN[13][20]	MAIN[12][17]	MAIN[12][19]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[10][18]	MAIN[11][16]	MAIN[10][16]	MAIN[10][17]	MAIN[10][19]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[11][18]	MAIN[11][20]	MAIN[10][20]	MAIN[11][17]	MAIN[11][19]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[9][18]	MAIN[8][16]	MAIN[9][16]	MAIN[9][17]	MAIN[9][19]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[8][18]	MAIN[8][20]	MAIN[9][20]	MAIN[8][17]	MAIN[8][19]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[6][18]	MAIN[7][16]	MAIN[6][16]	MAIN[6][17]	MAIN[6][19]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[7][18]	MAIN[7][20]	MAIN[6][20]	MAIN[7][17]	MAIN[7][19]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[5][18]	MAIN[4][16]	MAIN[5][16]	MAIN[5][17]	MAIN[5][19]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[4][18]	MAIN[4][20]	MAIN[5][20]	MAIN[4][17]	MAIN[4][19]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[2][18]	MAIN[3][16]	MAIN[2][16]	MAIN[2][17]	MAIN[2][19]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[3][18]	MAIN[3][20]	MAIN[2][20]	MAIN[3][17]	MAIN[3][19]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[1][18]	MAIN[0][16]	MAIN[1][16]	MAIN[1][17]	MAIN[1][19]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[0][18]	MAIN[0][20]	MAIN[1][20]	MAIN[0][17]	MAIN[0][19]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	OUT_LC_WS[0]	OUT_LC_WS[1]	OUT_LC_WS[2]	OUT_LC_WS[3]	OUT_LC_WS[4]	OUT_LC_WS[5]	OUT_LC_WS[6]	OUT_LC_WS[7]
0	0	1	1	1	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H1[0]	QUAD_H1[1]	QUAD_H1[2]	QUAD_H1[3]
0	1	0	0	1	OUT_LC_ES[0]	OUT_LC_ES[1]	OUT_LC_ES[2]	OUT_LC_ES[3]	OUT_LC_ES[4]	OUT_LC_ES[5]	OUT_LC_ES[6]	OUT_LC_ES[7]
0	1	0	1	1	QUAD_H2[0]	QUAD_H2[1]	QUAD_H2[2]	QUAD_H2[3]	QUAD_H3[0]	QUAD_H3[1]	QUAD_H3[2]	QUAD_H3[3]
0	1	1	0	1	OUT_LC_S[0]	OUT_LC_S[1]	OUT_LC_S[2]	OUT_LC_S[3]	OUT_LC_S[4]	OUT_LC_S[5]	OUT_LC_S[6]	OUT_LC_S[7]
0	1	1	1	1	LONG_V11[1]	LONG_V11[0]	LONG_V10[0]	LONG_V10[1]	LONG_V9[1]	LONG_V9[0]	LONG_V8[0]	LONG_V8[1]
1	0	0	0	1	LONG_V7[1]	LONG_V7[0]	LONG_V6[0]	LONG_V6[1]	LONG_V5[1]	LONG_V5[0]	LONG_V4[0]	LONG_V4[1]
1	0	0	1	1	QUAD_V2[4]	QUAD_V2[5]	QUAD_V2[6]	QUAD_V2[7]	QUAD_V2[8]	QUAD_V2[9]	QUAD_V2[10]	QUAD_V2[11]
1	0	1	0	1	LONG_V3[1]	LONG_V3[0]	LONG_V2[0]	LONG_V2[1]	LONG_V1[1]	LONG_V1[0]	LONG_V0[0]	LONG_V0[1]
1	0	1	1	1	QUAD_V1[1]	QUAD_V1[0]	QUAD_V1[3]	QUAD_V1[2]	QUAD_V1[5]	QUAD_V1[4]	QUAD_V1[7]	QUAD_V1[6]
1	1	0	0	1	QUAD_V3[1]	QUAD_V3[0]	QUAD_V3[3]	QUAD_V3[2]	QUAD_V3[5]	QUAD_V3[4]	QUAD_V3[7]	QUAD_V3[6]
1	1	0	1	1	QUAD_V1[9]	QUAD_V1[8]	QUAD_V1[11]	QUAD_V1[10]	QUAD_V0[0]	QUAD_V0[1]	QUAD_V0[2]	QUAD_V0[3]
1	1	1	0	1	QUAD_V3[9]	QUAD_V3[8]	QUAD_V3[11]	QUAD_V3[10]	QUAD_V2[0]	QUAD_V2[1]	QUAD_V2[2]	QUAD_V2[3]
1	1	1	1	1	QUAD_V0[4]	QUAD_V0[5]	QUAD_V0[6]	QUAD_V0[7]	QUAD_V0[8]	QUAD_V0[9]	QUAD_V0[10]	QUAD_V0[11]

siliconblue IOI_S_T04 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[5][36]	MAIN[5][37]	MAIN[4][36]	MAIN[4][37]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[1]
0	0	1	1	GLOBAL[3]
0	1	0	1	GLOBAL[5]
0	1	1	1	GLOBAL[7]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_S_T04 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[11][34]	MAIN[11][35]	MAIN[10][34]	MAIN[10][35]	IMUX_IO_DOUT0[0]	-
MAIN[4][34]	MAIN[4][35]	MAIN[5][34]	MAIN[5][35]	-	IMUX_IO_DOUT0[1]
MAIN[7][33]	MAIN[7][32]	MAIN[6][32]	MAIN[6][33]	-	IMUX_IO_DOUT1[0]
MAIN[0][33]	MAIN[0][32]	MAIN[1][32]	MAIN[1][33]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_S_T04 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[11][33]	MAIN[11][32]	MAIN[10][32]	MAIN[10][33]	IMUX_IO_OE[0]	-
MAIN[4][33]	MAIN[4][32]	MAIN[5][32]	MAIN[5][33]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_S_T04 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[7][35]	MAIN[7][36]	MAIN[7][34]	MAIN[6][34]	MAIN[6][37]	IMUX_IO_ICLK	-
MAIN[0][35]	MAIN[0][36]	MAIN[0][34]	MAIN[1][34]	MAIN[1][37]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_S_T04 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[10][36]	MAIN[10][37]	MAIN[11][36]	MAIN[11][37]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_S_T04 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_S_T04 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[13][5]	MAIN[2][5]
PIN_TYPE bit 1	MAIN[13][4]	MAIN[2][4]
PIN_TYPE bit 2	MAIN[15][5]	MAIN[4][5]
PIN_TYPE bit 3	MAIN[15][4]	MAIN[4][4]
PIN_TYPE bit 4	MAIN[11][4]	MAIN[0][4]
PIN_TYPE bit 5	MAIN[11][5]	MAIN[0][5]
OUTPUT_ENABLE	!MAIN[1][36]	!MAIN[0][37]

Bel wires

siliconblue IOI_S_T04 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_S_T04 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17	B18	B19	B20	B21	B22	B23	B24	B25	B26	B27	B28	B29	B30	B31	B32	B33	B34	B35	B36	B37	B38	B39	B40	B41
F0	-	-	-	-	IOI[1]: PIN_TYPE bit 4	IOI[1]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 3	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 3	-	-	INT: buffer QUAD_H1[3] ← OUT_LC[3]	-	INT: buffer QUAD_H2[3] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 3	IOI[1]: ! OUTPUT_ENABLE	-	-	-	-
F1	-	-	-	-	-	INT: buffer LONG_V0[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 2	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[7] bit 2	-	-	INT: buffer QUAD_V0[10] ← OUT_LC[3]	-	INT: buffer QUAD_H0[3] ← OUT_LC[3]	INT: buffer QUAD_H3[3] ← OUT_LC[3]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_OCLK bit 1	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	IOI[0]: ! OUTPUT_ENABLE	INT: mux IMUX_IO_OCLK bit 0	-	-	-	-
F2	-	-	-	-	IOI[1]: PIN_TYPE bit 1	IOI[1]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 2	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[5] bit 2	-	-	INT: buffer QUAD_V3[7] ← OUT_LC[3]	-	INT: buffer QUAD_V2[2] ← OUT_LC[3]	INT: buffer QUAD_V0[2] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux QUAD_V0[7] bit 1	INT: mux QUAD_V0[7] bit 0	INT: mux QUAD_H0[3] bit 1	INT: mux QUAD_H0[3] bit 0	-	-	-	-	-
F3	-	-	-	-	-	INT: buffer LONG_V4[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 3	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 3	-	-	INT: buffer QUAD_V2[10] ← OUT_LC[3]	-	INT: buffer QUAD_V1[7] ← OUT_LC[3]	-	-	-	-	-	-	-	INT: mux QUAD_H4[3] bit 0	INT: mux QUAD_H4[3] bit 1	INT: mux QUAD_V2[7] bit 1	INT: mux QUAD_V2[7] bit 0	-	-	-	-	-
F4	-	-	-	-	IOI[1]: PIN_TYPE bit 3	IOI[1]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 3	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 3	-	-	INT: buffer QUAD_H1[2] ← OUT_LC[2]	-	INT: buffer QUAD_H2[2] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 2	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_CE bit 1	INT: mux IMUX_CE bit 0	-	-	-	-
F5	-	-	-	-	-	INT: buffer LONG_V8[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 2	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[3] bit 2	-	-	INT: buffer QUAD_V0[8] ← OUT_LC[2]	-	INT: buffer QUAD_H0[2] ← OUT_LC[2]	INT: buffer QUAD_H3[2] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_CE bit 3	INT: mux IMUX_CE bit 2	-	-	-	-
F6	-	-	-	-	INT: buffer LONG_V9[1] ← OUT_LC[2]	INT: buffer LONG_V5[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 2	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[1] bit 2	-	-	INT: buffer QUAD_V3[5] ← OUT_LC[2]	-	INT: buffer QUAD_V2[0] ← OUT_LC[2]	INT: buffer QUAD_V0[0] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_ICLK bit 1	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	-	INT: mux IMUX_IO_ICLK bit 0	-	-	-	-
F7	-	-	-	-	INT: buffer LONG_V1[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 3	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 3	-	-	INT: buffer QUAD_V2[8] ← OUT_LC[2]	-	INT: buffer QUAD_V1[5] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 3	-	-	-	-	-
F8	-	-	-	-	INT: buffer LONG_V2[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 3	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 3	-	-	INT: buffer QUAD_H1[1] ← OUT_LC[1]	-	INT: buffer QUAD_H2[1] ← OUT_LC[1]	-	-	-	-	-	-	-	INT: mux QUAD_H4[2] bit 0	INT: mux QUAD_H4[2] bit 1	INT: mux QUAD_V2[1] bit 1	INT: mux QUAD_V2[1] bit 0	-	-	-	-	-
F9	-	-	-	-	INT: buffer LONG_V10[0] ← OUT_LC[1]	INT: buffer LONG_V6[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 2	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[7] bit 2	-	-	INT: buffer QUAD_V0[6] ← OUT_LC[1]	-	INT: buffer QUAD_H0[1] ← OUT_LC[1]	INT: buffer QUAD_H3[1] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux QUAD_V0[1] bit 1	INT: mux QUAD_V0[1] bit 0	INT: mux QUAD_H0[2] bit 1	INT: mux QUAD_H0[2] bit 0	-	-	-	-	-
F10	-	-	-	-	-	INT: buffer LONG_V3[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 2	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[5] bit 2	-	-	INT: buffer QUAD_V3[3] ← OUT_LC[1]	-	INT: buffer QUAD_V3[11] ← OUT_LC[1]	INT: buffer QUAD_V1[11] ← OUT_LC[1]	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_EXTRA bit 2	-	-	-	-
F11	-	-	-	-	IOI[0]: PIN_TYPE bit 4	IOI[0]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 3	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 3	-	-	INT: buffer QUAD_V2[6] ← OUT_LC[1]	-	INT: buffer QUAD_V1[3] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 2	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_EXTRA bit 0	-	-	-	-
F12	-	-	-	-	-	INT: buffer LONG_V7[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 3	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 3	-	-	INT: buffer QUAD_H1[0] ← OUT_LC[0]	-	INT: buffer QUAD_H2[0] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[1] bit 0	INT: mux QUAD_H4[1] bit 1	INT: mux QUAD_V3[6] bit 1	INT: mux QUAD_V3[6] bit 0	-	-	-	-	-
F13	-	-	-	-	IOI[0]: PIN_TYPE bit 1	IOI[0]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 2	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[3] bit 2	-	-	INT: buffer QUAD_V0[4] ← OUT_LC[0]	-	INT: buffer QUAD_H0[0] ← OUT_LC[0]	INT: buffer QUAD_H3[0] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V1[6] bit 1	INT: mux QUAD_V1[6] bit 0	INT: mux QUAD_H0[1] bit 1	INT: mux QUAD_H0[1] bit 0	-	-	-	-	-
F14	-	-	-	-	-	INT: buffer LONG_V11[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 2	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[1] bit 2	-	-	INT: buffer QUAD_V3[1] ← OUT_LC[0]	-	INT: buffer QUAD_V3[9] ← OUT_LC[0]	INT: buffer QUAD_V1[9] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V1[0] bit 1	INT: mux QUAD_V1[0] bit 0	INT: mux QUAD_H0[0] bit 1	INT: mux QUAD_H0[0] bit 0	-	-	-	-	-
F15	-	-	-	-	IOI[0]: PIN_TYPE bit 3	IOI[0]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 3	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 3	-	-	INT: buffer QUAD_V2[4] ← OUT_LC[0]	-	INT: buffer QUAD_V1[1] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[0] bit 0	INT: mux QUAD_H4[0] bit 1	INT: mux QUAD_V3[0] bit 1	INT: mux QUAD_V3[0] bit 0	-	-	-	-	-

Tile IOI_N_T04

Cells: 1

Switchbox INT

siliconblue IOI_N_T04 switchbox INT programmable buffers
Destination	Source	Bit
QUAD_H0[0]	OUT_LC[0]	MAIN[2][25]
QUAD_H0[1]	OUT_LC[1]	MAIN[6][25]
QUAD_H0[2]	OUT_LC[2]	MAIN[10][25]
QUAD_H0[3]	OUT_LC[3]	MAIN[14][25]
QUAD_H1[0]	OUT_LC[0]	MAIN[3][23]
QUAD_H1[1]	OUT_LC[1]	MAIN[7][23]
QUAD_H1[2]	OUT_LC[2]	MAIN[11][23]
QUAD_H1[3]	OUT_LC[3]	MAIN[15][23]
QUAD_H2[0]	OUT_LC[0]	MAIN[3][25]
QUAD_H2[1]	OUT_LC[1]	MAIN[7][25]
QUAD_H2[2]	OUT_LC[2]	MAIN[11][25]
QUAD_H2[3]	OUT_LC[3]	MAIN[15][25]
QUAD_H3[0]	OUT_LC[0]	MAIN[2][26]
QUAD_H3[1]	OUT_LC[1]	MAIN[6][26]
QUAD_H3[2]	OUT_LC[2]	MAIN[10][26]
QUAD_H3[3]	OUT_LC[3]	MAIN[14][26]
QUAD_V1[0]	OUT_LC[2]	MAIN[9][26]
QUAD_V1[2]	OUT_LC[3]	MAIN[13][26]
QUAD_V1[4]	OUT_LC[0]	MAIN[2][23]
QUAD_V1[6]	OUT_LC[1]	MAIN[6][23]
QUAD_V1[8]	OUT_LC[2]	MAIN[10][23]
QUAD_V1[10]	OUT_LC[3]	MAIN[14][23]
QUAD_V2[1]	OUT_LC[0]	MAIN[0][25]
QUAD_V2[3]	OUT_LC[1]	MAIN[4][25]
QUAD_V2[5]	OUT_LC[2]	MAIN[8][25]
QUAD_V2[7]	OUT_LC[3]	MAIN[12][25]
QUAD_V2[9]	OUT_LC[0]	MAIN[1][26]
QUAD_V2[11]	OUT_LC[1]	MAIN[5][26]
QUAD_V3[0]	OUT_LC[2]	MAIN[9][25]
QUAD_V3[2]	OUT_LC[3]	MAIN[13][25]
QUAD_V3[4]	OUT_LC[0]	MAIN[0][23]
QUAD_V3[6]	OUT_LC[1]	MAIN[4][23]
QUAD_V3[8]	OUT_LC[2]	MAIN[8][23]
QUAD_V3[10]	OUT_LC[3]	MAIN[12][23]
QUAD_V4[1]	OUT_LC[0]	MAIN[1][23]
QUAD_V4[3]	OUT_LC[1]	MAIN[5][23]
QUAD_V4[5]	OUT_LC[2]	MAIN[9][23]
QUAD_V4[7]	OUT_LC[3]	MAIN[13][23]
QUAD_V4[9]	OUT_LC[0]	MAIN[1][25]
QUAD_V4[11]	OUT_LC[1]	MAIN[5][25]
LONG_V1[0]	OUT_LC[3]	MAIN[14][5]
LONG_V2[1]	OUT_LC[2]	MAIN[8][4]
LONG_V3[0]	OUT_LC[1]	MAIN[7][4]
LONG_V4[1]	OUT_LC[0]	MAIN[5][5]
LONG_V5[0]	OUT_LC[3]	MAIN[12][5]
LONG_V6[1]	OUT_LC[2]	MAIN[9][5]
LONG_V7[0]	OUT_LC[1]	MAIN[6][5]
LONG_V8[1]	OUT_LC[0]	MAIN[3][5]
LONG_V9[0]	OUT_LC[3]	MAIN[10][5]
LONG_V10[1]	OUT_LC[2]	MAIN[9][4]
LONG_V11[0]	OUT_LC[1]	MAIN[6][4]
LONG_V12[1]	OUT_LC[0]	MAIN[1][5]

siliconblue IOI_N_T04 switchbox INT programmable inverters
Destination	Source	Bit
IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK	MAIN[9][35]
IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK	MAIN[14][35]

siliconblue IOI_N_T04 switchbox INT muxes QUAD_H
Bits		Destination
MAIN[1][35]	MAIN[1][36]	QUAD_H0[0]	-	-	-	-	-	-	-
MAIN[2][35]	MAIN[2][36]	-	QUAD_H0[1]	-	-	-	-	-	-
MAIN[6][35]	MAIN[6][36]	-	-	QUAD_H0[2]	-	-	-	-	-
MAIN[13][35]	MAIN[13][36]	-	-	-	QUAD_H0[3]	-	-	-	-
MAIN[0][34]	MAIN[0][33]	-	-	-	-	QUAD_H4[0]	-	-	-
MAIN[3][34]	MAIN[3][33]	-	-	-	-	-	QUAD_H4[1]	-	-
MAIN[7][34]	MAIN[7][33]	-	-	-	-	-	-	QUAD_H4[2]	-
MAIN[12][34]	MAIN[12][33]	-	-	-	-	-	-	-	QUAD_H4[3]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H4[0]	QUAD_H4[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]
1	0	QUAD_V2[0]	QUAD_V2[6]	QUAD_V1[1]	QUAD_V1[7]	QUAD_V2[0]	QUAD_V2[6]	QUAD_V1[1]	QUAD_V1[7]
1	1	QUAD_V4[0]	QUAD_V4[6]	QUAD_V3[1]	QUAD_V3[7]	QUAD_V4[0]	QUAD_V4[6]	QUAD_V3[1]	QUAD_V3[7]

siliconblue IOI_N_T04 switchbox INT muxes QUAD_V
Bits		Destination
MAIN[6][33]	MAIN[6][34]	QUAD_V1[1]	-	-	-	-	-	-	-
MAIN[13][33]	MAIN[13][34]	-	QUAD_V1[7]	-	-	-	-	-	-
MAIN[1][33]	MAIN[1][34]	-	-	QUAD_V2[0]	-	-	-	-	-
MAIN[2][33]	MAIN[2][34]	-	-	-	QUAD_V2[6]	-	-	-	-
MAIN[7][35]	MAIN[7][36]	-	-	-	-	QUAD_V3[1]	-	-	-
MAIN[12][35]	MAIN[12][36]	-	-	-	-	-	QUAD_V3[7]	-	-
MAIN[0][35]	MAIN[0][36]	-	-	-	-	-	-	QUAD_V4[0]	-
MAIN[3][35]	MAIN[3][36]	-	-	-	-	-	-	-	QUAD_V4[6]
		Source
0	0	off	off	off	off	off	off	off	off
0	1	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]
1	0	QUAD_H4[2]	QUAD_H4[3]	QUAD_H4[0]	QUAD_H4[1]	QUAD_V1[1]	QUAD_V1[7]	QUAD_V2[0]	QUAD_V2[6]
1	1	QUAD_V3[1]	QUAD_V3[7]	QUAD_V4[0]	QUAD_V4[6]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H0[0]	QUAD_H0[1]

siliconblue IOI_N_T04 switchbox INT muxes LOCAL
Bits					Destination
MAIN[1][18]	MAIN[0][16]	MAIN[1][16]	MAIN[1][17]	MAIN[1][19]	LOCAL_0[0]	-	-	-	-	-	-	-
MAIN[0][18]	MAIN[0][20]	MAIN[1][20]	MAIN[0][17]	MAIN[0][19]	-	LOCAL_0[1]	-	-	-	-	-	-
MAIN[2][18]	MAIN[3][16]	MAIN[2][16]	MAIN[2][17]	MAIN[2][19]	-	-	LOCAL_0[2]	-	-	-	-	-
MAIN[3][18]	MAIN[3][20]	MAIN[2][20]	MAIN[3][17]	MAIN[3][19]	-	-	-	LOCAL_0[3]	-	-	-	-
MAIN[5][18]	MAIN[4][16]	MAIN[5][16]	MAIN[5][17]	MAIN[5][19]	-	-	-	-	LOCAL_0[4]	-	-	-
MAIN[4][18]	MAIN[4][20]	MAIN[5][20]	MAIN[4][17]	MAIN[4][19]	-	-	-	-	-	LOCAL_0[5]	-	-
MAIN[6][18]	MAIN[7][16]	MAIN[6][16]	MAIN[6][17]	MAIN[6][19]	-	-	-	-	-	-	LOCAL_0[6]	-
MAIN[7][18]	MAIN[7][20]	MAIN[6][20]	MAIN[7][17]	MAIN[7][19]	-	-	-	-	-	-	-	LOCAL_0[7]
MAIN[9][18]	MAIN[8][16]	MAIN[9][16]	MAIN[9][17]	MAIN[9][19]	LOCAL_1[0]	-	-	-	-	-	-	-
MAIN[8][18]	MAIN[8][20]	MAIN[9][20]	MAIN[8][17]	MAIN[8][19]	-	LOCAL_1[1]	-	-	-	-	-	-
MAIN[10][18]	MAIN[11][16]	MAIN[10][16]	MAIN[10][17]	MAIN[10][19]	-	-	LOCAL_1[2]	-	-	-	-	-
MAIN[11][18]	MAIN[11][20]	MAIN[10][20]	MAIN[11][17]	MAIN[11][19]	-	-	-	LOCAL_1[3]	-	-	-	-
MAIN[13][18]	MAIN[12][16]	MAIN[13][16]	MAIN[13][17]	MAIN[13][19]	-	-	-	-	LOCAL_1[4]	-	-	-
MAIN[12][18]	MAIN[12][20]	MAIN[13][20]	MAIN[12][17]	MAIN[12][19]	-	-	-	-	-	LOCAL_1[5]	-	-
MAIN[14][18]	MAIN[15][16]	MAIN[14][16]	MAIN[14][17]	MAIN[14][19]	-	-	-	-	-	-	LOCAL_1[6]	-
MAIN[15][18]	MAIN[15][20]	MAIN[14][20]	MAIN[15][17]	MAIN[15][19]	-	-	-	-	-	-	-	LOCAL_1[7]
					Source
0	0	0	0	0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0	TIE_0
0	0	0	1	1	OUT_LC_WN[0]	OUT_LC_WN[1]	OUT_LC_WN[2]	OUT_LC_WN[3]	OUT_LC_WN[4]	OUT_LC_WN[5]	OUT_LC_WN[6]	OUT_LC_WN[7]
0	0	1	1	1	QUAD_H0[0]	QUAD_H0[1]	QUAD_H0[2]	QUAD_H0[3]	QUAD_H1[0]	QUAD_H1[1]	QUAD_H1[2]	QUAD_H1[3]
0	1	0	0	1	OUT_LC_EN[0]	OUT_LC_EN[1]	OUT_LC_EN[2]	OUT_LC_EN[3]	OUT_LC_EN[4]	OUT_LC_EN[5]	OUT_LC_EN[6]	OUT_LC_EN[7]
0	1	0	1	1	QUAD_H2[0]	QUAD_H2[1]	QUAD_H2[2]	QUAD_H2[3]	QUAD_H3[0]	QUAD_H3[1]	QUAD_H3[2]	QUAD_H3[3]
0	1	1	0	1	OUT_LC_N[0]	OUT_LC_N[1]	OUT_LC_N[2]	OUT_LC_N[3]	OUT_LC_N[4]	OUT_LC_N[5]	OUT_LC_N[6]	OUT_LC_N[7]
0	1	1	1	1	LONG_V12[1]	LONG_V12[0]	LONG_V11[0]	LONG_V11[1]	LONG_V10[1]	LONG_V10[0]	LONG_V9[0]	LONG_V9[1]
1	0	0	0	1	LONG_V8[1]	LONG_V8[0]	LONG_V7[0]	LONG_V7[1]	LONG_V6[1]	LONG_V6[0]	LONG_V5[0]	LONG_V5[1]
1	0	0	1	1	QUAD_V3[4]	QUAD_V3[5]	QUAD_V3[6]	QUAD_V3[7]	QUAD_V3[8]	QUAD_V3[9]	QUAD_V3[10]	QUAD_V3[11]
1	0	1	0	1	LONG_V4[1]	LONG_V4[0]	LONG_V3[0]	LONG_V3[1]	LONG_V2[1]	LONG_V2[0]	LONG_V1[0]	LONG_V1[1]
1	0	1	1	1	QUAD_V2[1]	QUAD_V2[0]	QUAD_V2[3]	QUAD_V2[2]	QUAD_V2[5]	QUAD_V2[4]	QUAD_V2[7]	QUAD_V2[6]
1	1	0	0	1	QUAD_V4[1]	QUAD_V4[0]	QUAD_V4[3]	QUAD_V4[2]	QUAD_V4[5]	QUAD_V4[4]	QUAD_V4[7]	QUAD_V4[6]
1	1	0	1	1	QUAD_V2[9]	QUAD_V2[8]	QUAD_V2[11]	QUAD_V2[10]	QUAD_V1[0]	QUAD_V1[1]	QUAD_V1[2]	QUAD_V1[3]
1	1	1	0	1	QUAD_V4[9]	QUAD_V4[8]	QUAD_V4[11]	QUAD_V4[10]	QUAD_V3[0]	QUAD_V3[1]	QUAD_V3[2]	QUAD_V3[3]
1	1	1	1	1	QUAD_V1[4]	QUAD_V1[5]	QUAD_V1[6]	QUAD_V1[7]	QUAD_V1[8]	QUAD_V1[9]	QUAD_V1[10]	QUAD_V1[11]

siliconblue IOI_N_T04 switchbox INT muxes IMUX_CE
Bits				Destination
MAIN[10][36]	MAIN[10][37]	MAIN[11][36]	MAIN[11][37]	IMUX_CE
				Source
0	0	0	0	TIE_1
0	0	0	1	GLOBAL[1]
0	0	1	1	GLOBAL[3]
0	1	0	1	GLOBAL[5]
0	1	1	1	GLOBAL[7]
1	0	0	1	LOCAL_0[2]
1	0	1	1	LOCAL_0[5]
1	1	0	1	LOCAL_1[2]
1	1	1	1	LOCAL_1[5]

siliconblue IOI_N_T04 switchbox INT muxes IMUX_IO_DOUT
Bits				Destination
MAIN[4][34]	MAIN[4][35]	MAIN[5][34]	MAIN[5][35]	IMUX_IO_DOUT0[0]	-
MAIN[11][34]	MAIN[11][35]	MAIN[10][34]	MAIN[10][35]	-	IMUX_IO_DOUT0[1]
MAIN[8][33]	MAIN[8][32]	MAIN[9][32]	MAIN[9][33]	-	IMUX_IO_DOUT1[0]
MAIN[15][33]	MAIN[15][32]	MAIN[14][32]	MAIN[14][33]	IMUX_IO_DOUT1[1]	-
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
0	0	1	1	LOCAL_0[2]	LOCAL_0[3]
0	1	0	1	LOCAL_0[4]	LOCAL_0[5]
0	1	1	1	LOCAL_0[6]	LOCAL_0[7]
1	0	0	1	LOCAL_1[1]	LOCAL_1[0]
1	0	1	1	LOCAL_1[3]	LOCAL_1[2]
1	1	0	1	LOCAL_1[5]	LOCAL_1[4]
1	1	1	1	LOCAL_1[7]	LOCAL_1[6]

siliconblue IOI_N_T04 switchbox INT muxes IMUX_IO_OE
Bits				Destination
MAIN[4][33]	MAIN[4][32]	MAIN[5][32]	MAIN[5][33]	IMUX_IO_OE[0]	-
MAIN[11][33]	MAIN[11][32]	MAIN[10][32]	MAIN[10][33]	-	IMUX_IO_OE[1]
				Source
0	0	0	0	TIE_0	TIE_0
0	0	0	1	LOCAL_0[1]	LOCAL_0[0]
0	0	1	1	LOCAL_0[3]	LOCAL_0[2]
0	1	0	1	LOCAL_0[5]	LOCAL_0[4]
0	1	1	1	LOCAL_0[7]	LOCAL_0[6]
1	0	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	LOCAL_1[2]	LOCAL_1[3]
1	1	0	1	LOCAL_1[4]	LOCAL_1[5]
1	1	1	1	LOCAL_1[6]	LOCAL_1[7]

siliconblue IOI_N_T04 switchbox INT muxes IMUX_IO_CLK
Bits					Destination
MAIN[8][35]	MAIN[8][36]	MAIN[8][34]	MAIN[9][34]	MAIN[9][37]	IMUX_IO_ICLK	-
MAIN[15][35]	MAIN[15][36]	MAIN[15][34]	MAIN[14][34]	MAIN[14][37]	-	IMUX_IO_OCLK
					Source
0	0	0	0	0	TIE_0	TIE_0
0	0	0	0	1	GLOBAL[0]	GLOBAL[0]
0	0	0	1	1	GLOBAL[1]	GLOBAL[1]
0	0	1	0	1	GLOBAL[2]	GLOBAL[2]
0	0	1	1	1	GLOBAL[3]	GLOBAL[3]
0	1	0	0	1	GLOBAL[4]	GLOBAL[4]
0	1	0	1	1	GLOBAL[5]	GLOBAL[5]
0	1	1	0	1	GLOBAL[6]	GLOBAL[6]
0	1	1	1	1	GLOBAL[7]	GLOBAL[7]
1	0	0	0	1	LOCAL_0[0]	LOCAL_0[1]
1	0	0	1	1	LOCAL_0[3]	LOCAL_0[4]
1	0	1	0	1	LOCAL_1[0]	LOCAL_1[1]
1	0	1	1	1	LOCAL_1[3]	LOCAL_1[4]

siliconblue IOI_N_T04 switchbox INT muxes IMUX_IO_EXTRA
Bits				Destination
MAIN[5][36]	MAIN[5][37]	MAIN[4][36]	MAIN[4][37]	IMUX_IO_EXTRA
				Source
0	0	0	0	TIE_0
0	0	0	1	LOCAL_0[1]
0	0	1	1	LOCAL_0[3]
0	1	0	1	LOCAL_0[5]
0	1	1	1	LOCAL_0[7]
1	0	0	1	LOCAL_1[0]
1	0	1	1	LOCAL_1[2]
1	1	0	1	LOCAL_1[4]
1	1	1	1	LOCAL_1[6]

Bels IOI

siliconblue IOI_N_T04 bel IOI pins
Pin	Direction	IOI[0]	IOI[1]
DOUT0	in	IMUX_IO_DOUT0[0]	IMUX_IO_DOUT0[1]
DOUT1	in	IMUX_IO_DOUT1[0]	IMUX_IO_DOUT1[1]
OE	in	IMUX_IO_OE[0]	IMUX_IO_OE[1]
IOB_DIN	in	IOB_DIN[0]	IOB_DIN[1]
CE	in	IMUX_CE	IMUX_CE
ICLK	in	IMUX_IO_ICLK_OPTINV	IMUX_IO_ICLK_OPTINV
OCLK	in	IMUX_IO_OCLK_OPTINV	IMUX_IO_OCLK_OPTINV
LATCH	in	IO_LATCH	IO_LATCH
DIN0	out	OUT_LC[0], OUT_LC[4]	OUT_LC[2], OUT_LC[6]
DIN1	out	OUT_LC[1], OUT_LC[5]	OUT_LC[3], OUT_LC[7]
IOB_DOUT	out	IOB_DOUT[0]	IOB_DOUT[1]

siliconblue IOI_N_T04 bel IOI attribute bits
Attribute	IOI[0]	IOI[1]
PIN_TYPE bit 0	MAIN[2][5]	MAIN[13][5]
PIN_TYPE bit 1	MAIN[2][4]	MAIN[13][4]
PIN_TYPE bit 2	MAIN[0][5]	MAIN[11][5]
PIN_TYPE bit 3	MAIN[0][4]	MAIN[11][4]
PIN_TYPE bit 4	MAIN[4][4]	MAIN[15][4]
PIN_TYPE bit 5	MAIN[4][5]	MAIN[15][5]
OUTPUT_ENABLE	!MAIN[14][36]	!MAIN[15][37]

Bel wires

siliconblue IOI_N_T04 bel wires
Wire	Pins
IMUX_CE	IOI[0].CE, IOI[1].CE
IMUX_IO_DOUT0[0]	IOI[0].DOUT0
IMUX_IO_DOUT0[1]	IOI[1].DOUT0
IMUX_IO_DOUT1[0]	IOI[0].DOUT1
IMUX_IO_DOUT1[1]	IOI[1].DOUT1
IMUX_IO_OE[0]	IOI[0].OE
IMUX_IO_OE[1]	IOI[1].OE
IMUX_IO_ICLK_OPTINV	IOI[0].ICLK, IOI[1].ICLK
IMUX_IO_OCLK_OPTINV	IOI[0].OCLK, IOI[1].OCLK
OUT_LC[0]	IOI[0].DIN0
OUT_LC[1]	IOI[0].DIN1
OUT_LC[2]	IOI[1].DIN0
OUT_LC[3]	IOI[1].DIN1
OUT_LC[4]	IOI[0].DIN0
OUT_LC[5]	IOI[0].DIN1
OUT_LC[6]	IOI[1].DIN0
OUT_LC[7]	IOI[1].DIN1
IO_LATCH	IOI[0].LATCH, IOI[1].LATCH
IOB_DIN[0]	IOI[0].IOB_DIN
IOB_DIN[1]	IOI[1].IOB_DIN
IOB_DOUT[0]	IOI[0].IOB_DOUT
IOB_DOUT[1]	IOI[1].IOB_DOUT

Bitstream

siliconblue IOI_N_T04 rect MAIN
Frame	Bit
Frame	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11	B12	B13	B14	B15	B16	B17	B18	B19	B20	B21	B22	B23	B24	B25	B26	B27	B28	B29	B30	B31	B32	B33	B34	B35	B36	B37	B38	B39	B40	B41
F0	-	-	-	-	IOI[0]: PIN_TYPE bit 3	IOI[0]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 3	INT: mux LOCAL_0[1] bit 1	INT: mux LOCAL_0[1] bit 4	INT: mux LOCAL_0[1] bit 0	INT: mux LOCAL_0[1] bit 3	-	-	INT: buffer QUAD_V3[4] ← OUT_LC[0]	-	INT: buffer QUAD_V2[1] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[0] bit 0	INT: mux QUAD_H4[0] bit 1	INT: mux QUAD_V4[0] bit 1	INT: mux QUAD_V4[0] bit 0	-	-	-	-	-
F1	-	-	-	-	-	INT: buffer LONG_V12[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[0] bit 2	INT: mux LOCAL_0[0] bit 1	INT: mux LOCAL_0[0] bit 4	INT: mux LOCAL_0[0] bit 0	INT: mux LOCAL_0[1] bit 2	-	-	INT: buffer QUAD_V4[1] ← OUT_LC[0]	-	INT: buffer QUAD_V4[9] ← OUT_LC[0]	INT: buffer QUAD_V2[9] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V2[0] bit 1	INT: mux QUAD_V2[0] bit 0	INT: mux QUAD_H0[0] bit 1	INT: mux QUAD_H0[0] bit 0	-	-	-	-	-
F2	-	-	-	-	IOI[0]: PIN_TYPE bit 1	IOI[0]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 2	INT: mux LOCAL_0[2] bit 1	INT: mux LOCAL_0[2] bit 4	INT: mux LOCAL_0[2] bit 0	INT: mux LOCAL_0[3] bit 2	-	-	INT: buffer QUAD_V1[4] ← OUT_LC[0]	-	INT: buffer QUAD_H0[0] ← OUT_LC[0]	INT: buffer QUAD_H3[0] ← OUT_LC[0]	-	-	-	-	-	-	INT: mux QUAD_V2[6] bit 1	INT: mux QUAD_V2[6] bit 0	INT: mux QUAD_H0[1] bit 1	INT: mux QUAD_H0[1] bit 0	-	-	-	-	-
F3	-	-	-	-	-	INT: buffer LONG_V8[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[2] bit 3	INT: mux LOCAL_0[3] bit 1	INT: mux LOCAL_0[3] bit 4	INT: mux LOCAL_0[3] bit 0	INT: mux LOCAL_0[3] bit 3	-	-	INT: buffer QUAD_H1[0] ← OUT_LC[0]	-	INT: buffer QUAD_H2[0] ← OUT_LC[0]	-	-	-	-	-	-	-	INT: mux QUAD_H4[1] bit 0	INT: mux QUAD_H4[1] bit 1	INT: mux QUAD_V4[6] bit 1	INT: mux QUAD_V4[6] bit 0	-	-	-	-	-
F4	-	-	-	-	IOI[0]: PIN_TYPE bit 4	IOI[0]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 3	INT: mux LOCAL_0[5] bit 1	INT: mux LOCAL_0[5] bit 4	INT: mux LOCAL_0[5] bit 0	INT: mux LOCAL_0[5] bit 3	-	-	INT: buffer QUAD_V3[6] ← OUT_LC[1]	-	INT: buffer QUAD_V2[3] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 2	INT: mux IMUX_IO_OE[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 3	INT: mux IMUX_IO_DOUT0[0] bit 2	INT: mux IMUX_IO_EXTRA bit 1	INT: mux IMUX_IO_EXTRA bit 0	-	-	-	-
F5	-	-	-	-	-	INT: buffer LONG_V4[1] ← OUT_LC[0]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[4] bit 2	INT: mux LOCAL_0[4] bit 1	INT: mux LOCAL_0[4] bit 4	INT: mux LOCAL_0[4] bit 0	INT: mux LOCAL_0[5] bit 2	-	-	INT: buffer QUAD_V4[3] ← OUT_LC[1]	-	INT: buffer QUAD_V4[11] ← OUT_LC[1]	INT: buffer QUAD_V2[11] ← OUT_LC[1]	-	-	-	-	-	INT: mux IMUX_IO_OE[0] bit 1	INT: mux IMUX_IO_OE[0] bit 0	INT: mux IMUX_IO_DOUT0[0] bit 1	INT: mux IMUX_IO_DOUT0[0] bit 0	INT: mux IMUX_IO_EXTRA bit 3	INT: mux IMUX_IO_EXTRA bit 2	-	-	-	-
F6	-	-	-	-	INT: buffer LONG_V11[0] ← OUT_LC[1]	INT: buffer LONG_V7[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 2	INT: mux LOCAL_0[6] bit 1	INT: mux LOCAL_0[6] bit 4	INT: mux LOCAL_0[6] bit 0	INT: mux LOCAL_0[7] bit 2	-	-	INT: buffer QUAD_V1[6] ← OUT_LC[1]	-	INT: buffer QUAD_H0[1] ← OUT_LC[1]	INT: buffer QUAD_H3[1] ← OUT_LC[1]	-	-	-	-	-	-	INT: mux QUAD_V1[1] bit 1	INT: mux QUAD_V1[1] bit 0	INT: mux QUAD_H0[2] bit 1	INT: mux QUAD_H0[2] bit 0	-	-	-	-	-
F7	-	-	-	-	INT: buffer LONG_V3[0] ← OUT_LC[1]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_0[6] bit 3	INT: mux LOCAL_0[7] bit 1	INT: mux LOCAL_0[7] bit 4	INT: mux LOCAL_0[7] bit 0	INT: mux LOCAL_0[7] bit 3	-	-	INT: buffer QUAD_H1[1] ← OUT_LC[1]	-	INT: buffer QUAD_H2[1] ← OUT_LC[1]	-	-	-	-	-	-	-	INT: mux QUAD_H4[2] bit 0	INT: mux QUAD_H4[2] bit 1	INT: mux QUAD_V3[1] bit 1	INT: mux QUAD_V3[1] bit 0	-	-	-	-	-
F8	-	-	-	-	INT: buffer LONG_V2[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 3	INT: mux LOCAL_1[1] bit 1	INT: mux LOCAL_1[1] bit 4	INT: mux LOCAL_1[1] bit 0	INT: mux LOCAL_1[1] bit 3	-	-	INT: buffer QUAD_V3[8] ← OUT_LC[2]	-	INT: buffer QUAD_V2[5] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 2	INT: mux IMUX_IO_DOUT1[0] bit 3	INT: mux IMUX_IO_ICLK bit 2	INT: mux IMUX_IO_ICLK bit 4	INT: mux IMUX_IO_ICLK bit 3	-	-	-	-	-
F9	-	-	-	-	INT: buffer LONG_V10[1] ← OUT_LC[2]	INT: buffer LONG_V6[1] ← OUT_LC[2]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[0] bit 2	INT: mux LOCAL_1[0] bit 1	INT: mux LOCAL_1[0] bit 4	INT: mux LOCAL_1[0] bit 0	INT: mux LOCAL_1[1] bit 2	-	-	INT: buffer QUAD_V4[5] ← OUT_LC[2]	-	INT: buffer QUAD_V3[0] ← OUT_LC[2]	INT: buffer QUAD_V1[0] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[0] bit 1	INT: mux IMUX_IO_DOUT1[0] bit 0	INT: mux IMUX_IO_ICLK bit 1	INT: invert IMUX_IO_ICLK_OPTINV ← IMUX_IO_ICLK	-	INT: mux IMUX_IO_ICLK bit 0	-	-	-	-
F10	-	-	-	-	-	INT: buffer LONG_V9[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 2	INT: mux LOCAL_1[2] bit 1	INT: mux LOCAL_1[2] bit 4	INT: mux LOCAL_1[2] bit 0	INT: mux LOCAL_1[3] bit 2	-	-	INT: buffer QUAD_V1[8] ← OUT_LC[2]	-	INT: buffer QUAD_H0[2] ← OUT_LC[2]	INT: buffer QUAD_H3[2] ← OUT_LC[2]	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 1	INT: mux IMUX_IO_OE[1] bit 0	INT: mux IMUX_IO_DOUT0[1] bit 1	INT: mux IMUX_IO_DOUT0[1] bit 0	INT: mux IMUX_CE bit 3	INT: mux IMUX_CE bit 2	-	-	-	-
F11	-	-	-	-	IOI[1]: PIN_TYPE bit 3	IOI[1]: PIN_TYPE bit 2	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[2] bit 3	INT: mux LOCAL_1[3] bit 1	INT: mux LOCAL_1[3] bit 4	INT: mux LOCAL_1[3] bit 0	INT: mux LOCAL_1[3] bit 3	-	-	INT: buffer QUAD_H1[2] ← OUT_LC[2]	-	INT: buffer QUAD_H2[2] ← OUT_LC[2]	-	-	-	-	-	-	INT: mux IMUX_IO_OE[1] bit 2	INT: mux IMUX_IO_OE[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 3	INT: mux IMUX_IO_DOUT0[1] bit 2	INT: mux IMUX_CE bit 1	INT: mux IMUX_CE bit 0	-	-	-	-
F12	-	-	-	-	-	INT: buffer LONG_V5[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 3	INT: mux LOCAL_1[5] bit 1	INT: mux LOCAL_1[5] bit 4	INT: mux LOCAL_1[5] bit 0	INT: mux LOCAL_1[5] bit 3	-	-	INT: buffer QUAD_V3[10] ← OUT_LC[3]	-	INT: buffer QUAD_V2[7] ← OUT_LC[3]	-	-	-	-	-	-	-	INT: mux QUAD_H4[3] bit 0	INT: mux QUAD_H4[3] bit 1	INT: mux QUAD_V3[7] bit 1	INT: mux QUAD_V3[7] bit 0	-	-	-	-	-
F13	-	-	-	-	IOI[1]: PIN_TYPE bit 1	IOI[1]: PIN_TYPE bit 0	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[4] bit 2	INT: mux LOCAL_1[4] bit 1	INT: mux LOCAL_1[4] bit 4	INT: mux LOCAL_1[4] bit 0	INT: mux LOCAL_1[5] bit 2	-	-	INT: buffer QUAD_V4[7] ← OUT_LC[3]	-	INT: buffer QUAD_V3[2] ← OUT_LC[3]	INT: buffer QUAD_V1[2] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux QUAD_V1[7] bit 1	INT: mux QUAD_V1[7] bit 0	INT: mux QUAD_H0[3] bit 1	INT: mux QUAD_H0[3] bit 0	-	-	-	-	-
F14	-	-	-	-	-	INT: buffer LONG_V1[0] ← OUT_LC[3]	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 2	INT: mux LOCAL_1[6] bit 1	INT: mux LOCAL_1[6] bit 4	INT: mux LOCAL_1[6] bit 0	INT: mux LOCAL_1[7] bit 2	-	-	INT: buffer QUAD_V1[10] ← OUT_LC[3]	-	INT: buffer QUAD_H0[3] ← OUT_LC[3]	INT: buffer QUAD_H3[3] ← OUT_LC[3]	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 1	INT: mux IMUX_IO_DOUT1[1] bit 0	INT: mux IMUX_IO_OCLK bit 1	INT: invert IMUX_IO_OCLK_OPTINV ← IMUX_IO_OCLK	IOI[0]: ! OUTPUT_ENABLE	INT: mux IMUX_IO_OCLK bit 0	-	-	-	-
F15	-	-	-	-	IOI[1]: PIN_TYPE bit 4	IOI[1]: PIN_TYPE bit 5	-	-	-	-	-	-	-	-	-	-	INT: mux LOCAL_1[6] bit 3	INT: mux LOCAL_1[7] bit 1	INT: mux LOCAL_1[7] bit 4	INT: mux LOCAL_1[7] bit 0	INT: mux LOCAL_1[7] bit 3	-	-	INT: buffer QUAD_H1[3] ← OUT_LC[3]	-	INT: buffer QUAD_H2[3] ← OUT_LC[3]	-	-	-	-	-	-	INT: mux IMUX_IO_DOUT1[1] bit 2	INT: mux IMUX_IO_DOUT1[1] bit 3	INT: mux IMUX_IO_OCLK bit 2	INT: mux IMUX_IO_OCLK bit 4	INT: mux IMUX_IO_OCLK bit 3	IOI[1]: ! OUTPUT_ENABLE	-	-	-	-

Tile IO_LATCH

Cells: 1

Switchbox IO_LATCH

siliconblue IO_LATCH switchbox IO_LATCH
Destination	Source	Kind
IO_LATCH	IMUX_IO_EXTRA	fixed buffer

Keyboard shortcuts

Project Combine