RF ADC
Tile HSADC
Cells: 60
Bel BUFG_GT0
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.5.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.19.DELAY |
Bel BUFG_GT1
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.6.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.21.DELAY |
Bel BUFG_GT2
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.29.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.5.DELAY |
Bel BUFG_GT3
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.9.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.6.DELAY |
Bel BUFG_GT4
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.10.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.29.DELAY |
Bel BUFG_GT5
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.11.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.9.DELAY |
Bel BUFG_GT6
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.13.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.10.DELAY |
Bel BUFG_GT7
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.42.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.11.DELAY |
Bel BUFG_GT8
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.44.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.13.DELAY |
Bel BUFG_GT9
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.46.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.42.DELAY |
Bel BUFG_GT10
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.1.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.44.DELAY |
Bel BUFG_GT11
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.19.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.46.DELAY |
Bel BUFG_GT12
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.21.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.1.DELAY |
Bel BUFG_GT13
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.5.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.19.DELAY |
Bel BUFG_GT14
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.6.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.21.DELAY |
Bel BUFG_GT15
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.29.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.5.DELAY |
Bel BUFG_GT16
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.9.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.6.DELAY |
Bel BUFG_GT17
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.10.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.29.DELAY |
Bel BUFG_GT18
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.11.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.9.DELAY |
Bel BUFG_GT19
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.13.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.10.DELAY |
Bel BUFG_GT20
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.42.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.11.DELAY |
Bel BUFG_GT21
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.44.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.13.DELAY |
Bel BUFG_GT22
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.46.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.42.DELAY |
Bel BUFG_GT23
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL16:IMUX.IMUX.1.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.44.DELAY |
Bel BUFG_GT_SYNC0
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL12:IMUX.IMUX.1.DELAY |
| RST_IN | input | TCELL13:IMUX.IMUX.21.DELAY |
Bel BUFG_GT_SYNC1
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL12:IMUX.IMUX.19.DELAY |
| RST_IN | input | TCELL13:IMUX.IMUX.5.DELAY |
Bel BUFG_GT_SYNC2
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL12:IMUX.IMUX.21.DELAY |
| RST_IN | input | TCELL13:IMUX.IMUX.6.DELAY |
Bel BUFG_GT_SYNC3
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL12:IMUX.IMUX.5.DELAY |
| RST_IN | input | TCELL13:IMUX.IMUX.29.DELAY |
Bel BUFG_GT_SYNC4
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC5
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC6
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC7
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC8
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC9
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC10
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC11
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC12
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC13
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC14
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL13:IMUX.IMUX.19.DELAY |
| CLK_IN | input | TCELL30:RCLK.IMUX.17 |
| RST_IN | input | TCELL14:IMUX.IMUX.21.DELAY |
Bel ABUS_SWITCH_GT0
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.10.DELAY |
Bel ABUS_SWITCH_GT1
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.10.DELAY |
Bel ABUS_SWITCH_GT2
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.10.DELAY |
Bel ABUS_SWITCH_GT3
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.10.DELAY |
Bel ABUS_SWITCH_GT4
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.11.DELAY |
Bel HSADC
| Pin | Direction | Wires |
|---|---|---|
| CLK_FIFO_LM | input | TCELL33:IMUX.CTRL.5 |
| CONTROL_ADC0_0 | input | TCELL0:IMUX.IMUX.23.DELAY |
| CONTROL_ADC0_1 | input | TCELL0:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_10 | input | TCELL6:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_11 | input | TCELL7:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_12 | input | TCELL8:IMUX.IMUX.23.DELAY |
| CONTROL_ADC0_13 | input | TCELL8:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_14 | input | TCELL9:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_15 | input | TCELL10:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_2 | input | TCELL1:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_3 | input | TCELL2:IMUX.IMUX.23.DELAY |
| CONTROL_ADC0_4 | input | TCELL2:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_5 | input | TCELL3:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_6 | input | TCELL4:IMUX.IMUX.23.DELAY |
| CONTROL_ADC0_7 | input | TCELL4:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_8 | input | TCELL5:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_9 | input | TCELL6:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_0 | input | TCELL11:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_1 | input | TCELL11:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_10 | input | TCELL17:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_11 | input | TCELL18:IMUX.IMUX.8.DELAY |
| CONTROL_ADC1_12 | input | TCELL19:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_13 | input | TCELL19:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_14 | input | TCELL20:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_15 | input | TCELL20:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_2 | input | TCELL12:IMUX.IMUX.8.DELAY |
| CONTROL_ADC1_3 | input | TCELL13:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_4 | input | TCELL13:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_5 | input | TCELL14:IMUX.IMUX.8.DELAY |
| CONTROL_ADC1_6 | input | TCELL15:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_7 | input | TCELL15:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_8 | input | TCELL16:IMUX.IMUX.8.DELAY |
| CONTROL_ADC1_9 | input | TCELL17:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_0 | input | TCELL39:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_1 | input | TCELL39:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_10 | input | TCELL45:IMUX.IMUX.8.DELAY |
| CONTROL_ADC2_11 | input | TCELL46:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_12 | input | TCELL46:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_13 | input | TCELL47:IMUX.IMUX.8.DELAY |
| CONTROL_ADC2_14 | input | TCELL48:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_15 | input | TCELL48:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_2 | input | TCELL40:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_3 | input | TCELL40:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_4 | input | TCELL41:IMUX.IMUX.8.DELAY |
| CONTROL_ADC2_5 | input | TCELL42:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_6 | input | TCELL42:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_7 | input | TCELL43:IMUX.IMUX.8.DELAY |
| CONTROL_ADC2_8 | input | TCELL44:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_9 | input | TCELL44:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_0 | input | TCELL49:IMUX.IMUX.23.DELAY |
| CONTROL_ADC3_1 | input | TCELL49:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_10 | input | TCELL55:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_11 | input | TCELL56:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_12 | input | TCELL57:IMUX.IMUX.23.DELAY |
| CONTROL_ADC3_13 | input | TCELL57:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_14 | input | TCELL58:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_15 | input | TCELL59:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_2 | input | TCELL50:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_3 | input | TCELL51:IMUX.IMUX.23.DELAY |
| CONTROL_ADC3_4 | input | TCELL51:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_5 | input | TCELL52:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_6 | input | TCELL53:IMUX.IMUX.23.DELAY |
| CONTROL_ADC3_7 | input | TCELL53:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_8 | input | TCELL54:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_9 | input | TCELL55:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON0 | input | TCELL21:IMUX.IMUX.8.DELAY |
| CONTROL_COMMON1 | input | TCELL22:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON10 | input | TCELL36:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON11 | input | TCELL36:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON12 | input | TCELL37:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON13 | input | TCELL37:IMUX.IMUX.8.DELAY |
| CONTROL_COMMON14 | input | TCELL37:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON15 | input | TCELL38:IMUX.IMUX.8.DELAY |
| CONTROL_COMMON2 | input | TCELL22:IMUX.IMUX.8.DELAY |
| CONTROL_COMMON3 | input | TCELL22:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON4 | input | TCELL23:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON5 | input | TCELL23:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON6 | input | TCELL24:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON7 | input | TCELL24:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON8 | input | TCELL35:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON9 | input | TCELL35:IMUX.IMUX.12.DELAY |
| DADDR0 | input | TCELL30:IMUX.IMUX.8.DELAY |
| DADDR1 | input | TCELL30:IMUX.IMUX.12.DELAY |
| DADDR10 | input | TCELL33:IMUX.IMUX.12.DELAY |
| DADDR11 | input | TCELL34:IMUX.IMUX.12.DELAY |
| DADDR2 | input | TCELL31:IMUX.IMUX.23.DELAY |
| DADDR3 | input | TCELL31:IMUX.IMUX.8.DELAY |
| DADDR4 | input | TCELL31:IMUX.IMUX.12.DELAY |
| DADDR5 | input | TCELL32:IMUX.IMUX.23.DELAY |
| DADDR6 | input | TCELL32:IMUX.IMUX.8.DELAY |
| DADDR7 | input | TCELL32:IMUX.IMUX.12.DELAY |
| DADDR8 | input | TCELL33:IMUX.IMUX.23.DELAY |
| DADDR9 | input | TCELL33:IMUX.IMUX.8.DELAY |
| DATA_ADC0_0 | output | TCELL0:OUT.2.TMIN |
| DATA_ADC0_1 | output | TCELL0:OUT.6.TMIN |
| DATA_ADC0_10 | output | TCELL1:OUT.6.TMIN |
| DATA_ADC0_100 | output | TCELL11:OUT.26.TMIN |
| DATA_ADC0_101 | output | TCELL11:OUT.30.TMIN |
| DATA_ADC0_102 | output | TCELL12:OUT.2.TMIN |
| DATA_ADC0_103 | output | TCELL12:OUT.6.TMIN |
| DATA_ADC0_104 | output | TCELL12:OUT.10.TMIN |
| DATA_ADC0_105 | output | TCELL12:OUT.13.TMIN |
| DATA_ADC0_106 | output | TCELL12:OUT.16.TMIN |
| DATA_ADC0_107 | output | TCELL12:OUT.19.TMIN |
| DATA_ADC0_108 | output | TCELL12:OUT.22.TMIN |
| DATA_ADC0_109 | output | TCELL12:OUT.26.TMIN |
| DATA_ADC0_11 | output | TCELL1:OUT.10.TMIN |
| DATA_ADC0_110 | output | TCELL12:OUT.30.TMIN |
| DATA_ADC0_111 | output | TCELL13:OUT.2.TMIN |
| DATA_ADC0_112 | output | TCELL13:OUT.6.TMIN |
| DATA_ADC0_113 | output | TCELL13:OUT.10.TMIN |
| DATA_ADC0_114 | output | TCELL13:OUT.14.TMIN |
| DATA_ADC0_115 | output | TCELL13:OUT.18.TMIN |
| DATA_ADC0_116 | output | TCELL13:OUT.22.TMIN |
| DATA_ADC0_117 | output | TCELL13:OUT.26.TMIN |
| DATA_ADC0_118 | output | TCELL13:OUT.30.TMIN |
| DATA_ADC0_119 | output | TCELL14:OUT.2.TMIN |
| DATA_ADC0_12 | output | TCELL1:OUT.14.TMIN |
| DATA_ADC0_120 | output | TCELL14:OUT.6.TMIN |
| DATA_ADC0_121 | output | TCELL14:OUT.10.TMIN |
| DATA_ADC0_122 | output | TCELL14:OUT.13.TMIN |
| DATA_ADC0_123 | output | TCELL14:OUT.16.TMIN |
| DATA_ADC0_124 | output | TCELL14:OUT.19.TMIN |
| DATA_ADC0_125 | output | TCELL14:OUT.22.TMIN |
| DATA_ADC0_126 | output | TCELL14:OUT.26.TMIN |
| DATA_ADC0_127 | output | TCELL14:OUT.30.TMIN |
| DATA_ADC0_13 | output | TCELL1:OUT.18.TMIN |
| DATA_ADC0_14 | output | TCELL1:OUT.22.TMIN |
| DATA_ADC0_15 | output | TCELL1:OUT.26.TMIN |
| DATA_ADC0_16 | output | TCELL1:OUT.30.TMIN |
| DATA_ADC0_17 | output | TCELL2:OUT.2.TMIN |
| DATA_ADC0_18 | output | TCELL2:OUT.6.TMIN |
| DATA_ADC0_19 | output | TCELL2:OUT.10.TMIN |
| DATA_ADC0_2 | output | TCELL0:OUT.10.TMIN |
| DATA_ADC0_20 | output | TCELL2:OUT.13.TMIN |
| DATA_ADC0_21 | output | TCELL2:OUT.16.TMIN |
| DATA_ADC0_22 | output | TCELL2:OUT.19.TMIN |
| DATA_ADC0_23 | output | TCELL2:OUT.22.TMIN |
| DATA_ADC0_24 | output | TCELL2:OUT.26.TMIN |
| DATA_ADC0_25 | output | TCELL2:OUT.30.TMIN |
| DATA_ADC0_26 | output | TCELL3:OUT.2.TMIN |
| DATA_ADC0_27 | output | TCELL3:OUT.6.TMIN |
| DATA_ADC0_28 | output | TCELL3:OUT.10.TMIN |
| DATA_ADC0_29 | output | TCELL3:OUT.14.TMIN |
| DATA_ADC0_3 | output | TCELL0:OUT.13.TMIN |
| DATA_ADC0_30 | output | TCELL3:OUT.18.TMIN |
| DATA_ADC0_31 | output | TCELL3:OUT.22.TMIN |
| DATA_ADC0_32 | output | TCELL3:OUT.26.TMIN |
| DATA_ADC0_33 | output | TCELL3:OUT.30.TMIN |
| DATA_ADC0_34 | output | TCELL4:OUT.2.TMIN |
| DATA_ADC0_35 | output | TCELL4:OUT.6.TMIN |
| DATA_ADC0_36 | output | TCELL4:OUT.10.TMIN |
| DATA_ADC0_37 | output | TCELL4:OUT.13.TMIN |
| DATA_ADC0_38 | output | TCELL4:OUT.16.TMIN |
| DATA_ADC0_39 | output | TCELL4:OUT.19.TMIN |
| DATA_ADC0_4 | output | TCELL0:OUT.16.TMIN |
| DATA_ADC0_40 | output | TCELL4:OUT.22.TMIN |
| DATA_ADC0_41 | output | TCELL4:OUT.26.TMIN |
| DATA_ADC0_42 | output | TCELL4:OUT.30.TMIN |
| DATA_ADC0_43 | output | TCELL5:OUT.2.TMIN |
| DATA_ADC0_44 | output | TCELL5:OUT.6.TMIN |
| DATA_ADC0_45 | output | TCELL5:OUT.10.TMIN |
| DATA_ADC0_46 | output | TCELL5:OUT.14.TMIN |
| DATA_ADC0_47 | output | TCELL5:OUT.18.TMIN |
| DATA_ADC0_48 | output | TCELL5:OUT.22.TMIN |
| DATA_ADC0_49 | output | TCELL5:OUT.26.TMIN |
| DATA_ADC0_5 | output | TCELL0:OUT.19.TMIN |
| DATA_ADC0_50 | output | TCELL5:OUT.30.TMIN |
| DATA_ADC0_51 | output | TCELL6:OUT.2.TMIN |
| DATA_ADC0_52 | output | TCELL6:OUT.6.TMIN |
| DATA_ADC0_53 | output | TCELL6:OUT.10.TMIN |
| DATA_ADC0_54 | output | TCELL6:OUT.13.TMIN |
| DATA_ADC0_55 | output | TCELL6:OUT.16.TMIN |
| DATA_ADC0_56 | output | TCELL6:OUT.19.TMIN |
| DATA_ADC0_57 | output | TCELL6:OUT.22.TMIN |
| DATA_ADC0_58 | output | TCELL6:OUT.26.TMIN |
| DATA_ADC0_59 | output | TCELL6:OUT.30.TMIN |
| DATA_ADC0_6 | output | TCELL0:OUT.22.TMIN |
| DATA_ADC0_60 | output | TCELL7:OUT.2.TMIN |
| DATA_ADC0_61 | output | TCELL7:OUT.6.TMIN |
| DATA_ADC0_62 | output | TCELL7:OUT.10.TMIN |
| DATA_ADC0_63 | output | TCELL7:OUT.14.TMIN |
| DATA_ADC0_64 | output | TCELL7:OUT.18.TMIN |
| DATA_ADC0_65 | output | TCELL7:OUT.22.TMIN |
| DATA_ADC0_66 | output | TCELL7:OUT.26.TMIN |
| DATA_ADC0_67 | output | TCELL7:OUT.30.TMIN |
| DATA_ADC0_68 | output | TCELL8:OUT.2.TMIN |
| DATA_ADC0_69 | output | TCELL8:OUT.6.TMIN |
| DATA_ADC0_7 | output | TCELL0:OUT.26.TMIN |
| DATA_ADC0_70 | output | TCELL8:OUT.10.TMIN |
| DATA_ADC0_71 | output | TCELL8:OUT.13.TMIN |
| DATA_ADC0_72 | output | TCELL8:OUT.16.TMIN |
| DATA_ADC0_73 | output | TCELL8:OUT.19.TMIN |
| DATA_ADC0_74 | output | TCELL8:OUT.22.TMIN |
| DATA_ADC0_75 | output | TCELL8:OUT.26.TMIN |
| DATA_ADC0_76 | output | TCELL8:OUT.30.TMIN |
| DATA_ADC0_77 | output | TCELL9:OUT.2.TMIN |
| DATA_ADC0_78 | output | TCELL9:OUT.6.TMIN |
| DATA_ADC0_79 | output | TCELL9:OUT.10.TMIN |
| DATA_ADC0_8 | output | TCELL0:OUT.30.TMIN |
| DATA_ADC0_80 | output | TCELL9:OUT.14.TMIN |
| DATA_ADC0_81 | output | TCELL9:OUT.18.TMIN |
| DATA_ADC0_82 | output | TCELL9:OUT.22.TMIN |
| DATA_ADC0_83 | output | TCELL9:OUT.26.TMIN |
| DATA_ADC0_84 | output | TCELL9:OUT.30.TMIN |
| DATA_ADC0_85 | output | TCELL10:OUT.2.TMIN |
| DATA_ADC0_86 | output | TCELL10:OUT.6.TMIN |
| DATA_ADC0_87 | output | TCELL10:OUT.10.TMIN |
| DATA_ADC0_88 | output | TCELL10:OUT.13.TMIN |
| DATA_ADC0_89 | output | TCELL10:OUT.16.TMIN |
| DATA_ADC0_9 | output | TCELL1:OUT.2.TMIN |
| DATA_ADC0_90 | output | TCELL10:OUT.19.TMIN |
| DATA_ADC0_91 | output | TCELL10:OUT.22.TMIN |
| DATA_ADC0_92 | output | TCELL10:OUT.26.TMIN |
| DATA_ADC0_93 | output | TCELL10:OUT.30.TMIN |
| DATA_ADC0_94 | output | TCELL11:OUT.2.TMIN |
| DATA_ADC0_95 | output | TCELL11:OUT.6.TMIN |
| DATA_ADC0_96 | output | TCELL11:OUT.10.TMIN |
| DATA_ADC0_97 | output | TCELL11:OUT.14.TMIN |
| DATA_ADC0_98 | output | TCELL11:OUT.18.TMIN |
| DATA_ADC0_99 | output | TCELL11:OUT.22.TMIN |
| DATA_ADC1_0 | output | TCELL15:OUT.2.TMIN |
| DATA_ADC1_1 | output | TCELL15:OUT.6.TMIN |
| DATA_ADC1_10 | output | TCELL16:OUT.6.TMIN |
| DATA_ADC1_100 | output | TCELL26:OUT.26.TMIN |
| DATA_ADC1_101 | output | TCELL26:OUT.30.TMIN |
| DATA_ADC1_102 | output | TCELL27:OUT.2.TMIN |
| DATA_ADC1_103 | output | TCELL27:OUT.6.TMIN |
| DATA_ADC1_104 | output | TCELL27:OUT.10.TMIN |
| DATA_ADC1_105 | output | TCELL27:OUT.13.TMIN |
| DATA_ADC1_106 | output | TCELL27:OUT.16.TMIN |
| DATA_ADC1_107 | output | TCELL27:OUT.19.TMIN |
| DATA_ADC1_108 | output | TCELL27:OUT.22.TMIN |
| DATA_ADC1_109 | output | TCELL27:OUT.26.TMIN |
| DATA_ADC1_11 | output | TCELL16:OUT.10.TMIN |
| DATA_ADC1_110 | output | TCELL27:OUT.30.TMIN |
| DATA_ADC1_111 | output | TCELL28:OUT.2.TMIN |
| DATA_ADC1_112 | output | TCELL28:OUT.6.TMIN |
| DATA_ADC1_113 | output | TCELL28:OUT.10.TMIN |
| DATA_ADC1_114 | output | TCELL28:OUT.14.TMIN |
| DATA_ADC1_115 | output | TCELL28:OUT.18.TMIN |
| DATA_ADC1_116 | output | TCELL28:OUT.22.TMIN |
| DATA_ADC1_117 | output | TCELL28:OUT.26.TMIN |
| DATA_ADC1_118 | output | TCELL28:OUT.30.TMIN |
| DATA_ADC1_119 | output | TCELL29:OUT.2.TMIN |
| DATA_ADC1_12 | output | TCELL16:OUT.14.TMIN |
| DATA_ADC1_120 | output | TCELL29:OUT.6.TMIN |
| DATA_ADC1_121 | output | TCELL29:OUT.10.TMIN |
| DATA_ADC1_122 | output | TCELL29:OUT.13.TMIN |
| DATA_ADC1_123 | output | TCELL29:OUT.16.TMIN |
| DATA_ADC1_124 | output | TCELL29:OUT.19.TMIN |
| DATA_ADC1_125 | output | TCELL29:OUT.22.TMIN |
| DATA_ADC1_126 | output | TCELL29:OUT.26.TMIN |
| DATA_ADC1_127 | output | TCELL29:OUT.30.TMIN |
| DATA_ADC1_13 | output | TCELL16:OUT.18.TMIN |
| DATA_ADC1_14 | output | TCELL16:OUT.22.TMIN |
| DATA_ADC1_15 | output | TCELL16:OUT.26.TMIN |
| DATA_ADC1_16 | output | TCELL16:OUT.30.TMIN |
| DATA_ADC1_17 | output | TCELL17:OUT.2.TMIN |
| DATA_ADC1_18 | output | TCELL17:OUT.6.TMIN |
| DATA_ADC1_19 | output | TCELL17:OUT.10.TMIN |
| DATA_ADC1_2 | output | TCELL15:OUT.10.TMIN |
| DATA_ADC1_20 | output | TCELL17:OUT.13.TMIN |
| DATA_ADC1_21 | output | TCELL17:OUT.16.TMIN |
| DATA_ADC1_22 | output | TCELL17:OUT.19.TMIN |
| DATA_ADC1_23 | output | TCELL17:OUT.22.TMIN |
| DATA_ADC1_24 | output | TCELL17:OUT.26.TMIN |
| DATA_ADC1_25 | output | TCELL17:OUT.30.TMIN |
| DATA_ADC1_26 | output | TCELL18:OUT.2.TMIN |
| DATA_ADC1_27 | output | TCELL18:OUT.6.TMIN |
| DATA_ADC1_28 | output | TCELL18:OUT.10.TMIN |
| DATA_ADC1_29 | output | TCELL18:OUT.14.TMIN |
| DATA_ADC1_3 | output | TCELL15:OUT.13.TMIN |
| DATA_ADC1_30 | output | TCELL18:OUT.18.TMIN |
| DATA_ADC1_31 | output | TCELL18:OUT.22.TMIN |
| DATA_ADC1_32 | output | TCELL18:OUT.26.TMIN |
| DATA_ADC1_33 | output | TCELL18:OUT.30.TMIN |
| DATA_ADC1_34 | output | TCELL19:OUT.2.TMIN |
| DATA_ADC1_35 | output | TCELL19:OUT.6.TMIN |
| DATA_ADC1_36 | output | TCELL19:OUT.10.TMIN |
| DATA_ADC1_37 | output | TCELL19:OUT.13.TMIN |
| DATA_ADC1_38 | output | TCELL19:OUT.16.TMIN |
| DATA_ADC1_39 | output | TCELL19:OUT.19.TMIN |
| DATA_ADC1_4 | output | TCELL15:OUT.16.TMIN |
| DATA_ADC1_40 | output | TCELL19:OUT.22.TMIN |
| DATA_ADC1_41 | output | TCELL19:OUT.26.TMIN |
| DATA_ADC1_42 | output | TCELL19:OUT.30.TMIN |
| DATA_ADC1_43 | output | TCELL20:OUT.2.TMIN |
| DATA_ADC1_44 | output | TCELL20:OUT.6.TMIN |
| DATA_ADC1_45 | output | TCELL20:OUT.10.TMIN |
| DATA_ADC1_46 | output | TCELL20:OUT.14.TMIN |
| DATA_ADC1_47 | output | TCELL20:OUT.18.TMIN |
| DATA_ADC1_48 | output | TCELL20:OUT.22.TMIN |
| DATA_ADC1_49 | output | TCELL20:OUT.26.TMIN |
| DATA_ADC1_5 | output | TCELL15:OUT.19.TMIN |
| DATA_ADC1_50 | output | TCELL20:OUT.30.TMIN |
| DATA_ADC1_51 | output | TCELL21:OUT.2.TMIN |
| DATA_ADC1_52 | output | TCELL21:OUT.6.TMIN |
| DATA_ADC1_53 | output | TCELL21:OUT.10.TMIN |
| DATA_ADC1_54 | output | TCELL21:OUT.13.TMIN |
| DATA_ADC1_55 | output | TCELL21:OUT.16.TMIN |
| DATA_ADC1_56 | output | TCELL21:OUT.19.TMIN |
| DATA_ADC1_57 | output | TCELL21:OUT.22.TMIN |
| DATA_ADC1_58 | output | TCELL21:OUT.26.TMIN |
| DATA_ADC1_59 | output | TCELL21:OUT.30.TMIN |
| DATA_ADC1_6 | output | TCELL15:OUT.22.TMIN |
| DATA_ADC1_60 | output | TCELL22:OUT.2.TMIN |
| DATA_ADC1_61 | output | TCELL22:OUT.6.TMIN |
| DATA_ADC1_62 | output | TCELL22:OUT.10.TMIN |
| DATA_ADC1_63 | output | TCELL22:OUT.14.TMIN |
| DATA_ADC1_64 | output | TCELL22:OUT.18.TMIN |
| DATA_ADC1_65 | output | TCELL22:OUT.22.TMIN |
| DATA_ADC1_66 | output | TCELL22:OUT.26.TMIN |
| DATA_ADC1_67 | output | TCELL22:OUT.30.TMIN |
| DATA_ADC1_68 | output | TCELL23:OUT.2.TMIN |
| DATA_ADC1_69 | output | TCELL23:OUT.6.TMIN |
| DATA_ADC1_7 | output | TCELL15:OUT.26.TMIN |
| DATA_ADC1_70 | output | TCELL23:OUT.10.TMIN |
| DATA_ADC1_71 | output | TCELL23:OUT.13.TMIN |
| DATA_ADC1_72 | output | TCELL23:OUT.16.TMIN |
| DATA_ADC1_73 | output | TCELL23:OUT.19.TMIN |
| DATA_ADC1_74 | output | TCELL23:OUT.22.TMIN |
| DATA_ADC1_75 | output | TCELL23:OUT.26.TMIN |
| DATA_ADC1_76 | output | TCELL23:OUT.30.TMIN |
| DATA_ADC1_77 | output | TCELL24:OUT.2.TMIN |
| DATA_ADC1_78 | output | TCELL24:OUT.6.TMIN |
| DATA_ADC1_79 | output | TCELL24:OUT.10.TMIN |
| DATA_ADC1_8 | output | TCELL15:OUT.30.TMIN |
| DATA_ADC1_80 | output | TCELL24:OUT.14.TMIN |
| DATA_ADC1_81 | output | TCELL24:OUT.18.TMIN |
| DATA_ADC1_82 | output | TCELL24:OUT.22.TMIN |
| DATA_ADC1_83 | output | TCELL24:OUT.26.TMIN |
| DATA_ADC1_84 | output | TCELL24:OUT.30.TMIN |
| DATA_ADC1_85 | output | TCELL25:OUT.2.TMIN |
| DATA_ADC1_86 | output | TCELL25:OUT.6.TMIN |
| DATA_ADC1_87 | output | TCELL25:OUT.10.TMIN |
| DATA_ADC1_88 | output | TCELL25:OUT.13.TMIN |
| DATA_ADC1_89 | output | TCELL25:OUT.16.TMIN |
| DATA_ADC1_9 | output | TCELL16:OUT.2.TMIN |
| DATA_ADC1_90 | output | TCELL25:OUT.19.TMIN |
| DATA_ADC1_91 | output | TCELL25:OUT.22.TMIN |
| DATA_ADC1_92 | output | TCELL25:OUT.26.TMIN |
| DATA_ADC1_93 | output | TCELL25:OUT.30.TMIN |
| DATA_ADC1_94 | output | TCELL26:OUT.2.TMIN |
| DATA_ADC1_95 | output | TCELL26:OUT.6.TMIN |
| DATA_ADC1_96 | output | TCELL26:OUT.10.TMIN |
| DATA_ADC1_97 | output | TCELL26:OUT.14.TMIN |
| DATA_ADC1_98 | output | TCELL26:OUT.18.TMIN |
| DATA_ADC1_99 | output | TCELL26:OUT.22.TMIN |
| DATA_ADC2_0 | output | TCELL30:OUT.2.TMIN |
| DATA_ADC2_1 | output | TCELL30:OUT.6.TMIN |
| DATA_ADC2_10 | output | TCELL31:OUT.6.TMIN |
| DATA_ADC2_100 | output | TCELL41:OUT.26.TMIN |
| DATA_ADC2_101 | output | TCELL41:OUT.30.TMIN |
| DATA_ADC2_102 | output | TCELL42:OUT.2.TMIN |
| DATA_ADC2_103 | output | TCELL42:OUT.6.TMIN |
| DATA_ADC2_104 | output | TCELL42:OUT.10.TMIN |
| DATA_ADC2_105 | output | TCELL42:OUT.13.TMIN |
| DATA_ADC2_106 | output | TCELL42:OUT.16.TMIN |
| DATA_ADC2_107 | output | TCELL42:OUT.19.TMIN |
| DATA_ADC2_108 | output | TCELL42:OUT.22.TMIN |
| DATA_ADC2_109 | output | TCELL42:OUT.26.TMIN |
| DATA_ADC2_11 | output | TCELL31:OUT.10.TMIN |
| DATA_ADC2_110 | output | TCELL42:OUT.30.TMIN |
| DATA_ADC2_111 | output | TCELL43:OUT.2.TMIN |
| DATA_ADC2_112 | output | TCELL43:OUT.6.TMIN |
| DATA_ADC2_113 | output | TCELL43:OUT.10.TMIN |
| DATA_ADC2_114 | output | TCELL43:OUT.14.TMIN |
| DATA_ADC2_115 | output | TCELL43:OUT.18.TMIN |
| DATA_ADC2_116 | output | TCELL43:OUT.22.TMIN |
| DATA_ADC2_117 | output | TCELL43:OUT.26.TMIN |
| DATA_ADC2_118 | output | TCELL43:OUT.30.TMIN |
| DATA_ADC2_119 | output | TCELL44:OUT.2.TMIN |
| DATA_ADC2_12 | output | TCELL31:OUT.14.TMIN |
| DATA_ADC2_120 | output | TCELL44:OUT.6.TMIN |
| DATA_ADC2_121 | output | TCELL44:OUT.10.TMIN |
| DATA_ADC2_122 | output | TCELL44:OUT.13.TMIN |
| DATA_ADC2_123 | output | TCELL44:OUT.16.TMIN |
| DATA_ADC2_124 | output | TCELL44:OUT.19.TMIN |
| DATA_ADC2_125 | output | TCELL44:OUT.22.TMIN |
| DATA_ADC2_126 | output | TCELL44:OUT.26.TMIN |
| DATA_ADC2_127 | output | TCELL44:OUT.30.TMIN |
| DATA_ADC2_13 | output | TCELL31:OUT.18.TMIN |
| DATA_ADC2_14 | output | TCELL31:OUT.22.TMIN |
| DATA_ADC2_15 | output | TCELL31:OUT.26.TMIN |
| DATA_ADC2_16 | output | TCELL31:OUT.30.TMIN |
| DATA_ADC2_17 | output | TCELL32:OUT.2.TMIN |
| DATA_ADC2_18 | output | TCELL32:OUT.6.TMIN |
| DATA_ADC2_19 | output | TCELL32:OUT.10.TMIN |
| DATA_ADC2_2 | output | TCELL30:OUT.10.TMIN |
| DATA_ADC2_20 | output | TCELL32:OUT.13.TMIN |
| DATA_ADC2_21 | output | TCELL32:OUT.16.TMIN |
| DATA_ADC2_22 | output | TCELL32:OUT.19.TMIN |
| DATA_ADC2_23 | output | TCELL32:OUT.22.TMIN |
| DATA_ADC2_24 | output | TCELL32:OUT.26.TMIN |
| DATA_ADC2_25 | output | TCELL32:OUT.30.TMIN |
| DATA_ADC2_26 | output | TCELL33:OUT.2.TMIN |
| DATA_ADC2_27 | output | TCELL33:OUT.6.TMIN |
| DATA_ADC2_28 | output | TCELL33:OUT.10.TMIN |
| DATA_ADC2_29 | output | TCELL33:OUT.14.TMIN |
| DATA_ADC2_3 | output | TCELL30:OUT.13.TMIN |
| DATA_ADC2_30 | output | TCELL33:OUT.18.TMIN |
| DATA_ADC2_31 | output | TCELL33:OUT.22.TMIN |
| DATA_ADC2_32 | output | TCELL33:OUT.26.TMIN |
| DATA_ADC2_33 | output | TCELL33:OUT.30.TMIN |
| DATA_ADC2_34 | output | TCELL34:OUT.2.TMIN |
| DATA_ADC2_35 | output | TCELL34:OUT.6.TMIN |
| DATA_ADC2_36 | output | TCELL34:OUT.10.TMIN |
| DATA_ADC2_37 | output | TCELL34:OUT.13.TMIN |
| DATA_ADC2_38 | output | TCELL34:OUT.16.TMIN |
| DATA_ADC2_39 | output | TCELL34:OUT.19.TMIN |
| DATA_ADC2_4 | output | TCELL30:OUT.16.TMIN |
| DATA_ADC2_40 | output | TCELL34:OUT.22.TMIN |
| DATA_ADC2_41 | output | TCELL34:OUT.26.TMIN |
| DATA_ADC2_42 | output | TCELL34:OUT.30.TMIN |
| DATA_ADC2_43 | output | TCELL35:OUT.2.TMIN |
| DATA_ADC2_44 | output | TCELL35:OUT.6.TMIN |
| DATA_ADC2_45 | output | TCELL35:OUT.10.TMIN |
| DATA_ADC2_46 | output | TCELL35:OUT.14.TMIN |
| DATA_ADC2_47 | output | TCELL35:OUT.18.TMIN |
| DATA_ADC2_48 | output | TCELL35:OUT.22.TMIN |
| DATA_ADC2_49 | output | TCELL35:OUT.26.TMIN |
| DATA_ADC2_5 | output | TCELL30:OUT.19.TMIN |
| DATA_ADC2_50 | output | TCELL35:OUT.30.TMIN |
| DATA_ADC2_51 | output | TCELL36:OUT.2.TMIN |
| DATA_ADC2_52 | output | TCELL36:OUT.6.TMIN |
| DATA_ADC2_53 | output | TCELL36:OUT.10.TMIN |
| DATA_ADC2_54 | output | TCELL36:OUT.13.TMIN |
| DATA_ADC2_55 | output | TCELL36:OUT.16.TMIN |
| DATA_ADC2_56 | output | TCELL36:OUT.19.TMIN |
| DATA_ADC2_57 | output | TCELL36:OUT.22.TMIN |
| DATA_ADC2_58 | output | TCELL36:OUT.26.TMIN |
| DATA_ADC2_59 | output | TCELL36:OUT.30.TMIN |
| DATA_ADC2_6 | output | TCELL30:OUT.22.TMIN |
| DATA_ADC2_60 | output | TCELL37:OUT.2.TMIN |
| DATA_ADC2_61 | output | TCELL37:OUT.6.TMIN |
| DATA_ADC2_62 | output | TCELL37:OUT.10.TMIN |
| DATA_ADC2_63 | output | TCELL37:OUT.14.TMIN |
| DATA_ADC2_64 | output | TCELL37:OUT.18.TMIN |
| DATA_ADC2_65 | output | TCELL37:OUT.22.TMIN |
| DATA_ADC2_66 | output | TCELL37:OUT.26.TMIN |
| DATA_ADC2_67 | output | TCELL37:OUT.30.TMIN |
| DATA_ADC2_68 | output | TCELL38:OUT.2.TMIN |
| DATA_ADC2_69 | output | TCELL38:OUT.6.TMIN |
| DATA_ADC2_7 | output | TCELL30:OUT.26.TMIN |
| DATA_ADC2_70 | output | TCELL38:OUT.10.TMIN |
| DATA_ADC2_71 | output | TCELL38:OUT.13.TMIN |
| DATA_ADC2_72 | output | TCELL38:OUT.16.TMIN |
| DATA_ADC2_73 | output | TCELL38:OUT.19.TMIN |
| DATA_ADC2_74 | output | TCELL38:OUT.22.TMIN |
| DATA_ADC2_75 | output | TCELL38:OUT.26.TMIN |
| DATA_ADC2_76 | output | TCELL38:OUT.30.TMIN |
| DATA_ADC2_77 | output | TCELL39:OUT.2.TMIN |
| DATA_ADC2_78 | output | TCELL39:OUT.6.TMIN |
| DATA_ADC2_79 | output | TCELL39:OUT.10.TMIN |
| DATA_ADC2_8 | output | TCELL30:OUT.30.TMIN |
| DATA_ADC2_80 | output | TCELL39:OUT.14.TMIN |
| DATA_ADC2_81 | output | TCELL39:OUT.18.TMIN |
| DATA_ADC2_82 | output | TCELL39:OUT.22.TMIN |
| DATA_ADC2_83 | output | TCELL39:OUT.26.TMIN |
| DATA_ADC2_84 | output | TCELL39:OUT.30.TMIN |
| DATA_ADC2_85 | output | TCELL40:OUT.2.TMIN |
| DATA_ADC2_86 | output | TCELL40:OUT.6.TMIN |
| DATA_ADC2_87 | output | TCELL40:OUT.10.TMIN |
| DATA_ADC2_88 | output | TCELL40:OUT.13.TMIN |
| DATA_ADC2_89 | output | TCELL40:OUT.16.TMIN |
| DATA_ADC2_9 | output | TCELL31:OUT.2.TMIN |
| DATA_ADC2_90 | output | TCELL40:OUT.19.TMIN |
| DATA_ADC2_91 | output | TCELL40:OUT.22.TMIN |
| DATA_ADC2_92 | output | TCELL40:OUT.26.TMIN |
| DATA_ADC2_93 | output | TCELL40:OUT.30.TMIN |
| DATA_ADC2_94 | output | TCELL41:OUT.2.TMIN |
| DATA_ADC2_95 | output | TCELL41:OUT.6.TMIN |
| DATA_ADC2_96 | output | TCELL41:OUT.10.TMIN |
| DATA_ADC2_97 | output | TCELL41:OUT.14.TMIN |
| DATA_ADC2_98 | output | TCELL41:OUT.18.TMIN |
| DATA_ADC2_99 | output | TCELL41:OUT.22.TMIN |
| DATA_ADC3_0 | output | TCELL45:OUT.2.TMIN |
| DATA_ADC3_1 | output | TCELL45:OUT.6.TMIN |
| DATA_ADC3_10 | output | TCELL46:OUT.6.TMIN |
| DATA_ADC3_100 | output | TCELL56:OUT.26.TMIN |
| DATA_ADC3_101 | output | TCELL56:OUT.30.TMIN |
| DATA_ADC3_102 | output | TCELL57:OUT.2.TMIN |
| DATA_ADC3_103 | output | TCELL57:OUT.6.TMIN |
| DATA_ADC3_104 | output | TCELL57:OUT.10.TMIN |
| DATA_ADC3_105 | output | TCELL57:OUT.13.TMIN |
| DATA_ADC3_106 | output | TCELL57:OUT.16.TMIN |
| DATA_ADC3_107 | output | TCELL57:OUT.19.TMIN |
| DATA_ADC3_108 | output | TCELL57:OUT.22.TMIN |
| DATA_ADC3_109 | output | TCELL57:OUT.26.TMIN |
| DATA_ADC3_11 | output | TCELL46:OUT.10.TMIN |
| DATA_ADC3_110 | output | TCELL57:OUT.30.TMIN |
| DATA_ADC3_111 | output | TCELL58:OUT.2.TMIN |
| DATA_ADC3_112 | output | TCELL58:OUT.6.TMIN |
| DATA_ADC3_113 | output | TCELL58:OUT.10.TMIN |
| DATA_ADC3_114 | output | TCELL58:OUT.14.TMIN |
| DATA_ADC3_115 | output | TCELL58:OUT.18.TMIN |
| DATA_ADC3_116 | output | TCELL58:OUT.22.TMIN |
| DATA_ADC3_117 | output | TCELL58:OUT.26.TMIN |
| DATA_ADC3_118 | output | TCELL58:OUT.30.TMIN |
| DATA_ADC3_119 | output | TCELL59:OUT.2.TMIN |
| DATA_ADC3_12 | output | TCELL46:OUT.14.TMIN |
| DATA_ADC3_120 | output | TCELL59:OUT.6.TMIN |
| DATA_ADC3_121 | output | TCELL59:OUT.10.TMIN |
| DATA_ADC3_122 | output | TCELL59:OUT.13.TMIN |
| DATA_ADC3_123 | output | TCELL59:OUT.16.TMIN |
| DATA_ADC3_124 | output | TCELL59:OUT.19.TMIN |
| DATA_ADC3_125 | output | TCELL59:OUT.22.TMIN |
| DATA_ADC3_126 | output | TCELL59:OUT.26.TMIN |
| DATA_ADC3_127 | output | TCELL59:OUT.30.TMIN |
| DATA_ADC3_13 | output | TCELL46:OUT.18.TMIN |
| DATA_ADC3_14 | output | TCELL46:OUT.22.TMIN |
| DATA_ADC3_15 | output | TCELL46:OUT.26.TMIN |
| DATA_ADC3_16 | output | TCELL46:OUT.30.TMIN |
| DATA_ADC3_17 | output | TCELL47:OUT.2.TMIN |
| DATA_ADC3_18 | output | TCELL47:OUT.6.TMIN |
| DATA_ADC3_19 | output | TCELL47:OUT.10.TMIN |
| DATA_ADC3_2 | output | TCELL45:OUT.10.TMIN |
| DATA_ADC3_20 | output | TCELL47:OUT.13.TMIN |
| DATA_ADC3_21 | output | TCELL47:OUT.16.TMIN |
| DATA_ADC3_22 | output | TCELL47:OUT.19.TMIN |
| DATA_ADC3_23 | output | TCELL47:OUT.22.TMIN |
| DATA_ADC3_24 | output | TCELL47:OUT.26.TMIN |
| DATA_ADC3_25 | output | TCELL47:OUT.30.TMIN |
| DATA_ADC3_26 | output | TCELL48:OUT.2.TMIN |
| DATA_ADC3_27 | output | TCELL48:OUT.6.TMIN |
| DATA_ADC3_28 | output | TCELL48:OUT.10.TMIN |
| DATA_ADC3_29 | output | TCELL48:OUT.14.TMIN |
| DATA_ADC3_3 | output | TCELL45:OUT.13.TMIN |
| DATA_ADC3_30 | output | TCELL48:OUT.18.TMIN |
| DATA_ADC3_31 | output | TCELL48:OUT.22.TMIN |
| DATA_ADC3_32 | output | TCELL48:OUT.26.TMIN |
| DATA_ADC3_33 | output | TCELL48:OUT.30.TMIN |
| DATA_ADC3_34 | output | TCELL49:OUT.2.TMIN |
| DATA_ADC3_35 | output | TCELL49:OUT.6.TMIN |
| DATA_ADC3_36 | output | TCELL49:OUT.10.TMIN |
| DATA_ADC3_37 | output | TCELL49:OUT.13.TMIN |
| DATA_ADC3_38 | output | TCELL49:OUT.16.TMIN |
| DATA_ADC3_39 | output | TCELL49:OUT.19.TMIN |
| DATA_ADC3_4 | output | TCELL45:OUT.16.TMIN |
| DATA_ADC3_40 | output | TCELL49:OUT.22.TMIN |
| DATA_ADC3_41 | output | TCELL49:OUT.26.TMIN |
| DATA_ADC3_42 | output | TCELL49:OUT.30.TMIN |
| DATA_ADC3_43 | output | TCELL50:OUT.2.TMIN |
| DATA_ADC3_44 | output | TCELL50:OUT.6.TMIN |
| DATA_ADC3_45 | output | TCELL50:OUT.10.TMIN |
| DATA_ADC3_46 | output | TCELL50:OUT.14.TMIN |
| DATA_ADC3_47 | output | TCELL50:OUT.18.TMIN |
| DATA_ADC3_48 | output | TCELL50:OUT.22.TMIN |
| DATA_ADC3_49 | output | TCELL50:OUT.26.TMIN |
| DATA_ADC3_5 | output | TCELL45:OUT.19.TMIN |
| DATA_ADC3_50 | output | TCELL50:OUT.30.TMIN |
| DATA_ADC3_51 | output | TCELL51:OUT.2.TMIN |
| DATA_ADC3_52 | output | TCELL51:OUT.6.TMIN |
| DATA_ADC3_53 | output | TCELL51:OUT.10.TMIN |
| DATA_ADC3_54 | output | TCELL51:OUT.13.TMIN |
| DATA_ADC3_55 | output | TCELL51:OUT.16.TMIN |
| DATA_ADC3_56 | output | TCELL51:OUT.19.TMIN |
| DATA_ADC3_57 | output | TCELL51:OUT.22.TMIN |
| DATA_ADC3_58 | output | TCELL51:OUT.26.TMIN |
| DATA_ADC3_59 | output | TCELL51:OUT.30.TMIN |
| DATA_ADC3_6 | output | TCELL45:OUT.22.TMIN |
| DATA_ADC3_60 | output | TCELL52:OUT.2.TMIN |
| DATA_ADC3_61 | output | TCELL52:OUT.6.TMIN |
| DATA_ADC3_62 | output | TCELL52:OUT.10.TMIN |
| DATA_ADC3_63 | output | TCELL52:OUT.14.TMIN |
| DATA_ADC3_64 | output | TCELL52:OUT.18.TMIN |
| DATA_ADC3_65 | output | TCELL52:OUT.22.TMIN |
| DATA_ADC3_66 | output | TCELL52:OUT.26.TMIN |
| DATA_ADC3_67 | output | TCELL52:OUT.30.TMIN |
| DATA_ADC3_68 | output | TCELL53:OUT.2.TMIN |
| DATA_ADC3_69 | output | TCELL53:OUT.6.TMIN |
| DATA_ADC3_7 | output | TCELL45:OUT.26.TMIN |
| DATA_ADC3_70 | output | TCELL53:OUT.10.TMIN |
| DATA_ADC3_71 | output | TCELL53:OUT.13.TMIN |
| DATA_ADC3_72 | output | TCELL53:OUT.16.TMIN |
| DATA_ADC3_73 | output | TCELL53:OUT.19.TMIN |
| DATA_ADC3_74 | output | TCELL53:OUT.22.TMIN |
| DATA_ADC3_75 | output | TCELL53:OUT.26.TMIN |
| DATA_ADC3_76 | output | TCELL53:OUT.30.TMIN |
| DATA_ADC3_77 | output | TCELL54:OUT.2.TMIN |
| DATA_ADC3_78 | output | TCELL54:OUT.6.TMIN |
| DATA_ADC3_79 | output | TCELL54:OUT.10.TMIN |
| DATA_ADC3_8 | output | TCELL45:OUT.30.TMIN |
| DATA_ADC3_80 | output | TCELL54:OUT.14.TMIN |
| DATA_ADC3_81 | output | TCELL54:OUT.18.TMIN |
| DATA_ADC3_82 | output | TCELL54:OUT.22.TMIN |
| DATA_ADC3_83 | output | TCELL54:OUT.26.TMIN |
| DATA_ADC3_84 | output | TCELL54:OUT.30.TMIN |
| DATA_ADC3_85 | output | TCELL55:OUT.2.TMIN |
| DATA_ADC3_86 | output | TCELL55:OUT.6.TMIN |
| DATA_ADC3_87 | output | TCELL55:OUT.10.TMIN |
| DATA_ADC3_88 | output | TCELL55:OUT.13.TMIN |
| DATA_ADC3_89 | output | TCELL55:OUT.16.TMIN |
| DATA_ADC3_9 | output | TCELL46:OUT.2.TMIN |
| DATA_ADC3_90 | output | TCELL55:OUT.19.TMIN |
| DATA_ADC3_91 | output | TCELL55:OUT.22.TMIN |
| DATA_ADC3_92 | output | TCELL55:OUT.26.TMIN |
| DATA_ADC3_93 | output | TCELL55:OUT.30.TMIN |
| DATA_ADC3_94 | output | TCELL56:OUT.2.TMIN |
| DATA_ADC3_95 | output | TCELL56:OUT.6.TMIN |
| DATA_ADC3_96 | output | TCELL56:OUT.10.TMIN |
| DATA_ADC3_97 | output | TCELL56:OUT.14.TMIN |
| DATA_ADC3_98 | output | TCELL56:OUT.18.TMIN |
| DATA_ADC3_99 | output | TCELL56:OUT.22.TMIN |
| DCLK | input | TCELL28:IMUX.CTRL.4 |
| DEN | input | TCELL34:IMUX.IMUX.8.DELAY |
| DI0 | input | TCELL25:IMUX.IMUX.23.DELAY |
| DI1 | input | TCELL25:IMUX.IMUX.8.DELAY |
| DI10 | input | TCELL28:IMUX.IMUX.8.DELAY |
| DI11 | input | TCELL28:IMUX.IMUX.12.DELAY |
| DI12 | input | TCELL29:IMUX.IMUX.23.DELAY |
| DI13 | input | TCELL29:IMUX.IMUX.8.DELAY |
| DI14 | input | TCELL29:IMUX.IMUX.12.DELAY |
| DI15 | input | TCELL30:IMUX.IMUX.23.DELAY |
| DI2 | input | TCELL25:IMUX.IMUX.12.DELAY |
| DI3 | input | TCELL26:IMUX.IMUX.23.DELAY |
| DI4 | input | TCELL26:IMUX.IMUX.8.DELAY |
| DI5 | input | TCELL26:IMUX.IMUX.12.DELAY |
| DI6 | input | TCELL27:IMUX.IMUX.23.DELAY |
| DI7 | input | TCELL27:IMUX.IMUX.8.DELAY |
| DI8 | input | TCELL27:IMUX.IMUX.12.DELAY |
| DI9 | input | TCELL28:IMUX.IMUX.23.DELAY |
| DOUT0 | output | TCELL26:OUT.8.TMIN |
| DOUT1 | output | TCELL26:OUT.24.TMIN |
| DOUT10 | output | TCELL31:OUT.8.TMIN |
| DOUT11 | output | TCELL31:OUT.24.TMIN |
| DOUT12 | output | TCELL32:OUT.8.TMIN |
| DOUT13 | output | TCELL32:OUT.24.TMIN |
| DOUT14 | output | TCELL33:OUT.8.TMIN |
| DOUT15 | output | TCELL33:OUT.24.TMIN |
| DOUT2 | output | TCELL27:OUT.8.TMIN |
| DOUT3 | output | TCELL27:OUT.24.TMIN |
| DOUT4 | output | TCELL28:OUT.8.TMIN |
| DOUT5 | output | TCELL28:OUT.24.TMIN |
| DOUT6 | output | TCELL29:OUT.8.TMIN |
| DOUT7 | output | TCELL29:OUT.24.TMIN |
| DOUT8 | output | TCELL30:OUT.8.TMIN |
| DOUT9 | output | TCELL30:OUT.24.TMIN |
| DRDY | output | TCELL29:OUT.28.TMIN |
| DWE | input | TCELL34:IMUX.IMUX.23.DELAY |
| FABRIC_CLK | input | TCELL31:IMUX.CTRL.5 |
| PLL_MONCLK | input | TCELL32:IMUX.CTRL.4 |
| PLL_REFCLK_IN_FABRIC | input | TCELL32:IMUX.CTRL.5 |
| PLL_SCAN_CLK_FD0 | input | TCELL28:IMUX.CTRL.5 |
| PLL_SCAN_CLK_FD1 | input | TCELL31:IMUX.CTRL.4 |
| PLL_SCAN_EN_B_FD | input | TCELL28:IMUX.IMUX.26.DELAY |
| PLL_SCAN_IN_FD0 | input | TCELL31:IMUX.IMUX.26.DELAY |
| PLL_SCAN_IN_FD1 | input | TCELL32:IMUX.IMUX.26.DELAY |
| PLL_SCAN_MODE_B_FD | input | TCELL27:IMUX.IMUX.36.DELAY |
| PLL_SCAN_OUT_B_FD0 | output | TCELL28:OUT.17.TMIN |
| PLL_SCAN_OUT_B_FD1 | output | TCELL31:OUT.17.TMIN |
| PLL_SCAN_RST_EN_FD | input | TCELL33:IMUX.IMUX.26.DELAY |
| STATUS_ADC0_0 | output | TCELL1:OUT.8.TMIN |
| STATUS_ADC0_1 | output | TCELL1:OUT.24.TMIN |
| STATUS_ADC0_10 | output | TCELL6:OUT.4.TMIN |
| STATUS_ADC0_11 | output | TCELL6:OUT.28.TMIN |
| STATUS_ADC0_12 | output | TCELL7:OUT.8.TMIN |
| STATUS_ADC0_13 | output | TCELL7:OUT.24.TMIN |
| STATUS_ADC0_14 | output | TCELL9:OUT.8.TMIN |
| STATUS_ADC0_15 | output | TCELL9:OUT.24.TMIN |
| STATUS_ADC0_2 | output | TCELL2:OUT.4.TMIN |
| STATUS_ADC0_3 | output | TCELL2:OUT.28.TMIN |
| STATUS_ADC0_4 | output | TCELL3:OUT.8.TMIN |
| STATUS_ADC0_5 | output | TCELL3:OUT.24.TMIN |
| STATUS_ADC0_6 | output | TCELL4:OUT.4.TMIN |
| STATUS_ADC0_7 | output | TCELL4:OUT.28.TMIN |
| STATUS_ADC0_8 | output | TCELL5:OUT.8.TMIN |
| STATUS_ADC0_9 | output | TCELL5:OUT.24.TMIN |
| STATUS_ADC1_0 | output | TCELL12:OUT.8.TMIN |
| STATUS_ADC1_1 | output | TCELL12:OUT.24.TMIN |
| STATUS_ADC1_10 | output | TCELL17:OUT.4.TMIN |
| STATUS_ADC1_11 | output | TCELL17:OUT.28.TMIN |
| STATUS_ADC1_12 | output | TCELL18:OUT.8.TMIN |
| STATUS_ADC1_13 | output | TCELL18:OUT.24.TMIN |
| STATUS_ADC1_14 | output | TCELL20:OUT.8.TMIN |
| STATUS_ADC1_15 | output | TCELL20:OUT.24.TMIN |
| STATUS_ADC1_2 | output | TCELL13:OUT.4.TMIN |
| STATUS_ADC1_3 | output | TCELL13:OUT.28.TMIN |
| STATUS_ADC1_4 | output | TCELL14:OUT.8.TMIN |
| STATUS_ADC1_5 | output | TCELL14:OUT.24.TMIN |
| STATUS_ADC1_6 | output | TCELL15:OUT.4.TMIN |
| STATUS_ADC1_7 | output | TCELL15:OUT.28.TMIN |
| STATUS_ADC1_8 | output | TCELL16:OUT.8.TMIN |
| STATUS_ADC1_9 | output | TCELL16:OUT.24.TMIN |
| STATUS_ADC2_0 | output | TCELL40:OUT.4.TMIN |
| STATUS_ADC2_1 | output | TCELL40:OUT.28.TMIN |
| STATUS_ADC2_10 | output | TCELL45:OUT.8.TMIN |
| STATUS_ADC2_11 | output | TCELL45:OUT.24.TMIN |
| STATUS_ADC2_12 | output | TCELL46:OUT.4.TMIN |
| STATUS_ADC2_13 | output | TCELL46:OUT.28.TMIN |
| STATUS_ADC2_14 | output | TCELL47:OUT.8.TMIN |
| STATUS_ADC2_15 | output | TCELL47:OUT.24.TMIN |
| STATUS_ADC2_2 | output | TCELL41:OUT.8.TMIN |
| STATUS_ADC2_3 | output | TCELL41:OUT.24.TMIN |
| STATUS_ADC2_4 | output | TCELL42:OUT.4.TMIN |
| STATUS_ADC2_5 | output | TCELL42:OUT.28.TMIN |
| STATUS_ADC2_6 | output | TCELL43:OUT.8.TMIN |
| STATUS_ADC2_7 | output | TCELL43:OUT.24.TMIN |
| STATUS_ADC2_8 | output | TCELL44:OUT.4.TMIN |
| STATUS_ADC2_9 | output | TCELL44:OUT.28.TMIN |
| STATUS_ADC3_0 | output | TCELL51:OUT.4.TMIN |
| STATUS_ADC3_1 | output | TCELL51:OUT.28.TMIN |
| STATUS_ADC3_10 | output | TCELL56:OUT.8.TMIN |
| STATUS_ADC3_11 | output | TCELL56:OUT.24.TMIN |
| STATUS_ADC3_12 | output | TCELL57:OUT.4.TMIN |
| STATUS_ADC3_13 | output | TCELL57:OUT.28.TMIN |
| STATUS_ADC3_14 | output | TCELL58:OUT.8.TMIN |
| STATUS_ADC3_15 | output | TCELL58:OUT.24.TMIN |
| STATUS_ADC3_2 | output | TCELL52:OUT.8.TMIN |
| STATUS_ADC3_3 | output | TCELL52:OUT.24.TMIN |
| STATUS_ADC3_4 | output | TCELL53:OUT.4.TMIN |
| STATUS_ADC3_5 | output | TCELL53:OUT.28.TMIN |
| STATUS_ADC3_6 | output | TCELL54:OUT.8.TMIN |
| STATUS_ADC3_7 | output | TCELL54:OUT.24.TMIN |
| STATUS_ADC3_8 | output | TCELL55:OUT.4.TMIN |
| STATUS_ADC3_9 | output | TCELL55:OUT.28.TMIN |
| STATUS_COMMON0 | output | TCELL22:OUT.4.TMIN |
| STATUS_COMMON1 | output | TCELL22:OUT.28.TMIN |
| STATUS_COMMON10 | output | TCELL35:OUT.8.TMIN |
| STATUS_COMMON11 | output | TCELL35:OUT.24.TMIN |
| STATUS_COMMON12 | output | TCELL36:OUT.4.TMIN |
| STATUS_COMMON13 | output | TCELL36:OUT.28.TMIN |
| STATUS_COMMON14 | output | TCELL37:OUT.8.TMIN |
| STATUS_COMMON15 | output | TCELL37:OUT.24.TMIN |
| STATUS_COMMON2 | output | TCELL23:OUT.8.TMIN |
| STATUS_COMMON3 | output | TCELL23:OUT.24.TMIN |
| STATUS_COMMON4 | output | TCELL24:OUT.4.TMIN |
| STATUS_COMMON5 | output | TCELL24:OUT.28.TMIN |
| STATUS_COMMON6 | output | TCELL25:OUT.8.TMIN |
| STATUS_COMMON7 | output | TCELL25:OUT.24.TMIN |
| STATUS_COMMON8 | output | TCELL34:OUT.4.TMIN |
| STATUS_COMMON9 | output | TCELL34:OUT.28.TMIN |
| TEST_SCAN_CLK0 | input | TCELL3:IMUX.CTRL.5 |
| TEST_SCAN_CLK1 | input | TCELL17:IMUX.CTRL.5 |
| TEST_SCAN_CLK2 | input | TCELL27:IMUX.CTRL.5 |
| TEST_SCAN_CLK3 | input | TCELL41:IMUX.CTRL.5 |
| TEST_SCAN_CLK4 | input | TCELL54:IMUX.CTRL.5 |
| TEST_SCAN_CTRL0 | input | TCELL22:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL1 | input | TCELL22:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL10 | input | TCELL35:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL11 | input | TCELL35:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL12 | input | TCELL36:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL13 | input | TCELL36:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL14 | input | TCELL37:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL15 | input | TCELL37:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL2 | input | TCELL23:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL3 | input | TCELL23:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL4 | input | TCELL24:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL5 | input | TCELL24:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL6 | input | TCELL25:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL7 | input | TCELL25:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL8 | input | TCELL34:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL9 | input | TCELL34:IMUX.IMUX.36.DELAY |
| TEST_SCAN_MODE_B | input | TCELL31:IMUX.IMUX.36.DELAY |
| TEST_SCAN_RESET | input | TCELL28:IMUX.IMUX.34.DELAY |
| TEST_SE_B | input | TCELL28:IMUX.IMUX.36.DELAY |
| TEST_SI0 | input | TCELL0:IMUX.IMUX.17.DELAY |
| TEST_SI1 | input | TCELL0:IMUX.IMUX.22.DELAY |
| TEST_SI10 | input | TCELL2:IMUX.IMUX.17.DELAY |
| TEST_SI100 | input | TCELL20:IMUX.IMUX.17.DELAY |
| TEST_SI101 | input | TCELL20:IMUX.IMUX.22.DELAY |
| TEST_SI102 | input | TCELL20:IMUX.IMUX.7.DELAY |
| TEST_SI103 | input | TCELL20:IMUX.IMUX.38.DELAY |
| TEST_SI104 | input | TCELL20:IMUX.IMUX.47.DELAY |
| TEST_SI105 | input | TCELL21:IMUX.IMUX.17.DELAY |
| TEST_SI106 | input | TCELL21:IMUX.IMUX.22.DELAY |
| TEST_SI107 | input | TCELL21:IMUX.IMUX.7.DELAY |
| TEST_SI108 | input | TCELL21:IMUX.IMUX.38.DELAY |
| TEST_SI109 | input | TCELL21:IMUX.IMUX.47.DELAY |
| TEST_SI11 | input | TCELL2:IMUX.IMUX.22.DELAY |
| TEST_SI110 | input | TCELL22:IMUX.IMUX.17.DELAY |
| TEST_SI111 | input | TCELL22:IMUX.IMUX.22.DELAY |
| TEST_SI112 | input | TCELL22:IMUX.IMUX.7.DELAY |
| TEST_SI113 | input | TCELL22:IMUX.IMUX.38.DELAY |
| TEST_SI114 | input | TCELL22:IMUX.IMUX.47.DELAY |
| TEST_SI115 | input | TCELL23:IMUX.IMUX.17.DELAY |
| TEST_SI116 | input | TCELL23:IMUX.IMUX.22.DELAY |
| TEST_SI117 | input | TCELL23:IMUX.IMUX.7.DELAY |
| TEST_SI118 | input | TCELL23:IMUX.IMUX.38.DELAY |
| TEST_SI119 | input | TCELL23:IMUX.IMUX.47.DELAY |
| TEST_SI12 | input | TCELL2:IMUX.IMUX.7.DELAY |
| TEST_SI120 | input | TCELL24:IMUX.IMUX.17.DELAY |
| TEST_SI121 | input | TCELL24:IMUX.IMUX.22.DELAY |
| TEST_SI122 | input | TCELL24:IMUX.IMUX.7.DELAY |
| TEST_SI123 | input | TCELL24:IMUX.IMUX.38.DELAY |
| TEST_SI124 | input | TCELL24:IMUX.IMUX.47.DELAY |
| TEST_SI125 | input | TCELL25:IMUX.IMUX.17.DELAY |
| TEST_SI126 | input | TCELL25:IMUX.IMUX.22.DELAY |
| TEST_SI127 | input | TCELL25:IMUX.IMUX.7.DELAY |
| TEST_SI128 | input | TCELL25:IMUX.IMUX.38.DELAY |
| TEST_SI129 | input | TCELL25:IMUX.IMUX.47.DELAY |
| TEST_SI13 | input | TCELL2:IMUX.IMUX.38.DELAY |
| TEST_SI130 | input | TCELL26:IMUX.IMUX.17.DELAY |
| TEST_SI131 | input | TCELL26:IMUX.IMUX.22.DELAY |
| TEST_SI132 | input | TCELL26:IMUX.IMUX.7.DELAY |
| TEST_SI133 | input | TCELL26:IMUX.IMUX.38.DELAY |
| TEST_SI134 | input | TCELL26:IMUX.IMUX.47.DELAY |
| TEST_SI135 | input | TCELL27:IMUX.IMUX.17.DELAY |
| TEST_SI136 | input | TCELL27:IMUX.IMUX.22.DELAY |
| TEST_SI137 | input | TCELL27:IMUX.IMUX.24.DELAY |
| TEST_SI138 | input | TCELL27:IMUX.IMUX.7.DELAY |
| TEST_SI139 | input | TCELL27:IMUX.IMUX.32.DELAY |
| TEST_SI14 | input | TCELL2:IMUX.IMUX.47.DELAY |
| TEST_SI140 | input | TCELL27:IMUX.IMUX.38.DELAY |
| TEST_SI141 | input | TCELL27:IMUX.IMUX.43.DELAY |
| TEST_SI142 | input | TCELL27:IMUX.IMUX.47.DELAY |
| TEST_SI143 | input | TCELL28:IMUX.IMUX.17.DELAY |
| TEST_SI144 | input | TCELL28:IMUX.IMUX.18.DELAY |
| TEST_SI145 | input | TCELL28:IMUX.IMUX.22.DELAY |
| TEST_SI146 | input | TCELL28:IMUX.IMUX.7.DELAY |
| TEST_SI147 | input | TCELL28:IMUX.IMUX.38.DELAY |
| TEST_SI148 | input | TCELL28:IMUX.IMUX.43.DELAY |
| TEST_SI149 | input | TCELL28:IMUX.IMUX.47.DELAY |
| TEST_SI15 | input | TCELL3:IMUX.IMUX.17.DELAY |
| TEST_SI150 | input | TCELL31:IMUX.IMUX.17.DELAY |
| TEST_SI151 | input | TCELL31:IMUX.IMUX.18.DELAY |
| TEST_SI152 | input | TCELL31:IMUX.IMUX.22.DELAY |
| TEST_SI153 | input | TCELL31:IMUX.IMUX.7.DELAY |
| TEST_SI154 | input | TCELL31:IMUX.IMUX.32.DELAY |
| TEST_SI155 | input | TCELL31:IMUX.IMUX.38.DELAY |
| TEST_SI156 | input | TCELL31:IMUX.IMUX.43.DELAY |
| TEST_SI157 | input | TCELL31:IMUX.IMUX.47.DELAY |
| TEST_SI158 | input | TCELL32:IMUX.IMUX.17.DELAY |
| TEST_SI159 | input | TCELL32:IMUX.IMUX.22.DELAY |
| TEST_SI16 | input | TCELL3:IMUX.IMUX.22.DELAY |
| TEST_SI160 | input | TCELL32:IMUX.IMUX.24.DELAY |
| TEST_SI161 | input | TCELL32:IMUX.IMUX.7.DELAY |
| TEST_SI162 | input | TCELL32:IMUX.IMUX.38.DELAY |
| TEST_SI163 | input | TCELL32:IMUX.IMUX.43.DELAY |
| TEST_SI164 | input | TCELL32:IMUX.IMUX.47.DELAY |
| TEST_SI165 | input | TCELL33:IMUX.IMUX.17.DELAY |
| TEST_SI166 | input | TCELL33:IMUX.IMUX.22.DELAY |
| TEST_SI167 | input | TCELL33:IMUX.IMUX.7.DELAY |
| TEST_SI168 | input | TCELL33:IMUX.IMUX.38.DELAY |
| TEST_SI169 | input | TCELL33:IMUX.IMUX.47.DELAY |
| TEST_SI17 | input | TCELL3:IMUX.IMUX.7.DELAY |
| TEST_SI170 | input | TCELL34:IMUX.IMUX.17.DELAY |
| TEST_SI171 | input | TCELL34:IMUX.IMUX.22.DELAY |
| TEST_SI172 | input | TCELL34:IMUX.IMUX.7.DELAY |
| TEST_SI173 | input | TCELL34:IMUX.IMUX.38.DELAY |
| TEST_SI174 | input | TCELL34:IMUX.IMUX.47.DELAY |
| TEST_SI175 | input | TCELL35:IMUX.IMUX.17.DELAY |
| TEST_SI176 | input | TCELL35:IMUX.IMUX.22.DELAY |
| TEST_SI177 | input | TCELL35:IMUX.IMUX.7.DELAY |
| TEST_SI178 | input | TCELL35:IMUX.IMUX.38.DELAY |
| TEST_SI179 | input | TCELL35:IMUX.IMUX.47.DELAY |
| TEST_SI18 | input | TCELL3:IMUX.IMUX.38.DELAY |
| TEST_SI180 | input | TCELL36:IMUX.IMUX.17.DELAY |
| TEST_SI181 | input | TCELL36:IMUX.IMUX.22.DELAY |
| TEST_SI182 | input | TCELL36:IMUX.IMUX.7.DELAY |
| TEST_SI183 | input | TCELL36:IMUX.IMUX.38.DELAY |
| TEST_SI184 | input | TCELL36:IMUX.IMUX.47.DELAY |
| TEST_SI185 | input | TCELL37:IMUX.IMUX.17.DELAY |
| TEST_SI186 | input | TCELL37:IMUX.IMUX.22.DELAY |
| TEST_SI187 | input | TCELL37:IMUX.IMUX.7.DELAY |
| TEST_SI188 | input | TCELL37:IMUX.IMUX.38.DELAY |
| TEST_SI189 | input | TCELL37:IMUX.IMUX.47.DELAY |
| TEST_SI19 | input | TCELL3:IMUX.IMUX.47.DELAY |
| TEST_SI190 | input | TCELL38:IMUX.IMUX.17.DELAY |
| TEST_SI191 | input | TCELL38:IMUX.IMUX.22.DELAY |
| TEST_SI192 | input | TCELL38:IMUX.IMUX.7.DELAY |
| TEST_SI193 | input | TCELL38:IMUX.IMUX.38.DELAY |
| TEST_SI194 | input | TCELL38:IMUX.IMUX.47.DELAY |
| TEST_SI195 | input | TCELL39:IMUX.IMUX.17.DELAY |
| TEST_SI196 | input | TCELL39:IMUX.IMUX.22.DELAY |
| TEST_SI197 | input | TCELL39:IMUX.IMUX.7.DELAY |
| TEST_SI198 | input | TCELL39:IMUX.IMUX.38.DELAY |
| TEST_SI199 | input | TCELL39:IMUX.IMUX.47.DELAY |
| TEST_SI2 | input | TCELL0:IMUX.IMUX.7.DELAY |
| TEST_SI20 | input | TCELL4:IMUX.IMUX.17.DELAY |
| TEST_SI200 | input | TCELL40:IMUX.IMUX.17.DELAY |
| TEST_SI201 | input | TCELL40:IMUX.IMUX.22.DELAY |
| TEST_SI202 | input | TCELL40:IMUX.IMUX.7.DELAY |
| TEST_SI203 | input | TCELL40:IMUX.IMUX.38.DELAY |
| TEST_SI204 | input | TCELL40:IMUX.IMUX.47.DELAY |
| TEST_SI205 | input | TCELL41:IMUX.IMUX.17.DELAY |
| TEST_SI206 | input | TCELL41:IMUX.IMUX.22.DELAY |
| TEST_SI207 | input | TCELL41:IMUX.IMUX.7.DELAY |
| TEST_SI208 | input | TCELL41:IMUX.IMUX.38.DELAY |
| TEST_SI209 | input | TCELL41:IMUX.IMUX.47.DELAY |
| TEST_SI21 | input | TCELL4:IMUX.IMUX.22.DELAY |
| TEST_SI210 | input | TCELL42:IMUX.IMUX.17.DELAY |
| TEST_SI211 | input | TCELL42:IMUX.IMUX.22.DELAY |
| TEST_SI212 | input | TCELL42:IMUX.IMUX.7.DELAY |
| TEST_SI213 | input | TCELL42:IMUX.IMUX.38.DELAY |
| TEST_SI214 | input | TCELL42:IMUX.IMUX.47.DELAY |
| TEST_SI215 | input | TCELL43:IMUX.IMUX.17.DELAY |
| TEST_SI216 | input | TCELL43:IMUX.IMUX.22.DELAY |
| TEST_SI217 | input | TCELL43:IMUX.IMUX.7.DELAY |
| TEST_SI218 | input | TCELL43:IMUX.IMUX.38.DELAY |
| TEST_SI219 | input | TCELL43:IMUX.IMUX.47.DELAY |
| TEST_SI22 | input | TCELL4:IMUX.IMUX.7.DELAY |
| TEST_SI220 | input | TCELL44:IMUX.IMUX.17.DELAY |
| TEST_SI221 | input | TCELL44:IMUX.IMUX.22.DELAY |
| TEST_SI222 | input | TCELL44:IMUX.IMUX.7.DELAY |
| TEST_SI223 | input | TCELL44:IMUX.IMUX.38.DELAY |
| TEST_SI224 | input | TCELL44:IMUX.IMUX.47.DELAY |
| TEST_SI225 | input | TCELL45:IMUX.IMUX.17.DELAY |
| TEST_SI226 | input | TCELL45:IMUX.IMUX.22.DELAY |
| TEST_SI227 | input | TCELL45:IMUX.IMUX.7.DELAY |
| TEST_SI228 | input | TCELL45:IMUX.IMUX.38.DELAY |
| TEST_SI229 | input | TCELL45:IMUX.IMUX.47.DELAY |
| TEST_SI23 | input | TCELL4:IMUX.IMUX.38.DELAY |
| TEST_SI230 | input | TCELL46:IMUX.IMUX.17.DELAY |
| TEST_SI231 | input | TCELL46:IMUX.IMUX.22.DELAY |
| TEST_SI232 | input | TCELL46:IMUX.IMUX.7.DELAY |
| TEST_SI233 | input | TCELL46:IMUX.IMUX.38.DELAY |
| TEST_SI234 | input | TCELL46:IMUX.IMUX.47.DELAY |
| TEST_SI235 | input | TCELL47:IMUX.IMUX.17.DELAY |
| TEST_SI236 | input | TCELL47:IMUX.IMUX.22.DELAY |
| TEST_SI237 | input | TCELL47:IMUX.IMUX.7.DELAY |
| TEST_SI238 | input | TCELL47:IMUX.IMUX.38.DELAY |
| TEST_SI239 | input | TCELL47:IMUX.IMUX.47.DELAY |
| TEST_SI24 | input | TCELL4:IMUX.IMUX.47.DELAY |
| TEST_SI240 | input | TCELL48:IMUX.IMUX.17.DELAY |
| TEST_SI241 | input | TCELL48:IMUX.IMUX.22.DELAY |
| TEST_SI242 | input | TCELL48:IMUX.IMUX.7.DELAY |
| TEST_SI243 | input | TCELL48:IMUX.IMUX.38.DELAY |
| TEST_SI244 | input | TCELL48:IMUX.IMUX.47.DELAY |
| TEST_SI245 | input | TCELL49:IMUX.IMUX.17.DELAY |
| TEST_SI246 | input | TCELL49:IMUX.IMUX.22.DELAY |
| TEST_SI247 | input | TCELL49:IMUX.IMUX.7.DELAY |
| TEST_SI248 | input | TCELL49:IMUX.IMUX.38.DELAY |
| TEST_SI249 | input | TCELL49:IMUX.IMUX.47.DELAY |
| TEST_SI25 | input | TCELL5:IMUX.IMUX.17.DELAY |
| TEST_SI250 | input | TCELL50:IMUX.IMUX.17.DELAY |
| TEST_SI251 | input | TCELL50:IMUX.IMUX.22.DELAY |
| TEST_SI252 | input | TCELL50:IMUX.IMUX.7.DELAY |
| TEST_SI253 | input | TCELL50:IMUX.IMUX.38.DELAY |
| TEST_SI254 | input | TCELL50:IMUX.IMUX.47.DELAY |
| TEST_SI255 | input | TCELL51:IMUX.IMUX.17.DELAY |
| TEST_SI256 | input | TCELL51:IMUX.IMUX.22.DELAY |
| TEST_SI257 | input | TCELL51:IMUX.IMUX.7.DELAY |
| TEST_SI258 | input | TCELL51:IMUX.IMUX.38.DELAY |
| TEST_SI259 | input | TCELL51:IMUX.IMUX.47.DELAY |
| TEST_SI26 | input | TCELL5:IMUX.IMUX.22.DELAY |
| TEST_SI260 | input | TCELL52:IMUX.IMUX.17.DELAY |
| TEST_SI261 | input | TCELL52:IMUX.IMUX.22.DELAY |
| TEST_SI262 | input | TCELL52:IMUX.IMUX.7.DELAY |
| TEST_SI263 | input | TCELL52:IMUX.IMUX.38.DELAY |
| TEST_SI264 | input | TCELL52:IMUX.IMUX.47.DELAY |
| TEST_SI265 | input | TCELL53:IMUX.IMUX.17.DELAY |
| TEST_SI266 | input | TCELL53:IMUX.IMUX.22.DELAY |
| TEST_SI267 | input | TCELL53:IMUX.IMUX.7.DELAY |
| TEST_SI268 | input | TCELL53:IMUX.IMUX.38.DELAY |
| TEST_SI269 | input | TCELL53:IMUX.IMUX.47.DELAY |
| TEST_SI27 | input | TCELL5:IMUX.IMUX.7.DELAY |
| TEST_SI270 | input | TCELL54:IMUX.IMUX.17.DELAY |
| TEST_SI271 | input | TCELL54:IMUX.IMUX.22.DELAY |
| TEST_SI272 | input | TCELL54:IMUX.IMUX.7.DELAY |
| TEST_SI273 | input | TCELL54:IMUX.IMUX.38.DELAY |
| TEST_SI274 | input | TCELL54:IMUX.IMUX.47.DELAY |
| TEST_SI275 | input | TCELL55:IMUX.IMUX.17.DELAY |
| TEST_SI276 | input | TCELL55:IMUX.IMUX.22.DELAY |
| TEST_SI277 | input | TCELL55:IMUX.IMUX.7.DELAY |
| TEST_SI278 | input | TCELL55:IMUX.IMUX.38.DELAY |
| TEST_SI279 | input | TCELL55:IMUX.IMUX.47.DELAY |
| TEST_SI28 | input | TCELL5:IMUX.IMUX.38.DELAY |
| TEST_SI280 | input | TCELL56:IMUX.IMUX.17.DELAY |
| TEST_SI281 | input | TCELL56:IMUX.IMUX.22.DELAY |
| TEST_SI282 | input | TCELL56:IMUX.IMUX.7.DELAY |
| TEST_SI283 | input | TCELL56:IMUX.IMUX.38.DELAY |
| TEST_SI284 | input | TCELL56:IMUX.IMUX.47.DELAY |
| TEST_SI285 | input | TCELL57:IMUX.IMUX.17.DELAY |
| TEST_SI286 | input | TCELL57:IMUX.IMUX.22.DELAY |
| TEST_SI287 | input | TCELL57:IMUX.IMUX.7.DELAY |
| TEST_SI288 | input | TCELL57:IMUX.IMUX.38.DELAY |
| TEST_SI289 | input | TCELL57:IMUX.IMUX.47.DELAY |
| TEST_SI29 | input | TCELL5:IMUX.IMUX.47.DELAY |
| TEST_SI290 | input | TCELL58:IMUX.IMUX.17.DELAY |
| TEST_SI291 | input | TCELL58:IMUX.IMUX.22.DELAY |
| TEST_SI292 | input | TCELL58:IMUX.IMUX.7.DELAY |
| TEST_SI293 | input | TCELL58:IMUX.IMUX.38.DELAY |
| TEST_SI294 | input | TCELL58:IMUX.IMUX.47.DELAY |
| TEST_SI295 | input | TCELL59:IMUX.IMUX.17.DELAY |
| TEST_SI296 | input | TCELL59:IMUX.IMUX.22.DELAY |
| TEST_SI297 | input | TCELL59:IMUX.IMUX.7.DELAY |
| TEST_SI298 | input | TCELL59:IMUX.IMUX.38.DELAY |
| TEST_SI299 | input | TCELL59:IMUX.IMUX.47.DELAY |
| TEST_SI3 | input | TCELL0:IMUX.IMUX.38.DELAY |
| TEST_SI30 | input | TCELL6:IMUX.IMUX.17.DELAY |
| TEST_SI31 | input | TCELL6:IMUX.IMUX.22.DELAY |
| TEST_SI32 | input | TCELL6:IMUX.IMUX.7.DELAY |
| TEST_SI33 | input | TCELL6:IMUX.IMUX.38.DELAY |
| TEST_SI34 | input | TCELL6:IMUX.IMUX.47.DELAY |
| TEST_SI35 | input | TCELL7:IMUX.IMUX.17.DELAY |
| TEST_SI36 | input | TCELL7:IMUX.IMUX.22.DELAY |
| TEST_SI37 | input | TCELL7:IMUX.IMUX.7.DELAY |
| TEST_SI38 | input | TCELL7:IMUX.IMUX.38.DELAY |
| TEST_SI39 | input | TCELL7:IMUX.IMUX.47.DELAY |
| TEST_SI4 | input | TCELL0:IMUX.IMUX.47.DELAY |
| TEST_SI40 | input | TCELL8:IMUX.IMUX.17.DELAY |
| TEST_SI41 | input | TCELL8:IMUX.IMUX.22.DELAY |
| TEST_SI42 | input | TCELL8:IMUX.IMUX.7.DELAY |
| TEST_SI43 | input | TCELL8:IMUX.IMUX.38.DELAY |
| TEST_SI44 | input | TCELL8:IMUX.IMUX.47.DELAY |
| TEST_SI45 | input | TCELL9:IMUX.IMUX.17.DELAY |
| TEST_SI46 | input | TCELL9:IMUX.IMUX.22.DELAY |
| TEST_SI47 | input | TCELL9:IMUX.IMUX.7.DELAY |
| TEST_SI48 | input | TCELL9:IMUX.IMUX.38.DELAY |
| TEST_SI49 | input | TCELL9:IMUX.IMUX.47.DELAY |
| TEST_SI5 | input | TCELL1:IMUX.IMUX.17.DELAY |
| TEST_SI50 | input | TCELL10:IMUX.IMUX.17.DELAY |
| TEST_SI51 | input | TCELL10:IMUX.IMUX.22.DELAY |
| TEST_SI52 | input | TCELL10:IMUX.IMUX.7.DELAY |
| TEST_SI53 | input | TCELL10:IMUX.IMUX.38.DELAY |
| TEST_SI54 | input | TCELL10:IMUX.IMUX.47.DELAY |
| TEST_SI55 | input | TCELL11:IMUX.IMUX.17.DELAY |
| TEST_SI56 | input | TCELL11:IMUX.IMUX.22.DELAY |
| TEST_SI57 | input | TCELL11:IMUX.IMUX.7.DELAY |
| TEST_SI58 | input | TCELL11:IMUX.IMUX.38.DELAY |
| TEST_SI59 | input | TCELL11:IMUX.IMUX.47.DELAY |
| TEST_SI6 | input | TCELL1:IMUX.IMUX.22.DELAY |
| TEST_SI60 | input | TCELL12:IMUX.IMUX.17.DELAY |
| TEST_SI61 | input | TCELL12:IMUX.IMUX.22.DELAY |
| TEST_SI62 | input | TCELL12:IMUX.IMUX.7.DELAY |
| TEST_SI63 | input | TCELL12:IMUX.IMUX.38.DELAY |
| TEST_SI64 | input | TCELL12:IMUX.IMUX.47.DELAY |
| TEST_SI65 | input | TCELL13:IMUX.IMUX.17.DELAY |
| TEST_SI66 | input | TCELL13:IMUX.IMUX.22.DELAY |
| TEST_SI67 | input | TCELL13:IMUX.IMUX.7.DELAY |
| TEST_SI68 | input | TCELL13:IMUX.IMUX.38.DELAY |
| TEST_SI69 | input | TCELL13:IMUX.IMUX.47.DELAY |
| TEST_SI7 | input | TCELL1:IMUX.IMUX.7.DELAY |
| TEST_SI70 | input | TCELL14:IMUX.IMUX.17.DELAY |
| TEST_SI71 | input | TCELL14:IMUX.IMUX.22.DELAY |
| TEST_SI72 | input | TCELL14:IMUX.IMUX.7.DELAY |
| TEST_SI73 | input | TCELL14:IMUX.IMUX.38.DELAY |
| TEST_SI74 | input | TCELL14:IMUX.IMUX.47.DELAY |
| TEST_SI75 | input | TCELL15:IMUX.IMUX.17.DELAY |
| TEST_SI76 | input | TCELL15:IMUX.IMUX.22.DELAY |
| TEST_SI77 | input | TCELL15:IMUX.IMUX.7.DELAY |
| TEST_SI78 | input | TCELL15:IMUX.IMUX.38.DELAY |
| TEST_SI79 | input | TCELL15:IMUX.IMUX.47.DELAY |
| TEST_SI8 | input | TCELL1:IMUX.IMUX.38.DELAY |
| TEST_SI80 | input | TCELL16:IMUX.IMUX.17.DELAY |
| TEST_SI81 | input | TCELL16:IMUX.IMUX.22.DELAY |
| TEST_SI82 | input | TCELL16:IMUX.IMUX.7.DELAY |
| TEST_SI83 | input | TCELL16:IMUX.IMUX.38.DELAY |
| TEST_SI84 | input | TCELL16:IMUX.IMUX.47.DELAY |
| TEST_SI85 | input | TCELL17:IMUX.IMUX.17.DELAY |
| TEST_SI86 | input | TCELL17:IMUX.IMUX.22.DELAY |
| TEST_SI87 | input | TCELL17:IMUX.IMUX.7.DELAY |
| TEST_SI88 | input | TCELL17:IMUX.IMUX.38.DELAY |
| TEST_SI89 | input | TCELL17:IMUX.IMUX.47.DELAY |
| TEST_SI9 | input | TCELL1:IMUX.IMUX.47.DELAY |
| TEST_SI90 | input | TCELL18:IMUX.IMUX.17.DELAY |
| TEST_SI91 | input | TCELL18:IMUX.IMUX.22.DELAY |
| TEST_SI92 | input | TCELL18:IMUX.IMUX.7.DELAY |
| TEST_SI93 | input | TCELL18:IMUX.IMUX.38.DELAY |
| TEST_SI94 | input | TCELL18:IMUX.IMUX.47.DELAY |
| TEST_SI95 | input | TCELL19:IMUX.IMUX.17.DELAY |
| TEST_SI96 | input | TCELL19:IMUX.IMUX.22.DELAY |
| TEST_SI97 | input | TCELL19:IMUX.IMUX.7.DELAY |
| TEST_SI98 | input | TCELL19:IMUX.IMUX.38.DELAY |
| TEST_SI99 | input | TCELL19:IMUX.IMUX.47.DELAY |
| TEST_SO0 | output | TCELL0:OUT.3.TMIN |
| TEST_SO1 | output | TCELL0:OUT.11.TMIN |
| TEST_SO10 | output | TCELL2:OUT.3.TMIN |
| TEST_SO100 | output | TCELL20:OUT.3.TMIN |
| TEST_SO101 | output | TCELL20:OUT.11.TMIN |
| TEST_SO102 | output | TCELL20:OUT.21.TMIN |
| TEST_SO103 | output | TCELL20:OUT.27.TMIN |
| TEST_SO104 | output | TCELL20:OUT.31.TMIN |
| TEST_SO105 | output | TCELL21:OUT.3.TMIN |
| TEST_SO106 | output | TCELL21:OUT.11.TMIN |
| TEST_SO107 | output | TCELL21:OUT.21.TMIN |
| TEST_SO108 | output | TCELL21:OUT.27.TMIN |
| TEST_SO109 | output | TCELL21:OUT.31.TMIN |
| TEST_SO11 | output | TCELL2:OUT.11.TMIN |
| TEST_SO110 | output | TCELL22:OUT.3.TMIN |
| TEST_SO111 | output | TCELL22:OUT.11.TMIN |
| TEST_SO112 | output | TCELL22:OUT.21.TMIN |
| TEST_SO113 | output | TCELL22:OUT.27.TMIN |
| TEST_SO114 | output | TCELL22:OUT.31.TMIN |
| TEST_SO115 | output | TCELL23:OUT.3.TMIN |
| TEST_SO116 | output | TCELL23:OUT.11.TMIN |
| TEST_SO117 | output | TCELL23:OUT.21.TMIN |
| TEST_SO118 | output | TCELL23:OUT.27.TMIN |
| TEST_SO119 | output | TCELL23:OUT.31.TMIN |
| TEST_SO12 | output | TCELL2:OUT.21.TMIN |
| TEST_SO120 | output | TCELL24:OUT.3.TMIN |
| TEST_SO121 | output | TCELL24:OUT.11.TMIN |
| TEST_SO122 | output | TCELL24:OUT.21.TMIN |
| TEST_SO123 | output | TCELL24:OUT.27.TMIN |
| TEST_SO124 | output | TCELL24:OUT.31.TMIN |
| TEST_SO125 | output | TCELL25:OUT.3.TMIN |
| TEST_SO126 | output | TCELL25:OUT.11.TMIN |
| TEST_SO127 | output | TCELL25:OUT.21.TMIN |
| TEST_SO128 | output | TCELL25:OUT.27.TMIN |
| TEST_SO129 | output | TCELL25:OUT.31.TMIN |
| TEST_SO13 | output | TCELL2:OUT.27.TMIN |
| TEST_SO130 | output | TCELL26:OUT.3.TMIN |
| TEST_SO131 | output | TCELL26:OUT.11.TMIN |
| TEST_SO132 | output | TCELL26:OUT.21.TMIN |
| TEST_SO133 | output | TCELL26:OUT.27.TMIN |
| TEST_SO134 | output | TCELL26:OUT.31.TMIN |
| TEST_SO135 | output | TCELL27:OUT.3.TMIN |
| TEST_SO136 | output | TCELL27:OUT.5.TMIN |
| TEST_SO137 | output | TCELL27:OUT.11.TMIN |
| TEST_SO138 | output | TCELL27:OUT.15.TMIN |
| TEST_SO139 | output | TCELL27:OUT.21.TMIN |
| TEST_SO14 | output | TCELL2:OUT.31.TMIN |
| TEST_SO140 | output | TCELL27:OUT.27.TMIN |
| TEST_SO141 | output | TCELL27:OUT.29.TMIN |
| TEST_SO142 | output | TCELL27:OUT.31.TMIN |
| TEST_SO143 | output | TCELL28:OUT.3.TMIN |
| TEST_SO144 | output | TCELL28:OUT.11.TMIN |
| TEST_SO145 | output | TCELL28:OUT.19.TMIN |
| TEST_SO146 | output | TCELL28:OUT.21.TMIN |
| TEST_SO147 | output | TCELL28:OUT.27.TMIN |
| TEST_SO148 | output | TCELL28:OUT.29.TMIN |
| TEST_SO149 | output | TCELL28:OUT.31.TMIN |
| TEST_SO15 | output | TCELL3:OUT.3.TMIN |
| TEST_SO150 | output | TCELL31:OUT.3.TMIN |
| TEST_SO151 | output | TCELL31:OUT.11.TMIN |
| TEST_SO152 | output | TCELL31:OUT.19.TMIN |
| TEST_SO153 | output | TCELL31:OUT.21.TMIN |
| TEST_SO154 | output | TCELL31:OUT.27.TMIN |
| TEST_SO155 | output | TCELL31:OUT.29.TMIN |
| TEST_SO156 | output | TCELL31:OUT.31.TMIN |
| TEST_SO157 | output | TCELL32:OUT.3.TMIN |
| TEST_SO158 | output | TCELL32:OUT.11.TMIN |
| TEST_SO159 | output | TCELL32:OUT.14.TMIN |
| TEST_SO16 | output | TCELL3:OUT.11.TMIN |
| TEST_SO160 | output | TCELL32:OUT.21.TMIN |
| TEST_SO161 | output | TCELL32:OUT.27.TMIN |
| TEST_SO162 | output | TCELL32:OUT.31.TMIN |
| TEST_SO163 | output | TCELL33:OUT.3.TMIN |
| TEST_SO164 | output | TCELL33:OUT.11.TMIN |
| TEST_SO165 | output | TCELL33:OUT.16.TMIN |
| TEST_SO166 | output | TCELL33:OUT.21.TMIN |
| TEST_SO167 | output | TCELL33:OUT.27.TMIN |
| TEST_SO168 | output | TCELL33:OUT.31.TMIN |
| TEST_SO169 | output | TCELL34:OUT.3.TMIN |
| TEST_SO17 | output | TCELL3:OUT.21.TMIN |
| TEST_SO170 | output | TCELL34:OUT.11.TMIN |
| TEST_SO171 | output | TCELL34:OUT.21.TMIN |
| TEST_SO172 | output | TCELL34:OUT.27.TMIN |
| TEST_SO173 | output | TCELL34:OUT.31.TMIN |
| TEST_SO174 | output | TCELL35:OUT.3.TMIN |
| TEST_SO175 | output | TCELL35:OUT.11.TMIN |
| TEST_SO176 | output | TCELL35:OUT.16.TMIN |
| TEST_SO177 | output | TCELL35:OUT.21.TMIN |
| TEST_SO178 | output | TCELL35:OUT.27.TMIN |
| TEST_SO179 | output | TCELL35:OUT.31.TMIN |
| TEST_SO18 | output | TCELL3:OUT.27.TMIN |
| TEST_SO180 | output | TCELL36:OUT.3.TMIN |
| TEST_SO181 | output | TCELL36:OUT.11.TMIN |
| TEST_SO182 | output | TCELL36:OUT.21.TMIN |
| TEST_SO183 | output | TCELL36:OUT.27.TMIN |
| TEST_SO184 | output | TCELL36:OUT.31.TMIN |
| TEST_SO185 | output | TCELL37:OUT.3.TMIN |
| TEST_SO186 | output | TCELL37:OUT.11.TMIN |
| TEST_SO187 | output | TCELL37:OUT.21.TMIN |
| TEST_SO188 | output | TCELL37:OUT.27.TMIN |
| TEST_SO189 | output | TCELL37:OUT.31.TMIN |
| TEST_SO19 | output | TCELL3:OUT.31.TMIN |
| TEST_SO190 | output | TCELL38:OUT.3.TMIN |
| TEST_SO191 | output | TCELL38:OUT.11.TMIN |
| TEST_SO192 | output | TCELL38:OUT.21.TMIN |
| TEST_SO193 | output | TCELL38:OUT.27.TMIN |
| TEST_SO194 | output | TCELL38:OUT.31.TMIN |
| TEST_SO195 | output | TCELL39:OUT.3.TMIN |
| TEST_SO196 | output | TCELL39:OUT.11.TMIN |
| TEST_SO197 | output | TCELL39:OUT.21.TMIN |
| TEST_SO198 | output | TCELL39:OUT.27.TMIN |
| TEST_SO199 | output | TCELL39:OUT.31.TMIN |
| TEST_SO2 | output | TCELL0:OUT.21.TMIN |
| TEST_SO20 | output | TCELL4:OUT.3.TMIN |
| TEST_SO200 | output | TCELL40:OUT.3.TMIN |
| TEST_SO201 | output | TCELL40:OUT.11.TMIN |
| TEST_SO202 | output | TCELL40:OUT.21.TMIN |
| TEST_SO203 | output | TCELL40:OUT.27.TMIN |
| TEST_SO204 | output | TCELL40:OUT.31.TMIN |
| TEST_SO205 | output | TCELL41:OUT.3.TMIN |
| TEST_SO206 | output | TCELL41:OUT.11.TMIN |
| TEST_SO207 | output | TCELL41:OUT.21.TMIN |
| TEST_SO208 | output | TCELL41:OUT.27.TMIN |
| TEST_SO209 | output | TCELL41:OUT.31.TMIN |
| TEST_SO21 | output | TCELL4:OUT.11.TMIN |
| TEST_SO210 | output | TCELL42:OUT.3.TMIN |
| TEST_SO211 | output | TCELL42:OUT.11.TMIN |
| TEST_SO212 | output | TCELL42:OUT.21.TMIN |
| TEST_SO213 | output | TCELL42:OUT.27.TMIN |
| TEST_SO214 | output | TCELL42:OUT.31.TMIN |
| TEST_SO215 | output | TCELL43:OUT.3.TMIN |
| TEST_SO216 | output | TCELL43:OUT.11.TMIN |
| TEST_SO217 | output | TCELL43:OUT.21.TMIN |
| TEST_SO218 | output | TCELL43:OUT.27.TMIN |
| TEST_SO219 | output | TCELL43:OUT.31.TMIN |
| TEST_SO22 | output | TCELL4:OUT.21.TMIN |
| TEST_SO220 | output | TCELL44:OUT.3.TMIN |
| TEST_SO221 | output | TCELL44:OUT.11.TMIN |
| TEST_SO222 | output | TCELL44:OUT.21.TMIN |
| TEST_SO223 | output | TCELL44:OUT.27.TMIN |
| TEST_SO224 | output | TCELL44:OUT.31.TMIN |
| TEST_SO225 | output | TCELL45:OUT.3.TMIN |
| TEST_SO226 | output | TCELL45:OUT.11.TMIN |
| TEST_SO227 | output | TCELL45:OUT.21.TMIN |
| TEST_SO228 | output | TCELL45:OUT.27.TMIN |
| TEST_SO229 | output | TCELL45:OUT.31.TMIN |
| TEST_SO23 | output | TCELL4:OUT.27.TMIN |
| TEST_SO230 | output | TCELL46:OUT.3.TMIN |
| TEST_SO231 | output | TCELL46:OUT.11.TMIN |
| TEST_SO232 | output | TCELL46:OUT.21.TMIN |
| TEST_SO233 | output | TCELL46:OUT.27.TMIN |
| TEST_SO234 | output | TCELL46:OUT.31.TMIN |
| TEST_SO235 | output | TCELL47:OUT.3.TMIN |
| TEST_SO236 | output | TCELL47:OUT.11.TMIN |
| TEST_SO237 | output | TCELL47:OUT.21.TMIN |
| TEST_SO238 | output | TCELL47:OUT.27.TMIN |
| TEST_SO239 | output | TCELL47:OUT.31.TMIN |
| TEST_SO24 | output | TCELL4:OUT.31.TMIN |
| TEST_SO240 | output | TCELL48:OUT.3.TMIN |
| TEST_SO241 | output | TCELL48:OUT.11.TMIN |
| TEST_SO242 | output | TCELL48:OUT.21.TMIN |
| TEST_SO243 | output | TCELL48:OUT.27.TMIN |
| TEST_SO244 | output | TCELL48:OUT.31.TMIN |
| TEST_SO245 | output | TCELL49:OUT.3.TMIN |
| TEST_SO246 | output | TCELL49:OUT.11.TMIN |
| TEST_SO247 | output | TCELL49:OUT.21.TMIN |
| TEST_SO248 | output | TCELL49:OUT.27.TMIN |
| TEST_SO249 | output | TCELL49:OUT.31.TMIN |
| TEST_SO25 | output | TCELL5:OUT.3.TMIN |
| TEST_SO250 | output | TCELL50:OUT.3.TMIN |
| TEST_SO251 | output | TCELL50:OUT.11.TMIN |
| TEST_SO252 | output | TCELL50:OUT.21.TMIN |
| TEST_SO253 | output | TCELL50:OUT.27.TMIN |
| TEST_SO254 | output | TCELL50:OUT.31.TMIN |
| TEST_SO255 | output | TCELL51:OUT.3.TMIN |
| TEST_SO256 | output | TCELL51:OUT.11.TMIN |
| TEST_SO257 | output | TCELL51:OUT.21.TMIN |
| TEST_SO258 | output | TCELL51:OUT.27.TMIN |
| TEST_SO259 | output | TCELL51:OUT.31.TMIN |
| TEST_SO26 | output | TCELL5:OUT.11.TMIN |
| TEST_SO260 | output | TCELL52:OUT.3.TMIN |
| TEST_SO261 | output | TCELL52:OUT.11.TMIN |
| TEST_SO262 | output | TCELL52:OUT.21.TMIN |
| TEST_SO263 | output | TCELL52:OUT.27.TMIN |
| TEST_SO264 | output | TCELL52:OUT.31.TMIN |
| TEST_SO265 | output | TCELL53:OUT.3.TMIN |
| TEST_SO266 | output | TCELL53:OUT.11.TMIN |
| TEST_SO267 | output | TCELL53:OUT.21.TMIN |
| TEST_SO268 | output | TCELL53:OUT.27.TMIN |
| TEST_SO269 | output | TCELL53:OUT.31.TMIN |
| TEST_SO27 | output | TCELL5:OUT.21.TMIN |
| TEST_SO270 | output | TCELL54:OUT.3.TMIN |
| TEST_SO271 | output | TCELL54:OUT.11.TMIN |
| TEST_SO272 | output | TCELL54:OUT.21.TMIN |
| TEST_SO273 | output | TCELL54:OUT.27.TMIN |
| TEST_SO274 | output | TCELL54:OUT.31.TMIN |
| TEST_SO275 | output | TCELL55:OUT.3.TMIN |
| TEST_SO276 | output | TCELL55:OUT.11.TMIN |
| TEST_SO277 | output | TCELL55:OUT.21.TMIN |
| TEST_SO278 | output | TCELL55:OUT.27.TMIN |
| TEST_SO279 | output | TCELL55:OUT.31.TMIN |
| TEST_SO28 | output | TCELL5:OUT.27.TMIN |
| TEST_SO280 | output | TCELL56:OUT.3.TMIN |
| TEST_SO281 | output | TCELL56:OUT.11.TMIN |
| TEST_SO282 | output | TCELL56:OUT.21.TMIN |
| TEST_SO283 | output | TCELL56:OUT.27.TMIN |
| TEST_SO284 | output | TCELL56:OUT.31.TMIN |
| TEST_SO285 | output | TCELL57:OUT.3.TMIN |
| TEST_SO286 | output | TCELL57:OUT.11.TMIN |
| TEST_SO287 | output | TCELL57:OUT.21.TMIN |
| TEST_SO288 | output | TCELL57:OUT.27.TMIN |
| TEST_SO289 | output | TCELL57:OUT.31.TMIN |
| TEST_SO29 | output | TCELL5:OUT.31.TMIN |
| TEST_SO290 | output | TCELL58:OUT.3.TMIN |
| TEST_SO291 | output | TCELL58:OUT.11.TMIN |
| TEST_SO292 | output | TCELL58:OUT.21.TMIN |
| TEST_SO293 | output | TCELL58:OUT.27.TMIN |
| TEST_SO294 | output | TCELL58:OUT.31.TMIN |
| TEST_SO295 | output | TCELL59:OUT.3.TMIN |
| TEST_SO296 | output | TCELL59:OUT.11.TMIN |
| TEST_SO297 | output | TCELL59:OUT.21.TMIN |
| TEST_SO298 | output | TCELL59:OUT.27.TMIN |
| TEST_SO299 | output | TCELL59:OUT.31.TMIN |
| TEST_SO3 | output | TCELL0:OUT.27.TMIN |
| TEST_SO30 | output | TCELL6:OUT.3.TMIN |
| TEST_SO31 | output | TCELL6:OUT.11.TMIN |
| TEST_SO32 | output | TCELL6:OUT.21.TMIN |
| TEST_SO33 | output | TCELL6:OUT.27.TMIN |
| TEST_SO34 | output | TCELL6:OUT.31.TMIN |
| TEST_SO35 | output | TCELL7:OUT.3.TMIN |
| TEST_SO36 | output | TCELL7:OUT.11.TMIN |
| TEST_SO37 | output | TCELL7:OUT.21.TMIN |
| TEST_SO38 | output | TCELL7:OUT.27.TMIN |
| TEST_SO39 | output | TCELL7:OUT.31.TMIN |
| TEST_SO4 | output | TCELL0:OUT.31.TMIN |
| TEST_SO40 | output | TCELL8:OUT.3.TMIN |
| TEST_SO41 | output | TCELL8:OUT.11.TMIN |
| TEST_SO42 | output | TCELL8:OUT.21.TMIN |
| TEST_SO43 | output | TCELL8:OUT.27.TMIN |
| TEST_SO44 | output | TCELL8:OUT.31.TMIN |
| TEST_SO45 | output | TCELL9:OUT.3.TMIN |
| TEST_SO46 | output | TCELL9:OUT.11.TMIN |
| TEST_SO47 | output | TCELL9:OUT.21.TMIN |
| TEST_SO48 | output | TCELL9:OUT.27.TMIN |
| TEST_SO49 | output | TCELL9:OUT.31.TMIN |
| TEST_SO5 | output | TCELL1:OUT.3.TMIN |
| TEST_SO50 | output | TCELL10:OUT.3.TMIN |
| TEST_SO51 | output | TCELL10:OUT.11.TMIN |
| TEST_SO52 | output | TCELL10:OUT.21.TMIN |
| TEST_SO53 | output | TCELL10:OUT.27.TMIN |
| TEST_SO54 | output | TCELL10:OUT.31.TMIN |
| TEST_SO55 | output | TCELL11:OUT.3.TMIN |
| TEST_SO56 | output | TCELL11:OUT.11.TMIN |
| TEST_SO57 | output | TCELL11:OUT.21.TMIN |
| TEST_SO58 | output | TCELL11:OUT.27.TMIN |
| TEST_SO59 | output | TCELL11:OUT.31.TMIN |
| TEST_SO6 | output | TCELL1:OUT.11.TMIN |
| TEST_SO60 | output | TCELL12:OUT.3.TMIN |
| TEST_SO61 | output | TCELL12:OUT.11.TMIN |
| TEST_SO62 | output | TCELL12:OUT.21.TMIN |
| TEST_SO63 | output | TCELL12:OUT.27.TMIN |
| TEST_SO64 | output | TCELL12:OUT.31.TMIN |
| TEST_SO65 | output | TCELL13:OUT.3.TMIN |
| TEST_SO66 | output | TCELL13:OUT.11.TMIN |
| TEST_SO67 | output | TCELL13:OUT.21.TMIN |
| TEST_SO68 | output | TCELL13:OUT.27.TMIN |
| TEST_SO69 | output | TCELL13:OUT.31.TMIN |
| TEST_SO7 | output | TCELL1:OUT.21.TMIN |
| TEST_SO70 | output | TCELL14:OUT.3.TMIN |
| TEST_SO71 | output | TCELL14:OUT.11.TMIN |
| TEST_SO72 | output | TCELL14:OUT.21.TMIN |
| TEST_SO73 | output | TCELL14:OUT.27.TMIN |
| TEST_SO74 | output | TCELL14:OUT.31.TMIN |
| TEST_SO75 | output | TCELL15:OUT.3.TMIN |
| TEST_SO76 | output | TCELL15:OUT.11.TMIN |
| TEST_SO77 | output | TCELL15:OUT.21.TMIN |
| TEST_SO78 | output | TCELL15:OUT.27.TMIN |
| TEST_SO79 | output | TCELL15:OUT.31.TMIN |
| TEST_SO8 | output | TCELL1:OUT.27.TMIN |
| TEST_SO80 | output | TCELL16:OUT.3.TMIN |
| TEST_SO81 | output | TCELL16:OUT.11.TMIN |
| TEST_SO82 | output | TCELL16:OUT.21.TMIN |
| TEST_SO83 | output | TCELL16:OUT.27.TMIN |
| TEST_SO84 | output | TCELL16:OUT.31.TMIN |
| TEST_SO85 | output | TCELL17:OUT.3.TMIN |
| TEST_SO86 | output | TCELL17:OUT.11.TMIN |
| TEST_SO87 | output | TCELL17:OUT.21.TMIN |
| TEST_SO88 | output | TCELL17:OUT.27.TMIN |
| TEST_SO89 | output | TCELL17:OUT.31.TMIN |
| TEST_SO9 | output | TCELL1:OUT.31.TMIN |
| TEST_SO90 | output | TCELL18:OUT.3.TMIN |
| TEST_SO91 | output | TCELL18:OUT.11.TMIN |
| TEST_SO92 | output | TCELL18:OUT.21.TMIN |
| TEST_SO93 | output | TCELL18:OUT.27.TMIN |
| TEST_SO94 | output | TCELL18:OUT.31.TMIN |
| TEST_SO95 | output | TCELL19:OUT.3.TMIN |
| TEST_SO96 | output | TCELL19:OUT.11.TMIN |
| TEST_SO97 | output | TCELL19:OUT.21.TMIN |
| TEST_SO98 | output | TCELL19:OUT.27.TMIN |
| TEST_SO99 | output | TCELL19:OUT.31.TMIN |
| TEST_STATUS0 | output | TCELL20:OUT.17.TMIN |
| TEST_STATUS1 | output | TCELL21:OUT.17.TMIN |
| TEST_STATUS10 | output | TCELL34:OUT.17.TMIN |
| TEST_STATUS11 | output | TCELL35:OUT.17.TMIN |
| TEST_STATUS12 | output | TCELL36:OUT.17.TMIN |
| TEST_STATUS13 | output | TCELL37:OUT.17.TMIN |
| TEST_STATUS14 | output | TCELL38:OUT.17.TMIN |
| TEST_STATUS15 | output | TCELL39:OUT.17.TMIN |
| TEST_STATUS2 | output | TCELL22:OUT.17.TMIN |
| TEST_STATUS3 | output | TCELL23:OUT.17.TMIN |
| TEST_STATUS4 | output | TCELL24:OUT.17.TMIN |
| TEST_STATUS5 | output | TCELL25:OUT.17.TMIN |
| TEST_STATUS6 | output | TCELL26:OUT.17.TMIN |
| TEST_STATUS7 | output | TCELL27:OUT.17.TMIN |
| TEST_STATUS8 | output | TCELL32:OUT.17.TMIN |
| TEST_STATUS9 | output | TCELL33:OUT.17.TMIN |
Bel RCLK_GT
| Pin | Direction | Wires |
|---|
Bel VCC_GT
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:OUT.2.TMIN | HSADC.DATA_ADC0_0 |
| TCELL0:OUT.3.TMIN | HSADC.TEST_SO0 |
| TCELL0:OUT.6.TMIN | HSADC.DATA_ADC0_1 |
| TCELL0:OUT.10.TMIN | HSADC.DATA_ADC0_2 |
| TCELL0:OUT.11.TMIN | HSADC.TEST_SO1 |
| TCELL0:OUT.13.TMIN | HSADC.DATA_ADC0_3 |
| TCELL0:OUT.16.TMIN | HSADC.DATA_ADC0_4 |
| TCELL0:OUT.19.TMIN | HSADC.DATA_ADC0_5 |
| TCELL0:OUT.21.TMIN | HSADC.TEST_SO2 |
| TCELL0:OUT.22.TMIN | HSADC.DATA_ADC0_6 |
| TCELL0:OUT.26.TMIN | HSADC.DATA_ADC0_7 |
| TCELL0:OUT.27.TMIN | HSADC.TEST_SO3 |
| TCELL0:OUT.30.TMIN | HSADC.DATA_ADC0_8 |
| TCELL0:OUT.31.TMIN | HSADC.TEST_SO4 |
| TCELL0:IMUX.IMUX.7.DELAY | HSADC.TEST_SI2 |
| TCELL0:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC0_1 |
| TCELL0:IMUX.IMUX.17.DELAY | HSADC.TEST_SI0 |
| TCELL0:IMUX.IMUX.22.DELAY | HSADC.TEST_SI1 |
| TCELL0:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC0_0 |
| TCELL0:IMUX.IMUX.38.DELAY | HSADC.TEST_SI3 |
| TCELL0:IMUX.IMUX.47.DELAY | HSADC.TEST_SI4 |
| TCELL1:OUT.2.TMIN | HSADC.DATA_ADC0_9 |
| TCELL1:OUT.3.TMIN | HSADC.TEST_SO5 |
| TCELL1:OUT.6.TMIN | HSADC.DATA_ADC0_10 |
| TCELL1:OUT.8.TMIN | HSADC.STATUS_ADC0_0 |
| TCELL1:OUT.10.TMIN | HSADC.DATA_ADC0_11 |
| TCELL1:OUT.11.TMIN | HSADC.TEST_SO6 |
| TCELL1:OUT.14.TMIN | HSADC.DATA_ADC0_12 |
| TCELL1:OUT.18.TMIN | HSADC.DATA_ADC0_13 |
| TCELL1:OUT.21.TMIN | HSADC.TEST_SO7 |
| TCELL1:OUT.22.TMIN | HSADC.DATA_ADC0_14 |
| TCELL1:OUT.24.TMIN | HSADC.STATUS_ADC0_1 |
| TCELL1:OUT.26.TMIN | HSADC.DATA_ADC0_15 |
| TCELL1:OUT.27.TMIN | HSADC.TEST_SO8 |
| TCELL1:OUT.30.TMIN | HSADC.DATA_ADC0_16 |
| TCELL1:OUT.31.TMIN | HSADC.TEST_SO9 |
| TCELL1:IMUX.IMUX.7.DELAY | HSADC.TEST_SI7 |
| TCELL1:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC0_2 |
| TCELL1:IMUX.IMUX.17.DELAY | HSADC.TEST_SI5 |
| TCELL1:IMUX.IMUX.22.DELAY | HSADC.TEST_SI6 |
| TCELL1:IMUX.IMUX.38.DELAY | HSADC.TEST_SI8 |
| TCELL1:IMUX.IMUX.47.DELAY | HSADC.TEST_SI9 |
| TCELL2:OUT.2.TMIN | HSADC.DATA_ADC0_17 |
| TCELL2:OUT.3.TMIN | HSADC.TEST_SO10 |
| TCELL2:OUT.4.TMIN | HSADC.STATUS_ADC0_2 |
| TCELL2:OUT.6.TMIN | HSADC.DATA_ADC0_18 |
| TCELL2:OUT.10.TMIN | HSADC.DATA_ADC0_19 |
| TCELL2:OUT.11.TMIN | HSADC.TEST_SO11 |
| TCELL2:OUT.13.TMIN | HSADC.DATA_ADC0_20 |
| TCELL2:OUT.16.TMIN | HSADC.DATA_ADC0_21 |
| TCELL2:OUT.19.TMIN | HSADC.DATA_ADC0_22 |
| TCELL2:OUT.21.TMIN | HSADC.TEST_SO12 |
| TCELL2:OUT.22.TMIN | HSADC.DATA_ADC0_23 |
| TCELL2:OUT.26.TMIN | HSADC.DATA_ADC0_24 |
| TCELL2:OUT.27.TMIN | HSADC.TEST_SO13 |
| TCELL2:OUT.28.TMIN | HSADC.STATUS_ADC0_3 |
| TCELL2:OUT.30.TMIN | HSADC.DATA_ADC0_25 |
| TCELL2:OUT.31.TMIN | HSADC.TEST_SO14 |
| TCELL2:IMUX.IMUX.7.DELAY | HSADC.TEST_SI12 |
| TCELL2:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC0_4 |
| TCELL2:IMUX.IMUX.17.DELAY | HSADC.TEST_SI10 |
| TCELL2:IMUX.IMUX.22.DELAY | HSADC.TEST_SI11 |
| TCELL2:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC0_3 |
| TCELL2:IMUX.IMUX.38.DELAY | HSADC.TEST_SI13 |
| TCELL2:IMUX.IMUX.47.DELAY | HSADC.TEST_SI14 |
| TCELL3:OUT.2.TMIN | HSADC.DATA_ADC0_26 |
| TCELL3:OUT.3.TMIN | HSADC.TEST_SO15 |
| TCELL3:OUT.6.TMIN | HSADC.DATA_ADC0_27 |
| TCELL3:OUT.8.TMIN | HSADC.STATUS_ADC0_4 |
| TCELL3:OUT.10.TMIN | HSADC.DATA_ADC0_28 |
| TCELL3:OUT.11.TMIN | HSADC.TEST_SO16 |
| TCELL3:OUT.14.TMIN | HSADC.DATA_ADC0_29 |
| TCELL3:OUT.18.TMIN | HSADC.DATA_ADC0_30 |
| TCELL3:OUT.21.TMIN | HSADC.TEST_SO17 |
| TCELL3:OUT.22.TMIN | HSADC.DATA_ADC0_31 |
| TCELL3:OUT.24.TMIN | HSADC.STATUS_ADC0_5 |
| TCELL3:OUT.26.TMIN | HSADC.DATA_ADC0_32 |
| TCELL3:OUT.27.TMIN | HSADC.TEST_SO18 |
| TCELL3:OUT.30.TMIN | HSADC.DATA_ADC0_33 |
| TCELL3:OUT.31.TMIN | HSADC.TEST_SO19 |
| TCELL3:IMUX.CTRL.5 | HSADC.TEST_SCAN_CLK0 |
| TCELL3:IMUX.IMUX.7.DELAY | HSADC.TEST_SI17 |
| TCELL3:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC0_5 |
| TCELL3:IMUX.IMUX.17.DELAY | HSADC.TEST_SI15 |
| TCELL3:IMUX.IMUX.22.DELAY | HSADC.TEST_SI16 |
| TCELL3:IMUX.IMUX.38.DELAY | HSADC.TEST_SI18 |
| TCELL3:IMUX.IMUX.47.DELAY | HSADC.TEST_SI19 |
| TCELL4:OUT.2.TMIN | HSADC.DATA_ADC0_34 |
| TCELL4:OUT.3.TMIN | HSADC.TEST_SO20 |
| TCELL4:OUT.4.TMIN | HSADC.STATUS_ADC0_6 |
| TCELL4:OUT.6.TMIN | HSADC.DATA_ADC0_35 |
| TCELL4:OUT.10.TMIN | HSADC.DATA_ADC0_36 |
| TCELL4:OUT.11.TMIN | HSADC.TEST_SO21 |
| TCELL4:OUT.13.TMIN | HSADC.DATA_ADC0_37 |
| TCELL4:OUT.16.TMIN | HSADC.DATA_ADC0_38 |
| TCELL4:OUT.19.TMIN | HSADC.DATA_ADC0_39 |
| TCELL4:OUT.21.TMIN | HSADC.TEST_SO22 |
| TCELL4:OUT.22.TMIN | HSADC.DATA_ADC0_40 |
| TCELL4:OUT.26.TMIN | HSADC.DATA_ADC0_41 |
| TCELL4:OUT.27.TMIN | HSADC.TEST_SO23 |
| TCELL4:OUT.28.TMIN | HSADC.STATUS_ADC0_7 |
| TCELL4:OUT.30.TMIN | HSADC.DATA_ADC0_42 |
| TCELL4:OUT.31.TMIN | HSADC.TEST_SO24 |
| TCELL4:IMUX.IMUX.7.DELAY | HSADC.TEST_SI22 |
| TCELL4:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC0_7 |
| TCELL4:IMUX.IMUX.17.DELAY | HSADC.TEST_SI20 |
| TCELL4:IMUX.IMUX.22.DELAY | HSADC.TEST_SI21 |
| TCELL4:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC0_6 |
| TCELL4:IMUX.IMUX.38.DELAY | HSADC.TEST_SI23 |
| TCELL4:IMUX.IMUX.47.DELAY | HSADC.TEST_SI24 |
| TCELL5:OUT.2.TMIN | HSADC.DATA_ADC0_43 |
| TCELL5:OUT.3.TMIN | HSADC.TEST_SO25 |
| TCELL5:OUT.6.TMIN | HSADC.DATA_ADC0_44 |
| TCELL5:OUT.8.TMIN | HSADC.STATUS_ADC0_8 |
| TCELL5:OUT.10.TMIN | HSADC.DATA_ADC0_45 |
| TCELL5:OUT.11.TMIN | HSADC.TEST_SO26 |
| TCELL5:OUT.14.TMIN | HSADC.DATA_ADC0_46 |
| TCELL5:OUT.18.TMIN | HSADC.DATA_ADC0_47 |
| TCELL5:OUT.21.TMIN | HSADC.TEST_SO27 |
| TCELL5:OUT.22.TMIN | HSADC.DATA_ADC0_48 |
| TCELL5:OUT.24.TMIN | HSADC.STATUS_ADC0_9 |
| TCELL5:OUT.26.TMIN | HSADC.DATA_ADC0_49 |
| TCELL5:OUT.27.TMIN | HSADC.TEST_SO28 |
| TCELL5:OUT.30.TMIN | HSADC.DATA_ADC0_50 |
| TCELL5:OUT.31.TMIN | HSADC.TEST_SO29 |
| TCELL5:IMUX.IMUX.7.DELAY | HSADC.TEST_SI27 |
| TCELL5:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC0_8 |
| TCELL5:IMUX.IMUX.17.DELAY | HSADC.TEST_SI25 |
| TCELL5:IMUX.IMUX.22.DELAY | HSADC.TEST_SI26 |
| TCELL5:IMUX.IMUX.38.DELAY | HSADC.TEST_SI28 |
| TCELL5:IMUX.IMUX.47.DELAY | HSADC.TEST_SI29 |
| TCELL6:OUT.2.TMIN | HSADC.DATA_ADC0_51 |
| TCELL6:OUT.3.TMIN | HSADC.TEST_SO30 |
| TCELL6:OUT.4.TMIN | HSADC.STATUS_ADC0_10 |
| TCELL6:OUT.6.TMIN | HSADC.DATA_ADC0_52 |
| TCELL6:OUT.10.TMIN | HSADC.DATA_ADC0_53 |
| TCELL6:OUT.11.TMIN | HSADC.TEST_SO31 |
| TCELL6:OUT.13.TMIN | HSADC.DATA_ADC0_54 |
| TCELL6:OUT.16.TMIN | HSADC.DATA_ADC0_55 |
| TCELL6:OUT.19.TMIN | HSADC.DATA_ADC0_56 |
| TCELL6:OUT.21.TMIN | HSADC.TEST_SO32 |
| TCELL6:OUT.22.TMIN | HSADC.DATA_ADC0_57 |
| TCELL6:OUT.26.TMIN | HSADC.DATA_ADC0_58 |
| TCELL6:OUT.27.TMIN | HSADC.TEST_SO33 |
| TCELL6:OUT.28.TMIN | HSADC.STATUS_ADC0_11 |
| TCELL6:OUT.30.TMIN | HSADC.DATA_ADC0_59 |
| TCELL6:OUT.31.TMIN | HSADC.TEST_SO34 |
| TCELL6:IMUX.IMUX.7.DELAY | HSADC.TEST_SI32 |
| TCELL6:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC0_10 |
| TCELL6:IMUX.IMUX.17.DELAY | HSADC.TEST_SI30 |
| TCELL6:IMUX.IMUX.22.DELAY | HSADC.TEST_SI31 |
| TCELL6:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC0_9 |
| TCELL6:IMUX.IMUX.38.DELAY | HSADC.TEST_SI33 |
| TCELL6:IMUX.IMUX.47.DELAY | HSADC.TEST_SI34 |
| TCELL7:OUT.2.TMIN | HSADC.DATA_ADC0_60 |
| TCELL7:OUT.3.TMIN | HSADC.TEST_SO35 |
| TCELL7:OUT.6.TMIN | HSADC.DATA_ADC0_61 |
| TCELL7:OUT.8.TMIN | HSADC.STATUS_ADC0_12 |
| TCELL7:OUT.10.TMIN | HSADC.DATA_ADC0_62 |
| TCELL7:OUT.11.TMIN | HSADC.TEST_SO36 |
| TCELL7:OUT.14.TMIN | HSADC.DATA_ADC0_63 |
| TCELL7:OUT.18.TMIN | HSADC.DATA_ADC0_64 |
| TCELL7:OUT.21.TMIN | HSADC.TEST_SO37 |
| TCELL7:OUT.22.TMIN | HSADC.DATA_ADC0_65 |
| TCELL7:OUT.24.TMIN | HSADC.STATUS_ADC0_13 |
| TCELL7:OUT.26.TMIN | HSADC.DATA_ADC0_66 |
| TCELL7:OUT.27.TMIN | HSADC.TEST_SO38 |
| TCELL7:OUT.30.TMIN | HSADC.DATA_ADC0_67 |
| TCELL7:OUT.31.TMIN | HSADC.TEST_SO39 |
| TCELL7:IMUX.IMUX.7.DELAY | HSADC.TEST_SI37 |
| TCELL7:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC0_11 |
| TCELL7:IMUX.IMUX.17.DELAY | HSADC.TEST_SI35 |
| TCELL7:IMUX.IMUX.22.DELAY | HSADC.TEST_SI36 |
| TCELL7:IMUX.IMUX.38.DELAY | HSADC.TEST_SI38 |
| TCELL7:IMUX.IMUX.47.DELAY | HSADC.TEST_SI39 |
| TCELL8:OUT.2.TMIN | HSADC.DATA_ADC0_68 |
| TCELL8:OUT.3.TMIN | HSADC.TEST_SO40 |
| TCELL8:OUT.6.TMIN | HSADC.DATA_ADC0_69 |
| TCELL8:OUT.10.TMIN | HSADC.DATA_ADC0_70 |
| TCELL8:OUT.11.TMIN | HSADC.TEST_SO41 |
| TCELL8:OUT.13.TMIN | HSADC.DATA_ADC0_71 |
| TCELL8:OUT.16.TMIN | HSADC.DATA_ADC0_72 |
| TCELL8:OUT.19.TMIN | HSADC.DATA_ADC0_73 |
| TCELL8:OUT.21.TMIN | HSADC.TEST_SO42 |
| TCELL8:OUT.22.TMIN | HSADC.DATA_ADC0_74 |
| TCELL8:OUT.26.TMIN | HSADC.DATA_ADC0_75 |
| TCELL8:OUT.27.TMIN | HSADC.TEST_SO43 |
| TCELL8:OUT.30.TMIN | HSADC.DATA_ADC0_76 |
| TCELL8:OUT.31.TMIN | HSADC.TEST_SO44 |
| TCELL8:IMUX.IMUX.7.DELAY | HSADC.TEST_SI42 |
| TCELL8:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC0_13 |
| TCELL8:IMUX.IMUX.17.DELAY | HSADC.TEST_SI40 |
| TCELL8:IMUX.IMUX.22.DELAY | HSADC.TEST_SI41 |
| TCELL8:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC0_12 |
| TCELL8:IMUX.IMUX.38.DELAY | HSADC.TEST_SI43 |
| TCELL8:IMUX.IMUX.47.DELAY | HSADC.TEST_SI44 |
| TCELL9:OUT.2.TMIN | HSADC.DATA_ADC0_77 |
| TCELL9:OUT.3.TMIN | HSADC.TEST_SO45 |
| TCELL9:OUT.6.TMIN | HSADC.DATA_ADC0_78 |
| TCELL9:OUT.8.TMIN | HSADC.STATUS_ADC0_14 |
| TCELL9:OUT.10.TMIN | HSADC.DATA_ADC0_79 |
| TCELL9:OUT.11.TMIN | HSADC.TEST_SO46 |
| TCELL9:OUT.14.TMIN | HSADC.DATA_ADC0_80 |
| TCELL9:OUT.18.TMIN | HSADC.DATA_ADC0_81 |
| TCELL9:OUT.21.TMIN | HSADC.TEST_SO47 |
| TCELL9:OUT.22.TMIN | HSADC.DATA_ADC0_82 |
| TCELL9:OUT.24.TMIN | HSADC.STATUS_ADC0_15 |
| TCELL9:OUT.26.TMIN | HSADC.DATA_ADC0_83 |
| TCELL9:OUT.27.TMIN | HSADC.TEST_SO48 |
| TCELL9:OUT.30.TMIN | HSADC.DATA_ADC0_84 |
| TCELL9:OUT.31.TMIN | HSADC.TEST_SO49 |
| TCELL9:IMUX.IMUX.7.DELAY | HSADC.TEST_SI47 |
| TCELL9:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC0_14 |
| TCELL9:IMUX.IMUX.17.DELAY | HSADC.TEST_SI45 |
| TCELL9:IMUX.IMUX.22.DELAY | HSADC.TEST_SI46 |
| TCELL9:IMUX.IMUX.38.DELAY | HSADC.TEST_SI48 |
| TCELL9:IMUX.IMUX.47.DELAY | HSADC.TEST_SI49 |
| TCELL10:OUT.2.TMIN | HSADC.DATA_ADC0_85 |
| TCELL10:OUT.3.TMIN | HSADC.TEST_SO50 |
| TCELL10:OUT.6.TMIN | HSADC.DATA_ADC0_86 |
| TCELL10:OUT.10.TMIN | HSADC.DATA_ADC0_87 |
| TCELL10:OUT.11.TMIN | HSADC.TEST_SO51 |
| TCELL10:OUT.13.TMIN | HSADC.DATA_ADC0_88 |
| TCELL10:OUT.16.TMIN | HSADC.DATA_ADC0_89 |
| TCELL10:OUT.19.TMIN | HSADC.DATA_ADC0_90 |
| TCELL10:OUT.21.TMIN | HSADC.TEST_SO52 |
| TCELL10:OUT.22.TMIN | HSADC.DATA_ADC0_91 |
| TCELL10:OUT.26.TMIN | HSADC.DATA_ADC0_92 |
| TCELL10:OUT.27.TMIN | HSADC.TEST_SO53 |
| TCELL10:OUT.30.TMIN | HSADC.DATA_ADC0_93 |
| TCELL10:OUT.31.TMIN | HSADC.TEST_SO54 |
| TCELL10:IMUX.IMUX.7.DELAY | HSADC.TEST_SI52 |
| TCELL10:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC0_15 |
| TCELL10:IMUX.IMUX.17.DELAY | HSADC.TEST_SI50 |
| TCELL10:IMUX.IMUX.22.DELAY | HSADC.TEST_SI51 |
| TCELL10:IMUX.IMUX.38.DELAY | HSADC.TEST_SI53 |
| TCELL10:IMUX.IMUX.47.DELAY | HSADC.TEST_SI54 |
| TCELL11:OUT.2.TMIN | HSADC.DATA_ADC0_94 |
| TCELL11:OUT.3.TMIN | HSADC.TEST_SO55 |
| TCELL11:OUT.6.TMIN | HSADC.DATA_ADC0_95 |
| TCELL11:OUT.10.TMIN | HSADC.DATA_ADC0_96 |
| TCELL11:OUT.11.TMIN | HSADC.TEST_SO56 |
| TCELL11:OUT.14.TMIN | HSADC.DATA_ADC0_97 |
| TCELL11:OUT.18.TMIN | HSADC.DATA_ADC0_98 |
| TCELL11:OUT.21.TMIN | HSADC.TEST_SO57 |
| TCELL11:OUT.22.TMIN | HSADC.DATA_ADC0_99 |
| TCELL11:OUT.26.TMIN | HSADC.DATA_ADC0_100 |
| TCELL11:OUT.27.TMIN | HSADC.TEST_SO58 |
| TCELL11:OUT.30.TMIN | HSADC.DATA_ADC0_101 |
| TCELL11:OUT.31.TMIN | HSADC.TEST_SO59 |
| TCELL11:IMUX.IMUX.7.DELAY | HSADC.TEST_SI57 |
| TCELL11:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC1_1 |
| TCELL11:IMUX.IMUX.17.DELAY | HSADC.TEST_SI55 |
| TCELL11:IMUX.IMUX.22.DELAY | HSADC.TEST_SI56 |
| TCELL11:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC1_0 |
| TCELL11:IMUX.IMUX.38.DELAY | HSADC.TEST_SI58 |
| TCELL11:IMUX.IMUX.47.DELAY | HSADC.TEST_SI59 |
| TCELL12:OUT.2.TMIN | HSADC.DATA_ADC0_102 |
| TCELL12:OUT.3.TMIN | HSADC.TEST_SO60 |
| TCELL12:OUT.6.TMIN | HSADC.DATA_ADC0_103 |
| TCELL12:OUT.8.TMIN | HSADC.STATUS_ADC1_0 |
| TCELL12:OUT.10.TMIN | HSADC.DATA_ADC0_104 |
| TCELL12:OUT.11.TMIN | HSADC.TEST_SO61 |
| TCELL12:OUT.13.TMIN | HSADC.DATA_ADC0_105 |
| TCELL12:OUT.16.TMIN | HSADC.DATA_ADC0_106 |
| TCELL12:OUT.19.TMIN | HSADC.DATA_ADC0_107 |
| TCELL12:OUT.21.TMIN | HSADC.TEST_SO62 |
| TCELL12:OUT.22.TMIN | HSADC.DATA_ADC0_108 |
| TCELL12:OUT.24.TMIN | HSADC.STATUS_ADC1_1 |
| TCELL12:OUT.26.TMIN | HSADC.DATA_ADC0_109 |
| TCELL12:OUT.27.TMIN | HSADC.TEST_SO63 |
| TCELL12:OUT.30.TMIN | HSADC.DATA_ADC0_110 |
| TCELL12:OUT.31.TMIN | HSADC.TEST_SO64 |
| TCELL12:IMUX.IMUX.1.DELAY | BUFG_GT_SYNC0.CE_IN |
| TCELL12:IMUX.IMUX.5.DELAY | BUFG_GT_SYNC3.CE_IN |
| TCELL12:IMUX.IMUX.7.DELAY | HSADC.TEST_SI62 |
| TCELL12:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC1_2 |
| TCELL12:IMUX.IMUX.17.DELAY | HSADC.TEST_SI60 |
| TCELL12:IMUX.IMUX.19.DELAY | BUFG_GT_SYNC1.CE_IN |
| TCELL12:IMUX.IMUX.21.DELAY | BUFG_GT_SYNC2.CE_IN |
| TCELL12:IMUX.IMUX.22.DELAY | HSADC.TEST_SI61 |
| TCELL12:IMUX.IMUX.38.DELAY | HSADC.TEST_SI63 |
| TCELL12:IMUX.IMUX.47.DELAY | HSADC.TEST_SI64 |
| TCELL13:OUT.2.TMIN | HSADC.DATA_ADC0_111 |
| TCELL13:OUT.3.TMIN | HSADC.TEST_SO65 |
| TCELL13:OUT.4.TMIN | HSADC.STATUS_ADC1_2 |
| TCELL13:OUT.6.TMIN | HSADC.DATA_ADC0_112 |
| TCELL13:OUT.10.TMIN | HSADC.DATA_ADC0_113 |
| TCELL13:OUT.11.TMIN | HSADC.TEST_SO66 |
| TCELL13:OUT.14.TMIN | HSADC.DATA_ADC0_114 |
| TCELL13:OUT.18.TMIN | HSADC.DATA_ADC0_115 |
| TCELL13:OUT.21.TMIN | HSADC.TEST_SO67 |
| TCELL13:OUT.22.TMIN | HSADC.DATA_ADC0_116 |
| TCELL13:OUT.26.TMIN | HSADC.DATA_ADC0_117 |
| TCELL13:OUT.27.TMIN | HSADC.TEST_SO68 |
| TCELL13:OUT.28.TMIN | HSADC.STATUS_ADC1_3 |
| TCELL13:OUT.30.TMIN | HSADC.DATA_ADC0_118 |
| TCELL13:OUT.31.TMIN | HSADC.TEST_SO69 |
| TCELL13:IMUX.IMUX.5.DELAY | BUFG_GT_SYNC1.RST_IN |
| TCELL13:IMUX.IMUX.6.DELAY | BUFG_GT_SYNC2.RST_IN |
| TCELL13:IMUX.IMUX.7.DELAY | HSADC.TEST_SI67 |
| TCELL13:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC1_4 |
| TCELL13:IMUX.IMUX.17.DELAY | HSADC.TEST_SI65 |
| TCELL13:IMUX.IMUX.19.DELAY | BUFG_GT_SYNC14.CE_IN |
| TCELL13:IMUX.IMUX.21.DELAY | BUFG_GT_SYNC0.RST_IN |
| TCELL13:IMUX.IMUX.22.DELAY | HSADC.TEST_SI66 |
| TCELL13:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC1_3 |
| TCELL13:IMUX.IMUX.29.DELAY | BUFG_GT_SYNC3.RST_IN |
| TCELL13:IMUX.IMUX.38.DELAY | HSADC.TEST_SI68 |
| TCELL13:IMUX.IMUX.47.DELAY | HSADC.TEST_SI69 |
| TCELL14:OUT.2.TMIN | HSADC.DATA_ADC0_119 |
| TCELL14:OUT.3.TMIN | HSADC.TEST_SO70 |
| TCELL14:OUT.6.TMIN | HSADC.DATA_ADC0_120 |
| TCELL14:OUT.8.TMIN | HSADC.STATUS_ADC1_4 |
| TCELL14:OUT.10.TMIN | HSADC.DATA_ADC0_121 |
| TCELL14:OUT.11.TMIN | HSADC.TEST_SO71 |
| TCELL14:OUT.13.TMIN | HSADC.DATA_ADC0_122 |
| TCELL14:OUT.16.TMIN | HSADC.DATA_ADC0_123 |
| TCELL14:OUT.19.TMIN | HSADC.DATA_ADC0_124 |
| TCELL14:OUT.21.TMIN | HSADC.TEST_SO72 |
| TCELL14:OUT.22.TMIN | HSADC.DATA_ADC0_125 |
| TCELL14:OUT.24.TMIN | HSADC.STATUS_ADC1_5 |
| TCELL14:OUT.26.TMIN | HSADC.DATA_ADC0_126 |
| TCELL14:OUT.27.TMIN | HSADC.TEST_SO73 |
| TCELL14:OUT.30.TMIN | HSADC.DATA_ADC0_127 |
| TCELL14:OUT.31.TMIN | HSADC.TEST_SO74 |
| TCELL14:IMUX.IMUX.5.DELAY | BUFG_GT0.CEMASK |
| TCELL14:IMUX.IMUX.6.DELAY | BUFG_GT1.CEMASK |
| TCELL14:IMUX.IMUX.7.DELAY | HSADC.TEST_SI72 |
| TCELL14:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC1_5 |
| TCELL14:IMUX.IMUX.9.DELAY | BUFG_GT3.CEMASK |
| TCELL14:IMUX.IMUX.10.DELAY | BUFG_GT4.CEMASK |
| TCELL14:IMUX.IMUX.11.DELAY | BUFG_GT5.CEMASK |
| TCELL14:IMUX.IMUX.13.DELAY | BUFG_GT6.CEMASK |
| TCELL14:IMUX.IMUX.17.DELAY | HSADC.TEST_SI70 |
| TCELL14:IMUX.IMUX.21.DELAY | BUFG_GT_SYNC14.RST_IN |
| TCELL14:IMUX.IMUX.22.DELAY | HSADC.TEST_SI71 |
| TCELL14:IMUX.IMUX.29.DELAY | BUFG_GT2.CEMASK |
| TCELL14:IMUX.IMUX.38.DELAY | HSADC.TEST_SI73 |
| TCELL14:IMUX.IMUX.42.DELAY | BUFG_GT7.CEMASK |
| TCELL14:IMUX.IMUX.44.DELAY | BUFG_GT8.CEMASK |
| TCELL14:IMUX.IMUX.46.DELAY | BUFG_GT9.CEMASK |
| TCELL14:IMUX.IMUX.47.DELAY | HSADC.TEST_SI74 |
| TCELL15:OUT.2.TMIN | HSADC.DATA_ADC1_0 |
| TCELL15:OUT.3.TMIN | HSADC.TEST_SO75 |
| TCELL15:OUT.4.TMIN | HSADC.STATUS_ADC1_6 |
| TCELL15:OUT.6.TMIN | HSADC.DATA_ADC1_1 |
| TCELL15:OUT.10.TMIN | HSADC.DATA_ADC1_2 |
| TCELL15:OUT.11.TMIN | HSADC.TEST_SO76 |
| TCELL15:OUT.13.TMIN | HSADC.DATA_ADC1_3 |
| TCELL15:OUT.16.TMIN | HSADC.DATA_ADC1_4 |
| TCELL15:OUT.19.TMIN | HSADC.DATA_ADC1_5 |
| TCELL15:OUT.21.TMIN | HSADC.TEST_SO77 |
| TCELL15:OUT.22.TMIN | HSADC.DATA_ADC1_6 |
| TCELL15:OUT.26.TMIN | HSADC.DATA_ADC1_7 |
| TCELL15:OUT.27.TMIN | HSADC.TEST_SO78 |
| TCELL15:OUT.28.TMIN | HSADC.STATUS_ADC1_7 |
| TCELL15:OUT.30.TMIN | HSADC.DATA_ADC1_8 |
| TCELL15:OUT.31.TMIN | HSADC.TEST_SO79 |
| TCELL15:IMUX.IMUX.1.DELAY | BUFG_GT10.CEMASK |
| TCELL15:IMUX.IMUX.5.DELAY | BUFG_GT13.CEMASK |
| TCELL15:IMUX.IMUX.6.DELAY | BUFG_GT14.CEMASK |
| TCELL15:IMUX.IMUX.7.DELAY | HSADC.TEST_SI77 |
| TCELL15:IMUX.IMUX.9.DELAY | BUFG_GT16.CEMASK |
| TCELL15:IMUX.IMUX.10.DELAY | BUFG_GT17.CEMASK |
| TCELL15:IMUX.IMUX.11.DELAY | BUFG_GT18.CEMASK |
| TCELL15:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC1_7 |
| TCELL15:IMUX.IMUX.13.DELAY | BUFG_GT19.CEMASK |
| TCELL15:IMUX.IMUX.17.DELAY | HSADC.TEST_SI75 |
| TCELL15:IMUX.IMUX.19.DELAY | BUFG_GT11.CEMASK |
| TCELL15:IMUX.IMUX.21.DELAY | BUFG_GT12.CEMASK |
| TCELL15:IMUX.IMUX.22.DELAY | HSADC.TEST_SI76 |
| TCELL15:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC1_6 |
| TCELL15:IMUX.IMUX.29.DELAY | BUFG_GT15.CEMASK |
| TCELL15:IMUX.IMUX.38.DELAY | HSADC.TEST_SI78 |
| TCELL15:IMUX.IMUX.42.DELAY | BUFG_GT20.CEMASK |
| TCELL15:IMUX.IMUX.44.DELAY | BUFG_GT21.CEMASK |
| TCELL15:IMUX.IMUX.46.DELAY | BUFG_GT22.CEMASK |
| TCELL15:IMUX.IMUX.47.DELAY | HSADC.TEST_SI79 |
| TCELL16:OUT.2.TMIN | HSADC.DATA_ADC1_9 |
| TCELL16:OUT.3.TMIN | HSADC.TEST_SO80 |
| TCELL16:OUT.6.TMIN | HSADC.DATA_ADC1_10 |
| TCELL16:OUT.8.TMIN | HSADC.STATUS_ADC1_8 |
| TCELL16:OUT.10.TMIN | HSADC.DATA_ADC1_11 |
| TCELL16:OUT.11.TMIN | HSADC.TEST_SO81 |
| TCELL16:OUT.14.TMIN | HSADC.DATA_ADC1_12 |
| TCELL16:OUT.18.TMIN | HSADC.DATA_ADC1_13 |
| TCELL16:OUT.21.TMIN | HSADC.TEST_SO82 |
| TCELL16:OUT.22.TMIN | HSADC.DATA_ADC1_14 |
| TCELL16:OUT.24.TMIN | HSADC.STATUS_ADC1_9 |
| TCELL16:OUT.26.TMIN | HSADC.DATA_ADC1_15 |
| TCELL16:OUT.27.TMIN | HSADC.TEST_SO83 |
| TCELL16:OUT.30.TMIN | HSADC.DATA_ADC1_16 |
| TCELL16:OUT.31.TMIN | HSADC.TEST_SO84 |
| TCELL16:IMUX.IMUX.1.DELAY | BUFG_GT23.CEMASK |
| TCELL16:IMUX.IMUX.5.DELAY | BUFG_GT2.RSTMASK |
| TCELL16:IMUX.IMUX.6.DELAY | BUFG_GT3.RSTMASK |
| TCELL16:IMUX.IMUX.7.DELAY | HSADC.TEST_SI82 |
| TCELL16:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC1_8 |
| TCELL16:IMUX.IMUX.9.DELAY | BUFG_GT5.RSTMASK |
| TCELL16:IMUX.IMUX.10.DELAY | BUFG_GT6.RSTMASK |
| TCELL16:IMUX.IMUX.11.DELAY | BUFG_GT7.RSTMASK |
| TCELL16:IMUX.IMUX.13.DELAY | BUFG_GT8.RSTMASK |
| TCELL16:IMUX.IMUX.17.DELAY | HSADC.TEST_SI80 |
| TCELL16:IMUX.IMUX.19.DELAY | BUFG_GT0.RSTMASK |
| TCELL16:IMUX.IMUX.21.DELAY | BUFG_GT1.RSTMASK |
| TCELL16:IMUX.IMUX.22.DELAY | HSADC.TEST_SI81 |
| TCELL16:IMUX.IMUX.29.DELAY | BUFG_GT4.RSTMASK |
| TCELL16:IMUX.IMUX.38.DELAY | HSADC.TEST_SI83 |
| TCELL16:IMUX.IMUX.42.DELAY | BUFG_GT9.RSTMASK |
| TCELL16:IMUX.IMUX.44.DELAY | BUFG_GT10.RSTMASK |
| TCELL16:IMUX.IMUX.46.DELAY | BUFG_GT11.RSTMASK |
| TCELL16:IMUX.IMUX.47.DELAY | HSADC.TEST_SI84 |
| TCELL17:OUT.2.TMIN | HSADC.DATA_ADC1_17 |
| TCELL17:OUT.3.TMIN | HSADC.TEST_SO85 |
| TCELL17:OUT.4.TMIN | HSADC.STATUS_ADC1_10 |
| TCELL17:OUT.6.TMIN | HSADC.DATA_ADC1_18 |
| TCELL17:OUT.10.TMIN | HSADC.DATA_ADC1_19 |
| TCELL17:OUT.11.TMIN | HSADC.TEST_SO86 |
| TCELL17:OUT.13.TMIN | HSADC.DATA_ADC1_20 |
| TCELL17:OUT.16.TMIN | HSADC.DATA_ADC1_21 |
| TCELL17:OUT.19.TMIN | HSADC.DATA_ADC1_22 |
| TCELL17:OUT.21.TMIN | HSADC.TEST_SO87 |
| TCELL17:OUT.22.TMIN | HSADC.DATA_ADC1_23 |
| TCELL17:OUT.26.TMIN | HSADC.DATA_ADC1_24 |
| TCELL17:OUT.27.TMIN | HSADC.TEST_SO88 |
| TCELL17:OUT.28.TMIN | HSADC.STATUS_ADC1_11 |
| TCELL17:OUT.30.TMIN | HSADC.DATA_ADC1_25 |
| TCELL17:OUT.31.TMIN | HSADC.TEST_SO89 |
| TCELL17:IMUX.CTRL.5 | HSADC.TEST_SCAN_CLK1 |
| TCELL17:IMUX.IMUX.1.DELAY | BUFG_GT12.RSTMASK |
| TCELL17:IMUX.IMUX.5.DELAY | BUFG_GT15.RSTMASK |
| TCELL17:IMUX.IMUX.6.DELAY | BUFG_GT16.RSTMASK |
| TCELL17:IMUX.IMUX.7.DELAY | HSADC.TEST_SI87 |
| TCELL17:IMUX.IMUX.9.DELAY | BUFG_GT18.RSTMASK |
| TCELL17:IMUX.IMUX.10.DELAY | BUFG_GT19.RSTMASK |
| TCELL17:IMUX.IMUX.11.DELAY | BUFG_GT20.RSTMASK |
| TCELL17:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC1_10 |
| TCELL17:IMUX.IMUX.13.DELAY | BUFG_GT21.RSTMASK |
| TCELL17:IMUX.IMUX.17.DELAY | HSADC.TEST_SI85 |
| TCELL17:IMUX.IMUX.19.DELAY | BUFG_GT13.RSTMASK |
| TCELL17:IMUX.IMUX.21.DELAY | BUFG_GT14.RSTMASK |
| TCELL17:IMUX.IMUX.22.DELAY | HSADC.TEST_SI86 |
| TCELL17:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC1_9 |
| TCELL17:IMUX.IMUX.29.DELAY | BUFG_GT17.RSTMASK |
| TCELL17:IMUX.IMUX.38.DELAY | HSADC.TEST_SI88 |
| TCELL17:IMUX.IMUX.42.DELAY | BUFG_GT22.RSTMASK |
| TCELL17:IMUX.IMUX.44.DELAY | BUFG_GT23.RSTMASK |
| TCELL17:IMUX.IMUX.47.DELAY | HSADC.TEST_SI89 |
| TCELL18:OUT.2.TMIN | HSADC.DATA_ADC1_26 |
| TCELL18:OUT.3.TMIN | HSADC.TEST_SO90 |
| TCELL18:OUT.6.TMIN | HSADC.DATA_ADC1_27 |
| TCELL18:OUT.8.TMIN | HSADC.STATUS_ADC1_12 |
| TCELL18:OUT.10.TMIN | HSADC.DATA_ADC1_28 |
| TCELL18:OUT.11.TMIN | HSADC.TEST_SO91 |
| TCELL18:OUT.14.TMIN | HSADC.DATA_ADC1_29 |
| TCELL18:OUT.18.TMIN | HSADC.DATA_ADC1_30 |
| TCELL18:OUT.21.TMIN | HSADC.TEST_SO92 |
| TCELL18:OUT.22.TMIN | HSADC.DATA_ADC1_31 |
| TCELL18:OUT.24.TMIN | HSADC.STATUS_ADC1_13 |
| TCELL18:OUT.26.TMIN | HSADC.DATA_ADC1_32 |
| TCELL18:OUT.27.TMIN | HSADC.TEST_SO93 |
| TCELL18:OUT.30.TMIN | HSADC.DATA_ADC1_33 |
| TCELL18:OUT.31.TMIN | HSADC.TEST_SO94 |
| TCELL18:IMUX.IMUX.7.DELAY | HSADC.TEST_SI92 |
| TCELL18:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC1_11 |
| TCELL18:IMUX.IMUX.17.DELAY | HSADC.TEST_SI90 |
| TCELL18:IMUX.IMUX.22.DELAY | HSADC.TEST_SI91 |
| TCELL18:IMUX.IMUX.38.DELAY | HSADC.TEST_SI93 |
| TCELL18:IMUX.IMUX.47.DELAY | HSADC.TEST_SI94 |
| TCELL19:OUT.2.TMIN | HSADC.DATA_ADC1_34 |
| TCELL19:OUT.3.TMIN | HSADC.TEST_SO95 |
| TCELL19:OUT.6.TMIN | HSADC.DATA_ADC1_35 |
| TCELL19:OUT.10.TMIN | HSADC.DATA_ADC1_36 |
| TCELL19:OUT.11.TMIN | HSADC.TEST_SO96 |
| TCELL19:OUT.13.TMIN | HSADC.DATA_ADC1_37 |
| TCELL19:OUT.16.TMIN | HSADC.DATA_ADC1_38 |
| TCELL19:OUT.19.TMIN | HSADC.DATA_ADC1_39 |
| TCELL19:OUT.21.TMIN | HSADC.TEST_SO97 |
| TCELL19:OUT.22.TMIN | HSADC.DATA_ADC1_40 |
| TCELL19:OUT.26.TMIN | HSADC.DATA_ADC1_41 |
| TCELL19:OUT.27.TMIN | HSADC.TEST_SO98 |
| TCELL19:OUT.30.TMIN | HSADC.DATA_ADC1_42 |
| TCELL19:OUT.31.TMIN | HSADC.TEST_SO99 |
| TCELL19:IMUX.IMUX.7.DELAY | HSADC.TEST_SI97 |
| TCELL19:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC1_13 |
| TCELL19:IMUX.IMUX.17.DELAY | HSADC.TEST_SI95 |
| TCELL19:IMUX.IMUX.22.DELAY | HSADC.TEST_SI96 |
| TCELL19:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC1_12 |
| TCELL19:IMUX.IMUX.38.DELAY | HSADC.TEST_SI98 |
| TCELL19:IMUX.IMUX.47.DELAY | HSADC.TEST_SI99 |
| TCELL20:OUT.2.TMIN | HSADC.DATA_ADC1_43 |
| TCELL20:OUT.3.TMIN | HSADC.TEST_SO100 |
| TCELL20:OUT.6.TMIN | HSADC.DATA_ADC1_44 |
| TCELL20:OUT.8.TMIN | HSADC.STATUS_ADC1_14 |
| TCELL20:OUT.10.TMIN | HSADC.DATA_ADC1_45 |
| TCELL20:OUT.11.TMIN | HSADC.TEST_SO101 |
| TCELL20:OUT.14.TMIN | HSADC.DATA_ADC1_46 |
| TCELL20:OUT.17.TMIN | HSADC.TEST_STATUS0 |
| TCELL20:OUT.18.TMIN | HSADC.DATA_ADC1_47 |
| TCELL20:OUT.21.TMIN | HSADC.TEST_SO102 |
| TCELL20:OUT.22.TMIN | HSADC.DATA_ADC1_48 |
| TCELL20:OUT.24.TMIN | HSADC.STATUS_ADC1_15 |
| TCELL20:OUT.26.TMIN | HSADC.DATA_ADC1_49 |
| TCELL20:OUT.27.TMIN | HSADC.TEST_SO103 |
| TCELL20:OUT.30.TMIN | HSADC.DATA_ADC1_50 |
| TCELL20:OUT.31.TMIN | HSADC.TEST_SO104 |
| TCELL20:IMUX.IMUX.7.DELAY | HSADC.TEST_SI102 |
| TCELL20:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC1_15 |
| TCELL20:IMUX.IMUX.17.DELAY | HSADC.TEST_SI100 |
| TCELL20:IMUX.IMUX.22.DELAY | HSADC.TEST_SI101 |
| TCELL20:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC1_14 |
| TCELL20:IMUX.IMUX.38.DELAY | HSADC.TEST_SI103 |
| TCELL20:IMUX.IMUX.47.DELAY | HSADC.TEST_SI104 |
| TCELL21:OUT.2.TMIN | HSADC.DATA_ADC1_51 |
| TCELL21:OUT.3.TMIN | HSADC.TEST_SO105 |
| TCELL21:OUT.6.TMIN | HSADC.DATA_ADC1_52 |
| TCELL21:OUT.10.TMIN | HSADC.DATA_ADC1_53 |
| TCELL21:OUT.11.TMIN | HSADC.TEST_SO106 |
| TCELL21:OUT.13.TMIN | HSADC.DATA_ADC1_54 |
| TCELL21:OUT.16.TMIN | HSADC.DATA_ADC1_55 |
| TCELL21:OUT.17.TMIN | HSADC.TEST_STATUS1 |
| TCELL21:OUT.19.TMIN | HSADC.DATA_ADC1_56 |
| TCELL21:OUT.21.TMIN | HSADC.TEST_SO107 |
| TCELL21:OUT.22.TMIN | HSADC.DATA_ADC1_57 |
| TCELL21:OUT.26.TMIN | HSADC.DATA_ADC1_58 |
| TCELL21:OUT.27.TMIN | HSADC.TEST_SO108 |
| TCELL21:OUT.30.TMIN | HSADC.DATA_ADC1_59 |
| TCELL21:OUT.31.TMIN | HSADC.TEST_SO109 |
| TCELL21:IMUX.IMUX.7.DELAY | HSADC.TEST_SI107 |
| TCELL21:IMUX.IMUX.8.DELAY | HSADC.CONTROL_COMMON0 |
| TCELL21:IMUX.IMUX.17.DELAY | HSADC.TEST_SI105 |
| TCELL21:IMUX.IMUX.22.DELAY | HSADC.TEST_SI106 |
| TCELL21:IMUX.IMUX.38.DELAY | HSADC.TEST_SI108 |
| TCELL21:IMUX.IMUX.47.DELAY | HSADC.TEST_SI109 |
| TCELL22:OUT.2.TMIN | HSADC.DATA_ADC1_60 |
| TCELL22:OUT.3.TMIN | HSADC.TEST_SO110 |
| TCELL22:OUT.4.TMIN | HSADC.STATUS_COMMON0 |
| TCELL22:OUT.6.TMIN | HSADC.DATA_ADC1_61 |
| TCELL22:OUT.10.TMIN | HSADC.DATA_ADC1_62 |
| TCELL22:OUT.11.TMIN | HSADC.TEST_SO111 |
| TCELL22:OUT.14.TMIN | HSADC.DATA_ADC1_63 |
| TCELL22:OUT.17.TMIN | HSADC.TEST_STATUS2 |
| TCELL22:OUT.18.TMIN | HSADC.DATA_ADC1_64 |
| TCELL22:OUT.21.TMIN | HSADC.TEST_SO112 |
| TCELL22:OUT.22.TMIN | HSADC.DATA_ADC1_65 |
| TCELL22:OUT.26.TMIN | HSADC.DATA_ADC1_66 |
| TCELL22:OUT.27.TMIN | HSADC.TEST_SO113 |
| TCELL22:OUT.28.TMIN | HSADC.STATUS_COMMON1 |
| TCELL22:OUT.30.TMIN | HSADC.DATA_ADC1_67 |
| TCELL22:OUT.31.TMIN | HSADC.TEST_SO114 |
| TCELL22:IMUX.IMUX.7.DELAY | HSADC.TEST_SI112 |
| TCELL22:IMUX.IMUX.8.DELAY | HSADC.CONTROL_COMMON2 |
| TCELL22:IMUX.IMUX.12.DELAY | HSADC.CONTROL_COMMON3 |
| TCELL22:IMUX.IMUX.17.DELAY | HSADC.TEST_SI110 |
| TCELL22:IMUX.IMUX.22.DELAY | HSADC.TEST_SI111 |
| TCELL22:IMUX.IMUX.23.DELAY | HSADC.CONTROL_COMMON1 |
| TCELL22:IMUX.IMUX.26.DELAY | HSADC.TEST_SCAN_CTRL0 |
| TCELL22:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_CTRL1 |
| TCELL22:IMUX.IMUX.38.DELAY | HSADC.TEST_SI113 |
| TCELL22:IMUX.IMUX.47.DELAY | HSADC.TEST_SI114 |
| TCELL23:OUT.2.TMIN | HSADC.DATA_ADC1_68 |
| TCELL23:OUT.3.TMIN | HSADC.TEST_SO115 |
| TCELL23:OUT.6.TMIN | HSADC.DATA_ADC1_69 |
| TCELL23:OUT.8.TMIN | HSADC.STATUS_COMMON2 |
| TCELL23:OUT.10.TMIN | HSADC.DATA_ADC1_70 |
| TCELL23:OUT.11.TMIN | HSADC.TEST_SO116 |
| TCELL23:OUT.13.TMIN | HSADC.DATA_ADC1_71 |
| TCELL23:OUT.16.TMIN | HSADC.DATA_ADC1_72 |
| TCELL23:OUT.17.TMIN | HSADC.TEST_STATUS3 |
| TCELL23:OUT.19.TMIN | HSADC.DATA_ADC1_73 |
| TCELL23:OUT.21.TMIN | HSADC.TEST_SO117 |
| TCELL23:OUT.22.TMIN | HSADC.DATA_ADC1_74 |
| TCELL23:OUT.24.TMIN | HSADC.STATUS_COMMON3 |
| TCELL23:OUT.26.TMIN | HSADC.DATA_ADC1_75 |
| TCELL23:OUT.27.TMIN | HSADC.TEST_SO118 |
| TCELL23:OUT.30.TMIN | HSADC.DATA_ADC1_76 |
| TCELL23:OUT.31.TMIN | HSADC.TEST_SO119 |
| TCELL23:IMUX.IMUX.7.DELAY | HSADC.TEST_SI117 |
| TCELL23:IMUX.IMUX.12.DELAY | HSADC.CONTROL_COMMON5 |
| TCELL23:IMUX.IMUX.17.DELAY | HSADC.TEST_SI115 |
| TCELL23:IMUX.IMUX.22.DELAY | HSADC.TEST_SI116 |
| TCELL23:IMUX.IMUX.23.DELAY | HSADC.CONTROL_COMMON4 |
| TCELL23:IMUX.IMUX.26.DELAY | HSADC.TEST_SCAN_CTRL2 |
| TCELL23:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_CTRL3 |
| TCELL23:IMUX.IMUX.38.DELAY | HSADC.TEST_SI118 |
| TCELL23:IMUX.IMUX.47.DELAY | HSADC.TEST_SI119 |
| TCELL24:OUT.2.TMIN | HSADC.DATA_ADC1_77 |
| TCELL24:OUT.3.TMIN | HSADC.TEST_SO120 |
| TCELL24:OUT.4.TMIN | HSADC.STATUS_COMMON4 |
| TCELL24:OUT.6.TMIN | HSADC.DATA_ADC1_78 |
| TCELL24:OUT.10.TMIN | HSADC.DATA_ADC1_79 |
| TCELL24:OUT.11.TMIN | HSADC.TEST_SO121 |
| TCELL24:OUT.14.TMIN | HSADC.DATA_ADC1_80 |
| TCELL24:OUT.17.TMIN | HSADC.TEST_STATUS4 |
| TCELL24:OUT.18.TMIN | HSADC.DATA_ADC1_81 |
| TCELL24:OUT.21.TMIN | HSADC.TEST_SO122 |
| TCELL24:OUT.22.TMIN | HSADC.DATA_ADC1_82 |
| TCELL24:OUT.26.TMIN | HSADC.DATA_ADC1_83 |
| TCELL24:OUT.27.TMIN | HSADC.TEST_SO123 |
| TCELL24:OUT.28.TMIN | HSADC.STATUS_COMMON5 |
| TCELL24:OUT.30.TMIN | HSADC.DATA_ADC1_84 |
| TCELL24:OUT.31.TMIN | HSADC.TEST_SO124 |
| TCELL24:IMUX.IMUX.7.DELAY | HSADC.TEST_SI122 |
| TCELL24:IMUX.IMUX.12.DELAY | HSADC.CONTROL_COMMON7 |
| TCELL24:IMUX.IMUX.17.DELAY | HSADC.TEST_SI120 |
| TCELL24:IMUX.IMUX.22.DELAY | HSADC.TEST_SI121 |
| TCELL24:IMUX.IMUX.23.DELAY | HSADC.CONTROL_COMMON6 |
| TCELL24:IMUX.IMUX.26.DELAY | HSADC.TEST_SCAN_CTRL4 |
| TCELL24:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_CTRL5 |
| TCELL24:IMUX.IMUX.38.DELAY | HSADC.TEST_SI123 |
| TCELL24:IMUX.IMUX.47.DELAY | HSADC.TEST_SI124 |
| TCELL25:OUT.2.TMIN | HSADC.DATA_ADC1_85 |
| TCELL25:OUT.3.TMIN | HSADC.TEST_SO125 |
| TCELL25:OUT.6.TMIN | HSADC.DATA_ADC1_86 |
| TCELL25:OUT.8.TMIN | HSADC.STATUS_COMMON6 |
| TCELL25:OUT.10.TMIN | HSADC.DATA_ADC1_87 |
| TCELL25:OUT.11.TMIN | HSADC.TEST_SO126 |
| TCELL25:OUT.13.TMIN | HSADC.DATA_ADC1_88 |
| TCELL25:OUT.16.TMIN | HSADC.DATA_ADC1_89 |
| TCELL25:OUT.17.TMIN | HSADC.TEST_STATUS5 |
| TCELL25:OUT.19.TMIN | HSADC.DATA_ADC1_90 |
| TCELL25:OUT.21.TMIN | HSADC.TEST_SO127 |
| TCELL25:OUT.22.TMIN | HSADC.DATA_ADC1_91 |
| TCELL25:OUT.24.TMIN | HSADC.STATUS_COMMON7 |
| TCELL25:OUT.26.TMIN | HSADC.DATA_ADC1_92 |
| TCELL25:OUT.27.TMIN | HSADC.TEST_SO128 |
| TCELL25:OUT.30.TMIN | HSADC.DATA_ADC1_93 |
| TCELL25:OUT.31.TMIN | HSADC.TEST_SO129 |
| TCELL25:IMUX.IMUX.7.DELAY | HSADC.TEST_SI127 |
| TCELL25:IMUX.IMUX.8.DELAY | HSADC.DI1 |
| TCELL25:IMUX.IMUX.12.DELAY | HSADC.DI2 |
| TCELL25:IMUX.IMUX.17.DELAY | HSADC.TEST_SI125 |
| TCELL25:IMUX.IMUX.22.DELAY | HSADC.TEST_SI126 |
| TCELL25:IMUX.IMUX.23.DELAY | HSADC.DI0 |
| TCELL25:IMUX.IMUX.26.DELAY | HSADC.TEST_SCAN_CTRL6 |
| TCELL25:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_CTRL7 |
| TCELL25:IMUX.IMUX.38.DELAY | HSADC.TEST_SI128 |
| TCELL25:IMUX.IMUX.47.DELAY | HSADC.TEST_SI129 |
| TCELL26:OUT.2.TMIN | HSADC.DATA_ADC1_94 |
| TCELL26:OUT.3.TMIN | HSADC.TEST_SO130 |
| TCELL26:OUT.6.TMIN | HSADC.DATA_ADC1_95 |
| TCELL26:OUT.8.TMIN | HSADC.DOUT0 |
| TCELL26:OUT.10.TMIN | HSADC.DATA_ADC1_96 |
| TCELL26:OUT.11.TMIN | HSADC.TEST_SO131 |
| TCELL26:OUT.14.TMIN | HSADC.DATA_ADC1_97 |
| TCELL26:OUT.17.TMIN | HSADC.TEST_STATUS6 |
| TCELL26:OUT.18.TMIN | HSADC.DATA_ADC1_98 |
| TCELL26:OUT.21.TMIN | HSADC.TEST_SO132 |
| TCELL26:OUT.22.TMIN | HSADC.DATA_ADC1_99 |
| TCELL26:OUT.24.TMIN | HSADC.DOUT1 |
| TCELL26:OUT.26.TMIN | HSADC.DATA_ADC1_100 |
| TCELL26:OUT.27.TMIN | HSADC.TEST_SO133 |
| TCELL26:OUT.30.TMIN | HSADC.DATA_ADC1_101 |
| TCELL26:OUT.31.TMIN | HSADC.TEST_SO134 |
| TCELL26:IMUX.IMUX.7.DELAY | HSADC.TEST_SI132 |
| TCELL26:IMUX.IMUX.8.DELAY | HSADC.DI4 |
| TCELL26:IMUX.IMUX.12.DELAY | HSADC.DI5 |
| TCELL26:IMUX.IMUX.17.DELAY | HSADC.TEST_SI130 |
| TCELL26:IMUX.IMUX.22.DELAY | HSADC.TEST_SI131 |
| TCELL26:IMUX.IMUX.23.DELAY | HSADC.DI3 |
| TCELL26:IMUX.IMUX.38.DELAY | HSADC.TEST_SI133 |
| TCELL26:IMUX.IMUX.47.DELAY | HSADC.TEST_SI134 |
| TCELL27:OUT.2.TMIN | HSADC.DATA_ADC1_102 |
| TCELL27:OUT.3.TMIN | HSADC.TEST_SO135 |
| TCELL27:OUT.5.TMIN | HSADC.TEST_SO136 |
| TCELL27:OUT.6.TMIN | HSADC.DATA_ADC1_103 |
| TCELL27:OUT.8.TMIN | HSADC.DOUT2 |
| TCELL27:OUT.10.TMIN | HSADC.DATA_ADC1_104 |
| TCELL27:OUT.11.TMIN | HSADC.TEST_SO137 |
| TCELL27:OUT.13.TMIN | HSADC.DATA_ADC1_105 |
| TCELL27:OUT.15.TMIN | HSADC.TEST_SO138 |
| TCELL27:OUT.16.TMIN | HSADC.DATA_ADC1_106 |
| TCELL27:OUT.17.TMIN | HSADC.TEST_STATUS7 |
| TCELL27:OUT.19.TMIN | HSADC.DATA_ADC1_107 |
| TCELL27:OUT.21.TMIN | HSADC.TEST_SO139 |
| TCELL27:OUT.22.TMIN | HSADC.DATA_ADC1_108 |
| TCELL27:OUT.24.TMIN | HSADC.DOUT3 |
| TCELL27:OUT.26.TMIN | HSADC.DATA_ADC1_109 |
| TCELL27:OUT.27.TMIN | HSADC.TEST_SO140 |
| TCELL27:OUT.29.TMIN | HSADC.TEST_SO141 |
| TCELL27:OUT.30.TMIN | HSADC.DATA_ADC1_110 |
| TCELL27:OUT.31.TMIN | HSADC.TEST_SO142 |
| TCELL27:IMUX.CTRL.5 | HSADC.TEST_SCAN_CLK2 |
| TCELL27:IMUX.IMUX.7.DELAY | HSADC.TEST_SI138 |
| TCELL27:IMUX.IMUX.8.DELAY | HSADC.DI7 |
| TCELL27:IMUX.IMUX.12.DELAY | HSADC.DI8 |
| TCELL27:IMUX.IMUX.17.DELAY | HSADC.TEST_SI135 |
| TCELL27:IMUX.IMUX.22.DELAY | HSADC.TEST_SI136 |
| TCELL27:IMUX.IMUX.23.DELAY | HSADC.DI6 |
| TCELL27:IMUX.IMUX.24.DELAY | HSADC.TEST_SI137 |
| TCELL27:IMUX.IMUX.32.DELAY | HSADC.TEST_SI139 |
| TCELL27:IMUX.IMUX.36.DELAY | HSADC.PLL_SCAN_MODE_B_FD |
| TCELL27:IMUX.IMUX.38.DELAY | HSADC.TEST_SI140 |
| TCELL27:IMUX.IMUX.43.DELAY | HSADC.TEST_SI141 |
| TCELL27:IMUX.IMUX.47.DELAY | HSADC.TEST_SI142 |
| TCELL28:OUT.2.TMIN | HSADC.DATA_ADC1_111 |
| TCELL28:OUT.3.TMIN | HSADC.TEST_SO143 |
| TCELL28:OUT.6.TMIN | HSADC.DATA_ADC1_112 |
| TCELL28:OUT.8.TMIN | HSADC.DOUT4 |
| TCELL28:OUT.10.TMIN | HSADC.DATA_ADC1_113 |
| TCELL28:OUT.11.TMIN | HSADC.TEST_SO144 |
| TCELL28:OUT.14.TMIN | HSADC.DATA_ADC1_114 |
| TCELL28:OUT.17.TMIN | HSADC.PLL_SCAN_OUT_B_FD0 |
| TCELL28:OUT.18.TMIN | HSADC.DATA_ADC1_115 |
| TCELL28:OUT.19.TMIN | HSADC.TEST_SO145 |
| TCELL28:OUT.21.TMIN | HSADC.TEST_SO146 |
| TCELL28:OUT.22.TMIN | HSADC.DATA_ADC1_116 |
| TCELL28:OUT.24.TMIN | HSADC.DOUT5 |
| TCELL28:OUT.26.TMIN | HSADC.DATA_ADC1_117 |
| TCELL28:OUT.27.TMIN | HSADC.TEST_SO147 |
| TCELL28:OUT.29.TMIN | HSADC.TEST_SO148 |
| TCELL28:OUT.30.TMIN | HSADC.DATA_ADC1_118 |
| TCELL28:OUT.31.TMIN | HSADC.TEST_SO149 |
| TCELL28:IMUX.CTRL.4 | HSADC.DCLK |
| TCELL28:IMUX.CTRL.5 | HSADC.PLL_SCAN_CLK_FD0 |
| TCELL28:IMUX.IMUX.7.DELAY | HSADC.TEST_SI146 |
| TCELL28:IMUX.IMUX.8.DELAY | HSADC.DI10 |
| TCELL28:IMUX.IMUX.12.DELAY | HSADC.DI11 |
| TCELL28:IMUX.IMUX.17.DELAY | HSADC.TEST_SI143 |
| TCELL28:IMUX.IMUX.18.DELAY | HSADC.TEST_SI144 |
| TCELL28:IMUX.IMUX.22.DELAY | HSADC.TEST_SI145 |
| TCELL28:IMUX.IMUX.23.DELAY | HSADC.DI9 |
| TCELL28:IMUX.IMUX.26.DELAY | HSADC.PLL_SCAN_EN_B_FD |
| TCELL28:IMUX.IMUX.34.DELAY | HSADC.TEST_SCAN_RESET |
| TCELL28:IMUX.IMUX.36.DELAY | HSADC.TEST_SE_B |
| TCELL28:IMUX.IMUX.38.DELAY | HSADC.TEST_SI147 |
| TCELL28:IMUX.IMUX.43.DELAY | HSADC.TEST_SI148 |
| TCELL28:IMUX.IMUX.47.DELAY | HSADC.TEST_SI149 |
| TCELL29:OUT.2.TMIN | HSADC.DATA_ADC1_119 |
| TCELL29:OUT.6.TMIN | HSADC.DATA_ADC1_120 |
| TCELL29:OUT.8.TMIN | HSADC.DOUT6 |
| TCELL29:OUT.10.TMIN | HSADC.DATA_ADC1_121 |
| TCELL29:OUT.13.TMIN | HSADC.DATA_ADC1_122 |
| TCELL29:OUT.16.TMIN | HSADC.DATA_ADC1_123 |
| TCELL29:OUT.19.TMIN | HSADC.DATA_ADC1_124 |
| TCELL29:OUT.22.TMIN | HSADC.DATA_ADC1_125 |
| TCELL29:OUT.24.TMIN | HSADC.DOUT7 |
| TCELL29:OUT.26.TMIN | HSADC.DATA_ADC1_126 |
| TCELL29:OUT.28.TMIN | HSADC.DRDY |
| TCELL29:OUT.30.TMIN | HSADC.DATA_ADC1_127 |
| TCELL29:IMUX.IMUX.8.DELAY | HSADC.DI13 |
| TCELL29:IMUX.IMUX.12.DELAY | HSADC.DI14 |
| TCELL29:IMUX.IMUX.23.DELAY | HSADC.DI12 |
| TCELL30:OUT.2.TMIN | HSADC.DATA_ADC2_0 |
| TCELL30:OUT.6.TMIN | HSADC.DATA_ADC2_1 |
| TCELL30:OUT.8.TMIN | HSADC.DOUT8 |
| TCELL30:OUT.10.TMIN | HSADC.DATA_ADC2_2 |
| TCELL30:OUT.13.TMIN | HSADC.DATA_ADC2_3 |
| TCELL30:OUT.16.TMIN | HSADC.DATA_ADC2_4 |
| TCELL30:OUT.19.TMIN | HSADC.DATA_ADC2_5 |
| TCELL30:OUT.22.TMIN | HSADC.DATA_ADC2_6 |
| TCELL30:OUT.24.TMIN | HSADC.DOUT9 |
| TCELL30:OUT.26.TMIN | HSADC.DATA_ADC2_7 |
| TCELL30:OUT.30.TMIN | HSADC.DATA_ADC2_8 |
| TCELL30:IMUX.IMUX.8.DELAY | HSADC.DADDR0 |
| TCELL30:IMUX.IMUX.12.DELAY | HSADC.DADDR1 |
| TCELL30:IMUX.IMUX.23.DELAY | HSADC.DI15 |
| TCELL30:RCLK.IMUX.17 | BUFG_GT_SYNC14.CLK_IN |
| TCELL31:OUT.2.TMIN | HSADC.DATA_ADC2_9 |
| TCELL31:OUT.3.TMIN | HSADC.TEST_SO150 |
| TCELL31:OUT.6.TMIN | HSADC.DATA_ADC2_10 |
| TCELL31:OUT.8.TMIN | HSADC.DOUT10 |
| TCELL31:OUT.10.TMIN | HSADC.DATA_ADC2_11 |
| TCELL31:OUT.11.TMIN | HSADC.TEST_SO151 |
| TCELL31:OUT.14.TMIN | HSADC.DATA_ADC2_12 |
| TCELL31:OUT.17.TMIN | HSADC.PLL_SCAN_OUT_B_FD1 |
| TCELL31:OUT.18.TMIN | HSADC.DATA_ADC2_13 |
| TCELL31:OUT.19.TMIN | HSADC.TEST_SO152 |
| TCELL31:OUT.21.TMIN | HSADC.TEST_SO153 |
| TCELL31:OUT.22.TMIN | HSADC.DATA_ADC2_14 |
| TCELL31:OUT.24.TMIN | HSADC.DOUT11 |
| TCELL31:OUT.26.TMIN | HSADC.DATA_ADC2_15 |
| TCELL31:OUT.27.TMIN | HSADC.TEST_SO154 |
| TCELL31:OUT.29.TMIN | HSADC.TEST_SO155 |
| TCELL31:OUT.30.TMIN | HSADC.DATA_ADC2_16 |
| TCELL31:OUT.31.TMIN | HSADC.TEST_SO156 |
| TCELL31:IMUX.CTRL.4 | HSADC.PLL_SCAN_CLK_FD1 |
| TCELL31:IMUX.CTRL.5 | HSADC.FABRIC_CLK |
| TCELL31:IMUX.IMUX.7.DELAY | HSADC.TEST_SI153 |
| TCELL31:IMUX.IMUX.8.DELAY | HSADC.DADDR3 |
| TCELL31:IMUX.IMUX.12.DELAY | HSADC.DADDR4 |
| TCELL31:IMUX.IMUX.17.DELAY | HSADC.TEST_SI150 |
| TCELL31:IMUX.IMUX.18.DELAY | HSADC.TEST_SI151 |
| TCELL31:IMUX.IMUX.22.DELAY | HSADC.TEST_SI152 |
| TCELL31:IMUX.IMUX.23.DELAY | HSADC.DADDR2 |
| TCELL31:IMUX.IMUX.26.DELAY | HSADC.PLL_SCAN_IN_FD0 |
| TCELL31:IMUX.IMUX.32.DELAY | HSADC.TEST_SI154 |
| TCELL31:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_MODE_B |
| TCELL31:IMUX.IMUX.38.DELAY | HSADC.TEST_SI155 |
| TCELL31:IMUX.IMUX.43.DELAY | HSADC.TEST_SI156 |
| TCELL31:IMUX.IMUX.47.DELAY | HSADC.TEST_SI157 |
| TCELL32:OUT.2.TMIN | HSADC.DATA_ADC2_17 |
| TCELL32:OUT.3.TMIN | HSADC.TEST_SO157 |
| TCELL32:OUT.6.TMIN | HSADC.DATA_ADC2_18 |
| TCELL32:OUT.8.TMIN | HSADC.DOUT12 |
| TCELL32:OUT.10.TMIN | HSADC.DATA_ADC2_19 |
| TCELL32:OUT.11.TMIN | HSADC.TEST_SO158 |
| TCELL32:OUT.13.TMIN | HSADC.DATA_ADC2_20 |
| TCELL32:OUT.14.TMIN | HSADC.TEST_SO159 |
| TCELL32:OUT.16.TMIN | HSADC.DATA_ADC2_21 |
| TCELL32:OUT.17.TMIN | HSADC.TEST_STATUS8 |
| TCELL32:OUT.19.TMIN | HSADC.DATA_ADC2_22 |
| TCELL32:OUT.21.TMIN | HSADC.TEST_SO160 |
| TCELL32:OUT.22.TMIN | HSADC.DATA_ADC2_23 |
| TCELL32:OUT.24.TMIN | HSADC.DOUT13 |
| TCELL32:OUT.26.TMIN | HSADC.DATA_ADC2_24 |
| TCELL32:OUT.27.TMIN | HSADC.TEST_SO161 |
| TCELL32:OUT.30.TMIN | HSADC.DATA_ADC2_25 |
| TCELL32:OUT.31.TMIN | HSADC.TEST_SO162 |
| TCELL32:IMUX.CTRL.4 | HSADC.PLL_MONCLK |
| TCELL32:IMUX.CTRL.5 | HSADC.PLL_REFCLK_IN_FABRIC |
| TCELL32:IMUX.IMUX.7.DELAY | HSADC.TEST_SI161 |
| TCELL32:IMUX.IMUX.8.DELAY | HSADC.DADDR6 |
| TCELL32:IMUX.IMUX.12.DELAY | HSADC.DADDR7 |
| TCELL32:IMUX.IMUX.17.DELAY | HSADC.TEST_SI158 |
| TCELL32:IMUX.IMUX.22.DELAY | HSADC.TEST_SI159 |
| TCELL32:IMUX.IMUX.23.DELAY | HSADC.DADDR5 |
| TCELL32:IMUX.IMUX.24.DELAY | HSADC.TEST_SI160 |
| TCELL32:IMUX.IMUX.26.DELAY | HSADC.PLL_SCAN_IN_FD1 |
| TCELL32:IMUX.IMUX.38.DELAY | HSADC.TEST_SI162 |
| TCELL32:IMUX.IMUX.43.DELAY | HSADC.TEST_SI163 |
| TCELL32:IMUX.IMUX.47.DELAY | HSADC.TEST_SI164 |
| TCELL33:OUT.2.TMIN | HSADC.DATA_ADC2_26 |
| TCELL33:OUT.3.TMIN | HSADC.TEST_SO163 |
| TCELL33:OUT.6.TMIN | HSADC.DATA_ADC2_27 |
| TCELL33:OUT.8.TMIN | HSADC.DOUT14 |
| TCELL33:OUT.10.TMIN | HSADC.DATA_ADC2_28 |
| TCELL33:OUT.11.TMIN | HSADC.TEST_SO164 |
| TCELL33:OUT.14.TMIN | HSADC.DATA_ADC2_29 |
| TCELL33:OUT.16.TMIN | HSADC.TEST_SO165 |
| TCELL33:OUT.17.TMIN | HSADC.TEST_STATUS9 |
| TCELL33:OUT.18.TMIN | HSADC.DATA_ADC2_30 |
| TCELL33:OUT.21.TMIN | HSADC.TEST_SO166 |
| TCELL33:OUT.22.TMIN | HSADC.DATA_ADC2_31 |
| TCELL33:OUT.24.TMIN | HSADC.DOUT15 |
| TCELL33:OUT.26.TMIN | HSADC.DATA_ADC2_32 |
| TCELL33:OUT.27.TMIN | HSADC.TEST_SO167 |
| TCELL33:OUT.30.TMIN | HSADC.DATA_ADC2_33 |
| TCELL33:OUT.31.TMIN | HSADC.TEST_SO168 |
| TCELL33:IMUX.CTRL.5 | HSADC.CLK_FIFO_LM |
| TCELL33:IMUX.IMUX.7.DELAY | HSADC.TEST_SI167 |
| TCELL33:IMUX.IMUX.8.DELAY | HSADC.DADDR9 |
| TCELL33:IMUX.IMUX.12.DELAY | HSADC.DADDR10 |
| TCELL33:IMUX.IMUX.17.DELAY | HSADC.TEST_SI165 |
| TCELL33:IMUX.IMUX.22.DELAY | HSADC.TEST_SI166 |
| TCELL33:IMUX.IMUX.23.DELAY | HSADC.DADDR8 |
| TCELL33:IMUX.IMUX.26.DELAY | HSADC.PLL_SCAN_RST_EN_FD |
| TCELL33:IMUX.IMUX.38.DELAY | HSADC.TEST_SI168 |
| TCELL33:IMUX.IMUX.47.DELAY | HSADC.TEST_SI169 |
| TCELL34:OUT.2.TMIN | HSADC.DATA_ADC2_34 |
| TCELL34:OUT.3.TMIN | HSADC.TEST_SO169 |
| TCELL34:OUT.4.TMIN | HSADC.STATUS_COMMON8 |
| TCELL34:OUT.6.TMIN | HSADC.DATA_ADC2_35 |
| TCELL34:OUT.10.TMIN | HSADC.DATA_ADC2_36 |
| TCELL34:OUT.11.TMIN | HSADC.TEST_SO170 |
| TCELL34:OUT.13.TMIN | HSADC.DATA_ADC2_37 |
| TCELL34:OUT.16.TMIN | HSADC.DATA_ADC2_38 |
| TCELL34:OUT.17.TMIN | HSADC.TEST_STATUS10 |
| TCELL34:OUT.19.TMIN | HSADC.DATA_ADC2_39 |
| TCELL34:OUT.21.TMIN | HSADC.TEST_SO171 |
| TCELL34:OUT.22.TMIN | HSADC.DATA_ADC2_40 |
| TCELL34:OUT.26.TMIN | HSADC.DATA_ADC2_41 |
| TCELL34:OUT.27.TMIN | HSADC.TEST_SO172 |
| TCELL34:OUT.28.TMIN | HSADC.STATUS_COMMON9 |
| TCELL34:OUT.30.TMIN | HSADC.DATA_ADC2_42 |
| TCELL34:OUT.31.TMIN | HSADC.TEST_SO173 |
| TCELL34:IMUX.IMUX.7.DELAY | HSADC.TEST_SI172 |
| TCELL34:IMUX.IMUX.8.DELAY | HSADC.DEN |
| TCELL34:IMUX.IMUX.12.DELAY | HSADC.DADDR11 |
| TCELL34:IMUX.IMUX.17.DELAY | HSADC.TEST_SI170 |
| TCELL34:IMUX.IMUX.22.DELAY | HSADC.TEST_SI171 |
| TCELL34:IMUX.IMUX.23.DELAY | HSADC.DWE |
| TCELL34:IMUX.IMUX.26.DELAY | HSADC.TEST_SCAN_CTRL8 |
| TCELL34:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_CTRL9 |
| TCELL34:IMUX.IMUX.38.DELAY | HSADC.TEST_SI173 |
| TCELL34:IMUX.IMUX.47.DELAY | HSADC.TEST_SI174 |
| TCELL35:OUT.2.TMIN | HSADC.DATA_ADC2_43 |
| TCELL35:OUT.3.TMIN | HSADC.TEST_SO174 |
| TCELL35:OUT.6.TMIN | HSADC.DATA_ADC2_44 |
| TCELL35:OUT.8.TMIN | HSADC.STATUS_COMMON10 |
| TCELL35:OUT.10.TMIN | HSADC.DATA_ADC2_45 |
| TCELL35:OUT.11.TMIN | HSADC.TEST_SO175 |
| TCELL35:OUT.14.TMIN | HSADC.DATA_ADC2_46 |
| TCELL35:OUT.16.TMIN | HSADC.TEST_SO176 |
| TCELL35:OUT.17.TMIN | HSADC.TEST_STATUS11 |
| TCELL35:OUT.18.TMIN | HSADC.DATA_ADC2_47 |
| TCELL35:OUT.21.TMIN | HSADC.TEST_SO177 |
| TCELL35:OUT.22.TMIN | HSADC.DATA_ADC2_48 |
| TCELL35:OUT.24.TMIN | HSADC.STATUS_COMMON11 |
| TCELL35:OUT.26.TMIN | HSADC.DATA_ADC2_49 |
| TCELL35:OUT.27.TMIN | HSADC.TEST_SO178 |
| TCELL35:OUT.30.TMIN | HSADC.DATA_ADC2_50 |
| TCELL35:OUT.31.TMIN | HSADC.TEST_SO179 |
| TCELL35:IMUX.IMUX.7.DELAY | HSADC.TEST_SI177 |
| TCELL35:IMUX.IMUX.12.DELAY | HSADC.CONTROL_COMMON9 |
| TCELL35:IMUX.IMUX.17.DELAY | HSADC.TEST_SI175 |
| TCELL35:IMUX.IMUX.22.DELAY | HSADC.TEST_SI176 |
| TCELL35:IMUX.IMUX.23.DELAY | HSADC.CONTROL_COMMON8 |
| TCELL35:IMUX.IMUX.26.DELAY | HSADC.TEST_SCAN_CTRL10 |
| TCELL35:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_CTRL11 |
| TCELL35:IMUX.IMUX.38.DELAY | HSADC.TEST_SI178 |
| TCELL35:IMUX.IMUX.47.DELAY | HSADC.TEST_SI179 |
| TCELL36:OUT.2.TMIN | HSADC.DATA_ADC2_51 |
| TCELL36:OUT.3.TMIN | HSADC.TEST_SO180 |
| TCELL36:OUT.4.TMIN | HSADC.STATUS_COMMON12 |
| TCELL36:OUT.6.TMIN | HSADC.DATA_ADC2_52 |
| TCELL36:OUT.10.TMIN | HSADC.DATA_ADC2_53 |
| TCELL36:OUT.11.TMIN | HSADC.TEST_SO181 |
| TCELL36:OUT.13.TMIN | HSADC.DATA_ADC2_54 |
| TCELL36:OUT.16.TMIN | HSADC.DATA_ADC2_55 |
| TCELL36:OUT.17.TMIN | HSADC.TEST_STATUS12 |
| TCELL36:OUT.19.TMIN | HSADC.DATA_ADC2_56 |
| TCELL36:OUT.21.TMIN | HSADC.TEST_SO182 |
| TCELL36:OUT.22.TMIN | HSADC.DATA_ADC2_57 |
| TCELL36:OUT.26.TMIN | HSADC.DATA_ADC2_58 |
| TCELL36:OUT.27.TMIN | HSADC.TEST_SO183 |
| TCELL36:OUT.28.TMIN | HSADC.STATUS_COMMON13 |
| TCELL36:OUT.30.TMIN | HSADC.DATA_ADC2_59 |
| TCELL36:OUT.31.TMIN | HSADC.TEST_SO184 |
| TCELL36:IMUX.IMUX.7.DELAY | HSADC.TEST_SI182 |
| TCELL36:IMUX.IMUX.12.DELAY | HSADC.CONTROL_COMMON11 |
| TCELL36:IMUX.IMUX.17.DELAY | HSADC.TEST_SI180 |
| TCELL36:IMUX.IMUX.22.DELAY | HSADC.TEST_SI181 |
| TCELL36:IMUX.IMUX.23.DELAY | HSADC.CONTROL_COMMON10 |
| TCELL36:IMUX.IMUX.26.DELAY | HSADC.TEST_SCAN_CTRL12 |
| TCELL36:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_CTRL13 |
| TCELL36:IMUX.IMUX.38.DELAY | HSADC.TEST_SI183 |
| TCELL36:IMUX.IMUX.47.DELAY | HSADC.TEST_SI184 |
| TCELL37:OUT.2.TMIN | HSADC.DATA_ADC2_60 |
| TCELL37:OUT.3.TMIN | HSADC.TEST_SO185 |
| TCELL37:OUT.6.TMIN | HSADC.DATA_ADC2_61 |
| TCELL37:OUT.8.TMIN | HSADC.STATUS_COMMON14 |
| TCELL37:OUT.10.TMIN | HSADC.DATA_ADC2_62 |
| TCELL37:OUT.11.TMIN | HSADC.TEST_SO186 |
| TCELL37:OUT.14.TMIN | HSADC.DATA_ADC2_63 |
| TCELL37:OUT.17.TMIN | HSADC.TEST_STATUS13 |
| TCELL37:OUT.18.TMIN | HSADC.DATA_ADC2_64 |
| TCELL37:OUT.21.TMIN | HSADC.TEST_SO187 |
| TCELL37:OUT.22.TMIN | HSADC.DATA_ADC2_65 |
| TCELL37:OUT.24.TMIN | HSADC.STATUS_COMMON15 |
| TCELL37:OUT.26.TMIN | HSADC.DATA_ADC2_66 |
| TCELL37:OUT.27.TMIN | HSADC.TEST_SO188 |
| TCELL37:OUT.30.TMIN | HSADC.DATA_ADC2_67 |
| TCELL37:OUT.31.TMIN | HSADC.TEST_SO189 |
| TCELL37:IMUX.IMUX.7.DELAY | HSADC.TEST_SI187 |
| TCELL37:IMUX.IMUX.8.DELAY | HSADC.CONTROL_COMMON13 |
| TCELL37:IMUX.IMUX.12.DELAY | HSADC.CONTROL_COMMON14 |
| TCELL37:IMUX.IMUX.17.DELAY | HSADC.TEST_SI185 |
| TCELL37:IMUX.IMUX.22.DELAY | HSADC.TEST_SI186 |
| TCELL37:IMUX.IMUX.23.DELAY | HSADC.CONTROL_COMMON12 |
| TCELL37:IMUX.IMUX.26.DELAY | HSADC.TEST_SCAN_CTRL14 |
| TCELL37:IMUX.IMUX.36.DELAY | HSADC.TEST_SCAN_CTRL15 |
| TCELL37:IMUX.IMUX.38.DELAY | HSADC.TEST_SI188 |
| TCELL37:IMUX.IMUX.47.DELAY | HSADC.TEST_SI189 |
| TCELL38:OUT.2.TMIN | HSADC.DATA_ADC2_68 |
| TCELL38:OUT.3.TMIN | HSADC.TEST_SO190 |
| TCELL38:OUT.6.TMIN | HSADC.DATA_ADC2_69 |
| TCELL38:OUT.10.TMIN | HSADC.DATA_ADC2_70 |
| TCELL38:OUT.11.TMIN | HSADC.TEST_SO191 |
| TCELL38:OUT.13.TMIN | HSADC.DATA_ADC2_71 |
| TCELL38:OUT.16.TMIN | HSADC.DATA_ADC2_72 |
| TCELL38:OUT.17.TMIN | HSADC.TEST_STATUS14 |
| TCELL38:OUT.19.TMIN | HSADC.DATA_ADC2_73 |
| TCELL38:OUT.21.TMIN | HSADC.TEST_SO192 |
| TCELL38:OUT.22.TMIN | HSADC.DATA_ADC2_74 |
| TCELL38:OUT.26.TMIN | HSADC.DATA_ADC2_75 |
| TCELL38:OUT.27.TMIN | HSADC.TEST_SO193 |
| TCELL38:OUT.30.TMIN | HSADC.DATA_ADC2_76 |
| TCELL38:OUT.31.TMIN | HSADC.TEST_SO194 |
| TCELL38:IMUX.IMUX.7.DELAY | HSADC.TEST_SI192 |
| TCELL38:IMUX.IMUX.8.DELAY | HSADC.CONTROL_COMMON15 |
| TCELL38:IMUX.IMUX.17.DELAY | HSADC.TEST_SI190 |
| TCELL38:IMUX.IMUX.22.DELAY | HSADC.TEST_SI191 |
| TCELL38:IMUX.IMUX.38.DELAY | HSADC.TEST_SI193 |
| TCELL38:IMUX.IMUX.47.DELAY | HSADC.TEST_SI194 |
| TCELL39:OUT.2.TMIN | HSADC.DATA_ADC2_77 |
| TCELL39:OUT.3.TMIN | HSADC.TEST_SO195 |
| TCELL39:OUT.6.TMIN | HSADC.DATA_ADC2_78 |
| TCELL39:OUT.10.TMIN | HSADC.DATA_ADC2_79 |
| TCELL39:OUT.11.TMIN | HSADC.TEST_SO196 |
| TCELL39:OUT.14.TMIN | HSADC.DATA_ADC2_80 |
| TCELL39:OUT.17.TMIN | HSADC.TEST_STATUS15 |
| TCELL39:OUT.18.TMIN | HSADC.DATA_ADC2_81 |
| TCELL39:OUT.21.TMIN | HSADC.TEST_SO197 |
| TCELL39:OUT.22.TMIN | HSADC.DATA_ADC2_82 |
| TCELL39:OUT.26.TMIN | HSADC.DATA_ADC2_83 |
| TCELL39:OUT.27.TMIN | HSADC.TEST_SO198 |
| TCELL39:OUT.30.TMIN | HSADC.DATA_ADC2_84 |
| TCELL39:OUT.31.TMIN | HSADC.TEST_SO199 |
| TCELL39:IMUX.IMUX.7.DELAY | HSADC.TEST_SI197 |
| TCELL39:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC2_1 |
| TCELL39:IMUX.IMUX.17.DELAY | HSADC.TEST_SI195 |
| TCELL39:IMUX.IMUX.22.DELAY | HSADC.TEST_SI196 |
| TCELL39:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC2_0 |
| TCELL39:IMUX.IMUX.38.DELAY | HSADC.TEST_SI198 |
| TCELL39:IMUX.IMUX.47.DELAY | HSADC.TEST_SI199 |
| TCELL40:OUT.2.TMIN | HSADC.DATA_ADC2_85 |
| TCELL40:OUT.3.TMIN | HSADC.TEST_SO200 |
| TCELL40:OUT.4.TMIN | HSADC.STATUS_ADC2_0 |
| TCELL40:OUT.6.TMIN | HSADC.DATA_ADC2_86 |
| TCELL40:OUT.10.TMIN | HSADC.DATA_ADC2_87 |
| TCELL40:OUT.11.TMIN | HSADC.TEST_SO201 |
| TCELL40:OUT.13.TMIN | HSADC.DATA_ADC2_88 |
| TCELL40:OUT.16.TMIN | HSADC.DATA_ADC2_89 |
| TCELL40:OUT.19.TMIN | HSADC.DATA_ADC2_90 |
| TCELL40:OUT.21.TMIN | HSADC.TEST_SO202 |
| TCELL40:OUT.22.TMIN | HSADC.DATA_ADC2_91 |
| TCELL40:OUT.26.TMIN | HSADC.DATA_ADC2_92 |
| TCELL40:OUT.27.TMIN | HSADC.TEST_SO203 |
| TCELL40:OUT.28.TMIN | HSADC.STATUS_ADC2_1 |
| TCELL40:OUT.30.TMIN | HSADC.DATA_ADC2_93 |
| TCELL40:OUT.31.TMIN | HSADC.TEST_SO204 |
| TCELL40:IMUX.IMUX.7.DELAY | HSADC.TEST_SI202 |
| TCELL40:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC2_3 |
| TCELL40:IMUX.IMUX.17.DELAY | HSADC.TEST_SI200 |
| TCELL40:IMUX.IMUX.22.DELAY | HSADC.TEST_SI201 |
| TCELL40:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC2_2 |
| TCELL40:IMUX.IMUX.38.DELAY | HSADC.TEST_SI203 |
| TCELL40:IMUX.IMUX.47.DELAY | HSADC.TEST_SI204 |
| TCELL41:OUT.2.TMIN | HSADC.DATA_ADC2_94 |
| TCELL41:OUT.3.TMIN | HSADC.TEST_SO205 |
| TCELL41:OUT.6.TMIN | HSADC.DATA_ADC2_95 |
| TCELL41:OUT.8.TMIN | HSADC.STATUS_ADC2_2 |
| TCELL41:OUT.10.TMIN | HSADC.DATA_ADC2_96 |
| TCELL41:OUT.11.TMIN | HSADC.TEST_SO206 |
| TCELL41:OUT.14.TMIN | HSADC.DATA_ADC2_97 |
| TCELL41:OUT.18.TMIN | HSADC.DATA_ADC2_98 |
| TCELL41:OUT.21.TMIN | HSADC.TEST_SO207 |
| TCELL41:OUT.22.TMIN | HSADC.DATA_ADC2_99 |
| TCELL41:OUT.24.TMIN | HSADC.STATUS_ADC2_3 |
| TCELL41:OUT.26.TMIN | HSADC.DATA_ADC2_100 |
| TCELL41:OUT.27.TMIN | HSADC.TEST_SO208 |
| TCELL41:OUT.30.TMIN | HSADC.DATA_ADC2_101 |
| TCELL41:OUT.31.TMIN | HSADC.TEST_SO209 |
| TCELL41:IMUX.CTRL.5 | HSADC.TEST_SCAN_CLK3 |
| TCELL41:IMUX.IMUX.7.DELAY | HSADC.TEST_SI207 |
| TCELL41:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC2_4 |
| TCELL41:IMUX.IMUX.17.DELAY | HSADC.TEST_SI205 |
| TCELL41:IMUX.IMUX.22.DELAY | HSADC.TEST_SI206 |
| TCELL41:IMUX.IMUX.38.DELAY | HSADC.TEST_SI208 |
| TCELL41:IMUX.IMUX.47.DELAY | HSADC.TEST_SI209 |
| TCELL42:OUT.2.TMIN | HSADC.DATA_ADC2_102 |
| TCELL42:OUT.3.TMIN | HSADC.TEST_SO210 |
| TCELL42:OUT.4.TMIN | HSADC.STATUS_ADC2_4 |
| TCELL42:OUT.6.TMIN | HSADC.DATA_ADC2_103 |
| TCELL42:OUT.10.TMIN | HSADC.DATA_ADC2_104 |
| TCELL42:OUT.11.TMIN | HSADC.TEST_SO211 |
| TCELL42:OUT.13.TMIN | HSADC.DATA_ADC2_105 |
| TCELL42:OUT.16.TMIN | HSADC.DATA_ADC2_106 |
| TCELL42:OUT.19.TMIN | HSADC.DATA_ADC2_107 |
| TCELL42:OUT.21.TMIN | HSADC.TEST_SO212 |
| TCELL42:OUT.22.TMIN | HSADC.DATA_ADC2_108 |
| TCELL42:OUT.26.TMIN | HSADC.DATA_ADC2_109 |
| TCELL42:OUT.27.TMIN | HSADC.TEST_SO213 |
| TCELL42:OUT.28.TMIN | HSADC.STATUS_ADC2_5 |
| TCELL42:OUT.30.TMIN | HSADC.DATA_ADC2_110 |
| TCELL42:OUT.31.TMIN | HSADC.TEST_SO214 |
| TCELL42:IMUX.IMUX.7.DELAY | HSADC.TEST_SI212 |
| TCELL42:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC2_6 |
| TCELL42:IMUX.IMUX.17.DELAY | HSADC.TEST_SI210 |
| TCELL42:IMUX.IMUX.22.DELAY | HSADC.TEST_SI211 |
| TCELL42:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC2_5 |
| TCELL42:IMUX.IMUX.38.DELAY | HSADC.TEST_SI213 |
| TCELL42:IMUX.IMUX.47.DELAY | HSADC.TEST_SI214 |
| TCELL43:OUT.2.TMIN | HSADC.DATA_ADC2_111 |
| TCELL43:OUT.3.TMIN | HSADC.TEST_SO215 |
| TCELL43:OUT.6.TMIN | HSADC.DATA_ADC2_112 |
| TCELL43:OUT.8.TMIN | HSADC.STATUS_ADC2_6 |
| TCELL43:OUT.10.TMIN | HSADC.DATA_ADC2_113 |
| TCELL43:OUT.11.TMIN | HSADC.TEST_SO216 |
| TCELL43:OUT.14.TMIN | HSADC.DATA_ADC2_114 |
| TCELL43:OUT.18.TMIN | HSADC.DATA_ADC2_115 |
| TCELL43:OUT.21.TMIN | HSADC.TEST_SO217 |
| TCELL43:OUT.22.TMIN | HSADC.DATA_ADC2_116 |
| TCELL43:OUT.24.TMIN | HSADC.STATUS_ADC2_7 |
| TCELL43:OUT.26.TMIN | HSADC.DATA_ADC2_117 |
| TCELL43:OUT.27.TMIN | HSADC.TEST_SO218 |
| TCELL43:OUT.30.TMIN | HSADC.DATA_ADC2_118 |
| TCELL43:OUT.31.TMIN | HSADC.TEST_SO219 |
| TCELL43:IMUX.IMUX.7.DELAY | HSADC.TEST_SI217 |
| TCELL43:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC2_7 |
| TCELL43:IMUX.IMUX.17.DELAY | HSADC.TEST_SI215 |
| TCELL43:IMUX.IMUX.22.DELAY | HSADC.TEST_SI216 |
| TCELL43:IMUX.IMUX.38.DELAY | HSADC.TEST_SI218 |
| TCELL43:IMUX.IMUX.47.DELAY | HSADC.TEST_SI219 |
| TCELL44:OUT.2.TMIN | HSADC.DATA_ADC2_119 |
| TCELL44:OUT.3.TMIN | HSADC.TEST_SO220 |
| TCELL44:OUT.4.TMIN | HSADC.STATUS_ADC2_8 |
| TCELL44:OUT.6.TMIN | HSADC.DATA_ADC2_120 |
| TCELL44:OUT.10.TMIN | HSADC.DATA_ADC2_121 |
| TCELL44:OUT.11.TMIN | HSADC.TEST_SO221 |
| TCELL44:OUT.13.TMIN | HSADC.DATA_ADC2_122 |
| TCELL44:OUT.16.TMIN | HSADC.DATA_ADC2_123 |
| TCELL44:OUT.19.TMIN | HSADC.DATA_ADC2_124 |
| TCELL44:OUT.21.TMIN | HSADC.TEST_SO222 |
| TCELL44:OUT.22.TMIN | HSADC.DATA_ADC2_125 |
| TCELL44:OUT.26.TMIN | HSADC.DATA_ADC2_126 |
| TCELL44:OUT.27.TMIN | HSADC.TEST_SO223 |
| TCELL44:OUT.28.TMIN | HSADC.STATUS_ADC2_9 |
| TCELL44:OUT.30.TMIN | HSADC.DATA_ADC2_127 |
| TCELL44:OUT.31.TMIN | HSADC.TEST_SO224 |
| TCELL44:IMUX.IMUX.7.DELAY | HSADC.TEST_SI222 |
| TCELL44:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC2_9 |
| TCELL44:IMUX.IMUX.17.DELAY | HSADC.TEST_SI220 |
| TCELL44:IMUX.IMUX.22.DELAY | HSADC.TEST_SI221 |
| TCELL44:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC2_8 |
| TCELL44:IMUX.IMUX.38.DELAY | HSADC.TEST_SI223 |
| TCELL44:IMUX.IMUX.47.DELAY | HSADC.TEST_SI224 |
| TCELL45:OUT.2.TMIN | HSADC.DATA_ADC3_0 |
| TCELL45:OUT.3.TMIN | HSADC.TEST_SO225 |
| TCELL45:OUT.6.TMIN | HSADC.DATA_ADC3_1 |
| TCELL45:OUT.8.TMIN | HSADC.STATUS_ADC2_10 |
| TCELL45:OUT.10.TMIN | HSADC.DATA_ADC3_2 |
| TCELL45:OUT.11.TMIN | HSADC.TEST_SO226 |
| TCELL45:OUT.13.TMIN | HSADC.DATA_ADC3_3 |
| TCELL45:OUT.16.TMIN | HSADC.DATA_ADC3_4 |
| TCELL45:OUT.19.TMIN | HSADC.DATA_ADC3_5 |
| TCELL45:OUT.21.TMIN | HSADC.TEST_SO227 |
| TCELL45:OUT.22.TMIN | HSADC.DATA_ADC3_6 |
| TCELL45:OUT.24.TMIN | HSADC.STATUS_ADC2_11 |
| TCELL45:OUT.26.TMIN | HSADC.DATA_ADC3_7 |
| TCELL45:OUT.27.TMIN | HSADC.TEST_SO228 |
| TCELL45:OUT.30.TMIN | HSADC.DATA_ADC3_8 |
| TCELL45:OUT.31.TMIN | HSADC.TEST_SO229 |
| TCELL45:IMUX.IMUX.7.DELAY | HSADC.TEST_SI227 |
| TCELL45:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC2_10 |
| TCELL45:IMUX.IMUX.17.DELAY | HSADC.TEST_SI225 |
| TCELL45:IMUX.IMUX.22.DELAY | HSADC.TEST_SI226 |
| TCELL45:IMUX.IMUX.38.DELAY | HSADC.TEST_SI228 |
| TCELL45:IMUX.IMUX.47.DELAY | HSADC.TEST_SI229 |
| TCELL46:OUT.2.TMIN | HSADC.DATA_ADC3_9 |
| TCELL46:OUT.3.TMIN | HSADC.TEST_SO230 |
| TCELL46:OUT.4.TMIN | HSADC.STATUS_ADC2_12 |
| TCELL46:OUT.6.TMIN | HSADC.DATA_ADC3_10 |
| TCELL46:OUT.10.TMIN | HSADC.DATA_ADC3_11 |
| TCELL46:OUT.11.TMIN | HSADC.TEST_SO231 |
| TCELL46:OUT.14.TMIN | HSADC.DATA_ADC3_12 |
| TCELL46:OUT.18.TMIN | HSADC.DATA_ADC3_13 |
| TCELL46:OUT.21.TMIN | HSADC.TEST_SO232 |
| TCELL46:OUT.22.TMIN | HSADC.DATA_ADC3_14 |
| TCELL46:OUT.26.TMIN | HSADC.DATA_ADC3_15 |
| TCELL46:OUT.27.TMIN | HSADC.TEST_SO233 |
| TCELL46:OUT.28.TMIN | HSADC.STATUS_ADC2_13 |
| TCELL46:OUT.30.TMIN | HSADC.DATA_ADC3_16 |
| TCELL46:OUT.31.TMIN | HSADC.TEST_SO234 |
| TCELL46:IMUX.IMUX.7.DELAY | HSADC.TEST_SI232 |
| TCELL46:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC2_12 |
| TCELL46:IMUX.IMUX.17.DELAY | HSADC.TEST_SI230 |
| TCELL46:IMUX.IMUX.22.DELAY | HSADC.TEST_SI231 |
| TCELL46:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC2_11 |
| TCELL46:IMUX.IMUX.38.DELAY | HSADC.TEST_SI233 |
| TCELL46:IMUX.IMUX.47.DELAY | HSADC.TEST_SI234 |
| TCELL47:OUT.2.TMIN | HSADC.DATA_ADC3_17 |
| TCELL47:OUT.3.TMIN | HSADC.TEST_SO235 |
| TCELL47:OUT.6.TMIN | HSADC.DATA_ADC3_18 |
| TCELL47:OUT.8.TMIN | HSADC.STATUS_ADC2_14 |
| TCELL47:OUT.10.TMIN | HSADC.DATA_ADC3_19 |
| TCELL47:OUT.11.TMIN | HSADC.TEST_SO236 |
| TCELL47:OUT.13.TMIN | HSADC.DATA_ADC3_20 |
| TCELL47:OUT.16.TMIN | HSADC.DATA_ADC3_21 |
| TCELL47:OUT.19.TMIN | HSADC.DATA_ADC3_22 |
| TCELL47:OUT.21.TMIN | HSADC.TEST_SO237 |
| TCELL47:OUT.22.TMIN | HSADC.DATA_ADC3_23 |
| TCELL47:OUT.24.TMIN | HSADC.STATUS_ADC2_15 |
| TCELL47:OUT.26.TMIN | HSADC.DATA_ADC3_24 |
| TCELL47:OUT.27.TMIN | HSADC.TEST_SO238 |
| TCELL47:OUT.30.TMIN | HSADC.DATA_ADC3_25 |
| TCELL47:OUT.31.TMIN | HSADC.TEST_SO239 |
| TCELL47:IMUX.IMUX.7.DELAY | HSADC.TEST_SI237 |
| TCELL47:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC2_13 |
| TCELL47:IMUX.IMUX.10.DELAY | ABUS_SWITCH_GT0.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT1.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT2.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT3.TEST_ANALOGBUS_SEL_B |
| TCELL47:IMUX.IMUX.11.DELAY | ABUS_SWITCH_GT4.TEST_ANALOGBUS_SEL_B |
| TCELL47:IMUX.IMUX.17.DELAY | HSADC.TEST_SI235 |
| TCELL47:IMUX.IMUX.22.DELAY | HSADC.TEST_SI236 |
| TCELL47:IMUX.IMUX.38.DELAY | HSADC.TEST_SI238 |
| TCELL47:IMUX.IMUX.47.DELAY | HSADC.TEST_SI239 |
| TCELL48:OUT.2.TMIN | HSADC.DATA_ADC3_26 |
| TCELL48:OUT.3.TMIN | HSADC.TEST_SO240 |
| TCELL48:OUT.6.TMIN | HSADC.DATA_ADC3_27 |
| TCELL48:OUT.10.TMIN | HSADC.DATA_ADC3_28 |
| TCELL48:OUT.11.TMIN | HSADC.TEST_SO241 |
| TCELL48:OUT.14.TMIN | HSADC.DATA_ADC3_29 |
| TCELL48:OUT.18.TMIN | HSADC.DATA_ADC3_30 |
| TCELL48:OUT.21.TMIN | HSADC.TEST_SO242 |
| TCELL48:OUT.22.TMIN | HSADC.DATA_ADC3_31 |
| TCELL48:OUT.26.TMIN | HSADC.DATA_ADC3_32 |
| TCELL48:OUT.27.TMIN | HSADC.TEST_SO243 |
| TCELL48:OUT.30.TMIN | HSADC.DATA_ADC3_33 |
| TCELL48:OUT.31.TMIN | HSADC.TEST_SO244 |
| TCELL48:IMUX.IMUX.7.DELAY | HSADC.TEST_SI242 |
| TCELL48:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC2_15 |
| TCELL48:IMUX.IMUX.17.DELAY | HSADC.TEST_SI240 |
| TCELL48:IMUX.IMUX.22.DELAY | HSADC.TEST_SI241 |
| TCELL48:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC2_14 |
| TCELL48:IMUX.IMUX.38.DELAY | HSADC.TEST_SI243 |
| TCELL48:IMUX.IMUX.47.DELAY | HSADC.TEST_SI244 |
| TCELL49:OUT.2.TMIN | HSADC.DATA_ADC3_34 |
| TCELL49:OUT.3.TMIN | HSADC.TEST_SO245 |
| TCELL49:OUT.6.TMIN | HSADC.DATA_ADC3_35 |
| TCELL49:OUT.10.TMIN | HSADC.DATA_ADC3_36 |
| TCELL49:OUT.11.TMIN | HSADC.TEST_SO246 |
| TCELL49:OUT.13.TMIN | HSADC.DATA_ADC3_37 |
| TCELL49:OUT.16.TMIN | HSADC.DATA_ADC3_38 |
| TCELL49:OUT.19.TMIN | HSADC.DATA_ADC3_39 |
| TCELL49:OUT.21.TMIN | HSADC.TEST_SO247 |
| TCELL49:OUT.22.TMIN | HSADC.DATA_ADC3_40 |
| TCELL49:OUT.26.TMIN | HSADC.DATA_ADC3_41 |
| TCELL49:OUT.27.TMIN | HSADC.TEST_SO248 |
| TCELL49:OUT.30.TMIN | HSADC.DATA_ADC3_42 |
| TCELL49:OUT.31.TMIN | HSADC.TEST_SO249 |
| TCELL49:IMUX.IMUX.7.DELAY | HSADC.TEST_SI247 |
| TCELL49:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC3_1 |
| TCELL49:IMUX.IMUX.17.DELAY | HSADC.TEST_SI245 |
| TCELL49:IMUX.IMUX.22.DELAY | HSADC.TEST_SI246 |
| TCELL49:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC3_0 |
| TCELL49:IMUX.IMUX.38.DELAY | HSADC.TEST_SI248 |
| TCELL49:IMUX.IMUX.47.DELAY | HSADC.TEST_SI249 |
| TCELL50:OUT.2.TMIN | HSADC.DATA_ADC3_43 |
| TCELL50:OUT.3.TMIN | HSADC.TEST_SO250 |
| TCELL50:OUT.6.TMIN | HSADC.DATA_ADC3_44 |
| TCELL50:OUT.10.TMIN | HSADC.DATA_ADC3_45 |
| TCELL50:OUT.11.TMIN | HSADC.TEST_SO251 |
| TCELL50:OUT.14.TMIN | HSADC.DATA_ADC3_46 |
| TCELL50:OUT.18.TMIN | HSADC.DATA_ADC3_47 |
| TCELL50:OUT.21.TMIN | HSADC.TEST_SO252 |
| TCELL50:OUT.22.TMIN | HSADC.DATA_ADC3_48 |
| TCELL50:OUT.26.TMIN | HSADC.DATA_ADC3_49 |
| TCELL50:OUT.27.TMIN | HSADC.TEST_SO253 |
| TCELL50:OUT.30.TMIN | HSADC.DATA_ADC3_50 |
| TCELL50:OUT.31.TMIN | HSADC.TEST_SO254 |
| TCELL50:IMUX.IMUX.7.DELAY | HSADC.TEST_SI252 |
| TCELL50:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC3_2 |
| TCELL50:IMUX.IMUX.17.DELAY | HSADC.TEST_SI250 |
| TCELL50:IMUX.IMUX.22.DELAY | HSADC.TEST_SI251 |
| TCELL50:IMUX.IMUX.38.DELAY | HSADC.TEST_SI253 |
| TCELL50:IMUX.IMUX.47.DELAY | HSADC.TEST_SI254 |
| TCELL51:OUT.2.TMIN | HSADC.DATA_ADC3_51 |
| TCELL51:OUT.3.TMIN | HSADC.TEST_SO255 |
| TCELL51:OUT.4.TMIN | HSADC.STATUS_ADC3_0 |
| TCELL51:OUT.6.TMIN | HSADC.DATA_ADC3_52 |
| TCELL51:OUT.10.TMIN | HSADC.DATA_ADC3_53 |
| TCELL51:OUT.11.TMIN | HSADC.TEST_SO256 |
| TCELL51:OUT.13.TMIN | HSADC.DATA_ADC3_54 |
| TCELL51:OUT.16.TMIN | HSADC.DATA_ADC3_55 |
| TCELL51:OUT.19.TMIN | HSADC.DATA_ADC3_56 |
| TCELL51:OUT.21.TMIN | HSADC.TEST_SO257 |
| TCELL51:OUT.22.TMIN | HSADC.DATA_ADC3_57 |
| TCELL51:OUT.26.TMIN | HSADC.DATA_ADC3_58 |
| TCELL51:OUT.27.TMIN | HSADC.TEST_SO258 |
| TCELL51:OUT.28.TMIN | HSADC.STATUS_ADC3_1 |
| TCELL51:OUT.30.TMIN | HSADC.DATA_ADC3_59 |
| TCELL51:OUT.31.TMIN | HSADC.TEST_SO259 |
| TCELL51:IMUX.IMUX.7.DELAY | HSADC.TEST_SI257 |
| TCELL51:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC3_4 |
| TCELL51:IMUX.IMUX.17.DELAY | HSADC.TEST_SI255 |
| TCELL51:IMUX.IMUX.22.DELAY | HSADC.TEST_SI256 |
| TCELL51:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC3_3 |
| TCELL51:IMUX.IMUX.38.DELAY | HSADC.TEST_SI258 |
| TCELL51:IMUX.IMUX.47.DELAY | HSADC.TEST_SI259 |
| TCELL52:OUT.2.TMIN | HSADC.DATA_ADC3_60 |
| TCELL52:OUT.3.TMIN | HSADC.TEST_SO260 |
| TCELL52:OUT.6.TMIN | HSADC.DATA_ADC3_61 |
| TCELL52:OUT.8.TMIN | HSADC.STATUS_ADC3_2 |
| TCELL52:OUT.10.TMIN | HSADC.DATA_ADC3_62 |
| TCELL52:OUT.11.TMIN | HSADC.TEST_SO261 |
| TCELL52:OUT.14.TMIN | HSADC.DATA_ADC3_63 |
| TCELL52:OUT.18.TMIN | HSADC.DATA_ADC3_64 |
| TCELL52:OUT.21.TMIN | HSADC.TEST_SO262 |
| TCELL52:OUT.22.TMIN | HSADC.DATA_ADC3_65 |
| TCELL52:OUT.24.TMIN | HSADC.STATUS_ADC3_3 |
| TCELL52:OUT.26.TMIN | HSADC.DATA_ADC3_66 |
| TCELL52:OUT.27.TMIN | HSADC.TEST_SO263 |
| TCELL52:OUT.30.TMIN | HSADC.DATA_ADC3_67 |
| TCELL52:OUT.31.TMIN | HSADC.TEST_SO264 |
| TCELL52:IMUX.IMUX.7.DELAY | HSADC.TEST_SI262 |
| TCELL52:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC3_5 |
| TCELL52:IMUX.IMUX.17.DELAY | HSADC.TEST_SI260 |
| TCELL52:IMUX.IMUX.22.DELAY | HSADC.TEST_SI261 |
| TCELL52:IMUX.IMUX.38.DELAY | HSADC.TEST_SI263 |
| TCELL52:IMUX.IMUX.47.DELAY | HSADC.TEST_SI264 |
| TCELL53:OUT.2.TMIN | HSADC.DATA_ADC3_68 |
| TCELL53:OUT.3.TMIN | HSADC.TEST_SO265 |
| TCELL53:OUT.4.TMIN | HSADC.STATUS_ADC3_4 |
| TCELL53:OUT.6.TMIN | HSADC.DATA_ADC3_69 |
| TCELL53:OUT.10.TMIN | HSADC.DATA_ADC3_70 |
| TCELL53:OUT.11.TMIN | HSADC.TEST_SO266 |
| TCELL53:OUT.13.TMIN | HSADC.DATA_ADC3_71 |
| TCELL53:OUT.16.TMIN | HSADC.DATA_ADC3_72 |
| TCELL53:OUT.19.TMIN | HSADC.DATA_ADC3_73 |
| TCELL53:OUT.21.TMIN | HSADC.TEST_SO267 |
| TCELL53:OUT.22.TMIN | HSADC.DATA_ADC3_74 |
| TCELL53:OUT.26.TMIN | HSADC.DATA_ADC3_75 |
| TCELL53:OUT.27.TMIN | HSADC.TEST_SO268 |
| TCELL53:OUT.28.TMIN | HSADC.STATUS_ADC3_5 |
| TCELL53:OUT.30.TMIN | HSADC.DATA_ADC3_76 |
| TCELL53:OUT.31.TMIN | HSADC.TEST_SO269 |
| TCELL53:IMUX.IMUX.7.DELAY | HSADC.TEST_SI267 |
| TCELL53:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC3_7 |
| TCELL53:IMUX.IMUX.17.DELAY | HSADC.TEST_SI265 |
| TCELL53:IMUX.IMUX.22.DELAY | HSADC.TEST_SI266 |
| TCELL53:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC3_6 |
| TCELL53:IMUX.IMUX.38.DELAY | HSADC.TEST_SI268 |
| TCELL53:IMUX.IMUX.47.DELAY | HSADC.TEST_SI269 |
| TCELL54:OUT.2.TMIN | HSADC.DATA_ADC3_77 |
| TCELL54:OUT.3.TMIN | HSADC.TEST_SO270 |
| TCELL54:OUT.6.TMIN | HSADC.DATA_ADC3_78 |
| TCELL54:OUT.8.TMIN | HSADC.STATUS_ADC3_6 |
| TCELL54:OUT.10.TMIN | HSADC.DATA_ADC3_79 |
| TCELL54:OUT.11.TMIN | HSADC.TEST_SO271 |
| TCELL54:OUT.14.TMIN | HSADC.DATA_ADC3_80 |
| TCELL54:OUT.18.TMIN | HSADC.DATA_ADC3_81 |
| TCELL54:OUT.21.TMIN | HSADC.TEST_SO272 |
| TCELL54:OUT.22.TMIN | HSADC.DATA_ADC3_82 |
| TCELL54:OUT.24.TMIN | HSADC.STATUS_ADC3_7 |
| TCELL54:OUT.26.TMIN | HSADC.DATA_ADC3_83 |
| TCELL54:OUT.27.TMIN | HSADC.TEST_SO273 |
| TCELL54:OUT.30.TMIN | HSADC.DATA_ADC3_84 |
| TCELL54:OUT.31.TMIN | HSADC.TEST_SO274 |
| TCELL54:IMUX.CTRL.5 | HSADC.TEST_SCAN_CLK4 |
| TCELL54:IMUX.IMUX.7.DELAY | HSADC.TEST_SI272 |
| TCELL54:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC3_8 |
| TCELL54:IMUX.IMUX.17.DELAY | HSADC.TEST_SI270 |
| TCELL54:IMUX.IMUX.22.DELAY | HSADC.TEST_SI271 |
| TCELL54:IMUX.IMUX.38.DELAY | HSADC.TEST_SI273 |
| TCELL54:IMUX.IMUX.47.DELAY | HSADC.TEST_SI274 |
| TCELL55:OUT.2.TMIN | HSADC.DATA_ADC3_85 |
| TCELL55:OUT.3.TMIN | HSADC.TEST_SO275 |
| TCELL55:OUT.4.TMIN | HSADC.STATUS_ADC3_8 |
| TCELL55:OUT.6.TMIN | HSADC.DATA_ADC3_86 |
| TCELL55:OUT.10.TMIN | HSADC.DATA_ADC3_87 |
| TCELL55:OUT.11.TMIN | HSADC.TEST_SO276 |
| TCELL55:OUT.13.TMIN | HSADC.DATA_ADC3_88 |
| TCELL55:OUT.16.TMIN | HSADC.DATA_ADC3_89 |
| TCELL55:OUT.19.TMIN | HSADC.DATA_ADC3_90 |
| TCELL55:OUT.21.TMIN | HSADC.TEST_SO277 |
| TCELL55:OUT.22.TMIN | HSADC.DATA_ADC3_91 |
| TCELL55:OUT.26.TMIN | HSADC.DATA_ADC3_92 |
| TCELL55:OUT.27.TMIN | HSADC.TEST_SO278 |
| TCELL55:OUT.28.TMIN | HSADC.STATUS_ADC3_9 |
| TCELL55:OUT.30.TMIN | HSADC.DATA_ADC3_93 |
| TCELL55:OUT.31.TMIN | HSADC.TEST_SO279 |
| TCELL55:IMUX.IMUX.7.DELAY | HSADC.TEST_SI277 |
| TCELL55:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC3_10 |
| TCELL55:IMUX.IMUX.17.DELAY | HSADC.TEST_SI275 |
| TCELL55:IMUX.IMUX.22.DELAY | HSADC.TEST_SI276 |
| TCELL55:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC3_9 |
| TCELL55:IMUX.IMUX.38.DELAY | HSADC.TEST_SI278 |
| TCELL55:IMUX.IMUX.47.DELAY | HSADC.TEST_SI279 |
| TCELL56:OUT.2.TMIN | HSADC.DATA_ADC3_94 |
| TCELL56:OUT.3.TMIN | HSADC.TEST_SO280 |
| TCELL56:OUT.6.TMIN | HSADC.DATA_ADC3_95 |
| TCELL56:OUT.8.TMIN | HSADC.STATUS_ADC3_10 |
| TCELL56:OUT.10.TMIN | HSADC.DATA_ADC3_96 |
| TCELL56:OUT.11.TMIN | HSADC.TEST_SO281 |
| TCELL56:OUT.14.TMIN | HSADC.DATA_ADC3_97 |
| TCELL56:OUT.18.TMIN | HSADC.DATA_ADC3_98 |
| TCELL56:OUT.21.TMIN | HSADC.TEST_SO282 |
| TCELL56:OUT.22.TMIN | HSADC.DATA_ADC3_99 |
| TCELL56:OUT.24.TMIN | HSADC.STATUS_ADC3_11 |
| TCELL56:OUT.26.TMIN | HSADC.DATA_ADC3_100 |
| TCELL56:OUT.27.TMIN | HSADC.TEST_SO283 |
| TCELL56:OUT.30.TMIN | HSADC.DATA_ADC3_101 |
| TCELL56:OUT.31.TMIN | HSADC.TEST_SO284 |
| TCELL56:IMUX.IMUX.7.DELAY | HSADC.TEST_SI282 |
| TCELL56:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC3_11 |
| TCELL56:IMUX.IMUX.17.DELAY | HSADC.TEST_SI280 |
| TCELL56:IMUX.IMUX.22.DELAY | HSADC.TEST_SI281 |
| TCELL56:IMUX.IMUX.38.DELAY | HSADC.TEST_SI283 |
| TCELL56:IMUX.IMUX.47.DELAY | HSADC.TEST_SI284 |
| TCELL57:OUT.2.TMIN | HSADC.DATA_ADC3_102 |
| TCELL57:OUT.3.TMIN | HSADC.TEST_SO285 |
| TCELL57:OUT.4.TMIN | HSADC.STATUS_ADC3_12 |
| TCELL57:OUT.6.TMIN | HSADC.DATA_ADC3_103 |
| TCELL57:OUT.10.TMIN | HSADC.DATA_ADC3_104 |
| TCELL57:OUT.11.TMIN | HSADC.TEST_SO286 |
| TCELL57:OUT.13.TMIN | HSADC.DATA_ADC3_105 |
| TCELL57:OUT.16.TMIN | HSADC.DATA_ADC3_106 |
| TCELL57:OUT.19.TMIN | HSADC.DATA_ADC3_107 |
| TCELL57:OUT.21.TMIN | HSADC.TEST_SO287 |
| TCELL57:OUT.22.TMIN | HSADC.DATA_ADC3_108 |
| TCELL57:OUT.26.TMIN | HSADC.DATA_ADC3_109 |
| TCELL57:OUT.27.TMIN | HSADC.TEST_SO288 |
| TCELL57:OUT.28.TMIN | HSADC.STATUS_ADC3_13 |
| TCELL57:OUT.30.TMIN | HSADC.DATA_ADC3_110 |
| TCELL57:OUT.31.TMIN | HSADC.TEST_SO289 |
| TCELL57:IMUX.IMUX.7.DELAY | HSADC.TEST_SI287 |
| TCELL57:IMUX.IMUX.12.DELAY | HSADC.CONTROL_ADC3_13 |
| TCELL57:IMUX.IMUX.17.DELAY | HSADC.TEST_SI285 |
| TCELL57:IMUX.IMUX.22.DELAY | HSADC.TEST_SI286 |
| TCELL57:IMUX.IMUX.23.DELAY | HSADC.CONTROL_ADC3_12 |
| TCELL57:IMUX.IMUX.38.DELAY | HSADC.TEST_SI288 |
| TCELL57:IMUX.IMUX.47.DELAY | HSADC.TEST_SI289 |
| TCELL58:OUT.2.TMIN | HSADC.DATA_ADC3_111 |
| TCELL58:OUT.3.TMIN | HSADC.TEST_SO290 |
| TCELL58:OUT.6.TMIN | HSADC.DATA_ADC3_112 |
| TCELL58:OUT.8.TMIN | HSADC.STATUS_ADC3_14 |
| TCELL58:OUT.10.TMIN | HSADC.DATA_ADC3_113 |
| TCELL58:OUT.11.TMIN | HSADC.TEST_SO291 |
| TCELL58:OUT.14.TMIN | HSADC.DATA_ADC3_114 |
| TCELL58:OUT.18.TMIN | HSADC.DATA_ADC3_115 |
| TCELL58:OUT.21.TMIN | HSADC.TEST_SO292 |
| TCELL58:OUT.22.TMIN | HSADC.DATA_ADC3_116 |
| TCELL58:OUT.24.TMIN | HSADC.STATUS_ADC3_15 |
| TCELL58:OUT.26.TMIN | HSADC.DATA_ADC3_117 |
| TCELL58:OUT.27.TMIN | HSADC.TEST_SO293 |
| TCELL58:OUT.30.TMIN | HSADC.DATA_ADC3_118 |
| TCELL58:OUT.31.TMIN | HSADC.TEST_SO294 |
| TCELL58:IMUX.IMUX.7.DELAY | HSADC.TEST_SI292 |
| TCELL58:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC3_14 |
| TCELL58:IMUX.IMUX.17.DELAY | HSADC.TEST_SI290 |
| TCELL58:IMUX.IMUX.22.DELAY | HSADC.TEST_SI291 |
| TCELL58:IMUX.IMUX.38.DELAY | HSADC.TEST_SI293 |
| TCELL58:IMUX.IMUX.47.DELAY | HSADC.TEST_SI294 |
| TCELL59:OUT.2.TMIN | HSADC.DATA_ADC3_119 |
| TCELL59:OUT.3.TMIN | HSADC.TEST_SO295 |
| TCELL59:OUT.6.TMIN | HSADC.DATA_ADC3_120 |
| TCELL59:OUT.10.TMIN | HSADC.DATA_ADC3_121 |
| TCELL59:OUT.11.TMIN | HSADC.TEST_SO296 |
| TCELL59:OUT.13.TMIN | HSADC.DATA_ADC3_122 |
| TCELL59:OUT.16.TMIN | HSADC.DATA_ADC3_123 |
| TCELL59:OUT.19.TMIN | HSADC.DATA_ADC3_124 |
| TCELL59:OUT.21.TMIN | HSADC.TEST_SO297 |
| TCELL59:OUT.22.TMIN | HSADC.DATA_ADC3_125 |
| TCELL59:OUT.26.TMIN | HSADC.DATA_ADC3_126 |
| TCELL59:OUT.27.TMIN | HSADC.TEST_SO298 |
| TCELL59:OUT.30.TMIN | HSADC.DATA_ADC3_127 |
| TCELL59:OUT.31.TMIN | HSADC.TEST_SO299 |
| TCELL59:IMUX.IMUX.7.DELAY | HSADC.TEST_SI297 |
| TCELL59:IMUX.IMUX.8.DELAY | HSADC.CONTROL_ADC3_15 |
| TCELL59:IMUX.IMUX.17.DELAY | HSADC.TEST_SI295 |
| TCELL59:IMUX.IMUX.22.DELAY | HSADC.TEST_SI296 |
| TCELL59:IMUX.IMUX.38.DELAY | HSADC.TEST_SI298 |
| TCELL59:IMUX.IMUX.47.DELAY | HSADC.TEST_SI299 |
Tile RFADC
Cells: 60
Bel BUFG_GT0
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.5.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.19.DELAY |
Bel BUFG_GT1
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.6.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.21.DELAY |
Bel BUFG_GT2
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.29.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.5.DELAY |
Bel BUFG_GT3
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.9.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.6.DELAY |
Bel BUFG_GT4
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.10.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.29.DELAY |
Bel BUFG_GT5
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.11.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.9.DELAY |
Bel BUFG_GT6
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.13.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.10.DELAY |
Bel BUFG_GT7
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.42.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.11.DELAY |
Bel BUFG_GT8
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.44.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.13.DELAY |
Bel BUFG_GT9
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL14:IMUX.IMUX.46.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.42.DELAY |
Bel BUFG_GT10
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.1.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.44.DELAY |
Bel BUFG_GT11
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.19.DELAY |
| RSTMASK | input | TCELL16:IMUX.IMUX.46.DELAY |
Bel BUFG_GT12
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.21.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.1.DELAY |
Bel BUFG_GT13
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.5.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.19.DELAY |
Bel BUFG_GT14
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.6.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.21.DELAY |
Bel BUFG_GT15
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.29.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.5.DELAY |
Bel BUFG_GT16
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.9.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.6.DELAY |
Bel BUFG_GT17
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.10.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.29.DELAY |
Bel BUFG_GT18
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.11.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.9.DELAY |
Bel BUFG_GT19
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.13.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.10.DELAY |
Bel BUFG_GT20
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.42.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.11.DELAY |
Bel BUFG_GT21
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.44.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.13.DELAY |
Bel BUFG_GT22
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL15:IMUX.IMUX.46.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.42.DELAY |
Bel BUFG_GT23
| Pin | Direction | Wires |
|---|---|---|
| CEMASK | input | TCELL16:IMUX.IMUX.1.DELAY |
| RSTMASK | input | TCELL17:IMUX.IMUX.44.DELAY |
Bel BUFG_GT_SYNC0
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL12:IMUX.IMUX.1.DELAY |
| RST_IN | input | TCELL13:IMUX.IMUX.21.DELAY |
Bel BUFG_GT_SYNC1
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL12:IMUX.IMUX.19.DELAY |
| RST_IN | input | TCELL13:IMUX.IMUX.5.DELAY |
Bel BUFG_GT_SYNC2
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL12:IMUX.IMUX.21.DELAY |
| RST_IN | input | TCELL13:IMUX.IMUX.6.DELAY |
Bel BUFG_GT_SYNC3
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL12:IMUX.IMUX.5.DELAY |
| RST_IN | input | TCELL13:IMUX.IMUX.29.DELAY |
Bel BUFG_GT_SYNC4
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC5
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC6
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC7
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC8
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC9
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC10
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC11
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC12
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC13
| Pin | Direction | Wires |
|---|
Bel BUFG_GT_SYNC14
| Pin | Direction | Wires |
|---|---|---|
| CE_IN | input | TCELL13:IMUX.IMUX.19.DELAY |
| CLK_IN | input | TCELL30:RCLK.IMUX.17 |
| RST_IN | input | TCELL14:IMUX.IMUX.21.DELAY |
Bel ABUS_SWITCH_GT0
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.10.DELAY |
Bel ABUS_SWITCH_GT1
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.10.DELAY |
Bel ABUS_SWITCH_GT2
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.10.DELAY |
Bel ABUS_SWITCH_GT3
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.10.DELAY |
Bel ABUS_SWITCH_GT4
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL47:IMUX.IMUX.11.DELAY |
Bel RFADC
| Pin | Direction | Wires |
|---|---|---|
| CLK_FIFO_LM | input | TCELL33:IMUX.CTRL.5 |
| CONTROL_ADC0_0 | input | TCELL0:IMUX.IMUX.23.DELAY |
| CONTROL_ADC0_1 | input | TCELL0:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_10 | input | TCELL6:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_11 | input | TCELL7:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_12 | input | TCELL8:IMUX.IMUX.23.DELAY |
| CONTROL_ADC0_13 | input | TCELL8:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_14 | input | TCELL9:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_15 | input | TCELL10:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_2 | input | TCELL1:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_3 | input | TCELL2:IMUX.IMUX.23.DELAY |
| CONTROL_ADC0_4 | input | TCELL2:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_5 | input | TCELL3:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_6 | input | TCELL4:IMUX.IMUX.23.DELAY |
| CONTROL_ADC0_7 | input | TCELL4:IMUX.IMUX.12.DELAY |
| CONTROL_ADC0_8 | input | TCELL5:IMUX.IMUX.8.DELAY |
| CONTROL_ADC0_9 | input | TCELL6:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_0 | input | TCELL11:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_1 | input | TCELL11:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_10 | input | TCELL17:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_11 | input | TCELL18:IMUX.IMUX.8.DELAY |
| CONTROL_ADC1_12 | input | TCELL19:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_13 | input | TCELL19:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_14 | input | TCELL20:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_15 | input | TCELL20:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_2 | input | TCELL12:IMUX.IMUX.8.DELAY |
| CONTROL_ADC1_3 | input | TCELL13:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_4 | input | TCELL13:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_5 | input | TCELL14:IMUX.IMUX.8.DELAY |
| CONTROL_ADC1_6 | input | TCELL15:IMUX.IMUX.23.DELAY |
| CONTROL_ADC1_7 | input | TCELL15:IMUX.IMUX.12.DELAY |
| CONTROL_ADC1_8 | input | TCELL16:IMUX.IMUX.8.DELAY |
| CONTROL_ADC1_9 | input | TCELL17:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_0 | input | TCELL39:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_1 | input | TCELL39:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_10 | input | TCELL45:IMUX.IMUX.8.DELAY |
| CONTROL_ADC2_11 | input | TCELL46:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_12 | input | TCELL46:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_13 | input | TCELL47:IMUX.IMUX.8.DELAY |
| CONTROL_ADC2_14 | input | TCELL48:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_15 | input | TCELL48:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_2 | input | TCELL40:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_3 | input | TCELL40:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_4 | input | TCELL41:IMUX.IMUX.8.DELAY |
| CONTROL_ADC2_5 | input | TCELL42:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_6 | input | TCELL42:IMUX.IMUX.12.DELAY |
| CONTROL_ADC2_7 | input | TCELL43:IMUX.IMUX.8.DELAY |
| CONTROL_ADC2_8 | input | TCELL44:IMUX.IMUX.23.DELAY |
| CONTROL_ADC2_9 | input | TCELL44:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_0 | input | TCELL49:IMUX.IMUX.23.DELAY |
| CONTROL_ADC3_1 | input | TCELL49:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_10 | input | TCELL55:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_11 | input | TCELL56:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_12 | input | TCELL57:IMUX.IMUX.23.DELAY |
| CONTROL_ADC3_13 | input | TCELL57:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_14 | input | TCELL58:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_15 | input | TCELL59:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_2 | input | TCELL50:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_3 | input | TCELL51:IMUX.IMUX.23.DELAY |
| CONTROL_ADC3_4 | input | TCELL51:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_5 | input | TCELL52:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_6 | input | TCELL53:IMUX.IMUX.23.DELAY |
| CONTROL_ADC3_7 | input | TCELL53:IMUX.IMUX.12.DELAY |
| CONTROL_ADC3_8 | input | TCELL54:IMUX.IMUX.8.DELAY |
| CONTROL_ADC3_9 | input | TCELL55:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON0 | input | TCELL21:IMUX.IMUX.8.DELAY |
| CONTROL_COMMON1 | input | TCELL22:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON10 | input | TCELL36:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON11 | input | TCELL36:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON12 | input | TCELL37:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON13 | input | TCELL37:IMUX.IMUX.8.DELAY |
| CONTROL_COMMON14 | input | TCELL37:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON15 | input | TCELL38:IMUX.IMUX.8.DELAY |
| CONTROL_COMMON2 | input | TCELL22:IMUX.IMUX.8.DELAY |
| CONTROL_COMMON3 | input | TCELL22:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON4 | input | TCELL23:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON5 | input | TCELL23:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON6 | input | TCELL24:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON7 | input | TCELL24:IMUX.IMUX.12.DELAY |
| CONTROL_COMMON8 | input | TCELL35:IMUX.IMUX.23.DELAY |
| CONTROL_COMMON9 | input | TCELL35:IMUX.IMUX.12.DELAY |
| DADDR0 | input | TCELL30:IMUX.IMUX.8.DELAY |
| DADDR1 | input | TCELL30:IMUX.IMUX.12.DELAY |
| DADDR10 | input | TCELL33:IMUX.IMUX.12.DELAY |
| DADDR11 | input | TCELL34:IMUX.IMUX.12.DELAY |
| DADDR2 | input | TCELL31:IMUX.IMUX.23.DELAY |
| DADDR3 | input | TCELL31:IMUX.IMUX.8.DELAY |
| DADDR4 | input | TCELL31:IMUX.IMUX.12.DELAY |
| DADDR5 | input | TCELL32:IMUX.IMUX.23.DELAY |
| DADDR6 | input | TCELL32:IMUX.IMUX.8.DELAY |
| DADDR7 | input | TCELL32:IMUX.IMUX.12.DELAY |
| DADDR8 | input | TCELL33:IMUX.IMUX.23.DELAY |
| DADDR9 | input | TCELL33:IMUX.IMUX.8.DELAY |
| DATA_ADC0_0 | output | TCELL0:OUT.1.TMIN |
| DATA_ADC0_1 | output | TCELL0:OUT.6.TMIN |
| DATA_ADC0_10 | output | TCELL1:OUT.1.TMIN |
| DATA_ADC0_100 | output | TCELL7:OUT.30.TMIN |
| DATA_ADC0_101 | output | TCELL8:OUT.1.TMIN |
| DATA_ADC0_102 | output | TCELL8:OUT.6.TMIN |
| DATA_ADC0_103 | output | TCELL8:OUT.8.TMIN |
| DATA_ADC0_104 | output | TCELL8:OUT.10.TMIN |
| DATA_ADC0_105 | output | TCELL8:OUT.12.TMIN |
| DATA_ADC0_106 | output | TCELL8:OUT.14.TMIN |
| DATA_ADC0_107 | output | TCELL8:OUT.16.TMIN |
| DATA_ADC0_108 | output | TCELL8:OUT.18.TMIN |
| DATA_ADC0_109 | output | TCELL8:OUT.20.TMIN |
| DATA_ADC0_11 | output | TCELL1:OUT.6.TMIN |
| DATA_ADC0_110 | output | TCELL8:OUT.22.TMIN |
| DATA_ADC0_111 | output | TCELL8:OUT.24.TMIN |
| DATA_ADC0_112 | output | TCELL8:OUT.26.TMIN |
| DATA_ADC0_113 | output | TCELL8:OUT.30.TMIN |
| DATA_ADC0_114 | output | TCELL9:OUT.1.TMIN |
| DATA_ADC0_115 | output | TCELL9:OUT.6.TMIN |
| DATA_ADC0_116 | output | TCELL9:OUT.8.TMIN |
| DATA_ADC0_117 | output | TCELL9:OUT.10.TMIN |
| DATA_ADC0_118 | output | TCELL9:OUT.12.TMIN |
| DATA_ADC0_119 | output | TCELL9:OUT.14.TMIN |
| DATA_ADC0_12 | output | TCELL1:OUT.8.TMIN |
| DATA_ADC0_120 | output | TCELL9:OUT.16.TMIN |
| DATA_ADC0_121 | output | TCELL9:OUT.18.TMIN |
| DATA_ADC0_122 | output | TCELL9:OUT.20.TMIN |
| DATA_ADC0_123 | output | TCELL9:OUT.22.TMIN |
| DATA_ADC0_124 | output | TCELL9:OUT.24.TMIN |
| DATA_ADC0_125 | output | TCELL9:OUT.26.TMIN |
| DATA_ADC0_126 | output | TCELL9:OUT.30.TMIN |
| DATA_ADC0_127 | output | TCELL10:OUT.1.TMIN |
| DATA_ADC0_128 | output | TCELL10:OUT.6.TMIN |
| DATA_ADC0_129 | output | TCELL10:OUT.8.TMIN |
| DATA_ADC0_13 | output | TCELL1:OUT.10.TMIN |
| DATA_ADC0_130 | output | TCELL10:OUT.10.TMIN |
| DATA_ADC0_131 | output | TCELL10:OUT.12.TMIN |
| DATA_ADC0_132 | output | TCELL10:OUT.14.TMIN |
| DATA_ADC0_133 | output | TCELL10:OUT.16.TMIN |
| DATA_ADC0_134 | output | TCELL10:OUT.18.TMIN |
| DATA_ADC0_135 | output | TCELL10:OUT.20.TMIN |
| DATA_ADC0_136 | output | TCELL10:OUT.22.TMIN |
| DATA_ADC0_137 | output | TCELL10:OUT.24.TMIN |
| DATA_ADC0_138 | output | TCELL10:OUT.26.TMIN |
| DATA_ADC0_139 | output | TCELL10:OUT.30.TMIN |
| DATA_ADC0_14 | output | TCELL1:OUT.12.TMIN |
| DATA_ADC0_140 | output | TCELL11:OUT.1.TMIN |
| DATA_ADC0_141 | output | TCELL11:OUT.6.TMIN |
| DATA_ADC0_142 | output | TCELL11:OUT.8.TMIN |
| DATA_ADC0_143 | output | TCELL11:OUT.10.TMIN |
| DATA_ADC0_144 | output | TCELL11:OUT.12.TMIN |
| DATA_ADC0_145 | output | TCELL11:OUT.14.TMIN |
| DATA_ADC0_146 | output | TCELL11:OUT.16.TMIN |
| DATA_ADC0_147 | output | TCELL11:OUT.18.TMIN |
| DATA_ADC0_148 | output | TCELL11:OUT.20.TMIN |
| DATA_ADC0_149 | output | TCELL11:OUT.22.TMIN |
| DATA_ADC0_15 | output | TCELL1:OUT.14.TMIN |
| DATA_ADC0_150 | output | TCELL11:OUT.24.TMIN |
| DATA_ADC0_151 | output | TCELL11:OUT.26.TMIN |
| DATA_ADC0_152 | output | TCELL11:OUT.30.TMIN |
| DATA_ADC0_153 | output | TCELL12:OUT.1.TMIN |
| DATA_ADC0_154 | output | TCELL12:OUT.6.TMIN |
| DATA_ADC0_155 | output | TCELL12:OUT.8.TMIN |
| DATA_ADC0_156 | output | TCELL12:OUT.10.TMIN |
| DATA_ADC0_157 | output | TCELL12:OUT.12.TMIN |
| DATA_ADC0_158 | output | TCELL12:OUT.14.TMIN |
| DATA_ADC0_159 | output | TCELL12:OUT.16.TMIN |
| DATA_ADC0_16 | output | TCELL1:OUT.16.TMIN |
| DATA_ADC0_160 | output | TCELL12:OUT.18.TMIN |
| DATA_ADC0_161 | output | TCELL12:OUT.20.TMIN |
| DATA_ADC0_162 | output | TCELL12:OUT.22.TMIN |
| DATA_ADC0_163 | output | TCELL12:OUT.24.TMIN |
| DATA_ADC0_164 | output | TCELL12:OUT.26.TMIN |
| DATA_ADC0_165 | output | TCELL12:OUT.30.TMIN |
| DATA_ADC0_166 | output | TCELL13:OUT.1.TMIN |
| DATA_ADC0_167 | output | TCELL13:OUT.6.TMIN |
| DATA_ADC0_168 | output | TCELL13:OUT.8.TMIN |
| DATA_ADC0_169 | output | TCELL13:OUT.10.TMIN |
| DATA_ADC0_17 | output | TCELL1:OUT.18.TMIN |
| DATA_ADC0_170 | output | TCELL13:OUT.12.TMIN |
| DATA_ADC0_171 | output | TCELL13:OUT.14.TMIN |
| DATA_ADC0_172 | output | TCELL13:OUT.16.TMIN |
| DATA_ADC0_173 | output | TCELL13:OUT.18.TMIN |
| DATA_ADC0_174 | output | TCELL13:OUT.20.TMIN |
| DATA_ADC0_175 | output | TCELL13:OUT.22.TMIN |
| DATA_ADC0_176 | output | TCELL13:OUT.24.TMIN |
| DATA_ADC0_177 | output | TCELL13:OUT.26.TMIN |
| DATA_ADC0_178 | output | TCELL13:OUT.30.TMIN |
| DATA_ADC0_179 | output | TCELL14:OUT.1.TMIN |
| DATA_ADC0_18 | output | TCELL1:OUT.20.TMIN |
| DATA_ADC0_180 | output | TCELL14:OUT.6.TMIN |
| DATA_ADC0_181 | output | TCELL14:OUT.8.TMIN |
| DATA_ADC0_182 | output | TCELL14:OUT.10.TMIN |
| DATA_ADC0_183 | output | TCELL14:OUT.12.TMIN |
| DATA_ADC0_184 | output | TCELL14:OUT.14.TMIN |
| DATA_ADC0_185 | output | TCELL14:OUT.16.TMIN |
| DATA_ADC0_186 | output | TCELL14:OUT.18.TMIN |
| DATA_ADC0_187 | output | TCELL14:OUT.20.TMIN |
| DATA_ADC0_188 | output | TCELL14:OUT.22.TMIN |
| DATA_ADC0_189 | output | TCELL14:OUT.24.TMIN |
| DATA_ADC0_19 | output | TCELL1:OUT.22.TMIN |
| DATA_ADC0_190 | output | TCELL14:OUT.26.TMIN |
| DATA_ADC0_191 | output | TCELL14:OUT.30.TMIN |
| DATA_ADC0_2 | output | TCELL0:OUT.8.TMIN |
| DATA_ADC0_20 | output | TCELL1:OUT.24.TMIN |
| DATA_ADC0_21 | output | TCELL1:OUT.26.TMIN |
| DATA_ADC0_22 | output | TCELL1:OUT.30.TMIN |
| DATA_ADC0_23 | output | TCELL2:OUT.1.TMIN |
| DATA_ADC0_24 | output | TCELL2:OUT.6.TMIN |
| DATA_ADC0_25 | output | TCELL2:OUT.8.TMIN |
| DATA_ADC0_26 | output | TCELL2:OUT.10.TMIN |
| DATA_ADC0_27 | output | TCELL2:OUT.12.TMIN |
| DATA_ADC0_28 | output | TCELL2:OUT.14.TMIN |
| DATA_ADC0_29 | output | TCELL2:OUT.16.TMIN |
| DATA_ADC0_3 | output | TCELL0:OUT.12.TMIN |
| DATA_ADC0_30 | output | TCELL2:OUT.18.TMIN |
| DATA_ADC0_31 | output | TCELL2:OUT.20.TMIN |
| DATA_ADC0_32 | output | TCELL2:OUT.22.TMIN |
| DATA_ADC0_33 | output | TCELL2:OUT.24.TMIN |
| DATA_ADC0_34 | output | TCELL2:OUT.26.TMIN |
| DATA_ADC0_35 | output | TCELL2:OUT.30.TMIN |
| DATA_ADC0_36 | output | TCELL3:OUT.1.TMIN |
| DATA_ADC0_37 | output | TCELL3:OUT.6.TMIN |
| DATA_ADC0_38 | output | TCELL3:OUT.8.TMIN |
| DATA_ADC0_39 | output | TCELL3:OUT.10.TMIN |
| DATA_ADC0_4 | output | TCELL0:OUT.16.TMIN |
| DATA_ADC0_40 | output | TCELL3:OUT.12.TMIN |
| DATA_ADC0_41 | output | TCELL3:OUT.14.TMIN |
| DATA_ADC0_42 | output | TCELL3:OUT.16.TMIN |
| DATA_ADC0_43 | output | TCELL3:OUT.18.TMIN |
| DATA_ADC0_44 | output | TCELL3:OUT.20.TMIN |
| DATA_ADC0_45 | output | TCELL3:OUT.22.TMIN |
| DATA_ADC0_46 | output | TCELL3:OUT.24.TMIN |
| DATA_ADC0_47 | output | TCELL3:OUT.26.TMIN |
| DATA_ADC0_48 | output | TCELL3:OUT.30.TMIN |
| DATA_ADC0_49 | output | TCELL4:OUT.1.TMIN |
| DATA_ADC0_5 | output | TCELL0:OUT.20.TMIN |
| DATA_ADC0_50 | output | TCELL4:OUT.6.TMIN |
| DATA_ADC0_51 | output | TCELL4:OUT.8.TMIN |
| DATA_ADC0_52 | output | TCELL4:OUT.10.TMIN |
| DATA_ADC0_53 | output | TCELL4:OUT.12.TMIN |
| DATA_ADC0_54 | output | TCELL4:OUT.14.TMIN |
| DATA_ADC0_55 | output | TCELL4:OUT.16.TMIN |
| DATA_ADC0_56 | output | TCELL4:OUT.18.TMIN |
| DATA_ADC0_57 | output | TCELL4:OUT.20.TMIN |
| DATA_ADC0_58 | output | TCELL4:OUT.22.TMIN |
| DATA_ADC0_59 | output | TCELL4:OUT.24.TMIN |
| DATA_ADC0_6 | output | TCELL0:OUT.22.TMIN |
| DATA_ADC0_60 | output | TCELL4:OUT.26.TMIN |
| DATA_ADC0_61 | output | TCELL4:OUT.30.TMIN |
| DATA_ADC0_62 | output | TCELL5:OUT.1.TMIN |
| DATA_ADC0_63 | output | TCELL5:OUT.6.TMIN |
| DATA_ADC0_64 | output | TCELL5:OUT.8.TMIN |
| DATA_ADC0_65 | output | TCELL5:OUT.10.TMIN |
| DATA_ADC0_66 | output | TCELL5:OUT.12.TMIN |
| DATA_ADC0_67 | output | TCELL5:OUT.14.TMIN |
| DATA_ADC0_68 | output | TCELL5:OUT.16.TMIN |
| DATA_ADC0_69 | output | TCELL5:OUT.18.TMIN |
| DATA_ADC0_7 | output | TCELL0:OUT.24.TMIN |
| DATA_ADC0_70 | output | TCELL5:OUT.20.TMIN |
| DATA_ADC0_71 | output | TCELL5:OUT.22.TMIN |
| DATA_ADC0_72 | output | TCELL5:OUT.24.TMIN |
| DATA_ADC0_73 | output | TCELL5:OUT.26.TMIN |
| DATA_ADC0_74 | output | TCELL5:OUT.30.TMIN |
| DATA_ADC0_75 | output | TCELL6:OUT.1.TMIN |
| DATA_ADC0_76 | output | TCELL6:OUT.6.TMIN |
| DATA_ADC0_77 | output | TCELL6:OUT.8.TMIN |
| DATA_ADC0_78 | output | TCELL6:OUT.10.TMIN |
| DATA_ADC0_79 | output | TCELL6:OUT.12.TMIN |
| DATA_ADC0_8 | output | TCELL0:OUT.26.TMIN |
| DATA_ADC0_80 | output | TCELL6:OUT.14.TMIN |
| DATA_ADC0_81 | output | TCELL6:OUT.16.TMIN |
| DATA_ADC0_82 | output | TCELL6:OUT.18.TMIN |
| DATA_ADC0_83 | output | TCELL6:OUT.20.TMIN |
| DATA_ADC0_84 | output | TCELL6:OUT.22.TMIN |
| DATA_ADC0_85 | output | TCELL6:OUT.24.TMIN |
| DATA_ADC0_86 | output | TCELL6:OUT.26.TMIN |
| DATA_ADC0_87 | output | TCELL6:OUT.30.TMIN |
| DATA_ADC0_88 | output | TCELL7:OUT.1.TMIN |
| DATA_ADC0_89 | output | TCELL7:OUT.6.TMIN |
| DATA_ADC0_9 | output | TCELL0:OUT.30.TMIN |
| DATA_ADC0_90 | output | TCELL7:OUT.8.TMIN |
| DATA_ADC0_91 | output | TCELL7:OUT.10.TMIN |
| DATA_ADC0_92 | output | TCELL7:OUT.12.TMIN |
| DATA_ADC0_93 | output | TCELL7:OUT.14.TMIN |
| DATA_ADC0_94 | output | TCELL7:OUT.16.TMIN |
| DATA_ADC0_95 | output | TCELL7:OUT.18.TMIN |
| DATA_ADC0_96 | output | TCELL7:OUT.20.TMIN |
| DATA_ADC0_97 | output | TCELL7:OUT.22.TMIN |
| DATA_ADC0_98 | output | TCELL7:OUT.24.TMIN |
| DATA_ADC0_99 | output | TCELL7:OUT.26.TMIN |
| DATA_ADC1_0 | output | TCELL15:OUT.1.TMIN |
| DATA_ADC1_1 | output | TCELL15:OUT.6.TMIN |
| DATA_ADC1_10 | output | TCELL15:OUT.24.TMIN |
| DATA_ADC1_100 | output | TCELL22:OUT.22.TMIN |
| DATA_ADC1_101 | output | TCELL22:OUT.24.TMIN |
| DATA_ADC1_102 | output | TCELL22:OUT.26.TMIN |
| DATA_ADC1_103 | output | TCELL22:OUT.30.TMIN |
| DATA_ADC1_104 | output | TCELL23:OUT.1.TMIN |
| DATA_ADC1_105 | output | TCELL23:OUT.6.TMIN |
| DATA_ADC1_106 | output | TCELL23:OUT.8.TMIN |
| DATA_ADC1_107 | output | TCELL23:OUT.10.TMIN |
| DATA_ADC1_108 | output | TCELL23:OUT.12.TMIN |
| DATA_ADC1_109 | output | TCELL23:OUT.14.TMIN |
| DATA_ADC1_11 | output | TCELL15:OUT.26.TMIN |
| DATA_ADC1_110 | output | TCELL23:OUT.16.TMIN |
| DATA_ADC1_111 | output | TCELL23:OUT.18.TMIN |
| DATA_ADC1_112 | output | TCELL23:OUT.20.TMIN |
| DATA_ADC1_113 | output | TCELL23:OUT.22.TMIN |
| DATA_ADC1_114 | output | TCELL23:OUT.24.TMIN |
| DATA_ADC1_115 | output | TCELL23:OUT.26.TMIN |
| DATA_ADC1_116 | output | TCELL23:OUT.30.TMIN |
| DATA_ADC1_117 | output | TCELL24:OUT.1.TMIN |
| DATA_ADC1_118 | output | TCELL24:OUT.6.TMIN |
| DATA_ADC1_119 | output | TCELL24:OUT.8.TMIN |
| DATA_ADC1_12 | output | TCELL15:OUT.30.TMIN |
| DATA_ADC1_120 | output | TCELL24:OUT.10.TMIN |
| DATA_ADC1_121 | output | TCELL24:OUT.12.TMIN |
| DATA_ADC1_122 | output | TCELL24:OUT.14.TMIN |
| DATA_ADC1_123 | output | TCELL24:OUT.16.TMIN |
| DATA_ADC1_124 | output | TCELL24:OUT.18.TMIN |
| DATA_ADC1_125 | output | TCELL24:OUT.20.TMIN |
| DATA_ADC1_126 | output | TCELL24:OUT.22.TMIN |
| DATA_ADC1_127 | output | TCELL24:OUT.24.TMIN |
| DATA_ADC1_128 | output | TCELL24:OUT.26.TMIN |
| DATA_ADC1_129 | output | TCELL24:OUT.30.TMIN |
| DATA_ADC1_13 | output | TCELL16:OUT.1.TMIN |
| DATA_ADC1_130 | output | TCELL25:OUT.1.TMIN |
| DATA_ADC1_131 | output | TCELL25:OUT.6.TMIN |
| DATA_ADC1_132 | output | TCELL25:OUT.8.TMIN |
| DATA_ADC1_133 | output | TCELL25:OUT.10.TMIN |
| DATA_ADC1_134 | output | TCELL25:OUT.12.TMIN |
| DATA_ADC1_135 | output | TCELL25:OUT.14.TMIN |
| DATA_ADC1_136 | output | TCELL25:OUT.16.TMIN |
| DATA_ADC1_137 | output | TCELL25:OUT.18.TMIN |
| DATA_ADC1_138 | output | TCELL25:OUT.20.TMIN |
| DATA_ADC1_139 | output | TCELL25:OUT.22.TMIN |
| DATA_ADC1_14 | output | TCELL16:OUT.6.TMIN |
| DATA_ADC1_140 | output | TCELL25:OUT.24.TMIN |
| DATA_ADC1_141 | output | TCELL25:OUT.26.TMIN |
| DATA_ADC1_142 | output | TCELL25:OUT.30.TMIN |
| DATA_ADC1_143 | output | TCELL26:OUT.2.TMIN |
| DATA_ADC1_144 | output | TCELL26:OUT.6.TMIN |
| DATA_ADC1_145 | output | TCELL26:OUT.8.TMIN |
| DATA_ADC1_146 | output | TCELL26:OUT.10.TMIN |
| DATA_ADC1_147 | output | TCELL26:OUT.12.TMIN |
| DATA_ADC1_148 | output | TCELL26:OUT.14.TMIN |
| DATA_ADC1_149 | output | TCELL26:OUT.16.TMIN |
| DATA_ADC1_15 | output | TCELL16:OUT.8.TMIN |
| DATA_ADC1_150 | output | TCELL26:OUT.18.TMIN |
| DATA_ADC1_151 | output | TCELL26:OUT.20.TMIN |
| DATA_ADC1_152 | output | TCELL26:OUT.22.TMIN |
| DATA_ADC1_153 | output | TCELL26:OUT.24.TMIN |
| DATA_ADC1_154 | output | TCELL26:OUT.26.TMIN |
| DATA_ADC1_155 | output | TCELL26:OUT.30.TMIN |
| DATA_ADC1_156 | output | TCELL27:OUT.2.TMIN |
| DATA_ADC1_157 | output | TCELL27:OUT.6.TMIN |
| DATA_ADC1_158 | output | TCELL27:OUT.8.TMIN |
| DATA_ADC1_159 | output | TCELL27:OUT.10.TMIN |
| DATA_ADC1_16 | output | TCELL16:OUT.10.TMIN |
| DATA_ADC1_160 | output | TCELL27:OUT.12.TMIN |
| DATA_ADC1_161 | output | TCELL27:OUT.14.TMIN |
| DATA_ADC1_162 | output | TCELL27:OUT.16.TMIN |
| DATA_ADC1_163 | output | TCELL27:OUT.18.TMIN |
| DATA_ADC1_164 | output | TCELL27:OUT.20.TMIN |
| DATA_ADC1_165 | output | TCELL27:OUT.22.TMIN |
| DATA_ADC1_166 | output | TCELL27:OUT.24.TMIN |
| DATA_ADC1_167 | output | TCELL27:OUT.26.TMIN |
| DATA_ADC1_168 | output | TCELL27:OUT.30.TMIN |
| DATA_ADC1_169 | output | TCELL28:OUT.1.TMIN |
| DATA_ADC1_17 | output | TCELL16:OUT.12.TMIN |
| DATA_ADC1_170 | output | TCELL28:OUT.6.TMIN |
| DATA_ADC1_171 | output | TCELL28:OUT.8.TMIN |
| DATA_ADC1_172 | output | TCELL28:OUT.10.TMIN |
| DATA_ADC1_173 | output | TCELL28:OUT.12.TMIN |
| DATA_ADC1_174 | output | TCELL28:OUT.14.TMIN |
| DATA_ADC1_175 | output | TCELL28:OUT.16.TMIN |
| DATA_ADC1_176 | output | TCELL28:OUT.18.TMIN |
| DATA_ADC1_177 | output | TCELL28:OUT.20.TMIN |
| DATA_ADC1_178 | output | TCELL28:OUT.22.TMIN |
| DATA_ADC1_179 | output | TCELL28:OUT.24.TMIN |
| DATA_ADC1_18 | output | TCELL16:OUT.14.TMIN |
| DATA_ADC1_180 | output | TCELL28:OUT.26.TMIN |
| DATA_ADC1_181 | output | TCELL28:OUT.30.TMIN |
| DATA_ADC1_182 | output | TCELL29:OUT.2.TMIN |
| DATA_ADC1_183 | output | TCELL29:OUT.6.TMIN |
| DATA_ADC1_184 | output | TCELL29:OUT.8.TMIN |
| DATA_ADC1_185 | output | TCELL29:OUT.10.TMIN |
| DATA_ADC1_186 | output | TCELL29:OUT.12.TMIN |
| DATA_ADC1_187 | output | TCELL29:OUT.14.TMIN |
| DATA_ADC1_188 | output | TCELL29:OUT.16.TMIN |
| DATA_ADC1_189 | output | TCELL29:OUT.18.TMIN |
| DATA_ADC1_19 | output | TCELL16:OUT.16.TMIN |
| DATA_ADC1_190 | output | TCELL29:OUT.20.TMIN |
| DATA_ADC1_191 | output | TCELL29:OUT.22.TMIN |
| DATA_ADC1_2 | output | TCELL15:OUT.8.TMIN |
| DATA_ADC1_20 | output | TCELL16:OUT.18.TMIN |
| DATA_ADC1_21 | output | TCELL16:OUT.20.TMIN |
| DATA_ADC1_22 | output | TCELL16:OUT.22.TMIN |
| DATA_ADC1_23 | output | TCELL16:OUT.24.TMIN |
| DATA_ADC1_24 | output | TCELL16:OUT.26.TMIN |
| DATA_ADC1_25 | output | TCELL16:OUT.30.TMIN |
| DATA_ADC1_26 | output | TCELL17:OUT.1.TMIN |
| DATA_ADC1_27 | output | TCELL17:OUT.6.TMIN |
| DATA_ADC1_28 | output | TCELL17:OUT.8.TMIN |
| DATA_ADC1_29 | output | TCELL17:OUT.10.TMIN |
| DATA_ADC1_3 | output | TCELL15:OUT.10.TMIN |
| DATA_ADC1_30 | output | TCELL17:OUT.12.TMIN |
| DATA_ADC1_31 | output | TCELL17:OUT.14.TMIN |
| DATA_ADC1_32 | output | TCELL17:OUT.16.TMIN |
| DATA_ADC1_33 | output | TCELL17:OUT.18.TMIN |
| DATA_ADC1_34 | output | TCELL17:OUT.20.TMIN |
| DATA_ADC1_35 | output | TCELL17:OUT.22.TMIN |
| DATA_ADC1_36 | output | TCELL17:OUT.24.TMIN |
| DATA_ADC1_37 | output | TCELL17:OUT.26.TMIN |
| DATA_ADC1_38 | output | TCELL17:OUT.30.TMIN |
| DATA_ADC1_39 | output | TCELL18:OUT.1.TMIN |
| DATA_ADC1_4 | output | TCELL15:OUT.12.TMIN |
| DATA_ADC1_40 | output | TCELL18:OUT.6.TMIN |
| DATA_ADC1_41 | output | TCELL18:OUT.8.TMIN |
| DATA_ADC1_42 | output | TCELL18:OUT.10.TMIN |
| DATA_ADC1_43 | output | TCELL18:OUT.12.TMIN |
| DATA_ADC1_44 | output | TCELL18:OUT.14.TMIN |
| DATA_ADC1_45 | output | TCELL18:OUT.16.TMIN |
| DATA_ADC1_46 | output | TCELL18:OUT.18.TMIN |
| DATA_ADC1_47 | output | TCELL18:OUT.20.TMIN |
| DATA_ADC1_48 | output | TCELL18:OUT.22.TMIN |
| DATA_ADC1_49 | output | TCELL18:OUT.24.TMIN |
| DATA_ADC1_5 | output | TCELL15:OUT.14.TMIN |
| DATA_ADC1_50 | output | TCELL18:OUT.26.TMIN |
| DATA_ADC1_51 | output | TCELL18:OUT.30.TMIN |
| DATA_ADC1_52 | output | TCELL19:OUT.1.TMIN |
| DATA_ADC1_53 | output | TCELL19:OUT.6.TMIN |
| DATA_ADC1_54 | output | TCELL19:OUT.8.TMIN |
| DATA_ADC1_55 | output | TCELL19:OUT.10.TMIN |
| DATA_ADC1_56 | output | TCELL19:OUT.12.TMIN |
| DATA_ADC1_57 | output | TCELL19:OUT.14.TMIN |
| DATA_ADC1_58 | output | TCELL19:OUT.16.TMIN |
| DATA_ADC1_59 | output | TCELL19:OUT.18.TMIN |
| DATA_ADC1_6 | output | TCELL15:OUT.16.TMIN |
| DATA_ADC1_60 | output | TCELL19:OUT.20.TMIN |
| DATA_ADC1_61 | output | TCELL19:OUT.22.TMIN |
| DATA_ADC1_62 | output | TCELL19:OUT.24.TMIN |
| DATA_ADC1_63 | output | TCELL19:OUT.26.TMIN |
| DATA_ADC1_64 | output | TCELL19:OUT.30.TMIN |
| DATA_ADC1_65 | output | TCELL20:OUT.1.TMIN |
| DATA_ADC1_66 | output | TCELL20:OUT.6.TMIN |
| DATA_ADC1_67 | output | TCELL20:OUT.8.TMIN |
| DATA_ADC1_68 | output | TCELL20:OUT.10.TMIN |
| DATA_ADC1_69 | output | TCELL20:OUT.12.TMIN |
| DATA_ADC1_7 | output | TCELL15:OUT.18.TMIN |
| DATA_ADC1_70 | output | TCELL20:OUT.14.TMIN |
| DATA_ADC1_71 | output | TCELL20:OUT.16.TMIN |
| DATA_ADC1_72 | output | TCELL20:OUT.18.TMIN |
| DATA_ADC1_73 | output | TCELL20:OUT.20.TMIN |
| DATA_ADC1_74 | output | TCELL20:OUT.22.TMIN |
| DATA_ADC1_75 | output | TCELL20:OUT.24.TMIN |
| DATA_ADC1_76 | output | TCELL20:OUT.26.TMIN |
| DATA_ADC1_77 | output | TCELL20:OUT.30.TMIN |
| DATA_ADC1_78 | output | TCELL21:OUT.1.TMIN |
| DATA_ADC1_79 | output | TCELL21:OUT.6.TMIN |
| DATA_ADC1_8 | output | TCELL15:OUT.20.TMIN |
| DATA_ADC1_80 | output | TCELL21:OUT.8.TMIN |
| DATA_ADC1_81 | output | TCELL21:OUT.10.TMIN |
| DATA_ADC1_82 | output | TCELL21:OUT.12.TMIN |
| DATA_ADC1_83 | output | TCELL21:OUT.14.TMIN |
| DATA_ADC1_84 | output | TCELL21:OUT.16.TMIN |
| DATA_ADC1_85 | output | TCELL21:OUT.18.TMIN |
| DATA_ADC1_86 | output | TCELL21:OUT.20.TMIN |
| DATA_ADC1_87 | output | TCELL21:OUT.22.TMIN |
| DATA_ADC1_88 | output | TCELL21:OUT.24.TMIN |
| DATA_ADC1_89 | output | TCELL21:OUT.26.TMIN |
| DATA_ADC1_9 | output | TCELL15:OUT.22.TMIN |
| DATA_ADC1_90 | output | TCELL21:OUT.30.TMIN |
| DATA_ADC1_91 | output | TCELL22:OUT.1.TMIN |
| DATA_ADC1_92 | output | TCELL22:OUT.6.TMIN |
| DATA_ADC1_93 | output | TCELL22:OUT.8.TMIN |
| DATA_ADC1_94 | output | TCELL22:OUT.10.TMIN |
| DATA_ADC1_95 | output | TCELL22:OUT.12.TMIN |
| DATA_ADC1_96 | output | TCELL22:OUT.14.TMIN |
| DATA_ADC1_97 | output | TCELL22:OUT.16.TMIN |
| DATA_ADC1_98 | output | TCELL22:OUT.18.TMIN |
| DATA_ADC1_99 | output | TCELL22:OUT.20.TMIN |
| DATA_ADC2_0 | output | TCELL30:OUT.10.TMIN |
| DATA_ADC2_1 | output | TCELL30:OUT.12.TMIN |
| DATA_ADC2_10 | output | TCELL31:OUT.1.TMIN |
| DATA_ADC2_100 | output | TCELL37:OUT.30.TMIN |
| DATA_ADC2_101 | output | TCELL38:OUT.1.TMIN |
| DATA_ADC2_102 | output | TCELL38:OUT.6.TMIN |
| DATA_ADC2_103 | output | TCELL38:OUT.8.TMIN |
| DATA_ADC2_104 | output | TCELL38:OUT.10.TMIN |
| DATA_ADC2_105 | output | TCELL38:OUT.12.TMIN |
| DATA_ADC2_106 | output | TCELL38:OUT.14.TMIN |
| DATA_ADC2_107 | output | TCELL38:OUT.16.TMIN |
| DATA_ADC2_108 | output | TCELL38:OUT.18.TMIN |
| DATA_ADC2_109 | output | TCELL38:OUT.20.TMIN |
| DATA_ADC2_11 | output | TCELL31:OUT.6.TMIN |
| DATA_ADC2_110 | output | TCELL38:OUT.22.TMIN |
| DATA_ADC2_111 | output | TCELL38:OUT.24.TMIN |
| DATA_ADC2_112 | output | TCELL38:OUT.26.TMIN |
| DATA_ADC2_113 | output | TCELL38:OUT.30.TMIN |
| DATA_ADC2_114 | output | TCELL39:OUT.1.TMIN |
| DATA_ADC2_115 | output | TCELL39:OUT.6.TMIN |
| DATA_ADC2_116 | output | TCELL39:OUT.8.TMIN |
| DATA_ADC2_117 | output | TCELL39:OUT.10.TMIN |
| DATA_ADC2_118 | output | TCELL39:OUT.12.TMIN |
| DATA_ADC2_119 | output | TCELL39:OUT.14.TMIN |
| DATA_ADC2_12 | output | TCELL31:OUT.8.TMIN |
| DATA_ADC2_120 | output | TCELL39:OUT.16.TMIN |
| DATA_ADC2_121 | output | TCELL39:OUT.18.TMIN |
| DATA_ADC2_122 | output | TCELL39:OUT.20.TMIN |
| DATA_ADC2_123 | output | TCELL39:OUT.22.TMIN |
| DATA_ADC2_124 | output | TCELL39:OUT.24.TMIN |
| DATA_ADC2_125 | output | TCELL39:OUT.26.TMIN |
| DATA_ADC2_126 | output | TCELL39:OUT.30.TMIN |
| DATA_ADC2_127 | output | TCELL40:OUT.1.TMIN |
| DATA_ADC2_128 | output | TCELL40:OUT.6.TMIN |
| DATA_ADC2_129 | output | TCELL40:OUT.8.TMIN |
| DATA_ADC2_13 | output | TCELL31:OUT.10.TMIN |
| DATA_ADC2_130 | output | TCELL40:OUT.10.TMIN |
| DATA_ADC2_131 | output | TCELL40:OUT.12.TMIN |
| DATA_ADC2_132 | output | TCELL40:OUT.14.TMIN |
| DATA_ADC2_133 | output | TCELL40:OUT.16.TMIN |
| DATA_ADC2_134 | output | TCELL40:OUT.18.TMIN |
| DATA_ADC2_135 | output | TCELL40:OUT.20.TMIN |
| DATA_ADC2_136 | output | TCELL40:OUT.22.TMIN |
| DATA_ADC2_137 | output | TCELL40:OUT.24.TMIN |
| DATA_ADC2_138 | output | TCELL40:OUT.26.TMIN |
| DATA_ADC2_139 | output | TCELL40:OUT.30.TMIN |
| DATA_ADC2_14 | output | TCELL31:OUT.12.TMIN |
| DATA_ADC2_140 | output | TCELL41:OUT.1.TMIN |
| DATA_ADC2_141 | output | TCELL41:OUT.6.TMIN |
| DATA_ADC2_142 | output | TCELL41:OUT.8.TMIN |
| DATA_ADC2_143 | output | TCELL41:OUT.10.TMIN |
| DATA_ADC2_144 | output | TCELL41:OUT.12.TMIN |
| DATA_ADC2_145 | output | TCELL41:OUT.14.TMIN |
| DATA_ADC2_146 | output | TCELL41:OUT.16.TMIN |
| DATA_ADC2_147 | output | TCELL41:OUT.18.TMIN |
| DATA_ADC2_148 | output | TCELL41:OUT.20.TMIN |
| DATA_ADC2_149 | output | TCELL41:OUT.22.TMIN |
| DATA_ADC2_15 | output | TCELL31:OUT.14.TMIN |
| DATA_ADC2_150 | output | TCELL41:OUT.24.TMIN |
| DATA_ADC2_151 | output | TCELL41:OUT.26.TMIN |
| DATA_ADC2_152 | output | TCELL41:OUT.30.TMIN |
| DATA_ADC2_153 | output | TCELL42:OUT.1.TMIN |
| DATA_ADC2_154 | output | TCELL42:OUT.6.TMIN |
| DATA_ADC2_155 | output | TCELL42:OUT.8.TMIN |
| DATA_ADC2_156 | output | TCELL42:OUT.10.TMIN |
| DATA_ADC2_157 | output | TCELL42:OUT.12.TMIN |
| DATA_ADC2_158 | output | TCELL42:OUT.14.TMIN |
| DATA_ADC2_159 | output | TCELL42:OUT.16.TMIN |
| DATA_ADC2_16 | output | TCELL31:OUT.16.TMIN |
| DATA_ADC2_160 | output | TCELL42:OUT.18.TMIN |
| DATA_ADC2_161 | output | TCELL42:OUT.20.TMIN |
| DATA_ADC2_162 | output | TCELL42:OUT.22.TMIN |
| DATA_ADC2_163 | output | TCELL42:OUT.24.TMIN |
| DATA_ADC2_164 | output | TCELL42:OUT.26.TMIN |
| DATA_ADC2_165 | output | TCELL42:OUT.30.TMIN |
| DATA_ADC2_166 | output | TCELL43:OUT.1.TMIN |
| DATA_ADC2_167 | output | TCELL43:OUT.6.TMIN |
| DATA_ADC2_168 | output | TCELL43:OUT.8.TMIN |
| DATA_ADC2_169 | output | TCELL43:OUT.10.TMIN |
| DATA_ADC2_17 | output | TCELL31:OUT.18.TMIN |
| DATA_ADC2_170 | output | TCELL43:OUT.12.TMIN |
| DATA_ADC2_171 | output | TCELL43:OUT.14.TMIN |
| DATA_ADC2_172 | output | TCELL43:OUT.16.TMIN |
| DATA_ADC2_173 | output | TCELL43:OUT.18.TMIN |
| DATA_ADC2_174 | output | TCELL43:OUT.20.TMIN |
| DATA_ADC2_175 | output | TCELL43:OUT.22.TMIN |
| DATA_ADC2_176 | output | TCELL43:OUT.24.TMIN |
| DATA_ADC2_177 | output | TCELL43:OUT.26.TMIN |
| DATA_ADC2_178 | output | TCELL43:OUT.30.TMIN |
| DATA_ADC2_179 | output | TCELL44:OUT.1.TMIN |
| DATA_ADC2_18 | output | TCELL31:OUT.20.TMIN |
| DATA_ADC2_180 | output | TCELL44:OUT.6.TMIN |
| DATA_ADC2_181 | output | TCELL44:OUT.8.TMIN |
| DATA_ADC2_182 | output | TCELL44:OUT.10.TMIN |
| DATA_ADC2_183 | output | TCELL44:OUT.12.TMIN |
| DATA_ADC2_184 | output | TCELL44:OUT.14.TMIN |
| DATA_ADC2_185 | output | TCELL44:OUT.16.TMIN |
| DATA_ADC2_186 | output | TCELL44:OUT.18.TMIN |
| DATA_ADC2_187 | output | TCELL44:OUT.20.TMIN |
| DATA_ADC2_188 | output | TCELL44:OUT.22.TMIN |
| DATA_ADC2_189 | output | TCELL44:OUT.24.TMIN |
| DATA_ADC2_19 | output | TCELL31:OUT.22.TMIN |
| DATA_ADC2_190 | output | TCELL44:OUT.26.TMIN |
| DATA_ADC2_191 | output | TCELL44:OUT.30.TMIN |
| DATA_ADC2_2 | output | TCELL30:OUT.14.TMIN |
| DATA_ADC2_20 | output | TCELL31:OUT.24.TMIN |
| DATA_ADC2_21 | output | TCELL31:OUT.26.TMIN |
| DATA_ADC2_22 | output | TCELL31:OUT.30.TMIN |
| DATA_ADC2_23 | output | TCELL32:OUT.2.TMIN |
| DATA_ADC2_24 | output | TCELL32:OUT.6.TMIN |
| DATA_ADC2_25 | output | TCELL32:OUT.8.TMIN |
| DATA_ADC2_26 | output | TCELL32:OUT.10.TMIN |
| DATA_ADC2_27 | output | TCELL32:OUT.12.TMIN |
| DATA_ADC2_28 | output | TCELL32:OUT.14.TMIN |
| DATA_ADC2_29 | output | TCELL32:OUT.16.TMIN |
| DATA_ADC2_3 | output | TCELL30:OUT.16.TMIN |
| DATA_ADC2_30 | output | TCELL32:OUT.18.TMIN |
| DATA_ADC2_31 | output | TCELL32:OUT.20.TMIN |
| DATA_ADC2_32 | output | TCELL32:OUT.22.TMIN |
| DATA_ADC2_33 | output | TCELL32:OUT.24.TMIN |
| DATA_ADC2_34 | output | TCELL32:OUT.26.TMIN |
| DATA_ADC2_35 | output | TCELL32:OUT.30.TMIN |
| DATA_ADC2_36 | output | TCELL33:OUT.1.TMIN |
| DATA_ADC2_37 | output | TCELL33:OUT.6.TMIN |
| DATA_ADC2_38 | output | TCELL33:OUT.8.TMIN |
| DATA_ADC2_39 | output | TCELL33:OUT.10.TMIN |
| DATA_ADC2_4 | output | TCELL30:OUT.18.TMIN |
| DATA_ADC2_40 | output | TCELL33:OUT.12.TMIN |
| DATA_ADC2_41 | output | TCELL33:OUT.14.TMIN |
| DATA_ADC2_42 | output | TCELL33:OUT.16.TMIN |
| DATA_ADC2_43 | output | TCELL33:OUT.18.TMIN |
| DATA_ADC2_44 | output | TCELL33:OUT.20.TMIN |
| DATA_ADC2_45 | output | TCELL33:OUT.22.TMIN |
| DATA_ADC2_46 | output | TCELL33:OUT.24.TMIN |
| DATA_ADC2_47 | output | TCELL33:OUT.26.TMIN |
| DATA_ADC2_48 | output | TCELL33:OUT.30.TMIN |
| DATA_ADC2_49 | output | TCELL34:OUT.1.TMIN |
| DATA_ADC2_5 | output | TCELL30:OUT.20.TMIN |
| DATA_ADC2_50 | output | TCELL34:OUT.6.TMIN |
| DATA_ADC2_51 | output | TCELL34:OUT.8.TMIN |
| DATA_ADC2_52 | output | TCELL34:OUT.10.TMIN |
| DATA_ADC2_53 | output | TCELL34:OUT.12.TMIN |
| DATA_ADC2_54 | output | TCELL34:OUT.14.TMIN |
| DATA_ADC2_55 | output | TCELL34:OUT.16.TMIN |
| DATA_ADC2_56 | output | TCELL34:OUT.18.TMIN |
| DATA_ADC2_57 | output | TCELL34:OUT.20.TMIN |
| DATA_ADC2_58 | output | TCELL34:OUT.22.TMIN |
| DATA_ADC2_59 | output | TCELL34:OUT.24.TMIN |
| DATA_ADC2_6 | output | TCELL30:OUT.22.TMIN |
| DATA_ADC2_60 | output | TCELL34:OUT.26.TMIN |
| DATA_ADC2_61 | output | TCELL34:OUT.30.TMIN |
| DATA_ADC2_62 | output | TCELL35:OUT.1.TMIN |
| DATA_ADC2_63 | output | TCELL35:OUT.6.TMIN |
| DATA_ADC2_64 | output | TCELL35:OUT.8.TMIN |
| DATA_ADC2_65 | output | TCELL35:OUT.10.TMIN |
| DATA_ADC2_66 | output | TCELL35:OUT.12.TMIN |
| DATA_ADC2_67 | output | TCELL35:OUT.14.TMIN |
| DATA_ADC2_68 | output | TCELL35:OUT.16.TMIN |
| DATA_ADC2_69 | output | TCELL35:OUT.18.TMIN |
| DATA_ADC2_7 | output | TCELL30:OUT.24.TMIN |
| DATA_ADC2_70 | output | TCELL35:OUT.20.TMIN |
| DATA_ADC2_71 | output | TCELL35:OUT.22.TMIN |
| DATA_ADC2_72 | output | TCELL35:OUT.24.TMIN |
| DATA_ADC2_73 | output | TCELL35:OUT.26.TMIN |
| DATA_ADC2_74 | output | TCELL35:OUT.30.TMIN |
| DATA_ADC2_75 | output | TCELL36:OUT.1.TMIN |
| DATA_ADC2_76 | output | TCELL36:OUT.6.TMIN |
| DATA_ADC2_77 | output | TCELL36:OUT.8.TMIN |
| DATA_ADC2_78 | output | TCELL36:OUT.10.TMIN |
| DATA_ADC2_79 | output | TCELL36:OUT.12.TMIN |
| DATA_ADC2_8 | output | TCELL30:OUT.26.TMIN |
| DATA_ADC2_80 | output | TCELL36:OUT.14.TMIN |
| DATA_ADC2_81 | output | TCELL36:OUT.16.TMIN |
| DATA_ADC2_82 | output | TCELL36:OUT.18.TMIN |
| DATA_ADC2_83 | output | TCELL36:OUT.20.TMIN |
| DATA_ADC2_84 | output | TCELL36:OUT.22.TMIN |
| DATA_ADC2_85 | output | TCELL36:OUT.24.TMIN |
| DATA_ADC2_86 | output | TCELL36:OUT.26.TMIN |
| DATA_ADC2_87 | output | TCELL36:OUT.30.TMIN |
| DATA_ADC2_88 | output | TCELL37:OUT.1.TMIN |
| DATA_ADC2_89 | output | TCELL37:OUT.6.TMIN |
| DATA_ADC2_9 | output | TCELL30:OUT.30.TMIN |
| DATA_ADC2_90 | output | TCELL37:OUT.8.TMIN |
| DATA_ADC2_91 | output | TCELL37:OUT.10.TMIN |
| DATA_ADC2_92 | output | TCELL37:OUT.12.TMIN |
| DATA_ADC2_93 | output | TCELL37:OUT.14.TMIN |
| DATA_ADC2_94 | output | TCELL37:OUT.16.TMIN |
| DATA_ADC2_95 | output | TCELL37:OUT.18.TMIN |
| DATA_ADC2_96 | output | TCELL37:OUT.20.TMIN |
| DATA_ADC2_97 | output | TCELL37:OUT.22.TMIN |
| DATA_ADC2_98 | output | TCELL37:OUT.24.TMIN |
| DATA_ADC2_99 | output | TCELL37:OUT.26.TMIN |
| DATA_ADC3_0 | output | TCELL45:OUT.1.TMIN |
| DATA_ADC3_1 | output | TCELL45:OUT.6.TMIN |
| DATA_ADC3_10 | output | TCELL45:OUT.24.TMIN |
| DATA_ADC3_100 | output | TCELL52:OUT.22.TMIN |
| DATA_ADC3_101 | output | TCELL52:OUT.24.TMIN |
| DATA_ADC3_102 | output | TCELL52:OUT.26.TMIN |
| DATA_ADC3_103 | output | TCELL52:OUT.30.TMIN |
| DATA_ADC3_104 | output | TCELL53:OUT.1.TMIN |
| DATA_ADC3_105 | output | TCELL53:OUT.6.TMIN |
| DATA_ADC3_106 | output | TCELL53:OUT.8.TMIN |
| DATA_ADC3_107 | output | TCELL53:OUT.10.TMIN |
| DATA_ADC3_108 | output | TCELL53:OUT.12.TMIN |
| DATA_ADC3_109 | output | TCELL53:OUT.14.TMIN |
| DATA_ADC3_11 | output | TCELL45:OUT.26.TMIN |
| DATA_ADC3_110 | output | TCELL53:OUT.16.TMIN |
| DATA_ADC3_111 | output | TCELL53:OUT.18.TMIN |
| DATA_ADC3_112 | output | TCELL53:OUT.20.TMIN |
| DATA_ADC3_113 | output | TCELL53:OUT.22.TMIN |
| DATA_ADC3_114 | output | TCELL53:OUT.24.TMIN |
| DATA_ADC3_115 | output | TCELL53:OUT.26.TMIN |
| DATA_ADC3_116 | output | TCELL53:OUT.30.TMIN |
| DATA_ADC3_117 | output | TCELL54:OUT.1.TMIN |
| DATA_ADC3_118 | output | TCELL54:OUT.6.TMIN |
| DATA_ADC3_119 | output | TCELL54:OUT.8.TMIN |
| DATA_ADC3_12 | output | TCELL45:OUT.30.TMIN |
| DATA_ADC3_120 | output | TCELL54:OUT.10.TMIN |
| DATA_ADC3_121 | output | TCELL54:OUT.12.TMIN |
| DATA_ADC3_122 | output | TCELL54:OUT.14.TMIN |
| DATA_ADC3_123 | output | TCELL54:OUT.16.TMIN |
| DATA_ADC3_124 | output | TCELL54:OUT.18.TMIN |
| DATA_ADC3_125 | output | TCELL54:OUT.20.TMIN |
| DATA_ADC3_126 | output | TCELL54:OUT.22.TMIN |
| DATA_ADC3_127 | output | TCELL54:OUT.24.TMIN |
| DATA_ADC3_128 | output | TCELL54:OUT.26.TMIN |
| DATA_ADC3_129 | output | TCELL54:OUT.30.TMIN |
| DATA_ADC3_13 | output | TCELL46:OUT.1.TMIN |
| DATA_ADC3_130 | output | TCELL55:OUT.1.TMIN |
| DATA_ADC3_131 | output | TCELL55:OUT.6.TMIN |
| DATA_ADC3_132 | output | TCELL55:OUT.8.TMIN |
| DATA_ADC3_133 | output | TCELL55:OUT.10.TMIN |
| DATA_ADC3_134 | output | TCELL55:OUT.12.TMIN |
| DATA_ADC3_135 | output | TCELL55:OUT.14.TMIN |
| DATA_ADC3_136 | output | TCELL55:OUT.16.TMIN |
| DATA_ADC3_137 | output | TCELL55:OUT.18.TMIN |
| DATA_ADC3_138 | output | TCELL55:OUT.20.TMIN |
| DATA_ADC3_139 | output | TCELL55:OUT.22.TMIN |
| DATA_ADC3_14 | output | TCELL46:OUT.6.TMIN |
| DATA_ADC3_140 | output | TCELL55:OUT.24.TMIN |
| DATA_ADC3_141 | output | TCELL55:OUT.26.TMIN |
| DATA_ADC3_142 | output | TCELL55:OUT.30.TMIN |
| DATA_ADC3_143 | output | TCELL56:OUT.1.TMIN |
| DATA_ADC3_144 | output | TCELL56:OUT.6.TMIN |
| DATA_ADC3_145 | output | TCELL56:OUT.8.TMIN |
| DATA_ADC3_146 | output | TCELL56:OUT.10.TMIN |
| DATA_ADC3_147 | output | TCELL56:OUT.12.TMIN |
| DATA_ADC3_148 | output | TCELL56:OUT.14.TMIN |
| DATA_ADC3_149 | output | TCELL56:OUT.16.TMIN |
| DATA_ADC3_15 | output | TCELL46:OUT.8.TMIN |
| DATA_ADC3_150 | output | TCELL56:OUT.18.TMIN |
| DATA_ADC3_151 | output | TCELL56:OUT.20.TMIN |
| DATA_ADC3_152 | output | TCELL56:OUT.22.TMIN |
| DATA_ADC3_153 | output | TCELL56:OUT.24.TMIN |
| DATA_ADC3_154 | output | TCELL56:OUT.26.TMIN |
| DATA_ADC3_155 | output | TCELL56:OUT.30.TMIN |
| DATA_ADC3_156 | output | TCELL57:OUT.1.TMIN |
| DATA_ADC3_157 | output | TCELL57:OUT.6.TMIN |
| DATA_ADC3_158 | output | TCELL57:OUT.8.TMIN |
| DATA_ADC3_159 | output | TCELL57:OUT.10.TMIN |
| DATA_ADC3_16 | output | TCELL46:OUT.10.TMIN |
| DATA_ADC3_160 | output | TCELL57:OUT.12.TMIN |
| DATA_ADC3_161 | output | TCELL57:OUT.14.TMIN |
| DATA_ADC3_162 | output | TCELL57:OUT.16.TMIN |
| DATA_ADC3_163 | output | TCELL57:OUT.18.TMIN |
| DATA_ADC3_164 | output | TCELL57:OUT.20.TMIN |
| DATA_ADC3_165 | output | TCELL57:OUT.22.TMIN |
| DATA_ADC3_166 | output | TCELL57:OUT.24.TMIN |
| DATA_ADC3_167 | output | TCELL57:OUT.26.TMIN |
| DATA_ADC3_168 | output | TCELL57:OUT.30.TMIN |
| DATA_ADC3_169 | output | TCELL58:OUT.1.TMIN |
| DATA_ADC3_17 | output | TCELL46:OUT.12.TMIN |
| DATA_ADC3_170 | output | TCELL58:OUT.6.TMIN |
| DATA_ADC3_171 | output | TCELL58:OUT.8.TMIN |
| DATA_ADC3_172 | output | TCELL58:OUT.10.TMIN |
| DATA_ADC3_173 | output | TCELL58:OUT.12.TMIN |
| DATA_ADC3_174 | output | TCELL58:OUT.14.TMIN |
| DATA_ADC3_175 | output | TCELL58:OUT.16.TMIN |
| DATA_ADC3_176 | output | TCELL58:OUT.18.TMIN |
| DATA_ADC3_177 | output | TCELL58:OUT.20.TMIN |
| DATA_ADC3_178 | output | TCELL58:OUT.22.TMIN |
| DATA_ADC3_179 | output | TCELL58:OUT.24.TMIN |
| DATA_ADC3_18 | output | TCELL46:OUT.14.TMIN |
| DATA_ADC3_180 | output | TCELL58:OUT.26.TMIN |
| DATA_ADC3_181 | output | TCELL58:OUT.30.TMIN |
| DATA_ADC3_182 | output | TCELL59:OUT.1.TMIN |
| DATA_ADC3_183 | output | TCELL59:OUT.6.TMIN |
| DATA_ADC3_184 | output | TCELL59:OUT.8.TMIN |
| DATA_ADC3_185 | output | TCELL59:OUT.10.TMIN |
| DATA_ADC3_186 | output | TCELL59:OUT.14.TMIN |
| DATA_ADC3_187 | output | TCELL59:OUT.18.TMIN |
| DATA_ADC3_188 | output | TCELL59:OUT.22.TMIN |
| DATA_ADC3_189 | output | TCELL59:OUT.26.TMIN |
| DATA_ADC3_19 | output | TCELL46:OUT.16.TMIN |
| DATA_ADC3_190 | output | TCELL59:OUT.28.TMIN |
| DATA_ADC3_191 | output | TCELL59:OUT.30.TMIN |
| DATA_ADC3_2 | output | TCELL45:OUT.8.TMIN |
| DATA_ADC3_20 | output | TCELL46:OUT.18.TMIN |
| DATA_ADC3_21 | output | TCELL46:OUT.20.TMIN |
| DATA_ADC3_22 | output | TCELL46:OUT.22.TMIN |
| DATA_ADC3_23 | output | TCELL46:OUT.24.TMIN |
| DATA_ADC3_24 | output | TCELL46:OUT.26.TMIN |
| DATA_ADC3_25 | output | TCELL46:OUT.30.TMIN |
| DATA_ADC3_26 | output | TCELL47:OUT.1.TMIN |
| DATA_ADC3_27 | output | TCELL47:OUT.6.TMIN |
| DATA_ADC3_28 | output | TCELL47:OUT.8.TMIN |
| DATA_ADC3_29 | output | TCELL47:OUT.10.TMIN |
| DATA_ADC3_3 | output | TCELL45:OUT.10.TMIN |
| DATA_ADC3_30 | output | TCELL47:OUT.12.TMIN |
| DATA_ADC3_31 | output | TCELL47:OUT.14.TMIN |
| DATA_ADC3_32 | output | TCELL47:OUT.16.TMIN |
| DATA_ADC3_33 | output | TCELL47:OUT.18.TMIN |
| DATA_ADC3_34 | output | TCELL47:OUT.20.TMIN |
| DATA_ADC3_35 | output | TCELL47:OUT.22.TMIN |
| DATA_ADC3_36 | output | TCELL47:OUT.24.TMIN |
| DATA_ADC3_37 | output | TCELL47:OUT.26.TMIN |
| DATA_ADC3_38 | output | TCELL47:OUT.30.TMIN |
| DATA_ADC3_39 | output | TCELL48:OUT.1.TMIN |
| DATA_ADC3_4 | output | TCELL45:OUT.12.TMIN |
| DATA_ADC3_40 | output | TCELL48:OUT.6.TMIN |
| DATA_ADC3_41 | output | TCELL48:OUT.8.TMIN |
| DATA_ADC3_42 | output | TCELL48:OUT.10.TMIN |
| DATA_ADC3_43 | output | TCELL48:OUT.12.TMIN |
| DATA_ADC3_44 | output | TCELL48:OUT.14.TMIN |
| DATA_ADC3_45 | output | TCELL48:OUT.16.TMIN |
| DATA_ADC3_46 | output | TCELL48:OUT.18.TMIN |
| DATA_ADC3_47 | output | TCELL48:OUT.20.TMIN |
| DATA_ADC3_48 | output | TCELL48:OUT.22.TMIN |
| DATA_ADC3_49 | output | TCELL48:OUT.24.TMIN |
| DATA_ADC3_5 | output | TCELL45:OUT.14.TMIN |
| DATA_ADC3_50 | output | TCELL48:OUT.26.TMIN |
| DATA_ADC3_51 | output | TCELL48:OUT.30.TMIN |
| DATA_ADC3_52 | output | TCELL49:OUT.1.TMIN |
| DATA_ADC3_53 | output | TCELL49:OUT.6.TMIN |
| DATA_ADC3_54 | output | TCELL49:OUT.8.TMIN |
| DATA_ADC3_55 | output | TCELL49:OUT.10.TMIN |
| DATA_ADC3_56 | output | TCELL49:OUT.12.TMIN |
| DATA_ADC3_57 | output | TCELL49:OUT.14.TMIN |
| DATA_ADC3_58 | output | TCELL49:OUT.16.TMIN |
| DATA_ADC3_59 | output | TCELL49:OUT.18.TMIN |
| DATA_ADC3_6 | output | TCELL45:OUT.16.TMIN |
| DATA_ADC3_60 | output | TCELL49:OUT.20.TMIN |
| DATA_ADC3_61 | output | TCELL49:OUT.22.TMIN |
| DATA_ADC3_62 | output | TCELL49:OUT.24.TMIN |
| DATA_ADC3_63 | output | TCELL49:OUT.26.TMIN |
| DATA_ADC3_64 | output | TCELL49:OUT.30.TMIN |
| DATA_ADC3_65 | output | TCELL50:OUT.1.TMIN |
| DATA_ADC3_66 | output | TCELL50:OUT.6.TMIN |
| DATA_ADC3_67 | output | TCELL50:OUT.8.TMIN |
| DATA_ADC3_68 | output | TCELL50:OUT.10.TMIN |
| DATA_ADC3_69 | output | TCELL50:OUT.12.TMIN |
| DATA_ADC3_7 | output | TCELL45:OUT.18.TMIN |
| DATA_ADC3_70 | output | TCELL50:OUT.14.TMIN |
| DATA_ADC3_71 | output | TCELL50:OUT.16.TMIN |
| DATA_ADC3_72 | output | TCELL50:OUT.18.TMIN |
| DATA_ADC3_73 | output | TCELL50:OUT.20.TMIN |
| DATA_ADC3_74 | output | TCELL50:OUT.22.TMIN |
| DATA_ADC3_75 | output | TCELL50:OUT.24.TMIN |
| DATA_ADC3_76 | output | TCELL50:OUT.26.TMIN |
| DATA_ADC3_77 | output | TCELL50:OUT.30.TMIN |
| DATA_ADC3_78 | output | TCELL51:OUT.1.TMIN |
| DATA_ADC3_79 | output | TCELL51:OUT.6.TMIN |
| DATA_ADC3_8 | output | TCELL45:OUT.20.TMIN |
| DATA_ADC3_80 | output | TCELL51:OUT.8.TMIN |
| DATA_ADC3_81 | output | TCELL51:OUT.10.TMIN |
| DATA_ADC3_82 | output | TCELL51:OUT.12.TMIN |
| DATA_ADC3_83 | output | TCELL51:OUT.14.TMIN |
| DATA_ADC3_84 | output | TCELL51:OUT.16.TMIN |
| DATA_ADC3_85 | output | TCELL51:OUT.18.TMIN |
| DATA_ADC3_86 | output | TCELL51:OUT.20.TMIN |
| DATA_ADC3_87 | output | TCELL51:OUT.22.TMIN |
| DATA_ADC3_88 | output | TCELL51:OUT.24.TMIN |
| DATA_ADC3_89 | output | TCELL51:OUT.26.TMIN |
| DATA_ADC3_9 | output | TCELL45:OUT.22.TMIN |
| DATA_ADC3_90 | output | TCELL51:OUT.30.TMIN |
| DATA_ADC3_91 | output | TCELL52:OUT.1.TMIN |
| DATA_ADC3_92 | output | TCELL52:OUT.6.TMIN |
| DATA_ADC3_93 | output | TCELL52:OUT.8.TMIN |
| DATA_ADC3_94 | output | TCELL52:OUT.10.TMIN |
| DATA_ADC3_95 | output | TCELL52:OUT.12.TMIN |
| DATA_ADC3_96 | output | TCELL52:OUT.14.TMIN |
| DATA_ADC3_97 | output | TCELL52:OUT.16.TMIN |
| DATA_ADC3_98 | output | TCELL52:OUT.18.TMIN |
| DATA_ADC3_99 | output | TCELL52:OUT.20.TMIN |
| DCLK | input | TCELL28:IMUX.CTRL.4 |
| DEN | input | TCELL34:IMUX.IMUX.8.DELAY |
| DI0 | input | TCELL25:IMUX.IMUX.23.DELAY |
| DI1 | input | TCELL25:IMUX.IMUX.8.DELAY |
| DI10 | input | TCELL28:IMUX.IMUX.8.DELAY |
| DI11 | input | TCELL28:IMUX.IMUX.12.DELAY |
| DI12 | input | TCELL29:IMUX.IMUX.23.DELAY |
| DI13 | input | TCELL29:IMUX.IMUX.8.DELAY |
| DI14 | input | TCELL29:IMUX.IMUX.12.DELAY |
| DI15 | input | TCELL30:IMUX.IMUX.23.DELAY |
| DI2 | input | TCELL25:IMUX.IMUX.12.DELAY |
| DI3 | input | TCELL26:IMUX.IMUX.23.DELAY |
| DI4 | input | TCELL26:IMUX.IMUX.8.DELAY |
| DI5 | input | TCELL26:IMUX.IMUX.12.DELAY |
| DI6 | input | TCELL27:IMUX.IMUX.23.DELAY |
| DI7 | input | TCELL27:IMUX.IMUX.8.DELAY |
| DI8 | input | TCELL27:IMUX.IMUX.12.DELAY |
| DI9 | input | TCELL28:IMUX.IMUX.23.DELAY |
| DOUT0 | output | TCELL25:OUT.28.TMIN |
| DOUT1 | output | TCELL26:OUT.4.TMIN |
| DOUT10 | output | TCELL31:OUT.4.TMIN |
| DOUT11 | output | TCELL31:OUT.28.TMIN |
| DOUT12 | output | TCELL32:OUT.4.TMIN |
| DOUT13 | output | TCELL32:OUT.28.TMIN |
| DOUT14 | output | TCELL33:OUT.4.TMIN |
| DOUT15 | output | TCELL33:OUT.28.TMIN |
| DOUT2 | output | TCELL26:OUT.28.TMIN |
| DOUT3 | output | TCELL27:OUT.4.TMIN |
| DOUT4 | output | TCELL27:OUT.28.TMIN |
| DOUT5 | output | TCELL28:OUT.4.TMIN |
| DOUT6 | output | TCELL28:OUT.28.TMIN |
| DOUT7 | output | TCELL29:OUT.4.TMIN |
| DOUT8 | output | TCELL30:OUT.4.TMIN |
| DOUT9 | output | TCELL30:OUT.28.TMIN |
| DRDY | output | TCELL29:OUT.28.TMIN |
| DWE | input | TCELL34:IMUX.IMUX.23.DELAY |
| FABRIC_CLK | input | TCELL31:IMUX.CTRL.5 |
| PLL_MONCLK | input | TCELL32:IMUX.CTRL.4 |
| PLL_REFCLK_IN_FABRIC | input | TCELL32:IMUX.CTRL.5 |
| PLL_SCAN_CLK_FD0 | input | TCELL28:IMUX.CTRL.5 |
| PLL_SCAN_CLK_FD1 | input | TCELL31:IMUX.CTRL.4 |
| PLL_SCAN_EN_B_FD | input | TCELL28:IMUX.IMUX.26.DELAY |
| PLL_SCAN_IN_FD0 | input | TCELL31:IMUX.IMUX.26.DELAY |
| PLL_SCAN_IN_FD1 | input | TCELL32:IMUX.IMUX.26.DELAY |
| PLL_SCAN_MODE_B_FD | input | TCELL27:IMUX.IMUX.36.DELAY |
| PLL_SCAN_OUT_B_FD0 | output | TCELL28:OUT.17.TMIN |
| PLL_SCAN_OUT_B_FD1 | output | TCELL31:OUT.17.TMIN |
| PLL_SCAN_RST_EN_FD | input | TCELL33:IMUX.IMUX.26.DELAY |
| STATUS_ADC0_0 | output | TCELL0:OUT.4.TMIN |
| STATUS_ADC0_1 | output | TCELL0:OUT.10.TMIN |
| STATUS_ADC0_10 | output | TCELL3:OUT.28.TMIN |
| STATUS_ADC0_11 | output | TCELL4:OUT.4.TMIN |
| STATUS_ADC0_12 | output | TCELL4:OUT.28.TMIN |
| STATUS_ADC0_13 | output | TCELL5:OUT.4.TMIN |
| STATUS_ADC0_14 | output | TCELL5:OUT.28.TMIN |
| STATUS_ADC0_15 | output | TCELL6:OUT.4.TMIN |
| STATUS_ADC0_16 | output | TCELL6:OUT.28.TMIN |
| STATUS_ADC0_17 | output | TCELL7:OUT.4.TMIN |
| STATUS_ADC0_18 | output | TCELL7:OUT.28.TMIN |
| STATUS_ADC0_19 | output | TCELL8:OUT.4.TMIN |
| STATUS_ADC0_2 | output | TCELL0:OUT.14.TMIN |
| STATUS_ADC0_20 | output | TCELL8:OUT.28.TMIN |
| STATUS_ADC0_21 | output | TCELL9:OUT.4.TMIN |
| STATUS_ADC0_22 | output | TCELL9:OUT.28.TMIN |
| STATUS_ADC0_23 | output | TCELL10:OUT.28.TMIN |
| STATUS_ADC0_3 | output | TCELL0:OUT.18.TMIN |
| STATUS_ADC0_4 | output | TCELL0:OUT.28.TMIN |
| STATUS_ADC0_5 | output | TCELL1:OUT.4.TMIN |
| STATUS_ADC0_6 | output | TCELL1:OUT.28.TMIN |
| STATUS_ADC0_7 | output | TCELL2:OUT.4.TMIN |
| STATUS_ADC0_8 | output | TCELL2:OUT.28.TMIN |
| STATUS_ADC0_9 | output | TCELL3:OUT.4.TMIN |
| STATUS_ADC1_0 | output | TCELL10:OUT.4.TMIN |
| STATUS_ADC1_1 | output | TCELL11:OUT.4.TMIN |
| STATUS_ADC1_10 | output | TCELL15:OUT.28.TMIN |
| STATUS_ADC1_11 | output | TCELL16:OUT.4.TMIN |
| STATUS_ADC1_12 | output | TCELL16:OUT.28.TMIN |
| STATUS_ADC1_13 | output | TCELL17:OUT.4.TMIN |
| STATUS_ADC1_14 | output | TCELL17:OUT.28.TMIN |
| STATUS_ADC1_15 | output | TCELL18:OUT.4.TMIN |
| STATUS_ADC1_16 | output | TCELL18:OUT.28.TMIN |
| STATUS_ADC1_17 | output | TCELL19:OUT.4.TMIN |
| STATUS_ADC1_18 | output | TCELL19:OUT.28.TMIN |
| STATUS_ADC1_19 | output | TCELL20:OUT.4.TMIN |
| STATUS_ADC1_2 | output | TCELL11:OUT.28.TMIN |
| STATUS_ADC1_20 | output | TCELL20:OUT.28.TMIN |
| STATUS_ADC1_21 | output | TCELL21:OUT.4.TMIN |
| STATUS_ADC1_22 | output | TCELL21:OUT.28.TMIN |
| STATUS_ADC1_23 | output | TCELL22:OUT.4.TMIN |
| STATUS_ADC1_3 | output | TCELL12:OUT.4.TMIN |
| STATUS_ADC1_4 | output | TCELL12:OUT.28.TMIN |
| STATUS_ADC1_5 | output | TCELL13:OUT.4.TMIN |
| STATUS_ADC1_6 | output | TCELL13:OUT.28.TMIN |
| STATUS_ADC1_7 | output | TCELL14:OUT.4.TMIN |
| STATUS_ADC1_8 | output | TCELL14:OUT.28.TMIN |
| STATUS_ADC1_9 | output | TCELL15:OUT.4.TMIN |
| STATUS_ADC2_0 | output | TCELL37:OUT.4.TMIN |
| STATUS_ADC2_1 | output | TCELL38:OUT.4.TMIN |
| STATUS_ADC2_10 | output | TCELL42:OUT.28.TMIN |
| STATUS_ADC2_11 | output | TCELL43:OUT.4.TMIN |
| STATUS_ADC2_12 | output | TCELL43:OUT.28.TMIN |
| STATUS_ADC2_13 | output | TCELL44:OUT.4.TMIN |
| STATUS_ADC2_14 | output | TCELL44:OUT.28.TMIN |
| STATUS_ADC2_15 | output | TCELL45:OUT.4.TMIN |
| STATUS_ADC2_16 | output | TCELL45:OUT.28.TMIN |
| STATUS_ADC2_17 | output | TCELL46:OUT.4.TMIN |
| STATUS_ADC2_18 | output | TCELL46:OUT.28.TMIN |
| STATUS_ADC2_19 | output | TCELL47:OUT.4.TMIN |
| STATUS_ADC2_2 | output | TCELL38:OUT.28.TMIN |
| STATUS_ADC2_20 | output | TCELL47:OUT.28.TMIN |
| STATUS_ADC2_21 | output | TCELL48:OUT.4.TMIN |
| STATUS_ADC2_22 | output | TCELL48:OUT.28.TMIN |
| STATUS_ADC2_23 | output | TCELL49:OUT.4.TMIN |
| STATUS_ADC2_3 | output | TCELL39:OUT.4.TMIN |
| STATUS_ADC2_4 | output | TCELL39:OUT.28.TMIN |
| STATUS_ADC2_5 | output | TCELL40:OUT.4.TMIN |
| STATUS_ADC2_6 | output | TCELL40:OUT.28.TMIN |
| STATUS_ADC2_7 | output | TCELL41:OUT.4.TMIN |
| STATUS_ADC2_8 | output | TCELL41:OUT.28.TMIN |
| STATUS_ADC2_9 | output | TCELL42:OUT.4.TMIN |
| STATUS_ADC3_0 | output | TCELL49:OUT.28.TMIN |
| STATUS_ADC3_1 | output | TCELL50:OUT.4.TMIN |
| STATUS_ADC3_10 | output | TCELL54:OUT.28.TMIN |
| STATUS_ADC3_11 | output | TCELL55:OUT.4.TMIN |
| STATUS_ADC3_12 | output | TCELL55:OUT.28.TMIN |
| STATUS_ADC3_13 | output | TCELL56:OUT.4.TMIN |
| STATUS_ADC3_14 | output | TCELL56:OUT.28.TMIN |
| STATUS_ADC3_15 | output | TCELL57:OUT.4.TMIN |
| STATUS_ADC3_16 | output | TCELL57:OUT.28.TMIN |
| STATUS_ADC3_17 | output | TCELL58:OUT.4.TMIN |
| STATUS_ADC3_18 | output | TCELL58:OUT.28.TMIN |
| STATUS_ADC3_19 | output | TCELL59:OUT.4.TMIN |
| STATUS_ADC3_2 | output | TCELL50:OUT.28.TMIN |
| STATUS_ADC3_20 | output | TCELL59:OUT.12.TMIN |
| STATUS_ADC3_21 | output | TCELL59:OUT.16.TMIN |
| STATUS_ADC3_22 | output | TCELL59:OUT.20.TMIN |
| STATUS_ADC3_23 | output | TCELL59:OUT.24.TMIN |
| STATUS_ADC3_3 | output | TCELL51:OUT.4.TMIN |
| STATUS_ADC3_4 | output | TCELL51:OUT.28.TMIN |
| STATUS_ADC3_5 | output | TCELL52:OUT.4.TMIN |
| STATUS_ADC3_6 | output | TCELL52:OUT.28.TMIN |
| STATUS_ADC3_7 | output | TCELL53:OUT.4.TMIN |
| STATUS_ADC3_8 | output | TCELL53:OUT.28.TMIN |
| STATUS_ADC3_9 | output | TCELL54:OUT.4.TMIN |
| STATUS_COMMON0 | output | TCELL22:OUT.28.TMIN |
| STATUS_COMMON1 | output | TCELL23:OUT.4.TMIN |
| STATUS_COMMON10 | output | TCELL29:OUT.26.TMIN |
| STATUS_COMMON11 | output | TCELL29:OUT.30.TMIN |
| STATUS_COMMON12 | output | TCELL30:OUT.0.TMIN |
| STATUS_COMMON13 | output | TCELL30:OUT.2.TMIN |
| STATUS_COMMON14 | output | TCELL30:OUT.6.TMIN |
| STATUS_COMMON15 | output | TCELL30:OUT.8.TMIN |
| STATUS_COMMON16 | output | TCELL32:OUT.0.TMIN |
| STATUS_COMMON17 | output | TCELL34:OUT.4.TMIN |
| STATUS_COMMON18 | output | TCELL34:OUT.28.TMIN |
| STATUS_COMMON19 | output | TCELL35:OUT.4.TMIN |
| STATUS_COMMON2 | output | TCELL23:OUT.28.TMIN |
| STATUS_COMMON20 | output | TCELL35:OUT.28.TMIN |
| STATUS_COMMON21 | output | TCELL36:OUT.4.TMIN |
| STATUS_COMMON22 | output | TCELL36:OUT.28.TMIN |
| STATUS_COMMON23 | output | TCELL37:OUT.28.TMIN |
| STATUS_COMMON3 | output | TCELL24:OUT.4.TMIN |
| STATUS_COMMON4 | output | TCELL24:OUT.28.TMIN |
| STATUS_COMMON5 | output | TCELL25:OUT.4.TMIN |
| STATUS_COMMON6 | output | TCELL26:OUT.0.TMIN |
| STATUS_COMMON7 | output | TCELL27:OUT.0.TMIN |
| STATUS_COMMON8 | output | TCELL29:OUT.0.TMIN |
| STATUS_COMMON9 | output | TCELL29:OUT.24.TMIN |
| TEST_SCAN_CLK0 | input | TCELL3:IMUX.CTRL.5 |
| TEST_SCAN_CLK1 | input | TCELL17:IMUX.CTRL.5 |
| TEST_SCAN_CLK2 | input | TCELL27:IMUX.CTRL.5 |
| TEST_SCAN_CLK3 | input | TCELL41:IMUX.CTRL.5 |
| TEST_SCAN_CLK4 | input | TCELL54:IMUX.CTRL.5 |
| TEST_SCAN_CTRL0 | input | TCELL22:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL1 | input | TCELL22:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL10 | input | TCELL35:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL11 | input | TCELL35:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL12 | input | TCELL36:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL13 | input | TCELL36:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL14 | input | TCELL37:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL15 | input | TCELL37:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL2 | input | TCELL23:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL3 | input | TCELL23:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL4 | input | TCELL24:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL5 | input | TCELL24:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL6 | input | TCELL25:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL7 | input | TCELL25:IMUX.IMUX.36.DELAY |
| TEST_SCAN_CTRL8 | input | TCELL34:IMUX.IMUX.26.DELAY |
| TEST_SCAN_CTRL9 | input | TCELL34:IMUX.IMUX.36.DELAY |
| TEST_SCAN_MODE_B | input | TCELL31:IMUX.IMUX.36.DELAY |
| TEST_SCAN_RESET | input | TCELL28:IMUX.IMUX.34.DELAY |
| TEST_SE_B | input | TCELL28:IMUX.IMUX.36.DELAY |
| TEST_SI0 | input | TCELL0:IMUX.IMUX.17.DELAY |
| TEST_SI1 | input | TCELL0:IMUX.IMUX.22.DELAY |
| TEST_SI10 | input | TCELL2:IMUX.IMUX.17.DELAY |
| TEST_SI100 | input | TCELL20:IMUX.IMUX.17.DELAY |
| TEST_SI101 | input | TCELL20:IMUX.IMUX.22.DELAY |
| TEST_SI102 | input | TCELL20:IMUX.IMUX.7.DELAY |
| TEST_SI103 | input | TCELL20:IMUX.IMUX.38.DELAY |
| TEST_SI104 | input | TCELL20:IMUX.IMUX.47.DELAY |
| TEST_SI105 | input | TCELL21:IMUX.IMUX.17.DELAY |
| TEST_SI106 | input | TCELL21:IMUX.IMUX.22.DELAY |
| TEST_SI107 | input | TCELL21:IMUX.IMUX.7.DELAY |
| TEST_SI108 | input | TCELL21:IMUX.IMUX.38.DELAY |
| TEST_SI109 | input | TCELL21:IMUX.IMUX.47.DELAY |
| TEST_SI11 | input | TCELL2:IMUX.IMUX.22.DELAY |
| TEST_SI110 | input | TCELL22:IMUX.IMUX.17.DELAY |
| TEST_SI111 | input | TCELL22:IMUX.IMUX.22.DELAY |
| TEST_SI112 | input | TCELL22:IMUX.IMUX.7.DELAY |
| TEST_SI113 | input | TCELL22:IMUX.IMUX.38.DELAY |
| TEST_SI114 | input | TCELL22:IMUX.IMUX.47.DELAY |
| TEST_SI115 | input | TCELL23:IMUX.IMUX.17.DELAY |
| TEST_SI116 | input | TCELL23:IMUX.IMUX.22.DELAY |
| TEST_SI117 | input | TCELL23:IMUX.IMUX.7.DELAY |
| TEST_SI118 | input | TCELL23:IMUX.IMUX.38.DELAY |
| TEST_SI119 | input | TCELL23:IMUX.IMUX.47.DELAY |
| TEST_SI12 | input | TCELL2:IMUX.IMUX.7.DELAY |
| TEST_SI120 | input | TCELL24:IMUX.IMUX.17.DELAY |
| TEST_SI121 | input | TCELL24:IMUX.IMUX.22.DELAY |
| TEST_SI122 | input | TCELL24:IMUX.IMUX.7.DELAY |
| TEST_SI123 | input | TCELL24:IMUX.IMUX.38.DELAY |
| TEST_SI124 | input | TCELL24:IMUX.IMUX.47.DELAY |
| TEST_SI125 | input | TCELL25:IMUX.IMUX.17.DELAY |
| TEST_SI126 | input | TCELL25:IMUX.IMUX.22.DELAY |
| TEST_SI127 | input | TCELL25:IMUX.IMUX.7.DELAY |
| TEST_SI128 | input | TCELL25:IMUX.IMUX.38.DELAY |
| TEST_SI129 | input | TCELL25:IMUX.IMUX.47.DELAY |
| TEST_SI13 | input | TCELL2:IMUX.IMUX.38.DELAY |
| TEST_SI130 | input | TCELL26:IMUX.IMUX.17.DELAY |
| TEST_SI131 | input | TCELL26:IMUX.IMUX.22.DELAY |
| TEST_SI132 | input | TCELL26:IMUX.IMUX.7.DELAY |
| TEST_SI133 | input | TCELL26:IMUX.IMUX.38.DELAY |
| TEST_SI134 | input | TCELL26:IMUX.IMUX.47.DELAY |
| TEST_SI135 | input | TCELL27:IMUX.IMUX.17.DELAY |
| TEST_SI136 | input | TCELL27:IMUX.IMUX.22.DELAY |
| TEST_SI137 | input | TCELL27:IMUX.IMUX.24.DELAY |
| TEST_SI138 | input | TCELL27:IMUX.IMUX.7.DELAY |
| TEST_SI139 | input | TCELL27:IMUX.IMUX.32.DELAY |
| TEST_SI14 | input | TCELL2:IMUX.IMUX.47.DELAY |
| TEST_SI140 | input | TCELL27:IMUX.IMUX.38.DELAY |
| TEST_SI141 | input | TCELL27:IMUX.IMUX.43.DELAY |
| TEST_SI142 | input | TCELL27:IMUX.IMUX.47.DELAY |
| TEST_SI143 | input | TCELL28:IMUX.IMUX.17.DELAY |
| TEST_SI144 | input | TCELL28:IMUX.IMUX.18.DELAY |
| TEST_SI145 | input | TCELL28:IMUX.IMUX.22.DELAY |
| TEST_SI146 | input | TCELL28:IMUX.IMUX.7.DELAY |
| TEST_SI147 | input | TCELL28:IMUX.IMUX.38.DELAY |
| TEST_SI148 | input | TCELL28:IMUX.IMUX.43.DELAY |
| TEST_SI149 | input | TCELL28:IMUX.IMUX.47.DELAY |
| TEST_SI15 | input | TCELL3:IMUX.IMUX.17.DELAY |
| TEST_SI150 | input | TCELL31:IMUX.IMUX.17.DELAY |
| TEST_SI151 | input | TCELL31:IMUX.IMUX.18.DELAY |
| TEST_SI152 | input | TCELL31:IMUX.IMUX.22.DELAY |
| TEST_SI153 | input | TCELL31:IMUX.IMUX.7.DELAY |
| TEST_SI154 | input | TCELL31:IMUX.IMUX.32.DELAY |
| TEST_SI155 | input | TCELL31:IMUX.IMUX.38.DELAY |
| TEST_SI156 | input | TCELL31:IMUX.IMUX.43.DELAY |
| TEST_SI157 | input | TCELL31:IMUX.IMUX.47.DELAY |
| TEST_SI158 | input | TCELL32:IMUX.IMUX.17.DELAY |
| TEST_SI159 | input | TCELL32:IMUX.IMUX.22.DELAY |
| TEST_SI16 | input | TCELL3:IMUX.IMUX.22.DELAY |
| TEST_SI160 | input | TCELL32:IMUX.IMUX.24.DELAY |
| TEST_SI161 | input | TCELL32:IMUX.IMUX.7.DELAY |
| TEST_SI162 | input | TCELL32:IMUX.IMUX.38.DELAY |
| TEST_SI163 | input | TCELL32:IMUX.IMUX.43.DELAY |
| TEST_SI164 | input | TCELL32:IMUX.IMUX.47.DELAY |
| TEST_SI165 | input | TCELL33:IMUX.IMUX.17.DELAY |
| TEST_SI166 | input | TCELL33:IMUX.IMUX.22.DELAY |
| TEST_SI167 | input | TCELL33:IMUX.IMUX.7.DELAY |
| TEST_SI168 | input | TCELL33:IMUX.IMUX.38.DELAY |
| TEST_SI169 | input | TCELL33:IMUX.IMUX.47.DELAY |
| TEST_SI17 | input | TCELL3:IMUX.IMUX.7.DELAY |
| TEST_SI170 | input | TCELL34:IMUX.IMUX.17.DELAY |
| TEST_SI171 | input | TCELL34:IMUX.IMUX.22.DELAY |
| TEST_SI172 | input | TCELL34:IMUX.IMUX.7.DELAY |
| TEST_SI173 | input | TCELL34:IMUX.IMUX.38.DELAY |
| TEST_SI174 | input | TCELL34:IMUX.IMUX.47.DELAY |
| TEST_SI175 | input | TCELL35:IMUX.IMUX.17.DELAY |
| TEST_SI176 | input | TCELL35:IMUX.IMUX.22.DELAY |
| TEST_SI177 | input | TCELL35:IMUX.IMUX.7.DELAY |
| TEST_SI178 | input | TCELL35:IMUX.IMUX.38.DELAY |
| TEST_SI179 | input | TCELL35:IMUX.IMUX.47.DELAY |
| TEST_SI18 | input | TCELL3:IMUX.IMUX.38.DELAY |
| TEST_SI180 | input | TCELL36:IMUX.IMUX.17.DELAY |
| TEST_SI181 | input | TCELL36:IMUX.IMUX.22.DELAY |
| TEST_SI182 | input | TCELL36:IMUX.IMUX.7.DELAY |
| TEST_SI183 | input | TCELL36:IMUX.IMUX.38.DELAY |
| TEST_SI184 | input | TCELL36:IMUX.IMUX.47.DELAY |
| TEST_SI185 | input | TCELL37:IMUX.IMUX.17.DELAY |
| TEST_SI186 | input | TCELL37:IMUX.IMUX.22.DELAY |
| TEST_SI187 | input | TCELL37:IMUX.IMUX.7.DELAY |
| TEST_SI188 | input | TCELL37:IMUX.IMUX.38.DELAY |
| TEST_SI189 | input | TCELL37:IMUX.IMUX.47.DELAY |
| TEST_SI19 | input | TCELL3:IMUX.IMUX.47.DELAY |
| TEST_SI190 | input | TCELL38:IMUX.IMUX.17.DELAY |
| TEST_SI191 | input | TCELL38:IMUX.IMUX.22.DELAY |
| TEST_SI192 | input | TCELL38:IMUX.IMUX.7.DELAY |
| TEST_SI193 | input | TCELL38:IMUX.IMUX.38.DELAY |
| TEST_SI194 | input | TCELL38:IMUX.IMUX.47.DELAY |
| TEST_SI195 | input | TCELL39:IMUX.IMUX.17.DELAY |
| TEST_SI196 | input | TCELL39:IMUX.IMUX.22.DELAY |
| TEST_SI197 | input | TCELL39:IMUX.IMUX.7.DELAY |
| TEST_SI198 | input | TCELL39:IMUX.IMUX.38.DELAY |
| TEST_SI199 | input | TCELL39:IMUX.IMUX.47.DELAY |
| TEST_SI2 | input | TCELL0:IMUX.IMUX.7.DELAY |
| TEST_SI20 | input | TCELL4:IMUX.IMUX.17.DELAY |
| TEST_SI200 | input | TCELL40:IMUX.IMUX.17.DELAY |
| TEST_SI201 | input | TCELL40:IMUX.IMUX.22.DELAY |
| TEST_SI202 | input | TCELL40:IMUX.IMUX.7.DELAY |
| TEST_SI203 | input | TCELL40:IMUX.IMUX.38.DELAY |
| TEST_SI204 | input | TCELL40:IMUX.IMUX.47.DELAY |
| TEST_SI205 | input | TCELL41:IMUX.IMUX.17.DELAY |
| TEST_SI206 | input | TCELL41:IMUX.IMUX.22.DELAY |
| TEST_SI207 | input | TCELL41:IMUX.IMUX.7.DELAY |
| TEST_SI208 | input | TCELL41:IMUX.IMUX.38.DELAY |
| TEST_SI209 | input | TCELL41:IMUX.IMUX.47.DELAY |
| TEST_SI21 | input | TCELL4:IMUX.IMUX.22.DELAY |
| TEST_SI210 | input | TCELL42:IMUX.IMUX.17.DELAY |
| TEST_SI211 | input | TCELL42:IMUX.IMUX.22.DELAY |
| TEST_SI212 | input | TCELL42:IMUX.IMUX.7.DELAY |
| TEST_SI213 | input | TCELL42:IMUX.IMUX.38.DELAY |
| TEST_SI214 | input | TCELL42:IMUX.IMUX.47.DELAY |
| TEST_SI215 | input | TCELL43:IMUX.IMUX.17.DELAY |
| TEST_SI216 | input | TCELL43:IMUX.IMUX.22.DELAY |
| TEST_SI217 | input | TCELL43:IMUX.IMUX.7.DELAY |
| TEST_SI218 | input | TCELL43:IMUX.IMUX.38.DELAY |
| TEST_SI219 | input | TCELL43:IMUX.IMUX.47.DELAY |
| TEST_SI22 | input | TCELL4:IMUX.IMUX.7.DELAY |
| TEST_SI220 | input | TCELL44:IMUX.IMUX.17.DELAY |
| TEST_SI221 | input | TCELL44:IMUX.IMUX.22.DELAY |
| TEST_SI222 | input | TCELL44:IMUX.IMUX.7.DELAY |
| TEST_SI223 | input | TCELL44:IMUX.IMUX.38.DELAY |
| TEST_SI224 | input | TCELL44:IMUX.IMUX.47.DELAY |
| TEST_SI225 | input | TCELL45:IMUX.IMUX.17.DELAY |
| TEST_SI226 | input | TCELL45:IMUX.IMUX.22.DELAY |
| TEST_SI227 | input | TCELL45:IMUX.IMUX.7.DELAY |
| TEST_SI228 | input | TCELL45:IMUX.IMUX.38.DELAY |
| TEST_SI229 | input | TCELL45:IMUX.IMUX.47.DELAY |
| TEST_SI23 | input | TCELL4:IMUX.IMUX.38.DELAY |
| TEST_SI230 | input | TCELL46:IMUX.IMUX.17.DELAY |
| TEST_SI231 | input | TCELL46:IMUX.IMUX.22.DELAY |
| TEST_SI232 | input | TCELL46:IMUX.IMUX.7.DELAY |
| TEST_SI233 | input | TCELL46:IMUX.IMUX.38.DELAY |
| TEST_SI234 | input | TCELL46:IMUX.IMUX.47.DELAY |
| TEST_SI235 | input | TCELL47:IMUX.IMUX.17.DELAY |
| TEST_SI236 | input | TCELL47:IMUX.IMUX.22.DELAY |
| TEST_SI237 | input | TCELL47:IMUX.IMUX.7.DELAY |
| TEST_SI238 | input | TCELL47:IMUX.IMUX.38.DELAY |
| TEST_SI239 | input | TCELL47:IMUX.IMUX.47.DELAY |
| TEST_SI24 | input | TCELL4:IMUX.IMUX.47.DELAY |
| TEST_SI240 | input | TCELL48:IMUX.IMUX.17.DELAY |
| TEST_SI241 | input | TCELL48:IMUX.IMUX.22.DELAY |
| TEST_SI242 | input | TCELL48:IMUX.IMUX.7.DELAY |
| TEST_SI243 | input | TCELL48:IMUX.IMUX.38.DELAY |
| TEST_SI244 | input | TCELL48:IMUX.IMUX.47.DELAY |
| TEST_SI245 | input | TCELL49:IMUX.IMUX.17.DELAY |
| TEST_SI246 | input | TCELL49:IMUX.IMUX.22.DELAY |
| TEST_SI247 | input | TCELL49:IMUX.IMUX.7.DELAY |
| TEST_SI248 | input | TCELL49:IMUX.IMUX.38.DELAY |
| TEST_SI249 | input | TCELL49:IMUX.IMUX.47.DELAY |
| TEST_SI25 | input | TCELL5:IMUX.IMUX.17.DELAY |
| TEST_SI250 | input | TCELL50:IMUX.IMUX.17.DELAY |
| TEST_SI251 | input | TCELL50:IMUX.IMUX.22.DELAY |
| TEST_SI252 | input | TCELL50:IMUX.IMUX.7.DELAY |
| TEST_SI253 | input | TCELL50:IMUX.IMUX.38.DELAY |
| TEST_SI254 | input | TCELL50:IMUX.IMUX.47.DELAY |
| TEST_SI255 | input | TCELL51:IMUX.IMUX.17.DELAY |
| TEST_SI256 | input | TCELL51:IMUX.IMUX.22.DELAY |
| TEST_SI257 | input | TCELL51:IMUX.IMUX.7.DELAY |
| TEST_SI258 | input | TCELL51:IMUX.IMUX.38.DELAY |
| TEST_SI259 | input | TCELL51:IMUX.IMUX.47.DELAY |
| TEST_SI26 | input | TCELL5:IMUX.IMUX.22.DELAY |
| TEST_SI260 | input | TCELL52:IMUX.IMUX.17.DELAY |
| TEST_SI261 | input | TCELL52:IMUX.IMUX.22.DELAY |
| TEST_SI262 | input | TCELL52:IMUX.IMUX.7.DELAY |
| TEST_SI263 | input | TCELL52:IMUX.IMUX.38.DELAY |
| TEST_SI264 | input | TCELL52:IMUX.IMUX.47.DELAY |
| TEST_SI265 | input | TCELL53:IMUX.IMUX.17.DELAY |
| TEST_SI266 | input | TCELL53:IMUX.IMUX.22.DELAY |
| TEST_SI267 | input | TCELL53:IMUX.IMUX.7.DELAY |
| TEST_SI268 | input | TCELL53:IMUX.IMUX.38.DELAY |
| TEST_SI269 | input | TCELL53:IMUX.IMUX.47.DELAY |
| TEST_SI27 | input | TCELL5:IMUX.IMUX.7.DELAY |
| TEST_SI270 | input | TCELL54:IMUX.IMUX.17.DELAY |
| TEST_SI271 | input | TCELL54:IMUX.IMUX.22.DELAY |
| TEST_SI272 | input | TCELL54:IMUX.IMUX.7.DELAY |
| TEST_SI273 | input | TCELL54:IMUX.IMUX.38.DELAY |
| TEST_SI274 | input | TCELL54:IMUX.IMUX.47.DELAY |
| TEST_SI275 | input | TCELL55:IMUX.IMUX.17.DELAY |
| TEST_SI276 | input | TCELL55:IMUX.IMUX.22.DELAY |
| TEST_SI277 | input | TCELL55:IMUX.IMUX.7.DELAY |
| TEST_SI278 | input | TCELL55:IMUX.IMUX.38.DELAY |
| TEST_SI279 | input | TCELL55:IMUX.IMUX.47.DELAY |
| TEST_SI28 | input | TCELL5:IMUX.IMUX.38.DELAY |
| TEST_SI280 | input | TCELL56:IMUX.IMUX.17.DELAY |
| TEST_SI281 | input | TCELL56:IMUX.IMUX.22.DELAY |
| TEST_SI282 | input | TCELL56:IMUX.IMUX.7.DELAY |
| TEST_SI283 | input | TCELL56:IMUX.IMUX.38.DELAY |
| TEST_SI284 | input | TCELL56:IMUX.IMUX.47.DELAY |
| TEST_SI285 | input | TCELL57:IMUX.IMUX.17.DELAY |
| TEST_SI286 | input | TCELL57:IMUX.IMUX.22.DELAY |
| TEST_SI287 | input | TCELL57:IMUX.IMUX.7.DELAY |
| TEST_SI288 | input | TCELL57:IMUX.IMUX.38.DELAY |
| TEST_SI289 | input | TCELL57:IMUX.IMUX.47.DELAY |
| TEST_SI29 | input | TCELL5:IMUX.IMUX.47.DELAY |
| TEST_SI290 | input | TCELL58:IMUX.IMUX.17.DELAY |
| TEST_SI291 | input | TCELL58:IMUX.IMUX.22.DELAY |
| TEST_SI292 | input | TCELL58:IMUX.IMUX.7.DELAY |
| TEST_SI293 | input | TCELL58:IMUX.IMUX.38.DELAY |
| TEST_SI294 | input | TCELL58:IMUX.IMUX.47.DELAY |
| TEST_SI295 | input | TCELL59:IMUX.IMUX.17.DELAY |
| TEST_SI296 | input | TCELL59:IMUX.IMUX.22.DELAY |
| TEST_SI297 | input | TCELL59:IMUX.IMUX.7.DELAY |
| TEST_SI298 | input | TCELL59:IMUX.IMUX.38.DELAY |
| TEST_SI299 | input | TCELL59:IMUX.IMUX.47.DELAY |
| TEST_SI3 | input | TCELL0:IMUX.IMUX.38.DELAY |
| TEST_SI30 | input | TCELL6:IMUX.IMUX.17.DELAY |
| TEST_SI31 | input | TCELL6:IMUX.IMUX.22.DELAY |
| TEST_SI32 | input | TCELL6:IMUX.IMUX.7.DELAY |
| TEST_SI33 | input | TCELL6:IMUX.IMUX.38.DELAY |
| TEST_SI34 | input | TCELL6:IMUX.IMUX.47.DELAY |
| TEST_SI35 | input | TCELL7:IMUX.IMUX.17.DELAY |
| TEST_SI36 | input | TCELL7:IMUX.IMUX.22.DELAY |
| TEST_SI37 | input | TCELL7:IMUX.IMUX.7.DELAY |
| TEST_SI38 | input | TCELL7:IMUX.IMUX.38.DELAY |
| TEST_SI39 | input | TCELL7:IMUX.IMUX.47.DELAY |
| TEST_SI4 | input | TCELL0:IMUX.IMUX.47.DELAY |
| TEST_SI40 | input | TCELL8:IMUX.IMUX.17.DELAY |
| TEST_SI41 | input | TCELL8:IMUX.IMUX.22.DELAY |
| TEST_SI42 | input | TCELL8:IMUX.IMUX.7.DELAY |
| TEST_SI43 | input | TCELL8:IMUX.IMUX.38.DELAY |
| TEST_SI44 | input | TCELL8:IMUX.IMUX.47.DELAY |
| TEST_SI45 | input | TCELL9:IMUX.IMUX.17.DELAY |
| TEST_SI46 | input | TCELL9:IMUX.IMUX.22.DELAY |
| TEST_SI47 | input | TCELL9:IMUX.IMUX.7.DELAY |
| TEST_SI48 | input | TCELL9:IMUX.IMUX.38.DELAY |
| TEST_SI49 | input | TCELL9:IMUX.IMUX.47.DELAY |
| TEST_SI5 | input | TCELL1:IMUX.IMUX.17.DELAY |
| TEST_SI50 | input | TCELL10:IMUX.IMUX.17.DELAY |
| TEST_SI51 | input | TCELL10:IMUX.IMUX.22.DELAY |
| TEST_SI52 | input | TCELL10:IMUX.IMUX.7.DELAY |
| TEST_SI53 | input | TCELL10:IMUX.IMUX.38.DELAY |
| TEST_SI54 | input | TCELL10:IMUX.IMUX.47.DELAY |
| TEST_SI55 | input | TCELL11:IMUX.IMUX.17.DELAY |
| TEST_SI56 | input | TCELL11:IMUX.IMUX.22.DELAY |
| TEST_SI57 | input | TCELL11:IMUX.IMUX.7.DELAY |
| TEST_SI58 | input | TCELL11:IMUX.IMUX.38.DELAY |
| TEST_SI59 | input | TCELL11:IMUX.IMUX.47.DELAY |
| TEST_SI6 | input | TCELL1:IMUX.IMUX.22.DELAY |
| TEST_SI60 | input | TCELL12:IMUX.IMUX.17.DELAY |
| TEST_SI61 | input | TCELL12:IMUX.IMUX.22.DELAY |
| TEST_SI62 | input | TCELL12:IMUX.IMUX.7.DELAY |
| TEST_SI63 | input | TCELL12:IMUX.IMUX.38.DELAY |
| TEST_SI64 | input | TCELL12:IMUX.IMUX.47.DELAY |
| TEST_SI65 | input | TCELL13:IMUX.IMUX.17.DELAY |
| TEST_SI66 | input | TCELL13:IMUX.IMUX.22.DELAY |
| TEST_SI67 | input | TCELL13:IMUX.IMUX.7.DELAY |
| TEST_SI68 | input | TCELL13:IMUX.IMUX.38.DELAY |
| TEST_SI69 | input | TCELL13:IMUX.IMUX.47.DELAY |
| TEST_SI7 | input | TCELL1:IMUX.IMUX.7.DELAY |
| TEST_SI70 | input | TCELL14:IMUX.IMUX.17.DELAY |
| TEST_SI71 | input | TCELL14:IMUX.IMUX.22.DELAY |
| TEST_SI72 | input | TCELL14:IMUX.IMUX.7.DELAY |
| TEST_SI73 | input | TCELL14:IMUX.IMUX.38.DELAY |
| TEST_SI74 | input | TCELL14:IMUX.IMUX.47.DELAY |
| TEST_SI75 | input | TCELL15:IMUX.IMUX.17.DELAY |
| TEST_SI76 | input | TCELL15:IMUX.IMUX.22.DELAY |
| TEST_SI77 | input | TCELL15:IMUX.IMUX.7.DELAY |
| TEST_SI78 | input | TCELL15:IMUX.IMUX.38.DELAY |
| TEST_SI79 | input | TCELL15:IMUX.IMUX.47.DELAY |
| TEST_SI8 | input | TCELL1:IMUX.IMUX.38.DELAY |
| TEST_SI80 | input | TCELL16:IMUX.IMUX.17.DELAY |
| TEST_SI81 | input | TCELL16:IMUX.IMUX.22.DELAY |
| TEST_SI82 | input | TCELL16:IMUX.IMUX.7.DELAY |
| TEST_SI83 | input | TCELL16:IMUX.IMUX.38.DELAY |
| TEST_SI84 | input | TCELL16:IMUX.IMUX.47.DELAY |
| TEST_SI85 | input | TCELL17:IMUX.IMUX.17.DELAY |
| TEST_SI86 | input | TCELL17:IMUX.IMUX.22.DELAY |
| TEST_SI87 | input | TCELL17:IMUX.IMUX.7.DELAY |
| TEST_SI88 | input | TCELL17:IMUX.IMUX.38.DELAY |
| TEST_SI89 | input | TCELL17:IMUX.IMUX.47.DELAY |
| TEST_SI9 | input | TCELL1:IMUX.IMUX.47.DELAY |
| TEST_SI90 | input | TCELL18:IMUX.IMUX.17.DELAY |
| TEST_SI91 | input | TCELL18:IMUX.IMUX.22.DELAY |
| TEST_SI92 | input | TCELL18:IMUX.IMUX.7.DELAY |
| TEST_SI93 | input | TCELL18:IMUX.IMUX.38.DELAY |
| TEST_SI94 | input | TCELL18:IMUX.IMUX.47.DELAY |
| TEST_SI95 | input | TCELL19:IMUX.IMUX.17.DELAY |
| TEST_SI96 | input | TCELL19:IMUX.IMUX.22.DELAY |
| TEST_SI97 | input | TCELL19:IMUX.IMUX.7.DELAY |
| TEST_SI98 | input | TCELL19:IMUX.IMUX.38.DELAY |
| TEST_SI99 | input | TCELL19:IMUX.IMUX.47.DELAY |
| TEST_SO0 | output | TCELL0:OUT.3.TMIN |
| TEST_SO1 | output | TCELL0:OUT.13.TMIN |
| TEST_SO10 | output | TCELL2:OUT.3.TMIN |
| TEST_SO100 | output | TCELL20:OUT.3.TMIN |
| TEST_SO101 | output | TCELL20:OUT.11.TMIN |
| TEST_SO102 | output | TCELL20:OUT.21.TMIN |
| TEST_SO103 | output | TCELL20:OUT.27.TMIN |
| TEST_SO104 | output | TCELL20:OUT.31.TMIN |
| TEST_SO105 | output | TCELL21:OUT.3.TMIN |
| TEST_SO106 | output | TCELL21:OUT.11.TMIN |
| TEST_SO107 | output | TCELL21:OUT.21.TMIN |
| TEST_SO108 | output | TCELL21:OUT.27.TMIN |
| TEST_SO109 | output | TCELL21:OUT.31.TMIN |
| TEST_SO11 | output | TCELL2:OUT.13.TMIN |
| TEST_SO110 | output | TCELL22:OUT.3.TMIN |
| TEST_SO111 | output | TCELL22:OUT.11.TMIN |
| TEST_SO112 | output | TCELL22:OUT.21.TMIN |
| TEST_SO113 | output | TCELL22:OUT.27.TMIN |
| TEST_SO114 | output | TCELL22:OUT.31.TMIN |
| TEST_SO115 | output | TCELL23:OUT.3.TMIN |
| TEST_SO116 | output | TCELL23:OUT.11.TMIN |
| TEST_SO117 | output | TCELL23:OUT.21.TMIN |
| TEST_SO118 | output | TCELL23:OUT.27.TMIN |
| TEST_SO119 | output | TCELL23:OUT.31.TMIN |
| TEST_SO12 | output | TCELL2:OUT.21.TMIN |
| TEST_SO120 | output | TCELL24:OUT.3.TMIN |
| TEST_SO121 | output | TCELL24:OUT.11.TMIN |
| TEST_SO122 | output | TCELL24:OUT.21.TMIN |
| TEST_SO123 | output | TCELL24:OUT.27.TMIN |
| TEST_SO124 | output | TCELL24:OUT.31.TMIN |
| TEST_SO125 | output | TCELL25:OUT.3.TMIN |
| TEST_SO126 | output | TCELL25:OUT.11.TMIN |
| TEST_SO127 | output | TCELL25:OUT.21.TMIN |
| TEST_SO128 | output | TCELL25:OUT.27.TMIN |
| TEST_SO129 | output | TCELL25:OUT.31.TMIN |
| TEST_SO13 | output | TCELL2:OUT.27.TMIN |
| TEST_SO130 | output | TCELL26:OUT.3.TMIN |
| TEST_SO131 | output | TCELL26:OUT.11.TMIN |
| TEST_SO132 | output | TCELL26:OUT.21.TMIN |
| TEST_SO133 | output | TCELL26:OUT.27.TMIN |
| TEST_SO134 | output | TCELL26:OUT.31.TMIN |
| TEST_SO135 | output | TCELL27:OUT.3.TMIN |
| TEST_SO136 | output | TCELL27:OUT.5.TMIN |
| TEST_SO137 | output | TCELL27:OUT.11.TMIN |
| TEST_SO138 | output | TCELL27:OUT.15.TMIN |
| TEST_SO139 | output | TCELL27:OUT.21.TMIN |
| TEST_SO14 | output | TCELL2:OUT.31.TMIN |
| TEST_SO140 | output | TCELL27:OUT.27.TMIN |
| TEST_SO141 | output | TCELL27:OUT.29.TMIN |
| TEST_SO142 | output | TCELL27:OUT.31.TMIN |
| TEST_SO143 | output | TCELL28:OUT.3.TMIN |
| TEST_SO144 | output | TCELL28:OUT.11.TMIN |
| TEST_SO145 | output | TCELL28:OUT.19.TMIN |
| TEST_SO146 | output | TCELL28:OUT.21.TMIN |
| TEST_SO147 | output | TCELL28:OUT.27.TMIN |
| TEST_SO148 | output | TCELL28:OUT.29.TMIN |
| TEST_SO149 | output | TCELL28:OUT.31.TMIN |
| TEST_SO15 | output | TCELL3:OUT.3.TMIN |
| TEST_SO150 | output | TCELL31:OUT.3.TMIN |
| TEST_SO151 | output | TCELL31:OUT.11.TMIN |
| TEST_SO152 | output | TCELL31:OUT.19.TMIN |
| TEST_SO153 | output | TCELL31:OUT.21.TMIN |
| TEST_SO154 | output | TCELL31:OUT.27.TMIN |
| TEST_SO155 | output | TCELL31:OUT.29.TMIN |
| TEST_SO156 | output | TCELL31:OUT.31.TMIN |
| TEST_SO157 | output | TCELL32:OUT.3.TMIN |
| TEST_SO158 | output | TCELL32:OUT.11.TMIN |
| TEST_SO159 | output | TCELL32:OUT.13.TMIN |
| TEST_SO16 | output | TCELL3:OUT.13.TMIN |
| TEST_SO160 | output | TCELL32:OUT.21.TMIN |
| TEST_SO161 | output | TCELL32:OUT.27.TMIN |
| TEST_SO162 | output | TCELL32:OUT.31.TMIN |
| TEST_SO163 | output | TCELL33:OUT.3.TMIN |
| TEST_SO164 | output | TCELL33:OUT.11.TMIN |
| TEST_SO165 | output | TCELL33:OUT.15.TMIN |
| TEST_SO166 | output | TCELL33:OUT.21.TMIN |
| TEST_SO167 | output | TCELL33:OUT.27.TMIN |
| TEST_SO168 | output | TCELL33:OUT.31.TMIN |
| TEST_SO169 | output | TCELL34:OUT.3.TMIN |
| TEST_SO17 | output | TCELL3:OUT.21.TMIN |
| TEST_SO170 | output | TCELL34:OUT.11.TMIN |
| TEST_SO171 | output | TCELL34:OUT.21.TMIN |
| TEST_SO172 | output | TCELL34:OUT.27.TMIN |
| TEST_SO173 | output | TCELL34:OUT.31.TMIN |
| TEST_SO174 | output | TCELL35:OUT.3.TMIN |
| TEST_SO175 | output | TCELL35:OUT.11.TMIN |
| TEST_SO176 | output | TCELL35:OUT.15.TMIN |
| TEST_SO177 | output | TCELL35:OUT.21.TMIN |
| TEST_SO178 | output | TCELL35:OUT.27.TMIN |
| TEST_SO179 | output | TCELL35:OUT.31.TMIN |
| TEST_SO18 | output | TCELL3:OUT.27.TMIN |
| TEST_SO180 | output | TCELL36:OUT.3.TMIN |
| TEST_SO181 | output | TCELL36:OUT.11.TMIN |
| TEST_SO182 | output | TCELL36:OUT.21.TMIN |
| TEST_SO183 | output | TCELL36:OUT.27.TMIN |
| TEST_SO184 | output | TCELL36:OUT.31.TMIN |
| TEST_SO185 | output | TCELL37:OUT.3.TMIN |
| TEST_SO186 | output | TCELL37:OUT.11.TMIN |
| TEST_SO187 | output | TCELL37:OUT.21.TMIN |
| TEST_SO188 | output | TCELL37:OUT.27.TMIN |
| TEST_SO189 | output | TCELL37:OUT.31.TMIN |
| TEST_SO19 | output | TCELL3:OUT.31.TMIN |
| TEST_SO190 | output | TCELL38:OUT.3.TMIN |
| TEST_SO191 | output | TCELL38:OUT.11.TMIN |
| TEST_SO192 | output | TCELL38:OUT.21.TMIN |
| TEST_SO193 | output | TCELL38:OUT.27.TMIN |
| TEST_SO194 | output | TCELL38:OUT.31.TMIN |
| TEST_SO195 | output | TCELL39:OUT.3.TMIN |
| TEST_SO196 | output | TCELL39:OUT.11.TMIN |
| TEST_SO197 | output | TCELL39:OUT.21.TMIN |
| TEST_SO198 | output | TCELL39:OUT.27.TMIN |
| TEST_SO199 | output | TCELL39:OUT.31.TMIN |
| TEST_SO2 | output | TCELL0:OUT.21.TMIN |
| TEST_SO20 | output | TCELL4:OUT.3.TMIN |
| TEST_SO200 | output | TCELL40:OUT.3.TMIN |
| TEST_SO201 | output | TCELL40:OUT.11.TMIN |
| TEST_SO202 | output | TCELL40:OUT.21.TMIN |
| TEST_SO203 | output | TCELL40:OUT.27.TMIN |
| TEST_SO204 | output | TCELL40:OUT.31.TMIN |
| TEST_SO205 | output | TCELL41:OUT.3.TMIN |
| TEST_SO206 | output | TCELL41:OUT.11.TMIN |
| TEST_SO207 | output | TCELL41:OUT.21.TMIN |
| TEST_SO208 | output | TCELL41:OUT.27.TMIN |
| TEST_SO209 | output | TCELL41:OUT.31.TMIN |
| TEST_SO21 | output | TCELL4:OUT.13.TMIN |
| TEST_SO210 | output | TCELL42:OUT.3.TMIN |
| TEST_SO211 | output | TCELL42:OUT.11.TMIN |
| TEST_SO212 | output | TCELL42:OUT.21.TMIN |
| TEST_SO213 | output | TCELL42:OUT.27.TMIN |
| TEST_SO214 | output | TCELL42:OUT.31.TMIN |
| TEST_SO215 | output | TCELL43:OUT.3.TMIN |
| TEST_SO216 | output | TCELL43:OUT.11.TMIN |
| TEST_SO217 | output | TCELL43:OUT.21.TMIN |
| TEST_SO218 | output | TCELL43:OUT.27.TMIN |
| TEST_SO219 | output | TCELL43:OUT.31.TMIN |
| TEST_SO22 | output | TCELL4:OUT.21.TMIN |
| TEST_SO220 | output | TCELL44:OUT.3.TMIN |
| TEST_SO221 | output | TCELL44:OUT.11.TMIN |
| TEST_SO222 | output | TCELL44:OUT.21.TMIN |
| TEST_SO223 | output | TCELL44:OUT.27.TMIN |
| TEST_SO224 | output | TCELL44:OUT.31.TMIN |
| TEST_SO225 | output | TCELL45:OUT.3.TMIN |
| TEST_SO226 | output | TCELL45:OUT.11.TMIN |
| TEST_SO227 | output | TCELL45:OUT.21.TMIN |
| TEST_SO228 | output | TCELL45:OUT.27.TMIN |
| TEST_SO229 | output | TCELL45:OUT.31.TMIN |
| TEST_SO23 | output | TCELL4:OUT.27.TMIN |
| TEST_SO230 | output | TCELL46:OUT.3.TMIN |
| TEST_SO231 | output | TCELL46:OUT.11.TMIN |
| TEST_SO232 | output | TCELL46:OUT.21.TMIN |
| TEST_SO233 | output | TCELL46:OUT.27.TMIN |
| TEST_SO234 | output | TCELL46:OUT.31.TMIN |
| TEST_SO235 | output | TCELL47:OUT.3.TMIN |
| TEST_SO236 | output | TCELL47:OUT.11.TMIN |
| TEST_SO237 | output | TCELL47:OUT.21.TMIN |
| TEST_SO238 | output | TCELL47:OUT.27.TMIN |
| TEST_SO239 | output | TCELL47:OUT.31.TMIN |
| TEST_SO24 | output | TCELL4:OUT.31.TMIN |
| TEST_SO240 | output | TCELL48:OUT.3.TMIN |
| TEST_SO241 | output | TCELL48:OUT.11.TMIN |
| TEST_SO242 | output | TCELL48:OUT.21.TMIN |
| TEST_SO243 | output | TCELL48:OUT.27.TMIN |
| TEST_SO244 | output | TCELL48:OUT.31.TMIN |
| TEST_SO245 | output | TCELL49:OUT.3.TMIN |
| TEST_SO246 | output | TCELL49:OUT.11.TMIN |
| TEST_SO247 | output | TCELL49:OUT.21.TMIN |
| TEST_SO248 | output | TCELL49:OUT.27.TMIN |
| TEST_SO249 | output | TCELL49:OUT.31.TMIN |
| TEST_SO25 | output | TCELL5:OUT.3.TMIN |
| TEST_SO250 | output | TCELL50:OUT.3.TMIN |
| TEST_SO251 | output | TCELL50:OUT.11.TMIN |
| TEST_SO252 | output | TCELL50:OUT.21.TMIN |
| TEST_SO253 | output | TCELL50:OUT.27.TMIN |
| TEST_SO254 | output | TCELL50:OUT.31.TMIN |
| TEST_SO255 | output | TCELL51:OUT.3.TMIN |
| TEST_SO256 | output | TCELL51:OUT.11.TMIN |
| TEST_SO257 | output | TCELL51:OUT.21.TMIN |
| TEST_SO258 | output | TCELL51:OUT.27.TMIN |
| TEST_SO259 | output | TCELL51:OUT.31.TMIN |
| TEST_SO26 | output | TCELL5:OUT.13.TMIN |
| TEST_SO260 | output | TCELL52:OUT.3.TMIN |
| TEST_SO261 | output | TCELL52:OUT.11.TMIN |
| TEST_SO262 | output | TCELL52:OUT.21.TMIN |
| TEST_SO263 | output | TCELL52:OUT.27.TMIN |
| TEST_SO264 | output | TCELL52:OUT.31.TMIN |
| TEST_SO265 | output | TCELL53:OUT.3.TMIN |
| TEST_SO266 | output | TCELL53:OUT.11.TMIN |
| TEST_SO267 | output | TCELL53:OUT.21.TMIN |
| TEST_SO268 | output | TCELL53:OUT.27.TMIN |
| TEST_SO269 | output | TCELL53:OUT.31.TMIN |
| TEST_SO27 | output | TCELL5:OUT.21.TMIN |
| TEST_SO270 | output | TCELL54:OUT.3.TMIN |
| TEST_SO271 | output | TCELL54:OUT.11.TMIN |
| TEST_SO272 | output | TCELL54:OUT.21.TMIN |
| TEST_SO273 | output | TCELL54:OUT.27.TMIN |
| TEST_SO274 | output | TCELL54:OUT.31.TMIN |
| TEST_SO275 | output | TCELL55:OUT.3.TMIN |
| TEST_SO276 | output | TCELL55:OUT.11.TMIN |
| TEST_SO277 | output | TCELL55:OUT.21.TMIN |
| TEST_SO278 | output | TCELL55:OUT.27.TMIN |
| TEST_SO279 | output | TCELL55:OUT.31.TMIN |
| TEST_SO28 | output | TCELL5:OUT.27.TMIN |
| TEST_SO280 | output | TCELL56:OUT.3.TMIN |
| TEST_SO281 | output | TCELL56:OUT.11.TMIN |
| TEST_SO282 | output | TCELL56:OUT.21.TMIN |
| TEST_SO283 | output | TCELL56:OUT.27.TMIN |
| TEST_SO284 | output | TCELL56:OUT.31.TMIN |
| TEST_SO285 | output | TCELL57:OUT.3.TMIN |
| TEST_SO286 | output | TCELL57:OUT.11.TMIN |
| TEST_SO287 | output | TCELL57:OUT.21.TMIN |
| TEST_SO288 | output | TCELL57:OUT.27.TMIN |
| TEST_SO289 | output | TCELL57:OUT.31.TMIN |
| TEST_SO29 | output | TCELL5:OUT.31.TMIN |
| TEST_SO290 | output | TCELL58:OUT.3.TMIN |
| TEST_SO291 | output | TCELL58:OUT.11.TMIN |
| TEST_SO292 | output | TCELL58:OUT.21.TMIN |
| TEST_SO293 | output | TCELL58:OUT.27.TMIN |
| TEST_SO294 | output | TCELL58:OUT.31.TMIN |
| TEST_SO295 | output | TCELL59:OUT.3.TMIN |
| TEST_SO296 | output | TCELL59:OUT.11.TMIN |
| TEST_SO297 | output | TCELL59:OUT.21.TMIN |
| TEST_SO298 | output | TCELL59:OUT.27.TMIN |
| TEST_SO299 | output | TCELL59:OUT.31.TMIN |
| TEST_SO3 | output | TCELL0:OUT.27.TMIN |
| TEST_SO30 | output | TCELL6:OUT.3.TMIN |
| TEST_SO31 | output | TCELL6:OUT.13.TMIN |
| TEST_SO32 | output | TCELL6:OUT.21.TMIN |
| TEST_SO33 | output | TCELL6:OUT.27.TMIN |
| TEST_SO34 | output | TCELL6:OUT.31.TMIN |
| TEST_SO35 | output | TCELL7:OUT.3.TMIN |
| TEST_SO36 | output | TCELL7:OUT.13.TMIN |
| TEST_SO37 | output | TCELL7:OUT.21.TMIN |
| TEST_SO38 | output | TCELL7:OUT.27.TMIN |
| TEST_SO39 | output | TCELL7:OUT.31.TMIN |
| TEST_SO4 | output | TCELL0:OUT.31.TMIN |
| TEST_SO40 | output | TCELL8:OUT.3.TMIN |
| TEST_SO41 | output | TCELL8:OUT.13.TMIN |
| TEST_SO42 | output | TCELL8:OUT.21.TMIN |
| TEST_SO43 | output | TCELL8:OUT.27.TMIN |
| TEST_SO44 | output | TCELL8:OUT.31.TMIN |
| TEST_SO45 | output | TCELL9:OUT.3.TMIN |
| TEST_SO46 | output | TCELL9:OUT.13.TMIN |
| TEST_SO47 | output | TCELL9:OUT.21.TMIN |
| TEST_SO48 | output | TCELL9:OUT.27.TMIN |
| TEST_SO49 | output | TCELL9:OUT.31.TMIN |
| TEST_SO5 | output | TCELL1:OUT.3.TMIN |
| TEST_SO50 | output | TCELL10:OUT.3.TMIN |
| TEST_SO51 | output | TCELL10:OUT.13.TMIN |
| TEST_SO52 | output | TCELL10:OUT.21.TMIN |
| TEST_SO53 | output | TCELL10:OUT.27.TMIN |
| TEST_SO54 | output | TCELL10:OUT.31.TMIN |
| TEST_SO55 | output | TCELL11:OUT.3.TMIN |
| TEST_SO56 | output | TCELL11:OUT.13.TMIN |
| TEST_SO57 | output | TCELL11:OUT.21.TMIN |
| TEST_SO58 | output | TCELL11:OUT.27.TMIN |
| TEST_SO59 | output | TCELL11:OUT.31.TMIN |
| TEST_SO6 | output | TCELL1:OUT.13.TMIN |
| TEST_SO60 | output | TCELL12:OUT.3.TMIN |
| TEST_SO61 | output | TCELL12:OUT.13.TMIN |
| TEST_SO62 | output | TCELL12:OUT.21.TMIN |
| TEST_SO63 | output | TCELL12:OUT.27.TMIN |
| TEST_SO64 | output | TCELL12:OUT.31.TMIN |
| TEST_SO65 | output | TCELL13:OUT.3.TMIN |
| TEST_SO66 | output | TCELL13:OUT.13.TMIN |
| TEST_SO67 | output | TCELL13:OUT.21.TMIN |
| TEST_SO68 | output | TCELL13:OUT.27.TMIN |
| TEST_SO69 | output | TCELL13:OUT.31.TMIN |
| TEST_SO7 | output | TCELL1:OUT.21.TMIN |
| TEST_SO70 | output | TCELL14:OUT.3.TMIN |
| TEST_SO71 | output | TCELL14:OUT.13.TMIN |
| TEST_SO72 | output | TCELL14:OUT.21.TMIN |
| TEST_SO73 | output | TCELL14:OUT.27.TMIN |
| TEST_SO74 | output | TCELL14:OUT.31.TMIN |
| TEST_SO75 | output | TCELL15:OUT.3.TMIN |
| TEST_SO76 | output | TCELL15:OUT.11.TMIN |
| TEST_SO77 | output | TCELL15:OUT.21.TMIN |
| TEST_SO78 | output | TCELL15:OUT.27.TMIN |
| TEST_SO79 | output | TCELL15:OUT.31.TMIN |
| TEST_SO8 | output | TCELL1:OUT.27.TMIN |
| TEST_SO80 | output | TCELL16:OUT.3.TMIN |
| TEST_SO81 | output | TCELL16:OUT.11.TMIN |
| TEST_SO82 | output | TCELL16:OUT.21.TMIN |
| TEST_SO83 | output | TCELL16:OUT.27.TMIN |
| TEST_SO84 | output | TCELL16:OUT.31.TMIN |
| TEST_SO85 | output | TCELL17:OUT.3.TMIN |
| TEST_SO86 | output | TCELL17:OUT.11.TMIN |
| TEST_SO87 | output | TCELL17:OUT.21.TMIN |
| TEST_SO88 | output | TCELL17:OUT.27.TMIN |
| TEST_SO89 | output | TCELL17:OUT.31.TMIN |
| TEST_SO9 | output | TCELL1:OUT.31.TMIN |
| TEST_SO90 | output | TCELL18:OUT.3.TMIN |
| TEST_SO91 | output | TCELL18:OUT.11.TMIN |
| TEST_SO92 | output | TCELL18:OUT.21.TMIN |
| TEST_SO93 | output | TCELL18:OUT.27.TMIN |
| TEST_SO94 | output | TCELL18:OUT.31.TMIN |
| TEST_SO95 | output | TCELL19:OUT.3.TMIN |
| TEST_SO96 | output | TCELL19:OUT.11.TMIN |
| TEST_SO97 | output | TCELL19:OUT.21.TMIN |
| TEST_SO98 | output | TCELL19:OUT.27.TMIN |
| TEST_SO99 | output | TCELL19:OUT.31.TMIN |
| TEST_STATUS0 | output | TCELL20:OUT.17.TMIN |
| TEST_STATUS1 | output | TCELL21:OUT.17.TMIN |
| TEST_STATUS10 | output | TCELL34:OUT.17.TMIN |
| TEST_STATUS11 | output | TCELL35:OUT.17.TMIN |
| TEST_STATUS12 | output | TCELL36:OUT.17.TMIN |
| TEST_STATUS13 | output | TCELL37:OUT.17.TMIN |
| TEST_STATUS14 | output | TCELL38:OUT.17.TMIN |
| TEST_STATUS15 | output | TCELL39:OUT.17.TMIN |
| TEST_STATUS2 | output | TCELL22:OUT.17.TMIN |
| TEST_STATUS3 | output | TCELL23:OUT.17.TMIN |
| TEST_STATUS4 | output | TCELL24:OUT.17.TMIN |
| TEST_STATUS5 | output | TCELL25:OUT.17.TMIN |
| TEST_STATUS6 | output | TCELL26:OUT.17.TMIN |
| TEST_STATUS7 | output | TCELL27:OUT.17.TMIN |
| TEST_STATUS8 | output | TCELL32:OUT.17.TMIN |
| TEST_STATUS9 | output | TCELL33:OUT.17.TMIN |
Bel RCLK_GT
| Pin | Direction | Wires |
|---|
Bel VCC_GT
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:OUT.1.TMIN | RFADC.DATA_ADC0_0 |
| TCELL0:OUT.3.TMIN | RFADC.TEST_SO0 |
| TCELL0:OUT.4.TMIN | RFADC.STATUS_ADC0_0 |
| TCELL0:OUT.6.TMIN | RFADC.DATA_ADC0_1 |
| TCELL0:OUT.8.TMIN | RFADC.DATA_ADC0_2 |
| TCELL0:OUT.10.TMIN | RFADC.STATUS_ADC0_1 |
| TCELL0:OUT.12.TMIN | RFADC.DATA_ADC0_3 |
| TCELL0:OUT.13.TMIN | RFADC.TEST_SO1 |
| TCELL0:OUT.14.TMIN | RFADC.STATUS_ADC0_2 |
| TCELL0:OUT.16.TMIN | RFADC.DATA_ADC0_4 |
| TCELL0:OUT.18.TMIN | RFADC.STATUS_ADC0_3 |
| TCELL0:OUT.20.TMIN | RFADC.DATA_ADC0_5 |
| TCELL0:OUT.21.TMIN | RFADC.TEST_SO2 |
| TCELL0:OUT.22.TMIN | RFADC.DATA_ADC0_6 |
| TCELL0:OUT.24.TMIN | RFADC.DATA_ADC0_7 |
| TCELL0:OUT.26.TMIN | RFADC.DATA_ADC0_8 |
| TCELL0:OUT.27.TMIN | RFADC.TEST_SO3 |
| TCELL0:OUT.28.TMIN | RFADC.STATUS_ADC0_4 |
| TCELL0:OUT.30.TMIN | RFADC.DATA_ADC0_9 |
| TCELL0:OUT.31.TMIN | RFADC.TEST_SO4 |
| TCELL0:IMUX.IMUX.7.DELAY | RFADC.TEST_SI2 |
| TCELL0:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC0_1 |
| TCELL0:IMUX.IMUX.17.DELAY | RFADC.TEST_SI0 |
| TCELL0:IMUX.IMUX.22.DELAY | RFADC.TEST_SI1 |
| TCELL0:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC0_0 |
| TCELL0:IMUX.IMUX.38.DELAY | RFADC.TEST_SI3 |
| TCELL0:IMUX.IMUX.47.DELAY | RFADC.TEST_SI4 |
| TCELL1:OUT.1.TMIN | RFADC.DATA_ADC0_10 |
| TCELL1:OUT.3.TMIN | RFADC.TEST_SO5 |
| TCELL1:OUT.4.TMIN | RFADC.STATUS_ADC0_5 |
| TCELL1:OUT.6.TMIN | RFADC.DATA_ADC0_11 |
| TCELL1:OUT.8.TMIN | RFADC.DATA_ADC0_12 |
| TCELL1:OUT.10.TMIN | RFADC.DATA_ADC0_13 |
| TCELL1:OUT.12.TMIN | RFADC.DATA_ADC0_14 |
| TCELL1:OUT.13.TMIN | RFADC.TEST_SO6 |
| TCELL1:OUT.14.TMIN | RFADC.DATA_ADC0_15 |
| TCELL1:OUT.16.TMIN | RFADC.DATA_ADC0_16 |
| TCELL1:OUT.18.TMIN | RFADC.DATA_ADC0_17 |
| TCELL1:OUT.20.TMIN | RFADC.DATA_ADC0_18 |
| TCELL1:OUT.21.TMIN | RFADC.TEST_SO7 |
| TCELL1:OUT.22.TMIN | RFADC.DATA_ADC0_19 |
| TCELL1:OUT.24.TMIN | RFADC.DATA_ADC0_20 |
| TCELL1:OUT.26.TMIN | RFADC.DATA_ADC0_21 |
| TCELL1:OUT.27.TMIN | RFADC.TEST_SO8 |
| TCELL1:OUT.28.TMIN | RFADC.STATUS_ADC0_6 |
| TCELL1:OUT.30.TMIN | RFADC.DATA_ADC0_22 |
| TCELL1:OUT.31.TMIN | RFADC.TEST_SO9 |
| TCELL1:IMUX.IMUX.7.DELAY | RFADC.TEST_SI7 |
| TCELL1:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC0_2 |
| TCELL1:IMUX.IMUX.17.DELAY | RFADC.TEST_SI5 |
| TCELL1:IMUX.IMUX.22.DELAY | RFADC.TEST_SI6 |
| TCELL1:IMUX.IMUX.38.DELAY | RFADC.TEST_SI8 |
| TCELL1:IMUX.IMUX.47.DELAY | RFADC.TEST_SI9 |
| TCELL2:OUT.1.TMIN | RFADC.DATA_ADC0_23 |
| TCELL2:OUT.3.TMIN | RFADC.TEST_SO10 |
| TCELL2:OUT.4.TMIN | RFADC.STATUS_ADC0_7 |
| TCELL2:OUT.6.TMIN | RFADC.DATA_ADC0_24 |
| TCELL2:OUT.8.TMIN | RFADC.DATA_ADC0_25 |
| TCELL2:OUT.10.TMIN | RFADC.DATA_ADC0_26 |
| TCELL2:OUT.12.TMIN | RFADC.DATA_ADC0_27 |
| TCELL2:OUT.13.TMIN | RFADC.TEST_SO11 |
| TCELL2:OUT.14.TMIN | RFADC.DATA_ADC0_28 |
| TCELL2:OUT.16.TMIN | RFADC.DATA_ADC0_29 |
| TCELL2:OUT.18.TMIN | RFADC.DATA_ADC0_30 |
| TCELL2:OUT.20.TMIN | RFADC.DATA_ADC0_31 |
| TCELL2:OUT.21.TMIN | RFADC.TEST_SO12 |
| TCELL2:OUT.22.TMIN | RFADC.DATA_ADC0_32 |
| TCELL2:OUT.24.TMIN | RFADC.DATA_ADC0_33 |
| TCELL2:OUT.26.TMIN | RFADC.DATA_ADC0_34 |
| TCELL2:OUT.27.TMIN | RFADC.TEST_SO13 |
| TCELL2:OUT.28.TMIN | RFADC.STATUS_ADC0_8 |
| TCELL2:OUT.30.TMIN | RFADC.DATA_ADC0_35 |
| TCELL2:OUT.31.TMIN | RFADC.TEST_SO14 |
| TCELL2:IMUX.IMUX.7.DELAY | RFADC.TEST_SI12 |
| TCELL2:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC0_4 |
| TCELL2:IMUX.IMUX.17.DELAY | RFADC.TEST_SI10 |
| TCELL2:IMUX.IMUX.22.DELAY | RFADC.TEST_SI11 |
| TCELL2:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC0_3 |
| TCELL2:IMUX.IMUX.38.DELAY | RFADC.TEST_SI13 |
| TCELL2:IMUX.IMUX.47.DELAY | RFADC.TEST_SI14 |
| TCELL3:OUT.1.TMIN | RFADC.DATA_ADC0_36 |
| TCELL3:OUT.3.TMIN | RFADC.TEST_SO15 |
| TCELL3:OUT.4.TMIN | RFADC.STATUS_ADC0_9 |
| TCELL3:OUT.6.TMIN | RFADC.DATA_ADC0_37 |
| TCELL3:OUT.8.TMIN | RFADC.DATA_ADC0_38 |
| TCELL3:OUT.10.TMIN | RFADC.DATA_ADC0_39 |
| TCELL3:OUT.12.TMIN | RFADC.DATA_ADC0_40 |
| TCELL3:OUT.13.TMIN | RFADC.TEST_SO16 |
| TCELL3:OUT.14.TMIN | RFADC.DATA_ADC0_41 |
| TCELL3:OUT.16.TMIN | RFADC.DATA_ADC0_42 |
| TCELL3:OUT.18.TMIN | RFADC.DATA_ADC0_43 |
| TCELL3:OUT.20.TMIN | RFADC.DATA_ADC0_44 |
| TCELL3:OUT.21.TMIN | RFADC.TEST_SO17 |
| TCELL3:OUT.22.TMIN | RFADC.DATA_ADC0_45 |
| TCELL3:OUT.24.TMIN | RFADC.DATA_ADC0_46 |
| TCELL3:OUT.26.TMIN | RFADC.DATA_ADC0_47 |
| TCELL3:OUT.27.TMIN | RFADC.TEST_SO18 |
| TCELL3:OUT.28.TMIN | RFADC.STATUS_ADC0_10 |
| TCELL3:OUT.30.TMIN | RFADC.DATA_ADC0_48 |
| TCELL3:OUT.31.TMIN | RFADC.TEST_SO19 |
| TCELL3:IMUX.CTRL.5 | RFADC.TEST_SCAN_CLK0 |
| TCELL3:IMUX.IMUX.7.DELAY | RFADC.TEST_SI17 |
| TCELL3:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC0_5 |
| TCELL3:IMUX.IMUX.17.DELAY | RFADC.TEST_SI15 |
| TCELL3:IMUX.IMUX.22.DELAY | RFADC.TEST_SI16 |
| TCELL3:IMUX.IMUX.38.DELAY | RFADC.TEST_SI18 |
| TCELL3:IMUX.IMUX.47.DELAY | RFADC.TEST_SI19 |
| TCELL4:OUT.1.TMIN | RFADC.DATA_ADC0_49 |
| TCELL4:OUT.3.TMIN | RFADC.TEST_SO20 |
| TCELL4:OUT.4.TMIN | RFADC.STATUS_ADC0_11 |
| TCELL4:OUT.6.TMIN | RFADC.DATA_ADC0_50 |
| TCELL4:OUT.8.TMIN | RFADC.DATA_ADC0_51 |
| TCELL4:OUT.10.TMIN | RFADC.DATA_ADC0_52 |
| TCELL4:OUT.12.TMIN | RFADC.DATA_ADC0_53 |
| TCELL4:OUT.13.TMIN | RFADC.TEST_SO21 |
| TCELL4:OUT.14.TMIN | RFADC.DATA_ADC0_54 |
| TCELL4:OUT.16.TMIN | RFADC.DATA_ADC0_55 |
| TCELL4:OUT.18.TMIN | RFADC.DATA_ADC0_56 |
| TCELL4:OUT.20.TMIN | RFADC.DATA_ADC0_57 |
| TCELL4:OUT.21.TMIN | RFADC.TEST_SO22 |
| TCELL4:OUT.22.TMIN | RFADC.DATA_ADC0_58 |
| TCELL4:OUT.24.TMIN | RFADC.DATA_ADC0_59 |
| TCELL4:OUT.26.TMIN | RFADC.DATA_ADC0_60 |
| TCELL4:OUT.27.TMIN | RFADC.TEST_SO23 |
| TCELL4:OUT.28.TMIN | RFADC.STATUS_ADC0_12 |
| TCELL4:OUT.30.TMIN | RFADC.DATA_ADC0_61 |
| TCELL4:OUT.31.TMIN | RFADC.TEST_SO24 |
| TCELL4:IMUX.IMUX.7.DELAY | RFADC.TEST_SI22 |
| TCELL4:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC0_7 |
| TCELL4:IMUX.IMUX.17.DELAY | RFADC.TEST_SI20 |
| TCELL4:IMUX.IMUX.22.DELAY | RFADC.TEST_SI21 |
| TCELL4:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC0_6 |
| TCELL4:IMUX.IMUX.38.DELAY | RFADC.TEST_SI23 |
| TCELL4:IMUX.IMUX.47.DELAY | RFADC.TEST_SI24 |
| TCELL5:OUT.1.TMIN | RFADC.DATA_ADC0_62 |
| TCELL5:OUT.3.TMIN | RFADC.TEST_SO25 |
| TCELL5:OUT.4.TMIN | RFADC.STATUS_ADC0_13 |
| TCELL5:OUT.6.TMIN | RFADC.DATA_ADC0_63 |
| TCELL5:OUT.8.TMIN | RFADC.DATA_ADC0_64 |
| TCELL5:OUT.10.TMIN | RFADC.DATA_ADC0_65 |
| TCELL5:OUT.12.TMIN | RFADC.DATA_ADC0_66 |
| TCELL5:OUT.13.TMIN | RFADC.TEST_SO26 |
| TCELL5:OUT.14.TMIN | RFADC.DATA_ADC0_67 |
| TCELL5:OUT.16.TMIN | RFADC.DATA_ADC0_68 |
| TCELL5:OUT.18.TMIN | RFADC.DATA_ADC0_69 |
| TCELL5:OUT.20.TMIN | RFADC.DATA_ADC0_70 |
| TCELL5:OUT.21.TMIN | RFADC.TEST_SO27 |
| TCELL5:OUT.22.TMIN | RFADC.DATA_ADC0_71 |
| TCELL5:OUT.24.TMIN | RFADC.DATA_ADC0_72 |
| TCELL5:OUT.26.TMIN | RFADC.DATA_ADC0_73 |
| TCELL5:OUT.27.TMIN | RFADC.TEST_SO28 |
| TCELL5:OUT.28.TMIN | RFADC.STATUS_ADC0_14 |
| TCELL5:OUT.30.TMIN | RFADC.DATA_ADC0_74 |
| TCELL5:OUT.31.TMIN | RFADC.TEST_SO29 |
| TCELL5:IMUX.IMUX.7.DELAY | RFADC.TEST_SI27 |
| TCELL5:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC0_8 |
| TCELL5:IMUX.IMUX.17.DELAY | RFADC.TEST_SI25 |
| TCELL5:IMUX.IMUX.22.DELAY | RFADC.TEST_SI26 |
| TCELL5:IMUX.IMUX.38.DELAY | RFADC.TEST_SI28 |
| TCELL5:IMUX.IMUX.47.DELAY | RFADC.TEST_SI29 |
| TCELL6:OUT.1.TMIN | RFADC.DATA_ADC0_75 |
| TCELL6:OUT.3.TMIN | RFADC.TEST_SO30 |
| TCELL6:OUT.4.TMIN | RFADC.STATUS_ADC0_15 |
| TCELL6:OUT.6.TMIN | RFADC.DATA_ADC0_76 |
| TCELL6:OUT.8.TMIN | RFADC.DATA_ADC0_77 |
| TCELL6:OUT.10.TMIN | RFADC.DATA_ADC0_78 |
| TCELL6:OUT.12.TMIN | RFADC.DATA_ADC0_79 |
| TCELL6:OUT.13.TMIN | RFADC.TEST_SO31 |
| TCELL6:OUT.14.TMIN | RFADC.DATA_ADC0_80 |
| TCELL6:OUT.16.TMIN | RFADC.DATA_ADC0_81 |
| TCELL6:OUT.18.TMIN | RFADC.DATA_ADC0_82 |
| TCELL6:OUT.20.TMIN | RFADC.DATA_ADC0_83 |
| TCELL6:OUT.21.TMIN | RFADC.TEST_SO32 |
| TCELL6:OUT.22.TMIN | RFADC.DATA_ADC0_84 |
| TCELL6:OUT.24.TMIN | RFADC.DATA_ADC0_85 |
| TCELL6:OUT.26.TMIN | RFADC.DATA_ADC0_86 |
| TCELL6:OUT.27.TMIN | RFADC.TEST_SO33 |
| TCELL6:OUT.28.TMIN | RFADC.STATUS_ADC0_16 |
| TCELL6:OUT.30.TMIN | RFADC.DATA_ADC0_87 |
| TCELL6:OUT.31.TMIN | RFADC.TEST_SO34 |
| TCELL6:IMUX.IMUX.7.DELAY | RFADC.TEST_SI32 |
| TCELL6:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC0_10 |
| TCELL6:IMUX.IMUX.17.DELAY | RFADC.TEST_SI30 |
| TCELL6:IMUX.IMUX.22.DELAY | RFADC.TEST_SI31 |
| TCELL6:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC0_9 |
| TCELL6:IMUX.IMUX.38.DELAY | RFADC.TEST_SI33 |
| TCELL6:IMUX.IMUX.47.DELAY | RFADC.TEST_SI34 |
| TCELL7:OUT.1.TMIN | RFADC.DATA_ADC0_88 |
| TCELL7:OUT.3.TMIN | RFADC.TEST_SO35 |
| TCELL7:OUT.4.TMIN | RFADC.STATUS_ADC0_17 |
| TCELL7:OUT.6.TMIN | RFADC.DATA_ADC0_89 |
| TCELL7:OUT.8.TMIN | RFADC.DATA_ADC0_90 |
| TCELL7:OUT.10.TMIN | RFADC.DATA_ADC0_91 |
| TCELL7:OUT.12.TMIN | RFADC.DATA_ADC0_92 |
| TCELL7:OUT.13.TMIN | RFADC.TEST_SO36 |
| TCELL7:OUT.14.TMIN | RFADC.DATA_ADC0_93 |
| TCELL7:OUT.16.TMIN | RFADC.DATA_ADC0_94 |
| TCELL7:OUT.18.TMIN | RFADC.DATA_ADC0_95 |
| TCELL7:OUT.20.TMIN | RFADC.DATA_ADC0_96 |
| TCELL7:OUT.21.TMIN | RFADC.TEST_SO37 |
| TCELL7:OUT.22.TMIN | RFADC.DATA_ADC0_97 |
| TCELL7:OUT.24.TMIN | RFADC.DATA_ADC0_98 |
| TCELL7:OUT.26.TMIN | RFADC.DATA_ADC0_99 |
| TCELL7:OUT.27.TMIN | RFADC.TEST_SO38 |
| TCELL7:OUT.28.TMIN | RFADC.STATUS_ADC0_18 |
| TCELL7:OUT.30.TMIN | RFADC.DATA_ADC0_100 |
| TCELL7:OUT.31.TMIN | RFADC.TEST_SO39 |
| TCELL7:IMUX.IMUX.7.DELAY | RFADC.TEST_SI37 |
| TCELL7:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC0_11 |
| TCELL7:IMUX.IMUX.17.DELAY | RFADC.TEST_SI35 |
| TCELL7:IMUX.IMUX.22.DELAY | RFADC.TEST_SI36 |
| TCELL7:IMUX.IMUX.38.DELAY | RFADC.TEST_SI38 |
| TCELL7:IMUX.IMUX.47.DELAY | RFADC.TEST_SI39 |
| TCELL8:OUT.1.TMIN | RFADC.DATA_ADC0_101 |
| TCELL8:OUT.3.TMIN | RFADC.TEST_SO40 |
| TCELL8:OUT.4.TMIN | RFADC.STATUS_ADC0_19 |
| TCELL8:OUT.6.TMIN | RFADC.DATA_ADC0_102 |
| TCELL8:OUT.8.TMIN | RFADC.DATA_ADC0_103 |
| TCELL8:OUT.10.TMIN | RFADC.DATA_ADC0_104 |
| TCELL8:OUT.12.TMIN | RFADC.DATA_ADC0_105 |
| TCELL8:OUT.13.TMIN | RFADC.TEST_SO41 |
| TCELL8:OUT.14.TMIN | RFADC.DATA_ADC0_106 |
| TCELL8:OUT.16.TMIN | RFADC.DATA_ADC0_107 |
| TCELL8:OUT.18.TMIN | RFADC.DATA_ADC0_108 |
| TCELL8:OUT.20.TMIN | RFADC.DATA_ADC0_109 |
| TCELL8:OUT.21.TMIN | RFADC.TEST_SO42 |
| TCELL8:OUT.22.TMIN | RFADC.DATA_ADC0_110 |
| TCELL8:OUT.24.TMIN | RFADC.DATA_ADC0_111 |
| TCELL8:OUT.26.TMIN | RFADC.DATA_ADC0_112 |
| TCELL8:OUT.27.TMIN | RFADC.TEST_SO43 |
| TCELL8:OUT.28.TMIN | RFADC.STATUS_ADC0_20 |
| TCELL8:OUT.30.TMIN | RFADC.DATA_ADC0_113 |
| TCELL8:OUT.31.TMIN | RFADC.TEST_SO44 |
| TCELL8:IMUX.IMUX.7.DELAY | RFADC.TEST_SI42 |
| TCELL8:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC0_13 |
| TCELL8:IMUX.IMUX.17.DELAY | RFADC.TEST_SI40 |
| TCELL8:IMUX.IMUX.22.DELAY | RFADC.TEST_SI41 |
| TCELL8:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC0_12 |
| TCELL8:IMUX.IMUX.38.DELAY | RFADC.TEST_SI43 |
| TCELL8:IMUX.IMUX.47.DELAY | RFADC.TEST_SI44 |
| TCELL9:OUT.1.TMIN | RFADC.DATA_ADC0_114 |
| TCELL9:OUT.3.TMIN | RFADC.TEST_SO45 |
| TCELL9:OUT.4.TMIN | RFADC.STATUS_ADC0_21 |
| TCELL9:OUT.6.TMIN | RFADC.DATA_ADC0_115 |
| TCELL9:OUT.8.TMIN | RFADC.DATA_ADC0_116 |
| TCELL9:OUT.10.TMIN | RFADC.DATA_ADC0_117 |
| TCELL9:OUT.12.TMIN | RFADC.DATA_ADC0_118 |
| TCELL9:OUT.13.TMIN | RFADC.TEST_SO46 |
| TCELL9:OUT.14.TMIN | RFADC.DATA_ADC0_119 |
| TCELL9:OUT.16.TMIN | RFADC.DATA_ADC0_120 |
| TCELL9:OUT.18.TMIN | RFADC.DATA_ADC0_121 |
| TCELL9:OUT.20.TMIN | RFADC.DATA_ADC0_122 |
| TCELL9:OUT.21.TMIN | RFADC.TEST_SO47 |
| TCELL9:OUT.22.TMIN | RFADC.DATA_ADC0_123 |
| TCELL9:OUT.24.TMIN | RFADC.DATA_ADC0_124 |
| TCELL9:OUT.26.TMIN | RFADC.DATA_ADC0_125 |
| TCELL9:OUT.27.TMIN | RFADC.TEST_SO48 |
| TCELL9:OUT.28.TMIN | RFADC.STATUS_ADC0_22 |
| TCELL9:OUT.30.TMIN | RFADC.DATA_ADC0_126 |
| TCELL9:OUT.31.TMIN | RFADC.TEST_SO49 |
| TCELL9:IMUX.IMUX.7.DELAY | RFADC.TEST_SI47 |
| TCELL9:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC0_14 |
| TCELL9:IMUX.IMUX.17.DELAY | RFADC.TEST_SI45 |
| TCELL9:IMUX.IMUX.22.DELAY | RFADC.TEST_SI46 |
| TCELL9:IMUX.IMUX.38.DELAY | RFADC.TEST_SI48 |
| TCELL9:IMUX.IMUX.47.DELAY | RFADC.TEST_SI49 |
| TCELL10:OUT.1.TMIN | RFADC.DATA_ADC0_127 |
| TCELL10:OUT.3.TMIN | RFADC.TEST_SO50 |
| TCELL10:OUT.4.TMIN | RFADC.STATUS_ADC1_0 |
| TCELL10:OUT.6.TMIN | RFADC.DATA_ADC0_128 |
| TCELL10:OUT.8.TMIN | RFADC.DATA_ADC0_129 |
| TCELL10:OUT.10.TMIN | RFADC.DATA_ADC0_130 |
| TCELL10:OUT.12.TMIN | RFADC.DATA_ADC0_131 |
| TCELL10:OUT.13.TMIN | RFADC.TEST_SO51 |
| TCELL10:OUT.14.TMIN | RFADC.DATA_ADC0_132 |
| TCELL10:OUT.16.TMIN | RFADC.DATA_ADC0_133 |
| TCELL10:OUT.18.TMIN | RFADC.DATA_ADC0_134 |
| TCELL10:OUT.20.TMIN | RFADC.DATA_ADC0_135 |
| TCELL10:OUT.21.TMIN | RFADC.TEST_SO52 |
| TCELL10:OUT.22.TMIN | RFADC.DATA_ADC0_136 |
| TCELL10:OUT.24.TMIN | RFADC.DATA_ADC0_137 |
| TCELL10:OUT.26.TMIN | RFADC.DATA_ADC0_138 |
| TCELL10:OUT.27.TMIN | RFADC.TEST_SO53 |
| TCELL10:OUT.28.TMIN | RFADC.STATUS_ADC0_23 |
| TCELL10:OUT.30.TMIN | RFADC.DATA_ADC0_139 |
| TCELL10:OUT.31.TMIN | RFADC.TEST_SO54 |
| TCELL10:IMUX.IMUX.7.DELAY | RFADC.TEST_SI52 |
| TCELL10:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC0_15 |
| TCELL10:IMUX.IMUX.17.DELAY | RFADC.TEST_SI50 |
| TCELL10:IMUX.IMUX.22.DELAY | RFADC.TEST_SI51 |
| TCELL10:IMUX.IMUX.38.DELAY | RFADC.TEST_SI53 |
| TCELL10:IMUX.IMUX.47.DELAY | RFADC.TEST_SI54 |
| TCELL11:OUT.1.TMIN | RFADC.DATA_ADC0_140 |
| TCELL11:OUT.3.TMIN | RFADC.TEST_SO55 |
| TCELL11:OUT.4.TMIN | RFADC.STATUS_ADC1_1 |
| TCELL11:OUT.6.TMIN | RFADC.DATA_ADC0_141 |
| TCELL11:OUT.8.TMIN | RFADC.DATA_ADC0_142 |
| TCELL11:OUT.10.TMIN | RFADC.DATA_ADC0_143 |
| TCELL11:OUT.12.TMIN | RFADC.DATA_ADC0_144 |
| TCELL11:OUT.13.TMIN | RFADC.TEST_SO56 |
| TCELL11:OUT.14.TMIN | RFADC.DATA_ADC0_145 |
| TCELL11:OUT.16.TMIN | RFADC.DATA_ADC0_146 |
| TCELL11:OUT.18.TMIN | RFADC.DATA_ADC0_147 |
| TCELL11:OUT.20.TMIN | RFADC.DATA_ADC0_148 |
| TCELL11:OUT.21.TMIN | RFADC.TEST_SO57 |
| TCELL11:OUT.22.TMIN | RFADC.DATA_ADC0_149 |
| TCELL11:OUT.24.TMIN | RFADC.DATA_ADC0_150 |
| TCELL11:OUT.26.TMIN | RFADC.DATA_ADC0_151 |
| TCELL11:OUT.27.TMIN | RFADC.TEST_SO58 |
| TCELL11:OUT.28.TMIN | RFADC.STATUS_ADC1_2 |
| TCELL11:OUT.30.TMIN | RFADC.DATA_ADC0_152 |
| TCELL11:OUT.31.TMIN | RFADC.TEST_SO59 |
| TCELL11:IMUX.IMUX.7.DELAY | RFADC.TEST_SI57 |
| TCELL11:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC1_1 |
| TCELL11:IMUX.IMUX.17.DELAY | RFADC.TEST_SI55 |
| TCELL11:IMUX.IMUX.22.DELAY | RFADC.TEST_SI56 |
| TCELL11:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC1_0 |
| TCELL11:IMUX.IMUX.38.DELAY | RFADC.TEST_SI58 |
| TCELL11:IMUX.IMUX.47.DELAY | RFADC.TEST_SI59 |
| TCELL12:OUT.1.TMIN | RFADC.DATA_ADC0_153 |
| TCELL12:OUT.3.TMIN | RFADC.TEST_SO60 |
| TCELL12:OUT.4.TMIN | RFADC.STATUS_ADC1_3 |
| TCELL12:OUT.6.TMIN | RFADC.DATA_ADC0_154 |
| TCELL12:OUT.8.TMIN | RFADC.DATA_ADC0_155 |
| TCELL12:OUT.10.TMIN | RFADC.DATA_ADC0_156 |
| TCELL12:OUT.12.TMIN | RFADC.DATA_ADC0_157 |
| TCELL12:OUT.13.TMIN | RFADC.TEST_SO61 |
| TCELL12:OUT.14.TMIN | RFADC.DATA_ADC0_158 |
| TCELL12:OUT.16.TMIN | RFADC.DATA_ADC0_159 |
| TCELL12:OUT.18.TMIN | RFADC.DATA_ADC0_160 |
| TCELL12:OUT.20.TMIN | RFADC.DATA_ADC0_161 |
| TCELL12:OUT.21.TMIN | RFADC.TEST_SO62 |
| TCELL12:OUT.22.TMIN | RFADC.DATA_ADC0_162 |
| TCELL12:OUT.24.TMIN | RFADC.DATA_ADC0_163 |
| TCELL12:OUT.26.TMIN | RFADC.DATA_ADC0_164 |
| TCELL12:OUT.27.TMIN | RFADC.TEST_SO63 |
| TCELL12:OUT.28.TMIN | RFADC.STATUS_ADC1_4 |
| TCELL12:OUT.30.TMIN | RFADC.DATA_ADC0_165 |
| TCELL12:OUT.31.TMIN | RFADC.TEST_SO64 |
| TCELL12:IMUX.IMUX.1.DELAY | BUFG_GT_SYNC0.CE_IN |
| TCELL12:IMUX.IMUX.5.DELAY | BUFG_GT_SYNC3.CE_IN |
| TCELL12:IMUX.IMUX.7.DELAY | RFADC.TEST_SI62 |
| TCELL12:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC1_2 |
| TCELL12:IMUX.IMUX.17.DELAY | RFADC.TEST_SI60 |
| TCELL12:IMUX.IMUX.19.DELAY | BUFG_GT_SYNC1.CE_IN |
| TCELL12:IMUX.IMUX.21.DELAY | BUFG_GT_SYNC2.CE_IN |
| TCELL12:IMUX.IMUX.22.DELAY | RFADC.TEST_SI61 |
| TCELL12:IMUX.IMUX.38.DELAY | RFADC.TEST_SI63 |
| TCELL12:IMUX.IMUX.47.DELAY | RFADC.TEST_SI64 |
| TCELL13:OUT.1.TMIN | RFADC.DATA_ADC0_166 |
| TCELL13:OUT.3.TMIN | RFADC.TEST_SO65 |
| TCELL13:OUT.4.TMIN | RFADC.STATUS_ADC1_5 |
| TCELL13:OUT.6.TMIN | RFADC.DATA_ADC0_167 |
| TCELL13:OUT.8.TMIN | RFADC.DATA_ADC0_168 |
| TCELL13:OUT.10.TMIN | RFADC.DATA_ADC0_169 |
| TCELL13:OUT.12.TMIN | RFADC.DATA_ADC0_170 |
| TCELL13:OUT.13.TMIN | RFADC.TEST_SO66 |
| TCELL13:OUT.14.TMIN | RFADC.DATA_ADC0_171 |
| TCELL13:OUT.16.TMIN | RFADC.DATA_ADC0_172 |
| TCELL13:OUT.18.TMIN | RFADC.DATA_ADC0_173 |
| TCELL13:OUT.20.TMIN | RFADC.DATA_ADC0_174 |
| TCELL13:OUT.21.TMIN | RFADC.TEST_SO67 |
| TCELL13:OUT.22.TMIN | RFADC.DATA_ADC0_175 |
| TCELL13:OUT.24.TMIN | RFADC.DATA_ADC0_176 |
| TCELL13:OUT.26.TMIN | RFADC.DATA_ADC0_177 |
| TCELL13:OUT.27.TMIN | RFADC.TEST_SO68 |
| TCELL13:OUT.28.TMIN | RFADC.STATUS_ADC1_6 |
| TCELL13:OUT.30.TMIN | RFADC.DATA_ADC0_178 |
| TCELL13:OUT.31.TMIN | RFADC.TEST_SO69 |
| TCELL13:IMUX.IMUX.5.DELAY | BUFG_GT_SYNC1.RST_IN |
| TCELL13:IMUX.IMUX.6.DELAY | BUFG_GT_SYNC2.RST_IN |
| TCELL13:IMUX.IMUX.7.DELAY | RFADC.TEST_SI67 |
| TCELL13:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC1_4 |
| TCELL13:IMUX.IMUX.17.DELAY | RFADC.TEST_SI65 |
| TCELL13:IMUX.IMUX.19.DELAY | BUFG_GT_SYNC14.CE_IN |
| TCELL13:IMUX.IMUX.21.DELAY | BUFG_GT_SYNC0.RST_IN |
| TCELL13:IMUX.IMUX.22.DELAY | RFADC.TEST_SI66 |
| TCELL13:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC1_3 |
| TCELL13:IMUX.IMUX.29.DELAY | BUFG_GT_SYNC3.RST_IN |
| TCELL13:IMUX.IMUX.38.DELAY | RFADC.TEST_SI68 |
| TCELL13:IMUX.IMUX.47.DELAY | RFADC.TEST_SI69 |
| TCELL14:OUT.1.TMIN | RFADC.DATA_ADC0_179 |
| TCELL14:OUT.3.TMIN | RFADC.TEST_SO70 |
| TCELL14:OUT.4.TMIN | RFADC.STATUS_ADC1_7 |
| TCELL14:OUT.6.TMIN | RFADC.DATA_ADC0_180 |
| TCELL14:OUT.8.TMIN | RFADC.DATA_ADC0_181 |
| TCELL14:OUT.10.TMIN | RFADC.DATA_ADC0_182 |
| TCELL14:OUT.12.TMIN | RFADC.DATA_ADC0_183 |
| TCELL14:OUT.13.TMIN | RFADC.TEST_SO71 |
| TCELL14:OUT.14.TMIN | RFADC.DATA_ADC0_184 |
| TCELL14:OUT.16.TMIN | RFADC.DATA_ADC0_185 |
| TCELL14:OUT.18.TMIN | RFADC.DATA_ADC0_186 |
| TCELL14:OUT.20.TMIN | RFADC.DATA_ADC0_187 |
| TCELL14:OUT.21.TMIN | RFADC.TEST_SO72 |
| TCELL14:OUT.22.TMIN | RFADC.DATA_ADC0_188 |
| TCELL14:OUT.24.TMIN | RFADC.DATA_ADC0_189 |
| TCELL14:OUT.26.TMIN | RFADC.DATA_ADC0_190 |
| TCELL14:OUT.27.TMIN | RFADC.TEST_SO73 |
| TCELL14:OUT.28.TMIN | RFADC.STATUS_ADC1_8 |
| TCELL14:OUT.30.TMIN | RFADC.DATA_ADC0_191 |
| TCELL14:OUT.31.TMIN | RFADC.TEST_SO74 |
| TCELL14:IMUX.IMUX.5.DELAY | BUFG_GT0.CEMASK |
| TCELL14:IMUX.IMUX.6.DELAY | BUFG_GT1.CEMASK |
| TCELL14:IMUX.IMUX.7.DELAY | RFADC.TEST_SI72 |
| TCELL14:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC1_5 |
| TCELL14:IMUX.IMUX.9.DELAY | BUFG_GT3.CEMASK |
| TCELL14:IMUX.IMUX.10.DELAY | BUFG_GT4.CEMASK |
| TCELL14:IMUX.IMUX.11.DELAY | BUFG_GT5.CEMASK |
| TCELL14:IMUX.IMUX.13.DELAY | BUFG_GT6.CEMASK |
| TCELL14:IMUX.IMUX.17.DELAY | RFADC.TEST_SI70 |
| TCELL14:IMUX.IMUX.21.DELAY | BUFG_GT_SYNC14.RST_IN |
| TCELL14:IMUX.IMUX.22.DELAY | RFADC.TEST_SI71 |
| TCELL14:IMUX.IMUX.29.DELAY | BUFG_GT2.CEMASK |
| TCELL14:IMUX.IMUX.38.DELAY | RFADC.TEST_SI73 |
| TCELL14:IMUX.IMUX.42.DELAY | BUFG_GT7.CEMASK |
| TCELL14:IMUX.IMUX.44.DELAY | BUFG_GT8.CEMASK |
| TCELL14:IMUX.IMUX.46.DELAY | BUFG_GT9.CEMASK |
| TCELL14:IMUX.IMUX.47.DELAY | RFADC.TEST_SI74 |
| TCELL15:OUT.1.TMIN | RFADC.DATA_ADC1_0 |
| TCELL15:OUT.3.TMIN | RFADC.TEST_SO75 |
| TCELL15:OUT.4.TMIN | RFADC.STATUS_ADC1_9 |
| TCELL15:OUT.6.TMIN | RFADC.DATA_ADC1_1 |
| TCELL15:OUT.8.TMIN | RFADC.DATA_ADC1_2 |
| TCELL15:OUT.10.TMIN | RFADC.DATA_ADC1_3 |
| TCELL15:OUT.11.TMIN | RFADC.TEST_SO76 |
| TCELL15:OUT.12.TMIN | RFADC.DATA_ADC1_4 |
| TCELL15:OUT.14.TMIN | RFADC.DATA_ADC1_5 |
| TCELL15:OUT.16.TMIN | RFADC.DATA_ADC1_6 |
| TCELL15:OUT.18.TMIN | RFADC.DATA_ADC1_7 |
| TCELL15:OUT.20.TMIN | RFADC.DATA_ADC1_8 |
| TCELL15:OUT.21.TMIN | RFADC.TEST_SO77 |
| TCELL15:OUT.22.TMIN | RFADC.DATA_ADC1_9 |
| TCELL15:OUT.24.TMIN | RFADC.DATA_ADC1_10 |
| TCELL15:OUT.26.TMIN | RFADC.DATA_ADC1_11 |
| TCELL15:OUT.27.TMIN | RFADC.TEST_SO78 |
| TCELL15:OUT.28.TMIN | RFADC.STATUS_ADC1_10 |
| TCELL15:OUT.30.TMIN | RFADC.DATA_ADC1_12 |
| TCELL15:OUT.31.TMIN | RFADC.TEST_SO79 |
| TCELL15:IMUX.IMUX.1.DELAY | BUFG_GT10.CEMASK |
| TCELL15:IMUX.IMUX.5.DELAY | BUFG_GT13.CEMASK |
| TCELL15:IMUX.IMUX.6.DELAY | BUFG_GT14.CEMASK |
| TCELL15:IMUX.IMUX.7.DELAY | RFADC.TEST_SI77 |
| TCELL15:IMUX.IMUX.9.DELAY | BUFG_GT16.CEMASK |
| TCELL15:IMUX.IMUX.10.DELAY | BUFG_GT17.CEMASK |
| TCELL15:IMUX.IMUX.11.DELAY | BUFG_GT18.CEMASK |
| TCELL15:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC1_7 |
| TCELL15:IMUX.IMUX.13.DELAY | BUFG_GT19.CEMASK |
| TCELL15:IMUX.IMUX.17.DELAY | RFADC.TEST_SI75 |
| TCELL15:IMUX.IMUX.19.DELAY | BUFG_GT11.CEMASK |
| TCELL15:IMUX.IMUX.21.DELAY | BUFG_GT12.CEMASK |
| TCELL15:IMUX.IMUX.22.DELAY | RFADC.TEST_SI76 |
| TCELL15:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC1_6 |
| TCELL15:IMUX.IMUX.29.DELAY | BUFG_GT15.CEMASK |
| TCELL15:IMUX.IMUX.38.DELAY | RFADC.TEST_SI78 |
| TCELL15:IMUX.IMUX.42.DELAY | BUFG_GT20.CEMASK |
| TCELL15:IMUX.IMUX.44.DELAY | BUFG_GT21.CEMASK |
| TCELL15:IMUX.IMUX.46.DELAY | BUFG_GT22.CEMASK |
| TCELL15:IMUX.IMUX.47.DELAY | RFADC.TEST_SI79 |
| TCELL16:OUT.1.TMIN | RFADC.DATA_ADC1_13 |
| TCELL16:OUT.3.TMIN | RFADC.TEST_SO80 |
| TCELL16:OUT.4.TMIN | RFADC.STATUS_ADC1_11 |
| TCELL16:OUT.6.TMIN | RFADC.DATA_ADC1_14 |
| TCELL16:OUT.8.TMIN | RFADC.DATA_ADC1_15 |
| TCELL16:OUT.10.TMIN | RFADC.DATA_ADC1_16 |
| TCELL16:OUT.11.TMIN | RFADC.TEST_SO81 |
| TCELL16:OUT.12.TMIN | RFADC.DATA_ADC1_17 |
| TCELL16:OUT.14.TMIN | RFADC.DATA_ADC1_18 |
| TCELL16:OUT.16.TMIN | RFADC.DATA_ADC1_19 |
| TCELL16:OUT.18.TMIN | RFADC.DATA_ADC1_20 |
| TCELL16:OUT.20.TMIN | RFADC.DATA_ADC1_21 |
| TCELL16:OUT.21.TMIN | RFADC.TEST_SO82 |
| TCELL16:OUT.22.TMIN | RFADC.DATA_ADC1_22 |
| TCELL16:OUT.24.TMIN | RFADC.DATA_ADC1_23 |
| TCELL16:OUT.26.TMIN | RFADC.DATA_ADC1_24 |
| TCELL16:OUT.27.TMIN | RFADC.TEST_SO83 |
| TCELL16:OUT.28.TMIN | RFADC.STATUS_ADC1_12 |
| TCELL16:OUT.30.TMIN | RFADC.DATA_ADC1_25 |
| TCELL16:OUT.31.TMIN | RFADC.TEST_SO84 |
| TCELL16:IMUX.IMUX.1.DELAY | BUFG_GT23.CEMASK |
| TCELL16:IMUX.IMUX.5.DELAY | BUFG_GT2.RSTMASK |
| TCELL16:IMUX.IMUX.6.DELAY | BUFG_GT3.RSTMASK |
| TCELL16:IMUX.IMUX.7.DELAY | RFADC.TEST_SI82 |
| TCELL16:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC1_8 |
| TCELL16:IMUX.IMUX.9.DELAY | BUFG_GT5.RSTMASK |
| TCELL16:IMUX.IMUX.10.DELAY | BUFG_GT6.RSTMASK |
| TCELL16:IMUX.IMUX.11.DELAY | BUFG_GT7.RSTMASK |
| TCELL16:IMUX.IMUX.13.DELAY | BUFG_GT8.RSTMASK |
| TCELL16:IMUX.IMUX.17.DELAY | RFADC.TEST_SI80 |
| TCELL16:IMUX.IMUX.19.DELAY | BUFG_GT0.RSTMASK |
| TCELL16:IMUX.IMUX.21.DELAY | BUFG_GT1.RSTMASK |
| TCELL16:IMUX.IMUX.22.DELAY | RFADC.TEST_SI81 |
| TCELL16:IMUX.IMUX.29.DELAY | BUFG_GT4.RSTMASK |
| TCELL16:IMUX.IMUX.38.DELAY | RFADC.TEST_SI83 |
| TCELL16:IMUX.IMUX.42.DELAY | BUFG_GT9.RSTMASK |
| TCELL16:IMUX.IMUX.44.DELAY | BUFG_GT10.RSTMASK |
| TCELL16:IMUX.IMUX.46.DELAY | BUFG_GT11.RSTMASK |
| TCELL16:IMUX.IMUX.47.DELAY | RFADC.TEST_SI84 |
| TCELL17:OUT.1.TMIN | RFADC.DATA_ADC1_26 |
| TCELL17:OUT.3.TMIN | RFADC.TEST_SO85 |
| TCELL17:OUT.4.TMIN | RFADC.STATUS_ADC1_13 |
| TCELL17:OUT.6.TMIN | RFADC.DATA_ADC1_27 |
| TCELL17:OUT.8.TMIN | RFADC.DATA_ADC1_28 |
| TCELL17:OUT.10.TMIN | RFADC.DATA_ADC1_29 |
| TCELL17:OUT.11.TMIN | RFADC.TEST_SO86 |
| TCELL17:OUT.12.TMIN | RFADC.DATA_ADC1_30 |
| TCELL17:OUT.14.TMIN | RFADC.DATA_ADC1_31 |
| TCELL17:OUT.16.TMIN | RFADC.DATA_ADC1_32 |
| TCELL17:OUT.18.TMIN | RFADC.DATA_ADC1_33 |
| TCELL17:OUT.20.TMIN | RFADC.DATA_ADC1_34 |
| TCELL17:OUT.21.TMIN | RFADC.TEST_SO87 |
| TCELL17:OUT.22.TMIN | RFADC.DATA_ADC1_35 |
| TCELL17:OUT.24.TMIN | RFADC.DATA_ADC1_36 |
| TCELL17:OUT.26.TMIN | RFADC.DATA_ADC1_37 |
| TCELL17:OUT.27.TMIN | RFADC.TEST_SO88 |
| TCELL17:OUT.28.TMIN | RFADC.STATUS_ADC1_14 |
| TCELL17:OUT.30.TMIN | RFADC.DATA_ADC1_38 |
| TCELL17:OUT.31.TMIN | RFADC.TEST_SO89 |
| TCELL17:IMUX.CTRL.5 | RFADC.TEST_SCAN_CLK1 |
| TCELL17:IMUX.IMUX.1.DELAY | BUFG_GT12.RSTMASK |
| TCELL17:IMUX.IMUX.5.DELAY | BUFG_GT15.RSTMASK |
| TCELL17:IMUX.IMUX.6.DELAY | BUFG_GT16.RSTMASK |
| TCELL17:IMUX.IMUX.7.DELAY | RFADC.TEST_SI87 |
| TCELL17:IMUX.IMUX.9.DELAY | BUFG_GT18.RSTMASK |
| TCELL17:IMUX.IMUX.10.DELAY | BUFG_GT19.RSTMASK |
| TCELL17:IMUX.IMUX.11.DELAY | BUFG_GT20.RSTMASK |
| TCELL17:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC1_10 |
| TCELL17:IMUX.IMUX.13.DELAY | BUFG_GT21.RSTMASK |
| TCELL17:IMUX.IMUX.17.DELAY | RFADC.TEST_SI85 |
| TCELL17:IMUX.IMUX.19.DELAY | BUFG_GT13.RSTMASK |
| TCELL17:IMUX.IMUX.21.DELAY | BUFG_GT14.RSTMASK |
| TCELL17:IMUX.IMUX.22.DELAY | RFADC.TEST_SI86 |
| TCELL17:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC1_9 |
| TCELL17:IMUX.IMUX.29.DELAY | BUFG_GT17.RSTMASK |
| TCELL17:IMUX.IMUX.38.DELAY | RFADC.TEST_SI88 |
| TCELL17:IMUX.IMUX.42.DELAY | BUFG_GT22.RSTMASK |
| TCELL17:IMUX.IMUX.44.DELAY | BUFG_GT23.RSTMASK |
| TCELL17:IMUX.IMUX.47.DELAY | RFADC.TEST_SI89 |
| TCELL18:OUT.1.TMIN | RFADC.DATA_ADC1_39 |
| TCELL18:OUT.3.TMIN | RFADC.TEST_SO90 |
| TCELL18:OUT.4.TMIN | RFADC.STATUS_ADC1_15 |
| TCELL18:OUT.6.TMIN | RFADC.DATA_ADC1_40 |
| TCELL18:OUT.8.TMIN | RFADC.DATA_ADC1_41 |
| TCELL18:OUT.10.TMIN | RFADC.DATA_ADC1_42 |
| TCELL18:OUT.11.TMIN | RFADC.TEST_SO91 |
| TCELL18:OUT.12.TMIN | RFADC.DATA_ADC1_43 |
| TCELL18:OUT.14.TMIN | RFADC.DATA_ADC1_44 |
| TCELL18:OUT.16.TMIN | RFADC.DATA_ADC1_45 |
| TCELL18:OUT.18.TMIN | RFADC.DATA_ADC1_46 |
| TCELL18:OUT.20.TMIN | RFADC.DATA_ADC1_47 |
| TCELL18:OUT.21.TMIN | RFADC.TEST_SO92 |
| TCELL18:OUT.22.TMIN | RFADC.DATA_ADC1_48 |
| TCELL18:OUT.24.TMIN | RFADC.DATA_ADC1_49 |
| TCELL18:OUT.26.TMIN | RFADC.DATA_ADC1_50 |
| TCELL18:OUT.27.TMIN | RFADC.TEST_SO93 |
| TCELL18:OUT.28.TMIN | RFADC.STATUS_ADC1_16 |
| TCELL18:OUT.30.TMIN | RFADC.DATA_ADC1_51 |
| TCELL18:OUT.31.TMIN | RFADC.TEST_SO94 |
| TCELL18:IMUX.IMUX.7.DELAY | RFADC.TEST_SI92 |
| TCELL18:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC1_11 |
| TCELL18:IMUX.IMUX.17.DELAY | RFADC.TEST_SI90 |
| TCELL18:IMUX.IMUX.22.DELAY | RFADC.TEST_SI91 |
| TCELL18:IMUX.IMUX.38.DELAY | RFADC.TEST_SI93 |
| TCELL18:IMUX.IMUX.47.DELAY | RFADC.TEST_SI94 |
| TCELL19:OUT.1.TMIN | RFADC.DATA_ADC1_52 |
| TCELL19:OUT.3.TMIN | RFADC.TEST_SO95 |
| TCELL19:OUT.4.TMIN | RFADC.STATUS_ADC1_17 |
| TCELL19:OUT.6.TMIN | RFADC.DATA_ADC1_53 |
| TCELL19:OUT.8.TMIN | RFADC.DATA_ADC1_54 |
| TCELL19:OUT.10.TMIN | RFADC.DATA_ADC1_55 |
| TCELL19:OUT.11.TMIN | RFADC.TEST_SO96 |
| TCELL19:OUT.12.TMIN | RFADC.DATA_ADC1_56 |
| TCELL19:OUT.14.TMIN | RFADC.DATA_ADC1_57 |
| TCELL19:OUT.16.TMIN | RFADC.DATA_ADC1_58 |
| TCELL19:OUT.18.TMIN | RFADC.DATA_ADC1_59 |
| TCELL19:OUT.20.TMIN | RFADC.DATA_ADC1_60 |
| TCELL19:OUT.21.TMIN | RFADC.TEST_SO97 |
| TCELL19:OUT.22.TMIN | RFADC.DATA_ADC1_61 |
| TCELL19:OUT.24.TMIN | RFADC.DATA_ADC1_62 |
| TCELL19:OUT.26.TMIN | RFADC.DATA_ADC1_63 |
| TCELL19:OUT.27.TMIN | RFADC.TEST_SO98 |
| TCELL19:OUT.28.TMIN | RFADC.STATUS_ADC1_18 |
| TCELL19:OUT.30.TMIN | RFADC.DATA_ADC1_64 |
| TCELL19:OUT.31.TMIN | RFADC.TEST_SO99 |
| TCELL19:IMUX.IMUX.7.DELAY | RFADC.TEST_SI97 |
| TCELL19:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC1_13 |
| TCELL19:IMUX.IMUX.17.DELAY | RFADC.TEST_SI95 |
| TCELL19:IMUX.IMUX.22.DELAY | RFADC.TEST_SI96 |
| TCELL19:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC1_12 |
| TCELL19:IMUX.IMUX.38.DELAY | RFADC.TEST_SI98 |
| TCELL19:IMUX.IMUX.47.DELAY | RFADC.TEST_SI99 |
| TCELL20:OUT.1.TMIN | RFADC.DATA_ADC1_65 |
| TCELL20:OUT.3.TMIN | RFADC.TEST_SO100 |
| TCELL20:OUT.4.TMIN | RFADC.STATUS_ADC1_19 |
| TCELL20:OUT.6.TMIN | RFADC.DATA_ADC1_66 |
| TCELL20:OUT.8.TMIN | RFADC.DATA_ADC1_67 |
| TCELL20:OUT.10.TMIN | RFADC.DATA_ADC1_68 |
| TCELL20:OUT.11.TMIN | RFADC.TEST_SO101 |
| TCELL20:OUT.12.TMIN | RFADC.DATA_ADC1_69 |
| TCELL20:OUT.14.TMIN | RFADC.DATA_ADC1_70 |
| TCELL20:OUT.16.TMIN | RFADC.DATA_ADC1_71 |
| TCELL20:OUT.17.TMIN | RFADC.TEST_STATUS0 |
| TCELL20:OUT.18.TMIN | RFADC.DATA_ADC1_72 |
| TCELL20:OUT.20.TMIN | RFADC.DATA_ADC1_73 |
| TCELL20:OUT.21.TMIN | RFADC.TEST_SO102 |
| TCELL20:OUT.22.TMIN | RFADC.DATA_ADC1_74 |
| TCELL20:OUT.24.TMIN | RFADC.DATA_ADC1_75 |
| TCELL20:OUT.26.TMIN | RFADC.DATA_ADC1_76 |
| TCELL20:OUT.27.TMIN | RFADC.TEST_SO103 |
| TCELL20:OUT.28.TMIN | RFADC.STATUS_ADC1_20 |
| TCELL20:OUT.30.TMIN | RFADC.DATA_ADC1_77 |
| TCELL20:OUT.31.TMIN | RFADC.TEST_SO104 |
| TCELL20:IMUX.IMUX.7.DELAY | RFADC.TEST_SI102 |
| TCELL20:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC1_15 |
| TCELL20:IMUX.IMUX.17.DELAY | RFADC.TEST_SI100 |
| TCELL20:IMUX.IMUX.22.DELAY | RFADC.TEST_SI101 |
| TCELL20:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC1_14 |
| TCELL20:IMUX.IMUX.38.DELAY | RFADC.TEST_SI103 |
| TCELL20:IMUX.IMUX.47.DELAY | RFADC.TEST_SI104 |
| TCELL21:OUT.1.TMIN | RFADC.DATA_ADC1_78 |
| TCELL21:OUT.3.TMIN | RFADC.TEST_SO105 |
| TCELL21:OUT.4.TMIN | RFADC.STATUS_ADC1_21 |
| TCELL21:OUT.6.TMIN | RFADC.DATA_ADC1_79 |
| TCELL21:OUT.8.TMIN | RFADC.DATA_ADC1_80 |
| TCELL21:OUT.10.TMIN | RFADC.DATA_ADC1_81 |
| TCELL21:OUT.11.TMIN | RFADC.TEST_SO106 |
| TCELL21:OUT.12.TMIN | RFADC.DATA_ADC1_82 |
| TCELL21:OUT.14.TMIN | RFADC.DATA_ADC1_83 |
| TCELL21:OUT.16.TMIN | RFADC.DATA_ADC1_84 |
| TCELL21:OUT.17.TMIN | RFADC.TEST_STATUS1 |
| TCELL21:OUT.18.TMIN | RFADC.DATA_ADC1_85 |
| TCELL21:OUT.20.TMIN | RFADC.DATA_ADC1_86 |
| TCELL21:OUT.21.TMIN | RFADC.TEST_SO107 |
| TCELL21:OUT.22.TMIN | RFADC.DATA_ADC1_87 |
| TCELL21:OUT.24.TMIN | RFADC.DATA_ADC1_88 |
| TCELL21:OUT.26.TMIN | RFADC.DATA_ADC1_89 |
| TCELL21:OUT.27.TMIN | RFADC.TEST_SO108 |
| TCELL21:OUT.28.TMIN | RFADC.STATUS_ADC1_22 |
| TCELL21:OUT.30.TMIN | RFADC.DATA_ADC1_90 |
| TCELL21:OUT.31.TMIN | RFADC.TEST_SO109 |
| TCELL21:IMUX.IMUX.7.DELAY | RFADC.TEST_SI107 |
| TCELL21:IMUX.IMUX.8.DELAY | RFADC.CONTROL_COMMON0 |
| TCELL21:IMUX.IMUX.17.DELAY | RFADC.TEST_SI105 |
| TCELL21:IMUX.IMUX.22.DELAY | RFADC.TEST_SI106 |
| TCELL21:IMUX.IMUX.38.DELAY | RFADC.TEST_SI108 |
| TCELL21:IMUX.IMUX.47.DELAY | RFADC.TEST_SI109 |
| TCELL22:OUT.1.TMIN | RFADC.DATA_ADC1_91 |
| TCELL22:OUT.3.TMIN | RFADC.TEST_SO110 |
| TCELL22:OUT.4.TMIN | RFADC.STATUS_ADC1_23 |
| TCELL22:OUT.6.TMIN | RFADC.DATA_ADC1_92 |
| TCELL22:OUT.8.TMIN | RFADC.DATA_ADC1_93 |
| TCELL22:OUT.10.TMIN | RFADC.DATA_ADC1_94 |
| TCELL22:OUT.11.TMIN | RFADC.TEST_SO111 |
| TCELL22:OUT.12.TMIN | RFADC.DATA_ADC1_95 |
| TCELL22:OUT.14.TMIN | RFADC.DATA_ADC1_96 |
| TCELL22:OUT.16.TMIN | RFADC.DATA_ADC1_97 |
| TCELL22:OUT.17.TMIN | RFADC.TEST_STATUS2 |
| TCELL22:OUT.18.TMIN | RFADC.DATA_ADC1_98 |
| TCELL22:OUT.20.TMIN | RFADC.DATA_ADC1_99 |
| TCELL22:OUT.21.TMIN | RFADC.TEST_SO112 |
| TCELL22:OUT.22.TMIN | RFADC.DATA_ADC1_100 |
| TCELL22:OUT.24.TMIN | RFADC.DATA_ADC1_101 |
| TCELL22:OUT.26.TMIN | RFADC.DATA_ADC1_102 |
| TCELL22:OUT.27.TMIN | RFADC.TEST_SO113 |
| TCELL22:OUT.28.TMIN | RFADC.STATUS_COMMON0 |
| TCELL22:OUT.30.TMIN | RFADC.DATA_ADC1_103 |
| TCELL22:OUT.31.TMIN | RFADC.TEST_SO114 |
| TCELL22:IMUX.IMUX.7.DELAY | RFADC.TEST_SI112 |
| TCELL22:IMUX.IMUX.8.DELAY | RFADC.CONTROL_COMMON2 |
| TCELL22:IMUX.IMUX.12.DELAY | RFADC.CONTROL_COMMON3 |
| TCELL22:IMUX.IMUX.17.DELAY | RFADC.TEST_SI110 |
| TCELL22:IMUX.IMUX.22.DELAY | RFADC.TEST_SI111 |
| TCELL22:IMUX.IMUX.23.DELAY | RFADC.CONTROL_COMMON1 |
| TCELL22:IMUX.IMUX.26.DELAY | RFADC.TEST_SCAN_CTRL0 |
| TCELL22:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_CTRL1 |
| TCELL22:IMUX.IMUX.38.DELAY | RFADC.TEST_SI113 |
| TCELL22:IMUX.IMUX.47.DELAY | RFADC.TEST_SI114 |
| TCELL23:OUT.1.TMIN | RFADC.DATA_ADC1_104 |
| TCELL23:OUT.3.TMIN | RFADC.TEST_SO115 |
| TCELL23:OUT.4.TMIN | RFADC.STATUS_COMMON1 |
| TCELL23:OUT.6.TMIN | RFADC.DATA_ADC1_105 |
| TCELL23:OUT.8.TMIN | RFADC.DATA_ADC1_106 |
| TCELL23:OUT.10.TMIN | RFADC.DATA_ADC1_107 |
| TCELL23:OUT.11.TMIN | RFADC.TEST_SO116 |
| TCELL23:OUT.12.TMIN | RFADC.DATA_ADC1_108 |
| TCELL23:OUT.14.TMIN | RFADC.DATA_ADC1_109 |
| TCELL23:OUT.16.TMIN | RFADC.DATA_ADC1_110 |
| TCELL23:OUT.17.TMIN | RFADC.TEST_STATUS3 |
| TCELL23:OUT.18.TMIN | RFADC.DATA_ADC1_111 |
| TCELL23:OUT.20.TMIN | RFADC.DATA_ADC1_112 |
| TCELL23:OUT.21.TMIN | RFADC.TEST_SO117 |
| TCELL23:OUT.22.TMIN | RFADC.DATA_ADC1_113 |
| TCELL23:OUT.24.TMIN | RFADC.DATA_ADC1_114 |
| TCELL23:OUT.26.TMIN | RFADC.DATA_ADC1_115 |
| TCELL23:OUT.27.TMIN | RFADC.TEST_SO118 |
| TCELL23:OUT.28.TMIN | RFADC.STATUS_COMMON2 |
| TCELL23:OUT.30.TMIN | RFADC.DATA_ADC1_116 |
| TCELL23:OUT.31.TMIN | RFADC.TEST_SO119 |
| TCELL23:IMUX.IMUX.7.DELAY | RFADC.TEST_SI117 |
| TCELL23:IMUX.IMUX.12.DELAY | RFADC.CONTROL_COMMON5 |
| TCELL23:IMUX.IMUX.17.DELAY | RFADC.TEST_SI115 |
| TCELL23:IMUX.IMUX.22.DELAY | RFADC.TEST_SI116 |
| TCELL23:IMUX.IMUX.23.DELAY | RFADC.CONTROL_COMMON4 |
| TCELL23:IMUX.IMUX.26.DELAY | RFADC.TEST_SCAN_CTRL2 |
| TCELL23:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_CTRL3 |
| TCELL23:IMUX.IMUX.38.DELAY | RFADC.TEST_SI118 |
| TCELL23:IMUX.IMUX.47.DELAY | RFADC.TEST_SI119 |
| TCELL24:OUT.1.TMIN | RFADC.DATA_ADC1_117 |
| TCELL24:OUT.3.TMIN | RFADC.TEST_SO120 |
| TCELL24:OUT.4.TMIN | RFADC.STATUS_COMMON3 |
| TCELL24:OUT.6.TMIN | RFADC.DATA_ADC1_118 |
| TCELL24:OUT.8.TMIN | RFADC.DATA_ADC1_119 |
| TCELL24:OUT.10.TMIN | RFADC.DATA_ADC1_120 |
| TCELL24:OUT.11.TMIN | RFADC.TEST_SO121 |
| TCELL24:OUT.12.TMIN | RFADC.DATA_ADC1_121 |
| TCELL24:OUT.14.TMIN | RFADC.DATA_ADC1_122 |
| TCELL24:OUT.16.TMIN | RFADC.DATA_ADC1_123 |
| TCELL24:OUT.17.TMIN | RFADC.TEST_STATUS4 |
| TCELL24:OUT.18.TMIN | RFADC.DATA_ADC1_124 |
| TCELL24:OUT.20.TMIN | RFADC.DATA_ADC1_125 |
| TCELL24:OUT.21.TMIN | RFADC.TEST_SO122 |
| TCELL24:OUT.22.TMIN | RFADC.DATA_ADC1_126 |
| TCELL24:OUT.24.TMIN | RFADC.DATA_ADC1_127 |
| TCELL24:OUT.26.TMIN | RFADC.DATA_ADC1_128 |
| TCELL24:OUT.27.TMIN | RFADC.TEST_SO123 |
| TCELL24:OUT.28.TMIN | RFADC.STATUS_COMMON4 |
| TCELL24:OUT.30.TMIN | RFADC.DATA_ADC1_129 |
| TCELL24:OUT.31.TMIN | RFADC.TEST_SO124 |
| TCELL24:IMUX.IMUX.7.DELAY | RFADC.TEST_SI122 |
| TCELL24:IMUX.IMUX.12.DELAY | RFADC.CONTROL_COMMON7 |
| TCELL24:IMUX.IMUX.17.DELAY | RFADC.TEST_SI120 |
| TCELL24:IMUX.IMUX.22.DELAY | RFADC.TEST_SI121 |
| TCELL24:IMUX.IMUX.23.DELAY | RFADC.CONTROL_COMMON6 |
| TCELL24:IMUX.IMUX.26.DELAY | RFADC.TEST_SCAN_CTRL4 |
| TCELL24:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_CTRL5 |
| TCELL24:IMUX.IMUX.38.DELAY | RFADC.TEST_SI123 |
| TCELL24:IMUX.IMUX.47.DELAY | RFADC.TEST_SI124 |
| TCELL25:OUT.1.TMIN | RFADC.DATA_ADC1_130 |
| TCELL25:OUT.3.TMIN | RFADC.TEST_SO125 |
| TCELL25:OUT.4.TMIN | RFADC.STATUS_COMMON5 |
| TCELL25:OUT.6.TMIN | RFADC.DATA_ADC1_131 |
| TCELL25:OUT.8.TMIN | RFADC.DATA_ADC1_132 |
| TCELL25:OUT.10.TMIN | RFADC.DATA_ADC1_133 |
| TCELL25:OUT.11.TMIN | RFADC.TEST_SO126 |
| TCELL25:OUT.12.TMIN | RFADC.DATA_ADC1_134 |
| TCELL25:OUT.14.TMIN | RFADC.DATA_ADC1_135 |
| TCELL25:OUT.16.TMIN | RFADC.DATA_ADC1_136 |
| TCELL25:OUT.17.TMIN | RFADC.TEST_STATUS5 |
| TCELL25:OUT.18.TMIN | RFADC.DATA_ADC1_137 |
| TCELL25:OUT.20.TMIN | RFADC.DATA_ADC1_138 |
| TCELL25:OUT.21.TMIN | RFADC.TEST_SO127 |
| TCELL25:OUT.22.TMIN | RFADC.DATA_ADC1_139 |
| TCELL25:OUT.24.TMIN | RFADC.DATA_ADC1_140 |
| TCELL25:OUT.26.TMIN | RFADC.DATA_ADC1_141 |
| TCELL25:OUT.27.TMIN | RFADC.TEST_SO128 |
| TCELL25:OUT.28.TMIN | RFADC.DOUT0 |
| TCELL25:OUT.30.TMIN | RFADC.DATA_ADC1_142 |
| TCELL25:OUT.31.TMIN | RFADC.TEST_SO129 |
| TCELL25:IMUX.IMUX.7.DELAY | RFADC.TEST_SI127 |
| TCELL25:IMUX.IMUX.8.DELAY | RFADC.DI1 |
| TCELL25:IMUX.IMUX.12.DELAY | RFADC.DI2 |
| TCELL25:IMUX.IMUX.17.DELAY | RFADC.TEST_SI125 |
| TCELL25:IMUX.IMUX.22.DELAY | RFADC.TEST_SI126 |
| TCELL25:IMUX.IMUX.23.DELAY | RFADC.DI0 |
| TCELL25:IMUX.IMUX.26.DELAY | RFADC.TEST_SCAN_CTRL6 |
| TCELL25:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_CTRL7 |
| TCELL25:IMUX.IMUX.38.DELAY | RFADC.TEST_SI128 |
| TCELL25:IMUX.IMUX.47.DELAY | RFADC.TEST_SI129 |
| TCELL26:OUT.0.TMIN | RFADC.STATUS_COMMON6 |
| TCELL26:OUT.2.TMIN | RFADC.DATA_ADC1_143 |
| TCELL26:OUT.3.TMIN | RFADC.TEST_SO130 |
| TCELL26:OUT.4.TMIN | RFADC.DOUT1 |
| TCELL26:OUT.6.TMIN | RFADC.DATA_ADC1_144 |
| TCELL26:OUT.8.TMIN | RFADC.DATA_ADC1_145 |
| TCELL26:OUT.10.TMIN | RFADC.DATA_ADC1_146 |
| TCELL26:OUT.11.TMIN | RFADC.TEST_SO131 |
| TCELL26:OUT.12.TMIN | RFADC.DATA_ADC1_147 |
| TCELL26:OUT.14.TMIN | RFADC.DATA_ADC1_148 |
| TCELL26:OUT.16.TMIN | RFADC.DATA_ADC1_149 |
| TCELL26:OUT.17.TMIN | RFADC.TEST_STATUS6 |
| TCELL26:OUT.18.TMIN | RFADC.DATA_ADC1_150 |
| TCELL26:OUT.20.TMIN | RFADC.DATA_ADC1_151 |
| TCELL26:OUT.21.TMIN | RFADC.TEST_SO132 |
| TCELL26:OUT.22.TMIN | RFADC.DATA_ADC1_152 |
| TCELL26:OUT.24.TMIN | RFADC.DATA_ADC1_153 |
| TCELL26:OUT.26.TMIN | RFADC.DATA_ADC1_154 |
| TCELL26:OUT.27.TMIN | RFADC.TEST_SO133 |
| TCELL26:OUT.28.TMIN | RFADC.DOUT2 |
| TCELL26:OUT.30.TMIN | RFADC.DATA_ADC1_155 |
| TCELL26:OUT.31.TMIN | RFADC.TEST_SO134 |
| TCELL26:IMUX.IMUX.7.DELAY | RFADC.TEST_SI132 |
| TCELL26:IMUX.IMUX.8.DELAY | RFADC.DI4 |
| TCELL26:IMUX.IMUX.12.DELAY | RFADC.DI5 |
| TCELL26:IMUX.IMUX.17.DELAY | RFADC.TEST_SI130 |
| TCELL26:IMUX.IMUX.22.DELAY | RFADC.TEST_SI131 |
| TCELL26:IMUX.IMUX.23.DELAY | RFADC.DI3 |
| TCELL26:IMUX.IMUX.38.DELAY | RFADC.TEST_SI133 |
| TCELL26:IMUX.IMUX.47.DELAY | RFADC.TEST_SI134 |
| TCELL27:OUT.0.TMIN | RFADC.STATUS_COMMON7 |
| TCELL27:OUT.2.TMIN | RFADC.DATA_ADC1_156 |
| TCELL27:OUT.3.TMIN | RFADC.TEST_SO135 |
| TCELL27:OUT.4.TMIN | RFADC.DOUT3 |
| TCELL27:OUT.5.TMIN | RFADC.TEST_SO136 |
| TCELL27:OUT.6.TMIN | RFADC.DATA_ADC1_157 |
| TCELL27:OUT.8.TMIN | RFADC.DATA_ADC1_158 |
| TCELL27:OUT.10.TMIN | RFADC.DATA_ADC1_159 |
| TCELL27:OUT.11.TMIN | RFADC.TEST_SO137 |
| TCELL27:OUT.12.TMIN | RFADC.DATA_ADC1_160 |
| TCELL27:OUT.14.TMIN | RFADC.DATA_ADC1_161 |
| TCELL27:OUT.15.TMIN | RFADC.TEST_SO138 |
| TCELL27:OUT.16.TMIN | RFADC.DATA_ADC1_162 |
| TCELL27:OUT.17.TMIN | RFADC.TEST_STATUS7 |
| TCELL27:OUT.18.TMIN | RFADC.DATA_ADC1_163 |
| TCELL27:OUT.20.TMIN | RFADC.DATA_ADC1_164 |
| TCELL27:OUT.21.TMIN | RFADC.TEST_SO139 |
| TCELL27:OUT.22.TMIN | RFADC.DATA_ADC1_165 |
| TCELL27:OUT.24.TMIN | RFADC.DATA_ADC1_166 |
| TCELL27:OUT.26.TMIN | RFADC.DATA_ADC1_167 |
| TCELL27:OUT.27.TMIN | RFADC.TEST_SO140 |
| TCELL27:OUT.28.TMIN | RFADC.DOUT4 |
| TCELL27:OUT.29.TMIN | RFADC.TEST_SO141 |
| TCELL27:OUT.30.TMIN | RFADC.DATA_ADC1_168 |
| TCELL27:OUT.31.TMIN | RFADC.TEST_SO142 |
| TCELL27:IMUX.CTRL.5 | RFADC.TEST_SCAN_CLK2 |
| TCELL27:IMUX.IMUX.7.DELAY | RFADC.TEST_SI138 |
| TCELL27:IMUX.IMUX.8.DELAY | RFADC.DI7 |
| TCELL27:IMUX.IMUX.12.DELAY | RFADC.DI8 |
| TCELL27:IMUX.IMUX.17.DELAY | RFADC.TEST_SI135 |
| TCELL27:IMUX.IMUX.22.DELAY | RFADC.TEST_SI136 |
| TCELL27:IMUX.IMUX.23.DELAY | RFADC.DI6 |
| TCELL27:IMUX.IMUX.24.DELAY | RFADC.TEST_SI137 |
| TCELL27:IMUX.IMUX.32.DELAY | RFADC.TEST_SI139 |
| TCELL27:IMUX.IMUX.36.DELAY | RFADC.PLL_SCAN_MODE_B_FD |
| TCELL27:IMUX.IMUX.38.DELAY | RFADC.TEST_SI140 |
| TCELL27:IMUX.IMUX.43.DELAY | RFADC.TEST_SI141 |
| TCELL27:IMUX.IMUX.47.DELAY | RFADC.TEST_SI142 |
| TCELL28:OUT.1.TMIN | RFADC.DATA_ADC1_169 |
| TCELL28:OUT.3.TMIN | RFADC.TEST_SO143 |
| TCELL28:OUT.4.TMIN | RFADC.DOUT5 |
| TCELL28:OUT.6.TMIN | RFADC.DATA_ADC1_170 |
| TCELL28:OUT.8.TMIN | RFADC.DATA_ADC1_171 |
| TCELL28:OUT.10.TMIN | RFADC.DATA_ADC1_172 |
| TCELL28:OUT.11.TMIN | RFADC.TEST_SO144 |
| TCELL28:OUT.12.TMIN | RFADC.DATA_ADC1_173 |
| TCELL28:OUT.14.TMIN | RFADC.DATA_ADC1_174 |
| TCELL28:OUT.16.TMIN | RFADC.DATA_ADC1_175 |
| TCELL28:OUT.17.TMIN | RFADC.PLL_SCAN_OUT_B_FD0 |
| TCELL28:OUT.18.TMIN | RFADC.DATA_ADC1_176 |
| TCELL28:OUT.19.TMIN | RFADC.TEST_SO145 |
| TCELL28:OUT.20.TMIN | RFADC.DATA_ADC1_177 |
| TCELL28:OUT.21.TMIN | RFADC.TEST_SO146 |
| TCELL28:OUT.22.TMIN | RFADC.DATA_ADC1_178 |
| TCELL28:OUT.24.TMIN | RFADC.DATA_ADC1_179 |
| TCELL28:OUT.26.TMIN | RFADC.DATA_ADC1_180 |
| TCELL28:OUT.27.TMIN | RFADC.TEST_SO147 |
| TCELL28:OUT.28.TMIN | RFADC.DOUT6 |
| TCELL28:OUT.29.TMIN | RFADC.TEST_SO148 |
| TCELL28:OUT.30.TMIN | RFADC.DATA_ADC1_181 |
| TCELL28:OUT.31.TMIN | RFADC.TEST_SO149 |
| TCELL28:IMUX.CTRL.4 | RFADC.DCLK |
| TCELL28:IMUX.CTRL.5 | RFADC.PLL_SCAN_CLK_FD0 |
| TCELL28:IMUX.IMUX.7.DELAY | RFADC.TEST_SI146 |
| TCELL28:IMUX.IMUX.8.DELAY | RFADC.DI10 |
| TCELL28:IMUX.IMUX.12.DELAY | RFADC.DI11 |
| TCELL28:IMUX.IMUX.17.DELAY | RFADC.TEST_SI143 |
| TCELL28:IMUX.IMUX.18.DELAY | RFADC.TEST_SI144 |
| TCELL28:IMUX.IMUX.22.DELAY | RFADC.TEST_SI145 |
| TCELL28:IMUX.IMUX.23.DELAY | RFADC.DI9 |
| TCELL28:IMUX.IMUX.26.DELAY | RFADC.PLL_SCAN_EN_B_FD |
| TCELL28:IMUX.IMUX.34.DELAY | RFADC.TEST_SCAN_RESET |
| TCELL28:IMUX.IMUX.36.DELAY | RFADC.TEST_SE_B |
| TCELL28:IMUX.IMUX.38.DELAY | RFADC.TEST_SI147 |
| TCELL28:IMUX.IMUX.43.DELAY | RFADC.TEST_SI148 |
| TCELL28:IMUX.IMUX.47.DELAY | RFADC.TEST_SI149 |
| TCELL29:OUT.0.TMIN | RFADC.STATUS_COMMON8 |
| TCELL29:OUT.2.TMIN | RFADC.DATA_ADC1_182 |
| TCELL29:OUT.4.TMIN | RFADC.DOUT7 |
| TCELL29:OUT.6.TMIN | RFADC.DATA_ADC1_183 |
| TCELL29:OUT.8.TMIN | RFADC.DATA_ADC1_184 |
| TCELL29:OUT.10.TMIN | RFADC.DATA_ADC1_185 |
| TCELL29:OUT.12.TMIN | RFADC.DATA_ADC1_186 |
| TCELL29:OUT.14.TMIN | RFADC.DATA_ADC1_187 |
| TCELL29:OUT.16.TMIN | RFADC.DATA_ADC1_188 |
| TCELL29:OUT.18.TMIN | RFADC.DATA_ADC1_189 |
| TCELL29:OUT.20.TMIN | RFADC.DATA_ADC1_190 |
| TCELL29:OUT.22.TMIN | RFADC.DATA_ADC1_191 |
| TCELL29:OUT.24.TMIN | RFADC.STATUS_COMMON9 |
| TCELL29:OUT.26.TMIN | RFADC.STATUS_COMMON10 |
| TCELL29:OUT.28.TMIN | RFADC.DRDY |
| TCELL29:OUT.30.TMIN | RFADC.STATUS_COMMON11 |
| TCELL29:IMUX.IMUX.8.DELAY | RFADC.DI13 |
| TCELL29:IMUX.IMUX.12.DELAY | RFADC.DI14 |
| TCELL29:IMUX.IMUX.23.DELAY | RFADC.DI12 |
| TCELL30:OUT.0.TMIN | RFADC.STATUS_COMMON12 |
| TCELL30:OUT.2.TMIN | RFADC.STATUS_COMMON13 |
| TCELL30:OUT.4.TMIN | RFADC.DOUT8 |
| TCELL30:OUT.6.TMIN | RFADC.STATUS_COMMON14 |
| TCELL30:OUT.8.TMIN | RFADC.STATUS_COMMON15 |
| TCELL30:OUT.10.TMIN | RFADC.DATA_ADC2_0 |
| TCELL30:OUT.12.TMIN | RFADC.DATA_ADC2_1 |
| TCELL30:OUT.14.TMIN | RFADC.DATA_ADC2_2 |
| TCELL30:OUT.16.TMIN | RFADC.DATA_ADC2_3 |
| TCELL30:OUT.18.TMIN | RFADC.DATA_ADC2_4 |
| TCELL30:OUT.20.TMIN | RFADC.DATA_ADC2_5 |
| TCELL30:OUT.22.TMIN | RFADC.DATA_ADC2_6 |
| TCELL30:OUT.24.TMIN | RFADC.DATA_ADC2_7 |
| TCELL30:OUT.26.TMIN | RFADC.DATA_ADC2_8 |
| TCELL30:OUT.28.TMIN | RFADC.DOUT9 |
| TCELL30:OUT.30.TMIN | RFADC.DATA_ADC2_9 |
| TCELL30:IMUX.IMUX.8.DELAY | RFADC.DADDR0 |
| TCELL30:IMUX.IMUX.12.DELAY | RFADC.DADDR1 |
| TCELL30:IMUX.IMUX.23.DELAY | RFADC.DI15 |
| TCELL30:RCLK.IMUX.17 | BUFG_GT_SYNC14.CLK_IN |
| TCELL31:OUT.1.TMIN | RFADC.DATA_ADC2_10 |
| TCELL31:OUT.3.TMIN | RFADC.TEST_SO150 |
| TCELL31:OUT.4.TMIN | RFADC.DOUT10 |
| TCELL31:OUT.6.TMIN | RFADC.DATA_ADC2_11 |
| TCELL31:OUT.8.TMIN | RFADC.DATA_ADC2_12 |
| TCELL31:OUT.10.TMIN | RFADC.DATA_ADC2_13 |
| TCELL31:OUT.11.TMIN | RFADC.TEST_SO151 |
| TCELL31:OUT.12.TMIN | RFADC.DATA_ADC2_14 |
| TCELL31:OUT.14.TMIN | RFADC.DATA_ADC2_15 |
| TCELL31:OUT.16.TMIN | RFADC.DATA_ADC2_16 |
| TCELL31:OUT.17.TMIN | RFADC.PLL_SCAN_OUT_B_FD1 |
| TCELL31:OUT.18.TMIN | RFADC.DATA_ADC2_17 |
| TCELL31:OUT.19.TMIN | RFADC.TEST_SO152 |
| TCELL31:OUT.20.TMIN | RFADC.DATA_ADC2_18 |
| TCELL31:OUT.21.TMIN | RFADC.TEST_SO153 |
| TCELL31:OUT.22.TMIN | RFADC.DATA_ADC2_19 |
| TCELL31:OUT.24.TMIN | RFADC.DATA_ADC2_20 |
| TCELL31:OUT.26.TMIN | RFADC.DATA_ADC2_21 |
| TCELL31:OUT.27.TMIN | RFADC.TEST_SO154 |
| TCELL31:OUT.28.TMIN | RFADC.DOUT11 |
| TCELL31:OUT.29.TMIN | RFADC.TEST_SO155 |
| TCELL31:OUT.30.TMIN | RFADC.DATA_ADC2_22 |
| TCELL31:OUT.31.TMIN | RFADC.TEST_SO156 |
| TCELL31:IMUX.CTRL.4 | RFADC.PLL_SCAN_CLK_FD1 |
| TCELL31:IMUX.CTRL.5 | RFADC.FABRIC_CLK |
| TCELL31:IMUX.IMUX.7.DELAY | RFADC.TEST_SI153 |
| TCELL31:IMUX.IMUX.8.DELAY | RFADC.DADDR3 |
| TCELL31:IMUX.IMUX.12.DELAY | RFADC.DADDR4 |
| TCELL31:IMUX.IMUX.17.DELAY | RFADC.TEST_SI150 |
| TCELL31:IMUX.IMUX.18.DELAY | RFADC.TEST_SI151 |
| TCELL31:IMUX.IMUX.22.DELAY | RFADC.TEST_SI152 |
| TCELL31:IMUX.IMUX.23.DELAY | RFADC.DADDR2 |
| TCELL31:IMUX.IMUX.26.DELAY | RFADC.PLL_SCAN_IN_FD0 |
| TCELL31:IMUX.IMUX.32.DELAY | RFADC.TEST_SI154 |
| TCELL31:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_MODE_B |
| TCELL31:IMUX.IMUX.38.DELAY | RFADC.TEST_SI155 |
| TCELL31:IMUX.IMUX.43.DELAY | RFADC.TEST_SI156 |
| TCELL31:IMUX.IMUX.47.DELAY | RFADC.TEST_SI157 |
| TCELL32:OUT.0.TMIN | RFADC.STATUS_COMMON16 |
| TCELL32:OUT.2.TMIN | RFADC.DATA_ADC2_23 |
| TCELL32:OUT.3.TMIN | RFADC.TEST_SO157 |
| TCELL32:OUT.4.TMIN | RFADC.DOUT12 |
| TCELL32:OUT.6.TMIN | RFADC.DATA_ADC2_24 |
| TCELL32:OUT.8.TMIN | RFADC.DATA_ADC2_25 |
| TCELL32:OUT.10.TMIN | RFADC.DATA_ADC2_26 |
| TCELL32:OUT.11.TMIN | RFADC.TEST_SO158 |
| TCELL32:OUT.12.TMIN | RFADC.DATA_ADC2_27 |
| TCELL32:OUT.13.TMIN | RFADC.TEST_SO159 |
| TCELL32:OUT.14.TMIN | RFADC.DATA_ADC2_28 |
| TCELL32:OUT.16.TMIN | RFADC.DATA_ADC2_29 |
| TCELL32:OUT.17.TMIN | RFADC.TEST_STATUS8 |
| TCELL32:OUT.18.TMIN | RFADC.DATA_ADC2_30 |
| TCELL32:OUT.20.TMIN | RFADC.DATA_ADC2_31 |
| TCELL32:OUT.21.TMIN | RFADC.TEST_SO160 |
| TCELL32:OUT.22.TMIN | RFADC.DATA_ADC2_32 |
| TCELL32:OUT.24.TMIN | RFADC.DATA_ADC2_33 |
| TCELL32:OUT.26.TMIN | RFADC.DATA_ADC2_34 |
| TCELL32:OUT.27.TMIN | RFADC.TEST_SO161 |
| TCELL32:OUT.28.TMIN | RFADC.DOUT13 |
| TCELL32:OUT.30.TMIN | RFADC.DATA_ADC2_35 |
| TCELL32:OUT.31.TMIN | RFADC.TEST_SO162 |
| TCELL32:IMUX.CTRL.4 | RFADC.PLL_MONCLK |
| TCELL32:IMUX.CTRL.5 | RFADC.PLL_REFCLK_IN_FABRIC |
| TCELL32:IMUX.IMUX.7.DELAY | RFADC.TEST_SI161 |
| TCELL32:IMUX.IMUX.8.DELAY | RFADC.DADDR6 |
| TCELL32:IMUX.IMUX.12.DELAY | RFADC.DADDR7 |
| TCELL32:IMUX.IMUX.17.DELAY | RFADC.TEST_SI158 |
| TCELL32:IMUX.IMUX.22.DELAY | RFADC.TEST_SI159 |
| TCELL32:IMUX.IMUX.23.DELAY | RFADC.DADDR5 |
| TCELL32:IMUX.IMUX.24.DELAY | RFADC.TEST_SI160 |
| TCELL32:IMUX.IMUX.26.DELAY | RFADC.PLL_SCAN_IN_FD1 |
| TCELL32:IMUX.IMUX.38.DELAY | RFADC.TEST_SI162 |
| TCELL32:IMUX.IMUX.43.DELAY | RFADC.TEST_SI163 |
| TCELL32:IMUX.IMUX.47.DELAY | RFADC.TEST_SI164 |
| TCELL33:OUT.1.TMIN | RFADC.DATA_ADC2_36 |
| TCELL33:OUT.3.TMIN | RFADC.TEST_SO163 |
| TCELL33:OUT.4.TMIN | RFADC.DOUT14 |
| TCELL33:OUT.6.TMIN | RFADC.DATA_ADC2_37 |
| TCELL33:OUT.8.TMIN | RFADC.DATA_ADC2_38 |
| TCELL33:OUT.10.TMIN | RFADC.DATA_ADC2_39 |
| TCELL33:OUT.11.TMIN | RFADC.TEST_SO164 |
| TCELL33:OUT.12.TMIN | RFADC.DATA_ADC2_40 |
| TCELL33:OUT.14.TMIN | RFADC.DATA_ADC2_41 |
| TCELL33:OUT.15.TMIN | RFADC.TEST_SO165 |
| TCELL33:OUT.16.TMIN | RFADC.DATA_ADC2_42 |
| TCELL33:OUT.17.TMIN | RFADC.TEST_STATUS9 |
| TCELL33:OUT.18.TMIN | RFADC.DATA_ADC2_43 |
| TCELL33:OUT.20.TMIN | RFADC.DATA_ADC2_44 |
| TCELL33:OUT.21.TMIN | RFADC.TEST_SO166 |
| TCELL33:OUT.22.TMIN | RFADC.DATA_ADC2_45 |
| TCELL33:OUT.24.TMIN | RFADC.DATA_ADC2_46 |
| TCELL33:OUT.26.TMIN | RFADC.DATA_ADC2_47 |
| TCELL33:OUT.27.TMIN | RFADC.TEST_SO167 |
| TCELL33:OUT.28.TMIN | RFADC.DOUT15 |
| TCELL33:OUT.30.TMIN | RFADC.DATA_ADC2_48 |
| TCELL33:OUT.31.TMIN | RFADC.TEST_SO168 |
| TCELL33:IMUX.CTRL.5 | RFADC.CLK_FIFO_LM |
| TCELL33:IMUX.IMUX.7.DELAY | RFADC.TEST_SI167 |
| TCELL33:IMUX.IMUX.8.DELAY | RFADC.DADDR9 |
| TCELL33:IMUX.IMUX.12.DELAY | RFADC.DADDR10 |
| TCELL33:IMUX.IMUX.17.DELAY | RFADC.TEST_SI165 |
| TCELL33:IMUX.IMUX.22.DELAY | RFADC.TEST_SI166 |
| TCELL33:IMUX.IMUX.23.DELAY | RFADC.DADDR8 |
| TCELL33:IMUX.IMUX.26.DELAY | RFADC.PLL_SCAN_RST_EN_FD |
| TCELL33:IMUX.IMUX.38.DELAY | RFADC.TEST_SI168 |
| TCELL33:IMUX.IMUX.47.DELAY | RFADC.TEST_SI169 |
| TCELL34:OUT.1.TMIN | RFADC.DATA_ADC2_49 |
| TCELL34:OUT.3.TMIN | RFADC.TEST_SO169 |
| TCELL34:OUT.4.TMIN | RFADC.STATUS_COMMON17 |
| TCELL34:OUT.6.TMIN | RFADC.DATA_ADC2_50 |
| TCELL34:OUT.8.TMIN | RFADC.DATA_ADC2_51 |
| TCELL34:OUT.10.TMIN | RFADC.DATA_ADC2_52 |
| TCELL34:OUT.11.TMIN | RFADC.TEST_SO170 |
| TCELL34:OUT.12.TMIN | RFADC.DATA_ADC2_53 |
| TCELL34:OUT.14.TMIN | RFADC.DATA_ADC2_54 |
| TCELL34:OUT.16.TMIN | RFADC.DATA_ADC2_55 |
| TCELL34:OUT.17.TMIN | RFADC.TEST_STATUS10 |
| TCELL34:OUT.18.TMIN | RFADC.DATA_ADC2_56 |
| TCELL34:OUT.20.TMIN | RFADC.DATA_ADC2_57 |
| TCELL34:OUT.21.TMIN | RFADC.TEST_SO171 |
| TCELL34:OUT.22.TMIN | RFADC.DATA_ADC2_58 |
| TCELL34:OUT.24.TMIN | RFADC.DATA_ADC2_59 |
| TCELL34:OUT.26.TMIN | RFADC.DATA_ADC2_60 |
| TCELL34:OUT.27.TMIN | RFADC.TEST_SO172 |
| TCELL34:OUT.28.TMIN | RFADC.STATUS_COMMON18 |
| TCELL34:OUT.30.TMIN | RFADC.DATA_ADC2_61 |
| TCELL34:OUT.31.TMIN | RFADC.TEST_SO173 |
| TCELL34:IMUX.IMUX.7.DELAY | RFADC.TEST_SI172 |
| TCELL34:IMUX.IMUX.8.DELAY | RFADC.DEN |
| TCELL34:IMUX.IMUX.12.DELAY | RFADC.DADDR11 |
| TCELL34:IMUX.IMUX.17.DELAY | RFADC.TEST_SI170 |
| TCELL34:IMUX.IMUX.22.DELAY | RFADC.TEST_SI171 |
| TCELL34:IMUX.IMUX.23.DELAY | RFADC.DWE |
| TCELL34:IMUX.IMUX.26.DELAY | RFADC.TEST_SCAN_CTRL8 |
| TCELL34:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_CTRL9 |
| TCELL34:IMUX.IMUX.38.DELAY | RFADC.TEST_SI173 |
| TCELL34:IMUX.IMUX.47.DELAY | RFADC.TEST_SI174 |
| TCELL35:OUT.1.TMIN | RFADC.DATA_ADC2_62 |
| TCELL35:OUT.3.TMIN | RFADC.TEST_SO174 |
| TCELL35:OUT.4.TMIN | RFADC.STATUS_COMMON19 |
| TCELL35:OUT.6.TMIN | RFADC.DATA_ADC2_63 |
| TCELL35:OUT.8.TMIN | RFADC.DATA_ADC2_64 |
| TCELL35:OUT.10.TMIN | RFADC.DATA_ADC2_65 |
| TCELL35:OUT.11.TMIN | RFADC.TEST_SO175 |
| TCELL35:OUT.12.TMIN | RFADC.DATA_ADC2_66 |
| TCELL35:OUT.14.TMIN | RFADC.DATA_ADC2_67 |
| TCELL35:OUT.15.TMIN | RFADC.TEST_SO176 |
| TCELL35:OUT.16.TMIN | RFADC.DATA_ADC2_68 |
| TCELL35:OUT.17.TMIN | RFADC.TEST_STATUS11 |
| TCELL35:OUT.18.TMIN | RFADC.DATA_ADC2_69 |
| TCELL35:OUT.20.TMIN | RFADC.DATA_ADC2_70 |
| TCELL35:OUT.21.TMIN | RFADC.TEST_SO177 |
| TCELL35:OUT.22.TMIN | RFADC.DATA_ADC2_71 |
| TCELL35:OUT.24.TMIN | RFADC.DATA_ADC2_72 |
| TCELL35:OUT.26.TMIN | RFADC.DATA_ADC2_73 |
| TCELL35:OUT.27.TMIN | RFADC.TEST_SO178 |
| TCELL35:OUT.28.TMIN | RFADC.STATUS_COMMON20 |
| TCELL35:OUT.30.TMIN | RFADC.DATA_ADC2_74 |
| TCELL35:OUT.31.TMIN | RFADC.TEST_SO179 |
| TCELL35:IMUX.IMUX.7.DELAY | RFADC.TEST_SI177 |
| TCELL35:IMUX.IMUX.12.DELAY | RFADC.CONTROL_COMMON9 |
| TCELL35:IMUX.IMUX.17.DELAY | RFADC.TEST_SI175 |
| TCELL35:IMUX.IMUX.22.DELAY | RFADC.TEST_SI176 |
| TCELL35:IMUX.IMUX.23.DELAY | RFADC.CONTROL_COMMON8 |
| TCELL35:IMUX.IMUX.26.DELAY | RFADC.TEST_SCAN_CTRL10 |
| TCELL35:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_CTRL11 |
| TCELL35:IMUX.IMUX.38.DELAY | RFADC.TEST_SI178 |
| TCELL35:IMUX.IMUX.47.DELAY | RFADC.TEST_SI179 |
| TCELL36:OUT.1.TMIN | RFADC.DATA_ADC2_75 |
| TCELL36:OUT.3.TMIN | RFADC.TEST_SO180 |
| TCELL36:OUT.4.TMIN | RFADC.STATUS_COMMON21 |
| TCELL36:OUT.6.TMIN | RFADC.DATA_ADC2_76 |
| TCELL36:OUT.8.TMIN | RFADC.DATA_ADC2_77 |
| TCELL36:OUT.10.TMIN | RFADC.DATA_ADC2_78 |
| TCELL36:OUT.11.TMIN | RFADC.TEST_SO181 |
| TCELL36:OUT.12.TMIN | RFADC.DATA_ADC2_79 |
| TCELL36:OUT.14.TMIN | RFADC.DATA_ADC2_80 |
| TCELL36:OUT.16.TMIN | RFADC.DATA_ADC2_81 |
| TCELL36:OUT.17.TMIN | RFADC.TEST_STATUS12 |
| TCELL36:OUT.18.TMIN | RFADC.DATA_ADC2_82 |
| TCELL36:OUT.20.TMIN | RFADC.DATA_ADC2_83 |
| TCELL36:OUT.21.TMIN | RFADC.TEST_SO182 |
| TCELL36:OUT.22.TMIN | RFADC.DATA_ADC2_84 |
| TCELL36:OUT.24.TMIN | RFADC.DATA_ADC2_85 |
| TCELL36:OUT.26.TMIN | RFADC.DATA_ADC2_86 |
| TCELL36:OUT.27.TMIN | RFADC.TEST_SO183 |
| TCELL36:OUT.28.TMIN | RFADC.STATUS_COMMON22 |
| TCELL36:OUT.30.TMIN | RFADC.DATA_ADC2_87 |
| TCELL36:OUT.31.TMIN | RFADC.TEST_SO184 |
| TCELL36:IMUX.IMUX.7.DELAY | RFADC.TEST_SI182 |
| TCELL36:IMUX.IMUX.12.DELAY | RFADC.CONTROL_COMMON11 |
| TCELL36:IMUX.IMUX.17.DELAY | RFADC.TEST_SI180 |
| TCELL36:IMUX.IMUX.22.DELAY | RFADC.TEST_SI181 |
| TCELL36:IMUX.IMUX.23.DELAY | RFADC.CONTROL_COMMON10 |
| TCELL36:IMUX.IMUX.26.DELAY | RFADC.TEST_SCAN_CTRL12 |
| TCELL36:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_CTRL13 |
| TCELL36:IMUX.IMUX.38.DELAY | RFADC.TEST_SI183 |
| TCELL36:IMUX.IMUX.47.DELAY | RFADC.TEST_SI184 |
| TCELL37:OUT.1.TMIN | RFADC.DATA_ADC2_88 |
| TCELL37:OUT.3.TMIN | RFADC.TEST_SO185 |
| TCELL37:OUT.4.TMIN | RFADC.STATUS_ADC2_0 |
| TCELL37:OUT.6.TMIN | RFADC.DATA_ADC2_89 |
| TCELL37:OUT.8.TMIN | RFADC.DATA_ADC2_90 |
| TCELL37:OUT.10.TMIN | RFADC.DATA_ADC2_91 |
| TCELL37:OUT.11.TMIN | RFADC.TEST_SO186 |
| TCELL37:OUT.12.TMIN | RFADC.DATA_ADC2_92 |
| TCELL37:OUT.14.TMIN | RFADC.DATA_ADC2_93 |
| TCELL37:OUT.16.TMIN | RFADC.DATA_ADC2_94 |
| TCELL37:OUT.17.TMIN | RFADC.TEST_STATUS13 |
| TCELL37:OUT.18.TMIN | RFADC.DATA_ADC2_95 |
| TCELL37:OUT.20.TMIN | RFADC.DATA_ADC2_96 |
| TCELL37:OUT.21.TMIN | RFADC.TEST_SO187 |
| TCELL37:OUT.22.TMIN | RFADC.DATA_ADC2_97 |
| TCELL37:OUT.24.TMIN | RFADC.DATA_ADC2_98 |
| TCELL37:OUT.26.TMIN | RFADC.DATA_ADC2_99 |
| TCELL37:OUT.27.TMIN | RFADC.TEST_SO188 |
| TCELL37:OUT.28.TMIN | RFADC.STATUS_COMMON23 |
| TCELL37:OUT.30.TMIN | RFADC.DATA_ADC2_100 |
| TCELL37:OUT.31.TMIN | RFADC.TEST_SO189 |
| TCELL37:IMUX.IMUX.7.DELAY | RFADC.TEST_SI187 |
| TCELL37:IMUX.IMUX.8.DELAY | RFADC.CONTROL_COMMON13 |
| TCELL37:IMUX.IMUX.12.DELAY | RFADC.CONTROL_COMMON14 |
| TCELL37:IMUX.IMUX.17.DELAY | RFADC.TEST_SI185 |
| TCELL37:IMUX.IMUX.22.DELAY | RFADC.TEST_SI186 |
| TCELL37:IMUX.IMUX.23.DELAY | RFADC.CONTROL_COMMON12 |
| TCELL37:IMUX.IMUX.26.DELAY | RFADC.TEST_SCAN_CTRL14 |
| TCELL37:IMUX.IMUX.36.DELAY | RFADC.TEST_SCAN_CTRL15 |
| TCELL37:IMUX.IMUX.38.DELAY | RFADC.TEST_SI188 |
| TCELL37:IMUX.IMUX.47.DELAY | RFADC.TEST_SI189 |
| TCELL38:OUT.1.TMIN | RFADC.DATA_ADC2_101 |
| TCELL38:OUT.3.TMIN | RFADC.TEST_SO190 |
| TCELL38:OUT.4.TMIN | RFADC.STATUS_ADC2_1 |
| TCELL38:OUT.6.TMIN | RFADC.DATA_ADC2_102 |
| TCELL38:OUT.8.TMIN | RFADC.DATA_ADC2_103 |
| TCELL38:OUT.10.TMIN | RFADC.DATA_ADC2_104 |
| TCELL38:OUT.11.TMIN | RFADC.TEST_SO191 |
| TCELL38:OUT.12.TMIN | RFADC.DATA_ADC2_105 |
| TCELL38:OUT.14.TMIN | RFADC.DATA_ADC2_106 |
| TCELL38:OUT.16.TMIN | RFADC.DATA_ADC2_107 |
| TCELL38:OUT.17.TMIN | RFADC.TEST_STATUS14 |
| TCELL38:OUT.18.TMIN | RFADC.DATA_ADC2_108 |
| TCELL38:OUT.20.TMIN | RFADC.DATA_ADC2_109 |
| TCELL38:OUT.21.TMIN | RFADC.TEST_SO192 |
| TCELL38:OUT.22.TMIN | RFADC.DATA_ADC2_110 |
| TCELL38:OUT.24.TMIN | RFADC.DATA_ADC2_111 |
| TCELL38:OUT.26.TMIN | RFADC.DATA_ADC2_112 |
| TCELL38:OUT.27.TMIN | RFADC.TEST_SO193 |
| TCELL38:OUT.28.TMIN | RFADC.STATUS_ADC2_2 |
| TCELL38:OUT.30.TMIN | RFADC.DATA_ADC2_113 |
| TCELL38:OUT.31.TMIN | RFADC.TEST_SO194 |
| TCELL38:IMUX.IMUX.7.DELAY | RFADC.TEST_SI192 |
| TCELL38:IMUX.IMUX.8.DELAY | RFADC.CONTROL_COMMON15 |
| TCELL38:IMUX.IMUX.17.DELAY | RFADC.TEST_SI190 |
| TCELL38:IMUX.IMUX.22.DELAY | RFADC.TEST_SI191 |
| TCELL38:IMUX.IMUX.38.DELAY | RFADC.TEST_SI193 |
| TCELL38:IMUX.IMUX.47.DELAY | RFADC.TEST_SI194 |
| TCELL39:OUT.1.TMIN | RFADC.DATA_ADC2_114 |
| TCELL39:OUT.3.TMIN | RFADC.TEST_SO195 |
| TCELL39:OUT.4.TMIN | RFADC.STATUS_ADC2_3 |
| TCELL39:OUT.6.TMIN | RFADC.DATA_ADC2_115 |
| TCELL39:OUT.8.TMIN | RFADC.DATA_ADC2_116 |
| TCELL39:OUT.10.TMIN | RFADC.DATA_ADC2_117 |
| TCELL39:OUT.11.TMIN | RFADC.TEST_SO196 |
| TCELL39:OUT.12.TMIN | RFADC.DATA_ADC2_118 |
| TCELL39:OUT.14.TMIN | RFADC.DATA_ADC2_119 |
| TCELL39:OUT.16.TMIN | RFADC.DATA_ADC2_120 |
| TCELL39:OUT.17.TMIN | RFADC.TEST_STATUS15 |
| TCELL39:OUT.18.TMIN | RFADC.DATA_ADC2_121 |
| TCELL39:OUT.20.TMIN | RFADC.DATA_ADC2_122 |
| TCELL39:OUT.21.TMIN | RFADC.TEST_SO197 |
| TCELL39:OUT.22.TMIN | RFADC.DATA_ADC2_123 |
| TCELL39:OUT.24.TMIN | RFADC.DATA_ADC2_124 |
| TCELL39:OUT.26.TMIN | RFADC.DATA_ADC2_125 |
| TCELL39:OUT.27.TMIN | RFADC.TEST_SO198 |
| TCELL39:OUT.28.TMIN | RFADC.STATUS_ADC2_4 |
| TCELL39:OUT.30.TMIN | RFADC.DATA_ADC2_126 |
| TCELL39:OUT.31.TMIN | RFADC.TEST_SO199 |
| TCELL39:IMUX.IMUX.7.DELAY | RFADC.TEST_SI197 |
| TCELL39:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC2_1 |
| TCELL39:IMUX.IMUX.17.DELAY | RFADC.TEST_SI195 |
| TCELL39:IMUX.IMUX.22.DELAY | RFADC.TEST_SI196 |
| TCELL39:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC2_0 |
| TCELL39:IMUX.IMUX.38.DELAY | RFADC.TEST_SI198 |
| TCELL39:IMUX.IMUX.47.DELAY | RFADC.TEST_SI199 |
| TCELL40:OUT.1.TMIN | RFADC.DATA_ADC2_127 |
| TCELL40:OUT.3.TMIN | RFADC.TEST_SO200 |
| TCELL40:OUT.4.TMIN | RFADC.STATUS_ADC2_5 |
| TCELL40:OUT.6.TMIN | RFADC.DATA_ADC2_128 |
| TCELL40:OUT.8.TMIN | RFADC.DATA_ADC2_129 |
| TCELL40:OUT.10.TMIN | RFADC.DATA_ADC2_130 |
| TCELL40:OUT.11.TMIN | RFADC.TEST_SO201 |
| TCELL40:OUT.12.TMIN | RFADC.DATA_ADC2_131 |
| TCELL40:OUT.14.TMIN | RFADC.DATA_ADC2_132 |
| TCELL40:OUT.16.TMIN | RFADC.DATA_ADC2_133 |
| TCELL40:OUT.18.TMIN | RFADC.DATA_ADC2_134 |
| TCELL40:OUT.20.TMIN | RFADC.DATA_ADC2_135 |
| TCELL40:OUT.21.TMIN | RFADC.TEST_SO202 |
| TCELL40:OUT.22.TMIN | RFADC.DATA_ADC2_136 |
| TCELL40:OUT.24.TMIN | RFADC.DATA_ADC2_137 |
| TCELL40:OUT.26.TMIN | RFADC.DATA_ADC2_138 |
| TCELL40:OUT.27.TMIN | RFADC.TEST_SO203 |
| TCELL40:OUT.28.TMIN | RFADC.STATUS_ADC2_6 |
| TCELL40:OUT.30.TMIN | RFADC.DATA_ADC2_139 |
| TCELL40:OUT.31.TMIN | RFADC.TEST_SO204 |
| TCELL40:IMUX.IMUX.7.DELAY | RFADC.TEST_SI202 |
| TCELL40:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC2_3 |
| TCELL40:IMUX.IMUX.17.DELAY | RFADC.TEST_SI200 |
| TCELL40:IMUX.IMUX.22.DELAY | RFADC.TEST_SI201 |
| TCELL40:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC2_2 |
| TCELL40:IMUX.IMUX.38.DELAY | RFADC.TEST_SI203 |
| TCELL40:IMUX.IMUX.47.DELAY | RFADC.TEST_SI204 |
| TCELL41:OUT.1.TMIN | RFADC.DATA_ADC2_140 |
| TCELL41:OUT.3.TMIN | RFADC.TEST_SO205 |
| TCELL41:OUT.4.TMIN | RFADC.STATUS_ADC2_7 |
| TCELL41:OUT.6.TMIN | RFADC.DATA_ADC2_141 |
| TCELL41:OUT.8.TMIN | RFADC.DATA_ADC2_142 |
| TCELL41:OUT.10.TMIN | RFADC.DATA_ADC2_143 |
| TCELL41:OUT.11.TMIN | RFADC.TEST_SO206 |
| TCELL41:OUT.12.TMIN | RFADC.DATA_ADC2_144 |
| TCELL41:OUT.14.TMIN | RFADC.DATA_ADC2_145 |
| TCELL41:OUT.16.TMIN | RFADC.DATA_ADC2_146 |
| TCELL41:OUT.18.TMIN | RFADC.DATA_ADC2_147 |
| TCELL41:OUT.20.TMIN | RFADC.DATA_ADC2_148 |
| TCELL41:OUT.21.TMIN | RFADC.TEST_SO207 |
| TCELL41:OUT.22.TMIN | RFADC.DATA_ADC2_149 |
| TCELL41:OUT.24.TMIN | RFADC.DATA_ADC2_150 |
| TCELL41:OUT.26.TMIN | RFADC.DATA_ADC2_151 |
| TCELL41:OUT.27.TMIN | RFADC.TEST_SO208 |
| TCELL41:OUT.28.TMIN | RFADC.STATUS_ADC2_8 |
| TCELL41:OUT.30.TMIN | RFADC.DATA_ADC2_152 |
| TCELL41:OUT.31.TMIN | RFADC.TEST_SO209 |
| TCELL41:IMUX.CTRL.5 | RFADC.TEST_SCAN_CLK3 |
| TCELL41:IMUX.IMUX.7.DELAY | RFADC.TEST_SI207 |
| TCELL41:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC2_4 |
| TCELL41:IMUX.IMUX.17.DELAY | RFADC.TEST_SI205 |
| TCELL41:IMUX.IMUX.22.DELAY | RFADC.TEST_SI206 |
| TCELL41:IMUX.IMUX.38.DELAY | RFADC.TEST_SI208 |
| TCELL41:IMUX.IMUX.47.DELAY | RFADC.TEST_SI209 |
| TCELL42:OUT.1.TMIN | RFADC.DATA_ADC2_153 |
| TCELL42:OUT.3.TMIN | RFADC.TEST_SO210 |
| TCELL42:OUT.4.TMIN | RFADC.STATUS_ADC2_9 |
| TCELL42:OUT.6.TMIN | RFADC.DATA_ADC2_154 |
| TCELL42:OUT.8.TMIN | RFADC.DATA_ADC2_155 |
| TCELL42:OUT.10.TMIN | RFADC.DATA_ADC2_156 |
| TCELL42:OUT.11.TMIN | RFADC.TEST_SO211 |
| TCELL42:OUT.12.TMIN | RFADC.DATA_ADC2_157 |
| TCELL42:OUT.14.TMIN | RFADC.DATA_ADC2_158 |
| TCELL42:OUT.16.TMIN | RFADC.DATA_ADC2_159 |
| TCELL42:OUT.18.TMIN | RFADC.DATA_ADC2_160 |
| TCELL42:OUT.20.TMIN | RFADC.DATA_ADC2_161 |
| TCELL42:OUT.21.TMIN | RFADC.TEST_SO212 |
| TCELL42:OUT.22.TMIN | RFADC.DATA_ADC2_162 |
| TCELL42:OUT.24.TMIN | RFADC.DATA_ADC2_163 |
| TCELL42:OUT.26.TMIN | RFADC.DATA_ADC2_164 |
| TCELL42:OUT.27.TMIN | RFADC.TEST_SO213 |
| TCELL42:OUT.28.TMIN | RFADC.STATUS_ADC2_10 |
| TCELL42:OUT.30.TMIN | RFADC.DATA_ADC2_165 |
| TCELL42:OUT.31.TMIN | RFADC.TEST_SO214 |
| TCELL42:IMUX.IMUX.7.DELAY | RFADC.TEST_SI212 |
| TCELL42:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC2_6 |
| TCELL42:IMUX.IMUX.17.DELAY | RFADC.TEST_SI210 |
| TCELL42:IMUX.IMUX.22.DELAY | RFADC.TEST_SI211 |
| TCELL42:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC2_5 |
| TCELL42:IMUX.IMUX.38.DELAY | RFADC.TEST_SI213 |
| TCELL42:IMUX.IMUX.47.DELAY | RFADC.TEST_SI214 |
| TCELL43:OUT.1.TMIN | RFADC.DATA_ADC2_166 |
| TCELL43:OUT.3.TMIN | RFADC.TEST_SO215 |
| TCELL43:OUT.4.TMIN | RFADC.STATUS_ADC2_11 |
| TCELL43:OUT.6.TMIN | RFADC.DATA_ADC2_167 |
| TCELL43:OUT.8.TMIN | RFADC.DATA_ADC2_168 |
| TCELL43:OUT.10.TMIN | RFADC.DATA_ADC2_169 |
| TCELL43:OUT.11.TMIN | RFADC.TEST_SO216 |
| TCELL43:OUT.12.TMIN | RFADC.DATA_ADC2_170 |
| TCELL43:OUT.14.TMIN | RFADC.DATA_ADC2_171 |
| TCELL43:OUT.16.TMIN | RFADC.DATA_ADC2_172 |
| TCELL43:OUT.18.TMIN | RFADC.DATA_ADC2_173 |
| TCELL43:OUT.20.TMIN | RFADC.DATA_ADC2_174 |
| TCELL43:OUT.21.TMIN | RFADC.TEST_SO217 |
| TCELL43:OUT.22.TMIN | RFADC.DATA_ADC2_175 |
| TCELL43:OUT.24.TMIN | RFADC.DATA_ADC2_176 |
| TCELL43:OUT.26.TMIN | RFADC.DATA_ADC2_177 |
| TCELL43:OUT.27.TMIN | RFADC.TEST_SO218 |
| TCELL43:OUT.28.TMIN | RFADC.STATUS_ADC2_12 |
| TCELL43:OUT.30.TMIN | RFADC.DATA_ADC2_178 |
| TCELL43:OUT.31.TMIN | RFADC.TEST_SO219 |
| TCELL43:IMUX.IMUX.7.DELAY | RFADC.TEST_SI217 |
| TCELL43:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC2_7 |
| TCELL43:IMUX.IMUX.17.DELAY | RFADC.TEST_SI215 |
| TCELL43:IMUX.IMUX.22.DELAY | RFADC.TEST_SI216 |
| TCELL43:IMUX.IMUX.38.DELAY | RFADC.TEST_SI218 |
| TCELL43:IMUX.IMUX.47.DELAY | RFADC.TEST_SI219 |
| TCELL44:OUT.1.TMIN | RFADC.DATA_ADC2_179 |
| TCELL44:OUT.3.TMIN | RFADC.TEST_SO220 |
| TCELL44:OUT.4.TMIN | RFADC.STATUS_ADC2_13 |
| TCELL44:OUT.6.TMIN | RFADC.DATA_ADC2_180 |
| TCELL44:OUT.8.TMIN | RFADC.DATA_ADC2_181 |
| TCELL44:OUT.10.TMIN | RFADC.DATA_ADC2_182 |
| TCELL44:OUT.11.TMIN | RFADC.TEST_SO221 |
| TCELL44:OUT.12.TMIN | RFADC.DATA_ADC2_183 |
| TCELL44:OUT.14.TMIN | RFADC.DATA_ADC2_184 |
| TCELL44:OUT.16.TMIN | RFADC.DATA_ADC2_185 |
| TCELL44:OUT.18.TMIN | RFADC.DATA_ADC2_186 |
| TCELL44:OUT.20.TMIN | RFADC.DATA_ADC2_187 |
| TCELL44:OUT.21.TMIN | RFADC.TEST_SO222 |
| TCELL44:OUT.22.TMIN | RFADC.DATA_ADC2_188 |
| TCELL44:OUT.24.TMIN | RFADC.DATA_ADC2_189 |
| TCELL44:OUT.26.TMIN | RFADC.DATA_ADC2_190 |
| TCELL44:OUT.27.TMIN | RFADC.TEST_SO223 |
| TCELL44:OUT.28.TMIN | RFADC.STATUS_ADC2_14 |
| TCELL44:OUT.30.TMIN | RFADC.DATA_ADC2_191 |
| TCELL44:OUT.31.TMIN | RFADC.TEST_SO224 |
| TCELL44:IMUX.IMUX.7.DELAY | RFADC.TEST_SI222 |
| TCELL44:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC2_9 |
| TCELL44:IMUX.IMUX.17.DELAY | RFADC.TEST_SI220 |
| TCELL44:IMUX.IMUX.22.DELAY | RFADC.TEST_SI221 |
| TCELL44:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC2_8 |
| TCELL44:IMUX.IMUX.38.DELAY | RFADC.TEST_SI223 |
| TCELL44:IMUX.IMUX.47.DELAY | RFADC.TEST_SI224 |
| TCELL45:OUT.1.TMIN | RFADC.DATA_ADC3_0 |
| TCELL45:OUT.3.TMIN | RFADC.TEST_SO225 |
| TCELL45:OUT.4.TMIN | RFADC.STATUS_ADC2_15 |
| TCELL45:OUT.6.TMIN | RFADC.DATA_ADC3_1 |
| TCELL45:OUT.8.TMIN | RFADC.DATA_ADC3_2 |
| TCELL45:OUT.10.TMIN | RFADC.DATA_ADC3_3 |
| TCELL45:OUT.11.TMIN | RFADC.TEST_SO226 |
| TCELL45:OUT.12.TMIN | RFADC.DATA_ADC3_4 |
| TCELL45:OUT.14.TMIN | RFADC.DATA_ADC3_5 |
| TCELL45:OUT.16.TMIN | RFADC.DATA_ADC3_6 |
| TCELL45:OUT.18.TMIN | RFADC.DATA_ADC3_7 |
| TCELL45:OUT.20.TMIN | RFADC.DATA_ADC3_8 |
| TCELL45:OUT.21.TMIN | RFADC.TEST_SO227 |
| TCELL45:OUT.22.TMIN | RFADC.DATA_ADC3_9 |
| TCELL45:OUT.24.TMIN | RFADC.DATA_ADC3_10 |
| TCELL45:OUT.26.TMIN | RFADC.DATA_ADC3_11 |
| TCELL45:OUT.27.TMIN | RFADC.TEST_SO228 |
| TCELL45:OUT.28.TMIN | RFADC.STATUS_ADC2_16 |
| TCELL45:OUT.30.TMIN | RFADC.DATA_ADC3_12 |
| TCELL45:OUT.31.TMIN | RFADC.TEST_SO229 |
| TCELL45:IMUX.IMUX.7.DELAY | RFADC.TEST_SI227 |
| TCELL45:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC2_10 |
| TCELL45:IMUX.IMUX.17.DELAY | RFADC.TEST_SI225 |
| TCELL45:IMUX.IMUX.22.DELAY | RFADC.TEST_SI226 |
| TCELL45:IMUX.IMUX.38.DELAY | RFADC.TEST_SI228 |
| TCELL45:IMUX.IMUX.47.DELAY | RFADC.TEST_SI229 |
| TCELL46:OUT.1.TMIN | RFADC.DATA_ADC3_13 |
| TCELL46:OUT.3.TMIN | RFADC.TEST_SO230 |
| TCELL46:OUT.4.TMIN | RFADC.STATUS_ADC2_17 |
| TCELL46:OUT.6.TMIN | RFADC.DATA_ADC3_14 |
| TCELL46:OUT.8.TMIN | RFADC.DATA_ADC3_15 |
| TCELL46:OUT.10.TMIN | RFADC.DATA_ADC3_16 |
| TCELL46:OUT.11.TMIN | RFADC.TEST_SO231 |
| TCELL46:OUT.12.TMIN | RFADC.DATA_ADC3_17 |
| TCELL46:OUT.14.TMIN | RFADC.DATA_ADC3_18 |
| TCELL46:OUT.16.TMIN | RFADC.DATA_ADC3_19 |
| TCELL46:OUT.18.TMIN | RFADC.DATA_ADC3_20 |
| TCELL46:OUT.20.TMIN | RFADC.DATA_ADC3_21 |
| TCELL46:OUT.21.TMIN | RFADC.TEST_SO232 |
| TCELL46:OUT.22.TMIN | RFADC.DATA_ADC3_22 |
| TCELL46:OUT.24.TMIN | RFADC.DATA_ADC3_23 |
| TCELL46:OUT.26.TMIN | RFADC.DATA_ADC3_24 |
| TCELL46:OUT.27.TMIN | RFADC.TEST_SO233 |
| TCELL46:OUT.28.TMIN | RFADC.STATUS_ADC2_18 |
| TCELL46:OUT.30.TMIN | RFADC.DATA_ADC3_25 |
| TCELL46:OUT.31.TMIN | RFADC.TEST_SO234 |
| TCELL46:IMUX.IMUX.7.DELAY | RFADC.TEST_SI232 |
| TCELL46:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC2_12 |
| TCELL46:IMUX.IMUX.17.DELAY | RFADC.TEST_SI230 |
| TCELL46:IMUX.IMUX.22.DELAY | RFADC.TEST_SI231 |
| TCELL46:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC2_11 |
| TCELL46:IMUX.IMUX.38.DELAY | RFADC.TEST_SI233 |
| TCELL46:IMUX.IMUX.47.DELAY | RFADC.TEST_SI234 |
| TCELL47:OUT.1.TMIN | RFADC.DATA_ADC3_26 |
| TCELL47:OUT.3.TMIN | RFADC.TEST_SO235 |
| TCELL47:OUT.4.TMIN | RFADC.STATUS_ADC2_19 |
| TCELL47:OUT.6.TMIN | RFADC.DATA_ADC3_27 |
| TCELL47:OUT.8.TMIN | RFADC.DATA_ADC3_28 |
| TCELL47:OUT.10.TMIN | RFADC.DATA_ADC3_29 |
| TCELL47:OUT.11.TMIN | RFADC.TEST_SO236 |
| TCELL47:OUT.12.TMIN | RFADC.DATA_ADC3_30 |
| TCELL47:OUT.14.TMIN | RFADC.DATA_ADC3_31 |
| TCELL47:OUT.16.TMIN | RFADC.DATA_ADC3_32 |
| TCELL47:OUT.18.TMIN | RFADC.DATA_ADC3_33 |
| TCELL47:OUT.20.TMIN | RFADC.DATA_ADC3_34 |
| TCELL47:OUT.21.TMIN | RFADC.TEST_SO237 |
| TCELL47:OUT.22.TMIN | RFADC.DATA_ADC3_35 |
| TCELL47:OUT.24.TMIN | RFADC.DATA_ADC3_36 |
| TCELL47:OUT.26.TMIN | RFADC.DATA_ADC3_37 |
| TCELL47:OUT.27.TMIN | RFADC.TEST_SO238 |
| TCELL47:OUT.28.TMIN | RFADC.STATUS_ADC2_20 |
| TCELL47:OUT.30.TMIN | RFADC.DATA_ADC3_38 |
| TCELL47:OUT.31.TMIN | RFADC.TEST_SO239 |
| TCELL47:IMUX.IMUX.7.DELAY | RFADC.TEST_SI237 |
| TCELL47:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC2_13 |
| TCELL47:IMUX.IMUX.10.DELAY | ABUS_SWITCH_GT0.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT1.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT2.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT3.TEST_ANALOGBUS_SEL_B |
| TCELL47:IMUX.IMUX.11.DELAY | ABUS_SWITCH_GT4.TEST_ANALOGBUS_SEL_B |
| TCELL47:IMUX.IMUX.17.DELAY | RFADC.TEST_SI235 |
| TCELL47:IMUX.IMUX.22.DELAY | RFADC.TEST_SI236 |
| TCELL47:IMUX.IMUX.38.DELAY | RFADC.TEST_SI238 |
| TCELL47:IMUX.IMUX.47.DELAY | RFADC.TEST_SI239 |
| TCELL48:OUT.1.TMIN | RFADC.DATA_ADC3_39 |
| TCELL48:OUT.3.TMIN | RFADC.TEST_SO240 |
| TCELL48:OUT.4.TMIN | RFADC.STATUS_ADC2_21 |
| TCELL48:OUT.6.TMIN | RFADC.DATA_ADC3_40 |
| TCELL48:OUT.8.TMIN | RFADC.DATA_ADC3_41 |
| TCELL48:OUT.10.TMIN | RFADC.DATA_ADC3_42 |
| TCELL48:OUT.11.TMIN | RFADC.TEST_SO241 |
| TCELL48:OUT.12.TMIN | RFADC.DATA_ADC3_43 |
| TCELL48:OUT.14.TMIN | RFADC.DATA_ADC3_44 |
| TCELL48:OUT.16.TMIN | RFADC.DATA_ADC3_45 |
| TCELL48:OUT.18.TMIN | RFADC.DATA_ADC3_46 |
| TCELL48:OUT.20.TMIN | RFADC.DATA_ADC3_47 |
| TCELL48:OUT.21.TMIN | RFADC.TEST_SO242 |
| TCELL48:OUT.22.TMIN | RFADC.DATA_ADC3_48 |
| TCELL48:OUT.24.TMIN | RFADC.DATA_ADC3_49 |
| TCELL48:OUT.26.TMIN | RFADC.DATA_ADC3_50 |
| TCELL48:OUT.27.TMIN | RFADC.TEST_SO243 |
| TCELL48:OUT.28.TMIN | RFADC.STATUS_ADC2_22 |
| TCELL48:OUT.30.TMIN | RFADC.DATA_ADC3_51 |
| TCELL48:OUT.31.TMIN | RFADC.TEST_SO244 |
| TCELL48:IMUX.IMUX.7.DELAY | RFADC.TEST_SI242 |
| TCELL48:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC2_15 |
| TCELL48:IMUX.IMUX.17.DELAY | RFADC.TEST_SI240 |
| TCELL48:IMUX.IMUX.22.DELAY | RFADC.TEST_SI241 |
| TCELL48:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC2_14 |
| TCELL48:IMUX.IMUX.38.DELAY | RFADC.TEST_SI243 |
| TCELL48:IMUX.IMUX.47.DELAY | RFADC.TEST_SI244 |
| TCELL49:OUT.1.TMIN | RFADC.DATA_ADC3_52 |
| TCELL49:OUT.3.TMIN | RFADC.TEST_SO245 |
| TCELL49:OUT.4.TMIN | RFADC.STATUS_ADC2_23 |
| TCELL49:OUT.6.TMIN | RFADC.DATA_ADC3_53 |
| TCELL49:OUT.8.TMIN | RFADC.DATA_ADC3_54 |
| TCELL49:OUT.10.TMIN | RFADC.DATA_ADC3_55 |
| TCELL49:OUT.11.TMIN | RFADC.TEST_SO246 |
| TCELL49:OUT.12.TMIN | RFADC.DATA_ADC3_56 |
| TCELL49:OUT.14.TMIN | RFADC.DATA_ADC3_57 |
| TCELL49:OUT.16.TMIN | RFADC.DATA_ADC3_58 |
| TCELL49:OUT.18.TMIN | RFADC.DATA_ADC3_59 |
| TCELL49:OUT.20.TMIN | RFADC.DATA_ADC3_60 |
| TCELL49:OUT.21.TMIN | RFADC.TEST_SO247 |
| TCELL49:OUT.22.TMIN | RFADC.DATA_ADC3_61 |
| TCELL49:OUT.24.TMIN | RFADC.DATA_ADC3_62 |
| TCELL49:OUT.26.TMIN | RFADC.DATA_ADC3_63 |
| TCELL49:OUT.27.TMIN | RFADC.TEST_SO248 |
| TCELL49:OUT.28.TMIN | RFADC.STATUS_ADC3_0 |
| TCELL49:OUT.30.TMIN | RFADC.DATA_ADC3_64 |
| TCELL49:OUT.31.TMIN | RFADC.TEST_SO249 |
| TCELL49:IMUX.IMUX.7.DELAY | RFADC.TEST_SI247 |
| TCELL49:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC3_1 |
| TCELL49:IMUX.IMUX.17.DELAY | RFADC.TEST_SI245 |
| TCELL49:IMUX.IMUX.22.DELAY | RFADC.TEST_SI246 |
| TCELL49:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC3_0 |
| TCELL49:IMUX.IMUX.38.DELAY | RFADC.TEST_SI248 |
| TCELL49:IMUX.IMUX.47.DELAY | RFADC.TEST_SI249 |
| TCELL50:OUT.1.TMIN | RFADC.DATA_ADC3_65 |
| TCELL50:OUT.3.TMIN | RFADC.TEST_SO250 |
| TCELL50:OUT.4.TMIN | RFADC.STATUS_ADC3_1 |
| TCELL50:OUT.6.TMIN | RFADC.DATA_ADC3_66 |
| TCELL50:OUT.8.TMIN | RFADC.DATA_ADC3_67 |
| TCELL50:OUT.10.TMIN | RFADC.DATA_ADC3_68 |
| TCELL50:OUT.11.TMIN | RFADC.TEST_SO251 |
| TCELL50:OUT.12.TMIN | RFADC.DATA_ADC3_69 |
| TCELL50:OUT.14.TMIN | RFADC.DATA_ADC3_70 |
| TCELL50:OUT.16.TMIN | RFADC.DATA_ADC3_71 |
| TCELL50:OUT.18.TMIN | RFADC.DATA_ADC3_72 |
| TCELL50:OUT.20.TMIN | RFADC.DATA_ADC3_73 |
| TCELL50:OUT.21.TMIN | RFADC.TEST_SO252 |
| TCELL50:OUT.22.TMIN | RFADC.DATA_ADC3_74 |
| TCELL50:OUT.24.TMIN | RFADC.DATA_ADC3_75 |
| TCELL50:OUT.26.TMIN | RFADC.DATA_ADC3_76 |
| TCELL50:OUT.27.TMIN | RFADC.TEST_SO253 |
| TCELL50:OUT.28.TMIN | RFADC.STATUS_ADC3_2 |
| TCELL50:OUT.30.TMIN | RFADC.DATA_ADC3_77 |
| TCELL50:OUT.31.TMIN | RFADC.TEST_SO254 |
| TCELL50:IMUX.IMUX.7.DELAY | RFADC.TEST_SI252 |
| TCELL50:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC3_2 |
| TCELL50:IMUX.IMUX.17.DELAY | RFADC.TEST_SI250 |
| TCELL50:IMUX.IMUX.22.DELAY | RFADC.TEST_SI251 |
| TCELL50:IMUX.IMUX.38.DELAY | RFADC.TEST_SI253 |
| TCELL50:IMUX.IMUX.47.DELAY | RFADC.TEST_SI254 |
| TCELL51:OUT.1.TMIN | RFADC.DATA_ADC3_78 |
| TCELL51:OUT.3.TMIN | RFADC.TEST_SO255 |
| TCELL51:OUT.4.TMIN | RFADC.STATUS_ADC3_3 |
| TCELL51:OUT.6.TMIN | RFADC.DATA_ADC3_79 |
| TCELL51:OUT.8.TMIN | RFADC.DATA_ADC3_80 |
| TCELL51:OUT.10.TMIN | RFADC.DATA_ADC3_81 |
| TCELL51:OUT.11.TMIN | RFADC.TEST_SO256 |
| TCELL51:OUT.12.TMIN | RFADC.DATA_ADC3_82 |
| TCELL51:OUT.14.TMIN | RFADC.DATA_ADC3_83 |
| TCELL51:OUT.16.TMIN | RFADC.DATA_ADC3_84 |
| TCELL51:OUT.18.TMIN | RFADC.DATA_ADC3_85 |
| TCELL51:OUT.20.TMIN | RFADC.DATA_ADC3_86 |
| TCELL51:OUT.21.TMIN | RFADC.TEST_SO257 |
| TCELL51:OUT.22.TMIN | RFADC.DATA_ADC3_87 |
| TCELL51:OUT.24.TMIN | RFADC.DATA_ADC3_88 |
| TCELL51:OUT.26.TMIN | RFADC.DATA_ADC3_89 |
| TCELL51:OUT.27.TMIN | RFADC.TEST_SO258 |
| TCELL51:OUT.28.TMIN | RFADC.STATUS_ADC3_4 |
| TCELL51:OUT.30.TMIN | RFADC.DATA_ADC3_90 |
| TCELL51:OUT.31.TMIN | RFADC.TEST_SO259 |
| TCELL51:IMUX.IMUX.7.DELAY | RFADC.TEST_SI257 |
| TCELL51:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC3_4 |
| TCELL51:IMUX.IMUX.17.DELAY | RFADC.TEST_SI255 |
| TCELL51:IMUX.IMUX.22.DELAY | RFADC.TEST_SI256 |
| TCELL51:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC3_3 |
| TCELL51:IMUX.IMUX.38.DELAY | RFADC.TEST_SI258 |
| TCELL51:IMUX.IMUX.47.DELAY | RFADC.TEST_SI259 |
| TCELL52:OUT.1.TMIN | RFADC.DATA_ADC3_91 |
| TCELL52:OUT.3.TMIN | RFADC.TEST_SO260 |
| TCELL52:OUT.4.TMIN | RFADC.STATUS_ADC3_5 |
| TCELL52:OUT.6.TMIN | RFADC.DATA_ADC3_92 |
| TCELL52:OUT.8.TMIN | RFADC.DATA_ADC3_93 |
| TCELL52:OUT.10.TMIN | RFADC.DATA_ADC3_94 |
| TCELL52:OUT.11.TMIN | RFADC.TEST_SO261 |
| TCELL52:OUT.12.TMIN | RFADC.DATA_ADC3_95 |
| TCELL52:OUT.14.TMIN | RFADC.DATA_ADC3_96 |
| TCELL52:OUT.16.TMIN | RFADC.DATA_ADC3_97 |
| TCELL52:OUT.18.TMIN | RFADC.DATA_ADC3_98 |
| TCELL52:OUT.20.TMIN | RFADC.DATA_ADC3_99 |
| TCELL52:OUT.21.TMIN | RFADC.TEST_SO262 |
| TCELL52:OUT.22.TMIN | RFADC.DATA_ADC3_100 |
| TCELL52:OUT.24.TMIN | RFADC.DATA_ADC3_101 |
| TCELL52:OUT.26.TMIN | RFADC.DATA_ADC3_102 |
| TCELL52:OUT.27.TMIN | RFADC.TEST_SO263 |
| TCELL52:OUT.28.TMIN | RFADC.STATUS_ADC3_6 |
| TCELL52:OUT.30.TMIN | RFADC.DATA_ADC3_103 |
| TCELL52:OUT.31.TMIN | RFADC.TEST_SO264 |
| TCELL52:IMUX.IMUX.7.DELAY | RFADC.TEST_SI262 |
| TCELL52:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC3_5 |
| TCELL52:IMUX.IMUX.17.DELAY | RFADC.TEST_SI260 |
| TCELL52:IMUX.IMUX.22.DELAY | RFADC.TEST_SI261 |
| TCELL52:IMUX.IMUX.38.DELAY | RFADC.TEST_SI263 |
| TCELL52:IMUX.IMUX.47.DELAY | RFADC.TEST_SI264 |
| TCELL53:OUT.1.TMIN | RFADC.DATA_ADC3_104 |
| TCELL53:OUT.3.TMIN | RFADC.TEST_SO265 |
| TCELL53:OUT.4.TMIN | RFADC.STATUS_ADC3_7 |
| TCELL53:OUT.6.TMIN | RFADC.DATA_ADC3_105 |
| TCELL53:OUT.8.TMIN | RFADC.DATA_ADC3_106 |
| TCELL53:OUT.10.TMIN | RFADC.DATA_ADC3_107 |
| TCELL53:OUT.11.TMIN | RFADC.TEST_SO266 |
| TCELL53:OUT.12.TMIN | RFADC.DATA_ADC3_108 |
| TCELL53:OUT.14.TMIN | RFADC.DATA_ADC3_109 |
| TCELL53:OUT.16.TMIN | RFADC.DATA_ADC3_110 |
| TCELL53:OUT.18.TMIN | RFADC.DATA_ADC3_111 |
| TCELL53:OUT.20.TMIN | RFADC.DATA_ADC3_112 |
| TCELL53:OUT.21.TMIN | RFADC.TEST_SO267 |
| TCELL53:OUT.22.TMIN | RFADC.DATA_ADC3_113 |
| TCELL53:OUT.24.TMIN | RFADC.DATA_ADC3_114 |
| TCELL53:OUT.26.TMIN | RFADC.DATA_ADC3_115 |
| TCELL53:OUT.27.TMIN | RFADC.TEST_SO268 |
| TCELL53:OUT.28.TMIN | RFADC.STATUS_ADC3_8 |
| TCELL53:OUT.30.TMIN | RFADC.DATA_ADC3_116 |
| TCELL53:OUT.31.TMIN | RFADC.TEST_SO269 |
| TCELL53:IMUX.IMUX.7.DELAY | RFADC.TEST_SI267 |
| TCELL53:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC3_7 |
| TCELL53:IMUX.IMUX.17.DELAY | RFADC.TEST_SI265 |
| TCELL53:IMUX.IMUX.22.DELAY | RFADC.TEST_SI266 |
| TCELL53:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC3_6 |
| TCELL53:IMUX.IMUX.38.DELAY | RFADC.TEST_SI268 |
| TCELL53:IMUX.IMUX.47.DELAY | RFADC.TEST_SI269 |
| TCELL54:OUT.1.TMIN | RFADC.DATA_ADC3_117 |
| TCELL54:OUT.3.TMIN | RFADC.TEST_SO270 |
| TCELL54:OUT.4.TMIN | RFADC.STATUS_ADC3_9 |
| TCELL54:OUT.6.TMIN | RFADC.DATA_ADC3_118 |
| TCELL54:OUT.8.TMIN | RFADC.DATA_ADC3_119 |
| TCELL54:OUT.10.TMIN | RFADC.DATA_ADC3_120 |
| TCELL54:OUT.11.TMIN | RFADC.TEST_SO271 |
| TCELL54:OUT.12.TMIN | RFADC.DATA_ADC3_121 |
| TCELL54:OUT.14.TMIN | RFADC.DATA_ADC3_122 |
| TCELL54:OUT.16.TMIN | RFADC.DATA_ADC3_123 |
| TCELL54:OUT.18.TMIN | RFADC.DATA_ADC3_124 |
| TCELL54:OUT.20.TMIN | RFADC.DATA_ADC3_125 |
| TCELL54:OUT.21.TMIN | RFADC.TEST_SO272 |
| TCELL54:OUT.22.TMIN | RFADC.DATA_ADC3_126 |
| TCELL54:OUT.24.TMIN | RFADC.DATA_ADC3_127 |
| TCELL54:OUT.26.TMIN | RFADC.DATA_ADC3_128 |
| TCELL54:OUT.27.TMIN | RFADC.TEST_SO273 |
| TCELL54:OUT.28.TMIN | RFADC.STATUS_ADC3_10 |
| TCELL54:OUT.30.TMIN | RFADC.DATA_ADC3_129 |
| TCELL54:OUT.31.TMIN | RFADC.TEST_SO274 |
| TCELL54:IMUX.CTRL.5 | RFADC.TEST_SCAN_CLK4 |
| TCELL54:IMUX.IMUX.7.DELAY | RFADC.TEST_SI272 |
| TCELL54:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC3_8 |
| TCELL54:IMUX.IMUX.17.DELAY | RFADC.TEST_SI270 |
| TCELL54:IMUX.IMUX.22.DELAY | RFADC.TEST_SI271 |
| TCELL54:IMUX.IMUX.38.DELAY | RFADC.TEST_SI273 |
| TCELL54:IMUX.IMUX.47.DELAY | RFADC.TEST_SI274 |
| TCELL55:OUT.1.TMIN | RFADC.DATA_ADC3_130 |
| TCELL55:OUT.3.TMIN | RFADC.TEST_SO275 |
| TCELL55:OUT.4.TMIN | RFADC.STATUS_ADC3_11 |
| TCELL55:OUT.6.TMIN | RFADC.DATA_ADC3_131 |
| TCELL55:OUT.8.TMIN | RFADC.DATA_ADC3_132 |
| TCELL55:OUT.10.TMIN | RFADC.DATA_ADC3_133 |
| TCELL55:OUT.11.TMIN | RFADC.TEST_SO276 |
| TCELL55:OUT.12.TMIN | RFADC.DATA_ADC3_134 |
| TCELL55:OUT.14.TMIN | RFADC.DATA_ADC3_135 |
| TCELL55:OUT.16.TMIN | RFADC.DATA_ADC3_136 |
| TCELL55:OUT.18.TMIN | RFADC.DATA_ADC3_137 |
| TCELL55:OUT.20.TMIN | RFADC.DATA_ADC3_138 |
| TCELL55:OUT.21.TMIN | RFADC.TEST_SO277 |
| TCELL55:OUT.22.TMIN | RFADC.DATA_ADC3_139 |
| TCELL55:OUT.24.TMIN | RFADC.DATA_ADC3_140 |
| TCELL55:OUT.26.TMIN | RFADC.DATA_ADC3_141 |
| TCELL55:OUT.27.TMIN | RFADC.TEST_SO278 |
| TCELL55:OUT.28.TMIN | RFADC.STATUS_ADC3_12 |
| TCELL55:OUT.30.TMIN | RFADC.DATA_ADC3_142 |
| TCELL55:OUT.31.TMIN | RFADC.TEST_SO279 |
| TCELL55:IMUX.IMUX.7.DELAY | RFADC.TEST_SI277 |
| TCELL55:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC3_10 |
| TCELL55:IMUX.IMUX.17.DELAY | RFADC.TEST_SI275 |
| TCELL55:IMUX.IMUX.22.DELAY | RFADC.TEST_SI276 |
| TCELL55:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC3_9 |
| TCELL55:IMUX.IMUX.38.DELAY | RFADC.TEST_SI278 |
| TCELL55:IMUX.IMUX.47.DELAY | RFADC.TEST_SI279 |
| TCELL56:OUT.1.TMIN | RFADC.DATA_ADC3_143 |
| TCELL56:OUT.3.TMIN | RFADC.TEST_SO280 |
| TCELL56:OUT.4.TMIN | RFADC.STATUS_ADC3_13 |
| TCELL56:OUT.6.TMIN | RFADC.DATA_ADC3_144 |
| TCELL56:OUT.8.TMIN | RFADC.DATA_ADC3_145 |
| TCELL56:OUT.10.TMIN | RFADC.DATA_ADC3_146 |
| TCELL56:OUT.11.TMIN | RFADC.TEST_SO281 |
| TCELL56:OUT.12.TMIN | RFADC.DATA_ADC3_147 |
| TCELL56:OUT.14.TMIN | RFADC.DATA_ADC3_148 |
| TCELL56:OUT.16.TMIN | RFADC.DATA_ADC3_149 |
| TCELL56:OUT.18.TMIN | RFADC.DATA_ADC3_150 |
| TCELL56:OUT.20.TMIN | RFADC.DATA_ADC3_151 |
| TCELL56:OUT.21.TMIN | RFADC.TEST_SO282 |
| TCELL56:OUT.22.TMIN | RFADC.DATA_ADC3_152 |
| TCELL56:OUT.24.TMIN | RFADC.DATA_ADC3_153 |
| TCELL56:OUT.26.TMIN | RFADC.DATA_ADC3_154 |
| TCELL56:OUT.27.TMIN | RFADC.TEST_SO283 |
| TCELL56:OUT.28.TMIN | RFADC.STATUS_ADC3_14 |
| TCELL56:OUT.30.TMIN | RFADC.DATA_ADC3_155 |
| TCELL56:OUT.31.TMIN | RFADC.TEST_SO284 |
| TCELL56:IMUX.IMUX.7.DELAY | RFADC.TEST_SI282 |
| TCELL56:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC3_11 |
| TCELL56:IMUX.IMUX.17.DELAY | RFADC.TEST_SI280 |
| TCELL56:IMUX.IMUX.22.DELAY | RFADC.TEST_SI281 |
| TCELL56:IMUX.IMUX.38.DELAY | RFADC.TEST_SI283 |
| TCELL56:IMUX.IMUX.47.DELAY | RFADC.TEST_SI284 |
| TCELL57:OUT.1.TMIN | RFADC.DATA_ADC3_156 |
| TCELL57:OUT.3.TMIN | RFADC.TEST_SO285 |
| TCELL57:OUT.4.TMIN | RFADC.STATUS_ADC3_15 |
| TCELL57:OUT.6.TMIN | RFADC.DATA_ADC3_157 |
| TCELL57:OUT.8.TMIN | RFADC.DATA_ADC3_158 |
| TCELL57:OUT.10.TMIN | RFADC.DATA_ADC3_159 |
| TCELL57:OUT.11.TMIN | RFADC.TEST_SO286 |
| TCELL57:OUT.12.TMIN | RFADC.DATA_ADC3_160 |
| TCELL57:OUT.14.TMIN | RFADC.DATA_ADC3_161 |
| TCELL57:OUT.16.TMIN | RFADC.DATA_ADC3_162 |
| TCELL57:OUT.18.TMIN | RFADC.DATA_ADC3_163 |
| TCELL57:OUT.20.TMIN | RFADC.DATA_ADC3_164 |
| TCELL57:OUT.21.TMIN | RFADC.TEST_SO287 |
| TCELL57:OUT.22.TMIN | RFADC.DATA_ADC3_165 |
| TCELL57:OUT.24.TMIN | RFADC.DATA_ADC3_166 |
| TCELL57:OUT.26.TMIN | RFADC.DATA_ADC3_167 |
| TCELL57:OUT.27.TMIN | RFADC.TEST_SO288 |
| TCELL57:OUT.28.TMIN | RFADC.STATUS_ADC3_16 |
| TCELL57:OUT.30.TMIN | RFADC.DATA_ADC3_168 |
| TCELL57:OUT.31.TMIN | RFADC.TEST_SO289 |
| TCELL57:IMUX.IMUX.7.DELAY | RFADC.TEST_SI287 |
| TCELL57:IMUX.IMUX.12.DELAY | RFADC.CONTROL_ADC3_13 |
| TCELL57:IMUX.IMUX.17.DELAY | RFADC.TEST_SI285 |
| TCELL57:IMUX.IMUX.22.DELAY | RFADC.TEST_SI286 |
| TCELL57:IMUX.IMUX.23.DELAY | RFADC.CONTROL_ADC3_12 |
| TCELL57:IMUX.IMUX.38.DELAY | RFADC.TEST_SI288 |
| TCELL57:IMUX.IMUX.47.DELAY | RFADC.TEST_SI289 |
| TCELL58:OUT.1.TMIN | RFADC.DATA_ADC3_169 |
| TCELL58:OUT.3.TMIN | RFADC.TEST_SO290 |
| TCELL58:OUT.4.TMIN | RFADC.STATUS_ADC3_17 |
| TCELL58:OUT.6.TMIN | RFADC.DATA_ADC3_170 |
| TCELL58:OUT.8.TMIN | RFADC.DATA_ADC3_171 |
| TCELL58:OUT.10.TMIN | RFADC.DATA_ADC3_172 |
| TCELL58:OUT.11.TMIN | RFADC.TEST_SO291 |
| TCELL58:OUT.12.TMIN | RFADC.DATA_ADC3_173 |
| TCELL58:OUT.14.TMIN | RFADC.DATA_ADC3_174 |
| TCELL58:OUT.16.TMIN | RFADC.DATA_ADC3_175 |
| TCELL58:OUT.18.TMIN | RFADC.DATA_ADC3_176 |
| TCELL58:OUT.20.TMIN | RFADC.DATA_ADC3_177 |
| TCELL58:OUT.21.TMIN | RFADC.TEST_SO292 |
| TCELL58:OUT.22.TMIN | RFADC.DATA_ADC3_178 |
| TCELL58:OUT.24.TMIN | RFADC.DATA_ADC3_179 |
| TCELL58:OUT.26.TMIN | RFADC.DATA_ADC3_180 |
| TCELL58:OUT.27.TMIN | RFADC.TEST_SO293 |
| TCELL58:OUT.28.TMIN | RFADC.STATUS_ADC3_18 |
| TCELL58:OUT.30.TMIN | RFADC.DATA_ADC3_181 |
| TCELL58:OUT.31.TMIN | RFADC.TEST_SO294 |
| TCELL58:IMUX.IMUX.7.DELAY | RFADC.TEST_SI292 |
| TCELL58:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC3_14 |
| TCELL58:IMUX.IMUX.17.DELAY | RFADC.TEST_SI290 |
| TCELL58:IMUX.IMUX.22.DELAY | RFADC.TEST_SI291 |
| TCELL58:IMUX.IMUX.38.DELAY | RFADC.TEST_SI293 |
| TCELL58:IMUX.IMUX.47.DELAY | RFADC.TEST_SI294 |
| TCELL59:OUT.1.TMIN | RFADC.DATA_ADC3_182 |
| TCELL59:OUT.3.TMIN | RFADC.TEST_SO295 |
| TCELL59:OUT.4.TMIN | RFADC.STATUS_ADC3_19 |
| TCELL59:OUT.6.TMIN | RFADC.DATA_ADC3_183 |
| TCELL59:OUT.8.TMIN | RFADC.DATA_ADC3_184 |
| TCELL59:OUT.10.TMIN | RFADC.DATA_ADC3_185 |
| TCELL59:OUT.11.TMIN | RFADC.TEST_SO296 |
| TCELL59:OUT.12.TMIN | RFADC.STATUS_ADC3_20 |
| TCELL59:OUT.14.TMIN | RFADC.DATA_ADC3_186 |
| TCELL59:OUT.16.TMIN | RFADC.STATUS_ADC3_21 |
| TCELL59:OUT.18.TMIN | RFADC.DATA_ADC3_187 |
| TCELL59:OUT.20.TMIN | RFADC.STATUS_ADC3_22 |
| TCELL59:OUT.21.TMIN | RFADC.TEST_SO297 |
| TCELL59:OUT.22.TMIN | RFADC.DATA_ADC3_188 |
| TCELL59:OUT.24.TMIN | RFADC.STATUS_ADC3_23 |
| TCELL59:OUT.26.TMIN | RFADC.DATA_ADC3_189 |
| TCELL59:OUT.27.TMIN | RFADC.TEST_SO298 |
| TCELL59:OUT.28.TMIN | RFADC.DATA_ADC3_190 |
| TCELL59:OUT.30.TMIN | RFADC.DATA_ADC3_191 |
| TCELL59:OUT.31.TMIN | RFADC.TEST_SO299 |
| TCELL59:IMUX.IMUX.7.DELAY | RFADC.TEST_SI297 |
| TCELL59:IMUX.IMUX.8.DELAY | RFADC.CONTROL_ADC3_15 |
| TCELL59:IMUX.IMUX.17.DELAY | RFADC.TEST_SI295 |
| TCELL59:IMUX.IMUX.22.DELAY | RFADC.TEST_SI296 |
| TCELL59:IMUX.IMUX.38.DELAY | RFADC.TEST_SI298 |
| TCELL59:IMUX.IMUX.47.DELAY | RFADC.TEST_SI299 |