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Logic block

TODO: document

Tile CLB

Cells: 1

Switchbox INT

virtex CLB switchbox INT permanent buffers
DestinationSource
SINGLE_W_BUF[0]SINGLE_W[0]
SINGLE_W_BUF[1]SINGLE_W[1]
SINGLE_W_BUF[2]SINGLE_W[2]
SINGLE_W_BUF[3]SINGLE_W[3]
SINGLE_W_BUF[4]SINGLE_W[4]
SINGLE_W_BUF[5]SINGLE_W[5]
SINGLE_W_BUF[6]SINGLE_W[6]
SINGLE_W_BUF[7]SINGLE_W[7]
SINGLE_W_BUF[8]SINGLE_W[8]
SINGLE_W_BUF[9]SINGLE_W[9]
SINGLE_W_BUF[10]SINGLE_W[10]
SINGLE_W_BUF[11]SINGLE_W[11]
SINGLE_W_BUF[12]SINGLE_W[12]
SINGLE_W_BUF[13]SINGLE_W[13]
SINGLE_W_BUF[14]SINGLE_W[14]
SINGLE_W_BUF[15]SINGLE_W[15]
SINGLE_W_BUF[16]SINGLE_W[16]
SINGLE_W_BUF[17]SINGLE_W[17]
SINGLE_W_BUF[18]SINGLE_W[18]
SINGLE_W_BUF[19]SINGLE_W[19]
SINGLE_W_BUF[20]SINGLE_W[20]
SINGLE_W_BUF[21]SINGLE_W[21]
SINGLE_W_BUF[22]SINGLE_W[22]
SINGLE_W_BUF[23]SINGLE_W[23]
SINGLE_E_BUF[0]SINGLE_E[0]
SINGLE_E_BUF[1]SINGLE_E[1]
SINGLE_E_BUF[2]SINGLE_E[2]
SINGLE_E_BUF[3]SINGLE_E[3]
SINGLE_E_BUF[4]SINGLE_E[4]
SINGLE_E_BUF[5]SINGLE_E[5]
SINGLE_E_BUF[6]SINGLE_E[6]
SINGLE_E_BUF[7]SINGLE_E[7]
SINGLE_E_BUF[8]SINGLE_E[8]
SINGLE_E_BUF[9]SINGLE_E[9]
SINGLE_E_BUF[10]SINGLE_E[10]
SINGLE_E_BUF[11]SINGLE_E[11]
SINGLE_E_BUF[12]SINGLE_E[12]
SINGLE_E_BUF[13]SINGLE_E[13]
SINGLE_E_BUF[14]SINGLE_E[14]
SINGLE_E_BUF[15]SINGLE_E[15]
SINGLE_E_BUF[16]SINGLE_E[16]
SINGLE_E_BUF[17]SINGLE_E[17]
SINGLE_E_BUF[18]SINGLE_E[18]
SINGLE_E_BUF[19]SINGLE_E[19]
SINGLE_E_BUF[20]SINGLE_E[20]
SINGLE_E_BUF[21]SINGLE_E[21]
SINGLE_E_BUF[22]SINGLE_E[22]
SINGLE_E_BUF[23]SINGLE_E[23]
SINGLE_S_BUF[0]SINGLE_S[0]
SINGLE_S_BUF[1]SINGLE_S[1]
SINGLE_S_BUF[2]SINGLE_S[2]
SINGLE_S_BUF[3]SINGLE_S[3]
SINGLE_S_BUF[4]SINGLE_S[4]
SINGLE_S_BUF[5]SINGLE_S[5]
SINGLE_S_BUF[6]SINGLE_S[6]
SINGLE_S_BUF[7]SINGLE_S[7]
SINGLE_S_BUF[8]SINGLE_S[8]
SINGLE_S_BUF[9]SINGLE_S[9]
SINGLE_S_BUF[10]SINGLE_S[10]
SINGLE_S_BUF[11]SINGLE_S[11]
SINGLE_S_BUF[12]SINGLE_S[12]
SINGLE_S_BUF[13]SINGLE_S[13]
SINGLE_S_BUF[14]SINGLE_S[14]
SINGLE_S_BUF[15]SINGLE_S[15]
SINGLE_S_BUF[16]SINGLE_S[16]
SINGLE_S_BUF[17]SINGLE_S[17]
SINGLE_S_BUF[18]SINGLE_S[18]
SINGLE_S_BUF[19]SINGLE_S[19]
SINGLE_S_BUF[20]SINGLE_S[20]
SINGLE_S_BUF[21]SINGLE_S[21]
SINGLE_S_BUF[22]SINGLE_S[22]
SINGLE_S_BUF[23]SINGLE_S[23]
SINGLE_N_BUF[0]SINGLE_N[0]
SINGLE_N_BUF[1]SINGLE_N[1]
SINGLE_N_BUF[2]SINGLE_N[2]
SINGLE_N_BUF[3]SINGLE_N[3]
SINGLE_N_BUF[4]SINGLE_N[4]
SINGLE_N_BUF[5]SINGLE_N[5]
SINGLE_N_BUF[6]SINGLE_N[6]
SINGLE_N_BUF[7]SINGLE_N[7]
SINGLE_N_BUF[8]SINGLE_N[8]
SINGLE_N_BUF[9]SINGLE_N[9]
SINGLE_N_BUF[10]SINGLE_N[10]
SINGLE_N_BUF[11]SINGLE_N[11]
SINGLE_N_BUF[12]SINGLE_N[12]
SINGLE_N_BUF[13]SINGLE_N[13]
SINGLE_N_BUF[14]SINGLE_N[14]
SINGLE_N_BUF[15]SINGLE_N[15]
SINGLE_N_BUF[16]SINGLE_N[16]
SINGLE_N_BUF[17]SINGLE_N[17]
SINGLE_N_BUF[18]SINGLE_N[18]
SINGLE_N_BUF[19]SINGLE_N[19]
SINGLE_N_BUF[20]SINGLE_N[20]
SINGLE_N_BUF[21]SINGLE_N[21]
SINGLE_N_BUF[22]SINGLE_N[22]
SINGLE_N_BUF[23]SINGLE_N[23]
virtex CLB switchbox INT programmable buffers
DestinationSourceBit
HEX_H0[0]HEX_H0_MUX[0]MAIN[37][2]
HEX_H0[1]HEX_H0_MUX[1]MAIN[25][2]
HEX_H0[2]HEX_H0_MUX[2]MAIN[13][2]
HEX_H0[3]HEX_H0_MUX[3]MAIN[1][2]
HEX_H6[0]HEX_H6_MUX[0]MAIN[40][2]
HEX_H6[1]HEX_H6_MUX[1]MAIN[28][2]
HEX_H6[2]HEX_H6_MUX[2]MAIN[16][2]
HEX_H6[3]HEX_H6_MUX[3]MAIN[4][2]
HEX_V0[0]HEX_V0_MUX[0]MAIN[43][2]
HEX_V0[1]HEX_V0_MUX[1]MAIN[31][2]
HEX_V0[2]HEX_V0_MUX[2]MAIN[19][2]
HEX_V0[3]HEX_V0_MUX[3]MAIN[7][2]
HEX_V6[0]HEX_V6_MUX[0]MAIN[46][2]
HEX_V6[1]HEX_V6_MUX[1]MAIN[34][2]
HEX_V6[2]HEX_V6_MUX[2]MAIN[22][2]
HEX_V6[3]HEX_V6_MUX[3]MAIN[10][2]
LH[0]LH_MUX[0]!MAIN[34][13]
LH[6]LH_MUX[6]!MAIN[14][13]
LV[0]LV_MUX[0]!MAIN[36][13]
LV[6]LV_MUX[6]!MAIN[9][13]
virtex CLB switchbox INT pass gates
DestinationSourceBit
SINGLE_W[0]HEX_N3[0]!MAIN[47][2]
SINGLE_W[1]HEX_S3[3]!MAIN[3][3]
SINGLE_W[2]HEX_S3[0]!MAIN[42][3]
SINGLE_W[3]HEX_W6[0]!MAIN[43][3]
SINGLE_W[3]HEX_V3[0]MAIN[44][4]
SINGLE_W[4]HEX_V0[0]MAIN[40][4]
SINGLE_W[4]OMUX[1]MAIN[38][5]
SINGLE_W[5]HEX_H0[0]MAIN[37][4]
SINGLE_W[5]OMUX[1]MAIN[37][5]
SINGLE_W[6]HEX_H0[1]MAIN[35][4]
SINGLE_W[6]HEX_N3[2]!MAIN[35][3]
SINGLE_W[7]OMUX[0]MAIN[42][5]
SINGLE_W[8]HEX_V3[1]MAIN[33][4]
SINGLE_W[8]HEX_S6[2]!MAIN[33][3]
SINGLE_W[9]HEX_V6[1]MAIN[30][4]
SINGLE_W[9]OMUX[2]MAIN[32][5]
SINGLE_W[10]HEX_N6[2]!MAIN[25][3]
SINGLE_W[10]OMUX[3]MAIN[24][5]
SINGLE_W[11]HEX_W6[2]!MAIN[29][3]
SINGLE_W[11]OMUX[3]MAIN[29][5]
SINGLE_W[12]HEX_N3[1]!MAIN[23][2]
SINGLE_W[13]HEX_S3[2]!MAIN[28][3]
SINGLE_W[14]HEX_S3[1]!MAIN[18][3]
SINGLE_W[15]HEX_W6[1]!MAIN[19][3]
SINGLE_W[15]HEX_V3[2]MAIN[20][4]
SINGLE_W[16]HEX_V0[2]MAIN[16][4]
SINGLE_W[16]OMUX[5]MAIN[14][5]
SINGLE_W[17]HEX_H0[2]MAIN[13][4]
SINGLE_W[17]OMUX[5]MAIN[13][5]
SINGLE_W[18]HEX_H0[3]MAIN[11][4]
SINGLE_W[18]HEX_N3[3]!MAIN[11][3]
SINGLE_W[19]OMUX[4]MAIN[18][5]
SINGLE_W[20]HEX_V3[3]MAIN[9][4]
SINGLE_W[20]HEX_S6[3]!MAIN[9][3]
SINGLE_W[21]HEX_V6[3]MAIN[6][4]
SINGLE_W[21]OMUX[6]MAIN[8][5]
SINGLE_W[22]HEX_N6[3]!MAIN[1][3]
SINGLE_W[22]OMUX[7]MAIN[0][5]
SINGLE_W[23]HEX_W6[3]!MAIN[5][3]
SINGLE_W[23]OMUX[7]MAIN[5][5]
SINGLE_E[0]HEX_V6[0]MAIN[42][4]
SINGLE_E[0]HEX_S3[0]!MAIN[42][2]
SINGLE_E[1]HEX_V3[0]MAIN[45][4]
SINGLE_E[1]HEX_S6[0]!MAIN[45][3]
SINGLE_E[2]OMUX[0]MAIN[43][5]
SINGLE_E[3]HEX_E6[0]!MAIN[39][3]
SINGLE_E[3]OMUX[1]MAIN[39][5]
SINGLE_E[4]HEX_N3[2]!MAIN[35][2]
SINGLE_E[5]HEX_N6[0]!MAIN[37][3]
SINGLE_E[5]OMUX[1]MAIN[36][5]
SINGLE_E[6]HEX_E6[2]!MAIN[30][2]
SINGLE_E[6]OMUX[2]MAIN[31][5]
SINGLE_E[7]HEX_V3[1]MAIN[32][4]
SINGLE_E[8]OMUX[3]MAIN[26][5]
SINGLE_E[9]HEX_V0[1]MAIN[28][4]
SINGLE_E[9]HEX_S3[2]!MAIN[27][3]
SINGLE_E[10]HEX_H6[2]MAIN[23][4]
SINGLE_E[10]HEX_N3[1]!MAIN[23][3]
SINGLE_E[11]HEX_H6[1]MAIN[25][4]
SINGLE_E[11]OMUX[3]MAIN[25][5]
SINGLE_E[12]HEX_V6[2]MAIN[18][4]
SINGLE_E[12]HEX_S3[1]!MAIN[18][2]
SINGLE_E[13]HEX_V3[2]MAIN[21][4]
SINGLE_E[13]HEX_S6[1]!MAIN[21][3]
SINGLE_E[14]OMUX[4]MAIN[19][5]
SINGLE_E[15]HEX_E6[1]!MAIN[15][3]
SINGLE_E[15]OMUX[5]MAIN[15][5]
SINGLE_E[16]HEX_N3[3]!MAIN[11][2]
SINGLE_E[17]HEX_N6[1]!MAIN[13][3]
SINGLE_E[17]OMUX[5]MAIN[12][5]
SINGLE_E[18]HEX_E6[3]!MAIN[6][2]
SINGLE_E[18]OMUX[6]MAIN[7][5]
SINGLE_E[19]HEX_V3[3]MAIN[8][4]
SINGLE_E[20]OMUX[7]MAIN[2][5]
SINGLE_E[21]HEX_V0[3]MAIN[4][4]
SINGLE_E[21]HEX_S3[3]!MAIN[4][3]
SINGLE_E[22]HEX_H6[0]MAIN[47][4]
SINGLE_E[22]HEX_N3[0]!MAIN[47][3]
SINGLE_E[23]HEX_H6[3]MAIN[1][4]
SINGLE_E[23]OMUX[7]MAIN[1][5]
SINGLE_S[0]OMUX[1]MAIN[41][5]
SINGLE_S[1]HEX_S6[0]!MAIN[46][3]
SINGLE_S[1]OMUX[0]MAIN[47][5]
SINGLE_S[2]HEX_W3[0]!MAIN[41][2]
SINGLE_S[2]HEX_V0[0]MAIN[41][4]
SINGLE_S[3]HEX_W6[0]!MAIN[44][3]
SINGLE_S[3]OMUX[0]MAIN[44][5]
SINGLE_S[4]HEX_H0[0]MAIN[36][4]
SINGLE_S[4]HEX_E3[0]!MAIN[36][2]
SINGLE_S[5]HEX_S6[2]!MAIN[34][3]
SINGLE_S[5]OMUX[2]MAIN[35][5]
SINGLE_S[6]HEX_H3[0]MAIN[39][4]
SINGLE_S[6]HEX_E6[0]!MAIN[40][3]
SINGLE_S[7]OMUX[2]MAIN[33][5]
SINGLE_S[8]HEX_H6[1]MAIN[24][4]
SINGLE_S[8]HEX_E3[2]!MAIN[24][3]
SINGLE_S[9]HEX_H3[1]MAIN[27][4]
SINGLE_S[10]HEX_V0[1]MAIN[29][4]
SINGLE_S[10]OMUX[3]MAIN[27][5]
SINGLE_S[11]HEX_W3[2]!MAIN[31][3]
SINGLE_S[12]OMUX[5]MAIN[17][5]
SINGLE_S[13]HEX_S6[1]!MAIN[22][3]
SINGLE_S[13]OMUX[4]MAIN[23][5]
SINGLE_S[14]HEX_W3[1]!MAIN[17][2]
SINGLE_S[14]HEX_V0[2]MAIN[17][4]
SINGLE_S[15]HEX_W6[1]!MAIN[20][3]
SINGLE_S[15]OMUX[4]MAIN[20][5]
SINGLE_S[16]HEX_H0[2]MAIN[12][4]
SINGLE_S[16]HEX_E3[1]!MAIN[12][2]
SINGLE_S[17]HEX_S6[3]!MAIN[10][3]
SINGLE_S[17]OMUX[6]MAIN[11][5]
SINGLE_S[18]HEX_H3[2]MAIN[15][4]
SINGLE_S[18]HEX_E6[1]!MAIN[16][3]
SINGLE_S[19]OMUX[6]MAIN[9][5]
SINGLE_S[20]HEX_H6[3]MAIN[0][4]
SINGLE_S[20]HEX_E3[3]!MAIN[0][3]
SINGLE_S[21]HEX_H3[3]MAIN[3][4]
SINGLE_S[22]HEX_V0[3]MAIN[5][4]
SINGLE_S[22]OMUX[7]MAIN[3][5]
SINGLE_S[23]HEX_W3[3]!MAIN[7][3]
SINGLE_N[0]HEX_H6[0]MAIN[46][4]
SINGLE_N[0]OMUX[0]MAIN[46][5]
SINGLE_N[1]HEX_V6[0]MAIN[43][4]
SINGLE_N[1]OMUX[0]MAIN[45][5]
SINGLE_N[2]OMUX[1]MAIN[40][5]
SINGLE_N[3]HEX_W3[0]!MAIN[41][3]
SINGLE_N[4]HEX_H3[0]MAIN[38][4]
SINGLE_N[4]HEX_N6[0]!MAIN[38][3]
SINGLE_N[5]HEX_E3[0]!MAIN[36][3]
SINGLE_N[6]HEX_H0[1]MAIN[34][4]
SINGLE_N[6]OMUX[2]MAIN[34][5]
SINGLE_N[7]HEX_W3[2]!MAIN[32][3]
SINGLE_N[7]HEX_V6[1]MAIN[31][4]
SINGLE_N[8]HEX_E6[2]!MAIN[30][3]
SINGLE_N[8]OMUX[2]MAIN[30][5]
SINGLE_N[9]HEX_W6[2]!MAIN[29][2]
SINGLE_N[9]OMUX[3]MAIN[28][5]
SINGLE_N[10]HEX_H3[1]MAIN[26][4]
SINGLE_N[10]HEX_N6[2]!MAIN[26][3]
SINGLE_N[11]HEX_E3[2]!MAIN[24][2]
SINGLE_N[12]HEX_H6[2]MAIN[22][4]
SINGLE_N[12]OMUX[4]MAIN[22][5]
SINGLE_N[13]HEX_V6[2]MAIN[19][4]
SINGLE_N[13]OMUX[4]MAIN[21][5]
SINGLE_N[14]OMUX[5]MAIN[16][5]
SINGLE_N[15]HEX_W3[1]!MAIN[17][3]
SINGLE_N[16]HEX_H3[2]MAIN[14][4]
SINGLE_N[16]HEX_N6[1]!MAIN[14][3]
SINGLE_N[17]HEX_E3[1]!MAIN[12][3]
SINGLE_N[18]HEX_H0[3]MAIN[10][4]
SINGLE_N[18]OMUX[6]MAIN[10][5]
SINGLE_N[19]HEX_W3[3]!MAIN[8][3]
SINGLE_N[19]HEX_V6[3]MAIN[7][4]
SINGLE_N[20]HEX_E6[3]!MAIN[6][3]
SINGLE_N[20]OMUX[6]MAIN[6][5]
SINGLE_N[21]HEX_W6[3]!MAIN[5][2]
SINGLE_N[21]OMUX[7]MAIN[4][5]
SINGLE_N[22]HEX_H3[3]MAIN[2][4]
SINGLE_N[22]HEX_N6[3]!MAIN[2][3]
SINGLE_N[23]HEX_E3[3]!MAIN[0][2]
virtex CLB switchbox INT bidirectional pass gates
Side ASide BBit
SINGLE_W[0]SINGLE_E[0]MAIN[47][8]
SINGLE_W[0]SINGLE_S[2]MAIN[47][6]
SINGLE_W[0]SINGLE_N[23]MAIN[0][8]
SINGLE_W[1]SINGLE_E[1]MAIN[45][6]
SINGLE_W[1]SINGLE_S[23]MAIN[5][8]
SINGLE_W[1]SINGLE_N[20]MAIN[6][8]
SINGLE_W[2]SINGLE_E[2]MAIN[43][8]
SINGLE_W[2]SINGLE_S[0]MAIN[43][6]
SINGLE_W[2]SINGLE_N[1]MAIN[44][8]
SINGLE_W[3]SINGLE_E[3]MAIN[41][6]
SINGLE_W[3]SINGLE_S[21]MAIN[1][8]
SINGLE_W[3]SINGLE_N[22]MAIN[2][8]
SINGLE_W[4]SINGLE_E[4]MAIN[39][8]
SINGLE_W[4]SINGLE_S[6]MAIN[39][6]
SINGLE_W[4]SINGLE_N[3]MAIN[40][8]
SINGLE_W[5]SINGLE_E[5]MAIN[37][6]
SINGLE_W[5]SINGLE_S[3]MAIN[45][8]
SINGLE_W[5]SINGLE_N[0]MAIN[46][8]
SINGLE_W[6]SINGLE_E[6]MAIN[35][8]
SINGLE_W[6]SINGLE_S[4]MAIN[35][6]
SINGLE_W[6]SINGLE_N[5]MAIN[36][8]
SINGLE_W[7]SINGLE_E[7]MAIN[33][6]
SINGLE_W[7]SINGLE_S[1]MAIN[41][8]
SINGLE_W[7]SINGLE_N[2]MAIN[42][8]
SINGLE_W[8]SINGLE_E[8]MAIN[31][8]
SINGLE_W[8]SINGLE_S[10]MAIN[31][6]
SINGLE_W[8]SINGLE_N[7]MAIN[32][8]
SINGLE_W[9]SINGLE_E[9]MAIN[29][6]
SINGLE_W[9]SINGLE_S[7]MAIN[37][8]
SINGLE_W[9]SINGLE_N[4]MAIN[38][8]
SINGLE_W[10]SINGLE_E[10]MAIN[27][8]
SINGLE_W[10]SINGLE_S[8]MAIN[27][6]
SINGLE_W[10]SINGLE_N[9]MAIN[28][8]
SINGLE_W[11]SINGLE_E[11]MAIN[25][6]
SINGLE_W[11]SINGLE_S[5]MAIN[33][8]
SINGLE_W[11]SINGLE_N[6]MAIN[34][8]
SINGLE_W[12]SINGLE_E[12]MAIN[23][8]
SINGLE_W[12]SINGLE_S[14]MAIN[23][6]
SINGLE_W[12]SINGLE_N[11]MAIN[24][8]
SINGLE_W[13]SINGLE_E[13]MAIN[21][6]
SINGLE_W[13]SINGLE_S[11]MAIN[29][8]
SINGLE_W[13]SINGLE_N[8]MAIN[30][8]
SINGLE_W[14]SINGLE_E[14]MAIN[19][8]
SINGLE_W[14]SINGLE_S[12]MAIN[19][6]
SINGLE_W[14]SINGLE_N[13]MAIN[20][8]
SINGLE_W[15]SINGLE_E[15]MAIN[17][6]
SINGLE_W[15]SINGLE_S[9]MAIN[25][8]
SINGLE_W[15]SINGLE_N[10]MAIN[26][8]
SINGLE_W[16]SINGLE_E[16]MAIN[15][8]
SINGLE_W[16]SINGLE_S[18]MAIN[15][6]
SINGLE_W[16]SINGLE_N[15]MAIN[16][8]
SINGLE_W[17]SINGLE_E[17]MAIN[13][6]
SINGLE_W[17]SINGLE_S[15]MAIN[21][8]
SINGLE_W[17]SINGLE_N[12]MAIN[22][8]
SINGLE_W[18]SINGLE_E[18]MAIN[11][8]
SINGLE_W[18]SINGLE_S[16]MAIN[11][6]
SINGLE_W[18]SINGLE_N[17]MAIN[12][8]
SINGLE_W[19]SINGLE_E[19]MAIN[9][6]
SINGLE_W[19]SINGLE_S[13]MAIN[17][8]
SINGLE_W[19]SINGLE_N[14]MAIN[18][8]
SINGLE_W[20]SINGLE_E[20]MAIN[7][8]
SINGLE_W[20]SINGLE_S[22]MAIN[7][6]
SINGLE_W[20]SINGLE_N[19]MAIN[8][8]
SINGLE_W[21]SINGLE_E[21]MAIN[5][6]
SINGLE_W[21]SINGLE_S[19]MAIN[13][8]
SINGLE_W[21]SINGLE_N[16]MAIN[14][8]
SINGLE_W[22]SINGLE_E[22]MAIN[3][8]
SINGLE_W[22]SINGLE_S[20]MAIN[3][6]
SINGLE_W[22]SINGLE_N[21]MAIN[4][8]
SINGLE_W[23]SINGLE_E[23]MAIN[1][6]
SINGLE_W[23]SINGLE_S[17]MAIN[9][8]
SINGLE_W[23]SINGLE_N[18]MAIN[10][8]
SINGLE_E[0]SINGLE_S[6]MAIN[39][7]
SINGLE_E[0]SINGLE_N[4]MAIN[38][7]
SINGLE_E[1]SINGLE_S[3]MAIN[45][7]
SINGLE_E[1]SINGLE_N[1]MAIN[44][7]
SINGLE_E[2]SINGLE_S[4]MAIN[35][7]
SINGLE_E[2]SINGLE_N[6]MAIN[34][7]
SINGLE_E[3]SINGLE_S[1]MAIN[41][7]
SINGLE_E[3]SINGLE_N[3]MAIN[40][7]
SINGLE_E[4]SINGLE_S[10]MAIN[31][7]
SINGLE_E[4]SINGLE_N[8]MAIN[30][7]
SINGLE_E[5]SINGLE_S[7]MAIN[37][7]
SINGLE_E[5]SINGLE_N[5]MAIN[36][7]
SINGLE_E[6]SINGLE_S[8]MAIN[27][7]
SINGLE_E[6]SINGLE_N[10]MAIN[26][7]
SINGLE_E[7]SINGLE_S[5]MAIN[33][7]
SINGLE_E[7]SINGLE_N[7]MAIN[32][7]
SINGLE_E[8]SINGLE_S[14]MAIN[23][7]
SINGLE_E[8]SINGLE_N[12]MAIN[22][7]
SINGLE_E[9]SINGLE_S[11]MAIN[29][7]
SINGLE_E[9]SINGLE_N[9]MAIN[28][7]
SINGLE_E[10]SINGLE_S[12]MAIN[19][7]
SINGLE_E[10]SINGLE_N[14]MAIN[18][7]
SINGLE_E[11]SINGLE_S[9]MAIN[25][7]
SINGLE_E[11]SINGLE_N[11]MAIN[24][7]
SINGLE_E[12]SINGLE_S[18]MAIN[15][7]
SINGLE_E[12]SINGLE_N[16]MAIN[14][7]
SINGLE_E[13]SINGLE_S[15]MAIN[21][7]
SINGLE_E[13]SINGLE_N[13]MAIN[20][7]
SINGLE_E[14]SINGLE_S[16]MAIN[11][7]
SINGLE_E[14]SINGLE_N[18]MAIN[10][7]
SINGLE_E[15]SINGLE_S[13]MAIN[17][7]
SINGLE_E[15]SINGLE_N[15]MAIN[16][7]
SINGLE_E[16]SINGLE_S[22]MAIN[7][7]
SINGLE_E[16]SINGLE_N[20]MAIN[6][7]
SINGLE_E[17]SINGLE_S[19]MAIN[13][7]
SINGLE_E[17]SINGLE_N[17]MAIN[12][7]
SINGLE_E[18]SINGLE_S[20]MAIN[3][7]
SINGLE_E[18]SINGLE_N[22]MAIN[2][7]
SINGLE_E[19]SINGLE_S[17]MAIN[9][7]
SINGLE_E[19]SINGLE_N[19]MAIN[8][7]
SINGLE_E[20]SINGLE_S[2]MAIN[47][7]
SINGLE_E[20]SINGLE_N[0]MAIN[46][7]
SINGLE_E[21]SINGLE_S[23]MAIN[5][7]
SINGLE_E[21]SINGLE_N[21]MAIN[4][7]
SINGLE_E[22]SINGLE_S[0]MAIN[43][7]
SINGLE_E[22]SINGLE_N[2]MAIN[42][7]
SINGLE_E[23]SINGLE_S[21]MAIN[1][7]
SINGLE_E[23]SINGLE_N[23]MAIN[0][7]
SINGLE_S[0]SINGLE_N[0]MAIN[46][6]
SINGLE_S[1]SINGLE_N[1]MAIN[44][6]
SINGLE_S[2]SINGLE_N[2]MAIN[42][6]
SINGLE_S[3]SINGLE_N[3]MAIN[40][6]
SINGLE_S[4]SINGLE_N[4]MAIN[38][6]
SINGLE_S[5]SINGLE_N[5]MAIN[36][6]
SINGLE_S[6]SINGLE_N[6]MAIN[34][6]
SINGLE_S[7]SINGLE_N[7]MAIN[32][6]
SINGLE_S[8]SINGLE_N[8]MAIN[30][6]
SINGLE_S[9]SINGLE_N[9]MAIN[28][6]
SINGLE_S[10]SINGLE_N[10]MAIN[26][6]
SINGLE_S[11]SINGLE_N[11]MAIN[24][6]
SINGLE_S[12]SINGLE_N[12]MAIN[22][6]
SINGLE_S[13]SINGLE_N[13]MAIN[20][6]
SINGLE_S[14]SINGLE_N[14]MAIN[18][6]
SINGLE_S[15]SINGLE_N[15]MAIN[16][6]
SINGLE_S[16]SINGLE_N[16]MAIN[14][6]
SINGLE_S[17]SINGLE_N[17]MAIN[12][6]
SINGLE_S[18]SINGLE_N[18]MAIN[10][6]
SINGLE_S[19]SINGLE_N[19]MAIN[8][6]
SINGLE_S[20]SINGLE_N[20]MAIN[6][6]
SINGLE_S[21]SINGLE_N[21]MAIN[4][6]
SINGLE_S[22]SINGLE_N[22]MAIN[2][6]
SINGLE_S[23]SINGLE_N[23]MAIN[0][6]
virtex CLB switchbox INT muxes HEX_H0_MUX[0]
BitsDestination
MAIN[39][0]MAIN[41][0]MAIN[37][0]HEX_H0_MUX[0]
Source
000LH[0]
010HEX_V3[0]
011HEX_H6[0]
100HEX_V6[1]
101HEX_V0[0]
111OMUX[1]
virtex CLB switchbox INT muxes HEX_H0_MUX[1]
BitsDestination
MAIN[27][0]MAIN[29][0]MAIN[25][0]HEX_H0_MUX[1]
Source
000HEX_V3[1]
010LH[0]
011HEX_H6[1]
100HEX_V6[2]
101HEX_V0[1]
111OMUX[3]
virtex CLB switchbox INT muxes HEX_H0_MUX[2]
BitsDestination
MAIN[15][0]MAIN[17][0]MAIN[13][0]HEX_H0_MUX[2]
Source
000LH[6]
010HEX_V3[2]
011HEX_H6[2]
100HEX_V6[3]
101HEX_V0[2]
111OMUX[5]
virtex CLB switchbox INT muxes HEX_H0_MUX[3]
BitsDestination
MAIN[3][0]MAIN[5][0]MAIN[1][0]HEX_H0_MUX[3]
Source
000HEX_V3[3]
010LH[6]
011HEX_H6[3]
100HEX_V6[0]
101HEX_V0[3]
111OMUX[7]
virtex CLB switchbox INT muxes HEX_H6_MUX[0]
BitsDestination
MAIN[38][0]MAIN[36][0]MAIN[40][0]HEX_H6_MUX[0]
Source
000HEX_V3[0]
010LH[0]
011HEX_H0[0]
100HEX_V0[0]
101HEX_V6[1]
111OMUX[1]
virtex CLB switchbox INT muxes HEX_H6_MUX[1]
BitsDestination
MAIN[26][0]MAIN[28][0]MAIN[24][0]HEX_H6_MUX[1]
Source
000LH[0]
001HEX_V3[1]
011HEX_H0[1]
100HEX_V0[1]
110HEX_V6[2]
111OMUX[3]
virtex CLB switchbox INT muxes HEX_H6_MUX[2]
BitsDestination
MAIN[14][0]MAIN[12][0]MAIN[16][0]HEX_H6_MUX[2]
Source
000HEX_V3[2]
010LH[6]
011HEX_H0[2]
100HEX_V0[2]
101HEX_V6[3]
111OMUX[5]
virtex CLB switchbox INT muxes HEX_H6_MUX[3]
BitsDestination
MAIN[2][0]MAIN[4][0]MAIN[0][0]HEX_H6_MUX[3]
Source
000LH[6]
001HEX_V3[3]
011HEX_H0[3]
100HEX_V0[3]
110HEX_V6[0]
111OMUX[7]
virtex CLB switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[44][1]MAIN[46][1]MAIN[42][1]HEX_W0[0]
Source
000HEX_S3[0]
001HEX_N3[0]
011HEX_W6[0]
100HEX_S6[3]
110HEX_N6[0]
111OMUX[0]
virtex CLB switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[20][1]MAIN[22][1]MAIN[18][1]HEX_W0[1]
Source
000HEX_S3[1]
001HEX_N3[1]
011HEX_W6[1]
100HEX_S6[2]
110HEX_N6[1]
111OMUX[4]
virtex CLB switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[32][1]MAIN[34][1]MAIN[30][1]HEX_W0[2]
Source
000HEX_S3[2]
001HEX_N3[2]
011HEX_W6[2]
100HEX_S6[0]
110HEX_N6[2]
111OMUX[2]
virtex CLB switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[8][1]MAIN[10][1]MAIN[6][1]HEX_W0[3]
Source
000HEX_S3[3]
001HEX_N3[3]
011HEX_W6[3]
100HEX_S6[1]
110HEX_N6[3]
111OMUX[6]
virtex CLB switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[45][1]MAIN[43][1]MAIN[47][1]HEX_E0[0]
Source
000HEX_N3[0]
001HEX_S3[0]
011HEX_E6[0]
100HEX_N6[0]
110HEX_S6[3]
111OMUX[0]
virtex CLB switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[21][1]MAIN[19][1]MAIN[23][1]HEX_E0[1]
Source
000HEX_N3[1]
001HEX_S3[1]
011HEX_E6[1]
100HEX_N6[1]
110HEX_S6[2]
111OMUX[4]
virtex CLB switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[33][1]MAIN[31][1]MAIN[35][1]HEX_E0[2]
Source
000HEX_N3[2]
001HEX_S3[2]
011HEX_E6[2]
100HEX_N6[2]
110HEX_S6[0]
111OMUX[2]
virtex CLB switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[9][1]MAIN[7][1]MAIN[11][1]HEX_E0[3]
Source
000HEX_N3[3]
001HEX_S3[3]
011HEX_E6[3]
100HEX_N6[3]
110HEX_S6[1]
111OMUX[6]
virtex CLB switchbox INT muxes HEX_V0_MUX[0]
BitsDestination
MAIN[47][0]MAIN[43][0]MAIN[45][0]HEX_V0_MUX[0]
Source
000HEX_H3[0]
001HEX_H6[0]
011HEX_H0[3]
100LV[0]
110HEX_V6[0]
111OMUX[0]
virtex CLB switchbox INT muxes HEX_V0_MUX[1]
BitsDestination
MAIN[35][0]MAIN[31][0]MAIN[33][0]HEX_V0_MUX[1]
Source
000LV[0]
001HEX_H6[1]
011HEX_H0[0]
100HEX_H3[1]
110HEX_V6[1]
111OMUX[2]
virtex CLB switchbox INT muxes HEX_V0_MUX[2]
BitsDestination
MAIN[23][0]MAIN[19][0]MAIN[21][0]HEX_V0_MUX[2]
Source
000HEX_H3[2]
001HEX_H6[2]
011HEX_H0[1]
100LV[6]
110HEX_V6[2]
111OMUX[4]
virtex CLB switchbox INT muxes HEX_V0_MUX[3]
BitsDestination
MAIN[11][0]MAIN[7][0]MAIN[9][0]HEX_V0_MUX[3]
Source
000LV[6]
001HEX_H6[3]
011HEX_H0[2]
100HEX_H3[3]
110HEX_V6[3]
111OMUX[6]
virtex CLB switchbox INT muxes HEX_V6_MUX[0]
BitsDestination
MAIN[46][0]MAIN[42][0]MAIN[44][0]HEX_V6_MUX[0]
Source
000LV[0]
001HEX_H0[3]
010HEX_H3[0]
101HEX_H6[0]
110HEX_V0[0]
111OMUX[0]
virtex CLB switchbox INT muxes HEX_V6_MUX[1]
BitsDestination
MAIN[30][0]MAIN[34][0]MAIN[32][0]HEX_V6_MUX[1]
Source
000HEX_H3[1]
001HEX_H0[0]
011HEX_H6[1]
100LV[0]
110HEX_V0[1]
111OMUX[2]
virtex CLB switchbox INT muxes HEX_V6_MUX[2]
BitsDestination
MAIN[22][0]MAIN[18][0]MAIN[20][0]HEX_V6_MUX[2]
Source
000LV[6]
001HEX_H0[1]
010HEX_H3[2]
101HEX_H6[2]
110HEX_V0[2]
111OMUX[4]
virtex CLB switchbox INT muxes HEX_V6_MUX[3]
BitsDestination
MAIN[6][0]MAIN[10][0]MAIN[8][0]HEX_V6_MUX[3]
Source
000HEX_H3[3]
001HEX_H0[2]
011HEX_H6[3]
100LV[6]
110HEX_V0[3]
111OMUX[6]
virtex CLB switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[40][1]MAIN[36][1]MAIN[38][1]HEX_S0[0]
Source
000HEX_W3[0]
001HEX_W6[0]
010HEX_E3[0]
101HEX_E6[2]
110HEX_S6[0]
111OMUX[1]
virtex CLB switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[16][1]MAIN[12][1]MAIN[14][1]HEX_S0[1]
Source
000HEX_W3[1]
001HEX_W6[1]
010HEX_E3[1]
101HEX_E6[3]
110HEX_S6[1]
111OMUX[5]
virtex CLB switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[28][1]MAIN[24][1]MAIN[26][1]HEX_S0[2]
Source
000HEX_W3[2]
001HEX_W6[2]
010HEX_E3[2]
101HEX_E6[1]
110HEX_S6[2]
111OMUX[3]
virtex CLB switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[4][1]MAIN[0][1]MAIN[2][1]HEX_S0[3]
Source
000HEX_W3[3]
001HEX_W6[3]
010HEX_E3[3]
101HEX_E6[0]
110HEX_S6[3]
111OMUX[7]
virtex CLB switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[37][1]MAIN[39][1]MAIN[41][1]HEX_N0[0]
Source
000HEX_E3[0]
001HEX_W3[0]
010HEX_E6[2]
101HEX_N6[0]
110HEX_W6[0]
111OMUX[1]
virtex CLB switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[13][1]MAIN[15][1]MAIN[17][1]HEX_N0[1]
Source
000HEX_E3[1]
001HEX_W3[1]
010HEX_E6[3]
101HEX_N6[1]
110HEX_W6[1]
111OMUX[5]
virtex CLB switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[25][1]MAIN[27][1]MAIN[29][1]HEX_N0[2]
Source
000HEX_E3[2]
001HEX_W3[2]
010HEX_E6[1]
101HEX_N6[2]
110HEX_W6[2]
111OMUX[3]
virtex CLB switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[1][1]MAIN[3][1]MAIN[5][1]HEX_N0[3]
Source
000HEX_E3[3]
001HEX_W3[3]
010HEX_E6[0]
101HEX_N6[3]
110HEX_W6[3]
111OMUX[7]
virtex CLB switchbox INT muxes LH_MUX[0]
BitsDestination
MAIN[33][13]LH_MUX[0]
Source
0OMUX[2]
1OMUX[3]
virtex CLB switchbox INT muxes LH_MUX[6]
BitsDestination
MAIN[12][13]LH_MUX[6]
Source
0OMUX[5]
1OMUX[4]
virtex CLB switchbox INT muxes LV_MUX[0]
BitsDestination
MAIN[37][10]MAIN[38][10]MAIN[36][11]LV_MUX[0]
Source
000SINGLE_W_BUF[11]
001OMUX[1]
010SINGLE_N_BUF[4]
011SINGLE_E_BUF[5]
100SINGLE_S_BUF[2]
101SINGLE_E_BUF[22]
110OMUX[2]
111SINGLE_W_BUF[6]
virtex CLB switchbox INT muxes LV_MUX[6]
BitsDestination
MAIN[11][11]MAIN[10][10]MAIN[9][10]LV_MUX[6]
Source
000SINGLE_E_BUF[18]
001SINGLE_N_BUF[14]
010OMUX[5]
011SINGLE_W_BUF[10]
100SINGLE_S_BUF[13]
101SINGLE_W_BUF[17]
110OMUX[6]
111SINGLE_E_BUF[23]
virtex CLB switchbox INT muxes IMUX_CLB_CLK[0]
BitsDestination
MAIN[23][11]MAIN[22][12]MAIN[21][12]MAIN[21][10]MAIN[23][9]MAIN[22][10]IMUX_CLB_CLK[0]
Source
000000PULLUP
000001SINGLE_S_BUF[10]
000010HEX_V4[2]
000100HEX_V5[2]
001000GCLK_LEAF[3]
010001GCLK_LEAF[0]
010010SINGLE_E_BUF[15]
010100SINGLE_N_BUF[18]
011000SINGLE_W_BUF[16]
100001HEX_V3[2]
100010GCLK_LEAF[1]
100100HEX_V2[2]
101000HEX_V1[2]
110001HEX_V0[2]
110010SINGLE_N_BUF[13]
110100GCLK_LEAF[2]
111000SINGLE_S_BUF[15]
virtex CLB switchbox INT muxes IMUX_CLB_CLK[1]
BitsDestination
MAIN[22][11]MAIN[21][11]MAIN[23][12]MAIN[22][9]MAIN[21][9]MAIN[23][10]IMUX_CLB_CLK[1]
Source
000000PULLUP
000001SINGLE_S_BUF[10]
000010HEX_V4[2]
000100HEX_V5[2]
001000GCLK_LEAF[3]
010001GCLK_LEAF[0]
010010SINGLE_E_BUF[15]
010100SINGLE_N_BUF[18]
011000SINGLE_W_BUF[16]
100001HEX_V0[2]
100010SINGLE_N_BUF[13]
100100GCLK_LEAF[2]
101000SINGLE_S_BUF[15]
110001HEX_V3[2]
110010GCLK_LEAF[1]
110100HEX_V2[2]
111000HEX_V1[2]
virtex CLB switchbox INT muxes IMUX_CLB_SR[0]
BitsDestination
MAIN[25][11]MAIN[26][11]MAIN[24][12]MAIN[26][9]MAIN[25][9]MAIN[24][10]IMUX_CLB_SR[0]
Source
000000PULLUP
000001HEX_V4[1]
000010HEX_V5[1]
000100SINGLE_S_BUF[7]
001000SINGLE_N_BUF[12]
010001SINGLE_W_BUF[15]
010010HEX_V0[1]
010100SINGLE_N_BUF[8]
011000SINGLE_E_BUF[21]
100001SINGLE_S_BUF[22]
100010SINGLE_W_BUF[23]
100100SINGLE_E_BUF[10]
101000SINGLE_S_BUF[1]
110001HEX_V1[1]
110010HEX_V3[1]
110100HEX_V2[1]
111000SINGLE_N_BUF[17]
virtex CLB switchbox INT muxes IMUX_CLB_SR[1]
BitsDestination
MAIN[24][11]MAIN[25][12]MAIN[26][12]MAIN[24][9]MAIN[26][10]MAIN[25][10]IMUX_CLB_SR[1]
Source
000000PULLUP
000001HEX_V4[1]
000010HEX_V5[1]
000100SINGLE_S_BUF[7]
001000SINGLE_N_BUF[12]
010001SINGLE_W_BUF[15]
010010HEX_V0[1]
010100SINGLE_N_BUF[8]
011000SINGLE_E_BUF[21]
100001HEX_V1[1]
100010HEX_V3[1]
100100HEX_V2[1]
101000SINGLE_N_BUF[17]
110001SINGLE_S_BUF[22]
110010SINGLE_W_BUF[23]
110100SINGLE_E_BUF[10]
111000SINGLE_S_BUF[1]
virtex CLB switchbox INT muxes IMUX_CLB_CE[0]
BitsDestination
MAIN[2][11]MAIN[1][11]MAIN[0][12]MAIN[0][10]MAIN[2][9]MAIN[1][9]IMUX_CLB_CE[0]
Source
000000PULLUP
000001HEX_V2[3]
000010HEX_V1[3]
000100SINGLE_S_BUF[6]
001000HEX_V0[3]
010001SINGLE_W_BUF[7]
010010SINGLE_E_BUF[2]
010100SINGLE_E_BUF[12]
011000SINGLE_S_BUF[21]
100001SINGLE_W_BUF[22]
100010SINGLE_S_BUF[5]
100100SINGLE_N_BUF[22]
101000SINGLE_N_BUF[19]
110001HEX_V3[3]
110010HEX_V5[3]
110100SINGLE_N_BUF[23]
111000HEX_V4[3]
virtex CLB switchbox INT muxes IMUX_CLB_CE[1]
BitsDestination
MAIN[0][11]MAIN[1][12]MAIN[2][12]MAIN[1][10]MAIN[0][9]MAIN[2][10]IMUX_CLB_CE[1]
Source
000000PULLUP
000001HEX_V2[3]
000010HEX_V1[3]
000100SINGLE_S_BUF[6]
001000HEX_V0[3]
010001SINGLE_W_BUF[22]
010010SINGLE_S_BUF[5]
010100SINGLE_N_BUF[22]
011000SINGLE_N_BUF[19]
100001HEX_V3[3]
100010HEX_V5[3]
100100SINGLE_N_BUF[23]
101000HEX_V4[3]
110001SINGLE_W_BUF[7]
110010SINGLE_E_BUF[2]
110100SINGLE_E_BUF[12]
111000SINGLE_S_BUF[21]
virtex CLB switchbox INT muxes IMUX_CLB_BX[0]
BitsDestination
MAIN[35][11]MAIN[35][12]MAIN[36][12]MAIN[34][9]MAIN[34][10]MAIN[35][9]IMUX_CLB_BX[0]
Source
000000PULLUP
000001SINGLE_E_BUF[3]
000010SINGLE_W_BUF[14]
000100SINGLE_N_BUF[11]
001000SINGLE_S_BUF[9]
010001SINGLE_W_BUF[0]
010010SINGLE_E_BUF[7]
010100SINGLE_S_BUF[8]
011000SINGLE_N_BUF[2]
100001SINGLE_S_BUF[0]
100010SINGLE_E_BUF[19]
100100SINGLE_E_BUF[1]
101000SINGLE_S_BUF[14]
110001SINGLE_N_BUF[6]
110010SINGLE_W_BUF[4]
110100SINGLE_W_BUF[8]
111000SINGLE_N_BUF[5]
virtex CLB switchbox INT muxes IMUX_CLB_BX[1]
BitsDestination
MAIN[12][12]MAIN[12][11]MAIN[13][10]MAIN[11][12]MAIN[13][9]MAIN[12][9]IMUX_CLB_BX[1]
Source
000000PULLUP
000001SINGLE_W_BUF[19]
000010SINGLE_S_BUF[17]
000100SINGLE_W_BUF[18]
001000SINGLE_E_BUF[20]
010001SINGLE_W_BUF[2]
010010SINGLE_N_BUF[9]
010100SINGLE_E_BUF[13]
011000SINGLE_N_BUF[20]
100001SINGLE_N_BUF[15]
100010SINGLE_W_BUF[12]
100100SINGLE_N_BUF[21]
101000SINGLE_S_BUF[19]
110001SINGLE_W_BUF[21]
110010SINGLE_E_BUF[6]
110100SINGLE_S_BUF[23]
111000SINGLE_S_BUF[12]
virtex CLB switchbox INT muxes IMUX_CLB_BY[0]
BitsDestination
MAIN[34][11]MAIN[33][11]MAIN[34][12]MAIN[36][9]MAIN[33][10]MAIN[35][10]IMUX_CLB_BY[0]
Source
000000PULLUP
000001SINGLE_E_BUF[3]
000010SINGLE_W_BUF[14]
000100SINGLE_N_BUF[11]
001000SINGLE_S_BUF[9]
010001SINGLE_W_BUF[0]
010010SINGLE_E_BUF[7]
010100SINGLE_S_BUF[8]
011000SINGLE_N_BUF[2]
100001SINGLE_S_BUF[0]
100010SINGLE_E_BUF[19]
100100SINGLE_E_BUF[1]
101000SINGLE_S_BUF[14]
110001SINGLE_N_BUF[6]
110010SINGLE_W_BUF[4]
110100SINGLE_W_BUF[8]
111000SINGLE_N_BUF[5]
virtex CLB switchbox INT muxes IMUX_CLB_BY[1]
BitsDestination
MAIN[14][11]MAIN[13][11]MAIN[14][10]MAIN[13][12]MAIN[11][9]MAIN[12][10]IMUX_CLB_BY[1]
Source
000000PULLUP
000001SINGLE_W_BUF[19]
000010SINGLE_S_BUF[17]
000100SINGLE_W_BUF[18]
001000SINGLE_E_BUF[20]
010001SINGLE_W_BUF[2]
010010SINGLE_N_BUF[9]
010100SINGLE_E_BUF[13]
011000SINGLE_N_BUF[20]
100001SINGLE_N_BUF[15]
100010SINGLE_W_BUF[12]
100100SINGLE_N_BUF[21]
101000SINGLE_S_BUF[19]
110001SINGLE_W_BUF[21]
110010SINGLE_E_BUF[6]
110100SINGLE_S_BUF[23]
111000SINGLE_S_BUF[12]
virtex CLB switchbox INT muxes IMUX_CLB_F1[0]
BitsDestination
MAIN[7][12]MAIN[8][12]MAIN[9][12]MAIN[5][9]MAIN[6][11]MAIN[6][9]MAIN[8][9]MAIN[8][11]MAIN[7][10]IMUX_CLB_F1[0]
Source
000000000off
000000001SINGLE_W_BUF[21]
000000010SINGLE_N_BUF[9]
000000100SINGLE_W_BUF[13]
000001000SINGLE_N_BUF[14]
000010000SINGLE_S_BUF[17]
000100000SINGLE_S_BUF[5]
001000000OMUX_E1
010000001SINGLE_W_BUF[5]
010000010SINGLE_S_BUF[6]
010000100SINGLE_E_BUF[2]
010001000SINGLE_W_BUF[22]
010010000SINGLE_E_BUF[12]
010100000SINGLE_S_BUF[12]
100000001SINGLE_E_BUF[14]
100000010SINGLE_W_BUF[7]
100000100SINGLE_W_BUF[17]
100001000SINGLE_W_BUF[18]
100010000SINGLE_E_BUF[20]
100100000SINGLE_N_BUF[20]
101000000OUT_CLB_X[1]
110000001SINGLE_N_BUF[22]
110000010SINGLE_S_BUF[13]
110000100SINGLE_S_BUF[21]
110001000SINGLE_N_BUF[23]
110010000SINGLE_N_BUF[15]
110100000SINGLE_N_BUF[19]
virtex CLB switchbox INT muxes IMUX_CLB_F1[1]
BitsDestination
MAIN[39][12]MAIN[40][12]MAIN[38][12]MAIN[42][9]MAIN[39][11]MAIN[41][9]MAIN[41][11]MAIN[39][9]MAIN[40][10]IMUX_CLB_F1[1]
Source
000000000off
000000001SINGLE_S_BUF[16]
000000010SINGLE_E_BUF[16]
000000100SINGLE_S_BUF[9]
000001000SINGLE_E_BUF[8]
000010000SINGLE_S_BUF[11]
000100000SINGLE_S_BUF[18]
001000000OMUX_W6
010000001SINGLE_W_BUF[1]
010000010SINGLE_E_BUF[19]
010000100SINGLE_W_BUF[11]
010001000SINGLE_N_BUF[5]
010010000SINGLE_E_BUF[17]
010100000SINGLE_S_BUF[2]
011000000OUT_CLB_X[0]
100000001SINGLE_W_BUF[14]
100000010SINGLE_E_BUF[4]
100000100SINGLE_N_BUF[3]
100001000SINGLE_N_BUF[1]
100010000SINGLE_E_BUF[22]
100100000SINGLE_N_BUF[7]
110000001SINGLE_N_BUF[0]
110000010SINGLE_W_BUF[3]
110000100SINGLE_W_BUF[9]
110001000SINGLE_E_BUF[0]
110010000SINGLE_S_BUF[8]
110100000SINGLE_N_BUF[10]
virtex CLB switchbox INT muxes IMUX_CLB_F2[0]
BitsDestination
MAIN[19][12]MAIN[17][12]MAIN[21][13]MAIN[19][11]MAIN[20][12]MAIN[21][15]MAIN[22][15]MAIN[20][9]MAIN[19][9]IMUX_CLB_F2[0]
Source
000000000off
000000001SINGLE_E_BUF[23]
000000010SINGLE_N_BUF[18]
000000100SINGLE_N_BUF[17]
000001000SINGLE_E_BUF[18]
000010000SINGLE_S_BUF[1]
000100000SINGLE_N_BUF[16]
001000000OMUX_E0
010000001SINGLE_W_BUF[2]
010000010SINGLE_W_BUF[10]
010000100SINGLE_W_BUF[12]
010001000SINGLE_S_BUF[4]
010010000SINGLE_S_BUF[23]
010100000SINGLE_E_BUF[13]
100000001SINGLE_S_BUF[3]
100000010SINGLE_E_BUF[15]
100000100SINGLE_W_BUF[16]
100001000SINGLE_S_BUF[10]
100010000SINGLE_E_BUF[11]
100100000SINGLE_S_BUF[7]
101000000OUT_CLB_Y[1]
110000001SINGLE_W_BUF[20]
110000010SINGLE_S_BUF[19]
110000100SINGLE_E_BUF[6]
110001000SINGLE_W_BUF[19]
110010000SINGLE_N_BUF[21]
110100000SINGLE_N_BUF[12]
virtex CLB switchbox INT muxes IMUX_CLB_F2[1]
BitsDestination
MAIN[30][12]MAIN[28][12]MAIN[26][13]MAIN[27][12]MAIN[28][11]MAIN[23][15]MAIN[25][15]MAIN[27][9]MAIN[28][9]IMUX_CLB_F2[1]
Source
000000000off
000000001SINGLE_W_BUF[6]
000000010SINGLE_E_BUF[5]
000000100SINGLE_E_BUF[21]
000001000SINGLE_S_BUF[15]
000010000SINGLE_N_BUF[11]
000100000SINGLE_N_BUF[13]
001000000OMUX_W7
010000001SINGLE_S_BUF[22]
010000010SINGLE_W_BUF[4]
010000100SINGLE_E_BUF[1]
010001000SINGLE_S_BUF[14]
010010000SINGLE_W_BUF[23]
010100000SINGLE_E_BUF[10]
011000000OUT_CLB_Y[0]
100000001SINGLE_S_BUF[20]
100000010SINGLE_S_BUF[0]
100000100SINGLE_W_BUF[8]
100001000SINGLE_W_BUF[15]
100010000SINGLE_N_BUF[6]
100100000SINGLE_N_BUF[2]
110000001SINGLE_W_BUF[0]
110000010SINGLE_N_BUF[4]
110000100SINGLE_N_BUF[8]
110001000SINGLE_E_BUF[3]
110010000SINGLE_E_BUF[9]
110100000SINGLE_E_BUF[7]
virtex CLB switchbox INT muxes IMUX_CLB_F3[0]
BitsDestination
MAIN[31][12]MAIN[32][12]MAIN[30][13]MAIN[32][11]MAIN[30][9]MAIN[30][11]MAIN[29][9]MAIN[32][9]MAIN[31][10]IMUX_CLB_F3[0]
Source
000000000off
000000001SINGLE_S_BUF[20]
000000010SINGLE_E_BUF[1]
000000100SINGLE_W_BUF[15]
000001000SINGLE_W_BUF[23]
000010000SINGLE_N_BUF[4]
000100000SINGLE_N_BUF[11]
001000000OMUX_W7
010000001SINGLE_W_BUF[0]
010000010SINGLE_W_BUF[8]
010000100SINGLE_N_BUF[13]
010001000SINGLE_N_BUF[6]
010010000SINGLE_E_BUF[5]
010100000SINGLE_S_BUF[14]
100000001SINGLE_W_BUF[6]
100000010SINGLE_W_BUF[4]
100000100SINGLE_N_BUF[8]
100001000SINGLE_E_BUF[3]
100010000SINGLE_E_BUF[7]
100100000SINGLE_E_BUF[10]
101000000OUT_CLB_Y[0]
110000001SINGLE_S_BUF[22]
110000010SINGLE_E_BUF[21]
110000100SINGLE_N_BUF[2]
110001000SINGLE_S_BUF[15]
110010000SINGLE_S_BUF[0]
110100000SINGLE_E_BUF[9]
virtex CLB switchbox INT muxes IMUX_CLB_F3[1]
BitsDestination
MAIN[16][12]MAIN[15][12]MAIN[17][13]MAIN[15][11]MAIN[18][9]MAIN[17][11]MAIN[15][9]MAIN[17][9]MAIN[16][10]IMUX_CLB_F3[1]
Source
000000000off
000000001SINGLE_W_BUF[2]
000000010SINGLE_S_BUF[19]
000000100SINGLE_W_BUF[16]
000001000SINGLE_S_BUF[7]
000010000SINGLE_S_BUF[4]
000100000SINGLE_N_BUF[16]
001000000OMUX_E0
010000001SINGLE_W_BUF[20]
010000010SINGLE_N_BUF[18]
010000100SINGLE_W_BUF[12]
010001000SINGLE_E_BUF[13]
010010000SINGLE_S_BUF[1]
010100000SINGLE_S_BUF[10]
100000001SINGLE_E_BUF[23]
100000010SINGLE_N_BUF[21]
100000100SINGLE_E_BUF[15]
100001000SINGLE_W_BUF[19]
100010000SINGLE_E_BUF[6]
100100000SINGLE_E_BUF[11]
101000000OUT_CLB_Y[1]
110000001SINGLE_S_BUF[3]
110000010SINGLE_W_BUF[10]
110000100SINGLE_N_BUF[17]
110001000SINGLE_E_BUF[18]
110010000SINGLE_S_BUF[23]
110100000SINGLE_N_BUF[12]
virtex CLB switchbox INT muxes IMUX_CLB_F4[0]
BitsDestination
MAIN[43][12]MAIN[41][12]MAIN[45][13]MAIN[43][11]MAIN[44][12]MAIN[44][9]MAIN[27][15]MAIN[37][12]MAIN[43][9]IMUX_CLB_F4[0]
Source
000000000off
000000001SINGLE_W_BUF[1]
000000010SINGLE_W_BUF[3]
000000100SINGLE_W_BUF[9]
000001000SINGLE_N_BUF[1]
000010000SINGLE_N_BUF[7]
000100000SINGLE_S_BUF[11]
001000000OMUX_W6
010000001SINGLE_S_BUF[16]
010000010SINGLE_E_BUF[4]
010000100SINGLE_S_BUF[18]
010001000SINGLE_E_BUF[0]
010010000SINGLE_N_BUF[10]
010100000SINGLE_N_BUF[3]
100000001SINGLE_N_BUF[0]
100000010SINGLE_E_BUF[16]
100000100SINGLE_E_BUF[22]
100001000SINGLE_E_BUF[19]
100010000SINGLE_E_BUF[17]
100100000SINGLE_S_BUF[9]
110000001SINGLE_W_BUF[14]
110000010SINGLE_S_BUF[2]
110000100SINGLE_W_BUF[11]
110001000SINGLE_E_BUF[8]
110010000SINGLE_N_BUF[5]
110100000SINGLE_S_BUF[8]
virtex CLB switchbox INT muxes IMUX_CLB_F4[1]
BitsDestination
MAIN[6][12]MAIN[4][12]MAIN[2][13]MAIN[20][15]MAIN[4][11]MAIN[3][9]MAIN[10][12]MAIN[3][12]MAIN[4][9]IMUX_CLB_F4[1]
Source
000000000off
000000001SINGLE_E_BUF[14]
000000010SINGLE_S_BUF[12]
000000100SINGLE_S_BUF[21]
000001000SINGLE_W_BUF[22]
000010000SINGLE_N_BUF[9]
000100000SINGLE_N_BUF[15]
001000000OMUX_E1
010000001SINGLE_N_BUF[22]
010000010SINGLE_W_BUF[7]
010000100SINGLE_W_BUF[13]
010001000SINGLE_W_BUF[17]
010010000SINGLE_S_BUF[17]
010100000SINGLE_S_BUF[6]
100000001SINGLE_W_BUF[21]
100000010SINGLE_N_BUF[19]
100000100SINGLE_E_BUF[2]
100001000SINGLE_N_BUF[23]
100010000SINGLE_E_BUF[12]
100100000SINGLE_S_BUF[5]
110000001SINGLE_W_BUF[5]
110000010SINGLE_W_BUF[18]
110000100SINGLE_N_BUF[20]
110001000SINGLE_N_BUF[14]
110010000SINGLE_S_BUF[13]
110100000SINGLE_E_BUF[20]
virtex CLB switchbox INT muxes IMUX_CLB_G1[0]
BitsDestination
MAIN[7][13]MAIN[8][13]MAIN[6][13]MAIN[9][9]MAIN[10][9]MAIN[8][10]MAIN[6][10]MAIN[7][11]MAIN[7][9]IMUX_CLB_G1[0]
Source
000000000off
000000001SINGLE_W_BUF[21]
000000010SINGLE_N_BUF[9]
000000100SINGLE_W_BUF[13]
000001000SINGLE_N_BUF[14]
000010000SINGLE_S_BUF[17]
000100000SINGLE_S_BUF[5]
001000000OMUX_E1
010000001SINGLE_W_BUF[5]
010000010SINGLE_S_BUF[6]
010000100SINGLE_E_BUF[2]
010001000SINGLE_W_BUF[22]
010010000SINGLE_E_BUF[12]
010100000SINGLE_S_BUF[12]
100000001SINGLE_E_BUF[14]
100000010SINGLE_W_BUF[7]
100000100SINGLE_W_BUF[17]
100001000SINGLE_W_BUF[18]
100010000SINGLE_E_BUF[20]
100100000SINGLE_N_BUF[20]
101000000OUT_CLB_X[1]
110000001SINGLE_N_BUF[22]
110000010SINGLE_S_BUF[13]
110000100SINGLE_S_BUF[21]
110001000SINGLE_N_BUF[23]
110010000SINGLE_N_BUF[15]
110100000SINGLE_N_BUF[19]
virtex CLB switchbox INT muxes IMUX_CLB_G1[1]
BitsDestination
MAIN[39][13]MAIN[40][13]MAIN[41][13]MAIN[38][9]MAIN[40][11]MAIN[39][10]MAIN[37][9]MAIN[41][10]MAIN[40][9]IMUX_CLB_G1[1]
Source
000000000off
000000001SINGLE_S_BUF[16]
000000010SINGLE_E_BUF[16]
000000100SINGLE_S_BUF[9]
000001000SINGLE_E_BUF[8]
000010000SINGLE_S_BUF[11]
000100000SINGLE_S_BUF[18]
001000000OMUX_W6
010000001SINGLE_W_BUF[1]
010000010SINGLE_E_BUF[19]
010000100SINGLE_W_BUF[11]
010001000SINGLE_N_BUF[5]
010010000SINGLE_E_BUF[17]
010100000SINGLE_S_BUF[2]
011000000OUT_CLB_X[0]
100000001SINGLE_W_BUF[14]
100000010SINGLE_E_BUF[4]
100000100SINGLE_N_BUF[3]
100001000SINGLE_N_BUF[1]
100010000SINGLE_E_BUF[22]
100100000SINGLE_N_BUF[7]
110000001SINGLE_N_BUF[0]
110000010SINGLE_W_BUF[3]
110000100SINGLE_W_BUF[9]
110001000SINGLE_E_BUF[0]
110010000SINGLE_S_BUF[8]
110100000SINGLE_N_BUF[10]
virtex CLB switchbox INT muxes IMUX_CLB_G2[0]
BitsDestination
MAIN[19][13]MAIN[18][13]MAIN[20][13]MAIN[18][11]MAIN[20][11]MAIN[18][12]MAIN[20][10]MAIN[18][10]MAIN[19][10]IMUX_CLB_G2[0]
Source
000000000off
000000001SINGLE_E_BUF[23]
000000010SINGLE_N_BUF[18]
000000100SINGLE_N_BUF[17]
000001000SINGLE_E_BUF[18]
000010000SINGLE_S_BUF[1]
000100000SINGLE_N_BUF[16]
001000000OMUX_E0
010000001SINGLE_W_BUF[2]
010000010SINGLE_W_BUF[10]
010000100SINGLE_W_BUF[12]
010001000SINGLE_S_BUF[4]
010010000SINGLE_S_BUF[23]
010100000SINGLE_E_BUF[13]
100000001SINGLE_S_BUF[3]
100000010SINGLE_E_BUF[15]
100000100SINGLE_W_BUF[16]
100001000SINGLE_S_BUF[10]
100010000SINGLE_E_BUF[11]
100100000SINGLE_S_BUF[7]
101000000OUT_CLB_Y[1]
110000001SINGLE_W_BUF[20]
110000010SINGLE_S_BUF[19]
110000100SINGLE_E_BUF[6]
110001000SINGLE_W_BUF[19]
110010000SINGLE_N_BUF[21]
110100000SINGLE_N_BUF[12]
virtex CLB switchbox INT muxes IMUX_CLB_G2[1]
BitsDestination
MAIN[29][13]MAIN[28][13]MAIN[27][13]MAIN[27][11]MAIN[29][11]MAIN[29][12]MAIN[27][10]MAIN[29][10]MAIN[28][10]IMUX_CLB_G2[1]
Source
000000000off
000000001SINGLE_W_BUF[6]
000000010SINGLE_E_BUF[5]
000000100SINGLE_E_BUF[21]
000001000SINGLE_S_BUF[15]
000010000SINGLE_N_BUF[11]
000100000SINGLE_N_BUF[13]
001000000OMUX_W7
010000001SINGLE_S_BUF[22]
010000010SINGLE_W_BUF[4]
010000100SINGLE_E_BUF[1]
010001000SINGLE_S_BUF[14]
010010000SINGLE_W_BUF[23]
010100000SINGLE_E_BUF[10]
011000000OUT_CLB_Y[0]
100000001SINGLE_S_BUF[20]
100000010SINGLE_S_BUF[0]
100000100SINGLE_W_BUF[8]
100001000SINGLE_W_BUF[15]
100010000SINGLE_N_BUF[6]
100100000SINGLE_N_BUF[2]
110000001SINGLE_W_BUF[0]
110000010SINGLE_N_BUF[4]
110000100SINGLE_N_BUF[8]
110001000SINGLE_E_BUF[3]
110010000SINGLE_E_BUF[9]
110100000SINGLE_E_BUF[7]
virtex CLB switchbox INT muxes IMUX_CLB_G3[0]
BitsDestination
MAIN[31][13]MAIN[32][13]MAIN[26][15]MAIN[31][11]MAIN[32][10]MAIN[33][12]MAIN[33][9]MAIN[30][10]MAIN[31][9]IMUX_CLB_G3[0]
Source
000000000off
000000001SINGLE_S_BUF[20]
000000010SINGLE_E_BUF[1]
000000100SINGLE_W_BUF[15]
000001000SINGLE_W_BUF[23]
000010000SINGLE_N_BUF[4]
000100000SINGLE_N_BUF[11]
001000000OMUX_W7
010000001SINGLE_W_BUF[0]
010000010SINGLE_W_BUF[8]
010000100SINGLE_N_BUF[13]
010001000SINGLE_N_BUF[6]
010010000SINGLE_E_BUF[5]
010100000SINGLE_S_BUF[14]
100000001SINGLE_W_BUF[6]
100000010SINGLE_W_BUF[4]
100000100SINGLE_N_BUF[8]
100001000SINGLE_E_BUF[3]
100010000SINGLE_E_BUF[7]
100100000SINGLE_E_BUF[10]
110000001SINGLE_S_BUF[22]
110000010SINGLE_E_BUF[21]
110000100SINGLE_N_BUF[2]
110001000SINGLE_S_BUF[15]
110010000SINGLE_S_BUF[0]
110100000SINGLE_E_BUF[9]
virtex CLB switchbox INT muxes IMUX_CLB_G3[1]
BitsDestination
MAIN[16][13]MAIN[15][13]MAIN[24][15]MAIN[16][11]MAIN[14][9]MAIN[14][12]MAIN[17][10]MAIN[15][10]MAIN[16][9]IMUX_CLB_G3[1]
Source
000000000off
000000001SINGLE_W_BUF[2]
000000010SINGLE_S_BUF[19]
000000100SINGLE_W_BUF[16]
000001000SINGLE_S_BUF[7]
000010000SINGLE_S_BUF[4]
000100000SINGLE_N_BUF[16]
001000000OMUX_E0
010000001SINGLE_W_BUF[20]
010000010SINGLE_N_BUF[18]
010000100SINGLE_W_BUF[12]
010001000SINGLE_E_BUF[13]
010010000SINGLE_S_BUF[1]
010100000SINGLE_S_BUF[10]
100000001SINGLE_E_BUF[23]
100000010SINGLE_N_BUF[21]
100000100SINGLE_E_BUF[15]
100001000SINGLE_W_BUF[19]
100010000SINGLE_E_BUF[6]
100100000SINGLE_E_BUF[11]
110000001SINGLE_S_BUF[3]
110000010SINGLE_W_BUF[10]
110000100SINGLE_N_BUF[17]
110001000SINGLE_E_BUF[18]
110010000SINGLE_S_BUF[23]
110100000SINGLE_N_BUF[12]
virtex CLB switchbox INT muxes IMUX_CLB_G4[0]
BitsDestination
MAIN[43][13]MAIN[42][13]MAIN[44][13]MAIN[42][11]MAIN[44][11]MAIN[42][10]MAIN[42][12]MAIN[44][10]MAIN[43][10]IMUX_CLB_G4[0]
Source
000000000off
000000001SINGLE_W_BUF[1]
000000010SINGLE_W_BUF[3]
000000100SINGLE_W_BUF[9]
000001000SINGLE_N_BUF[1]
000010000SINGLE_N_BUF[7]
000100000SINGLE_S_BUF[11]
001000000OMUX_W6
010000001SINGLE_S_BUF[16]
010000010SINGLE_E_BUF[4]
010000100SINGLE_S_BUF[18]
010001000SINGLE_E_BUF[0]
010010000SINGLE_N_BUF[10]
010100000SINGLE_N_BUF[3]
100000001SINGLE_N_BUF[0]
100000010SINGLE_E_BUF[16]
100000100SINGLE_E_BUF[22]
100001000SINGLE_E_BUF[19]
100010000SINGLE_E_BUF[17]
100100000SINGLE_S_BUF[9]
101000000OUT_CLB_X[0]
110000001SINGLE_W_BUF[14]
110000010SINGLE_S_BUF[2]
110000100SINGLE_W_BUF[11]
110001000SINGLE_E_BUF[8]
110010000SINGLE_N_BUF[5]
110100000SINGLE_S_BUF[8]
virtex CLB switchbox INT muxes IMUX_CLB_G4[1]
BitsDestination
MAIN[5][13]MAIN[4][13]MAIN[3][13]MAIN[5][12]MAIN[5][11]MAIN[5][10]MAIN[3][10]MAIN[3][11]MAIN[4][10]IMUX_CLB_G4[1]
Source
000000000off
000000001SINGLE_E_BUF[14]
000000010SINGLE_S_BUF[12]
000000100SINGLE_S_BUF[21]
000001000SINGLE_W_BUF[22]
000010000SINGLE_N_BUF[9]
000100000SINGLE_N_BUF[15]
001000000OMUX_E1
010000001SINGLE_N_BUF[22]
010000010SINGLE_W_BUF[7]
010000100SINGLE_W_BUF[13]
010001000SINGLE_W_BUF[17]
010010000SINGLE_S_BUF[17]
010100000SINGLE_S_BUF[6]
011000000OUT_CLB_X[1]
100000001SINGLE_W_BUF[21]
100000010SINGLE_N_BUF[19]
100000100SINGLE_E_BUF[2]
100001000SINGLE_N_BUF[23]
100010000SINGLE_E_BUF[12]
100100000SINGLE_S_BUF[5]
110000001SINGLE_W_BUF[5]
110000010SINGLE_W_BUF[18]
110000100SINGLE_N_BUF[20]
110001000SINGLE_N_BUF[14]
110010000SINGLE_S_BUF[13]
110100000SINGLE_E_BUF[20]
virtex CLB switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[46][11]MAIN[45][11]MAIN[45][9]MAIN[46][9]MAIN[47][12]MAIN[47][10]IMUX_TBUF_T[0]
Source
000000PULLUP
000001SINGLE_S_BUF[16]
000010HEX_V4[0]
000100HEX_V5[0]
001000SINGLE_S_BUF[11]
010001SINGLE_W_BUF[1]
010010SINGLE_N_BUF[10]
010100SINGLE_S_BUF[18]
011000HEX_V0[0]
100001SINGLE_N_BUF[0]
100010SINGLE_W_BUF[3]
100100HEX_V1[0]
101000SINGLE_N_BUF[3]
110001SINGLE_E_BUF[0]
110010HEX_V2[0]
110100SINGLE_E_BUF[8]
111000HEX_V3[0]
virtex CLB switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[47][11]MAIN[46][12]MAIN[47][9]MAIN[45][10]MAIN[45][12]MAIN[46][10]IMUX_TBUF_T[1]
Source
000000PULLUP
000001SINGLE_S_BUF[16]
000010HEX_V4[0]
000100HEX_V5[0]
001000SINGLE_S_BUF[11]
010001SINGLE_W_BUF[1]
010010SINGLE_N_BUF[10]
010100SINGLE_S_BUF[18]
011000HEX_V0[0]
100001SINGLE_E_BUF[0]
100010HEX_V2[0]
100100SINGLE_E_BUF[8]
101000HEX_V3[0]
110001SINGLE_N_BUF[0]
110010SINGLE_W_BUF[3]
110100HEX_V1[0]
111000SINGLE_N_BUF[3]
virtex CLB switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[36][10]MAIN[38][11]MAIN[37][11]IMUX_TBUF_I[0]
Source
000SINGLE_N_BUF[4]
001SINGLE_W_BUF[11]
010OMUX[1]
011SINGLE_E_BUF[5]
100OMUX[2]
101SINGLE_S_BUF[2]
110SINGLE_E_BUF[22]
111SINGLE_W_BUF[6]
virtex CLB switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[9][11]MAIN[10][11]MAIN[11][10]IMUX_TBUF_I[1]
Source
000SINGLE_N_BUF[14]
001SINGLE_W_BUF[10]
010SINGLE_E_BUF[18]
011OMUX[5]
100SINGLE_S_BUF[13]
101OMUX[6]
110SINGLE_W_BUF[17]
111SINGLE_E_BUF[23]
virtex CLB switchbox INT muxes OMUX[0]
BitsDestination
MAIN[39][17]MAIN[45][17]MAIN[43][17]MAIN[40][17]MAIN[44][17]MAIN[41][17]MAIN[42][17]OMUX[0]
Source
0001111OUT_CLB_X[0]
0010111OUT_CLB_Y[0]
0011011OUT_CLB_XQ[0]
0011101OUT_CLB_XQ[1]
0011110OUT_CLB_YQ[1]
0011111off
0101111OUT_CLB_Y[1]
0110111OUT_CLB_X[1]
0111011OUT_CLB_YB[0]
0111101OUT_CLB_XB[0]
0111110OUT_CLB_YB[1]
1011111OUT_CLB_YQ[0]
1111111OUT_TBUF
virtex CLB switchbox INT muxes OMUX[1]
BitsDestination
MAIN[37][17]MAIN[38][17]MAIN[47][17]MAIN[36][17]MAIN[46][17]MAIN[38][16]MAIN[42][16]OMUX[1]
Source
0001111OUT_CLB_X[0]
0010111OUT_CLB_Y[0]
0011011OUT_CLB_XQ[0]
0011101OUT_CLB_XQ[1]
0011110OUT_CLB_YQ[1]
0011111off
0101111OUT_CLB_Y[1]
0110111OUT_CLB_X[1]
0111011OUT_CLB_YB[0]
0111101OUT_CLB_XB[0]
0111110OUT_CLB_YB[1]
1011111OUT_CLB_YQ[0]
1111111OUT_TBUF
virtex CLB switchbox INT muxes OMUX[2]
BitsDestination
MAIN[34][17]MAIN[33][17]MAIN[24][17]MAIN[35][17]MAIN[25][17]MAIN[34][16]MAIN[33][16]OMUX[2]
Source
0001111OUT_CLB_X[0]
0010111OUT_CLB_Y[0]
0011011OUT_CLB_XQ[0]
0011101OUT_CLB_XQ[1]
0011110OUT_CLB_YQ[1]
0011111off
0101111OUT_CLB_Y[1]
0110111OUT_CLB_X[1]
0111011OUT_CLB_YB[0]
0111101OUT_CLB_XB[0]
0111110OUT_CLB_XB[1]
1011111OUT_CLB_YQ[0]
1111111OUT_TBUF
virtex CLB switchbox INT muxes OMUX[3]
BitsDestination
MAIN[32][17]MAIN[26][17]MAIN[28][17]MAIN[31][17]MAIN[27][17]MAIN[30][17]MAIN[29][17]OMUX[3]
Source
0001111OUT_CLB_X[0]
0010111OUT_CLB_Y[0]
0011011OUT_CLB_XQ[0]
0011101OUT_CLB_XQ[1]
0011110OUT_CLB_YQ[1]
0011111off
0101111OUT_CLB_Y[1]
0110111OUT_CLB_X[1]
0111011OUT_CLB_YB[0]
0111101OUT_CLB_XB[0]
0111110OUT_CLB_XB[1]
1011111OUT_CLB_YQ[0]
1111111OUT_TBUF
virtex CLB switchbox INT muxes OMUX[4]
BitsDestination
MAIN[15][17]MAIN[21][17]MAIN[19][17]MAIN[16][17]MAIN[20][17]MAIN[17][17]MAIN[18][17]OMUX[4]
Source
0001111OUT_CLB_X[0]
0010111OUT_CLB_Y[0]
0011011OUT_CLB_XQ[0]
0011101OUT_CLB_XQ[1]
0011110OUT_CLB_YQ[1]
0011111off
0101111OUT_CLB_Y[1]
0110111OUT_CLB_X[1]
0111011OUT_CLB_XB[0]
0111101OUT_CLB_XB[1]
0111110OUT_CLB_YB[1]
1011111OUT_CLB_YQ[0]
1111111OUT_TBUF
virtex CLB switchbox INT muxes OMUX[5]
BitsDestination
MAIN[13][17]MAIN[14][17]MAIN[23][17]MAIN[12][17]MAIN[22][17]MAIN[13][16]MAIN[14][16]OMUX[5]
Source
0001111OUT_CLB_X[0]
0010111OUT_CLB_Y[0]
0011011OUT_CLB_XQ[0]
0011101OUT_CLB_XQ[1]
0011110OUT_CLB_YQ[1]
0011111off
0101111OUT_CLB_Y[1]
0110111OUT_CLB_X[1]
0111011OUT_CLB_XB[0]
0111101OUT_CLB_XB[1]
0111110OUT_CLB_YB[1]
1011111OUT_CLB_YQ[0]
1111111OUT_TBUF
virtex CLB switchbox INT muxes OMUX[6]
BitsDestination
MAIN[10][17]MAIN[9][17]MAIN[0][17]MAIN[11][17]MAIN[1][17]MAIN[9][16]MAIN[5][16]OMUX[6]
Source
0001111OUT_CLB_X[0]
0010111OUT_CLB_Y[0]
0011011OUT_CLB_XQ[0]
0011101OUT_CLB_XQ[1]
0011110OUT_CLB_YQ[1]
0011111off
0101111OUT_CLB_Y[1]
0110111OUT_CLB_X[1]
0111011OUT_CLB_YB[0]
0111101OUT_CLB_XB[1]
0111110OUT_CLB_YB[1]
1011111OUT_CLB_YQ[0]
1111111OUT_TBUF
virtex CLB switchbox INT muxes OMUX[7]
BitsDestination
MAIN[8][17]MAIN[2][17]MAIN[4][17]MAIN[7][17]MAIN[3][17]MAIN[6][17]MAIN[5][17]OMUX[7]
Source
0001111OUT_CLB_X[0]
0010111OUT_CLB_Y[0]
0011011OUT_CLB_XQ[0]
0011101OUT_CLB_XQ[1]
0011110OUT_CLB_YQ[1]
0011111off
0101111OUT_CLB_Y[1]
0110111OUT_CLB_X[1]
0111011OUT_CLB_YB[0]
0111101OUT_CLB_XB[1]
0111110OUT_CLB_YB[1]
1011111OUT_CLB_YQ[0]
1111111OUT_TBUF

Bels SLICE

virtex CLB bel SLICE pins
PinDirectionSLICE[0]SLICE[1]
F1inIMUX_CLB_F1[0]IMUX_CLB_F1[1]
F2inIMUX_CLB_F2[0]IMUX_CLB_F2[1]
F3inIMUX_CLB_F3[0]IMUX_CLB_F3[1]
F4inIMUX_CLB_F4[0]IMUX_CLB_F4[1]
G1inIMUX_CLB_G1[0]IMUX_CLB_G1[1]
G2inIMUX_CLB_G2[0]IMUX_CLB_G2[1]
G3inIMUX_CLB_G3[0]IMUX_CLB_G3[1]
G4inIMUX_CLB_G4[0]IMUX_CLB_G4[1]
BXinIMUX_CLB_BX[0] invert by MAIN[38][13]IMUX_CLB_BX[1] invert by MAIN[11][13]
BYinIMUX_CLB_BY[0] invert by MAIN[35][13]IMUX_CLB_BY[1] invert by MAIN[13][13]
CLKinIMUX_CLB_CLK[0] invert by MAIN[23][13]IMUX_CLB_CLK[1] invert by MAIN[22][13]
SRinIMUX_CLB_SR[0] invert by !MAIN[25][13]IMUX_CLB_SR[1] invert by !MAIN[24][13]
CEinIMUX_CLB_CE[0] invert by MAIN[1][13]IMUX_CLB_CE[1] invert by MAIN[0][13]
XoutOUT_CLB_X[0]OUT_CLB_X[1]
YoutOUT_CLB_Y[0]OUT_CLB_Y[1]
XQoutOUT_CLB_XQ[0]OUT_CLB_XQ[1]
YQoutOUT_CLB_YQ[0]OUT_CLB_YQ[1]
XBoutOUT_CLB_XB[0]OUT_CLB_XB[1]
YBoutOUT_CLB_YB[0]OUT_CLB_YB[1]
virtex CLB bel SLICE attribute bits
AttributeSLICE[0]SLICE[1]
F bit 0!MAIN[32][14]!MAIN[15][14]
F bit 1!MAIN[33][14]!MAIN[14][14]
F bit 2!MAIN[34][14]!MAIN[13][14]
F bit 3!MAIN[35][14]!MAIN[12][14]
F bit 4!MAIN[36][14]!MAIN[11][14]
F bit 5!MAIN[37][14]!MAIN[10][14]
F bit 6!MAIN[38][14]!MAIN[9][14]
F bit 7!MAIN[39][14]!MAIN[8][14]
F bit 8!MAIN[40][14]!MAIN[7][14]
F bit 9!MAIN[41][14]!MAIN[6][14]
F bit 10!MAIN[42][14]!MAIN[5][14]
F bit 11!MAIN[43][14]!MAIN[4][14]
F bit 12!MAIN[44][14]!MAIN[3][14]
F bit 13!MAIN[45][14]!MAIN[2][14]
F bit 14!MAIN[46][14]!MAIN[1][14]
F bit 15!MAIN[47][14]!MAIN[0][14]
G bit 0!MAIN[32][15]!MAIN[15][15]
G bit 1!MAIN[33][15]!MAIN[14][15]
G bit 2!MAIN[34][15]!MAIN[13][15]
G bit 3!MAIN[35][15]!MAIN[12][15]
G bit 4!MAIN[36][15]!MAIN[11][15]
G bit 5!MAIN[37][15]!MAIN[10][15]
G bit 6!MAIN[38][15]!MAIN[9][15]
G bit 7!MAIN[39][15]!MAIN[8][15]
G bit 8!MAIN[40][15]!MAIN[7][15]
G bit 9!MAIN[41][15]!MAIN[6][15]
G bit 10!MAIN[42][15]!MAIN[5][15]
G bit 11!MAIN[43][15]!MAIN[4][15]
G bit 12!MAIN[44][15]!MAIN[3][15]
G bit 13!MAIN[45][15]!MAIN[2][15]
G bit 14!MAIN[46][15]!MAIN[1][15]
G bit 15!MAIN[47][15]!MAIN[0][15]
DIF_MUX[enum: SLICE_DIF_MUX][enum: SLICE_DIF_MUX]
F_RAM_ENABLE!MAIN[27][14]!MAIN[20][14]
G_RAM_ENABLE!MAIN[28][14]!MAIN[19][14]
F_SHIFT_ENABLE!MAIN[26][14]!MAIN[21][14]
G_SHIFT_ENABLE!MAIN[24][14]!MAIN[23][14]
WA4_ENABLEMAIN[25][14]MAIN[22][14]
CYINIT[enum: SLICE_CYINIT][enum: SLICE_CYINIT]
CY0[enum: SLICE_CY0][enum: SLICE_CY0]
CYSELF[enum: SLICE_CYSELF][enum: SLICE_CYSELF]
CYSELG[enum: SLICE_CYSELG][enum: SLICE_CYSELG]
FFX_INIT bit 0MAIN[41][16]MAIN[6][16]
FFY_INIT bit 0MAIN[35][16]MAIN[12][16]
FFX_READBACK bit 0MAIN[45][16]MAIN[2][16]
FFY_READBACK bit 0MAIN[39][16]MAIN[8][16]
FF_LATCHMAIN[44][16]MAIN[3][16]
FF_REV_ENABLEMAIN[28][16]MAIN[19][16]
FF_SR_SYNCMAIN[43][16]MAIN[4][16]
FF_SR_ENABLEMAIN[29][14]MAIN[18][14]
FXMUX[enum: SLICE_FXMUX][enum: SLICE_FXMUX]
GYMUX[enum: SLICE_GYMUX][enum: SLICE_GYMUX]
DXMUX[enum: SLICE_DXMUX][enum: SLICE_DXMUX]
DYMUX[enum: SLICE_DYMUX][enum: SLICE_DYMUX]
YBMUX[enum: SLICE_YBMUX][enum: SLICE_YBMUX]
virtex CLB enum SLICE_DIF_MUX
SLICE[0].DIF_MUXMAIN[31][15]
SLICE[1].DIF_MUXMAIN[16][15]
BX0
BY1
virtex CLB enum SLICE_CYINIT
SLICE[0].CYINITMAIN[25][16]
SLICE[1].CYINITMAIN[22][16]
BX1
CIN0
virtex CLB enum SLICE_CY0
SLICE[0].CY0MAIN[30][16]MAIN[32][16]
SLICE[1].CY0MAIN[17][16]MAIN[15][16]
CONST_000
CONST_101
F1_G110
PROD11
virtex CLB enum SLICE_CYSELF
SLICE[0].CYSELFMAIN[26][16]
SLICE[1].CYSELFMAIN[21][16]
CONST_10
F1
virtex CLB enum SLICE_CYSELG
SLICE[0].CYSELGMAIN[27][16]
SLICE[1].CYSELGMAIN[20][16]
CONST_10
G1
virtex CLB enum SLICE_FXMUX
SLICE[0].FXMUXMAIN[29][15]MAIN[31][16]
SLICE[1].FXMUXMAIN[18][15]MAIN[16][16]
F01
F510
FXOR00
virtex CLB enum SLICE_GYMUX
SLICE[0].GYMUXMAIN[28][15]MAIN[24][16]
SLICE[1].GYMUXMAIN[19][15]MAIN[23][16]
G01
F610
GXOR00
virtex CLB enum SLICE_DXMUX
SLICE[0].DXMUXMAIN[46][16]
SLICE[1].DXMUXMAIN[1][16]
BX1
X0
virtex CLB enum SLICE_DYMUX
SLICE[0].DYMUXMAIN[40][16]
SLICE[1].DYMUXMAIN[7][16]
BY1
Y0
virtex CLB enum SLICE_YBMUX
SLICE[0].YBMUXMAIN[29][16]
SLICE[1].YBMUXMAIN[18][16]
GCY0
BY1

Bels TBUF

virtex CLB bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinIMUX_TBUF_I[0] invert by !MAIN[37][13]IMUX_TBUF_I[1] invert by !MAIN[10][13]
TinIMUX_TBUF_T[0] invert by MAIN[46][13]IMUX_TBUF_T[1] invert by MAIN[47][13]
virtex CLB bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
OUT_A!MAIN[36][16]!MAIN[0][16]
OUT_B!MAIN[47][16]!MAIN[37][16]

Bels TBUS

virtex CLB bel TBUS pins
PinDirectionTBUS
OUToutOUT_TBUF
virtex CLB bel TBUS attribute bits
AttributeTBUS
JOINER_E!MAIN[11][16]

Bel wires

virtex CLB bel wires
WirePins
IMUX_CLB_CLK[0]SLICE[0].CLK
IMUX_CLB_CLK[1]SLICE[1].CLK
IMUX_CLB_SR[0]SLICE[0].SR
IMUX_CLB_SR[1]SLICE[1].SR
IMUX_CLB_CE[0]SLICE[0].CE
IMUX_CLB_CE[1]SLICE[1].CE
IMUX_CLB_BX[0]SLICE[0].BX
IMUX_CLB_BX[1]SLICE[1].BX
IMUX_CLB_BY[0]SLICE[0].BY
IMUX_CLB_BY[1]SLICE[1].BY
IMUX_CLB_F1[0]SLICE[0].F1
IMUX_CLB_F1[1]SLICE[1].F1
IMUX_CLB_F2[0]SLICE[0].F2
IMUX_CLB_F2[1]SLICE[1].F2
IMUX_CLB_F3[0]SLICE[0].F3
IMUX_CLB_F3[1]SLICE[1].F3
IMUX_CLB_F4[0]SLICE[0].F4
IMUX_CLB_F4[1]SLICE[1].F4
IMUX_CLB_G1[0]SLICE[0].G1
IMUX_CLB_G1[1]SLICE[1].G1
IMUX_CLB_G2[0]SLICE[0].G2
IMUX_CLB_G2[1]SLICE[1].G2
IMUX_CLB_G3[0]SLICE[0].G3
IMUX_CLB_G3[1]SLICE[1].G3
IMUX_CLB_G4[0]SLICE[0].G4
IMUX_CLB_G4[1]SLICE[1].G4
IMUX_TBUF_T[0]TBUF[0].T
IMUX_TBUF_T[1]TBUF[1].T
IMUX_TBUF_I[0]TBUF[0].I
IMUX_TBUF_I[1]TBUF[1].I
OUT_CLB_X[0]SLICE[0].X
OUT_CLB_X[1]SLICE[1].X
OUT_CLB_Y[0]SLICE[0].Y
OUT_CLB_Y[1]SLICE[1].Y
OUT_CLB_XQ[0]SLICE[0].XQ
OUT_CLB_XQ[1]SLICE[1].XQ
OUT_CLB_YQ[0]SLICE[0].YQ
OUT_CLB_YQ[1]SLICE[1].YQ
OUT_CLB_XB[0]SLICE[0].XB
OUT_CLB_XB[1]SLICE[1].XB
OUT_CLB_YB[0]SLICE[0].YB
OUT_CLB_YB[1]SLICE[1].YB
OUT_TBUFTBUS.OUT

Bitstream

virtex CLB rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47
B17 INT: mux OMUX[6] bit 4 INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 5 INT: mux OMUX[7] bit 2 INT: mux OMUX[7] bit 4 INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 1 INT: mux OMUX[7] bit 3 INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 5 INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 3 INT: mux OMUX[5] bit 3 INT: mux OMUX[5] bit 6 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 3 INT: mux OMUX[4] bit 1 INT: mux OMUX[4] bit 0 INT: mux OMUX[4] bit 4 INT: mux OMUX[4] bit 2 INT: mux OMUX[4] bit 5 INT: mux OMUX[5] bit 2 INT: mux OMUX[5] bit 4 INT: mux OMUX[2] bit 4 INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 5 INT: mux OMUX[3] bit 2 INT: mux OMUX[3] bit 4 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 1 INT: mux OMUX[3] bit 3 INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 3 INT: mux OMUX[1] bit 3 INT: mux OMUX[1] bit 6 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 3 INT: mux OMUX[0] bit 1 INT: mux OMUX[0] bit 0 INT: mux OMUX[0] bit 4 INT: mux OMUX[0] bit 2 INT: mux OMUX[0] bit 5 INT: mux OMUX[1] bit 2 INT: mux OMUX[1] bit 4
B16 TBUF[1]: ! OUT_A SLICE[1]: DXMUX bit 0 SLICE[1]: FFX_READBACK bit 0 SLICE[1]: FF_LATCH SLICE[1]: FF_SR_SYNC INT: mux OMUX[6] bit 0 SLICE[1]: FFX_INIT bit 0 SLICE[1]: DYMUX bit 0 SLICE[1]: FFY_READBACK bit 0 INT: mux OMUX[6] bit 1 - TBUS: ! JOINER_E SLICE[1]: FFY_INIT bit 0 INT: mux OMUX[5] bit 1 INT: mux OMUX[5] bit 0 SLICE[1]: CY0 bit 0 SLICE[1]: FXMUX bit 0 SLICE[1]: CY0 bit 1 SLICE[1]: YBMUX bit 0 SLICE[1]: FF_REV_ENABLE SLICE[1]: CYSELG bit 0 SLICE[1]: CYSELF bit 0 SLICE[1]: CYINIT bit 0 SLICE[1]: GYMUX bit 0 SLICE[0]: GYMUX bit 0 SLICE[0]: CYINIT bit 0 SLICE[0]: CYSELF bit 0 SLICE[0]: CYSELG bit 0 SLICE[0]: FF_REV_ENABLE SLICE[0]: YBMUX bit 0 SLICE[0]: CY0 bit 1 SLICE[0]: FXMUX bit 0 SLICE[0]: CY0 bit 0 INT: mux OMUX[2] bit 0 INT: mux OMUX[2] bit 1 SLICE[0]: FFY_INIT bit 0 TBUF[0]: ! OUT_A TBUF[1]: ! OUT_B INT: mux OMUX[1] bit 1 SLICE[0]: FFY_READBACK bit 0 SLICE[0]: DYMUX bit 0 SLICE[0]: FFX_INIT bit 0 INT: mux OMUX[1] bit 0 SLICE[0]: FF_SR_SYNC SLICE[0]: FF_LATCH SLICE[0]: FFX_READBACK bit 0 SLICE[0]: DXMUX bit 0 TBUF[0]: ! OUT_B
B15 SLICE[1]: ! G bit 15 SLICE[1]: ! G bit 14 SLICE[1]: ! G bit 13 SLICE[1]: ! G bit 12 SLICE[1]: ! G bit 11 SLICE[1]: ! G bit 10 SLICE[1]: ! G bit 9 SLICE[1]: ! G bit 8 SLICE[1]: ! G bit 7 SLICE[1]: ! G bit 6 SLICE[1]: ! G bit 5 SLICE[1]: ! G bit 4 SLICE[1]: ! G bit 3 SLICE[1]: ! G bit 2 SLICE[1]: ! G bit 1 SLICE[1]: ! G bit 0 SLICE[1]: DIF_MUX bit 0 - SLICE[1]: FXMUX bit 1 SLICE[1]: GYMUX bit 1 INT: mux IMUX_CLB_F4[1] bit 5 INT: mux IMUX_CLB_F2[0] bit 3 INT: mux IMUX_CLB_F2[0] bit 2 INT: mux IMUX_CLB_F2[1] bit 3 INT: mux IMUX_CLB_G3[1] bit 6 INT: mux IMUX_CLB_F2[1] bit 2 INT: mux IMUX_CLB_G3[0] bit 6 INT: mux IMUX_CLB_F4[0] bit 2 SLICE[0]: GYMUX bit 1 SLICE[0]: FXMUX bit 1 - SLICE[0]: DIF_MUX bit 0 SLICE[0]: ! G bit 0 SLICE[0]: ! G bit 1 SLICE[0]: ! G bit 2 SLICE[0]: ! G bit 3 SLICE[0]: ! G bit 4 SLICE[0]: ! G bit 5 SLICE[0]: ! G bit 6 SLICE[0]: ! G bit 7 SLICE[0]: ! G bit 8 SLICE[0]: ! G bit 9 SLICE[0]: ! G bit 10 SLICE[0]: ! G bit 11 SLICE[0]: ! G bit 12 SLICE[0]: ! G bit 13 SLICE[0]: ! G bit 14 SLICE[0]: ! G bit 15
B14 SLICE[1]: ! F bit 15 SLICE[1]: ! F bit 14 SLICE[1]: ! F bit 13 SLICE[1]: ! F bit 12 SLICE[1]: ! F bit 11 SLICE[1]: ! F bit 10 SLICE[1]: ! F bit 9 SLICE[1]: ! F bit 8 SLICE[1]: ! F bit 7 SLICE[1]: ! F bit 6 SLICE[1]: ! F bit 5 SLICE[1]: ! F bit 4 SLICE[1]: ! F bit 3 SLICE[1]: ! F bit 2 SLICE[1]: ! F bit 1 SLICE[1]: ! F bit 0 - - SLICE[1]: FF_SR_ENABLE SLICE[1]: ! G_RAM_ENABLE SLICE[1]: ! F_RAM_ENABLE SLICE[1]: ! F_SHIFT_ENABLE SLICE[1]: WA4_ENABLE SLICE[1]: ! G_SHIFT_ENABLE SLICE[0]: ! G_SHIFT_ENABLE SLICE[0]: WA4_ENABLE SLICE[0]: ! F_SHIFT_ENABLE SLICE[0]: ! F_RAM_ENABLE SLICE[0]: ! G_RAM_ENABLE SLICE[0]: FF_SR_ENABLE - - SLICE[0]: ! F bit 0 SLICE[0]: ! F bit 1 SLICE[0]: ! F bit 2 SLICE[0]: ! F bit 3 SLICE[0]: ! F bit 4 SLICE[0]: ! F bit 5 SLICE[0]: ! F bit 6 SLICE[0]: ! F bit 7 SLICE[0]: ! F bit 8 SLICE[0]: ! F bit 9 SLICE[0]: ! F bit 10 SLICE[0]: ! F bit 11 SLICE[0]: ! F bit 12 SLICE[0]: ! F bit 13 SLICE[0]: ! F bit 14 SLICE[0]: ! F bit 15
B13 SLICE[1]: invert CE SLICE[0]: invert CE INT: mux IMUX_CLB_F4[1] bit 6 INT: mux IMUX_CLB_G4[1] bit 6 INT: mux IMUX_CLB_G4[1] bit 7 INT: mux IMUX_CLB_G4[1] bit 8 INT: mux IMUX_CLB_G1[0] bit 6 INT: mux IMUX_CLB_G1[0] bit 8 INT: mux IMUX_CLB_G1[0] bit 7 INT: !buffer LV[6] ← LV_MUX[6] TBUF[1]: !invert I SLICE[1]: invert BX INT: mux LH_MUX[6] bit 0 SLICE[1]: invert BY INT: !buffer LH[6] ← LH_MUX[6] INT: mux IMUX_CLB_G3[1] bit 7 INT: mux IMUX_CLB_G3[1] bit 8 INT: mux IMUX_CLB_F3[1] bit 6 INT: mux IMUX_CLB_G2[0] bit 7 INT: mux IMUX_CLB_G2[0] bit 8 INT: mux IMUX_CLB_G2[0] bit 6 INT: mux IMUX_CLB_F2[0] bit 6 SLICE[1]: invert CLK SLICE[0]: invert CLK SLICE[1]: !invert SR SLICE[0]: !invert SR INT: mux IMUX_CLB_F2[1] bit 6 INT: mux IMUX_CLB_G2[1] bit 6 INT: mux IMUX_CLB_G2[1] bit 7 INT: mux IMUX_CLB_G2[1] bit 8 INT: mux IMUX_CLB_F3[0] bit 6 INT: mux IMUX_CLB_G3[0] bit 8 INT: mux IMUX_CLB_G3[0] bit 7 INT: mux LH_MUX[0] bit 0 INT: !buffer LH[0] ← LH_MUX[0] SLICE[0]: invert BY INT: !buffer LV[0] ← LV_MUX[0] TBUF[0]: !invert I SLICE[0]: invert BX INT: mux IMUX_CLB_G1[1] bit 8 INT: mux IMUX_CLB_G1[1] bit 7 INT: mux IMUX_CLB_G1[1] bit 6 INT: mux IMUX_CLB_G4[0] bit 7 INT: mux IMUX_CLB_G4[0] bit 8 INT: mux IMUX_CLB_G4[0] bit 6 INT: mux IMUX_CLB_F4[0] bit 6 TBUF[0]: invert T TBUF[1]: invert T
B12 INT: mux IMUX_CLB_CE[0] bit 3 INT: mux IMUX_CLB_CE[1] bit 4 INT: mux IMUX_CLB_CE[1] bit 3 INT: mux IMUX_CLB_F4[1] bit 1 INT: mux IMUX_CLB_F4[1] bit 7 INT: mux IMUX_CLB_G4[1] bit 5 INT: mux IMUX_CLB_F4[1] bit 8 INT: mux IMUX_CLB_F1[0] bit 8 INT: mux IMUX_CLB_F1[0] bit 7 INT: mux IMUX_CLB_F1[0] bit 6 INT: mux IMUX_CLB_F4[1] bit 2 INT: mux IMUX_CLB_BX[1] bit 2 INT: mux IMUX_CLB_BX[1] bit 5 INT: mux IMUX_CLB_BY[1] bit 2 INT: mux IMUX_CLB_G3[1] bit 3 INT: mux IMUX_CLB_F3[1] bit 7 INT: mux IMUX_CLB_F3[1] bit 8 INT: mux IMUX_CLB_F2[0] bit 7 INT: mux IMUX_CLB_G2[0] bit 3 INT: mux IMUX_CLB_F2[0] bit 8 INT: mux IMUX_CLB_F2[0] bit 4 INT: mux IMUX_CLB_CLK[0] bit 3 INT: mux IMUX_CLB_CLK[0] bit 4 INT: mux IMUX_CLB_CLK[1] bit 3 INT: mux IMUX_CLB_SR[0] bit 3 INT: mux IMUX_CLB_SR[1] bit 4 INT: mux IMUX_CLB_SR[1] bit 3 INT: mux IMUX_CLB_F2[1] bit 5 INT: mux IMUX_CLB_F2[1] bit 7 INT: mux IMUX_CLB_G2[1] bit 3 INT: mux IMUX_CLB_F2[1] bit 8 INT: mux IMUX_CLB_F3[0] bit 8 INT: mux IMUX_CLB_F3[0] bit 7 INT: mux IMUX_CLB_G3[0] bit 3 INT: mux IMUX_CLB_BY[0] bit 3 INT: mux IMUX_CLB_BX[0] bit 4 INT: mux IMUX_CLB_BX[0] bit 3 INT: mux IMUX_CLB_F4[0] bit 1 INT: mux IMUX_CLB_F1[1] bit 6 INT: mux IMUX_CLB_F1[1] bit 8 INT: mux IMUX_CLB_F1[1] bit 7 INT: mux IMUX_CLB_F4[0] bit 7 INT: mux IMUX_CLB_G4[0] bit 2 INT: mux IMUX_CLB_F4[0] bit 8 INT: mux IMUX_CLB_F4[0] bit 4 INT: mux IMUX_TBUF_T[1] bit 1 INT: mux IMUX_TBUF_T[1] bit 4 INT: mux IMUX_TBUF_T[0] bit 1
B11 INT: mux IMUX_CLB_CE[1] bit 5 INT: mux IMUX_CLB_CE[0] bit 4 INT: mux IMUX_CLB_CE[0] bit 5 INT: mux IMUX_CLB_G4[1] bit 1 INT: mux IMUX_CLB_F4[1] bit 4 INT: mux IMUX_CLB_G4[1] bit 4 INT: mux IMUX_CLB_F1[0] bit 4 INT: mux IMUX_CLB_G1[0] bit 1 INT: mux IMUX_CLB_F1[0] bit 1 INT: mux IMUX_TBUF_I[1] bit 2 INT: mux IMUX_TBUF_I[1] bit 1 INT: mux LV_MUX[6] bit 2 INT: mux IMUX_CLB_BX[1] bit 4 INT: mux IMUX_CLB_BY[1] bit 4 INT: mux IMUX_CLB_BY[1] bit 5 INT: mux IMUX_CLB_F3[1] bit 5 INT: mux IMUX_CLB_G3[1] bit 5 INT: mux IMUX_CLB_F3[1] bit 3 INT: mux IMUX_CLB_G2[0] bit 5 INT: mux IMUX_CLB_F2[0] bit 5 INT: mux IMUX_CLB_G2[0] bit 4 INT: mux IMUX_CLB_CLK[1] bit 4 INT: mux IMUX_CLB_CLK[1] bit 5 INT: mux IMUX_CLB_CLK[0] bit 5 INT: mux IMUX_CLB_SR[1] bit 5 INT: mux IMUX_CLB_SR[0] bit 5 INT: mux IMUX_CLB_SR[0] bit 4 INT: mux IMUX_CLB_G2[1] bit 5 INT: mux IMUX_CLB_F2[1] bit 4 INT: mux IMUX_CLB_G2[1] bit 4 INT: mux IMUX_CLB_F3[0] bit 3 INT: mux IMUX_CLB_G3[0] bit 5 INT: mux IMUX_CLB_F3[0] bit 5 INT: mux IMUX_CLB_BY[0] bit 4 INT: mux IMUX_CLB_BY[0] bit 5 INT: mux IMUX_CLB_BX[0] bit 5 INT: mux LV_MUX[0] bit 0 INT: mux IMUX_TBUF_I[0] bit 0 INT: mux IMUX_TBUF_I[0] bit 1 INT: mux IMUX_CLB_F1[1] bit 4 INT: mux IMUX_CLB_G1[1] bit 4 INT: mux IMUX_CLB_F1[1] bit 2 INT: mux IMUX_CLB_G4[0] bit 5 INT: mux IMUX_CLB_F4[0] bit 5 INT: mux IMUX_CLB_G4[0] bit 4 INT: mux IMUX_TBUF_T[0] bit 4 INT: mux IMUX_TBUF_T[0] bit 5 INT: mux IMUX_TBUF_T[1] bit 5
B10 INT: mux IMUX_CLB_CE[0] bit 2 INT: mux IMUX_CLB_CE[1] bit 2 INT: mux IMUX_CLB_CE[1] bit 0 INT: mux IMUX_CLB_G4[1] bit 2 INT: mux IMUX_CLB_G4[1] bit 0 INT: mux IMUX_CLB_G4[1] bit 3 INT: mux IMUX_CLB_G1[0] bit 2 INT: mux IMUX_CLB_F1[0] bit 0 INT: mux IMUX_CLB_G1[0] bit 3 INT: mux LV_MUX[6] bit 0 INT: mux LV_MUX[6] bit 1 INT: mux IMUX_TBUF_I[1] bit 0 INT: mux IMUX_CLB_BY[1] bit 0 INT: mux IMUX_CLB_BX[1] bit 3 INT: mux IMUX_CLB_BY[1] bit 3 INT: mux IMUX_CLB_G3[1] bit 1 INT: mux IMUX_CLB_F3[1] bit 0 INT: mux IMUX_CLB_G3[1] bit 2 INT: mux IMUX_CLB_G2[0] bit 1 INT: mux IMUX_CLB_G2[0] bit 0 INT: mux IMUX_CLB_G2[0] bit 2 INT: mux IMUX_CLB_CLK[0] bit 2 INT: mux IMUX_CLB_CLK[0] bit 0 INT: mux IMUX_CLB_CLK[1] bit 0 INT: mux IMUX_CLB_SR[0] bit 0 INT: mux IMUX_CLB_SR[1] bit 0 INT: mux IMUX_CLB_SR[1] bit 1 INT: mux IMUX_CLB_G2[1] bit 2 INT: mux IMUX_CLB_G2[1] bit 0 INT: mux IMUX_CLB_G2[1] bit 1 INT: mux IMUX_CLB_G3[0] bit 1 INT: mux IMUX_CLB_F3[0] bit 0 INT: mux IMUX_CLB_G3[0] bit 4 INT: mux IMUX_CLB_BY[0] bit 1 INT: mux IMUX_CLB_BX[0] bit 1 INT: mux IMUX_CLB_BY[0] bit 0 INT: mux IMUX_TBUF_I[0] bit 2 INT: mux LV_MUX[0] bit 2 INT: mux LV_MUX[0] bit 1 INT: mux IMUX_CLB_G1[1] bit 3 INT: mux IMUX_CLB_F1[1] bit 0 INT: mux IMUX_CLB_G1[1] bit 1 INT: mux IMUX_CLB_G4[0] bit 3 INT: mux IMUX_CLB_G4[0] bit 0 INT: mux IMUX_CLB_G4[0] bit 1 INT: mux IMUX_TBUF_T[1] bit 2 INT: mux IMUX_TBUF_T[1] bit 0 INT: mux IMUX_TBUF_T[0] bit 0
B9 INT: mux IMUX_CLB_CE[1] bit 1 INT: mux IMUX_CLB_CE[0] bit 0 INT: mux IMUX_CLB_CE[0] bit 1 INT: mux IMUX_CLB_F4[1] bit 3 INT: mux IMUX_CLB_F4[1] bit 0 INT: mux IMUX_CLB_F1[0] bit 5 INT: mux IMUX_CLB_F1[0] bit 3 INT: mux IMUX_CLB_G1[0] bit 0 INT: mux IMUX_CLB_F1[0] bit 2 INT: mux IMUX_CLB_G1[0] bit 5 INT: mux IMUX_CLB_G1[0] bit 4 INT: mux IMUX_CLB_BY[1] bit 1 INT: mux IMUX_CLB_BX[1] bit 0 INT: mux IMUX_CLB_BX[1] bit 1 INT: mux IMUX_CLB_G3[1] bit 4 INT: mux IMUX_CLB_F3[1] bit 2 INT: mux IMUX_CLB_G3[1] bit 0 INT: mux IMUX_CLB_F3[1] bit 1 INT: mux IMUX_CLB_F3[1] bit 4 INT: mux IMUX_CLB_F2[0] bit 0 INT: mux IMUX_CLB_F2[0] bit 1 INT: mux IMUX_CLB_CLK[1] bit 1 INT: mux IMUX_CLB_CLK[1] bit 2 INT: mux IMUX_CLB_CLK[0] bit 1 INT: mux IMUX_CLB_SR[1] bit 2 INT: mux IMUX_CLB_SR[0] bit 1 INT: mux IMUX_CLB_SR[0] bit 2 INT: mux IMUX_CLB_F2[1] bit 1 INT: mux IMUX_CLB_F2[1] bit 0 INT: mux IMUX_CLB_F3[0] bit 2 INT: mux IMUX_CLB_F3[0] bit 4 INT: mux IMUX_CLB_G3[0] bit 0 INT: mux IMUX_CLB_F3[0] bit 1 INT: mux IMUX_CLB_G3[0] bit 2 INT: mux IMUX_CLB_BX[0] bit 2 INT: mux IMUX_CLB_BX[0] bit 0 INT: mux IMUX_CLB_BY[0] bit 2 INT: mux IMUX_CLB_G1[1] bit 2 INT: mux IMUX_CLB_G1[1] bit 5 INT: mux IMUX_CLB_F1[1] bit 1 INT: mux IMUX_CLB_G1[1] bit 0 INT: mux IMUX_CLB_F1[1] bit 3 INT: mux IMUX_CLB_F1[1] bit 5 INT: mux IMUX_CLB_F4[0] bit 0 INT: mux IMUX_CLB_F4[0] bit 3 INT: mux IMUX_TBUF_T[0] bit 3 INT: mux IMUX_TBUF_T[0] bit 2 INT: mux IMUX_TBUF_T[1] bit 3
B8 INT: bipass SINGLE_W[0] = SINGLE_N[23] INT: bipass SINGLE_W[3] = SINGLE_S[21] INT: bipass SINGLE_W[3] = SINGLE_N[22] INT: bipass SINGLE_W[22] = SINGLE_E[22] INT: bipass SINGLE_W[22] = SINGLE_N[21] INT: bipass SINGLE_W[1] = SINGLE_S[23] INT: bipass SINGLE_W[1] = SINGLE_N[20] INT: bipass SINGLE_W[20] = SINGLE_E[20] INT: bipass SINGLE_W[20] = SINGLE_N[19] INT: bipass SINGLE_W[23] = SINGLE_S[17] INT: bipass SINGLE_W[23] = SINGLE_N[18] INT: bipass SINGLE_W[18] = SINGLE_E[18] INT: bipass SINGLE_W[18] = SINGLE_N[17] INT: bipass SINGLE_W[21] = SINGLE_S[19] INT: bipass SINGLE_W[21] = SINGLE_N[16] INT: bipass SINGLE_W[16] = SINGLE_E[16] INT: bipass SINGLE_W[16] = SINGLE_N[15] INT: bipass SINGLE_W[19] = SINGLE_S[13] INT: bipass SINGLE_W[19] = SINGLE_N[14] INT: bipass SINGLE_W[14] = SINGLE_E[14] INT: bipass SINGLE_W[14] = SINGLE_N[13] INT: bipass SINGLE_W[17] = SINGLE_S[15] INT: bipass SINGLE_W[17] = SINGLE_N[12] INT: bipass SINGLE_W[12] = SINGLE_E[12] INT: bipass SINGLE_W[12] = SINGLE_N[11] INT: bipass SINGLE_W[15] = SINGLE_S[9] INT: bipass SINGLE_W[15] = SINGLE_N[10] INT: bipass SINGLE_W[10] = SINGLE_E[10] INT: bipass SINGLE_W[10] = SINGLE_N[9] INT: bipass SINGLE_W[13] = SINGLE_S[11] INT: bipass SINGLE_W[13] = SINGLE_N[8] INT: bipass SINGLE_W[8] = SINGLE_E[8] INT: bipass SINGLE_W[8] = SINGLE_N[7] INT: bipass SINGLE_W[11] = SINGLE_S[5] INT: bipass SINGLE_W[11] = SINGLE_N[6] INT: bipass SINGLE_W[6] = SINGLE_E[6] INT: bipass SINGLE_W[6] = SINGLE_N[5] INT: bipass SINGLE_W[9] = SINGLE_S[7] INT: bipass SINGLE_W[9] = SINGLE_N[4] INT: bipass SINGLE_W[4] = SINGLE_E[4] INT: bipass SINGLE_W[4] = SINGLE_N[3] INT: bipass SINGLE_W[7] = SINGLE_S[1] INT: bipass SINGLE_W[7] = SINGLE_N[2] INT: bipass SINGLE_W[2] = SINGLE_E[2] INT: bipass SINGLE_W[2] = SINGLE_N[1] INT: bipass SINGLE_W[5] = SINGLE_S[3] INT: bipass SINGLE_W[5] = SINGLE_N[0] INT: bipass SINGLE_W[0] = SINGLE_E[0]
B7 INT: bipass SINGLE_E[23] = SINGLE_N[23] INT: bipass SINGLE_E[23] = SINGLE_S[21] INT: bipass SINGLE_E[18] = SINGLE_N[22] INT: bipass SINGLE_E[18] = SINGLE_S[20] INT: bipass SINGLE_E[21] = SINGLE_N[21] INT: bipass SINGLE_E[21] = SINGLE_S[23] INT: bipass SINGLE_E[16] = SINGLE_N[20] INT: bipass SINGLE_E[16] = SINGLE_S[22] INT: bipass SINGLE_E[19] = SINGLE_N[19] INT: bipass SINGLE_E[19] = SINGLE_S[17] INT: bipass SINGLE_E[14] = SINGLE_N[18] INT: bipass SINGLE_E[14] = SINGLE_S[16] INT: bipass SINGLE_E[17] = SINGLE_N[17] INT: bipass SINGLE_E[17] = SINGLE_S[19] INT: bipass SINGLE_E[12] = SINGLE_N[16] INT: bipass SINGLE_E[12] = SINGLE_S[18] INT: bipass SINGLE_E[15] = SINGLE_N[15] INT: bipass SINGLE_E[15] = SINGLE_S[13] INT: bipass SINGLE_E[10] = SINGLE_N[14] INT: bipass SINGLE_E[10] = SINGLE_S[12] INT: bipass SINGLE_E[13] = SINGLE_N[13] INT: bipass SINGLE_E[13] = SINGLE_S[15] INT: bipass SINGLE_E[8] = SINGLE_N[12] INT: bipass SINGLE_E[8] = SINGLE_S[14] INT: bipass SINGLE_E[11] = SINGLE_N[11] INT: bipass SINGLE_E[11] = SINGLE_S[9] INT: bipass SINGLE_E[6] = SINGLE_N[10] INT: bipass SINGLE_E[6] = SINGLE_S[8] INT: bipass SINGLE_E[9] = SINGLE_N[9] INT: bipass SINGLE_E[9] = SINGLE_S[11] INT: bipass SINGLE_E[4] = SINGLE_N[8] INT: bipass SINGLE_E[4] = SINGLE_S[10] INT: bipass SINGLE_E[7] = SINGLE_N[7] INT: bipass SINGLE_E[7] = SINGLE_S[5] INT: bipass SINGLE_E[2] = SINGLE_N[6] INT: bipass SINGLE_E[2] = SINGLE_S[4] INT: bipass SINGLE_E[5] = SINGLE_N[5] INT: bipass SINGLE_E[5] = SINGLE_S[7] INT: bipass SINGLE_E[0] = SINGLE_N[4] INT: bipass SINGLE_E[0] = SINGLE_S[6] INT: bipass SINGLE_E[3] = SINGLE_N[3] INT: bipass SINGLE_E[3] = SINGLE_S[1] INT: bipass SINGLE_E[22] = SINGLE_N[2] INT: bipass SINGLE_E[22] = SINGLE_S[0] INT: bipass SINGLE_E[1] = SINGLE_N[1] INT: bipass SINGLE_E[1] = SINGLE_S[3] INT: bipass SINGLE_E[20] = SINGLE_N[0] INT: bipass SINGLE_E[20] = SINGLE_S[2]
B6 INT: bipass SINGLE_S[23] = SINGLE_N[23] INT: bipass SINGLE_W[23] = SINGLE_E[23] INT: bipass SINGLE_S[22] = SINGLE_N[22] INT: bipass SINGLE_W[22] = SINGLE_S[20] INT: bipass SINGLE_S[21] = SINGLE_N[21] INT: bipass SINGLE_W[21] = SINGLE_E[21] INT: bipass SINGLE_S[20] = SINGLE_N[20] INT: bipass SINGLE_W[20] = SINGLE_S[22] INT: bipass SINGLE_S[19] = SINGLE_N[19] INT: bipass SINGLE_W[19] = SINGLE_E[19] INT: bipass SINGLE_S[18] = SINGLE_N[18] INT: bipass SINGLE_W[18] = SINGLE_S[16] INT: bipass SINGLE_S[17] = SINGLE_N[17] INT: bipass SINGLE_W[17] = SINGLE_E[17] INT: bipass SINGLE_S[16] = SINGLE_N[16] INT: bipass SINGLE_W[16] = SINGLE_S[18] INT: bipass SINGLE_S[15] = SINGLE_N[15] INT: bipass SINGLE_W[15] = SINGLE_E[15] INT: bipass SINGLE_S[14] = SINGLE_N[14] INT: bipass SINGLE_W[14] = SINGLE_S[12] INT: bipass SINGLE_S[13] = SINGLE_N[13] INT: bipass SINGLE_W[13] = SINGLE_E[13] INT: bipass SINGLE_S[12] = SINGLE_N[12] INT: bipass SINGLE_W[12] = SINGLE_S[14] INT: bipass SINGLE_S[11] = SINGLE_N[11] INT: bipass SINGLE_W[11] = SINGLE_E[11] INT: bipass SINGLE_S[10] = SINGLE_N[10] INT: bipass SINGLE_W[10] = SINGLE_S[8] INT: bipass SINGLE_S[9] = SINGLE_N[9] INT: bipass SINGLE_W[9] = SINGLE_E[9] INT: bipass SINGLE_S[8] = SINGLE_N[8] INT: bipass SINGLE_W[8] = SINGLE_S[10] INT: bipass SINGLE_S[7] = SINGLE_N[7] INT: bipass SINGLE_W[7] = SINGLE_E[7] INT: bipass SINGLE_S[6] = SINGLE_N[6] INT: bipass SINGLE_W[6] = SINGLE_S[4] INT: bipass SINGLE_S[5] = SINGLE_N[5] INT: bipass SINGLE_W[5] = SINGLE_E[5] INT: bipass SINGLE_S[4] = SINGLE_N[4] INT: bipass SINGLE_W[4] = SINGLE_S[6] INT: bipass SINGLE_S[3] = SINGLE_N[3] INT: bipass SINGLE_W[3] = SINGLE_E[3] INT: bipass SINGLE_S[2] = SINGLE_N[2] INT: bipass SINGLE_W[2] = SINGLE_S[0] INT: bipass SINGLE_S[1] = SINGLE_N[1] INT: bipass SINGLE_W[1] = SINGLE_E[1] INT: bipass SINGLE_S[0] = SINGLE_N[0] INT: bipass SINGLE_W[0] = SINGLE_S[2]
B5 INT: pass SINGLE_W[22] ← OMUX[7] INT: pass SINGLE_E[23] ← OMUX[7] INT: pass SINGLE_E[20] ← OMUX[7] INT: pass SINGLE_S[22] ← OMUX[7] INT: pass SINGLE_N[21] ← OMUX[7] INT: pass SINGLE_W[23] ← OMUX[7] INT: pass SINGLE_N[20] ← OMUX[6] INT: pass SINGLE_E[18] ← OMUX[6] INT: pass SINGLE_W[21] ← OMUX[6] INT: pass SINGLE_S[19] ← OMUX[6] INT: pass SINGLE_N[18] ← OMUX[6] INT: pass SINGLE_S[17] ← OMUX[6] INT: pass SINGLE_E[17] ← OMUX[5] INT: pass SINGLE_W[17] ← OMUX[5] INT: pass SINGLE_W[16] ← OMUX[5] INT: pass SINGLE_E[15] ← OMUX[5] INT: pass SINGLE_N[14] ← OMUX[5] INT: pass SINGLE_S[12] ← OMUX[5] INT: pass SINGLE_W[19] ← OMUX[4] INT: pass SINGLE_E[14] ← OMUX[4] INT: pass SINGLE_S[15] ← OMUX[4] INT: pass SINGLE_N[13] ← OMUX[4] INT: pass SINGLE_N[12] ← OMUX[4] INT: pass SINGLE_S[13] ← OMUX[4] INT: pass SINGLE_W[10] ← OMUX[3] INT: pass SINGLE_E[11] ← OMUX[3] INT: pass SINGLE_E[8] ← OMUX[3] INT: pass SINGLE_S[10] ← OMUX[3] INT: pass SINGLE_N[9] ← OMUX[3] INT: pass SINGLE_W[11] ← OMUX[3] INT: pass SINGLE_N[8] ← OMUX[2] INT: pass SINGLE_E[6] ← OMUX[2] INT: pass SINGLE_W[9] ← OMUX[2] INT: pass SINGLE_S[7] ← OMUX[2] INT: pass SINGLE_N[6] ← OMUX[2] INT: pass SINGLE_S[5] ← OMUX[2] INT: pass SINGLE_E[5] ← OMUX[1] INT: pass SINGLE_W[5] ← OMUX[1] INT: pass SINGLE_W[4] ← OMUX[1] INT: pass SINGLE_E[3] ← OMUX[1] INT: pass SINGLE_N[2] ← OMUX[1] INT: pass SINGLE_S[0] ← OMUX[1] INT: pass SINGLE_W[7] ← OMUX[0] INT: pass SINGLE_E[2] ← OMUX[0] INT: pass SINGLE_S[3] ← OMUX[0] INT: pass SINGLE_N[1] ← OMUX[0] INT: pass SINGLE_N[0] ← OMUX[0] INT: pass SINGLE_S[1] ← OMUX[0]
B4 INT: pass SINGLE_S[20] ← HEX_H6[3] INT: pass SINGLE_E[23] ← HEX_H6[3] INT: pass SINGLE_N[22] ← HEX_H3[3] INT: pass SINGLE_S[21] ← HEX_H3[3] INT: pass SINGLE_E[21] ← HEX_V0[3] INT: pass SINGLE_S[22] ← HEX_V0[3] INT: pass SINGLE_W[21] ← HEX_V6[3] INT: pass SINGLE_N[19] ← HEX_V6[3] INT: pass SINGLE_E[19] ← HEX_V3[3] INT: pass SINGLE_W[20] ← HEX_V3[3] INT: pass SINGLE_N[18] ← HEX_H0[3] INT: pass SINGLE_W[18] ← HEX_H0[3] INT: pass SINGLE_S[16] ← HEX_H0[2] INT: pass SINGLE_W[17] ← HEX_H0[2] INT: pass SINGLE_N[16] ← HEX_H3[2] INT: pass SINGLE_S[18] ← HEX_H3[2] INT: pass SINGLE_W[16] ← HEX_V0[2] INT: pass SINGLE_S[14] ← HEX_V0[2] INT: pass SINGLE_E[12] ← HEX_V6[2] INT: pass SINGLE_N[13] ← HEX_V6[2] INT: pass SINGLE_W[15] ← HEX_V3[2] INT: pass SINGLE_E[13] ← HEX_V3[2] INT: pass SINGLE_N[12] ← HEX_H6[2] INT: pass SINGLE_E[10] ← HEX_H6[2] INT: pass SINGLE_S[8] ← HEX_H6[1] INT: pass SINGLE_E[11] ← HEX_H6[1] INT: pass SINGLE_N[10] ← HEX_H3[1] INT: pass SINGLE_S[9] ← HEX_H3[1] INT: pass SINGLE_E[9] ← HEX_V0[1] INT: pass SINGLE_S[10] ← HEX_V0[1] INT: pass SINGLE_W[9] ← HEX_V6[1] INT: pass SINGLE_N[7] ← HEX_V6[1] INT: pass SINGLE_E[7] ← HEX_V3[1] INT: pass SINGLE_W[8] ← HEX_V3[1] INT: pass SINGLE_N[6] ← HEX_H0[1] INT: pass SINGLE_W[6] ← HEX_H0[1] INT: pass SINGLE_S[4] ← HEX_H0[0] INT: pass SINGLE_W[5] ← HEX_H0[0] INT: pass SINGLE_N[4] ← HEX_H3[0] INT: pass SINGLE_S[6] ← HEX_H3[0] INT: pass SINGLE_W[4] ← HEX_V0[0] INT: pass SINGLE_S[2] ← HEX_V0[0] INT: pass SINGLE_E[0] ← HEX_V6[0] INT: pass SINGLE_N[1] ← HEX_V6[0] INT: pass SINGLE_W[3] ← HEX_V3[0] INT: pass SINGLE_E[1] ← HEX_V3[0] INT: pass SINGLE_N[0] ← HEX_H6[0] INT: pass SINGLE_E[22] ← HEX_H6[0]
B3 INT: !pass SINGLE_S[20] ← HEX_E3[3] INT: !pass SINGLE_W[22] ← HEX_N6[3] INT: !pass SINGLE_N[22] ← HEX_N6[3] INT: !pass SINGLE_W[1] ← HEX_S3[3] INT: !pass SINGLE_E[21] ← HEX_S3[3] INT: !pass SINGLE_W[23] ← HEX_W6[3] INT: !pass SINGLE_N[20] ← HEX_E6[3] INT: !pass SINGLE_S[23] ← HEX_W3[3] INT: !pass SINGLE_N[19] ← HEX_W3[3] INT: !pass SINGLE_W[20] ← HEX_S6[3] INT: !pass SINGLE_S[17] ← HEX_S6[3] INT: !pass SINGLE_W[18] ← HEX_N3[3] INT: !pass SINGLE_N[17] ← HEX_E3[1] INT: !pass SINGLE_E[17] ← HEX_N6[1] INT: !pass SINGLE_N[16] ← HEX_N6[1] INT: !pass SINGLE_E[15] ← HEX_E6[1] INT: !pass SINGLE_S[18] ← HEX_E6[1] INT: !pass SINGLE_N[15] ← HEX_W3[1] INT: !pass SINGLE_W[14] ← HEX_S3[1] INT: !pass SINGLE_W[15] ← HEX_W6[1] INT: !pass SINGLE_S[15] ← HEX_W6[1] INT: !pass SINGLE_E[13] ← HEX_S6[1] INT: !pass SINGLE_S[13] ← HEX_S6[1] INT: !pass SINGLE_E[10] ← HEX_N3[1] INT: !pass SINGLE_S[8] ← HEX_E3[2] INT: !pass SINGLE_W[10] ← HEX_N6[2] INT: !pass SINGLE_N[10] ← HEX_N6[2] INT: !pass SINGLE_E[9] ← HEX_S3[2] INT: !pass SINGLE_W[13] ← HEX_S3[2] INT: !pass SINGLE_W[11] ← HEX_W6[2] INT: !pass SINGLE_N[8] ← HEX_E6[2] INT: !pass SINGLE_S[11] ← HEX_W3[2] INT: !pass SINGLE_N[7] ← HEX_W3[2] INT: !pass SINGLE_W[8] ← HEX_S6[2] INT: !pass SINGLE_S[5] ← HEX_S6[2] INT: !pass SINGLE_W[6] ← HEX_N3[2] INT: !pass SINGLE_N[5] ← HEX_E3[0] INT: !pass SINGLE_E[5] ← HEX_N6[0] INT: !pass SINGLE_N[4] ← HEX_N6[0] INT: !pass SINGLE_E[3] ← HEX_E6[0] INT: !pass SINGLE_S[6] ← HEX_E6[0] INT: !pass SINGLE_N[3] ← HEX_W3[0] INT: !pass SINGLE_W[2] ← HEX_S3[0] INT: !pass SINGLE_W[3] ← HEX_W6[0] INT: !pass SINGLE_S[3] ← HEX_W6[0] INT: !pass SINGLE_E[1] ← HEX_S6[0] INT: !pass SINGLE_S[1] ← HEX_S6[0] INT: !pass SINGLE_E[22] ← HEX_N3[0]
B2 INT: !pass SINGLE_N[23] ← HEX_E3[3] INT: buffer HEX_H0[3] ← HEX_H0_MUX[3] - - INT: buffer HEX_H6[3] ← HEX_H6_MUX[3] INT: !pass SINGLE_N[21] ← HEX_W6[3] INT: !pass SINGLE_E[18] ← HEX_E6[3] INT: buffer HEX_V0[3] ← HEX_V0_MUX[3] - - INT: buffer HEX_V6[3] ← HEX_V6_MUX[3] INT: !pass SINGLE_E[16] ← HEX_N3[3] INT: !pass SINGLE_S[16] ← HEX_E3[1] INT: buffer HEX_H0[2] ← HEX_H0_MUX[2] - - INT: buffer HEX_H6[2] ← HEX_H6_MUX[2] INT: !pass SINGLE_S[14] ← HEX_W3[1] INT: !pass SINGLE_E[12] ← HEX_S3[1] INT: buffer HEX_V0[2] ← HEX_V0_MUX[2] - - INT: buffer HEX_V6[2] ← HEX_V6_MUX[2] INT: !pass SINGLE_W[12] ← HEX_N3[1] INT: !pass SINGLE_N[11] ← HEX_E3[2] INT: buffer HEX_H0[1] ← HEX_H0_MUX[1] - - INT: buffer HEX_H6[1] ← HEX_H6_MUX[1] INT: !pass SINGLE_N[9] ← HEX_W6[2] INT: !pass SINGLE_E[6] ← HEX_E6[2] INT: buffer HEX_V0[1] ← HEX_V0_MUX[1] - - INT: buffer HEX_V6[1] ← HEX_V6_MUX[1] INT: !pass SINGLE_E[4] ← HEX_N3[2] INT: !pass SINGLE_S[4] ← HEX_E3[0] INT: buffer HEX_H0[0] ← HEX_H0_MUX[0] - - INT: buffer HEX_H6[0] ← HEX_H6_MUX[0] INT: !pass SINGLE_S[2] ← HEX_W3[0] INT: !pass SINGLE_E[0] ← HEX_S3[0] INT: buffer HEX_V0[0] ← HEX_V0_MUX[0] - - INT: buffer HEX_V6[0] ← HEX_V6_MUX[0] INT: !pass SINGLE_W[0] ← HEX_N3[0]
B1 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_N0[3] bit 0 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux HEX_E0[3] bit 2 INT: mux HEX_W0[3] bit 1 INT: mux HEX_E0[3] bit 0 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 2 INT: mux HEX_N0[1] bit 0 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_E0[1] bit 2 INT: mux HEX_W0[1] bit 1 INT: mux HEX_E0[1] bit 0 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_N0[2] bit 0 INT: mux HEX_W0[2] bit 0 INT: mux HEX_E0[2] bit 1 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 2 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 0 INT: mux HEX_S0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux HEX_N0[0] bit 0 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_E0[0] bit 2 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 0
B0 INT: mux HEX_H6_MUX[3] bit 0 INT: mux HEX_H0_MUX[3] bit 0 INT: mux HEX_H6_MUX[3] bit 2 INT: mux HEX_H0_MUX[3] bit 2 INT: mux HEX_H6_MUX[3] bit 1 INT: mux HEX_H0_MUX[3] bit 1 INT: mux HEX_V6_MUX[3] bit 2 INT: mux HEX_V0_MUX[3] bit 1 INT: mux HEX_V6_MUX[3] bit 0 INT: mux HEX_V0_MUX[3] bit 0 INT: mux HEX_V6_MUX[3] bit 1 INT: mux HEX_V0_MUX[3] bit 2 INT: mux HEX_H6_MUX[2] bit 1 INT: mux HEX_H0_MUX[2] bit 0 INT: mux HEX_H6_MUX[2] bit 2 INT: mux HEX_H0_MUX[2] bit 2 INT: mux HEX_H6_MUX[2] bit 0 INT: mux HEX_H0_MUX[2] bit 1 INT: mux HEX_V6_MUX[2] bit 1 INT: mux HEX_V0_MUX[2] bit 1 INT: mux HEX_V6_MUX[2] bit 0 INT: mux HEX_V0_MUX[2] bit 0 INT: mux HEX_V6_MUX[2] bit 2 INT: mux HEX_V0_MUX[2] bit 2 INT: mux HEX_H6_MUX[1] bit 0 INT: mux HEX_H0_MUX[1] bit 0 INT: mux HEX_H6_MUX[1] bit 2 INT: mux HEX_H0_MUX[1] bit 2 INT: mux HEX_H6_MUX[1] bit 1 INT: mux HEX_H0_MUX[1] bit 1 INT: mux HEX_V6_MUX[1] bit 2 INT: mux HEX_V0_MUX[1] bit 1 INT: mux HEX_V6_MUX[1] bit 0 INT: mux HEX_V0_MUX[1] bit 0 INT: mux HEX_V6_MUX[1] bit 1 INT: mux HEX_V0_MUX[1] bit 2 INT: mux HEX_H6_MUX[0] bit 1 INT: mux HEX_H0_MUX[0] bit 0 INT: mux HEX_H6_MUX[0] bit 2 INT: mux HEX_H0_MUX[0] bit 2 INT: mux HEX_H6_MUX[0] bit 0 INT: mux HEX_H0_MUX[0] bit 1 INT: mux HEX_V6_MUX[0] bit 1 INT: mux HEX_V0_MUX[0] bit 1 INT: mux HEX_V6_MUX[0] bit 0 INT: mux HEX_V0_MUX[0] bit 0 INT: mux HEX_V6_MUX[0] bit 2 INT: mux HEX_V0_MUX[0] bit 2