Clock interconnect

Tile CLK_S_V

Cells: 3

Switchbox GCLK_INT

virtex CLK_S_V switchbox GCLK_INT muxes HEX_H1[0]
Bits	Destination
CELL.HEX_H1[0]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes HEX_H1[1]
Bits	Destination
CELL.HEX_H1[1]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes HEX_H1[2]
Bits	Destination
CELL.HEX_H1[2]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes HEX_H1[3]
Bits	Destination
CELL.HEX_H1[3]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes HEX_H6[0]
Bits	Destination
CELL.HEX_H6[0]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes HEX_H6[1]
Bits	Destination
CELL.HEX_H6[1]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes HEX_H6[2]
Bits	Destination
CELL.HEX_H6[2]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes HEX_H6[3]
Bits	Destination
CELL.HEX_H6[3]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes LH[0]
Bits	Destination
CELL.LH[0]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes LH[3]
Bits	Destination
CELL.LH[3]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes LH[6]
Bits	Destination
CELL.LH[6]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes LH[9]
Bits	Destination
CELL.LH[9]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_S_V switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[0]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[0]
	Source
DLL_E.OUT_DLL_CLKDV

virtex CLK_S_V switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[1]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[1]
	Source
DLL_E.OUT_DLL_CLKDV

virtex CLK_S_V switchbox GCLK_INT muxes IMUX_BUFGCE_CE[0]
Bits	Destination
CELL.IMUX_BUFGCE_CE[0]
	Source
CELL.HEX_H6[3]

virtex CLK_S_V switchbox GCLK_INT muxes IMUX_BUFGCE_CE[1]
Bits	Destination
CELL.IMUX_BUFGCE_CE[1]
	Source
CELL.HEX_H6[3]

Bel GCLK_IO[0]

virtex CLK_S_V bel GCLK_IO[0]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[0]

Bel GCLK_IO[1]

virtex CLK_S_V bel GCLK_IO[1]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[1]

Bel BUFG[0]

virtex CLK_S_V bel BUFG[0]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[0]
IN	input	CELL.IMUX_BUFGCE_CLK[0]
OUT	output	CELL.OUT_BUFGCE_O[0]

Bel BUFG[1]

virtex CLK_S_V bel BUFG[1]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[1]
IN	input	CELL.IMUX_BUFGCE_CLK[1]
OUT	output	CELL.OUT_BUFGCE_O[1]

Bel wires

virtex CLK_S_V bel wires
Wire	Pins
CELL.IMUX_BUFGCE_CLK[0]	BUFG[0].IN
CELL.IMUX_BUFGCE_CLK[1]	BUFG[1].IN
CELL.IMUX_BUFGCE_CE[0]	BUFG[0].CE
CELL.IMUX_BUFGCE_CE[1]	BUFG[1].CE
CELL.OUT_BUFGCE_O[0]	BUFG[0].OUT
CELL.OUT_BUFGCE_O[1]	BUFG[1].OUT
CELL.OUT_CLKPAD[0]	GCLK_IO[0].GCLKOUT
CELL.OUT_CLKPAD[1]	GCLK_IO[1].GCLKOUT

Bitstream

virtex CLK_S_V rect CLK[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

virtex CLK_S_V rect CLK[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

### Bitstream

virtex CLK_S_V rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	GCLK_INT:MUX.0.HEX_H1[0][1]	GCLK_INT:MUX.0.HEX_H1[0][0]	GCLK_INT:MUX.0.HEX_H1[0][2]	GCLK_INT:MUX.0.HEX_H1[0][3]	GCLK_INT:MUX.0.HEX_H1[0][4]	GCLK_INT:MUX.0.HEX_H1[0][6]	GCLK_INT:MUX.0.HEX_H1[0][5]	~GCLK_INT:DRIVE.0.HEX_H1[0]
B16	GCLK_INT:MUX.0.HEX_H1[1][1]	GCLK_INT:MUX.0.HEX_H1[1][0]	GCLK_INT:MUX.0.HEX_H1[1][2]	GCLK_INT:MUX.0.HEX_H1[1][3]	GCLK_INT:MUX.0.HEX_H1[1][4]	GCLK_INT:MUX.0.HEX_H1[1][6]	GCLK_INT:MUX.0.HEX_H1[1][5]	~GCLK_INT:DRIVE.0.HEX_H1[1]
B15	GCLK_INT:MUX.0.HEX_H1[2][1]	GCLK_INT:MUX.0.HEX_H1[2][0]	GCLK_INT:MUX.0.HEX_H1[2][2]	GCLK_INT:MUX.0.HEX_H1[2][3]	GCLK_INT:MUX.0.HEX_H1[2][4]	GCLK_INT:MUX.0.HEX_H1[2][6]	GCLK_INT:MUX.0.HEX_H1[2][5]	~GCLK_INT:DRIVE.0.HEX_H1[2]
B14	GCLK_INT:MUX.0.HEX_H1[3][1]	GCLK_INT:MUX.0.HEX_H1[3][0]	GCLK_INT:MUX.0.HEX_H1[3][2]	GCLK_INT:MUX.0.HEX_H1[3][3]	GCLK_INT:MUX.0.HEX_H1[3][4]	GCLK_INT:MUX.0.HEX_H1[3][6]	GCLK_INT:MUX.0.HEX_H1[3][5]	~GCLK_INT:DRIVE.0.HEX_H1[3]
B13	GCLK_INT:MUX.0.HEX_H6[0][1]	GCLK_INT:MUX.0.HEX_H6[0][0]	GCLK_INT:MUX.0.HEX_H6[0][2]	GCLK_INT:MUX.0.HEX_H6[0][3]	GCLK_INT:MUX.0.HEX_H6[0][4]	GCLK_INT:MUX.0.HEX_H6[0][6]	GCLK_INT:MUX.0.HEX_H6[0][5]	~GCLK_INT:DRIVE.0.HEX_H6[0]
B12	GCLK_INT:MUX.0.HEX_H6[1][1]	GCLK_INT:MUX.0.HEX_H6[1][0]	GCLK_INT:MUX.0.HEX_H6[1][2]	GCLK_INT:MUX.0.HEX_H6[1][3]	GCLK_INT:MUX.0.HEX_H6[1][4]	GCLK_INT:MUX.0.HEX_H6[1][6]	GCLK_INT:MUX.0.HEX_H6[1][5]	~GCLK_INT:DRIVE.0.HEX_H6[1]
B11	GCLK_INT:MUX.0.HEX_H6[2][1]	GCLK_INT:MUX.0.HEX_H6[2][0]	GCLK_INT:MUX.0.HEX_H6[2][2]	GCLK_INT:MUX.0.HEX_H6[2][3]	GCLK_INT:MUX.0.HEX_H6[2][4]	GCLK_INT:MUX.0.HEX_H6[2][6]	GCLK_INT:MUX.0.HEX_H6[2][5]	~GCLK_INT:DRIVE.0.HEX_H6[2]
B10	GCLK_INT:MUX.0.HEX_H6[3][1]	GCLK_INT:MUX.0.HEX_H6[3][0]	GCLK_INT:MUX.0.HEX_H6[3][2]	GCLK_INT:MUX.0.HEX_H6[3][3]	GCLK_INT:MUX.0.HEX_H6[3][4]	GCLK_INT:MUX.0.HEX_H6[3][6]	GCLK_INT:MUX.0.HEX_H6[3][5]	~GCLK_INT:DRIVE.0.HEX_H6[3]
B9	GCLK_INT:MUX.0.LH[9][0]	GCLK_INT:MUX.0.LH[9][4]	GCLK_INT:MUX.0.LH[9][3]	GCLK_INT:MUX.0.LH[9][2]	GCLK_INT:MUX.0.LH[9][1]	GCLK_INT:MUX.0.LH[9][6]	GCLK_INT:MUX.0.LH[9][5]	GCLK_INT:DRIVE.0.LH[9]
B8	GCLK_INT:MUX.0.LH[6][0]	GCLK_INT:MUX.0.LH[6][4]	GCLK_INT:MUX.0.LH[6][3]	GCLK_INT:MUX.0.LH[6][2]	GCLK_INT:MUX.0.LH[6][1]	GCLK_INT:MUX.0.LH[6][6]	GCLK_INT:MUX.0.LH[6][5]	GCLK_INT:DRIVE.0.LH[6]
B7	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][1]
B6	GCLK_IO[1]:DELAY[1]	GCLK_IO[1]:DELAY[2]	BUFG[0]:DISABLE_ATTR	BUFG[1]:DISABLE_ATTR	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][0]	GCLK_IO[1]:DELAY[4]	GCLK_IO[1]:DELAY[3]
B5	GCLK_INT:MUX.0.LH[0][0]	GCLK_INT:MUX.0.LH[0][4]	GCLK_INT:MUX.0.LH[0][3]	GCLK_INT:MUX.0.LH[0][2]	GCLK_INT:MUX.0.LH[0][1]	GCLK_INT:MUX.0.LH[0][6]	GCLK_INT:MUX.0.LH[0][5]	GCLK_INT:DRIVE.0.LH[0]
B4	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][6]	GCLK_INT:INV.IMUX_BUFGCE_CE[0]	GCLK_INT:INV.IMUX_BUFGCE_CE[1]
B3	GCLK_IO[0]:DELAY[0]	GCLK_IO[0]:DELAY[1]	GCLK_IO[0]:DELAY[2]	GCLK_IO[0]:DELAY[3]	GCLK_IO[0]:DELAY[4]	GCLK_IO[1]:DELAY[0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][1]
B2	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][2]
B1	GCLK_INT:MUX.0.LH[3][0]	GCLK_INT:MUX.0.LH[3][4]	GCLK_INT:MUX.0.LH[3][3]	GCLK_INT:MUX.0.LH[3][2]	GCLK_INT:MUX.0.LH[3][1]	GCLK_INT:MUX.0.LH[3][6]	GCLK_INT:MUX.0.LH[3][5]	GCLK_INT:DRIVE.0.LH[3]
B0	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][3]

virtex CLK_S_V rect R1
Bit	Frame
Bit	F0	F1
B2	GCLK_IO[1]:IBUF[0]	GCLK_IO[1]:IBUF[1]
B1	-	-
B0	GCLK_IO[0]:IBUF[0]	GCLK_IO[0]:IBUF[1]

BUFG[0]:DISABLE_ATTR	0.F2.B6
BUFG[1]:DISABLE_ATTR	0.F3.B6
GCLK_INT:DRIVE.0.LH[0]	0.F7.B5
GCLK_INT:DRIVE.0.LH[3]	0.F7.B1
GCLK_INT:DRIVE.0.LH[6]	0.F7.B8
GCLK_INT:DRIVE.0.LH[9]	0.F7.B9
GCLK_INT:INV.IMUX_BUFGCE_CE[0]	0.F6.B4
GCLK_INT:INV.IMUX_BUFGCE_CE[1]	0.F7.B4
non-inverted	[0]

GCLK_INT:DRIVE.0.HEX_H1[0]	0.F7.B17
GCLK_INT:DRIVE.0.HEX_H1[1]	0.F7.B16
GCLK_INT:DRIVE.0.HEX_H1[2]	0.F7.B15
GCLK_INT:DRIVE.0.HEX_H1[3]	0.F7.B14
GCLK_INT:DRIVE.0.HEX_H6[0]	0.F7.B13
GCLK_INT:DRIVE.0.HEX_H6[1]	0.F7.B12
GCLK_INT:DRIVE.0.HEX_H6[2]	0.F7.B11
GCLK_INT:DRIVE.0.HEX_H6[3]	0.F7.B10
inverted	~[0]

GCLK_INT:MUX.0.HEX_H1[0]	0.F5.B17	0.F6.B17	0.F4.B17	0.F3.B17	0.F2.B17	0.F0.B17	0.F1.B17
GCLK_INT:MUX.0.HEX_H1[1]	0.F5.B16	0.F6.B16	0.F4.B16	0.F3.B16	0.F2.B16	0.F0.B16	0.F1.B16
GCLK_INT:MUX.0.HEX_H1[2]	0.F5.B15	0.F6.B15	0.F4.B15	0.F3.B15	0.F2.B15	0.F0.B15	0.F1.B15
GCLK_INT:MUX.0.HEX_H1[3]	0.F5.B14	0.F6.B14	0.F4.B14	0.F3.B14	0.F2.B14	0.F0.B14	0.F1.B14
GCLK_INT:MUX.0.HEX_H6[0]	0.F5.B13	0.F6.B13	0.F4.B13	0.F3.B13	0.F2.B13	0.F0.B13	0.F1.B13
GCLK_INT:MUX.0.HEX_H6[1]	0.F5.B12	0.F6.B12	0.F4.B12	0.F3.B12	0.F2.B12	0.F0.B12	0.F1.B12
GCLK_INT:MUX.0.HEX_H6[2]	0.F5.B11	0.F6.B11	0.F4.B11	0.F3.B11	0.F2.B11	0.F0.B11	0.F1.B11
GCLK_INT:MUX.0.HEX_H6[3]	0.F5.B10	0.F6.B10	0.F4.B10	0.F3.B10	0.F2.B10	0.F0.B10	0.F1.B10
NONE	0	0	0	0	0	0	0
2.OUT_DLL_LOCKED	0	0	0	0	0	0	1
1.OUT_DLL_LOCKED	0	0	0	0	0	1	0
0.OUT_CLKPAD[1]	0	0	0	0	1	0	0
2.OUT_DLL_CLK0	0	0	0	1	0	0	0
2.OUT_DLL_CLKDV	0	0	1	0	0	0	0
0.OUT_BUFGCE_O[0]	0	1	0	0	0	0	1
1.OUT_DLL_CLK2X90	0	1	0	0	0	1	0
2.OUT_DLL_CLK180	0	1	0	0	1	0	0
2.OUT_DLL_CLK270	0	1	0	1	0	0	0
2.OUT_DLL_CLK2X	0	1	1	0	0	0	0
2.OUT_DLL_CLK2X90	1	0	0	0	0	0	1
0.OUT_BUFGCE_O[1]	1	0	0	0	0	1	0
1.OUT_DLL_CLK180	1	0	0	0	1	0	0
1.OUT_DLL_CLK0	1	0	0	1	0	0	0
2.OUT_DLL_CLK90	1	0	1	0	0	0	0
1.OUT_DLL_CLK270	1	1	0	0	0	0	1
1.OUT_DLL_CLK2X	1	1	0	0	0	1	0
0.OUT_CLKPAD[0]	1	1	0	0	1	0	0
1.OUT_DLL_CLK90	1	1	0	1	0	0	0
1.OUT_DLL_CLKDV	1	1	1	0	0	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0]	0.F5.B4	0.F3.B4	0.F2.B4	0.F1.B4	0.F0.B4	0.F7.B7	0.F6.B7
GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1]	0.F4.B4	0.F5.B7	0.F4.B7	0.F3.B7	0.F2.B7	0.F1.B7	0.F0.B7
NONE	0	0	0	0	0	0	0
0.HEX_H1[2]	0	0	0	0	0	0	1
0.HEX_H2[2]	0	0	0	0	0	1	0
0.HEX_H3[2]	0	0	0	0	1	0	0
0.HEX_H4[2]	0	0	0	1	0	0	0
0.HEX_H5[2]	0	0	1	0	0	0	0
0.HEX_H6[2]	0	1	0	0	0	0	0
0.HEX_H1[3]	1	0	0	0	0	0	1
0.HEX_H2[3]	1	0	0	0	0	1	0
0.HEX_H3[3]	1	0	0	0	1	0	0
0.HEX_H4[3]	1	0	0	1	0	0	0
0.HEX_H5[3]	1	0	1	0	0	0	0
0.HEX_H6[3]	1	1	0	0	0	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0]	0.F1.B2	0.F4.B2	0.F5.B2	0.F6.B2	0.F3.B2	0.F2.B2	0.F6.B0	0.F0.B2	0.F6.B3	0.F4.B6
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	1	0
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1
1.OUT_DLL_CLK270	0	0	0	0	0	0	1	1	1	0
1.OUT_DLL_CLKDV	0	0	0	0	0	1	0	0	1	0
0.HEX_H6[0]	0	0	0	0	0	1	0	0	1	1
1.OUT_DLL_CLK90	0	0	0	0	0	1	1	0	1	0
0.HEX_H1[1]	0	0	0	0	0	1	1	0	1	1
2.OUT_DLL_CLK2X	0	0	0	0	1	0	0	0	1	0
0.HEX_H2[0]	0	0	0	0	1	0	0	0	1	1
2.OUT_DLL_CLK180	0	0	0	0	1	0	1	0	1	0
0.HEX_H5[1]	0	0	0	0	1	0	1	0	1	1
1.OUT_DLL_CLK0	0	0	0	1	0	0	0	0	1	0
0.HEX_H3[0]	0	0	0	1	0	0	0	0	1	1
1.OUT_DLL_CLK2X	0	0	0	1	0	0	1	0	1	0
0.HEX_H2[1]	0	0	0	1	0	0	1	0	1	1
2.OUT_DLL_CLK0	0	0	1	0	0	0	0	0	1	0
0.HEX_H4[0]	0	0	1	0	0	0	0	0	1	1
1.OUT_DLL_CLK2X90	0	0	1	0	0	0	1	0	1	0
0.HEX_H3[1]	0	0	1	0	0	0	1	0	1	1
2.OUT_DLL_CLK90	0	1	0	0	0	0	0	0	1	0
0.HEX_H5[0]	0	1	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK2X90	0	1	0	0	0	0	1	0	1	0
0.HEX_H4[1]	0	1	0	0	0	0	1	0	1	1
2.OUT_DLL_CLKDV	1	0	0	0	0	0	0	0	1	0
1.OUT_DLL_CLK180	1	0	0	0	0	0	1	0	1	0
0.HEX_H6[1]	1	0	0	0	0	0	1	0	1	1

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1]	0.F0.B0	0.F3.B0	0.F4.B0	0.F5.B0	0.F2.B0	0.F1.B0	0.F7.B0	0.F7.B2	0.F7.B3	0.F5.B6
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	1	0
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1
1.OUT_DLL_CLK270	0	0	0	0	0	0	1	1	1	0
1.OUT_DLL_CLKDV	0	0	0	0	0	1	0	0	1	0
0.HEX_H6[0]	0	0	0	0	0	1	0	0	1	1
1.OUT_DLL_CLK90	0	0	0	0	0	1	1	0	1	0
0.HEX_H1[1]	0	0	0	0	0	1	1	0	1	1
2.OUT_DLL_CLK2X	0	0	0	0	1	0	0	0	1	0
0.HEX_H2[0]	0	0	0	0	1	0	0	0	1	1
2.OUT_DLL_CLK180	0	0	0	0	1	0	1	0	1	0
0.HEX_H5[1]	0	0	0	0	1	0	1	0	1	1
1.OUT_DLL_CLK0	0	0	0	1	0	0	0	0	1	0
0.HEX_H3[0]	0	0	0	1	0	0	0	0	1	1
1.OUT_DLL_CLK2X	0	0	0	1	0	0	1	0	1	0
0.HEX_H2[1]	0	0	0	1	0	0	1	0	1	1
2.OUT_DLL_CLK0	0	0	1	0	0	0	0	0	1	0
0.HEX_H4[0]	0	0	1	0	0	0	0	0	1	1
1.OUT_DLL_CLK2X90	0	0	1	0	0	0	1	0	1	0
0.HEX_H3[1]	0	0	1	0	0	0	1	0	1	1
2.OUT_DLL_CLK90	0	1	0	0	0	0	0	0	1	0
0.HEX_H5[0]	0	1	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK2X90	0	1	0	0	0	0	1	0	1	0
0.HEX_H4[1]	0	1	0	0	0	0	1	0	1	1
2.OUT_DLL_CLKDV	1	0	0	0	0	0	0	0	1	0
1.OUT_DLL_CLK180	1	0	0	0	0	0	1	0	1	0
0.HEX_H6[1]	1	0	0	0	0	0	1	0	1	1

GCLK_INT:MUX.0.LH[0]	0.F5.B5	0.F6.B5	0.F1.B5	0.F2.B5	0.F3.B5	0.F4.B5	0.F0.B5
GCLK_INT:MUX.0.LH[3]	0.F5.B1	0.F6.B1	0.F1.B1	0.F2.B1	0.F3.B1	0.F4.B1	0.F0.B1
GCLK_INT:MUX.0.LH[6]	0.F5.B8	0.F6.B8	0.F1.B8	0.F2.B8	0.F3.B8	0.F4.B8	0.F0.B8
GCLK_INT:MUX.0.LH[9]	0.F5.B9	0.F6.B9	0.F1.B9	0.F2.B9	0.F3.B9	0.F4.B9	0.F0.B9
NONE	0	0	0	0	0	0	0
0.OUT_BUFGCE_O[0]	0	0	0	0	0	0	1
0.OUT_BUFGCE_O[1]	0	0	0	0	0	1	0
0.OUT_CLKPAD[1]	0	0	0	0	1	0	0
1.OUT_DLL_CLK2X	0	0	0	1	0	0	0
2.OUT_DLL_CLK2X90	0	0	1	0	0	0	0
1.OUT_DLL_CLK180	0	1	0	0	0	0	1
0.OUT_CLKPAD[0]	0	1	0	0	0	1	0
2.OUT_DLL_CLK90	0	1	0	0	1	0	0
2.OUT_DLL_LOCKED	0	1	0	1	0	0	0
1.OUT_DLL_CLK270	0	1	1	0	0	0	0
1.OUT_DLL_LOCKED	1	0	0	0	0	0	1
2.OUT_DLL_CLK180	1	0	0	0	0	1	0
1.OUT_DLL_CLK2X90	1	0	0	0	1	0	0
1.OUT_DLL_CLK0	1	0	0	1	0	0	0
1.OUT_DLL_CLK90	1	0	1	0	0	0	0
2.OUT_DLL_CLKDV	1	1	0	0	0	0	1
2.OUT_DLL_CLK0	1	1	0	0	0	1	0
2.OUT_DLL_CLK2X	1	1	0	0	1	0	0
1.OUT_DLL_CLKDV	1	1	0	1	0	0	0
2.OUT_DLL_CLK270	1	1	1	0	0	0	0

GCLK_IO[0]:DELAY	0.F4.B3	0.F3.B3	0.F2.B3	0.F1.B3	0.F0.B3
GCLK_IO[1]:DELAY	0.F6.B6	0.F7.B6	0.F1.B6	0.F0.B6	0.F5.B3
non-inverted	[4]	[3]	[2]	[1]	[0]

GCLK_IO[0]:IBUF	1.F1.B0	1.F0.B0
GCLK_IO[1]:IBUF	1.F1.B2	1.F0.B2
CMOS	0	0
VREF_LV	0	1
VREF_HV	1	0
NONE	1	1

Tile CLK_S_VE_4DLL

Cells: 5

Switchbox GCLK_INT

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes HEX_H1[0]
Bits	Destination
CELL.HEX_H1[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes HEX_H1[1]
Bits	Destination
CELL.HEX_H1[1]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes HEX_H1[2]
Bits	Destination
CELL.HEX_H1[2]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes HEX_H1[3]
Bits	Destination
CELL.HEX_H1[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes HEX_H6[0]
Bits	Destination
CELL.HEX_H6[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes HEX_H6[1]
Bits	Destination
CELL.HEX_H6[1]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes HEX_H6[2]
Bits	Destination
CELL.HEX_H6[2]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes HEX_H6[3]
Bits	Destination
CELL.HEX_H6[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes LH[0]
Bits	Destination
CELL.LH[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes LH[3]
Bits	Destination
CELL.LH[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes LH[6]
Bits	Destination
CELL.LH[6]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes LH[9]
Bits	Destination
CELL.LH[9]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[0]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[0]
	Source
DLLS_E.OUT_DLL_CLKDV

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[1]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[1]
	Source
DLLS_E.OUT_DLL_CLKDV

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CE[0]
Bits	Destination
CELL.IMUX_BUFGCE_CE[0]
	Source
CELL.HEX_H6[3]

virtex CLK_S_VE_4DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CE[1]
Bits	Destination
CELL.IMUX_BUFGCE_CE[1]
	Source
CELL.HEX_H6[3]

Bel GCLK_IO[0]

virtex CLK_S_VE_4DLL bel GCLK_IO[0]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[0]

Bel GCLK_IO[1]

virtex CLK_S_VE_4DLL bel GCLK_IO[1]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[1]

Bel BUFG[0]

virtex CLK_S_VE_4DLL bel BUFG[0]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[0]
IN	input	CELL.IMUX_BUFGCE_CLK[0]
OUT	output	CELL.OUT_BUFGCE_O[0]

Bel BUFG[1]

virtex CLK_S_VE_4DLL bel BUFG[1]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[1]
IN	input	CELL.IMUX_BUFGCE_CLK[1]
OUT	output	CELL.OUT_BUFGCE_O[1]

Bel IOFB[0]

virtex CLK_S_VE_4DLL bel IOFB[0]
Pin	Direction	Wires
O	output	CELL.OUT_IOFB[0]

Bel IOFB[1]

virtex CLK_S_VE_4DLL bel IOFB[1]
Pin	Direction	Wires
O	output	CELL.OUT_IOFB[1]

Bel wires

virtex CLK_S_VE_4DLL bel wires
Wire	Pins
CELL.IMUX_BUFGCE_CLK[0]	BUFG[0].IN
CELL.IMUX_BUFGCE_CLK[1]	BUFG[1].IN
CELL.IMUX_BUFGCE_CE[0]	BUFG[0].CE
CELL.IMUX_BUFGCE_CE[1]	BUFG[1].CE
CELL.OUT_BUFGCE_O[0]	BUFG[0].OUT
CELL.OUT_BUFGCE_O[1]	BUFG[1].OUT
CELL.OUT_CLKPAD[0]	GCLK_IO[0].GCLKOUT
CELL.OUT_CLKPAD[1]	GCLK_IO[1].GCLKOUT
CELL.OUT_IOFB[0]	IOFB[0].O
CELL.OUT_IOFB[1]	IOFB[1].O

Bitstream

virtex CLK_S_VE_4DLL rect CLK[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

virtex CLK_S_VE_4DLL rect CLK[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

### Bitstream

virtex CLK_S_VE_4DLL rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	GCLK_INT:MUX.0.HEX_H1[0][2]	GCLK_INT:MUX.0.HEX_H1[0][3]	GCLK_INT:MUX.0.HEX_H1[0][1]	GCLK_INT:MUX.0.HEX_H1[0][0]	GCLK_INT:MUX.0.HEX_H1[0][5]	GCLK_INT:MUX.0.HEX_H1[0][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[0]
B16	GCLK_INT:MUX.0.HEX_H1[1][2]	GCLK_INT:MUX.0.HEX_H1[1][3]	GCLK_INT:MUX.0.HEX_H1[1][1]	GCLK_INT:MUX.0.HEX_H1[1][0]	GCLK_INT:MUX.0.HEX_H1[1][5]	GCLK_INT:MUX.0.HEX_H1[1][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[1]
B15	GCLK_INT:MUX.0.HEX_H1[2][2]	GCLK_INT:MUX.0.HEX_H1[2][3]	GCLK_INT:MUX.0.HEX_H1[2][1]	GCLK_INT:MUX.0.HEX_H1[2][0]	GCLK_INT:MUX.0.HEX_H1[2][5]	GCLK_INT:MUX.0.HEX_H1[2][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[2]
B14	GCLK_INT:MUX.0.HEX_H1[3][2]	GCLK_INT:MUX.0.HEX_H1[3][3]	GCLK_INT:MUX.0.HEX_H1[3][1]	GCLK_INT:MUX.0.HEX_H1[3][0]	GCLK_INT:MUX.0.HEX_H1[3][5]	GCLK_INT:MUX.0.HEX_H1[3][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[3]
B13	GCLK_INT:MUX.0.HEX_H6[0][2]	GCLK_INT:MUX.0.HEX_H6[0][3]	GCLK_INT:MUX.0.HEX_H6[0][1]	GCLK_INT:MUX.0.HEX_H6[0][0]	GCLK_INT:MUX.0.HEX_H6[0][5]	GCLK_INT:MUX.0.HEX_H6[0][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[0]
B12	GCLK_INT:MUX.0.HEX_H6[1][2]	GCLK_INT:MUX.0.HEX_H6[1][3]	GCLK_INT:MUX.0.HEX_H6[1][1]	GCLK_INT:MUX.0.HEX_H6[1][0]	GCLK_INT:MUX.0.HEX_H6[1][5]	GCLK_INT:MUX.0.HEX_H6[1][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[1]
B11	GCLK_INT:MUX.0.HEX_H6[2][2]	GCLK_INT:MUX.0.HEX_H6[2][3]	GCLK_INT:MUX.0.HEX_H6[2][1]	GCLK_INT:MUX.0.HEX_H6[2][0]	GCLK_INT:MUX.0.HEX_H6[2][5]	GCLK_INT:MUX.0.HEX_H6[2][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[2]
B10	GCLK_INT:MUX.0.HEX_H6[3][2]	GCLK_INT:MUX.0.HEX_H6[3][3]	GCLK_INT:MUX.0.HEX_H6[3][1]	GCLK_INT:MUX.0.HEX_H6[3][0]	GCLK_INT:MUX.0.HEX_H6[3][5]	GCLK_INT:MUX.0.HEX_H6[3][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[3]
B9	GCLK_INT:MUX.0.LH[9][2]	GCLK_INT:MUX.0.LH[9][3]	GCLK_INT:MUX.0.LH[9][1]	GCLK_INT:MUX.0.LH[9][0]	GCLK_INT:MUX.0.LH[9][5]	GCLK_INT:MUX.0.LH[9][4]	-	GCLK_INT:DRIVE.0.LH[9]
B8	GCLK_INT:MUX.0.LH[6][2]	GCLK_INT:MUX.0.LH[6][3]	GCLK_INT:MUX.0.LH[6][1]	GCLK_INT:MUX.0.LH[6][0]	GCLK_INT:MUX.0.LH[6][5]	GCLK_INT:MUX.0.LH[6][4]	-	GCLK_INT:DRIVE.0.LH[6]
B7	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][1]
B6	GCLK_IO[1]:DELAY[1]	GCLK_IO[1]:DELAY[2]	BUFG[0]:DISABLE_ATTR	BUFG[1]:DISABLE_ATTR	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][0]	GCLK_IO[1]:DELAY[4]	GCLK_IO[1]:DELAY[3]
B5	GCLK_INT:MUX.0.LH[0][2]	GCLK_INT:MUX.0.LH[0][3]	GCLK_INT:MUX.0.LH[0][1]	GCLK_INT:MUX.0.LH[0][0]	GCLK_INT:MUX.0.LH[0][5]	GCLK_INT:MUX.0.LH[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][2]	GCLK_INT:DRIVE.0.LH[0]
B4	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][6]	GCLK_INT:INV.IMUX_BUFGCE_CE[0]	GCLK_INT:INV.IMUX_BUFGCE_CE[1]
B3	GCLK_IO[0]:DELAY[0]	GCLK_IO[0]:DELAY[1]	GCLK_IO[0]:DELAY[2]	GCLK_IO[0]:DELAY[3]	GCLK_IO[0]:DELAY[4]	GCLK_IO[1]:DELAY[0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][1]
B2	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][3]
B1	GCLK_INT:MUX.0.LH[3][2]	GCLK_INT:MUX.0.LH[3][3]	GCLK_INT:MUX.0.LH[3][1]	GCLK_INT:MUX.0.LH[3][0]	GCLK_INT:MUX.0.LH[3][5]	GCLK_INT:MUX.0.LH[3][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][10]	GCLK_INT:DRIVE.0.LH[3]
B0	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][10]

virtex CLK_S_VE_4DLL rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B2	GCLK_IO[1]:IBUF[0]	GCLK_IO[1]:IBUF[1]	IOFB[1]:IBUF[1]	IOFB[1]:IBUF[0]
B1	-	-	-	-
B0	GCLK_IO[0]:IBUF[0]	GCLK_IO[0]:IBUF[1]	IOFB[0]:IBUF[1]	IOFB[0]:IBUF[0]

BUFG[0]:DISABLE_ATTR	0.F2.B6
BUFG[1]:DISABLE_ATTR	0.F3.B6
GCLK_INT:DRIVE.0.LH[0]	0.F7.B5
GCLK_INT:DRIVE.0.LH[3]	0.F7.B1
GCLK_INT:DRIVE.0.LH[6]	0.F7.B8
GCLK_INT:DRIVE.0.LH[9]	0.F7.B9
GCLK_INT:INV.IMUX_BUFGCE_CE[0]	0.F6.B4
GCLK_INT:INV.IMUX_BUFGCE_CE[1]	0.F7.B4
non-inverted	[0]

GCLK_INT:DRIVE.0.HEX_H1[0]	0.F7.B17
GCLK_INT:DRIVE.0.HEX_H1[1]	0.F7.B16
GCLK_INT:DRIVE.0.HEX_H1[2]	0.F7.B15
GCLK_INT:DRIVE.0.HEX_H1[3]	0.F7.B14
GCLK_INT:DRIVE.0.HEX_H6[0]	0.F7.B13
GCLK_INT:DRIVE.0.HEX_H6[1]	0.F7.B12
GCLK_INT:DRIVE.0.HEX_H6[2]	0.F7.B11
GCLK_INT:DRIVE.0.HEX_H6[3]	0.F7.B10
inverted	~[0]

GCLK_INT:MUX.0.HEX_H1[0]	0.F4.B17	0.F5.B17	0.F1.B17	0.F0.B17	0.F2.B17	0.F3.B17
GCLK_INT:MUX.0.HEX_H1[1]	0.F4.B16	0.F5.B16	0.F1.B16	0.F0.B16	0.F2.B16	0.F3.B16
GCLK_INT:MUX.0.HEX_H1[2]	0.F4.B15	0.F5.B15	0.F1.B15	0.F0.B15	0.F2.B15	0.F3.B15
GCLK_INT:MUX.0.HEX_H1[3]	0.F4.B14	0.F5.B14	0.F1.B14	0.F0.B14	0.F2.B14	0.F3.B14
GCLK_INT:MUX.0.HEX_H6[0]	0.F4.B13	0.F5.B13	0.F1.B13	0.F0.B13	0.F2.B13	0.F3.B13
GCLK_INT:MUX.0.HEX_H6[1]	0.F4.B12	0.F5.B12	0.F1.B12	0.F0.B12	0.F2.B12	0.F3.B12
GCLK_INT:MUX.0.HEX_H6[2]	0.F4.B11	0.F5.B11	0.F1.B11	0.F0.B11	0.F2.B11	0.F3.B11
GCLK_INT:MUX.0.HEX_H6[3]	0.F4.B10	0.F5.B10	0.F1.B10	0.F0.B10	0.F2.B10	0.F3.B10
GCLK_INT:MUX.0.LH[0]	0.F4.B5	0.F5.B5	0.F1.B5	0.F0.B5	0.F2.B5	0.F3.B5
GCLK_INT:MUX.0.LH[3]	0.F4.B1	0.F5.B1	0.F1.B1	0.F0.B1	0.F2.B1	0.F3.B1
GCLK_INT:MUX.0.LH[6]	0.F4.B8	0.F5.B8	0.F1.B8	0.F0.B8	0.F2.B8	0.F3.B8
GCLK_INT:MUX.0.LH[9]	0.F4.B9	0.F5.B9	0.F1.B9	0.F0.B9	0.F2.B9	0.F3.B9
0.OUT_CLKPAD[0]	0	0	0	0	1	1
1.OUT_DLL_CLK2X90	0	0	0	1	0	1
0.OUT_BUFGCE_O[0]	0	0	0	1	1	1
1.OUT_DLL_CLK90	0	0	1	0	0	1
1.OUT_DLL_CLKDV	0	0	1	0	1	1
2.OUT_DLL_CLK180	0	0	1	1	0	1
3.OUT_DLL_CLK2X	0	1	0	0	1	0
2.OUT_DLL_CLK270	0	1	0	0	1	1
3.OUT_DLL_CLKDV	0	1	0	1	0	0
2.OUT_DLL_CLK2X90	0	1	0	1	0	1
4.OUT_DLL_CLK180	0	1	0	1	1	0
1.OUT_DLL_CLK180	0	1	0	1	1	1
3.OUT_DLL_CLK270	0	1	1	0	0	0
2.OUT_DLL_CLK2X	0	1	1	0	0	1
3.OUT_DLL_CLK90	0	1	1	0	1	0
0.OUT_BUFGCE_O[1]	0	1	1	0	1	1
4.OUT_DLL_CLK270	0	1	1	1	0	0
1.OUT_DLL_CLK0	0	1	1	1	0	1
4.OUT_DLL_CLK2X	1	0	0	0	1	0
2.OUT_DLL_CLK90	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	1	0	0
0.OUT_CLKPAD[1]	1	0	0	1	0	1
3.OUT_DLL_CLK180	1	0	0	1	1	0
2.OUT_DLL_CLK0	1	0	0	1	1	1
4.OUT_DLL_CLK90	1	0	1	0	0	0
1.OUT_DLL_LOCKED	1	0	1	0	0	1
4.OUT_DLL_CLK2X90	1	0	1	0	1	0
2.OUT_DLL_LOCKED	1	0	1	0	1	1
3.OUT_DLL_CLK0	1	0	1	1	0	0
2.OUT_DLL_CLKDV	1	0	1	1	0	1
4.OUT_DLL_LOCKED	1	1	0	0	1	0
4.OUT_DLL_CLKDV	1	1	0	1	0	0
1.OUT_DLL_CLK2X	1	1	0	1	1	0
3.OUT_DLL_LOCKED	1	1	1	0	0	0
4.OUT_DLL_CLK0	1	1	1	0	1	0
1.OUT_DLL_CLK270	1	1	1	1	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0]	0.F5.B4	0.F3.B4	0.F2.B4	0.F1.B4	0.F0.B4	0.F7.B7	0.F6.B7
GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1]	0.F4.B4	0.F5.B7	0.F4.B7	0.F3.B7	0.F2.B7	0.F1.B7	0.F0.B7
NONE	0	0	0	0	0	0	0
0.HEX_H1[2]	0	0	0	0	0	0	1
0.HEX_H2[2]	0	0	0	0	0	1	0
0.HEX_H3[2]	0	0	0	0	1	0	0
0.HEX_H4[2]	0	0	0	1	0	0	0
0.HEX_H5[2]	0	0	1	0	0	0	0
0.HEX_H6[2]	0	1	0	0	0	0	0
0.HEX_H1[3]	1	0	0	0	0	0	1
0.HEX_H2[3]	1	0	0	0	0	1	0
0.HEX_H3[3]	1	0	0	0	1	0	0
0.HEX_H4[3]	1	0	0	1	0	0	0
0.HEX_H5[3]	1	0	1	0	0	0	0
0.HEX_H6[3]	1	1	0	0	0	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0]	0.F7.B0	0.F1.B2	0.F4.B2	0.F5.B2	0.F6.B2	0.F3.B2	0.F2.B2	0.F0.B2	0.F6.B0	0.F6.B3	0.F4.B6
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	0	1	1
1.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	0	1	0
2.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	1	1	0
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1	1
1.OUT_DLL_CLK90	0	0	0	0	0	0	1	0	0	1	0
0.HEX_H1[1]	0	0	0	0	0	0	1	0	0	1	1
1.OUT_DLL_CLKDV	0	0	0	0	0	0	1	0	1	1	0
0.HEX_H6[0]	0	0	0	0	0	0	1	0	1	1	1
2.OUT_DLL_CLK180	0	0	0	0	0	1	0	0	0	1	0
0.HEX_H5[1]	0	0	0	0	0	1	0	0	0	1	1
2.OUT_DLL_CLK2X	0	0	0	0	0	1	0	0	1	1	0
0.HEX_H2[0]	0	0	0	0	0	1	0	0	1	1	1
1.OUT_DLL_CLK2X	0	0	0	0	1	0	0	0	0	1	0
0.HEX_H2[1]	0	0	0	0	1	0	0	0	0	1	1
1.OUT_DLL_CLK0	0	0	0	0	1	0	0	0	1	1	0
0.HEX_H3[0]	0	0	0	0	1	0	0	0	1	1	1
1.OUT_DLL_CLK2X90	0	0	0	1	0	0	0	0	0	1	0
0.HEX_H3[1]	0	0	0	1	0	0	0	0	0	1	1
2.OUT_DLL_CLK0	0	0	0	1	0	0	0	0	1	1	0
0.HEX_H4[0]	0	0	0	1	0	0	0	0	1	1	1
2.OUT_DLL_CLK2X90	0	0	1	0	0	0	0	0	0	1	0
0.HEX_H4[1]	0	0	1	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK90	0	0	1	0	0	0	0	0	1	1	0
0.HEX_H5[0]	0	0	1	0	0	0	0	0	1	1	1
1.OUT_DLL_CLK180	0	1	0	0	0	0	0	0	0	1	0
0.HEX_H6[1]	0	1	0	0	0	0	0	0	0	1	1
2.OUT_DLL_CLKDV	0	1	0	0	0	0	0	0	1	1	0
3.OUT_DLL_CLK270	1	0	0	0	0	0	0	1	0	1	0
4.OUT_DLL_CLK180	1	0	0	0	0	0	0	1	0	1	1
3.OUT_DLL_CLK90	1	0	0	0	0	0	1	0	0	1	0
4.OUT_DLL_CLKDV	1	0	0	0	0	0	1	0	0	1	1
3.OUT_DLL_CLKDV	1	0	0	0	0	1	0	0	0	1	0
4.OUT_DLL_CLK2X90	1	0	0	0	0	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	0	1	0	0	0	0	1	0
4.OUT_DLL_CLK0	1	0	0	0	1	0	0	0	0	1	1
3.OUT_DLL_CLK0	1	0	0	1	0	0	0	0	0	1	0
4.OUT_DLL_CLK90	1	0	0	1	0	0	0	0	0	1	1
3.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK180	1	1	0	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK270	1	1	0	0	0	0	0	0	0	1	1

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1]	0.F6.B1	0.F0.B0	0.F3.B0	0.F4.B0	0.F5.B0	0.F2.B0	0.F1.B0	0.F7.B2	0.F6.B5	0.F7.B3	0.F5.B6
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	0	1	1
1.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	0	1	0
2.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	1	1	0
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1	1
1.OUT_DLL_CLK90	0	0	0	0	0	0	1	0	0	1	0
0.HEX_H1[1]	0	0	0	0	0	0	1	0	0	1	1
1.OUT_DLL_CLKDV	0	0	0	0	0	0	1	0	1	1	0
0.HEX_H6[0]	0	0	0	0	0	0	1	0	1	1	1
2.OUT_DLL_CLK180	0	0	0	0	0	1	0	0	0	1	0
0.HEX_H5[1]	0	0	0	0	0	1	0	0	0	1	1
2.OUT_DLL_CLK2X	0	0	0	0	0	1	0	0	1	1	0
0.HEX_H2[0]	0	0	0	0	0	1	0	0	1	1	1
1.OUT_DLL_CLK2X	0	0	0	0	1	0	0	0	0	1	0
0.HEX_H2[1]	0	0	0	0	1	0	0	0	0	1	1
1.OUT_DLL_CLK0	0	0	0	0	1	0	0	0	1	1	0
0.HEX_H3[0]	0	0	0	0	1	0	0	0	1	1	1
1.OUT_DLL_CLK2X90	0	0	0	1	0	0	0	0	0	1	0
0.HEX_H3[1]	0	0	0	1	0	0	0	0	0	1	1
2.OUT_DLL_CLK0	0	0	0	1	0	0	0	0	1	1	0
0.HEX_H4[0]	0	0	0	1	0	0	0	0	1	1	1
2.OUT_DLL_CLK2X90	0	0	1	0	0	0	0	0	0	1	0
0.HEX_H4[1]	0	0	1	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK90	0	0	1	0	0	0	0	0	1	1	0
0.HEX_H5[0]	0	0	1	0	0	0	0	0	1	1	1
1.OUT_DLL_CLK180	0	1	0	0	0	0	0	0	0	1	0
0.HEX_H6[1]	0	1	0	0	0	0	0	0	0	1	1
2.OUT_DLL_CLKDV	0	1	0	0	0	0	0	0	1	1	0
3.OUT_DLL_CLK270	1	0	0	0	0	0	0	1	0	1	0
4.OUT_DLL_CLK180	1	0	0	0	0	0	0	1	0	1	1
3.OUT_DLL_CLK90	1	0	0	0	0	0	1	0	0	1	0
4.OUT_DLL_CLKDV	1	0	0	0	0	0	1	0	0	1	1
3.OUT_DLL_CLKDV	1	0	0	0	0	1	0	0	0	1	0
4.OUT_DLL_CLK2X90	1	0	0	0	0	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	0	1	0	0	0	0	1	0
4.OUT_DLL_CLK0	1	0	0	0	1	0	0	0	0	1	1
3.OUT_DLL_CLK0	1	0	0	1	0	0	0	0	0	1	0
4.OUT_DLL_CLK90	1	0	0	1	0	0	0	0	0	1	1
3.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK180	1	1	0	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK270	1	1	0	0	0	0	0	0	0	1	1

GCLK_IO[0]:DELAY	0.F4.B3	0.F3.B3	0.F2.B3	0.F1.B3	0.F0.B3
GCLK_IO[1]:DELAY	0.F6.B6	0.F7.B6	0.F1.B6	0.F0.B6	0.F5.B3
non-inverted	[4]	[3]	[2]	[1]	[0]

GCLK_IO[0]:IBUF	1.F1.B0	1.F0.B0
GCLK_IO[1]:IBUF	1.F1.B2	1.F0.B2
CMOS	0	0
VREF	0	1
DIFF	1	0
NONE	1	1

IOFB[0]:IBUF	1.F2.B0	1.F3.B0
IOFB[1]:IBUF	1.F2.B2	1.F3.B2
CMOS	0	1
VREF	1	0
NONE	1	1

Tile CLK_S_VE_2DLL

Cells: 5

Switchbox GCLK_INT

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes HEX_H1[0]
Bits	Destination
CELL.HEX_H1[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes HEX_H1[1]
Bits	Destination
CELL.HEX_H1[1]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes HEX_H1[2]
Bits	Destination
CELL.HEX_H1[2]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes HEX_H1[3]
Bits	Destination
CELL.HEX_H1[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes HEX_H6[0]
Bits	Destination
CELL.HEX_H6[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes HEX_H6[1]
Bits	Destination
CELL.HEX_H6[1]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes HEX_H6[2]
Bits	Destination
CELL.HEX_H6[2]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes HEX_H6[3]
Bits	Destination
CELL.HEX_H6[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes LH[0]
Bits	Destination
CELL.LH[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes LH[3]
Bits	Destination
CELL.LH[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes LH[6]
Bits	Destination
CELL.LH[6]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes LH[9]
Bits	Destination
CELL.LH[9]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[0]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[0]
	Source
DLLS_E.OUT_DLL_CLKDV

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[1]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[1]
	Source
DLLS_E.OUT_DLL_CLKDV

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CE[0]
Bits	Destination
CELL.IMUX_BUFGCE_CE[0]
	Source
CELL.HEX_H6[3]

virtex CLK_S_VE_2DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CE[1]
Bits	Destination
CELL.IMUX_BUFGCE_CE[1]
	Source
CELL.HEX_H6[3]

Bel GCLK_IO[0]

virtex CLK_S_VE_2DLL bel GCLK_IO[0]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[0]

Bel GCLK_IO[1]

virtex CLK_S_VE_2DLL bel GCLK_IO[1]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[1]

Bel BUFG[0]

virtex CLK_S_VE_2DLL bel BUFG[0]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[0]
IN	input	CELL.IMUX_BUFGCE_CLK[0]
OUT	output	CELL.OUT_BUFGCE_O[0]

Bel BUFG[1]

virtex CLK_S_VE_2DLL bel BUFG[1]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[1]
IN	input	CELL.IMUX_BUFGCE_CLK[1]
OUT	output	CELL.OUT_BUFGCE_O[1]

Bel IOFB[0]

virtex CLK_S_VE_2DLL bel IOFB[0]
Pin	Direction	Wires
O	output	CELL.OUT_IOFB[0]

Bel IOFB[1]

virtex CLK_S_VE_2DLL bel IOFB[1]
Pin	Direction	Wires
O	output	CELL.OUT_IOFB[1]

Bel wires

virtex CLK_S_VE_2DLL bel wires
Wire	Pins
CELL.IMUX_BUFGCE_CLK[0]	BUFG[0].IN
CELL.IMUX_BUFGCE_CLK[1]	BUFG[1].IN
CELL.IMUX_BUFGCE_CE[0]	BUFG[0].CE
CELL.IMUX_BUFGCE_CE[1]	BUFG[1].CE
CELL.OUT_BUFGCE_O[0]	BUFG[0].OUT
CELL.OUT_BUFGCE_O[1]	BUFG[1].OUT
CELL.OUT_CLKPAD[0]	GCLK_IO[0].GCLKOUT
CELL.OUT_CLKPAD[1]	GCLK_IO[1].GCLKOUT
CELL.OUT_IOFB[0]	IOFB[0].O
CELL.OUT_IOFB[1]	IOFB[1].O

Bitstream

virtex CLK_S_VE_2DLL rect CLK[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

virtex CLK_S_VE_2DLL rect CLK[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

### Bitstream

virtex CLK_S_VE_2DLL rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	GCLK_INT:MUX.0.HEX_H1[0][2]	GCLK_INT:MUX.0.HEX_H1[0][3]	GCLK_INT:MUX.0.HEX_H1[0][1]	GCLK_INT:MUX.0.HEX_H1[0][0]	GCLK_INT:MUX.0.HEX_H1[0][5]	GCLK_INT:MUX.0.HEX_H1[0][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[0]
B16	GCLK_INT:MUX.0.HEX_H1[1][2]	GCLK_INT:MUX.0.HEX_H1[1][3]	GCLK_INT:MUX.0.HEX_H1[1][1]	GCLK_INT:MUX.0.HEX_H1[1][0]	GCLK_INT:MUX.0.HEX_H1[1][5]	GCLK_INT:MUX.0.HEX_H1[1][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[1]
B15	GCLK_INT:MUX.0.HEX_H1[2][2]	GCLK_INT:MUX.0.HEX_H1[2][3]	GCLK_INT:MUX.0.HEX_H1[2][1]	GCLK_INT:MUX.0.HEX_H1[2][0]	GCLK_INT:MUX.0.HEX_H1[2][5]	GCLK_INT:MUX.0.HEX_H1[2][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[2]
B14	GCLK_INT:MUX.0.HEX_H1[3][2]	GCLK_INT:MUX.0.HEX_H1[3][3]	GCLK_INT:MUX.0.HEX_H1[3][1]	GCLK_INT:MUX.0.HEX_H1[3][0]	GCLK_INT:MUX.0.HEX_H1[3][5]	GCLK_INT:MUX.0.HEX_H1[3][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[3]
B13	GCLK_INT:MUX.0.HEX_H6[0][2]	GCLK_INT:MUX.0.HEX_H6[0][3]	GCLK_INT:MUX.0.HEX_H6[0][1]	GCLK_INT:MUX.0.HEX_H6[0][0]	GCLK_INT:MUX.0.HEX_H6[0][5]	GCLK_INT:MUX.0.HEX_H6[0][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[0]
B12	GCLK_INT:MUX.0.HEX_H6[1][2]	GCLK_INT:MUX.0.HEX_H6[1][3]	GCLK_INT:MUX.0.HEX_H6[1][1]	GCLK_INT:MUX.0.HEX_H6[1][0]	GCLK_INT:MUX.0.HEX_H6[1][5]	GCLK_INT:MUX.0.HEX_H6[1][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[1]
B11	GCLK_INT:MUX.0.HEX_H6[2][2]	GCLK_INT:MUX.0.HEX_H6[2][3]	GCLK_INT:MUX.0.HEX_H6[2][1]	GCLK_INT:MUX.0.HEX_H6[2][0]	GCLK_INT:MUX.0.HEX_H6[2][5]	GCLK_INT:MUX.0.HEX_H6[2][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[2]
B10	GCLK_INT:MUX.0.HEX_H6[3][2]	GCLK_INT:MUX.0.HEX_H6[3][3]	GCLK_INT:MUX.0.HEX_H6[3][1]	GCLK_INT:MUX.0.HEX_H6[3][0]	GCLK_INT:MUX.0.HEX_H6[3][5]	GCLK_INT:MUX.0.HEX_H6[3][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[3]
B9	GCLK_INT:MUX.0.LH[9][2]	GCLK_INT:MUX.0.LH[9][3]	GCLK_INT:MUX.0.LH[9][1]	GCLK_INT:MUX.0.LH[9][0]	GCLK_INT:MUX.0.LH[9][5]	GCLK_INT:MUX.0.LH[9][4]	-	GCLK_INT:DRIVE.0.LH[9]
B8	GCLK_INT:MUX.0.LH[6][2]	GCLK_INT:MUX.0.LH[6][3]	GCLK_INT:MUX.0.LH[6][1]	GCLK_INT:MUX.0.LH[6][0]	GCLK_INT:MUX.0.LH[6][5]	GCLK_INT:MUX.0.LH[6][4]	-	GCLK_INT:DRIVE.0.LH[6]
B7	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][1]
B6	GCLK_IO[1]:DELAY[1]	GCLK_IO[1]:DELAY[2]	BUFG[0]:DISABLE_ATTR	BUFG[1]:DISABLE_ATTR	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][0]	GCLK_IO[1]:DELAY[4]	GCLK_IO[1]:DELAY[3]
B5	GCLK_INT:MUX.0.LH[0][2]	GCLK_INT:MUX.0.LH[0][3]	GCLK_INT:MUX.0.LH[0][1]	GCLK_INT:MUX.0.LH[0][0]	GCLK_INT:MUX.0.LH[0][5]	GCLK_INT:MUX.0.LH[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][2]	GCLK_INT:DRIVE.0.LH[0]
B4	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][6]	GCLK_INT:INV.IMUX_BUFGCE_CE[0]	GCLK_INT:INV.IMUX_BUFGCE_CE[1]
B3	GCLK_IO[0]:DELAY[0]	GCLK_IO[0]:DELAY[1]	GCLK_IO[0]:DELAY[2]	GCLK_IO[0]:DELAY[3]	GCLK_IO[0]:DELAY[4]	GCLK_IO[1]:DELAY[0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][1]
B2	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][3]
B1	GCLK_INT:MUX.0.LH[3][2]	GCLK_INT:MUX.0.LH[3][3]	GCLK_INT:MUX.0.LH[3][1]	GCLK_INT:MUX.0.LH[3][0]	GCLK_INT:MUX.0.LH[3][5]	GCLK_INT:MUX.0.LH[3][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][10]	GCLK_INT:DRIVE.0.LH[3]
B0	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][10]

virtex CLK_S_VE_2DLL rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B2	GCLK_IO[1]:IBUF[0]	GCLK_IO[1]:IBUF[1]	IOFB[1]:IBUF[1]	IOFB[1]:IBUF[0]
B1	-	-	-	-
B0	GCLK_IO[0]:IBUF[0]	GCLK_IO[0]:IBUF[1]	IOFB[0]:IBUF[1]	IOFB[0]:IBUF[0]

BUFG[0]:DISABLE_ATTR	0.F2.B6
BUFG[1]:DISABLE_ATTR	0.F3.B6
GCLK_INT:DRIVE.0.LH[0]	0.F7.B5
GCLK_INT:DRIVE.0.LH[3]	0.F7.B1
GCLK_INT:DRIVE.0.LH[6]	0.F7.B8
GCLK_INT:DRIVE.0.LH[9]	0.F7.B9
GCLK_INT:INV.IMUX_BUFGCE_CE[0]	0.F6.B4
GCLK_INT:INV.IMUX_BUFGCE_CE[1]	0.F7.B4
non-inverted	[0]

GCLK_INT:DRIVE.0.HEX_H1[0]	0.F7.B17
GCLK_INT:DRIVE.0.HEX_H1[1]	0.F7.B16
GCLK_INT:DRIVE.0.HEX_H1[2]	0.F7.B15
GCLK_INT:DRIVE.0.HEX_H1[3]	0.F7.B14
GCLK_INT:DRIVE.0.HEX_H6[0]	0.F7.B13
GCLK_INT:DRIVE.0.HEX_H6[1]	0.F7.B12
GCLK_INT:DRIVE.0.HEX_H6[2]	0.F7.B11
GCLK_INT:DRIVE.0.HEX_H6[3]	0.F7.B10
inverted	~[0]

GCLK_INT:MUX.0.HEX_H1[0]	0.F4.B17	0.F5.B17	0.F1.B17	0.F0.B17	0.F2.B17	0.F3.B17
GCLK_INT:MUX.0.HEX_H1[1]	0.F4.B16	0.F5.B16	0.F1.B16	0.F0.B16	0.F2.B16	0.F3.B16
GCLK_INT:MUX.0.HEX_H1[2]	0.F4.B15	0.F5.B15	0.F1.B15	0.F0.B15	0.F2.B15	0.F3.B15
GCLK_INT:MUX.0.HEX_H1[3]	0.F4.B14	0.F5.B14	0.F1.B14	0.F0.B14	0.F2.B14	0.F3.B14
GCLK_INT:MUX.0.HEX_H6[0]	0.F4.B13	0.F5.B13	0.F1.B13	0.F0.B13	0.F2.B13	0.F3.B13
GCLK_INT:MUX.0.HEX_H6[1]	0.F4.B12	0.F5.B12	0.F1.B12	0.F0.B12	0.F2.B12	0.F3.B12
GCLK_INT:MUX.0.HEX_H6[2]	0.F4.B11	0.F5.B11	0.F1.B11	0.F0.B11	0.F2.B11	0.F3.B11
GCLK_INT:MUX.0.HEX_H6[3]	0.F4.B10	0.F5.B10	0.F1.B10	0.F0.B10	0.F2.B10	0.F3.B10
GCLK_INT:MUX.0.LH[0]	0.F4.B5	0.F5.B5	0.F1.B5	0.F0.B5	0.F2.B5	0.F3.B5
GCLK_INT:MUX.0.LH[3]	0.F4.B1	0.F5.B1	0.F1.B1	0.F0.B1	0.F2.B1	0.F3.B1
GCLK_INT:MUX.0.LH[6]	0.F4.B8	0.F5.B8	0.F1.B8	0.F0.B8	0.F2.B8	0.F3.B8
GCLK_INT:MUX.0.LH[9]	0.F4.B9	0.F5.B9	0.F1.B9	0.F0.B9	0.F2.B9	0.F3.B9
0.OUT_CLKPAD[0]	0	0	0	0	1	1
0.OUT_BUFGCE_O[0]	0	0	0	1	1	1
3.OUT_DLL_CLK2X	0	1	0	0	1	0
3.OUT_DLL_CLKDV	0	1	0	1	0	0
4.OUT_DLL_CLK180	0	1	0	1	1	0
3.OUT_DLL_CLK270	0	1	1	0	0	0
3.OUT_DLL_CLK90	0	1	1	0	1	0
0.OUT_BUFGCE_O[1]	0	1	1	0	1	1
4.OUT_DLL_CLK270	0	1	1	1	0	0
4.OUT_DLL_CLK2X	1	0	0	0	1	0
3.OUT_DLL_CLK2X90	1	0	0	1	0	0
0.OUT_CLKPAD[1]	1	0	0	1	0	1
3.OUT_DLL_CLK180	1	0	0	1	1	0
4.OUT_DLL_CLK90	1	0	1	0	0	0
4.OUT_DLL_CLK2X90	1	0	1	0	1	0
3.OUT_DLL_CLK0	1	0	1	1	0	0
4.OUT_DLL_LOCKED	1	1	0	0	1	0
4.OUT_DLL_CLKDV	1	1	0	1	0	0
3.OUT_DLL_LOCKED	1	1	1	0	0	0
4.OUT_DLL_CLK0	1	1	1	0	1	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0]	0.F5.B4	0.F3.B4	0.F2.B4	0.F1.B4	0.F0.B4	0.F7.B7	0.F6.B7
GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1]	0.F4.B4	0.F5.B7	0.F4.B7	0.F3.B7	0.F2.B7	0.F1.B7	0.F0.B7
NONE	0	0	0	0	0	0	0
0.HEX_H1[2]	0	0	0	0	0	0	1
0.HEX_H2[2]	0	0	0	0	0	1	0
0.HEX_H3[2]	0	0	0	0	1	0	0
0.HEX_H4[2]	0	0	0	1	0	0	0
0.HEX_H5[2]	0	0	1	0	0	0	0
0.HEX_H6[2]	0	1	0	0	0	0	0
0.HEX_H1[3]	1	0	0	0	0	0	1
0.HEX_H2[3]	1	0	0	0	0	1	0
0.HEX_H3[3]	1	0	0	0	1	0	0
0.HEX_H4[3]	1	0	0	1	0	0	0
0.HEX_H5[3]	1	0	1	0	0	0	0
0.HEX_H6[3]	1	1	0	0	0	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0]	0.F7.B0	0.F1.B2	0.F4.B2	0.F5.B2	0.F6.B2	0.F3.B2	0.F2.B2	0.F0.B2	0.F6.B0	0.F6.B3	0.F4.B6
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	0	1	1
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1	1
0.HEX_H1[1]	0	0	0	0	0	0	1	0	0	1	1
0.HEX_H6[0]	0	0	0	0	0	0	1	0	1	1	1
0.HEX_H5[1]	0	0	0	0	0	1	0	0	0	1	1
0.HEX_H2[0]	0	0	0	0	0	1	0	0	1	1	1
0.HEX_H2[1]	0	0	0	0	1	0	0	0	0	1	1
0.HEX_H3[0]	0	0	0	0	1	0	0	0	1	1	1
0.HEX_H3[1]	0	0	0	1	0	0	0	0	0	1	1
0.HEX_H4[0]	0	0	0	1	0	0	0	0	1	1	1
0.HEX_H4[1]	0	0	1	0	0	0	0	0	0	1	1
0.HEX_H5[0]	0	0	1	0	0	0	0	0	1	1	1
0.HEX_H6[1]	0	1	0	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK270	1	0	0	0	0	0	0	1	0	1	0
4.OUT_DLL_CLK180	1	0	0	0	0	0	0	1	0	1	1
3.OUT_DLL_CLK90	1	0	0	0	0	0	1	0	0	1	0
4.OUT_DLL_CLKDV	1	0	0	0	0	0	1	0	0	1	1
3.OUT_DLL_CLKDV	1	0	0	0	0	1	0	0	0	1	0
4.OUT_DLL_CLK2X90	1	0	0	0	0	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	0	1	0	0	0	0	1	0
4.OUT_DLL_CLK0	1	0	0	0	1	0	0	0	0	1	1
3.OUT_DLL_CLK0	1	0	0	1	0	0	0	0	0	1	0
4.OUT_DLL_CLK90	1	0	0	1	0	0	0	0	0	1	1
3.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK180	1	1	0	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK270	1	1	0	0	0	0	0	0	0	1	1

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1]	0.F6.B1	0.F0.B0	0.F3.B0	0.F4.B0	0.F5.B0	0.F2.B0	0.F1.B0	0.F7.B2	0.F6.B5	0.F7.B3	0.F5.B6
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	0	1	1
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1	1
0.HEX_H1[1]	0	0	0	0	0	0	1	0	0	1	1
0.HEX_H6[0]	0	0	0	0	0	0	1	0	1	1	1
0.HEX_H5[1]	0	0	0	0	0	1	0	0	0	1	1
0.HEX_H2[0]	0	0	0	0	0	1	0	0	1	1	1
0.HEX_H2[1]	0	0	0	0	1	0	0	0	0	1	1
0.HEX_H3[0]	0	0	0	0	1	0	0	0	1	1	1
0.HEX_H3[1]	0	0	0	1	0	0	0	0	0	1	1
0.HEX_H4[0]	0	0	0	1	0	0	0	0	1	1	1
0.HEX_H4[1]	0	0	1	0	0	0	0	0	0	1	1
0.HEX_H5[0]	0	0	1	0	0	0	0	0	1	1	1
0.HEX_H6[1]	0	1	0	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK270	1	0	0	0	0	0	0	1	0	1	0
4.OUT_DLL_CLK180	1	0	0	0	0	0	0	1	0	1	1
3.OUT_DLL_CLK90	1	0	0	0	0	0	1	0	0	1	0
4.OUT_DLL_CLKDV	1	0	0	0	0	0	1	0	0	1	1
3.OUT_DLL_CLKDV	1	0	0	0	0	1	0	0	0	1	0
4.OUT_DLL_CLK2X90	1	0	0	0	0	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	0	1	0	0	0	0	1	0
4.OUT_DLL_CLK0	1	0	0	0	1	0	0	0	0	1	1
3.OUT_DLL_CLK0	1	0	0	1	0	0	0	0	0	1	0
4.OUT_DLL_CLK90	1	0	0	1	0	0	0	0	0	1	1
3.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK180	1	1	0	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK270	1	1	0	0	0	0	0	0	0	1	1

GCLK_IO[0]:DELAY	0.F4.B3	0.F3.B3	0.F2.B3	0.F1.B3	0.F0.B3
GCLK_IO[1]:DELAY	0.F6.B6	0.F7.B6	0.F1.B6	0.F0.B6	0.F5.B3
non-inverted	[4]	[3]	[2]	[1]	[0]

GCLK_IO[0]:IBUF	1.F1.B0	1.F0.B0
GCLK_IO[1]:IBUF	1.F1.B2	1.F0.B2
CMOS	0	0
VREF	0	1
DIFF	1	0
NONE	1	1

IOFB[0]:IBUF	1.F2.B0	1.F3.B0
IOFB[1]:IBUF	1.F2.B2	1.F3.B2
CMOS	0	1
VREF	1	0
NONE	1	1

Tile CLK_N_V

Cells: 3

Switchbox GCLK_INT

virtex CLK_N_V switchbox GCLK_INT muxes HEX_H1[0]
Bits	Destination
CELL.HEX_H1[0]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes HEX_H1[1]
Bits	Destination
CELL.HEX_H1[1]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes HEX_H1[2]
Bits	Destination
CELL.HEX_H1[2]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes HEX_H1[3]
Bits	Destination
CELL.HEX_H1[3]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes HEX_H6[0]
Bits	Destination
CELL.HEX_H6[0]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes HEX_H6[1]
Bits	Destination
CELL.HEX_H6[1]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes HEX_H6[2]
Bits	Destination
CELL.HEX_H6[2]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes HEX_H6[3]
Bits	Destination
CELL.HEX_H6[3]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes LH[0]
Bits	Destination
CELL.LH[0]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes LH[3]
Bits	Destination
CELL.LH[3]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes LH[6]
Bits	Destination
CELL.LH[6]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes LH[9]
Bits	Destination
CELL.LH[9]
	Source
DLL_E.OUT_DLL_LOCKED

virtex CLK_N_V switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[0]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[0]
	Source
DLL_E.OUT_DLL_CLKDV

virtex CLK_N_V switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[1]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[1]
	Source
DLL_E.OUT_DLL_CLKDV

virtex CLK_N_V switchbox GCLK_INT muxes IMUX_BUFGCE_CE[0]
Bits	Destination
CELL.IMUX_BUFGCE_CE[0]
	Source
CELL.HEX_H6[3]

virtex CLK_N_V switchbox GCLK_INT muxes IMUX_BUFGCE_CE[1]
Bits	Destination
CELL.IMUX_BUFGCE_CE[1]
	Source
CELL.HEX_H6[3]

Bel GCLK_IO[0]

virtex CLK_N_V bel GCLK_IO[0]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[0]

Bel GCLK_IO[1]

virtex CLK_N_V bel GCLK_IO[1]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[1]

Bel BUFG[0]

virtex CLK_N_V bel BUFG[0]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[0]
IN	input	CELL.IMUX_BUFGCE_CLK[0]
OUT	output	CELL.OUT_BUFGCE_O[0]

Bel BUFG[1]

virtex CLK_N_V bel BUFG[1]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[1]
IN	input	CELL.IMUX_BUFGCE_CLK[1]
OUT	output	CELL.OUT_BUFGCE_O[1]

Bel wires

virtex CLK_N_V bel wires
Wire	Pins
CELL.IMUX_BUFGCE_CLK[0]	BUFG[0].IN
CELL.IMUX_BUFGCE_CLK[1]	BUFG[1].IN
CELL.IMUX_BUFGCE_CE[0]	BUFG[0].CE
CELL.IMUX_BUFGCE_CE[1]	BUFG[1].CE
CELL.OUT_BUFGCE_O[0]	BUFG[0].OUT
CELL.OUT_BUFGCE_O[1]	BUFG[1].OUT
CELL.OUT_CLKPAD[0]	GCLK_IO[0].GCLKOUT
CELL.OUT_CLKPAD[1]	GCLK_IO[1].GCLKOUT

Bitstream

virtex CLK_N_V rect CLK[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

virtex CLK_N_V rect CLK[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

### Bitstream

virtex CLK_N_V rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	GCLK_INT:MUX.0.HEX_H1[0][1]	GCLK_INT:MUX.0.HEX_H1[0][0]	GCLK_INT:MUX.0.HEX_H1[0][2]	GCLK_INT:MUX.0.HEX_H1[0][3]	GCLK_INT:MUX.0.HEX_H1[0][4]	GCLK_INT:MUX.0.HEX_H1[0][6]	GCLK_INT:MUX.0.HEX_H1[0][5]	~GCLK_INT:DRIVE.0.HEX_H1[0]
B16	GCLK_INT:MUX.0.HEX_H1[1][1]	GCLK_INT:MUX.0.HEX_H1[1][0]	GCLK_INT:MUX.0.HEX_H1[1][2]	GCLK_INT:MUX.0.HEX_H1[1][3]	GCLK_INT:MUX.0.HEX_H1[1][4]	GCLK_INT:MUX.0.HEX_H1[1][6]	GCLK_INT:MUX.0.HEX_H1[1][5]	~GCLK_INT:DRIVE.0.HEX_H1[1]
B15	GCLK_INT:MUX.0.HEX_H1[2][1]	GCLK_INT:MUX.0.HEX_H1[2][0]	GCLK_INT:MUX.0.HEX_H1[2][2]	GCLK_INT:MUX.0.HEX_H1[2][3]	GCLK_INT:MUX.0.HEX_H1[2][4]	GCLK_INT:MUX.0.HEX_H1[2][6]	GCLK_INT:MUX.0.HEX_H1[2][5]	~GCLK_INT:DRIVE.0.HEX_H1[2]
B14	GCLK_INT:MUX.0.HEX_H1[3][1]	GCLK_INT:MUX.0.HEX_H1[3][0]	GCLK_INT:MUX.0.HEX_H1[3][2]	GCLK_INT:MUX.0.HEX_H1[3][3]	GCLK_INT:MUX.0.HEX_H1[3][4]	GCLK_INT:MUX.0.HEX_H1[3][6]	GCLK_INT:MUX.0.HEX_H1[3][5]	~GCLK_INT:DRIVE.0.HEX_H1[3]
B13	GCLK_INT:MUX.0.HEX_H6[0][1]	GCLK_INT:MUX.0.HEX_H6[0][0]	GCLK_INT:MUX.0.HEX_H6[0][2]	GCLK_INT:MUX.0.HEX_H6[0][3]	GCLK_INT:MUX.0.HEX_H6[0][4]	GCLK_INT:MUX.0.HEX_H6[0][6]	GCLK_INT:MUX.0.HEX_H6[0][5]	~GCLK_INT:DRIVE.0.HEX_H6[0]
B12	GCLK_INT:MUX.0.HEX_H6[1][1]	GCLK_INT:MUX.0.HEX_H6[1][0]	GCLK_INT:MUX.0.HEX_H6[1][2]	GCLK_INT:MUX.0.HEX_H6[1][3]	GCLK_INT:MUX.0.HEX_H6[1][4]	GCLK_INT:MUX.0.HEX_H6[1][6]	GCLK_INT:MUX.0.HEX_H6[1][5]	~GCLK_INT:DRIVE.0.HEX_H6[1]
B11	GCLK_INT:MUX.0.HEX_H6[2][1]	GCLK_INT:MUX.0.HEX_H6[2][0]	GCLK_INT:MUX.0.HEX_H6[2][2]	GCLK_INT:MUX.0.HEX_H6[2][3]	GCLK_INT:MUX.0.HEX_H6[2][4]	GCLK_INT:MUX.0.HEX_H6[2][6]	GCLK_INT:MUX.0.HEX_H6[2][5]	~GCLK_INT:DRIVE.0.HEX_H6[2]
B10	GCLK_INT:MUX.0.HEX_H6[3][1]	GCLK_INT:MUX.0.HEX_H6[3][0]	GCLK_INT:MUX.0.HEX_H6[3][2]	GCLK_INT:MUX.0.HEX_H6[3][3]	GCLK_INT:MUX.0.HEX_H6[3][4]	GCLK_INT:MUX.0.HEX_H6[3][6]	GCLK_INT:MUX.0.HEX_H6[3][5]	~GCLK_INT:DRIVE.0.HEX_H6[3]
B9	GCLK_INT:MUX.0.LH[9][0]	GCLK_INT:MUX.0.LH[9][4]	GCLK_INT:MUX.0.LH[9][3]	GCLK_INT:MUX.0.LH[9][2]	GCLK_INT:MUX.0.LH[9][1]	GCLK_INT:MUX.0.LH[9][6]	GCLK_INT:MUX.0.LH[9][5]	GCLK_INT:DRIVE.0.LH[9]
B8	GCLK_INT:MUX.0.LH[6][0]	GCLK_INT:MUX.0.LH[6][4]	GCLK_INT:MUX.0.LH[6][3]	GCLK_INT:MUX.0.LH[6][2]	GCLK_INT:MUX.0.LH[6][1]	GCLK_INT:MUX.0.LH[6][6]	GCLK_INT:MUX.0.LH[6][5]	GCLK_INT:DRIVE.0.LH[6]
B7	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][1]
B6	GCLK_IO[1]:DELAY[1]	GCLK_IO[1]:DELAY[2]	BUFG[0]:DISABLE_ATTR	BUFG[1]:DISABLE_ATTR	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][0]	GCLK_IO[1]:DELAY[4]	GCLK_IO[1]:DELAY[3]
B5	GCLK_INT:MUX.0.LH[0][0]	GCLK_INT:MUX.0.LH[0][4]	GCLK_INT:MUX.0.LH[0][3]	GCLK_INT:MUX.0.LH[0][2]	GCLK_INT:MUX.0.LH[0][1]	GCLK_INT:MUX.0.LH[0][6]	GCLK_INT:MUX.0.LH[0][5]	GCLK_INT:DRIVE.0.LH[0]
B4	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][6]	GCLK_INT:INV.IMUX_BUFGCE_CE[0]	GCLK_INT:INV.IMUX_BUFGCE_CE[1]
B3	GCLK_IO[0]:DELAY[0]	GCLK_IO[0]:DELAY[1]	GCLK_IO[0]:DELAY[2]	GCLK_IO[0]:DELAY[3]	GCLK_IO[0]:DELAY[4]	GCLK_IO[1]:DELAY[0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][1]
B2	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][2]
B1	GCLK_INT:MUX.0.LH[3][0]	GCLK_INT:MUX.0.LH[3][4]	GCLK_INT:MUX.0.LH[3][3]	GCLK_INT:MUX.0.LH[3][2]	GCLK_INT:MUX.0.LH[3][1]	GCLK_INT:MUX.0.LH[3][6]	GCLK_INT:MUX.0.LH[3][5]	GCLK_INT:DRIVE.0.LH[3]
B0	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][3]

virtex CLK_N_V rect R1
Bit	Frame
Bit	F0	F1
B17	GCLK_IO[1]:IBUF[0]	GCLK_IO[1]:IBUF[1]
B16	GCLK_IO[0]:IBUF[0]	GCLK_IO[0]:IBUF[1]
B15	-	-
B14	-	-
B13	-	-
B12	-	-
B11	-	-
B10	-	-
B9	-	-
B8	-	-
B7	-	-
B6	-	-
B5	-	-
B4	-	-
B3	-	-
B2	-	-
B1	-	-
B0	-	-

BUFG[0]:DISABLE_ATTR	0.F2.B6
BUFG[1]:DISABLE_ATTR	0.F3.B6
GCLK_INT:DRIVE.0.LH[0]	0.F7.B5
GCLK_INT:DRIVE.0.LH[3]	0.F7.B1
GCLK_INT:DRIVE.0.LH[6]	0.F7.B8
GCLK_INT:DRIVE.0.LH[9]	0.F7.B9
GCLK_INT:INV.IMUX_BUFGCE_CE[0]	0.F6.B4
GCLK_INT:INV.IMUX_BUFGCE_CE[1]	0.F7.B4
non-inverted	[0]

GCLK_INT:DRIVE.0.HEX_H1[0]	0.F7.B17
GCLK_INT:DRIVE.0.HEX_H1[1]	0.F7.B16
GCLK_INT:DRIVE.0.HEX_H1[2]	0.F7.B15
GCLK_INT:DRIVE.0.HEX_H1[3]	0.F7.B14
GCLK_INT:DRIVE.0.HEX_H6[0]	0.F7.B13
GCLK_INT:DRIVE.0.HEX_H6[1]	0.F7.B12
GCLK_INT:DRIVE.0.HEX_H6[2]	0.F7.B11
GCLK_INT:DRIVE.0.HEX_H6[3]	0.F7.B10
inverted	~[0]

GCLK_INT:MUX.0.HEX_H1[0]	0.F5.B17	0.F6.B17	0.F4.B17	0.F3.B17	0.F2.B17	0.F0.B17	0.F1.B17
GCLK_INT:MUX.0.HEX_H1[1]	0.F5.B16	0.F6.B16	0.F4.B16	0.F3.B16	0.F2.B16	0.F0.B16	0.F1.B16
GCLK_INT:MUX.0.HEX_H1[2]	0.F5.B15	0.F6.B15	0.F4.B15	0.F3.B15	0.F2.B15	0.F0.B15	0.F1.B15
GCLK_INT:MUX.0.HEX_H1[3]	0.F5.B14	0.F6.B14	0.F4.B14	0.F3.B14	0.F2.B14	0.F0.B14	0.F1.B14
GCLK_INT:MUX.0.HEX_H6[0]	0.F5.B13	0.F6.B13	0.F4.B13	0.F3.B13	0.F2.B13	0.F0.B13	0.F1.B13
GCLK_INT:MUX.0.HEX_H6[1]	0.F5.B12	0.F6.B12	0.F4.B12	0.F3.B12	0.F2.B12	0.F0.B12	0.F1.B12
GCLK_INT:MUX.0.HEX_H6[2]	0.F5.B11	0.F6.B11	0.F4.B11	0.F3.B11	0.F2.B11	0.F0.B11	0.F1.B11
GCLK_INT:MUX.0.HEX_H6[3]	0.F5.B10	0.F6.B10	0.F4.B10	0.F3.B10	0.F2.B10	0.F0.B10	0.F1.B10
NONE	0	0	0	0	0	0	0
2.OUT_DLL_LOCKED	0	0	0	0	0	0	1
1.OUT_DLL_LOCKED	0	0	0	0	0	1	0
0.OUT_CLKPAD[1]	0	0	0	0	1	0	0
2.OUT_DLL_CLK0	0	0	0	1	0	0	0
2.OUT_DLL_CLKDV	0	0	1	0	0	0	0
0.OUT_BUFGCE_O[0]	0	1	0	0	0	0	1
1.OUT_DLL_CLK2X90	0	1	0	0	0	1	0
2.OUT_DLL_CLK180	0	1	0	0	1	0	0
2.OUT_DLL_CLK270	0	1	0	1	0	0	0
2.OUT_DLL_CLK2X	0	1	1	0	0	0	0
2.OUT_DLL_CLK2X90	1	0	0	0	0	0	1
0.OUT_BUFGCE_O[1]	1	0	0	0	0	1	0
1.OUT_DLL_CLK180	1	0	0	0	1	0	0
1.OUT_DLL_CLK0	1	0	0	1	0	0	0
2.OUT_DLL_CLK90	1	0	1	0	0	0	0
1.OUT_DLL_CLK270	1	1	0	0	0	0	1
1.OUT_DLL_CLK2X	1	1	0	0	0	1	0
0.OUT_CLKPAD[0]	1	1	0	0	1	0	0
1.OUT_DLL_CLK90	1	1	0	1	0	0	0
1.OUT_DLL_CLKDV	1	1	1	0	0	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0]	0.F5.B4	0.F3.B4	0.F2.B4	0.F1.B4	0.F0.B4	0.F7.B7	0.F6.B7
GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1]	0.F4.B4	0.F5.B7	0.F4.B7	0.F3.B7	0.F2.B7	0.F1.B7	0.F0.B7
NONE	0	0	0	0	0	0	0
0.HEX_H1[2]	0	0	0	0	0	0	1
0.HEX_H2[2]	0	0	0	0	0	1	0
0.HEX_H3[2]	0	0	0	0	1	0	0
0.HEX_H4[2]	0	0	0	1	0	0	0
0.HEX_H5[2]	0	0	1	0	0	0	0
0.HEX_H6[2]	0	1	0	0	0	0	0
0.HEX_H1[3]	1	0	0	0	0	0	1
0.HEX_H2[3]	1	0	0	0	0	1	0
0.HEX_H3[3]	1	0	0	0	1	0	0
0.HEX_H4[3]	1	0	0	1	0	0	0
0.HEX_H5[3]	1	0	1	0	0	0	0
0.HEX_H6[3]	1	1	0	0	0	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0]	0.F1.B2	0.F4.B2	0.F5.B2	0.F6.B2	0.F3.B2	0.F2.B2	0.F6.B0	0.F0.B2	0.F6.B3	0.F4.B6
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	1	0
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1
1.OUT_DLL_CLK270	0	0	0	0	0	0	1	1	1	0
1.OUT_DLL_CLKDV	0	0	0	0	0	1	0	0	1	0
0.HEX_H6[0]	0	0	0	0	0	1	0	0	1	1
1.OUT_DLL_CLK90	0	0	0	0	0	1	1	0	1	0
0.HEX_H1[1]	0	0	0	0	0	1	1	0	1	1
2.OUT_DLL_CLK2X	0	0	0	0	1	0	0	0	1	0
0.HEX_H2[0]	0	0	0	0	1	0	0	0	1	1
2.OUT_DLL_CLK180	0	0	0	0	1	0	1	0	1	0
0.HEX_H5[1]	0	0	0	0	1	0	1	0	1	1
1.OUT_DLL_CLK0	0	0	0	1	0	0	0	0	1	0
0.HEX_H3[0]	0	0	0	1	0	0	0	0	1	1
1.OUT_DLL_CLK2X	0	0	0	1	0	0	1	0	1	0
0.HEX_H2[1]	0	0	0	1	0	0	1	0	1	1
2.OUT_DLL_CLK0	0	0	1	0	0	0	0	0	1	0
0.HEX_H4[0]	0	0	1	0	0	0	0	0	1	1
1.OUT_DLL_CLK2X90	0	0	1	0	0	0	1	0	1	0
0.HEX_H3[1]	0	0	1	0	0	0	1	0	1	1
2.OUT_DLL_CLK90	0	1	0	0	0	0	0	0	1	0
0.HEX_H5[0]	0	1	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK2X90	0	1	0	0	0	0	1	0	1	0
0.HEX_H4[1]	0	1	0	0	0	0	1	0	1	1
2.OUT_DLL_CLKDV	1	0	0	0	0	0	0	0	1	0
1.OUT_DLL_CLK180	1	0	0	0	0	0	1	0	1	0
0.HEX_H6[1]	1	0	0	0	0	0	1	0	1	1

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1]	0.F0.B0	0.F3.B0	0.F4.B0	0.F5.B0	0.F2.B0	0.F1.B0	0.F7.B0	0.F7.B2	0.F7.B3	0.F5.B6
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	1	0
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1
1.OUT_DLL_CLK270	0	0	0	0	0	0	1	1	1	0
1.OUT_DLL_CLKDV	0	0	0	0	0	1	0	0	1	0
0.HEX_H6[0]	0	0	0	0	0	1	0	0	1	1
1.OUT_DLL_CLK90	0	0	0	0	0	1	1	0	1	0
0.HEX_H1[1]	0	0	0	0	0	1	1	0	1	1
2.OUT_DLL_CLK2X	0	0	0	0	1	0	0	0	1	0
0.HEX_H2[0]	0	0	0	0	1	0	0	0	1	1
2.OUT_DLL_CLK180	0	0	0	0	1	0	1	0	1	0
0.HEX_H5[1]	0	0	0	0	1	0	1	0	1	1
1.OUT_DLL_CLK0	0	0	0	1	0	0	0	0	1	0
0.HEX_H3[0]	0	0	0	1	0	0	0	0	1	1
1.OUT_DLL_CLK2X	0	0	0	1	0	0	1	0	1	0
0.HEX_H2[1]	0	0	0	1	0	0	1	0	1	1
2.OUT_DLL_CLK0	0	0	1	0	0	0	0	0	1	0
0.HEX_H4[0]	0	0	1	0	0	0	0	0	1	1
1.OUT_DLL_CLK2X90	0	0	1	0	0	0	1	0	1	0
0.HEX_H3[1]	0	0	1	0	0	0	1	0	1	1
2.OUT_DLL_CLK90	0	1	0	0	0	0	0	0	1	0
0.HEX_H5[0]	0	1	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK2X90	0	1	0	0	0	0	1	0	1	0
0.HEX_H4[1]	0	1	0	0	0	0	1	0	1	1
2.OUT_DLL_CLKDV	1	0	0	0	0	0	0	0	1	0
1.OUT_DLL_CLK180	1	0	0	0	0	0	1	0	1	0
0.HEX_H6[1]	1	0	0	0	0	0	1	0	1	1

GCLK_INT:MUX.0.LH[0]	0.F5.B5	0.F6.B5	0.F1.B5	0.F2.B5	0.F3.B5	0.F4.B5	0.F0.B5
GCLK_INT:MUX.0.LH[3]	0.F5.B1	0.F6.B1	0.F1.B1	0.F2.B1	0.F3.B1	0.F4.B1	0.F0.B1
GCLK_INT:MUX.0.LH[6]	0.F5.B8	0.F6.B8	0.F1.B8	0.F2.B8	0.F3.B8	0.F4.B8	0.F0.B8
GCLK_INT:MUX.0.LH[9]	0.F5.B9	0.F6.B9	0.F1.B9	0.F2.B9	0.F3.B9	0.F4.B9	0.F0.B9
NONE	0	0	0	0	0	0	0
0.OUT_BUFGCE_O[0]	0	0	0	0	0	0	1
0.OUT_BUFGCE_O[1]	0	0	0	0	0	1	0
0.OUT_CLKPAD[1]	0	0	0	0	1	0	0
1.OUT_DLL_CLK2X	0	0	0	1	0	0	0
2.OUT_DLL_CLK2X90	0	0	1	0	0	0	0
1.OUT_DLL_CLK180	0	1	0	0	0	0	1
0.OUT_CLKPAD[0]	0	1	0	0	0	1	0
2.OUT_DLL_CLK90	0	1	0	0	1	0	0
2.OUT_DLL_LOCKED	0	1	0	1	0	0	0
1.OUT_DLL_CLK270	0	1	1	0	0	0	0
1.OUT_DLL_LOCKED	1	0	0	0	0	0	1
2.OUT_DLL_CLK180	1	0	0	0	0	1	0
1.OUT_DLL_CLK2X90	1	0	0	0	1	0	0
1.OUT_DLL_CLK0	1	0	0	1	0	0	0
1.OUT_DLL_CLK90	1	0	1	0	0	0	0
2.OUT_DLL_CLKDV	1	1	0	0	0	0	1
2.OUT_DLL_CLK0	1	1	0	0	0	1	0
2.OUT_DLL_CLK2X	1	1	0	0	1	0	0
1.OUT_DLL_CLKDV	1	1	0	1	0	0	0
2.OUT_DLL_CLK270	1	1	1	0	0	0	0

GCLK_IO[0]:DELAY	0.F4.B3	0.F3.B3	0.F2.B3	0.F1.B3	0.F0.B3
GCLK_IO[1]:DELAY	0.F6.B6	0.F7.B6	0.F1.B6	0.F0.B6	0.F5.B3
non-inverted	[4]	[3]	[2]	[1]	[0]

GCLK_IO[0]:IBUF	1.F1.B16	1.F0.B16
GCLK_IO[1]:IBUF	1.F1.B17	1.F0.B17
CMOS	0	0
VREF_LV	0	1
VREF_HV	1	0
NONE	1	1

Tile CLK_N_VE_4DLL

Cells: 5

Switchbox GCLK_INT

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes HEX_H1[0]
Bits	Destination
CELL.HEX_H1[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes HEX_H1[1]
Bits	Destination
CELL.HEX_H1[1]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes HEX_H1[2]
Bits	Destination
CELL.HEX_H1[2]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes HEX_H1[3]
Bits	Destination
CELL.HEX_H1[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes HEX_H6[0]
Bits	Destination
CELL.HEX_H6[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes HEX_H6[1]
Bits	Destination
CELL.HEX_H6[1]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes HEX_H6[2]
Bits	Destination
CELL.HEX_H6[2]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes HEX_H6[3]
Bits	Destination
CELL.HEX_H6[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes LH[0]
Bits	Destination
CELL.LH[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes LH[3]
Bits	Destination
CELL.LH[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes LH[6]
Bits	Destination
CELL.LH[6]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes LH[9]
Bits	Destination
CELL.LH[9]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[0]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[0]
	Source
DLLS_E.OUT_DLL_CLKDV

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[1]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[1]
	Source
DLLS_E.OUT_DLL_CLKDV

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CE[0]
Bits	Destination
CELL.IMUX_BUFGCE_CE[0]
	Source
CELL.HEX_H6[3]

virtex CLK_N_VE_4DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CE[1]
Bits	Destination
CELL.IMUX_BUFGCE_CE[1]
	Source
CELL.HEX_H6[3]

Bel GCLK_IO[0]

virtex CLK_N_VE_4DLL bel GCLK_IO[0]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[0]

Bel GCLK_IO[1]

virtex CLK_N_VE_4DLL bel GCLK_IO[1]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[1]

Bel BUFG[0]

virtex CLK_N_VE_4DLL bel BUFG[0]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[0]
IN	input	CELL.IMUX_BUFGCE_CLK[0]
OUT	output	CELL.OUT_BUFGCE_O[0]

Bel BUFG[1]

virtex CLK_N_VE_4DLL bel BUFG[1]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[1]
IN	input	CELL.IMUX_BUFGCE_CLK[1]
OUT	output	CELL.OUT_BUFGCE_O[1]

Bel IOFB[0]

virtex CLK_N_VE_4DLL bel IOFB[0]
Pin	Direction	Wires
O	output	CELL.OUT_IOFB[0]

Bel IOFB[1]

virtex CLK_N_VE_4DLL bel IOFB[1]
Pin	Direction	Wires
O	output	CELL.OUT_IOFB[1]

Bel wires

virtex CLK_N_VE_4DLL bel wires
Wire	Pins
CELL.IMUX_BUFGCE_CLK[0]	BUFG[0].IN
CELL.IMUX_BUFGCE_CLK[1]	BUFG[1].IN
CELL.IMUX_BUFGCE_CE[0]	BUFG[0].CE
CELL.IMUX_BUFGCE_CE[1]	BUFG[1].CE
CELL.OUT_BUFGCE_O[0]	BUFG[0].OUT
CELL.OUT_BUFGCE_O[1]	BUFG[1].OUT
CELL.OUT_CLKPAD[0]	GCLK_IO[0].GCLKOUT
CELL.OUT_CLKPAD[1]	GCLK_IO[1].GCLKOUT
CELL.OUT_IOFB[0]	IOFB[0].O
CELL.OUT_IOFB[1]	IOFB[1].O

Bitstream

virtex CLK_N_VE_4DLL rect CLK[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

virtex CLK_N_VE_4DLL rect CLK[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

### Bitstream

virtex CLK_N_VE_4DLL rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	GCLK_INT:MUX.0.HEX_H1[0][2]	GCLK_INT:MUX.0.HEX_H1[0][3]	GCLK_INT:MUX.0.HEX_H1[0][1]	GCLK_INT:MUX.0.HEX_H1[0][0]	GCLK_INT:MUX.0.HEX_H1[0][5]	GCLK_INT:MUX.0.HEX_H1[0][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[0]
B16	GCLK_INT:MUX.0.HEX_H1[1][2]	GCLK_INT:MUX.0.HEX_H1[1][3]	GCLK_INT:MUX.0.HEX_H1[1][1]	GCLK_INT:MUX.0.HEX_H1[1][0]	GCLK_INT:MUX.0.HEX_H1[1][5]	GCLK_INT:MUX.0.HEX_H1[1][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[1]
B15	GCLK_INT:MUX.0.HEX_H1[2][2]	GCLK_INT:MUX.0.HEX_H1[2][3]	GCLK_INT:MUX.0.HEX_H1[2][1]	GCLK_INT:MUX.0.HEX_H1[2][0]	GCLK_INT:MUX.0.HEX_H1[2][5]	GCLK_INT:MUX.0.HEX_H1[2][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[2]
B14	GCLK_INT:MUX.0.HEX_H1[3][2]	GCLK_INT:MUX.0.HEX_H1[3][3]	GCLK_INT:MUX.0.HEX_H1[3][1]	GCLK_INT:MUX.0.HEX_H1[3][0]	GCLK_INT:MUX.0.HEX_H1[3][5]	GCLK_INT:MUX.0.HEX_H1[3][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[3]
B13	GCLK_INT:MUX.0.HEX_H6[0][2]	GCLK_INT:MUX.0.HEX_H6[0][3]	GCLK_INT:MUX.0.HEX_H6[0][1]	GCLK_INT:MUX.0.HEX_H6[0][0]	GCLK_INT:MUX.0.HEX_H6[0][5]	GCLK_INT:MUX.0.HEX_H6[0][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[0]
B12	GCLK_INT:MUX.0.HEX_H6[1][2]	GCLK_INT:MUX.0.HEX_H6[1][3]	GCLK_INT:MUX.0.HEX_H6[1][1]	GCLK_INT:MUX.0.HEX_H6[1][0]	GCLK_INT:MUX.0.HEX_H6[1][5]	GCLK_INT:MUX.0.HEX_H6[1][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[1]
B11	GCLK_INT:MUX.0.HEX_H6[2][2]	GCLK_INT:MUX.0.HEX_H6[2][3]	GCLK_INT:MUX.0.HEX_H6[2][1]	GCLK_INT:MUX.0.HEX_H6[2][0]	GCLK_INT:MUX.0.HEX_H6[2][5]	GCLK_INT:MUX.0.HEX_H6[2][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[2]
B10	GCLK_INT:MUX.0.HEX_H6[3][2]	GCLK_INT:MUX.0.HEX_H6[3][3]	GCLK_INT:MUX.0.HEX_H6[3][1]	GCLK_INT:MUX.0.HEX_H6[3][0]	GCLK_INT:MUX.0.HEX_H6[3][5]	GCLK_INT:MUX.0.HEX_H6[3][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[3]
B9	GCLK_INT:MUX.0.LH[9][2]	GCLK_INT:MUX.0.LH[9][3]	GCLK_INT:MUX.0.LH[9][1]	GCLK_INT:MUX.0.LH[9][0]	GCLK_INT:MUX.0.LH[9][5]	GCLK_INT:MUX.0.LH[9][4]	-	GCLK_INT:DRIVE.0.LH[9]
B8	GCLK_INT:MUX.0.LH[6][2]	GCLK_INT:MUX.0.LH[6][3]	GCLK_INT:MUX.0.LH[6][1]	GCLK_INT:MUX.0.LH[6][0]	GCLK_INT:MUX.0.LH[6][5]	GCLK_INT:MUX.0.LH[6][4]	-	GCLK_INT:DRIVE.0.LH[6]
B7	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][1]
B6	GCLK_IO[1]:DELAY[1]	GCLK_IO[1]:DELAY[2]	BUFG[0]:DISABLE_ATTR	BUFG[1]:DISABLE_ATTR	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][0]	GCLK_IO[1]:DELAY[4]	GCLK_IO[1]:DELAY[3]
B5	GCLK_INT:MUX.0.LH[0][2]	GCLK_INT:MUX.0.LH[0][3]	GCLK_INT:MUX.0.LH[0][1]	GCLK_INT:MUX.0.LH[0][0]	GCLK_INT:MUX.0.LH[0][5]	GCLK_INT:MUX.0.LH[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][2]	GCLK_INT:DRIVE.0.LH[0]
B4	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][6]	GCLK_INT:INV.IMUX_BUFGCE_CE[0]	GCLK_INT:INV.IMUX_BUFGCE_CE[1]
B3	GCLK_IO[0]:DELAY[0]	GCLK_IO[0]:DELAY[1]	GCLK_IO[0]:DELAY[2]	GCLK_IO[0]:DELAY[3]	GCLK_IO[0]:DELAY[4]	GCLK_IO[1]:DELAY[0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][1]
B2	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][3]
B1	GCLK_INT:MUX.0.LH[3][2]	GCLK_INT:MUX.0.LH[3][3]	GCLK_INT:MUX.0.LH[3][1]	GCLK_INT:MUX.0.LH[3][0]	GCLK_INT:MUX.0.LH[3][5]	GCLK_INT:MUX.0.LH[3][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][10]	GCLK_INT:DRIVE.0.LH[3]
B0	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][10]

virtex CLK_N_VE_4DLL rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B17	GCLK_IO[1]:IBUF[0]	GCLK_IO[1]:IBUF[1]	IOFB[1]:IBUF[1]	IOFB[1]:IBUF[0]
B16	GCLK_IO[0]:IBUF[0]	GCLK_IO[0]:IBUF[1]	IOFB[0]:IBUF[1]	IOFB[0]:IBUF[0]
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

BUFG[0]:DISABLE_ATTR	0.F2.B6
BUFG[1]:DISABLE_ATTR	0.F3.B6
GCLK_INT:DRIVE.0.LH[0]	0.F7.B5
GCLK_INT:DRIVE.0.LH[3]	0.F7.B1
GCLK_INT:DRIVE.0.LH[6]	0.F7.B8
GCLK_INT:DRIVE.0.LH[9]	0.F7.B9
GCLK_INT:INV.IMUX_BUFGCE_CE[0]	0.F6.B4
GCLK_INT:INV.IMUX_BUFGCE_CE[1]	0.F7.B4
non-inverted	[0]

GCLK_INT:DRIVE.0.HEX_H1[0]	0.F7.B17
GCLK_INT:DRIVE.0.HEX_H1[1]	0.F7.B16
GCLK_INT:DRIVE.0.HEX_H1[2]	0.F7.B15
GCLK_INT:DRIVE.0.HEX_H1[3]	0.F7.B14
GCLK_INT:DRIVE.0.HEX_H6[0]	0.F7.B13
GCLK_INT:DRIVE.0.HEX_H6[1]	0.F7.B12
GCLK_INT:DRIVE.0.HEX_H6[2]	0.F7.B11
GCLK_INT:DRIVE.0.HEX_H6[3]	0.F7.B10
inverted	~[0]

GCLK_INT:MUX.0.HEX_H1[0]	0.F4.B17	0.F5.B17	0.F1.B17	0.F0.B17	0.F2.B17	0.F3.B17
GCLK_INT:MUX.0.HEX_H1[1]	0.F4.B16	0.F5.B16	0.F1.B16	0.F0.B16	0.F2.B16	0.F3.B16
GCLK_INT:MUX.0.HEX_H1[2]	0.F4.B15	0.F5.B15	0.F1.B15	0.F0.B15	0.F2.B15	0.F3.B15
GCLK_INT:MUX.0.HEX_H1[3]	0.F4.B14	0.F5.B14	0.F1.B14	0.F0.B14	0.F2.B14	0.F3.B14
GCLK_INT:MUX.0.HEX_H6[0]	0.F4.B13	0.F5.B13	0.F1.B13	0.F0.B13	0.F2.B13	0.F3.B13
GCLK_INT:MUX.0.HEX_H6[1]	0.F4.B12	0.F5.B12	0.F1.B12	0.F0.B12	0.F2.B12	0.F3.B12
GCLK_INT:MUX.0.HEX_H6[2]	0.F4.B11	0.F5.B11	0.F1.B11	0.F0.B11	0.F2.B11	0.F3.B11
GCLK_INT:MUX.0.HEX_H6[3]	0.F4.B10	0.F5.B10	0.F1.B10	0.F0.B10	0.F2.B10	0.F3.B10
GCLK_INT:MUX.0.LH[0]	0.F4.B5	0.F5.B5	0.F1.B5	0.F0.B5	0.F2.B5	0.F3.B5
GCLK_INT:MUX.0.LH[3]	0.F4.B1	0.F5.B1	0.F1.B1	0.F0.B1	0.F2.B1	0.F3.B1
GCLK_INT:MUX.0.LH[6]	0.F4.B8	0.F5.B8	0.F1.B8	0.F0.B8	0.F2.B8	0.F3.B8
GCLK_INT:MUX.0.LH[9]	0.F4.B9	0.F5.B9	0.F1.B9	0.F0.B9	0.F2.B9	0.F3.B9
0.OUT_CLKPAD[0]	0	0	0	0	1	1
1.OUT_DLL_CLK2X90	0	0	0	1	0	1
0.OUT_BUFGCE_O[0]	0	0	0	1	1	1
1.OUT_DLL_CLK90	0	0	1	0	0	1
1.OUT_DLL_CLKDV	0	0	1	0	1	1
2.OUT_DLL_CLK180	0	0	1	1	0	1
3.OUT_DLL_CLK2X	0	1	0	0	1	0
2.OUT_DLL_CLK270	0	1	0	0	1	1
3.OUT_DLL_CLKDV	0	1	0	1	0	0
2.OUT_DLL_CLK2X90	0	1	0	1	0	1
4.OUT_DLL_CLK180	0	1	0	1	1	0
1.OUT_DLL_CLK180	0	1	0	1	1	1
3.OUT_DLL_CLK270	0	1	1	0	0	0
2.OUT_DLL_CLK2X	0	1	1	0	0	1
3.OUT_DLL_CLK90	0	1	1	0	1	0
0.OUT_BUFGCE_O[1]	0	1	1	0	1	1
4.OUT_DLL_CLK270	0	1	1	1	0	0
1.OUT_DLL_CLK0	0	1	1	1	0	1
4.OUT_DLL_CLK2X	1	0	0	0	1	0
2.OUT_DLL_CLK90	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	1	0	0
0.OUT_CLKPAD[1]	1	0	0	1	0	1
3.OUT_DLL_CLK180	1	0	0	1	1	0
2.OUT_DLL_CLK0	1	0	0	1	1	1
4.OUT_DLL_CLK90	1	0	1	0	0	0
1.OUT_DLL_LOCKED	1	0	1	0	0	1
4.OUT_DLL_CLK2X90	1	0	1	0	1	0
2.OUT_DLL_LOCKED	1	0	1	0	1	1
3.OUT_DLL_CLK0	1	0	1	1	0	0
2.OUT_DLL_CLKDV	1	0	1	1	0	1
4.OUT_DLL_LOCKED	1	1	0	0	1	0
4.OUT_DLL_CLKDV	1	1	0	1	0	0
1.OUT_DLL_CLK2X	1	1	0	1	1	0
3.OUT_DLL_LOCKED	1	1	1	0	0	0
4.OUT_DLL_CLK0	1	1	1	0	1	0
1.OUT_DLL_CLK270	1	1	1	1	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0]	0.F5.B4	0.F3.B4	0.F2.B4	0.F1.B4	0.F0.B4	0.F7.B7	0.F6.B7
GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1]	0.F4.B4	0.F5.B7	0.F4.B7	0.F3.B7	0.F2.B7	0.F1.B7	0.F0.B7
NONE	0	0	0	0	0	0	0
0.HEX_H1[2]	0	0	0	0	0	0	1
0.HEX_H2[2]	0	0	0	0	0	1	0
0.HEX_H3[2]	0	0	0	0	1	0	0
0.HEX_H4[2]	0	0	0	1	0	0	0
0.HEX_H5[2]	0	0	1	0	0	0	0
0.HEX_H6[2]	0	1	0	0	0	0	0
0.HEX_H1[3]	1	0	0	0	0	0	1
0.HEX_H2[3]	1	0	0	0	0	1	0
0.HEX_H3[3]	1	0	0	0	1	0	0
0.HEX_H4[3]	1	0	0	1	0	0	0
0.HEX_H5[3]	1	0	1	0	0	0	0
0.HEX_H6[3]	1	1	0	0	0	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0]	0.F7.B0	0.F1.B2	0.F4.B2	0.F5.B2	0.F6.B2	0.F3.B2	0.F2.B2	0.F0.B2	0.F6.B0	0.F6.B3	0.F4.B6
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	0	1	1
1.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	0	1	0
2.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	1	1	0
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1	1
1.OUT_DLL_CLK90	0	0	0	0	0	0	1	0	0	1	0
0.HEX_H1[1]	0	0	0	0	0	0	1	0	0	1	1
1.OUT_DLL_CLKDV	0	0	0	0	0	0	1	0	1	1	0
0.HEX_H6[0]	0	0	0	0	0	0	1	0	1	1	1
2.OUT_DLL_CLK180	0	0	0	0	0	1	0	0	0	1	0
0.HEX_H5[1]	0	0	0	0	0	1	0	0	0	1	1
2.OUT_DLL_CLK2X	0	0	0	0	0	1	0	0	1	1	0
0.HEX_H2[0]	0	0	0	0	0	1	0	0	1	1	1
1.OUT_DLL_CLK2X	0	0	0	0	1	0	0	0	0	1	0
0.HEX_H2[1]	0	0	0	0	1	0	0	0	0	1	1
1.OUT_DLL_CLK0	0	0	0	0	1	0	0	0	1	1	0
0.HEX_H3[0]	0	0	0	0	1	0	0	0	1	1	1
1.OUT_DLL_CLK2X90	0	0	0	1	0	0	0	0	0	1	0
0.HEX_H3[1]	0	0	0	1	0	0	0	0	0	1	1
2.OUT_DLL_CLK0	0	0	0	1	0	0	0	0	1	1	0
0.HEX_H4[0]	0	0	0	1	0	0	0	0	1	1	1
2.OUT_DLL_CLK2X90	0	0	1	0	0	0	0	0	0	1	0
0.HEX_H4[1]	0	0	1	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK90	0	0	1	0	0	0	0	0	1	1	0
0.HEX_H5[0]	0	0	1	0	0	0	0	0	1	1	1
1.OUT_DLL_CLK180	0	1	0	0	0	0	0	0	0	1	0
0.HEX_H6[1]	0	1	0	0	0	0	0	0	0	1	1
2.OUT_DLL_CLKDV	0	1	0	0	0	0	0	0	1	1	0
3.OUT_DLL_CLK270	1	0	0	0	0	0	0	1	0	1	0
4.OUT_DLL_CLK180	1	0	0	0	0	0	0	1	0	1	1
3.OUT_DLL_CLK90	1	0	0	0	0	0	1	0	0	1	0
4.OUT_DLL_CLKDV	1	0	0	0	0	0	1	0	0	1	1
3.OUT_DLL_CLKDV	1	0	0	0	0	1	0	0	0	1	0
4.OUT_DLL_CLK2X90	1	0	0	0	0	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	0	1	0	0	0	0	1	0
4.OUT_DLL_CLK0	1	0	0	0	1	0	0	0	0	1	1
3.OUT_DLL_CLK0	1	0	0	1	0	0	0	0	0	1	0
4.OUT_DLL_CLK90	1	0	0	1	0	0	0	0	0	1	1
3.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK180	1	1	0	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK270	1	1	0	0	0	0	0	0	0	1	1

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1]	0.F6.B1	0.F0.B0	0.F3.B0	0.F4.B0	0.F5.B0	0.F2.B0	0.F1.B0	0.F7.B2	0.F6.B5	0.F7.B3	0.F5.B6
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	0	1	1
1.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	0	1	0
2.OUT_DLL_CLK270	0	0	0	0	0	0	0	1	1	1	0
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1	1
1.OUT_DLL_CLK90	0	0	0	0	0	0	1	0	0	1	0
0.HEX_H1[1]	0	0	0	0	0	0	1	0	0	1	1
1.OUT_DLL_CLKDV	0	0	0	0	0	0	1	0	1	1	0
0.HEX_H6[0]	0	0	0	0	0	0	1	0	1	1	1
2.OUT_DLL_CLK180	0	0	0	0	0	1	0	0	0	1	0
0.HEX_H5[1]	0	0	0	0	0	1	0	0	0	1	1
2.OUT_DLL_CLK2X	0	0	0	0	0	1	0	0	1	1	0
0.HEX_H2[0]	0	0	0	0	0	1	0	0	1	1	1
1.OUT_DLL_CLK2X	0	0	0	0	1	0	0	0	0	1	0
0.HEX_H2[1]	0	0	0	0	1	0	0	0	0	1	1
1.OUT_DLL_CLK0	0	0	0	0	1	0	0	0	1	1	0
0.HEX_H3[0]	0	0	0	0	1	0	0	0	1	1	1
1.OUT_DLL_CLK2X90	0	0	0	1	0	0	0	0	0	1	0
0.HEX_H3[1]	0	0	0	1	0	0	0	0	0	1	1
2.OUT_DLL_CLK0	0	0	0	1	0	0	0	0	1	1	0
0.HEX_H4[0]	0	0	0	1	0	0	0	0	1	1	1
2.OUT_DLL_CLK2X90	0	0	1	0	0	0	0	0	0	1	0
0.HEX_H4[1]	0	0	1	0	0	0	0	0	0	1	1
2.OUT_DLL_CLK90	0	0	1	0	0	0	0	0	1	1	0
0.HEX_H5[0]	0	0	1	0	0	0	0	0	1	1	1
1.OUT_DLL_CLK180	0	1	0	0	0	0	0	0	0	1	0
0.HEX_H6[1]	0	1	0	0	0	0	0	0	0	1	1
2.OUT_DLL_CLKDV	0	1	0	0	0	0	0	0	1	1	0
3.OUT_DLL_CLK270	1	0	0	0	0	0	0	1	0	1	0
4.OUT_DLL_CLK180	1	0	0	0	0	0	0	1	0	1	1
3.OUT_DLL_CLK90	1	0	0	0	0	0	1	0	0	1	0
4.OUT_DLL_CLKDV	1	0	0	0	0	0	1	0	0	1	1
3.OUT_DLL_CLKDV	1	0	0	0	0	1	0	0	0	1	0
4.OUT_DLL_CLK2X90	1	0	0	0	0	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	0	1	0	0	0	0	1	0
4.OUT_DLL_CLK0	1	0	0	0	1	0	0	0	0	1	1
3.OUT_DLL_CLK0	1	0	0	1	0	0	0	0	0	1	0
4.OUT_DLL_CLK90	1	0	0	1	0	0	0	0	0	1	1
3.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK180	1	1	0	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK270	1	1	0	0	0	0	0	0	0	1	1

GCLK_IO[0]:DELAY	0.F4.B3	0.F3.B3	0.F2.B3	0.F1.B3	0.F0.B3
GCLK_IO[1]:DELAY	0.F6.B6	0.F7.B6	0.F1.B6	0.F0.B6	0.F5.B3
non-inverted	[4]	[3]	[2]	[1]	[0]

GCLK_IO[0]:IBUF	1.F1.B16	1.F0.B16
GCLK_IO[1]:IBUF	1.F1.B17	1.F0.B17
CMOS	0	0
VREF	0	1
DIFF	1	0
NONE	1	1

IOFB[0]:IBUF	1.F2.B16	1.F3.B16
IOFB[1]:IBUF	1.F2.B17	1.F3.B17
CMOS	0	1
VREF	1	0
NONE	1	1

Tile CLK_N_VE_2DLL

Cells: 5

Switchbox GCLK_INT

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes HEX_H1[0]
Bits	Destination
CELL.HEX_H1[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes HEX_H1[1]
Bits	Destination
CELL.HEX_H1[1]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes HEX_H1[2]
Bits	Destination
CELL.HEX_H1[2]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes HEX_H1[3]
Bits	Destination
CELL.HEX_H1[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes HEX_H6[0]
Bits	Destination
CELL.HEX_H6[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes HEX_H6[1]
Bits	Destination
CELL.HEX_H6[1]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes HEX_H6[2]
Bits	Destination
CELL.HEX_H6[2]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes HEX_H6[3]
Bits	Destination
CELL.HEX_H6[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes LH[0]
Bits	Destination
CELL.LH[0]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes LH[3]
Bits	Destination
CELL.LH[3]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes LH[6]
Bits	Destination
CELL.LH[6]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes LH[9]
Bits	Destination
CELL.LH[9]
	Source
DLLS_E.OUT_DLL_LOCKED

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[0]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[0]
	Source
DLLS_E.OUT_DLL_CLKDV

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CLK[1]
Bits	Destination
CELL.IMUX_BUFGCE_CLK[1]
	Source
DLLS_E.OUT_DLL_CLKDV

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CE[0]
Bits	Destination
CELL.IMUX_BUFGCE_CE[0]
	Source
CELL.HEX_H6[3]

virtex CLK_N_VE_2DLL switchbox GCLK_INT muxes IMUX_BUFGCE_CE[1]
Bits	Destination
CELL.IMUX_BUFGCE_CE[1]
	Source
CELL.HEX_H6[3]

Bel GCLK_IO[0]

virtex CLK_N_VE_2DLL bel GCLK_IO[0]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[0]

Bel GCLK_IO[1]

virtex CLK_N_VE_2DLL bel GCLK_IO[1]
Pin	Direction	Wires
GCLKOUT	output	CELL.OUT_CLKPAD[1]

Bel BUFG[0]

virtex CLK_N_VE_2DLL bel BUFG[0]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[0]
IN	input	CELL.IMUX_BUFGCE_CLK[0]
OUT	output	CELL.OUT_BUFGCE_O[0]

Bel BUFG[1]

virtex CLK_N_VE_2DLL bel BUFG[1]
Pin	Direction	Wires
CE	input	CELL.IMUX_BUFGCE_CE[1]
IN	input	CELL.IMUX_BUFGCE_CLK[1]
OUT	output	CELL.OUT_BUFGCE_O[1]

Bel IOFB[0]

virtex CLK_N_VE_2DLL bel IOFB[0]
Pin	Direction	Wires
O	output	CELL.OUT_IOFB[0]

Bel IOFB[1]

virtex CLK_N_VE_2DLL bel IOFB[1]
Pin	Direction	Wires
O	output	CELL.OUT_IOFB[1]

Bel wires

virtex CLK_N_VE_2DLL bel wires
Wire	Pins
CELL.IMUX_BUFGCE_CLK[0]	BUFG[0].IN
CELL.IMUX_BUFGCE_CLK[1]	BUFG[1].IN
CELL.IMUX_BUFGCE_CE[0]	BUFG[0].CE
CELL.IMUX_BUFGCE_CE[1]	BUFG[1].CE
CELL.OUT_BUFGCE_O[0]	BUFG[0].OUT
CELL.OUT_BUFGCE_O[1]	BUFG[1].OUT
CELL.OUT_CLKPAD[0]	GCLK_IO[0].GCLKOUT
CELL.OUT_CLKPAD[1]	GCLK_IO[1].GCLKOUT
CELL.OUT_IOFB[0]	IOFB[0].O
CELL.OUT_IOFB[1]	IOFB[1].O

Bitstream

virtex CLK_N_VE_2DLL rect CLK[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

virtex CLK_N_VE_2DLL rect CLK[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-

### Bitstream

virtex CLK_N_VE_2DLL rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7
B17	GCLK_INT:MUX.0.HEX_H1[0][2]	GCLK_INT:MUX.0.HEX_H1[0][3]	GCLK_INT:MUX.0.HEX_H1[0][1]	GCLK_INT:MUX.0.HEX_H1[0][0]	GCLK_INT:MUX.0.HEX_H1[0][5]	GCLK_INT:MUX.0.HEX_H1[0][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[0]
B16	GCLK_INT:MUX.0.HEX_H1[1][2]	GCLK_INT:MUX.0.HEX_H1[1][3]	GCLK_INT:MUX.0.HEX_H1[1][1]	GCLK_INT:MUX.0.HEX_H1[1][0]	GCLK_INT:MUX.0.HEX_H1[1][5]	GCLK_INT:MUX.0.HEX_H1[1][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[1]
B15	GCLK_INT:MUX.0.HEX_H1[2][2]	GCLK_INT:MUX.0.HEX_H1[2][3]	GCLK_INT:MUX.0.HEX_H1[2][1]	GCLK_INT:MUX.0.HEX_H1[2][0]	GCLK_INT:MUX.0.HEX_H1[2][5]	GCLK_INT:MUX.0.HEX_H1[2][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[2]
B14	GCLK_INT:MUX.0.HEX_H1[3][2]	GCLK_INT:MUX.0.HEX_H1[3][3]	GCLK_INT:MUX.0.HEX_H1[3][1]	GCLK_INT:MUX.0.HEX_H1[3][0]	GCLK_INT:MUX.0.HEX_H1[3][5]	GCLK_INT:MUX.0.HEX_H1[3][4]	-	~GCLK_INT:DRIVE.0.HEX_H1[3]
B13	GCLK_INT:MUX.0.HEX_H6[0][2]	GCLK_INT:MUX.0.HEX_H6[0][3]	GCLK_INT:MUX.0.HEX_H6[0][1]	GCLK_INT:MUX.0.HEX_H6[0][0]	GCLK_INT:MUX.0.HEX_H6[0][5]	GCLK_INT:MUX.0.HEX_H6[0][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[0]
B12	GCLK_INT:MUX.0.HEX_H6[1][2]	GCLK_INT:MUX.0.HEX_H6[1][3]	GCLK_INT:MUX.0.HEX_H6[1][1]	GCLK_INT:MUX.0.HEX_H6[1][0]	GCLK_INT:MUX.0.HEX_H6[1][5]	GCLK_INT:MUX.0.HEX_H6[1][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[1]
B11	GCLK_INT:MUX.0.HEX_H6[2][2]	GCLK_INT:MUX.0.HEX_H6[2][3]	GCLK_INT:MUX.0.HEX_H6[2][1]	GCLK_INT:MUX.0.HEX_H6[2][0]	GCLK_INT:MUX.0.HEX_H6[2][5]	GCLK_INT:MUX.0.HEX_H6[2][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[2]
B10	GCLK_INT:MUX.0.HEX_H6[3][2]	GCLK_INT:MUX.0.HEX_H6[3][3]	GCLK_INT:MUX.0.HEX_H6[3][1]	GCLK_INT:MUX.0.HEX_H6[3][0]	GCLK_INT:MUX.0.HEX_H6[3][5]	GCLK_INT:MUX.0.HEX_H6[3][4]	-	~GCLK_INT:DRIVE.0.HEX_H6[3]
B9	GCLK_INT:MUX.0.LH[9][2]	GCLK_INT:MUX.0.LH[9][3]	GCLK_INT:MUX.0.LH[9][1]	GCLK_INT:MUX.0.LH[9][0]	GCLK_INT:MUX.0.LH[9][5]	GCLK_INT:MUX.0.LH[9][4]	-	GCLK_INT:DRIVE.0.LH[9]
B8	GCLK_INT:MUX.0.LH[6][2]	GCLK_INT:MUX.0.LH[6][3]	GCLK_INT:MUX.0.LH[6][1]	GCLK_INT:MUX.0.LH[6][0]	GCLK_INT:MUX.0.LH[6][5]	GCLK_INT:MUX.0.LH[6][4]	-	GCLK_INT:DRIVE.0.LH[6]
B7	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][1]
B6	GCLK_IO[1]:DELAY[1]	GCLK_IO[1]:DELAY[2]	BUFG[0]:DISABLE_ATTR	BUFG[1]:DISABLE_ATTR	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][0]	GCLK_IO[1]:DELAY[4]	GCLK_IO[1]:DELAY[3]
B5	GCLK_INT:MUX.0.LH[0][2]	GCLK_INT:MUX.0.LH[0][3]	GCLK_INT:MUX.0.LH[0][1]	GCLK_INT:MUX.0.LH[0][0]	GCLK_INT:MUX.0.LH[0][5]	GCLK_INT:MUX.0.LH[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][2]	GCLK_INT:DRIVE.0.LH[0]
B4	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0][6]	GCLK_INT:INV.IMUX_BUFGCE_CE[0]	GCLK_INT:INV.IMUX_BUFGCE_CE[1]
B3	GCLK_IO[0]:DELAY[0]	GCLK_IO[0]:DELAY[1]	GCLK_IO[0]:DELAY[2]	GCLK_IO[0]:DELAY[3]	GCLK_IO[0]:DELAY[4]	GCLK_IO[1]:DELAY[0]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][1]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][1]
B2	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][3]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][3]
B1	GCLK_INT:MUX.0.LH[3][2]	GCLK_INT:MUX.0.LH[3][3]	GCLK_INT:MUX.0.LH[3][1]	GCLK_INT:MUX.0.LH[3][0]	GCLK_INT:MUX.0.LH[3][5]	GCLK_INT:MUX.0.LH[3][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][10]	GCLK_INT:DRIVE.0.LH[3]
B0	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][9]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][4]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][5]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][8]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][7]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1][6]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][2]	GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0][10]

virtex CLK_N_VE_2DLL rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B17	GCLK_IO[1]:IBUF[0]	GCLK_IO[1]:IBUF[1]	IOFB[1]:IBUF[1]	IOFB[1]:IBUF[0]
B16	GCLK_IO[0]:IBUF[0]	GCLK_IO[0]:IBUF[1]	IOFB[0]:IBUF[1]	IOFB[0]:IBUF[0]
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

BUFG[0]:DISABLE_ATTR	0.F2.B6
BUFG[1]:DISABLE_ATTR	0.F3.B6
GCLK_INT:DRIVE.0.LH[0]	0.F7.B5
GCLK_INT:DRIVE.0.LH[3]	0.F7.B1
GCLK_INT:DRIVE.0.LH[6]	0.F7.B8
GCLK_INT:DRIVE.0.LH[9]	0.F7.B9
GCLK_INT:INV.IMUX_BUFGCE_CE[0]	0.F6.B4
GCLK_INT:INV.IMUX_BUFGCE_CE[1]	0.F7.B4
non-inverted	[0]

GCLK_INT:DRIVE.0.HEX_H1[0]	0.F7.B17
GCLK_INT:DRIVE.0.HEX_H1[1]	0.F7.B16
GCLK_INT:DRIVE.0.HEX_H1[2]	0.F7.B15
GCLK_INT:DRIVE.0.HEX_H1[3]	0.F7.B14
GCLK_INT:DRIVE.0.HEX_H6[0]	0.F7.B13
GCLK_INT:DRIVE.0.HEX_H6[1]	0.F7.B12
GCLK_INT:DRIVE.0.HEX_H6[2]	0.F7.B11
GCLK_INT:DRIVE.0.HEX_H6[3]	0.F7.B10
inverted	~[0]

GCLK_INT:MUX.0.HEX_H1[0]	0.F4.B17	0.F5.B17	0.F1.B17	0.F0.B17	0.F2.B17	0.F3.B17
GCLK_INT:MUX.0.HEX_H1[1]	0.F4.B16	0.F5.B16	0.F1.B16	0.F0.B16	0.F2.B16	0.F3.B16
GCLK_INT:MUX.0.HEX_H1[2]	0.F4.B15	0.F5.B15	0.F1.B15	0.F0.B15	0.F2.B15	0.F3.B15
GCLK_INT:MUX.0.HEX_H1[3]	0.F4.B14	0.F5.B14	0.F1.B14	0.F0.B14	0.F2.B14	0.F3.B14
GCLK_INT:MUX.0.HEX_H6[0]	0.F4.B13	0.F5.B13	0.F1.B13	0.F0.B13	0.F2.B13	0.F3.B13
GCLK_INT:MUX.0.HEX_H6[1]	0.F4.B12	0.F5.B12	0.F1.B12	0.F0.B12	0.F2.B12	0.F3.B12
GCLK_INT:MUX.0.HEX_H6[2]	0.F4.B11	0.F5.B11	0.F1.B11	0.F0.B11	0.F2.B11	0.F3.B11
GCLK_INT:MUX.0.HEX_H6[3]	0.F4.B10	0.F5.B10	0.F1.B10	0.F0.B10	0.F2.B10	0.F3.B10
GCLK_INT:MUX.0.LH[0]	0.F4.B5	0.F5.B5	0.F1.B5	0.F0.B5	0.F2.B5	0.F3.B5
GCLK_INT:MUX.0.LH[3]	0.F4.B1	0.F5.B1	0.F1.B1	0.F0.B1	0.F2.B1	0.F3.B1
GCLK_INT:MUX.0.LH[6]	0.F4.B8	0.F5.B8	0.F1.B8	0.F0.B8	0.F2.B8	0.F3.B8
GCLK_INT:MUX.0.LH[9]	0.F4.B9	0.F5.B9	0.F1.B9	0.F0.B9	0.F2.B9	0.F3.B9
0.OUT_CLKPAD[0]	0	0	0	0	1	1
0.OUT_BUFGCE_O[0]	0	0	0	1	1	1
3.OUT_DLL_CLK2X	0	1	0	0	1	0
3.OUT_DLL_CLKDV	0	1	0	1	0	0
4.OUT_DLL_CLK180	0	1	0	1	1	0
3.OUT_DLL_CLK270	0	1	1	0	0	0
3.OUT_DLL_CLK90	0	1	1	0	1	0
0.OUT_BUFGCE_O[1]	0	1	1	0	1	1
4.OUT_DLL_CLK270	0	1	1	1	0	0
4.OUT_DLL_CLK2X	1	0	0	0	1	0
3.OUT_DLL_CLK2X90	1	0	0	1	0	0
0.OUT_CLKPAD[1]	1	0	0	1	0	1
3.OUT_DLL_CLK180	1	0	0	1	1	0
4.OUT_DLL_CLK90	1	0	1	0	0	0
4.OUT_DLL_CLK2X90	1	0	1	0	1	0
3.OUT_DLL_CLK0	1	0	1	1	0	0
4.OUT_DLL_LOCKED	1	1	0	0	1	0
4.OUT_DLL_CLKDV	1	1	0	1	0	0
3.OUT_DLL_LOCKED	1	1	1	0	0	0
4.OUT_DLL_CLK0	1	1	1	0	1	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CE[0]	0.F5.B4	0.F3.B4	0.F2.B4	0.F1.B4	0.F0.B4	0.F7.B7	0.F6.B7
GCLK_INT:MUX.0.IMUX_BUFGCE_CE[1]	0.F4.B4	0.F5.B7	0.F4.B7	0.F3.B7	0.F2.B7	0.F1.B7	0.F0.B7
NONE	0	0	0	0	0	0	0
0.HEX_H1[2]	0	0	0	0	0	0	1
0.HEX_H2[2]	0	0	0	0	0	1	0
0.HEX_H3[2]	0	0	0	0	1	0	0
0.HEX_H4[2]	0	0	0	1	0	0	0
0.HEX_H5[2]	0	0	1	0	0	0	0
0.HEX_H6[2]	0	1	0	0	0	0	0
0.HEX_H1[3]	1	0	0	0	0	0	1
0.HEX_H2[3]	1	0	0	0	0	1	0
0.HEX_H3[3]	1	0	0	0	1	0	0
0.HEX_H4[3]	1	0	0	1	0	0	0
0.HEX_H5[3]	1	0	1	0	0	0	0
0.HEX_H6[3]	1	1	0	0	0	0	0

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[0]	0.F7.B0	0.F1.B2	0.F4.B2	0.F5.B2	0.F6.B2	0.F3.B2	0.F2.B2	0.F0.B2	0.F6.B0	0.F6.B3	0.F4.B6
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	0	1	1
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1	1
0.HEX_H1[1]	0	0	0	0	0	0	1	0	0	1	1
0.HEX_H6[0]	0	0	0	0	0	0	1	0	1	1	1
0.HEX_H5[1]	0	0	0	0	0	1	0	0	0	1	1
0.HEX_H2[0]	0	0	0	0	0	1	0	0	1	1	1
0.HEX_H2[1]	0	0	0	0	1	0	0	0	0	1	1
0.HEX_H3[0]	0	0	0	0	1	0	0	0	1	1	1
0.HEX_H3[1]	0	0	0	1	0	0	0	0	0	1	1
0.HEX_H4[0]	0	0	0	1	0	0	0	0	1	1	1
0.HEX_H4[1]	0	0	1	0	0	0	0	0	0	1	1
0.HEX_H5[0]	0	0	1	0	0	0	0	0	1	1	1
0.HEX_H6[1]	0	1	0	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK270	1	0	0	0	0	0	0	1	0	1	0
4.OUT_DLL_CLK180	1	0	0	0	0	0	0	1	0	1	1
3.OUT_DLL_CLK90	1	0	0	0	0	0	1	0	0	1	0
4.OUT_DLL_CLKDV	1	0	0	0	0	0	1	0	0	1	1
3.OUT_DLL_CLKDV	1	0	0	0	0	1	0	0	0	1	0
4.OUT_DLL_CLK2X90	1	0	0	0	0	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	0	1	0	0	0	0	1	0
4.OUT_DLL_CLK0	1	0	0	0	1	0	0	0	0	1	1
3.OUT_DLL_CLK0	1	0	0	1	0	0	0	0	0	1	0
4.OUT_DLL_CLK90	1	0	0	1	0	0	0	0	0	1	1
3.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK180	1	1	0	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK270	1	1	0	0	0	0	0	0	0	1	1

GCLK_INT:MUX.0.IMUX_BUFGCE_CLK[1]	0.F6.B1	0.F0.B0	0.F3.B0	0.F4.B0	0.F5.B0	0.F2.B0	0.F1.B0	0.F7.B2	0.F6.B5	0.F7.B3	0.F5.B6
0.OUT_CLKPAD[0]	0	0	0	0	0	0	0	0	0	0	0
0.OUT_CLKPAD[1]	0	0	0	0	0	0	0	0	0	0	1
NONE	0	0	0	0	0	0	0	0	0	1	1
0.HEX_H1[0]	0	0	0	0	0	0	0	1	1	1	1
0.HEX_H1[1]	0	0	0	0	0	0	1	0	0	1	1
0.HEX_H6[0]	0	0	0	0	0	0	1	0	1	1	1
0.HEX_H5[1]	0	0	0	0	0	1	0	0	0	1	1
0.HEX_H2[0]	0	0	0	0	0	1	0	0	1	1	1
0.HEX_H2[1]	0	0	0	0	1	0	0	0	0	1	1
0.HEX_H3[0]	0	0	0	0	1	0	0	0	1	1	1
0.HEX_H3[1]	0	0	0	1	0	0	0	0	0	1	1
0.HEX_H4[0]	0	0	0	1	0	0	0	0	1	1	1
0.HEX_H4[1]	0	0	1	0	0	0	0	0	0	1	1
0.HEX_H5[0]	0	0	1	0	0	0	0	0	1	1	1
0.HEX_H6[1]	0	1	0	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK270	1	0	0	0	0	0	0	1	0	1	0
4.OUT_DLL_CLK180	1	0	0	0	0	0	0	1	0	1	1
3.OUT_DLL_CLK90	1	0	0	0	0	0	1	0	0	1	0
4.OUT_DLL_CLKDV	1	0	0	0	0	0	1	0	0	1	1
3.OUT_DLL_CLKDV	1	0	0	0	0	1	0	0	0	1	0
4.OUT_DLL_CLK2X90	1	0	0	0	0	1	0	0	0	1	1
3.OUT_DLL_CLK2X90	1	0	0	0	1	0	0	0	0	1	0
4.OUT_DLL_CLK0	1	0	0	0	1	0	0	0	0	1	1
3.OUT_DLL_CLK0	1	0	0	1	0	0	0	0	0	1	0
4.OUT_DLL_CLK90	1	0	0	1	0	0	0	0	0	1	1
3.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK2X	1	0	1	0	0	0	0	0	0	1	1
3.OUT_DLL_CLK180	1	1	0	0	0	0	0	0	0	1	0
4.OUT_DLL_CLK270	1	1	0	0	0	0	0	0	0	1	1

GCLK_IO[0]:DELAY	0.F4.B3	0.F3.B3	0.F2.B3	0.F1.B3	0.F0.B3
GCLK_IO[1]:DELAY	0.F6.B6	0.F7.B6	0.F1.B6	0.F0.B6	0.F5.B3
non-inverted	[4]	[3]	[2]	[1]	[0]

GCLK_IO[0]:IBUF	1.F1.B16	1.F0.B16
GCLK_IO[1]:IBUF	1.F1.B17	1.F0.B17
CMOS	0	0
VREF	0	1
DIFF	1	0
NONE	1	1

IOFB[0]:IBUF	1.F2.B16	1.F3.B16
IOFB[1]:IBUF	1.F2.B17	1.F3.B17
CMOS	0	1
VREF	1	0
NONE	1	1

Tile CLKV_CLKV

Cells: 2

Bel CLKV

virtex CLKV_CLKV bel CLKV
Pin	Direction	Wires
OUT_L0	output	W.GCLK[0]
OUT_L1	output	W.GCLK[1]
OUT_L2	output	W.GCLK[2]
OUT_L3	output	W.GCLK[3]
OUT_R0	output	E.GCLK[0]
OUT_R1	output	E.GCLK[1]
OUT_R2	output	E.GCLK[2]
OUT_R3	output	E.GCLK[3]

Bel wires

virtex CLKV_CLKV bel wires
Wire	Pins
W.GCLK[0]	CLKV.OUT_L0
W.GCLK[1]	CLKV.OUT_L1
W.GCLK[2]	CLKV.OUT_L2
W.GCLK[3]	CLKV.OUT_L3
E.GCLK[0]	CLKV.OUT_R0
E.GCLK[1]	CLKV.OUT_R1
E.GCLK[2]	CLKV.OUT_R2
E.GCLK[3]	CLKV.OUT_R3

Bitstream

virtex CLKV_CLKV rect CLKV
Bit	Frame
Bit	F0
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

virtex CLKV_CLKV rect R0
Bit	Frame
Bit	F0
B12	CLKV:BUF.GCLK_R2
B11	CLKV:BUF.GCLK_L2
B10	CLKV:BUF.GCLK_R3
B9	CLKV:BUF.GCLK_L3
B8	CLKV:BUF.GCLK_L0
B7	CLKV:BUF.GCLK_R1
B6	CLKV:BUF.GCLK_R0
B5	CLKV:BUF.GCLK_L1
B4	-
B3	-
B2	-
B1	-
B0	-

CLKV:BUF.GCLK_L0	0.F0.B8
CLKV:BUF.GCLK_L1	0.F0.B5
CLKV:BUF.GCLK_L2	0.F0.B11
CLKV:BUF.GCLK_L3	0.F0.B9
CLKV:BUF.GCLK_R0	0.F0.B6
CLKV:BUF.GCLK_R1	0.F0.B7
CLKV:BUF.GCLK_R2	0.F0.B12
CLKV:BUF.GCLK_R3	0.F0.B10
non-inverted	[0]

Tile CLKV_GCLKV

Cells: 2

Bel CLKV

virtex CLKV_GCLKV bel CLKV
Pin	Direction	Wires
OUT_L0	output	W.GCLK[0]
OUT_L1	output	W.GCLK[1]
OUT_L2	output	W.GCLK[2]
OUT_L3	output	W.GCLK[3]
OUT_R0	output	E.GCLK[0]
OUT_R1	output	E.GCLK[1]
OUT_R2	output	E.GCLK[2]
OUT_R3	output	E.GCLK[3]

Bel wires

virtex CLKV_GCLKV bel wires
Wire	Pins
W.GCLK[0]	CLKV.OUT_L0
W.GCLK[1]	CLKV.OUT_L1
W.GCLK[2]	CLKV.OUT_L2
W.GCLK[3]	CLKV.OUT_L3
E.GCLK[0]	CLKV.OUT_R0
E.GCLK[1]	CLKV.OUT_R1
E.GCLK[2]	CLKV.OUT_R2
E.GCLK[3]	CLKV.OUT_R3

Bitstream

virtex CLKV_GCLKV rect CLKV
Bit	Frame
Bit	F0
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

virtex CLKV_GCLKV rect R0
Bit	Frame
Bit	F0
B12	CLKV:BUF.GCLK_R3
B11	CLKV:BUF.GCLK_L3
B10	CLKV:BUF.GCLK_R2
B9	CLKV:BUF.GCLK_L2
B8	CLKV:BUF.GCLK_R1
B7	CLKV:BUF.GCLK_L1
B6	CLKV:BUF.GCLK_R0
B5	CLKV:BUF.GCLK_L0
B4	-
B3	-
B2	-
B1	-
B0	-

CLKV:BUF.GCLK_L0	0.F0.B5
CLKV:BUF.GCLK_L1	0.F0.B7
CLKV:BUF.GCLK_L2	0.F0.B9
CLKV:BUF.GCLK_L3	0.F0.B11
CLKV:BUF.GCLK_R0	0.F0.B6
CLKV:BUF.GCLK_R1	0.F0.B8
CLKV:BUF.GCLK_R2	0.F0.B10
CLKV:BUF.GCLK_R3	0.F0.B12
non-inverted	[0]

Tile CLKV_BRAM_S

Cells: 3

Bel CLKV_BRAM_S

virtex CLKV_BRAM_S bel CLKV_BRAM_S
Pin	Direction	Wires
IN0	input	BRAM.GCLK[0]
IN1	input	BRAM.GCLK[1]
IN2	input	BRAM.GCLK[2]
IN3	input	BRAM.GCLK[3]
OUT_L0	output	W.GCLK[0]
OUT_L1	output	W.GCLK[1]
OUT_L2	output	W.GCLK[2]
OUT_L3	output	W.GCLK[3]
OUT_R0	output	CELL.GCLK[0]
OUT_R1	output	CELL.GCLK[1]
OUT_R2	output	CELL.GCLK[2]
OUT_R3	output	CELL.GCLK[3]

Bel wires

virtex CLKV_BRAM_S bel wires
Wire	Pins
CELL.GCLK[0]	CLKV_BRAM_S.OUT_R0
CELL.GCLK[1]	CLKV_BRAM_S.OUT_R1
CELL.GCLK[2]	CLKV_BRAM_S.OUT_R2
CELL.GCLK[3]	CLKV_BRAM_S.OUT_R3
W.GCLK[0]	CLKV_BRAM_S.OUT_L0
W.GCLK[1]	CLKV_BRAM_S.OUT_L1
W.GCLK[2]	CLKV_BRAM_S.OUT_L2
W.GCLK[3]	CLKV_BRAM_S.OUT_L3
BRAM.GCLK[0]	CLKV_BRAM_S.IN0
BRAM.GCLK[1]	CLKV_BRAM_S.IN1
BRAM.GCLK[2]	CLKV_BRAM_S.IN2
BRAM.GCLK[3]	CLKV_BRAM_S.IN3

Bitstream

virtex CLKV_BRAM_S rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

### Bitstream

virtex CLKV_BRAM_S rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12
B13	-	-	-	-	-	~CLKV_BRAM_S:BUF.GCLK0[0]	~CLKV_BRAM_S:BUF.GCLK1[0]	~CLKV_BRAM_S:BUF.GCLK2[0]	~CLKV_BRAM_S:BUF.GCLK3[0]	~CLKV_BRAM_S:BUF.GCLK0[1]	~CLKV_BRAM_S:BUF.GCLK1[1]	~CLKV_BRAM_S:BUF.GCLK2[1]	~CLKV_BRAM_S:BUF.GCLK3[1]
B12	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-

CLKV_BRAM_S:BUF.GCLK0	0.F9.B13	0.F5.B13
CLKV_BRAM_S:BUF.GCLK1	0.F10.B13	0.F6.B13
CLKV_BRAM_S:BUF.GCLK2	0.F11.B13	0.F7.B13
CLKV_BRAM_S:BUF.GCLK3	0.F12.B13	0.F8.B13
inverted	~[1]	~[0]

Tile CLKV_BRAM_N

Cells: 3

Bel CLKV_BRAM_N

virtex CLKV_BRAM_N bel CLKV_BRAM_N
Pin	Direction	Wires
IN0	input	BRAM.GCLK[0]
IN1	input	BRAM.GCLK[1]
IN2	input	BRAM.GCLK[2]
IN3	input	BRAM.GCLK[3]
OUT_L0	output	W.GCLK[0]
OUT_L1	output	W.GCLK[1]
OUT_L2	output	W.GCLK[2]
OUT_L3	output	W.GCLK[3]
OUT_R0	output	CELL.GCLK[0]
OUT_R1	output	CELL.GCLK[1]
OUT_R2	output	CELL.GCLK[2]
OUT_R3	output	CELL.GCLK[3]

Bel wires

virtex CLKV_BRAM_N bel wires
Wire	Pins
CELL.GCLK[0]	CLKV_BRAM_N.OUT_R0
CELL.GCLK[1]	CLKV_BRAM_N.OUT_R1
CELL.GCLK[2]	CLKV_BRAM_N.OUT_R2
CELL.GCLK[3]	CLKV_BRAM_N.OUT_R3
W.GCLK[0]	CLKV_BRAM_N.OUT_L0
W.GCLK[1]	CLKV_BRAM_N.OUT_L1
W.GCLK[2]	CLKV_BRAM_N.OUT_L2
W.GCLK[3]	CLKV_BRAM_N.OUT_L3
BRAM.GCLK[0]	CLKV_BRAM_N.IN0
BRAM.GCLK[1]	CLKV_BRAM_N.IN1
BRAM.GCLK[2]	CLKV_BRAM_N.IN2
BRAM.GCLK[3]	CLKV_BRAM_N.IN3

Bitstream

virtex CLKV_BRAM_N rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

### Bitstream

virtex CLKV_BRAM_N rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12
B13	-	-	-	-	-	~CLKV_BRAM_N:BUF.GCLK0[0]	~CLKV_BRAM_N:BUF.GCLK1[0]	~CLKV_BRAM_N:BUF.GCLK2[0]	~CLKV_BRAM_N:BUF.GCLK3[0]	~CLKV_BRAM_N:BUF.GCLK0[1]	~CLKV_BRAM_N:BUF.GCLK1[1]	~CLKV_BRAM_N:BUF.GCLK2[1]	~CLKV_BRAM_N:BUF.GCLK3[1]
B12	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-

CLKV_BRAM_N:BUF.GCLK0	0.F9.B13	0.F5.B13
CLKV_BRAM_N:BUF.GCLK1	0.F10.B13	0.F6.B13
CLKV_BRAM_N:BUF.GCLK2	0.F11.B13	0.F7.B13
CLKV_BRAM_N:BUF.GCLK3	0.F12.B13	0.F8.B13
inverted	~[1]	~[0]

Tile CLKV_NULL

Cells: 2

Bel CLKV

virtex CLKV_NULL bel CLKV
Pin	Direction	Wires
OUT_L0	output	W.GCLK[0]
OUT_L1	output	W.GCLK[1]
OUT_L2	output	W.GCLK[2]
OUT_L3	output	W.GCLK[3]
OUT_R0	output	E.GCLK[0]
OUT_R1	output	E.GCLK[1]
OUT_R2	output	E.GCLK[2]
OUT_R3	output	E.GCLK[3]

Bel wires

virtex CLKV_NULL bel wires
Wire	Pins
W.GCLK[0]	CLKV.OUT_L0
W.GCLK[1]	CLKV.OUT_L1
W.GCLK[2]	CLKV.OUT_L2
W.GCLK[3]	CLKV.OUT_L3
E.GCLK[0]	CLKV.OUT_R0
E.GCLK[1]	CLKV.OUT_R1
E.GCLK[2]	CLKV.OUT_R2
E.GCLK[3]	CLKV.OUT_R3

Tile CLKC

Cells: 0

Bel CLKC

virtex CLKC bel CLKC
Pin	Direction	Wires

Bel GCLKC

virtex CLKC bel GCLKC
Pin	Direction	Wires

Tile GCLKC

Cells: 0

Bel GCLKC

virtex GCLKC bel GCLKC
Pin	Direction	Wires

Tile BRAM_CLKH

Cells: 1

Bel BRAM_CLKH

virtex BRAM_CLKH bel BRAM_CLKH
Pin	Direction	Wires
OUT0	output	GCLK[0]
OUT1	output	GCLK[1]
OUT2	output	GCLK[2]
OUT3	output	GCLK[3]

Bel wires

virtex BRAM_CLKH bel wires
Wire	Pins
GCLK[0]	BRAM_CLKH.OUT0
GCLK[1]	BRAM_CLKH.OUT1
GCLK[2]	BRAM_CLKH.OUT2
GCLK[3]	BRAM_CLKH.OUT3

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