Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Clock interconnect

Tile CLK_S_V

Cells: 4

Switchbox CLK_INT

virtex CLK_S_V switchbox CLK_INT permanent buffers
DestinationSource
W.GCLK[0]E.OUT_BUFGCE_O[0]
W.GCLK[1]E.OUT_BUFGCE_O[1]
W.GCLK_LEAF[0]W.GCLK[0]
W.GCLK_LEAF[1]W.GCLK[1]
W.GCLK_LEAF[2]W.GCLK[2]
W.GCLK_LEAF[3]W.GCLK[3]
E.GCLK_LEAF[0]W.GCLK[0]
E.GCLK_LEAF[1]W.GCLK[1]
E.GCLK_LEAF[2]W.GCLK[2]
E.GCLK_LEAF[3]W.GCLK[3]
virtex CLK_S_V switchbox CLK_INT programmable buffers
DestinationSourceBit
W.HEX_H0[0]W.HEX_H0_MUX[0]!CLK[0][7][17]
W.HEX_H0[1]W.HEX_H0_MUX[1]!CLK[0][7][16]
W.HEX_H0[2]W.HEX_H0_MUX[2]!CLK[0][7][15]
W.HEX_H0[3]W.HEX_H0_MUX[3]!CLK[0][7][14]
W.HEX_H5[0]W.HEX_H5_MUX[0]!CLK[0][7][13]
W.HEX_H5[1]W.HEX_H5_MUX[1]!CLK[0][7][12]
W.HEX_H5[2]W.HEX_H5_MUX[2]!CLK[0][7][11]
W.HEX_H5[3]W.HEX_H5_MUX[3]!CLK[0][7][10]
W.LH[1]W.LH_MUX[1]CLK[0][7][5]
W.LH[4]W.LH_MUX[4]CLK[0][7][1]
W.LH[7]W.LH_MUX[7]CLK[0][7][8]
W.LH[10]W.LH_MUX[10]CLK[0][7][9]
virtex CLK_S_V switchbox CLK_INT muxes HEX_H0_MUX[0]
BitsDestination
CLK[0][5][17]CLK[0][6][17]CLK[0][4][17]CLK[0][3][17]CLK[0][2][17]CLK[0][0][17]CLK[0][1][17]W.HEX_H0_MUX[0]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_S_V switchbox CLK_INT muxes HEX_H0_MUX[1]
BitsDestination
CLK[0][5][16]CLK[0][6][16]CLK[0][4][16]CLK[0][3][16]CLK[0][2][16]CLK[0][0][16]CLK[0][1][16]W.HEX_H0_MUX[1]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_S_V switchbox CLK_INT muxes HEX_H0_MUX[2]
BitsDestination
CLK[0][5][15]CLK[0][6][15]CLK[0][4][15]CLK[0][3][15]CLK[0][2][15]CLK[0][0][15]CLK[0][1][15]W.HEX_H0_MUX[2]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_S_V switchbox CLK_INT muxes HEX_H0_MUX[3]
BitsDestination
CLK[0][5][14]CLK[0][6][14]CLK[0][4][14]CLK[0][3][14]CLK[0][2][14]CLK[0][0][14]CLK[0][1][14]W.HEX_H0_MUX[3]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_S_V switchbox CLK_INT muxes HEX_H5_MUX[0]
BitsDestination
CLK[0][5][13]CLK[0][6][13]CLK[0][4][13]CLK[0][3][13]CLK[0][2][13]CLK[0][0][13]CLK[0][1][13]W.HEX_H5_MUX[0]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_S_V switchbox CLK_INT muxes HEX_H5_MUX[1]
BitsDestination
CLK[0][5][12]CLK[0][6][12]CLK[0][4][12]CLK[0][3][12]CLK[0][2][12]CLK[0][0][12]CLK[0][1][12]W.HEX_H5_MUX[1]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_S_V switchbox CLK_INT muxes HEX_H5_MUX[2]
BitsDestination
CLK[0][5][11]CLK[0][6][11]CLK[0][4][11]CLK[0][3][11]CLK[0][2][11]CLK[0][0][11]CLK[0][1][11]W.HEX_H5_MUX[2]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_S_V switchbox CLK_INT muxes HEX_H5_MUX[3]
BitsDestination
CLK[0][5][10]CLK[0][6][10]CLK[0][4][10]CLK[0][3][10]CLK[0][2][10]CLK[0][0][10]CLK[0][1][10]W.HEX_H5_MUX[3]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_S_V switchbox CLK_INT muxes LH_MUX[1]
BitsDestination
CLK[0][5][5]CLK[0][6][5]CLK[0][1][5]CLK[0][2][5]CLK[0][3][5]CLK[0][4][5]CLK[0][0][5]W.LH_MUX[1]
Source
0000000off
0000001E.OUT_BUFGCE_O[0]
0000010E.OUT_BUFGCE_O[1]
0000100E.OUT_CLKPAD[1]
0001000DLL_W.OUT_DLL_CLK2X
0010000DLL_E.OUT_DLL_CLK2X90
0100001DLL_W.OUT_DLL_CLK180
0100010E.OUT_CLKPAD[0]
0100100DLL_E.OUT_DLL_CLK90
0101000DLL_E.OUT_DLL_LOCKED
0110000DLL_W.OUT_DLL_CLK270
1000001DLL_W.OUT_DLL_LOCKED
1000010DLL_E.OUT_DLL_CLK180
1000100DLL_W.OUT_DLL_CLK2X90
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_W.OUT_DLL_CLK90
1100001DLL_E.OUT_DLL_CLKDV
1100010DLL_E.OUT_DLL_CLK0
1100100DLL_E.OUT_DLL_CLK2X
1101000DLL_W.OUT_DLL_CLKDV
1110000DLL_E.OUT_DLL_CLK270
virtex CLK_S_V switchbox CLK_INT muxes LH_MUX[4]
BitsDestination
CLK[0][5][1]CLK[0][6][1]CLK[0][1][1]CLK[0][2][1]CLK[0][3][1]CLK[0][4][1]CLK[0][0][1]W.LH_MUX[4]
Source
0000000off
0000001E.OUT_BUFGCE_O[0]
0000010E.OUT_BUFGCE_O[1]
0000100E.OUT_CLKPAD[1]
0001000DLL_W.OUT_DLL_CLK2X
0010000DLL_E.OUT_DLL_CLK2X90
0100001DLL_W.OUT_DLL_CLK180
0100010E.OUT_CLKPAD[0]
0100100DLL_E.OUT_DLL_CLK90
0101000DLL_E.OUT_DLL_LOCKED
0110000DLL_W.OUT_DLL_CLK270
1000001DLL_W.OUT_DLL_LOCKED
1000010DLL_E.OUT_DLL_CLK180
1000100DLL_W.OUT_DLL_CLK2X90
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_W.OUT_DLL_CLK90
1100001DLL_E.OUT_DLL_CLKDV
1100010DLL_E.OUT_DLL_CLK0
1100100DLL_E.OUT_DLL_CLK2X
1101000DLL_W.OUT_DLL_CLKDV
1110000DLL_E.OUT_DLL_CLK270
virtex CLK_S_V switchbox CLK_INT muxes LH_MUX[7]
BitsDestination
CLK[0][5][8]CLK[0][6][8]CLK[0][1][8]CLK[0][2][8]CLK[0][3][8]CLK[0][4][8]CLK[0][0][8]W.LH_MUX[7]
Source
0000000off
0000001E.OUT_BUFGCE_O[0]
0000010E.OUT_BUFGCE_O[1]
0000100E.OUT_CLKPAD[1]
0001000DLL_W.OUT_DLL_CLK2X
0010000DLL_E.OUT_DLL_CLK2X90
0100001DLL_W.OUT_DLL_CLK180
0100010E.OUT_CLKPAD[0]
0100100DLL_E.OUT_DLL_CLK90
0101000DLL_E.OUT_DLL_LOCKED
0110000DLL_W.OUT_DLL_CLK270
1000001DLL_W.OUT_DLL_LOCKED
1000010DLL_E.OUT_DLL_CLK180
1000100DLL_W.OUT_DLL_CLK2X90
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_W.OUT_DLL_CLK90
1100001DLL_E.OUT_DLL_CLKDV
1100010DLL_E.OUT_DLL_CLK0
1100100DLL_E.OUT_DLL_CLK2X
1101000DLL_W.OUT_DLL_CLKDV
1110000DLL_E.OUT_DLL_CLK270
virtex CLK_S_V switchbox CLK_INT muxes LH_MUX[10]
BitsDestination
CLK[0][5][9]CLK[0][6][9]CLK[0][1][9]CLK[0][2][9]CLK[0][3][9]CLK[0][4][9]CLK[0][0][9]W.LH_MUX[10]
Source
0000000off
0000001E.OUT_BUFGCE_O[0]
0000010E.OUT_BUFGCE_O[1]
0000100E.OUT_CLKPAD[1]
0001000DLL_W.OUT_DLL_CLK2X
0010000DLL_E.OUT_DLL_CLK2X90
0100001DLL_W.OUT_DLL_CLK180
0100010E.OUT_CLKPAD[0]
0100100DLL_E.OUT_DLL_CLK90
0101000DLL_E.OUT_DLL_LOCKED
0110000DLL_W.OUT_DLL_CLK270
1000001DLL_W.OUT_DLL_LOCKED
1000010DLL_E.OUT_DLL_CLK180
1000100DLL_W.OUT_DLL_CLK2X90
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_W.OUT_DLL_CLK90
1100001DLL_E.OUT_DLL_CLKDV
1100010DLL_E.OUT_DLL_CLK0
1100100DLL_E.OUT_DLL_CLK2X
1101000DLL_W.OUT_DLL_CLKDV
1110000DLL_E.OUT_DLL_CLK270
virtex CLK_S_V switchbox CLK_INT muxes IMUX_BUFGCE_CLK[0]
BitsDestination
CLK[0][1][2]CLK[0][4][2]CLK[0][5][2]CLK[0][6][2]CLK[0][3][2]CLK[0][2][2]CLK[0][6][0]CLK[0][0][2]CLK[0][6][3]CLK[0][4][6]E.IMUX_BUFGCE_CLK[0]
Source
0000000000E.OUT_CLKPAD[1]
0000000001E.OUT_CLKPAD[0]
0000000011off
0000000110DLL_E.OUT_DLL_CLK270
0000000111W.HEX_H0[0]
0000001110DLL_W.OUT_DLL_CLK270
0000010010DLL_W.OUT_DLL_CLKDV
0000010011W.HEX_H5[0]
0000011010DLL_W.OUT_DLL_CLK90
0000011011W.HEX_H0[1]
0000100010DLL_E.OUT_DLL_CLK2X
0000100011W.HEX_H1[0]
0000101010DLL_E.OUT_DLL_CLK180
0000101011W.HEX_H4[1]
0001000010DLL_W.OUT_DLL_CLK0
0001000011E.HEX_H3[0]
0001001010DLL_W.OUT_DLL_CLK2X
0001001011W.HEX_H1[1]
0010000010DLL_E.OUT_DLL_CLK0
0010000011W.HEX_H3[0]
0010001010DLL_W.OUT_DLL_CLK2X90
0010001011E.HEX_H3[1]
0100000010DLL_E.OUT_DLL_CLK90
0100000011W.HEX_H4[0]
0100001010DLL_E.OUT_DLL_CLK2X90
0100001011W.HEX_H3[1]
1000000010DLL_E.OUT_DLL_CLKDV
1000001010DLL_W.OUT_DLL_CLK180
1000001011W.HEX_H5[1]
virtex CLK_S_V switchbox CLK_INT muxes IMUX_BUFGCE_CLK[1]
BitsDestination
CLK[0][0][0]CLK[0][3][0]CLK[0][4][0]CLK[0][5][0]CLK[0][2][0]CLK[0][1][0]CLK[0][7][0]CLK[0][7][2]CLK[0][7][3]CLK[0][5][6]E.IMUX_BUFGCE_CLK[1]
Source
0000000000E.OUT_CLKPAD[0]
0000000001E.OUT_CLKPAD[1]
0000000011off
0000000110DLL_E.OUT_DLL_CLK270
0000000111W.HEX_H0[0]
0000001110DLL_W.OUT_DLL_CLK270
0000010010DLL_W.OUT_DLL_CLKDV
0000010011W.HEX_H5[0]
0000011010DLL_W.OUT_DLL_CLK90
0000011011W.HEX_H0[1]
0000100010DLL_E.OUT_DLL_CLK2X
0000100011W.HEX_H1[0]
0000101010DLL_E.OUT_DLL_CLK180
0000101011W.HEX_H4[1]
0001000010DLL_W.OUT_DLL_CLK0
0001000011E.HEX_H3[0]
0001001010DLL_W.OUT_DLL_CLK2X
0001001011W.HEX_H1[1]
0010000010DLL_E.OUT_DLL_CLK0
0010000011W.HEX_H3[0]
0010001010DLL_W.OUT_DLL_CLK2X90
0010001011E.HEX_H3[1]
0100000010DLL_E.OUT_DLL_CLK90
0100000011W.HEX_H4[0]
0100001010DLL_E.OUT_DLL_CLK2X90
0100001011W.HEX_H3[1]
1000000010DLL_E.OUT_DLL_CLKDV
1000001010DLL_W.OUT_DLL_CLK180
1000001011W.HEX_H5[1]
virtex CLK_S_V switchbox CLK_INT muxes IMUX_BUFGCE_CE[0]
BitsDestination
CLK[0][5][4]CLK[0][0][4]CLK[0][3][4]CLK[0][2][4]CLK[0][1][4]CLK[0][7][7]CLK[0][6][7]E.IMUX_BUFGCE_CE[0]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]
virtex CLK_S_V switchbox CLK_INT muxes IMUX_BUFGCE_CE[1]
BitsDestination
CLK[0][4][4]CLK[0][2][7]CLK[0][5][7]CLK[0][4][7]CLK[0][3][7]CLK[0][1][7]CLK[0][0][7]E.IMUX_BUFGCE_CE[1]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]

Bels GCLK_IOB

virtex CLK_S_V bel GCLK_IOB pins
PinDirectionGCLK_IOB[0]GCLK_IOB[1]
IoutE.OUT_CLKPAD[0]E.OUT_CLKPAD[1]
virtex CLK_S_V bel GCLK_IOB attribute bits
AttributeGCLK_IOB[0]GCLK_IOB[1]
DELAY bit 0CLK[0][0][3]CLK[0][5][3]
DELAY bit 1CLK[0][1][3]CLK[0][0][6]
DELAY bit 2CLK[0][2][3]CLK[0][1][6]
DELAY bit 3CLK[0][3][3]CLK[0][7][6]
DELAY bit 4CLK[0][4][3]CLK[0][6][6]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_S_V enum IOB_IBUF_MODE
GCLK_IOB[0].IBUF_MODECLK[1][1][0]CLK[1][0][0]
GCLK_IOB[1].IBUF_MODECLK[1][1][2]CLK[1][0][2]
NONE11
VREF_LV01
VREF_HV10
CMOS00

Bels BUFGCE

virtex CLK_S_V bel BUFGCE pins
PinDirectionBUFGCE[0]BUFGCE[1]
IinE.IMUX_BUFGCE_CLK[0]E.IMUX_BUFGCE_CLK[1]
CEinE.IMUX_BUFGCE_CE[0] invert by CLK[0][6][4]E.IMUX_BUFGCE_CE[1] invert by CLK[0][7][4]
OoutE.OUT_BUFGCE_O[0]E.OUT_BUFGCE_O[1]
virtex CLK_S_V bel BUFGCE attribute bits
AttributeBUFGCE[0]BUFGCE[1]
INIT_OUT bit 0CLK[0][2][6]CLK[0][3][6]

Bel wires

virtex CLK_S_V bel wires
WirePins
E.IMUX_BUFGCE_CLK[0]BUFGCE[0].I
E.IMUX_BUFGCE_CLK[1]BUFGCE[1].I
E.IMUX_BUFGCE_CE[0]BUFGCE[0].CE
E.IMUX_BUFGCE_CE[1]BUFGCE[1].CE
E.OUT_BUFGCE_O[0]BUFGCE[0].O
E.OUT_BUFGCE_O[1]BUFGCE[1].O
E.OUT_CLKPAD[0]GCLK_IOB[0].I
E.OUT_CLKPAD[1]GCLK_IOB[1].I

Bitstream

virtex CLK_S_V rect CLK[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 CLK_INT: mux W.HEX_H0_MUX[0] bit 1 CLK_INT: mux W.HEX_H0_MUX[0] bit 0 CLK_INT: mux W.HEX_H0_MUX[0] bit 2 CLK_INT: mux W.HEX_H0_MUX[0] bit 3 CLK_INT: mux W.HEX_H0_MUX[0] bit 4 CLK_INT: mux W.HEX_H0_MUX[0] bit 6 CLK_INT: mux W.HEX_H0_MUX[0] bit 5 CLK_INT: !buffer W.HEX_H0[0] ← W.HEX_H0_MUX[0]
B16 CLK_INT: mux W.HEX_H0_MUX[1] bit 1 CLK_INT: mux W.HEX_H0_MUX[1] bit 0 CLK_INT: mux W.HEX_H0_MUX[1] bit 2 CLK_INT: mux W.HEX_H0_MUX[1] bit 3 CLK_INT: mux W.HEX_H0_MUX[1] bit 4 CLK_INT: mux W.HEX_H0_MUX[1] bit 6 CLK_INT: mux W.HEX_H0_MUX[1] bit 5 CLK_INT: !buffer W.HEX_H0[1] ← W.HEX_H0_MUX[1]
B15 CLK_INT: mux W.HEX_H0_MUX[2] bit 1 CLK_INT: mux W.HEX_H0_MUX[2] bit 0 CLK_INT: mux W.HEX_H0_MUX[2] bit 2 CLK_INT: mux W.HEX_H0_MUX[2] bit 3 CLK_INT: mux W.HEX_H0_MUX[2] bit 4 CLK_INT: mux W.HEX_H0_MUX[2] bit 6 CLK_INT: mux W.HEX_H0_MUX[2] bit 5 CLK_INT: !buffer W.HEX_H0[2] ← W.HEX_H0_MUX[2]
B14 CLK_INT: mux W.HEX_H0_MUX[3] bit 1 CLK_INT: mux W.HEX_H0_MUX[3] bit 0 CLK_INT: mux W.HEX_H0_MUX[3] bit 2 CLK_INT: mux W.HEX_H0_MUX[3] bit 3 CLK_INT: mux W.HEX_H0_MUX[3] bit 4 CLK_INT: mux W.HEX_H0_MUX[3] bit 6 CLK_INT: mux W.HEX_H0_MUX[3] bit 5 CLK_INT: !buffer W.HEX_H0[3] ← W.HEX_H0_MUX[3]
B13 CLK_INT: mux W.HEX_H5_MUX[0] bit 1 CLK_INT: mux W.HEX_H5_MUX[0] bit 0 CLK_INT: mux W.HEX_H5_MUX[0] bit 2 CLK_INT: mux W.HEX_H5_MUX[0] bit 3 CLK_INT: mux W.HEX_H5_MUX[0] bit 4 CLK_INT: mux W.HEX_H5_MUX[0] bit 6 CLK_INT: mux W.HEX_H5_MUX[0] bit 5 CLK_INT: !buffer W.HEX_H5[0] ← W.HEX_H5_MUX[0]
B12 CLK_INT: mux W.HEX_H5_MUX[1] bit 1 CLK_INT: mux W.HEX_H5_MUX[1] bit 0 CLK_INT: mux W.HEX_H5_MUX[1] bit 2 CLK_INT: mux W.HEX_H5_MUX[1] bit 3 CLK_INT: mux W.HEX_H5_MUX[1] bit 4 CLK_INT: mux W.HEX_H5_MUX[1] bit 6 CLK_INT: mux W.HEX_H5_MUX[1] bit 5 CLK_INT: !buffer W.HEX_H5[1] ← W.HEX_H5_MUX[1]
B11 CLK_INT: mux W.HEX_H5_MUX[2] bit 1 CLK_INT: mux W.HEX_H5_MUX[2] bit 0 CLK_INT: mux W.HEX_H5_MUX[2] bit 2 CLK_INT: mux W.HEX_H5_MUX[2] bit 3 CLK_INT: mux W.HEX_H5_MUX[2] bit 4 CLK_INT: mux W.HEX_H5_MUX[2] bit 6 CLK_INT: mux W.HEX_H5_MUX[2] bit 5 CLK_INT: !buffer W.HEX_H5[2] ← W.HEX_H5_MUX[2]
B10 CLK_INT: mux W.HEX_H5_MUX[3] bit 1 CLK_INT: mux W.HEX_H5_MUX[3] bit 0 CLK_INT: mux W.HEX_H5_MUX[3] bit 2 CLK_INT: mux W.HEX_H5_MUX[3] bit 3 CLK_INT: mux W.HEX_H5_MUX[3] bit 4 CLK_INT: mux W.HEX_H5_MUX[3] bit 6 CLK_INT: mux W.HEX_H5_MUX[3] bit 5 CLK_INT: !buffer W.HEX_H5[3] ← W.HEX_H5_MUX[3]
B9 CLK_INT: mux W.LH_MUX[10] bit 0 CLK_INT: mux W.LH_MUX[10] bit 4 CLK_INT: mux W.LH_MUX[10] bit 3 CLK_INT: mux W.LH_MUX[10] bit 2 CLK_INT: mux W.LH_MUX[10] bit 1 CLK_INT: mux W.LH_MUX[10] bit 6 CLK_INT: mux W.LH_MUX[10] bit 5 CLK_INT: buffer W.LH[10] ← W.LH_MUX[10]
B8 CLK_INT: mux W.LH_MUX[7] bit 0 CLK_INT: mux W.LH_MUX[7] bit 4 CLK_INT: mux W.LH_MUX[7] bit 3 CLK_INT: mux W.LH_MUX[7] bit 2 CLK_INT: mux W.LH_MUX[7] bit 1 CLK_INT: mux W.LH_MUX[7] bit 6 CLK_INT: mux W.LH_MUX[7] bit 5 CLK_INT: buffer W.LH[7] ← W.LH_MUX[7]
B7 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 1
B6 GCLK_IOB[1]: DELAY bit 1 GCLK_IOB[1]: DELAY bit 2 BUFGCE[0]: INIT_OUT bit 0 BUFGCE[1]: INIT_OUT bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 0 GCLK_IOB[1]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 3
B5 CLK_INT: mux W.LH_MUX[1] bit 0 CLK_INT: mux W.LH_MUX[1] bit 4 CLK_INT: mux W.LH_MUX[1] bit 3 CLK_INT: mux W.LH_MUX[1] bit 2 CLK_INT: mux W.LH_MUX[1] bit 1 CLK_INT: mux W.LH_MUX[1] bit 6 CLK_INT: mux W.LH_MUX[1] bit 5 CLK_INT: buffer W.LH[1] ← W.LH_MUX[1]
B4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 6 BUFGCE[0]: invert CE BUFGCE[1]: invert CE
B3 GCLK_IOB[0]: DELAY bit 0 GCLK_IOB[0]: DELAY bit 1 GCLK_IOB[0]: DELAY bit 2 GCLK_IOB[0]: DELAY bit 3 GCLK_IOB[0]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 1
B2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 2
B1 CLK_INT: mux W.LH_MUX[4] bit 0 CLK_INT: mux W.LH_MUX[4] bit 4 CLK_INT: mux W.LH_MUX[4] bit 3 CLK_INT: mux W.LH_MUX[4] bit 2 CLK_INT: mux W.LH_MUX[4] bit 1 CLK_INT: mux W.LH_MUX[4] bit 6 CLK_INT: mux W.LH_MUX[4] bit 5 CLK_INT: buffer W.LH[4] ← W.LH_MUX[4]
B0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 3
virtex CLK_S_V rect CLK[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 - - - - - - - -
B16 - - - - - - - -
B15 - - - - - - - -
B14 - - - - - - - -
B13 - - - - - - - -
B12 - - - - - - - -
B11 - - - - - - - -
B10 - - - - - - - -
B9 - - - - - - - -
B8 - - - - - - - -
B7 - - - - - - - -
B6 - - - - - - - -
B5 - - - - - - - -
B4 - - - - - - - -
B3 - - - - - - - -
B2 GCLK_IOB[1]: IBUF_MODE bit 0 GCLK_IOB[1]: IBUF_MODE bit 1 - - - - - -
B1 - - - - - - - -
B0 GCLK_IOB[0]: IBUF_MODE bit 0 GCLK_IOB[0]: IBUF_MODE bit 1 - - - - - -

Tile CLK_S_VE_4DLL

Cells: 6

Switchbox CLK_INT

virtex CLK_S_VE_4DLL switchbox CLK_INT permanent buffers
DestinationSource
W.GCLK[0]E.OUT_BUFGCE_O[0]
W.GCLK[1]E.OUT_BUFGCE_O[1]
W.GCLK_LEAF[0]W.GCLK[0]
W.GCLK_LEAF[1]W.GCLK[1]
W.GCLK_LEAF[2]W.GCLK[2]
W.GCLK_LEAF[3]W.GCLK[3]
E.GCLK_LEAF[0]W.GCLK[0]
E.GCLK_LEAF[1]W.GCLK[1]
E.GCLK_LEAF[2]W.GCLK[2]
E.GCLK_LEAF[3]W.GCLK[3]
virtex CLK_S_VE_4DLL switchbox CLK_INT programmable buffers
DestinationSourceBit
W.HEX_H0[0]W.HEX_H0_MUX[0]!CLK[0][7][17]
W.HEX_H0[1]W.HEX_H0_MUX[1]!CLK[0][7][16]
W.HEX_H0[2]W.HEX_H0_MUX[2]!CLK[0][7][15]
W.HEX_H0[3]W.HEX_H0_MUX[3]!CLK[0][7][14]
W.HEX_H5[0]W.HEX_H5_MUX[0]!CLK[0][7][13]
W.HEX_H5[1]W.HEX_H5_MUX[1]!CLK[0][7][12]
W.HEX_H5[2]W.HEX_H5_MUX[2]!CLK[0][7][11]
W.HEX_H5[3]W.HEX_H5_MUX[3]!CLK[0][7][10]
W.LH[1]W.LH_MUX[1]CLK[0][7][5]
W.LH[4]W.LH_MUX[4]CLK[0][7][1]
W.LH[7]W.LH_MUX[7]CLK[0][7][8]
W.LH[10]W.LH_MUX[10]CLK[0][7][9]
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes HEX_H0_MUX[0]
BitsDestination
CLK[0][4][17]CLK[0][5][17]CLK[0][1][17]CLK[0][0][17]CLK[0][2][17]CLK[0][3][17]W.HEX_H0_MUX[0]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes HEX_H0_MUX[1]
BitsDestination
CLK[0][4][16]CLK[0][5][16]CLK[0][1][16]CLK[0][0][16]CLK[0][2][16]CLK[0][3][16]W.HEX_H0_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes HEX_H0_MUX[2]
BitsDestination
CLK[0][4][15]CLK[0][5][15]CLK[0][1][15]CLK[0][0][15]CLK[0][2][15]CLK[0][3][15]W.HEX_H0_MUX[2]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes HEX_H0_MUX[3]
BitsDestination
CLK[0][4][14]CLK[0][5][14]CLK[0][1][14]CLK[0][0][14]CLK[0][2][14]CLK[0][3][14]W.HEX_H0_MUX[3]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes HEX_H5_MUX[0]
BitsDestination
CLK[0][4][13]CLK[0][5][13]CLK[0][1][13]CLK[0][0][13]CLK[0][2][13]CLK[0][3][13]W.HEX_H5_MUX[0]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes HEX_H5_MUX[1]
BitsDestination
CLK[0][4][12]CLK[0][5][12]CLK[0][1][12]CLK[0][0][12]CLK[0][2][12]CLK[0][3][12]W.HEX_H5_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes HEX_H5_MUX[2]
BitsDestination
CLK[0][4][11]CLK[0][5][11]CLK[0][1][11]CLK[0][0][11]CLK[0][2][11]CLK[0][3][11]W.HEX_H5_MUX[2]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes HEX_H5_MUX[3]
BitsDestination
CLK[0][4][10]CLK[0][5][10]CLK[0][1][10]CLK[0][0][10]CLK[0][2][10]CLK[0][3][10]W.HEX_H5_MUX[3]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes LH_MUX[1]
BitsDestination
CLK[0][4][5]CLK[0][5][5]CLK[0][1][5]CLK[0][0][5]CLK[0][2][5]CLK[0][3][5]W.LH_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes LH_MUX[4]
BitsDestination
CLK[0][4][1]CLK[0][5][1]CLK[0][1][1]CLK[0][0][1]CLK[0][2][1]CLK[0][3][1]W.LH_MUX[4]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes LH_MUX[7]
BitsDestination
CLK[0][4][8]CLK[0][5][8]CLK[0][1][8]CLK[0][0][8]CLK[0][2][8]CLK[0][3][8]W.LH_MUX[7]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes LH_MUX[10]
BitsDestination
CLK[0][4][9]CLK[0][5][9]CLK[0][1][9]CLK[0][0][9]CLK[0][2][9]CLK[0][3][9]W.LH_MUX[10]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes IMUX_BUFGCE_CLK[0]
BitsDestination
CLK[0][7][0]CLK[0][1][2]CLK[0][4][2]CLK[0][5][2]CLK[0][6][2]CLK[0][3][2]CLK[0][2][2]CLK[0][0][2]CLK[0][6][0]CLK[0][6][3]CLK[0][4][6]E.IMUX_BUFGCE_CLK[0]
Source
00000000000E.OUT_CLKPAD[1]
00000000001E.OUT_CLKPAD[0]
00000000011off
00000001010DLLP_W.OUT_DLL_CLK270
00000001110DLLP_E.OUT_DLL_CLK270
00000001111W.HEX_H0[0]
00000010010DLLP_W.OUT_DLL_CLK90
00000010011W.HEX_H0[1]
00000010110DLLP_W.OUT_DLL_CLKDV
00000010111W.HEX_H5[0]
00000100010DLLP_E.OUT_DLL_CLK180
00000100011W.HEX_H4[1]
00000100110DLLP_E.OUT_DLL_CLK2X
00000100111W.HEX_H1[0]
00001000010DLLP_W.OUT_DLL_CLK2X
00001000011W.HEX_H1[1]
00001000110DLLP_W.OUT_DLL_CLK0
00001000111E.HEX_H3[0]
00010000010DLLP_W.OUT_DLL_CLK2X90
00010000011E.HEX_H3[1]
00010000110DLLP_E.OUT_DLL_CLK0
00010000111W.HEX_H3[0]
00100000010DLLP_E.OUT_DLL_CLK2X90
00100000011W.HEX_H3[1]
00100000110DLLP_E.OUT_DLL_CLK90
00100000111W.HEX_H4[0]
01000000010DLLP_W.OUT_DLL_CLK180
01000000011W.HEX_H5[1]
01000000110DLLP_E.OUT_DLL_CLKDV
10000001010DLLS_W.OUT_DLL_CLK270
10000001011DLLS_E.OUT_DLL_CLK180
10000010010DLLS_W.OUT_DLL_CLK90
10000010011DLLS_E.OUT_DLL_CLKDV
10000100010DLLS_W.OUT_DLL_CLKDV
10000100011DLLS_E.OUT_DLL_CLK2X90
10001000010DLLS_W.OUT_DLL_CLK2X90
10001000011DLLS_E.OUT_DLL_CLK0
10010000010DLLS_W.OUT_DLL_CLK0
10010000011DLLS_E.OUT_DLL_CLK90
10100000010DLLS_W.OUT_DLL_CLK2X
10100000011DLLS_E.OUT_DLL_CLK2X
11000000010DLLS_W.OUT_DLL_CLK180
11000000011DLLS_E.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes IMUX_BUFGCE_CLK[1]
BitsDestination
CLK[0][6][1]CLK[0][0][0]CLK[0][3][0]CLK[0][4][0]CLK[0][5][0]CLK[0][2][0]CLK[0][1][0]CLK[0][7][2]CLK[0][6][5]CLK[0][7][3]CLK[0][5][6]E.IMUX_BUFGCE_CLK[1]
Source
00000000000E.OUT_CLKPAD[0]
00000000001E.OUT_CLKPAD[1]
00000000011off
00000001010DLLP_W.OUT_DLL_CLK270
00000001110DLLP_E.OUT_DLL_CLK270
00000001111W.HEX_H0[0]
00000010010DLLP_W.OUT_DLL_CLK90
00000010011W.HEX_H0[1]
00000010110DLLP_W.OUT_DLL_CLKDV
00000010111W.HEX_H5[0]
00000100010DLLP_E.OUT_DLL_CLK180
00000100011W.HEX_H4[1]
00000100110DLLP_E.OUT_DLL_CLK2X
00000100111W.HEX_H1[0]
00001000010DLLP_W.OUT_DLL_CLK2X
00001000011W.HEX_H1[1]
00001000110DLLP_W.OUT_DLL_CLK0
00001000111E.HEX_H3[0]
00010000010DLLP_W.OUT_DLL_CLK2X90
00010000011E.HEX_H3[1]
00010000110DLLP_E.OUT_DLL_CLK0
00010000111W.HEX_H3[0]
00100000010DLLP_E.OUT_DLL_CLK2X90
00100000011W.HEX_H3[1]
00100000110DLLP_E.OUT_DLL_CLK90
00100000111W.HEX_H4[0]
01000000010DLLP_W.OUT_DLL_CLK180
01000000011W.HEX_H5[1]
01000000110DLLP_E.OUT_DLL_CLKDV
10000001010DLLS_W.OUT_DLL_CLK270
10000001011DLLS_E.OUT_DLL_CLK180
10000010010DLLS_W.OUT_DLL_CLK90
10000010011DLLS_E.OUT_DLL_CLKDV
10000100010DLLS_W.OUT_DLL_CLKDV
10000100011DLLS_E.OUT_DLL_CLK2X90
10001000010DLLS_W.OUT_DLL_CLK2X90
10001000011DLLS_E.OUT_DLL_CLK0
10010000010DLLS_W.OUT_DLL_CLK0
10010000011DLLS_E.OUT_DLL_CLK90
10100000010DLLS_W.OUT_DLL_CLK2X
10100000011DLLS_E.OUT_DLL_CLK2X
11000000010DLLS_W.OUT_DLL_CLK180
11000000011DLLS_E.OUT_DLL_CLK270
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes IMUX_BUFGCE_CE[0]
BitsDestination
CLK[0][5][4]CLK[0][0][4]CLK[0][3][4]CLK[0][2][4]CLK[0][1][4]CLK[0][7][7]CLK[0][6][7]E.IMUX_BUFGCE_CE[0]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]
virtex CLK_S_VE_4DLL switchbox CLK_INT muxes IMUX_BUFGCE_CE[1]
BitsDestination
CLK[0][4][4]CLK[0][2][7]CLK[0][5][7]CLK[0][4][7]CLK[0][3][7]CLK[0][1][7]CLK[0][0][7]E.IMUX_BUFGCE_CE[1]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]

Bels GCLK_IOB

virtex CLK_S_VE_4DLL bel GCLK_IOB pins
PinDirectionGCLK_IOB[0]GCLK_IOB[1]
IoutE.OUT_CLKPAD[0]E.OUT_CLKPAD[1]
virtex CLK_S_VE_4DLL bel GCLK_IOB attribute bits
AttributeGCLK_IOB[0]GCLK_IOB[1]
DELAY bit 0CLK[0][0][3]CLK[0][5][3]
DELAY bit 1CLK[0][1][3]CLK[0][0][6]
DELAY bit 2CLK[0][2][3]CLK[0][1][6]
DELAY bit 3CLK[0][3][3]CLK[0][7][6]
DELAY bit 4CLK[0][4][3]CLK[0][6][6]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_S_VE_4DLL enum IOB_IBUF_MODE
GCLK_IOB[0].IBUF_MODECLK[1][1][0]CLK[1][0][0]
GCLK_IOB[1].IBUF_MODECLK[1][1][2]CLK[1][0][2]
NONE11
VREF01
DIFF10
CMOS00

Bels IOFB

virtex CLK_S_VE_4DLL bel IOFB pins
PinDirectionIOFB[0]IOFB[1]
IoutE.OUT_IOFB[0]E.OUT_IOFB[1]
virtex CLK_S_VE_4DLL bel IOFB attribute bits
AttributeIOFB[0]IOFB[1]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_S_VE_4DLL enum IOB_IBUF_MODE
IOFB[0].IBUF_MODECLK[1][2][0]CLK[1][3][0]
IOFB[1].IBUF_MODECLK[1][2][2]CLK[1][3][2]
NONE11
VREF10
CMOS01

Bels BUFGCE

virtex CLK_S_VE_4DLL bel BUFGCE pins
PinDirectionBUFGCE[0]BUFGCE[1]
IinE.IMUX_BUFGCE_CLK[0]E.IMUX_BUFGCE_CLK[1]
CEinE.IMUX_BUFGCE_CE[0] invert by CLK[0][6][4]E.IMUX_BUFGCE_CE[1] invert by CLK[0][7][4]
OoutE.OUT_BUFGCE_O[0]E.OUT_BUFGCE_O[1]
virtex CLK_S_VE_4DLL bel BUFGCE attribute bits
AttributeBUFGCE[0]BUFGCE[1]
INIT_OUT bit 0CLK[0][2][6]CLK[0][3][6]

Bel wires

virtex CLK_S_VE_4DLL bel wires
WirePins
E.IMUX_BUFGCE_CLK[0]BUFGCE[0].I
E.IMUX_BUFGCE_CLK[1]BUFGCE[1].I
E.IMUX_BUFGCE_CE[0]BUFGCE[0].CE
E.IMUX_BUFGCE_CE[1]BUFGCE[1].CE
E.OUT_BUFGCE_O[0]BUFGCE[0].O
E.OUT_BUFGCE_O[1]BUFGCE[1].O
E.OUT_CLKPAD[0]GCLK_IOB[0].I
E.OUT_CLKPAD[1]GCLK_IOB[1].I
E.OUT_IOFB[0]IOFB[0].I
E.OUT_IOFB[1]IOFB[1].I

Bitstream

virtex CLK_S_VE_4DLL rect CLK[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 CLK_INT: mux W.HEX_H0_MUX[0] bit 2 CLK_INT: mux W.HEX_H0_MUX[0] bit 3 CLK_INT: mux W.HEX_H0_MUX[0] bit 1 CLK_INT: mux W.HEX_H0_MUX[0] bit 0 CLK_INT: mux W.HEX_H0_MUX[0] bit 5 CLK_INT: mux W.HEX_H0_MUX[0] bit 4 - CLK_INT: !buffer W.HEX_H0[0] ← W.HEX_H0_MUX[0]
B16 CLK_INT: mux W.HEX_H0_MUX[1] bit 2 CLK_INT: mux W.HEX_H0_MUX[1] bit 3 CLK_INT: mux W.HEX_H0_MUX[1] bit 1 CLK_INT: mux W.HEX_H0_MUX[1] bit 0 CLK_INT: mux W.HEX_H0_MUX[1] bit 5 CLK_INT: mux W.HEX_H0_MUX[1] bit 4 - CLK_INT: !buffer W.HEX_H0[1] ← W.HEX_H0_MUX[1]
B15 CLK_INT: mux W.HEX_H0_MUX[2] bit 2 CLK_INT: mux W.HEX_H0_MUX[2] bit 3 CLK_INT: mux W.HEX_H0_MUX[2] bit 1 CLK_INT: mux W.HEX_H0_MUX[2] bit 0 CLK_INT: mux W.HEX_H0_MUX[2] bit 5 CLK_INT: mux W.HEX_H0_MUX[2] bit 4 - CLK_INT: !buffer W.HEX_H0[2] ← W.HEX_H0_MUX[2]
B14 CLK_INT: mux W.HEX_H0_MUX[3] bit 2 CLK_INT: mux W.HEX_H0_MUX[3] bit 3 CLK_INT: mux W.HEX_H0_MUX[3] bit 1 CLK_INT: mux W.HEX_H0_MUX[3] bit 0 CLK_INT: mux W.HEX_H0_MUX[3] bit 5 CLK_INT: mux W.HEX_H0_MUX[3] bit 4 - CLK_INT: !buffer W.HEX_H0[3] ← W.HEX_H0_MUX[3]
B13 CLK_INT: mux W.HEX_H5_MUX[0] bit 2 CLK_INT: mux W.HEX_H5_MUX[0] bit 3 CLK_INT: mux W.HEX_H5_MUX[0] bit 1 CLK_INT: mux W.HEX_H5_MUX[0] bit 0 CLK_INT: mux W.HEX_H5_MUX[0] bit 5 CLK_INT: mux W.HEX_H5_MUX[0] bit 4 - CLK_INT: !buffer W.HEX_H5[0] ← W.HEX_H5_MUX[0]
B12 CLK_INT: mux W.HEX_H5_MUX[1] bit 2 CLK_INT: mux W.HEX_H5_MUX[1] bit 3 CLK_INT: mux W.HEX_H5_MUX[1] bit 1 CLK_INT: mux W.HEX_H5_MUX[1] bit 0 CLK_INT: mux W.HEX_H5_MUX[1] bit 5 CLK_INT: mux W.HEX_H5_MUX[1] bit 4 - CLK_INT: !buffer W.HEX_H5[1] ← W.HEX_H5_MUX[1]
B11 CLK_INT: mux W.HEX_H5_MUX[2] bit 2 CLK_INT: mux W.HEX_H5_MUX[2] bit 3 CLK_INT: mux W.HEX_H5_MUX[2] bit 1 CLK_INT: mux W.HEX_H5_MUX[2] bit 0 CLK_INT: mux W.HEX_H5_MUX[2] bit 5 CLK_INT: mux W.HEX_H5_MUX[2] bit 4 - CLK_INT: !buffer W.HEX_H5[2] ← W.HEX_H5_MUX[2]
B10 CLK_INT: mux W.HEX_H5_MUX[3] bit 2 CLK_INT: mux W.HEX_H5_MUX[3] bit 3 CLK_INT: mux W.HEX_H5_MUX[3] bit 1 CLK_INT: mux W.HEX_H5_MUX[3] bit 0 CLK_INT: mux W.HEX_H5_MUX[3] bit 5 CLK_INT: mux W.HEX_H5_MUX[3] bit 4 - CLK_INT: !buffer W.HEX_H5[3] ← W.HEX_H5_MUX[3]
B9 CLK_INT: mux W.LH_MUX[10] bit 2 CLK_INT: mux W.LH_MUX[10] bit 3 CLK_INT: mux W.LH_MUX[10] bit 1 CLK_INT: mux W.LH_MUX[10] bit 0 CLK_INT: mux W.LH_MUX[10] bit 5 CLK_INT: mux W.LH_MUX[10] bit 4 - CLK_INT: buffer W.LH[10] ← W.LH_MUX[10]
B8 CLK_INT: mux W.LH_MUX[7] bit 2 CLK_INT: mux W.LH_MUX[7] bit 3 CLK_INT: mux W.LH_MUX[7] bit 1 CLK_INT: mux W.LH_MUX[7] bit 0 CLK_INT: mux W.LH_MUX[7] bit 5 CLK_INT: mux W.LH_MUX[7] bit 4 - CLK_INT: buffer W.LH[7] ← W.LH_MUX[7]
B7 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 1
B6 GCLK_IOB[1]: DELAY bit 1 GCLK_IOB[1]: DELAY bit 2 BUFGCE[0]: INIT_OUT bit 0 BUFGCE[1]: INIT_OUT bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 0 GCLK_IOB[1]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 3
B5 CLK_INT: mux W.LH_MUX[1] bit 2 CLK_INT: mux W.LH_MUX[1] bit 3 CLK_INT: mux W.LH_MUX[1] bit 1 CLK_INT: mux W.LH_MUX[1] bit 0 CLK_INT: mux W.LH_MUX[1] bit 5 CLK_INT: mux W.LH_MUX[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 2 CLK_INT: buffer W.LH[1] ← W.LH_MUX[1]
B4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 6 BUFGCE[0]: invert CE BUFGCE[1]: invert CE
B3 GCLK_IOB[0]: DELAY bit 0 GCLK_IOB[0]: DELAY bit 1 GCLK_IOB[0]: DELAY bit 2 GCLK_IOB[0]: DELAY bit 3 GCLK_IOB[0]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 1
B2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 3
B1 CLK_INT: mux W.LH_MUX[4] bit 2 CLK_INT: mux W.LH_MUX[4] bit 3 CLK_INT: mux W.LH_MUX[4] bit 1 CLK_INT: mux W.LH_MUX[4] bit 0 CLK_INT: mux W.LH_MUX[4] bit 5 CLK_INT: mux W.LH_MUX[4] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 10 CLK_INT: buffer W.LH[4] ← W.LH_MUX[4]
B0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 10
virtex CLK_S_VE_4DLL rect CLK[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 - - - - - - - -
B16 - - - - - - - -
B15 - - - - - - - -
B14 - - - - - - - -
B13 - - - - - - - -
B12 - - - - - - - -
B11 - - - - - - - -
B10 - - - - - - - -
B9 - - - - - - - -
B8 - - - - - - - -
B7 - - - - - - - -
B6 - - - - - - - -
B5 - - - - - - - -
B4 - - - - - - - -
B3 - - - - - - - -
B2 GCLK_IOB[1]: IBUF_MODE bit 0 GCLK_IOB[1]: IBUF_MODE bit 1 IOFB[1]: IBUF_MODE bit 1 IOFB[1]: IBUF_MODE bit 0 - - - -
B1 - - - - - - - -
B0 GCLK_IOB[0]: IBUF_MODE bit 0 GCLK_IOB[0]: IBUF_MODE bit 1 IOFB[0]: IBUF_MODE bit 1 IOFB[0]: IBUF_MODE bit 0 - - - -

Tile CLK_S_VE_2DLL

Cells: 6

Switchbox CLK_INT

virtex CLK_S_VE_2DLL switchbox CLK_INT permanent buffers
DestinationSource
W.GCLK[0]E.OUT_BUFGCE_O[0]
W.GCLK[1]E.OUT_BUFGCE_O[1]
W.GCLK_LEAF[0]W.GCLK[0]
W.GCLK_LEAF[1]W.GCLK[1]
W.GCLK_LEAF[2]W.GCLK[2]
W.GCLK_LEAF[3]W.GCLK[3]
E.GCLK_LEAF[0]W.GCLK[0]
E.GCLK_LEAF[1]W.GCLK[1]
E.GCLK_LEAF[2]W.GCLK[2]
E.GCLK_LEAF[3]W.GCLK[3]
virtex CLK_S_VE_2DLL switchbox CLK_INT programmable buffers
DestinationSourceBit
W.HEX_H0[0]W.HEX_H0_MUX[0]!CLK[0][7][17]
W.HEX_H0[1]W.HEX_H0_MUX[1]!CLK[0][7][16]
W.HEX_H0[2]W.HEX_H0_MUX[2]!CLK[0][7][15]
W.HEX_H0[3]W.HEX_H0_MUX[3]!CLK[0][7][14]
W.HEX_H5[0]W.HEX_H5_MUX[0]!CLK[0][7][13]
W.HEX_H5[1]W.HEX_H5_MUX[1]!CLK[0][7][12]
W.HEX_H5[2]W.HEX_H5_MUX[2]!CLK[0][7][11]
W.HEX_H5[3]W.HEX_H5_MUX[3]!CLK[0][7][10]
W.LH[1]W.LH_MUX[1]CLK[0][7][5]
W.LH[4]W.LH_MUX[4]CLK[0][7][1]
W.LH[7]W.LH_MUX[7]CLK[0][7][8]
W.LH[10]W.LH_MUX[10]CLK[0][7][9]
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes HEX_H0_MUX[0]
BitsDestination
CLK[0][4][17]CLK[0][5][17]CLK[0][1][17]CLK[0][0][17]CLK[0][2][17]CLK[0][3][17]W.HEX_H0_MUX[0]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes HEX_H0_MUX[1]
BitsDestination
CLK[0][4][16]CLK[0][5][16]CLK[0][1][16]CLK[0][0][16]CLK[0][2][16]CLK[0][3][16]W.HEX_H0_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes HEX_H0_MUX[2]
BitsDestination
CLK[0][4][15]CLK[0][5][15]CLK[0][1][15]CLK[0][0][15]CLK[0][2][15]CLK[0][3][15]W.HEX_H0_MUX[2]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes HEX_H0_MUX[3]
BitsDestination
CLK[0][4][14]CLK[0][5][14]CLK[0][1][14]CLK[0][0][14]CLK[0][2][14]CLK[0][3][14]W.HEX_H0_MUX[3]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes HEX_H5_MUX[0]
BitsDestination
CLK[0][4][13]CLK[0][5][13]CLK[0][1][13]CLK[0][0][13]CLK[0][2][13]CLK[0][3][13]W.HEX_H5_MUX[0]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes HEX_H5_MUX[1]
BitsDestination
CLK[0][4][12]CLK[0][5][12]CLK[0][1][12]CLK[0][0][12]CLK[0][2][12]CLK[0][3][12]W.HEX_H5_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes HEX_H5_MUX[2]
BitsDestination
CLK[0][4][11]CLK[0][5][11]CLK[0][1][11]CLK[0][0][11]CLK[0][2][11]CLK[0][3][11]W.HEX_H5_MUX[2]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes HEX_H5_MUX[3]
BitsDestination
CLK[0][4][10]CLK[0][5][10]CLK[0][1][10]CLK[0][0][10]CLK[0][2][10]CLK[0][3][10]W.HEX_H5_MUX[3]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes LH_MUX[1]
BitsDestination
CLK[0][4][5]CLK[0][5][5]CLK[0][1][5]CLK[0][0][5]CLK[0][2][5]CLK[0][3][5]W.LH_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes LH_MUX[4]
BitsDestination
CLK[0][4][1]CLK[0][5][1]CLK[0][1][1]CLK[0][0][1]CLK[0][2][1]CLK[0][3][1]W.LH_MUX[4]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes LH_MUX[7]
BitsDestination
CLK[0][4][8]CLK[0][5][8]CLK[0][1][8]CLK[0][0][8]CLK[0][2][8]CLK[0][3][8]W.LH_MUX[7]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes LH_MUX[10]
BitsDestination
CLK[0][4][9]CLK[0][5][9]CLK[0][1][9]CLK[0][0][9]CLK[0][2][9]CLK[0][3][9]W.LH_MUX[10]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes IMUX_BUFGCE_CLK[0]
BitsDestination
CLK[0][7][0]CLK[0][1][2]CLK[0][4][2]CLK[0][5][2]CLK[0][6][2]CLK[0][3][2]CLK[0][2][2]CLK[0][0][2]CLK[0][6][0]CLK[0][6][3]CLK[0][4][6]E.IMUX_BUFGCE_CLK[0]
Source
00000000000E.OUT_CLKPAD[1]
00000000001E.OUT_CLKPAD[0]
00000000011off
00000001111W.HEX_H0[0]
00000010011W.HEX_H0[1]
00000010111W.HEX_H5[0]
00000100011W.HEX_H4[1]
00000100111W.HEX_H1[0]
00001000011W.HEX_H1[1]
00001000111E.HEX_H3[0]
00010000011E.HEX_H3[1]
00010000111W.HEX_H3[0]
00100000011W.HEX_H3[1]
00100000111W.HEX_H4[0]
01000000011W.HEX_H5[1]
10000001010DLLS_W.OUT_DLL_CLK270
10000001011DLLS_E.OUT_DLL_CLK180
10000010010DLLS_W.OUT_DLL_CLK90
10000010011DLLS_E.OUT_DLL_CLKDV
10000100010DLLS_W.OUT_DLL_CLKDV
10000100011DLLS_E.OUT_DLL_CLK2X90
10001000010DLLS_W.OUT_DLL_CLK2X90
10001000011DLLS_E.OUT_DLL_CLK0
10010000010DLLS_W.OUT_DLL_CLK0
10010000011DLLS_E.OUT_DLL_CLK90
10100000010DLLS_W.OUT_DLL_CLK2X
10100000011DLLS_E.OUT_DLL_CLK2X
11000000010DLLS_W.OUT_DLL_CLK180
11000000011DLLS_E.OUT_DLL_CLK270
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes IMUX_BUFGCE_CLK[1]
BitsDestination
CLK[0][6][1]CLK[0][0][0]CLK[0][3][0]CLK[0][4][0]CLK[0][5][0]CLK[0][2][0]CLK[0][1][0]CLK[0][7][2]CLK[0][6][5]CLK[0][7][3]CLK[0][5][6]E.IMUX_BUFGCE_CLK[1]
Source
00000000000E.OUT_CLKPAD[0]
00000000001E.OUT_CLKPAD[1]
00000000011off
00000001111W.HEX_H0[0]
00000010011W.HEX_H0[1]
00000010111W.HEX_H5[0]
00000100011W.HEX_H4[1]
00000100111W.HEX_H1[0]
00001000011W.HEX_H1[1]
00001000111E.HEX_H3[0]
00010000011E.HEX_H3[1]
00010000111W.HEX_H3[0]
00100000011W.HEX_H3[1]
00100000111W.HEX_H4[0]
01000000011W.HEX_H5[1]
10000001010DLLS_W.OUT_DLL_CLK270
10000001011DLLS_E.OUT_DLL_CLK180
10000010010DLLS_W.OUT_DLL_CLK90
10000010011DLLS_E.OUT_DLL_CLKDV
10000100010DLLS_W.OUT_DLL_CLKDV
10000100011DLLS_E.OUT_DLL_CLK2X90
10001000010DLLS_W.OUT_DLL_CLK2X90
10001000011DLLS_E.OUT_DLL_CLK0
10010000010DLLS_W.OUT_DLL_CLK0
10010000011DLLS_E.OUT_DLL_CLK90
10100000010DLLS_W.OUT_DLL_CLK2X
10100000011DLLS_E.OUT_DLL_CLK2X
11000000010DLLS_W.OUT_DLL_CLK180
11000000011DLLS_E.OUT_DLL_CLK270
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes IMUX_BUFGCE_CE[0]
BitsDestination
CLK[0][5][4]CLK[0][0][4]CLK[0][3][4]CLK[0][2][4]CLK[0][1][4]CLK[0][7][7]CLK[0][6][7]E.IMUX_BUFGCE_CE[0]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]
virtex CLK_S_VE_2DLL switchbox CLK_INT muxes IMUX_BUFGCE_CE[1]
BitsDestination
CLK[0][4][4]CLK[0][2][7]CLK[0][5][7]CLK[0][4][7]CLK[0][3][7]CLK[0][1][7]CLK[0][0][7]E.IMUX_BUFGCE_CE[1]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]

Bels GCLK_IOB

virtex CLK_S_VE_2DLL bel GCLK_IOB pins
PinDirectionGCLK_IOB[0]GCLK_IOB[1]
IoutE.OUT_CLKPAD[0]E.OUT_CLKPAD[1]
virtex CLK_S_VE_2DLL bel GCLK_IOB attribute bits
AttributeGCLK_IOB[0]GCLK_IOB[1]
DELAY bit 0CLK[0][0][3]CLK[0][5][3]
DELAY bit 1CLK[0][1][3]CLK[0][0][6]
DELAY bit 2CLK[0][2][3]CLK[0][1][6]
DELAY bit 3CLK[0][3][3]CLK[0][7][6]
DELAY bit 4CLK[0][4][3]CLK[0][6][6]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_S_VE_2DLL enum IOB_IBUF_MODE
GCLK_IOB[0].IBUF_MODECLK[1][1][0]CLK[1][0][0]
GCLK_IOB[1].IBUF_MODECLK[1][1][2]CLK[1][0][2]
NONE11
VREF01
DIFF10
CMOS00

Bels IOFB

virtex CLK_S_VE_2DLL bel IOFB pins
PinDirectionIOFB[0]IOFB[1]
IoutE.OUT_IOFB[0]E.OUT_IOFB[1]
virtex CLK_S_VE_2DLL bel IOFB attribute bits
AttributeIOFB[0]IOFB[1]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_S_VE_2DLL enum IOB_IBUF_MODE
IOFB[0].IBUF_MODECLK[1][2][0]CLK[1][3][0]
IOFB[1].IBUF_MODECLK[1][2][2]CLK[1][3][2]
NONE11
VREF10
CMOS01

Bels BUFGCE

virtex CLK_S_VE_2DLL bel BUFGCE pins
PinDirectionBUFGCE[0]BUFGCE[1]
IinE.IMUX_BUFGCE_CLK[0]E.IMUX_BUFGCE_CLK[1]
CEinE.IMUX_BUFGCE_CE[0] invert by CLK[0][6][4]E.IMUX_BUFGCE_CE[1] invert by CLK[0][7][4]
OoutE.OUT_BUFGCE_O[0]E.OUT_BUFGCE_O[1]
virtex CLK_S_VE_2DLL bel BUFGCE attribute bits
AttributeBUFGCE[0]BUFGCE[1]
INIT_OUT bit 0CLK[0][2][6]CLK[0][3][6]

Bel wires

virtex CLK_S_VE_2DLL bel wires
WirePins
E.IMUX_BUFGCE_CLK[0]BUFGCE[0].I
E.IMUX_BUFGCE_CLK[1]BUFGCE[1].I
E.IMUX_BUFGCE_CE[0]BUFGCE[0].CE
E.IMUX_BUFGCE_CE[1]BUFGCE[1].CE
E.OUT_BUFGCE_O[0]BUFGCE[0].O
E.OUT_BUFGCE_O[1]BUFGCE[1].O
E.OUT_CLKPAD[0]GCLK_IOB[0].I
E.OUT_CLKPAD[1]GCLK_IOB[1].I
E.OUT_IOFB[0]IOFB[0].I
E.OUT_IOFB[1]IOFB[1].I

Bitstream

virtex CLK_S_VE_2DLL rect CLK[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 CLK_INT: mux W.HEX_H0_MUX[0] bit 2 CLK_INT: mux W.HEX_H0_MUX[0] bit 3 CLK_INT: mux W.HEX_H0_MUX[0] bit 1 CLK_INT: mux W.HEX_H0_MUX[0] bit 0 CLK_INT: mux W.HEX_H0_MUX[0] bit 5 CLK_INT: mux W.HEX_H0_MUX[0] bit 4 - CLK_INT: !buffer W.HEX_H0[0] ← W.HEX_H0_MUX[0]
B16 CLK_INT: mux W.HEX_H0_MUX[1] bit 2 CLK_INT: mux W.HEX_H0_MUX[1] bit 3 CLK_INT: mux W.HEX_H0_MUX[1] bit 1 CLK_INT: mux W.HEX_H0_MUX[1] bit 0 CLK_INT: mux W.HEX_H0_MUX[1] bit 5 CLK_INT: mux W.HEX_H0_MUX[1] bit 4 - CLK_INT: !buffer W.HEX_H0[1] ← W.HEX_H0_MUX[1]
B15 CLK_INT: mux W.HEX_H0_MUX[2] bit 2 CLK_INT: mux W.HEX_H0_MUX[2] bit 3 CLK_INT: mux W.HEX_H0_MUX[2] bit 1 CLK_INT: mux W.HEX_H0_MUX[2] bit 0 CLK_INT: mux W.HEX_H0_MUX[2] bit 5 CLK_INT: mux W.HEX_H0_MUX[2] bit 4 - CLK_INT: !buffer W.HEX_H0[2] ← W.HEX_H0_MUX[2]
B14 CLK_INT: mux W.HEX_H0_MUX[3] bit 2 CLK_INT: mux W.HEX_H0_MUX[3] bit 3 CLK_INT: mux W.HEX_H0_MUX[3] bit 1 CLK_INT: mux W.HEX_H0_MUX[3] bit 0 CLK_INT: mux W.HEX_H0_MUX[3] bit 5 CLK_INT: mux W.HEX_H0_MUX[3] bit 4 - CLK_INT: !buffer W.HEX_H0[3] ← W.HEX_H0_MUX[3]
B13 CLK_INT: mux W.HEX_H5_MUX[0] bit 2 CLK_INT: mux W.HEX_H5_MUX[0] bit 3 CLK_INT: mux W.HEX_H5_MUX[0] bit 1 CLK_INT: mux W.HEX_H5_MUX[0] bit 0 CLK_INT: mux W.HEX_H5_MUX[0] bit 5 CLK_INT: mux W.HEX_H5_MUX[0] bit 4 - CLK_INT: !buffer W.HEX_H5[0] ← W.HEX_H5_MUX[0]
B12 CLK_INT: mux W.HEX_H5_MUX[1] bit 2 CLK_INT: mux W.HEX_H5_MUX[1] bit 3 CLK_INT: mux W.HEX_H5_MUX[1] bit 1 CLK_INT: mux W.HEX_H5_MUX[1] bit 0 CLK_INT: mux W.HEX_H5_MUX[1] bit 5 CLK_INT: mux W.HEX_H5_MUX[1] bit 4 - CLK_INT: !buffer W.HEX_H5[1] ← W.HEX_H5_MUX[1]
B11 CLK_INT: mux W.HEX_H5_MUX[2] bit 2 CLK_INT: mux W.HEX_H5_MUX[2] bit 3 CLK_INT: mux W.HEX_H5_MUX[2] bit 1 CLK_INT: mux W.HEX_H5_MUX[2] bit 0 CLK_INT: mux W.HEX_H5_MUX[2] bit 5 CLK_INT: mux W.HEX_H5_MUX[2] bit 4 - CLK_INT: !buffer W.HEX_H5[2] ← W.HEX_H5_MUX[2]
B10 CLK_INT: mux W.HEX_H5_MUX[3] bit 2 CLK_INT: mux W.HEX_H5_MUX[3] bit 3 CLK_INT: mux W.HEX_H5_MUX[3] bit 1 CLK_INT: mux W.HEX_H5_MUX[3] bit 0 CLK_INT: mux W.HEX_H5_MUX[3] bit 5 CLK_INT: mux W.HEX_H5_MUX[3] bit 4 - CLK_INT: !buffer W.HEX_H5[3] ← W.HEX_H5_MUX[3]
B9 CLK_INT: mux W.LH_MUX[10] bit 2 CLK_INT: mux W.LH_MUX[10] bit 3 CLK_INT: mux W.LH_MUX[10] bit 1 CLK_INT: mux W.LH_MUX[10] bit 0 CLK_INT: mux W.LH_MUX[10] bit 5 CLK_INT: mux W.LH_MUX[10] bit 4 - CLK_INT: buffer W.LH[10] ← W.LH_MUX[10]
B8 CLK_INT: mux W.LH_MUX[7] bit 2 CLK_INT: mux W.LH_MUX[7] bit 3 CLK_INT: mux W.LH_MUX[7] bit 1 CLK_INT: mux W.LH_MUX[7] bit 0 CLK_INT: mux W.LH_MUX[7] bit 5 CLK_INT: mux W.LH_MUX[7] bit 4 - CLK_INT: buffer W.LH[7] ← W.LH_MUX[7]
B7 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 1
B6 GCLK_IOB[1]: DELAY bit 1 GCLK_IOB[1]: DELAY bit 2 BUFGCE[0]: INIT_OUT bit 0 BUFGCE[1]: INIT_OUT bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 0 GCLK_IOB[1]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 3
B5 CLK_INT: mux W.LH_MUX[1] bit 2 CLK_INT: mux W.LH_MUX[1] bit 3 CLK_INT: mux W.LH_MUX[1] bit 1 CLK_INT: mux W.LH_MUX[1] bit 0 CLK_INT: mux W.LH_MUX[1] bit 5 CLK_INT: mux W.LH_MUX[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 2 CLK_INT: buffer W.LH[1] ← W.LH_MUX[1]
B4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 6 BUFGCE[0]: invert CE BUFGCE[1]: invert CE
B3 GCLK_IOB[0]: DELAY bit 0 GCLK_IOB[0]: DELAY bit 1 GCLK_IOB[0]: DELAY bit 2 GCLK_IOB[0]: DELAY bit 3 GCLK_IOB[0]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 1
B2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 3
B1 CLK_INT: mux W.LH_MUX[4] bit 2 CLK_INT: mux W.LH_MUX[4] bit 3 CLK_INT: mux W.LH_MUX[4] bit 1 CLK_INT: mux W.LH_MUX[4] bit 0 CLK_INT: mux W.LH_MUX[4] bit 5 CLK_INT: mux W.LH_MUX[4] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 10 CLK_INT: buffer W.LH[4] ← W.LH_MUX[4]
B0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 10
virtex CLK_S_VE_2DLL rect CLK[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 - - - - - - - -
B16 - - - - - - - -
B15 - - - - - - - -
B14 - - - - - - - -
B13 - - - - - - - -
B12 - - - - - - - -
B11 - - - - - - - -
B10 - - - - - - - -
B9 - - - - - - - -
B8 - - - - - - - -
B7 - - - - - - - -
B6 - - - - - - - -
B5 - - - - - - - -
B4 - - - - - - - -
B3 - - - - - - - -
B2 GCLK_IOB[1]: IBUF_MODE bit 0 GCLK_IOB[1]: IBUF_MODE bit 1 IOFB[1]: IBUF_MODE bit 1 IOFB[1]: IBUF_MODE bit 0 - - - -
B1 - - - - - - - -
B0 GCLK_IOB[0]: IBUF_MODE bit 0 GCLK_IOB[0]: IBUF_MODE bit 1 IOFB[0]: IBUF_MODE bit 1 IOFB[0]: IBUF_MODE bit 0 - - - -

Tile CLK_N_V

Cells: 4

Switchbox CLK_INT

virtex CLK_N_V switchbox CLK_INT permanent buffers
DestinationSource
W.GCLK[2]E.OUT_BUFGCE_O[0]
W.GCLK[3]E.OUT_BUFGCE_O[1]
W.GCLK_LEAF[0]W.GCLK[0]
W.GCLK_LEAF[1]W.GCLK[1]
W.GCLK_LEAF[2]W.GCLK[2]
W.GCLK_LEAF[3]W.GCLK[3]
E.GCLK_LEAF[0]W.GCLK[0]
E.GCLK_LEAF[1]W.GCLK[1]
E.GCLK_LEAF[2]W.GCLK[2]
E.GCLK_LEAF[3]W.GCLK[3]
virtex CLK_N_V switchbox CLK_INT programmable buffers
DestinationSourceBit
W.HEX_H0[0]W.HEX_H0_MUX[0]!CLK[0][7][17]
W.HEX_H0[1]W.HEX_H0_MUX[1]!CLK[0][7][16]
W.HEX_H0[2]W.HEX_H0_MUX[2]!CLK[0][7][15]
W.HEX_H0[3]W.HEX_H0_MUX[3]!CLK[0][7][14]
W.HEX_H5[0]W.HEX_H5_MUX[0]!CLK[0][7][13]
W.HEX_H5[1]W.HEX_H5_MUX[1]!CLK[0][7][12]
W.HEX_H5[2]W.HEX_H5_MUX[2]!CLK[0][7][11]
W.HEX_H5[3]W.HEX_H5_MUX[3]!CLK[0][7][10]
W.LH[1]W.LH_MUX[1]CLK[0][7][5]
W.LH[4]W.LH_MUX[4]CLK[0][7][1]
W.LH[7]W.LH_MUX[7]CLK[0][7][8]
W.LH[10]W.LH_MUX[10]CLK[0][7][9]
virtex CLK_N_V switchbox CLK_INT muxes HEX_H0_MUX[0]
BitsDestination
CLK[0][5][17]CLK[0][6][17]CLK[0][4][17]CLK[0][3][17]CLK[0][2][17]CLK[0][0][17]CLK[0][1][17]W.HEX_H0_MUX[0]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_N_V switchbox CLK_INT muxes HEX_H0_MUX[1]
BitsDestination
CLK[0][5][16]CLK[0][6][16]CLK[0][4][16]CLK[0][3][16]CLK[0][2][16]CLK[0][0][16]CLK[0][1][16]W.HEX_H0_MUX[1]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_N_V switchbox CLK_INT muxes HEX_H0_MUX[2]
BitsDestination
CLK[0][5][15]CLK[0][6][15]CLK[0][4][15]CLK[0][3][15]CLK[0][2][15]CLK[0][0][15]CLK[0][1][15]W.HEX_H0_MUX[2]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_N_V switchbox CLK_INT muxes HEX_H0_MUX[3]
BitsDestination
CLK[0][5][14]CLK[0][6][14]CLK[0][4][14]CLK[0][3][14]CLK[0][2][14]CLK[0][0][14]CLK[0][1][14]W.HEX_H0_MUX[3]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_N_V switchbox CLK_INT muxes HEX_H5_MUX[0]
BitsDestination
CLK[0][5][13]CLK[0][6][13]CLK[0][4][13]CLK[0][3][13]CLK[0][2][13]CLK[0][0][13]CLK[0][1][13]W.HEX_H5_MUX[0]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_N_V switchbox CLK_INT muxes HEX_H5_MUX[1]
BitsDestination
CLK[0][5][12]CLK[0][6][12]CLK[0][4][12]CLK[0][3][12]CLK[0][2][12]CLK[0][0][12]CLK[0][1][12]W.HEX_H5_MUX[1]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_N_V switchbox CLK_INT muxes HEX_H5_MUX[2]
BitsDestination
CLK[0][5][11]CLK[0][6][11]CLK[0][4][11]CLK[0][3][11]CLK[0][2][11]CLK[0][0][11]CLK[0][1][11]W.HEX_H5_MUX[2]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_N_V switchbox CLK_INT muxes HEX_H5_MUX[3]
BitsDestination
CLK[0][5][10]CLK[0][6][10]CLK[0][4][10]CLK[0][3][10]CLK[0][2][10]CLK[0][0][10]CLK[0][1][10]W.HEX_H5_MUX[3]
Source
0000000off
0000001DLL_E.OUT_DLL_LOCKED
0000010DLL_W.OUT_DLL_LOCKED
0000100E.OUT_CLKPAD[1]
0001000DLL_E.OUT_DLL_CLK0
0010000DLL_E.OUT_DLL_CLKDV
0100001E.OUT_BUFGCE_O[0]
0100010DLL_W.OUT_DLL_CLK2X90
0100100DLL_E.OUT_DLL_CLK180
0101000DLL_E.OUT_DLL_CLK270
0110000DLL_E.OUT_DLL_CLK2X
1000001DLL_E.OUT_DLL_CLK2X90
1000010E.OUT_BUFGCE_O[1]
1000100DLL_W.OUT_DLL_CLK180
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_E.OUT_DLL_CLK90
1100001DLL_W.OUT_DLL_CLK270
1100010DLL_W.OUT_DLL_CLK2X
1100100E.OUT_CLKPAD[0]
1101000DLL_W.OUT_DLL_CLK90
1110000DLL_W.OUT_DLL_CLKDV
virtex CLK_N_V switchbox CLK_INT muxes LH_MUX[1]
BitsDestination
CLK[0][5][5]CLK[0][6][5]CLK[0][1][5]CLK[0][2][5]CLK[0][3][5]CLK[0][4][5]CLK[0][0][5]W.LH_MUX[1]
Source
0000000off
0000001E.OUT_BUFGCE_O[0]
0000010E.OUT_BUFGCE_O[1]
0000100E.OUT_CLKPAD[1]
0001000DLL_W.OUT_DLL_CLK2X
0010000DLL_E.OUT_DLL_CLK2X90
0100001DLL_W.OUT_DLL_CLK180
0100010E.OUT_CLKPAD[0]
0100100DLL_E.OUT_DLL_CLK90
0101000DLL_E.OUT_DLL_LOCKED
0110000DLL_W.OUT_DLL_CLK270
1000001DLL_W.OUT_DLL_LOCKED
1000010DLL_E.OUT_DLL_CLK180
1000100DLL_W.OUT_DLL_CLK2X90
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_W.OUT_DLL_CLK90
1100001DLL_E.OUT_DLL_CLKDV
1100010DLL_E.OUT_DLL_CLK0
1100100DLL_E.OUT_DLL_CLK2X
1101000DLL_W.OUT_DLL_CLKDV
1110000DLL_E.OUT_DLL_CLK270
virtex CLK_N_V switchbox CLK_INT muxes LH_MUX[4]
BitsDestination
CLK[0][5][1]CLK[0][6][1]CLK[0][1][1]CLK[0][2][1]CLK[0][3][1]CLK[0][4][1]CLK[0][0][1]W.LH_MUX[4]
Source
0000000off
0000001E.OUT_BUFGCE_O[0]
0000010E.OUT_BUFGCE_O[1]
0000100E.OUT_CLKPAD[1]
0001000DLL_W.OUT_DLL_CLK2X
0010000DLL_E.OUT_DLL_CLK2X90
0100001DLL_W.OUT_DLL_CLK180
0100010E.OUT_CLKPAD[0]
0100100DLL_E.OUT_DLL_CLK90
0101000DLL_E.OUT_DLL_LOCKED
0110000DLL_W.OUT_DLL_CLK270
1000001DLL_W.OUT_DLL_LOCKED
1000010DLL_E.OUT_DLL_CLK180
1000100DLL_W.OUT_DLL_CLK2X90
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_W.OUT_DLL_CLK90
1100001DLL_E.OUT_DLL_CLKDV
1100010DLL_E.OUT_DLL_CLK0
1100100DLL_E.OUT_DLL_CLK2X
1101000DLL_W.OUT_DLL_CLKDV
1110000DLL_E.OUT_DLL_CLK270
virtex CLK_N_V switchbox CLK_INT muxes LH_MUX[7]
BitsDestination
CLK[0][5][8]CLK[0][6][8]CLK[0][1][8]CLK[0][2][8]CLK[0][3][8]CLK[0][4][8]CLK[0][0][8]W.LH_MUX[7]
Source
0000000off
0000001E.OUT_BUFGCE_O[0]
0000010E.OUT_BUFGCE_O[1]
0000100E.OUT_CLKPAD[1]
0001000DLL_W.OUT_DLL_CLK2X
0010000DLL_E.OUT_DLL_CLK2X90
0100001DLL_W.OUT_DLL_CLK180
0100010E.OUT_CLKPAD[0]
0100100DLL_E.OUT_DLL_CLK90
0101000DLL_E.OUT_DLL_LOCKED
0110000DLL_W.OUT_DLL_CLK270
1000001DLL_W.OUT_DLL_LOCKED
1000010DLL_E.OUT_DLL_CLK180
1000100DLL_W.OUT_DLL_CLK2X90
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_W.OUT_DLL_CLK90
1100001DLL_E.OUT_DLL_CLKDV
1100010DLL_E.OUT_DLL_CLK0
1100100DLL_E.OUT_DLL_CLK2X
1101000DLL_W.OUT_DLL_CLKDV
1110000DLL_E.OUT_DLL_CLK270
virtex CLK_N_V switchbox CLK_INT muxes LH_MUX[10]
BitsDestination
CLK[0][5][9]CLK[0][6][9]CLK[0][1][9]CLK[0][2][9]CLK[0][3][9]CLK[0][4][9]CLK[0][0][9]W.LH_MUX[10]
Source
0000000off
0000001E.OUT_BUFGCE_O[0]
0000010E.OUT_BUFGCE_O[1]
0000100E.OUT_CLKPAD[1]
0001000DLL_W.OUT_DLL_CLK2X
0010000DLL_E.OUT_DLL_CLK2X90
0100001DLL_W.OUT_DLL_CLK180
0100010E.OUT_CLKPAD[0]
0100100DLL_E.OUT_DLL_CLK90
0101000DLL_E.OUT_DLL_LOCKED
0110000DLL_W.OUT_DLL_CLK270
1000001DLL_W.OUT_DLL_LOCKED
1000010DLL_E.OUT_DLL_CLK180
1000100DLL_W.OUT_DLL_CLK2X90
1001000DLL_W.OUT_DLL_CLK0
1010000DLL_W.OUT_DLL_CLK90
1100001DLL_E.OUT_DLL_CLKDV
1100010DLL_E.OUT_DLL_CLK0
1100100DLL_E.OUT_DLL_CLK2X
1101000DLL_W.OUT_DLL_CLKDV
1110000DLL_E.OUT_DLL_CLK270
virtex CLK_N_V switchbox CLK_INT muxes IMUX_BUFGCE_CLK[0]
BitsDestination
CLK[0][1][2]CLK[0][4][2]CLK[0][5][2]CLK[0][6][2]CLK[0][3][2]CLK[0][2][2]CLK[0][6][0]CLK[0][0][2]CLK[0][6][3]CLK[0][4][6]E.IMUX_BUFGCE_CLK[0]
Source
0000000000E.OUT_CLKPAD[1]
0000000001E.OUT_CLKPAD[0]
0000000011off
0000000110DLL_E.OUT_DLL_CLK270
0000000111W.HEX_H0[0]
0000001110DLL_W.OUT_DLL_CLK270
0000010010DLL_W.OUT_DLL_CLKDV
0000010011W.HEX_H5[0]
0000011010DLL_W.OUT_DLL_CLK90
0000011011W.HEX_H0[1]
0000100010DLL_E.OUT_DLL_CLK2X
0000100011W.HEX_H1[0]
0000101010DLL_E.OUT_DLL_CLK180
0000101011W.HEX_H4[1]
0001000010DLL_W.OUT_DLL_CLK0
0001000011E.HEX_H3[0]
0001001010DLL_W.OUT_DLL_CLK2X
0001001011W.HEX_H1[1]
0010000010DLL_E.OUT_DLL_CLK0
0010000011W.HEX_H3[0]
0010001010DLL_W.OUT_DLL_CLK2X90
0010001011E.HEX_H3[1]
0100000010DLL_E.OUT_DLL_CLK90
0100000011W.HEX_H4[0]
0100001010DLL_E.OUT_DLL_CLK2X90
0100001011W.HEX_H3[1]
1000000010DLL_E.OUT_DLL_CLKDV
1000001010DLL_W.OUT_DLL_CLK180
1000001011W.HEX_H5[1]
virtex CLK_N_V switchbox CLK_INT muxes IMUX_BUFGCE_CLK[1]
BitsDestination
CLK[0][0][0]CLK[0][3][0]CLK[0][4][0]CLK[0][5][0]CLK[0][2][0]CLK[0][1][0]CLK[0][7][0]CLK[0][7][2]CLK[0][7][3]CLK[0][5][6]E.IMUX_BUFGCE_CLK[1]
Source
0000000000E.OUT_CLKPAD[0]
0000000001E.OUT_CLKPAD[1]
0000000011off
0000000110DLL_E.OUT_DLL_CLK270
0000000111W.HEX_H0[0]
0000001110DLL_W.OUT_DLL_CLK270
0000010010DLL_W.OUT_DLL_CLKDV
0000010011W.HEX_H5[0]
0000011010DLL_W.OUT_DLL_CLK90
0000011011W.HEX_H0[1]
0000100010DLL_E.OUT_DLL_CLK2X
0000100011W.HEX_H1[0]
0000101010DLL_E.OUT_DLL_CLK180
0000101011W.HEX_H4[1]
0001000010DLL_W.OUT_DLL_CLK0
0001000011E.HEX_H3[0]
0001001010DLL_W.OUT_DLL_CLK2X
0001001011W.HEX_H1[1]
0010000010DLL_E.OUT_DLL_CLK0
0010000011W.HEX_H3[0]
0010001010DLL_W.OUT_DLL_CLK2X90
0010001011E.HEX_H3[1]
0100000010DLL_E.OUT_DLL_CLK90
0100000011W.HEX_H4[0]
0100001010DLL_E.OUT_DLL_CLK2X90
0100001011W.HEX_H3[1]
1000000010DLL_E.OUT_DLL_CLKDV
1000001010DLL_W.OUT_DLL_CLK180
1000001011W.HEX_H5[1]
virtex CLK_N_V switchbox CLK_INT muxes IMUX_BUFGCE_CE[0]
BitsDestination
CLK[0][5][4]CLK[0][0][4]CLK[0][3][4]CLK[0][2][4]CLK[0][1][4]CLK[0][7][7]CLK[0][6][7]E.IMUX_BUFGCE_CE[0]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]
virtex CLK_N_V switchbox CLK_INT muxes IMUX_BUFGCE_CE[1]
BitsDestination
CLK[0][4][4]CLK[0][2][7]CLK[0][5][7]CLK[0][4][7]CLK[0][3][7]CLK[0][1][7]CLK[0][0][7]E.IMUX_BUFGCE_CE[1]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]

Bels GCLK_IOB

virtex CLK_N_V bel GCLK_IOB pins
PinDirectionGCLK_IOB[0]GCLK_IOB[1]
IoutE.OUT_CLKPAD[0]E.OUT_CLKPAD[1]
virtex CLK_N_V bel GCLK_IOB attribute bits
AttributeGCLK_IOB[0]GCLK_IOB[1]
DELAY bit 0CLK[0][0][3]CLK[0][5][3]
DELAY bit 1CLK[0][1][3]CLK[0][0][6]
DELAY bit 2CLK[0][2][3]CLK[0][1][6]
DELAY bit 3CLK[0][3][3]CLK[0][7][6]
DELAY bit 4CLK[0][4][3]CLK[0][6][6]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_N_V enum IOB_IBUF_MODE
GCLK_IOB[0].IBUF_MODECLK[1][1][16]CLK[1][0][16]
GCLK_IOB[1].IBUF_MODECLK[1][1][17]CLK[1][0][17]
NONE11
VREF_LV01
VREF_HV10
CMOS00

Bels BUFGCE

virtex CLK_N_V bel BUFGCE pins
PinDirectionBUFGCE[0]BUFGCE[1]
IinE.IMUX_BUFGCE_CLK[0]E.IMUX_BUFGCE_CLK[1]
CEinE.IMUX_BUFGCE_CE[0] invert by CLK[0][6][4]E.IMUX_BUFGCE_CE[1] invert by CLK[0][7][4]
OoutE.OUT_BUFGCE_O[0]E.OUT_BUFGCE_O[1]
virtex CLK_N_V bel BUFGCE attribute bits
AttributeBUFGCE[0]BUFGCE[1]
INIT_OUT bit 0CLK[0][2][6]CLK[0][3][6]

Bel wires

virtex CLK_N_V bel wires
WirePins
E.IMUX_BUFGCE_CLK[0]BUFGCE[0].I
E.IMUX_BUFGCE_CLK[1]BUFGCE[1].I
E.IMUX_BUFGCE_CE[0]BUFGCE[0].CE
E.IMUX_BUFGCE_CE[1]BUFGCE[1].CE
E.OUT_BUFGCE_O[0]BUFGCE[0].O
E.OUT_BUFGCE_O[1]BUFGCE[1].O
E.OUT_CLKPAD[0]GCLK_IOB[0].I
E.OUT_CLKPAD[1]GCLK_IOB[1].I

Bitstream

virtex CLK_N_V rect CLK[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 CLK_INT: mux W.HEX_H0_MUX[0] bit 1 CLK_INT: mux W.HEX_H0_MUX[0] bit 0 CLK_INT: mux W.HEX_H0_MUX[0] bit 2 CLK_INT: mux W.HEX_H0_MUX[0] bit 3 CLK_INT: mux W.HEX_H0_MUX[0] bit 4 CLK_INT: mux W.HEX_H0_MUX[0] bit 6 CLK_INT: mux W.HEX_H0_MUX[0] bit 5 CLK_INT: !buffer W.HEX_H0[0] ← W.HEX_H0_MUX[0]
B16 CLK_INT: mux W.HEX_H0_MUX[1] bit 1 CLK_INT: mux W.HEX_H0_MUX[1] bit 0 CLK_INT: mux W.HEX_H0_MUX[1] bit 2 CLK_INT: mux W.HEX_H0_MUX[1] bit 3 CLK_INT: mux W.HEX_H0_MUX[1] bit 4 CLK_INT: mux W.HEX_H0_MUX[1] bit 6 CLK_INT: mux W.HEX_H0_MUX[1] bit 5 CLK_INT: !buffer W.HEX_H0[1] ← W.HEX_H0_MUX[1]
B15 CLK_INT: mux W.HEX_H0_MUX[2] bit 1 CLK_INT: mux W.HEX_H0_MUX[2] bit 0 CLK_INT: mux W.HEX_H0_MUX[2] bit 2 CLK_INT: mux W.HEX_H0_MUX[2] bit 3 CLK_INT: mux W.HEX_H0_MUX[2] bit 4 CLK_INT: mux W.HEX_H0_MUX[2] bit 6 CLK_INT: mux W.HEX_H0_MUX[2] bit 5 CLK_INT: !buffer W.HEX_H0[2] ← W.HEX_H0_MUX[2]
B14 CLK_INT: mux W.HEX_H0_MUX[3] bit 1 CLK_INT: mux W.HEX_H0_MUX[3] bit 0 CLK_INT: mux W.HEX_H0_MUX[3] bit 2 CLK_INT: mux W.HEX_H0_MUX[3] bit 3 CLK_INT: mux W.HEX_H0_MUX[3] bit 4 CLK_INT: mux W.HEX_H0_MUX[3] bit 6 CLK_INT: mux W.HEX_H0_MUX[3] bit 5 CLK_INT: !buffer W.HEX_H0[3] ← W.HEX_H0_MUX[3]
B13 CLK_INT: mux W.HEX_H5_MUX[0] bit 1 CLK_INT: mux W.HEX_H5_MUX[0] bit 0 CLK_INT: mux W.HEX_H5_MUX[0] bit 2 CLK_INT: mux W.HEX_H5_MUX[0] bit 3 CLK_INT: mux W.HEX_H5_MUX[0] bit 4 CLK_INT: mux W.HEX_H5_MUX[0] bit 6 CLK_INT: mux W.HEX_H5_MUX[0] bit 5 CLK_INT: !buffer W.HEX_H5[0] ← W.HEX_H5_MUX[0]
B12 CLK_INT: mux W.HEX_H5_MUX[1] bit 1 CLK_INT: mux W.HEX_H5_MUX[1] bit 0 CLK_INT: mux W.HEX_H5_MUX[1] bit 2 CLK_INT: mux W.HEX_H5_MUX[1] bit 3 CLK_INT: mux W.HEX_H5_MUX[1] bit 4 CLK_INT: mux W.HEX_H5_MUX[1] bit 6 CLK_INT: mux W.HEX_H5_MUX[1] bit 5 CLK_INT: !buffer W.HEX_H5[1] ← W.HEX_H5_MUX[1]
B11 CLK_INT: mux W.HEX_H5_MUX[2] bit 1 CLK_INT: mux W.HEX_H5_MUX[2] bit 0 CLK_INT: mux W.HEX_H5_MUX[2] bit 2 CLK_INT: mux W.HEX_H5_MUX[2] bit 3 CLK_INT: mux W.HEX_H5_MUX[2] bit 4 CLK_INT: mux W.HEX_H5_MUX[2] bit 6 CLK_INT: mux W.HEX_H5_MUX[2] bit 5 CLK_INT: !buffer W.HEX_H5[2] ← W.HEX_H5_MUX[2]
B10 CLK_INT: mux W.HEX_H5_MUX[3] bit 1 CLK_INT: mux W.HEX_H5_MUX[3] bit 0 CLK_INT: mux W.HEX_H5_MUX[3] bit 2 CLK_INT: mux W.HEX_H5_MUX[3] bit 3 CLK_INT: mux W.HEX_H5_MUX[3] bit 4 CLK_INT: mux W.HEX_H5_MUX[3] bit 6 CLK_INT: mux W.HEX_H5_MUX[3] bit 5 CLK_INT: !buffer W.HEX_H5[3] ← W.HEX_H5_MUX[3]
B9 CLK_INT: mux W.LH_MUX[10] bit 0 CLK_INT: mux W.LH_MUX[10] bit 4 CLK_INT: mux W.LH_MUX[10] bit 3 CLK_INT: mux W.LH_MUX[10] bit 2 CLK_INT: mux W.LH_MUX[10] bit 1 CLK_INT: mux W.LH_MUX[10] bit 6 CLK_INT: mux W.LH_MUX[10] bit 5 CLK_INT: buffer W.LH[10] ← W.LH_MUX[10]
B8 CLK_INT: mux W.LH_MUX[7] bit 0 CLK_INT: mux W.LH_MUX[7] bit 4 CLK_INT: mux W.LH_MUX[7] bit 3 CLK_INT: mux W.LH_MUX[7] bit 2 CLK_INT: mux W.LH_MUX[7] bit 1 CLK_INT: mux W.LH_MUX[7] bit 6 CLK_INT: mux W.LH_MUX[7] bit 5 CLK_INT: buffer W.LH[7] ← W.LH_MUX[7]
B7 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 1
B6 GCLK_IOB[1]: DELAY bit 1 GCLK_IOB[1]: DELAY bit 2 BUFGCE[0]: INIT_OUT bit 0 BUFGCE[1]: INIT_OUT bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 0 GCLK_IOB[1]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 3
B5 CLK_INT: mux W.LH_MUX[1] bit 0 CLK_INT: mux W.LH_MUX[1] bit 4 CLK_INT: mux W.LH_MUX[1] bit 3 CLK_INT: mux W.LH_MUX[1] bit 2 CLK_INT: mux W.LH_MUX[1] bit 1 CLK_INT: mux W.LH_MUX[1] bit 6 CLK_INT: mux W.LH_MUX[1] bit 5 CLK_INT: buffer W.LH[1] ← W.LH_MUX[1]
B4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 6 BUFGCE[0]: invert CE BUFGCE[1]: invert CE
B3 GCLK_IOB[0]: DELAY bit 0 GCLK_IOB[0]: DELAY bit 1 GCLK_IOB[0]: DELAY bit 2 GCLK_IOB[0]: DELAY bit 3 GCLK_IOB[0]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 1
B2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 2
B1 CLK_INT: mux W.LH_MUX[4] bit 0 CLK_INT: mux W.LH_MUX[4] bit 4 CLK_INT: mux W.LH_MUX[4] bit 3 CLK_INT: mux W.LH_MUX[4] bit 2 CLK_INT: mux W.LH_MUX[4] bit 1 CLK_INT: mux W.LH_MUX[4] bit 6 CLK_INT: mux W.LH_MUX[4] bit 5 CLK_INT: buffer W.LH[4] ← W.LH_MUX[4]
B0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 3
virtex CLK_N_V rect CLK[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 GCLK_IOB[1]: IBUF_MODE bit 0 GCLK_IOB[1]: IBUF_MODE bit 1 - - - - - -
B16 GCLK_IOB[0]: IBUF_MODE bit 0 GCLK_IOB[0]: IBUF_MODE bit 1 - - - - - -
B15 - - - - - - - -
B14 - - - - - - - -
B13 - - - - - - - -
B12 - - - - - - - -
B11 - - - - - - - -
B10 - - - - - - - -
B9 - - - - - - - -
B8 - - - - - - - -
B7 - - - - - - - -
B6 - - - - - - - -
B5 - - - - - - - -
B4 - - - - - - - -
B3 - - - - - - - -
B2 - - - - - - - -
B1 - - - - - - - -
B0 - - - - - - - -

Tile CLK_N_VE_4DLL

Cells: 6

Switchbox CLK_INT

virtex CLK_N_VE_4DLL switchbox CLK_INT permanent buffers
DestinationSource
W.GCLK[2]E.OUT_BUFGCE_O[0]
W.GCLK[3]E.OUT_BUFGCE_O[1]
W.GCLK_LEAF[0]W.GCLK[0]
W.GCLK_LEAF[1]W.GCLK[1]
W.GCLK_LEAF[2]W.GCLK[2]
W.GCLK_LEAF[3]W.GCLK[3]
E.GCLK_LEAF[0]W.GCLK[0]
E.GCLK_LEAF[1]W.GCLK[1]
E.GCLK_LEAF[2]W.GCLK[2]
E.GCLK_LEAF[3]W.GCLK[3]
virtex CLK_N_VE_4DLL switchbox CLK_INT programmable buffers
DestinationSourceBit
W.HEX_H0[0]W.HEX_H0_MUX[0]!CLK[0][7][17]
W.HEX_H0[1]W.HEX_H0_MUX[1]!CLK[0][7][16]
W.HEX_H0[2]W.HEX_H0_MUX[2]!CLK[0][7][15]
W.HEX_H0[3]W.HEX_H0_MUX[3]!CLK[0][7][14]
W.HEX_H5[0]W.HEX_H5_MUX[0]!CLK[0][7][13]
W.HEX_H5[1]W.HEX_H5_MUX[1]!CLK[0][7][12]
W.HEX_H5[2]W.HEX_H5_MUX[2]!CLK[0][7][11]
W.HEX_H5[3]W.HEX_H5_MUX[3]!CLK[0][7][10]
W.LH[1]W.LH_MUX[1]CLK[0][7][5]
W.LH[4]W.LH_MUX[4]CLK[0][7][1]
W.LH[7]W.LH_MUX[7]CLK[0][7][8]
W.LH[10]W.LH_MUX[10]CLK[0][7][9]
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes HEX_H0_MUX[0]
BitsDestination
CLK[0][4][17]CLK[0][5][17]CLK[0][1][17]CLK[0][0][17]CLK[0][2][17]CLK[0][3][17]W.HEX_H0_MUX[0]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes HEX_H0_MUX[1]
BitsDestination
CLK[0][4][16]CLK[0][5][16]CLK[0][1][16]CLK[0][0][16]CLK[0][2][16]CLK[0][3][16]W.HEX_H0_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes HEX_H0_MUX[2]
BitsDestination
CLK[0][4][15]CLK[0][5][15]CLK[0][1][15]CLK[0][0][15]CLK[0][2][15]CLK[0][3][15]W.HEX_H0_MUX[2]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes HEX_H0_MUX[3]
BitsDestination
CLK[0][4][14]CLK[0][5][14]CLK[0][1][14]CLK[0][0][14]CLK[0][2][14]CLK[0][3][14]W.HEX_H0_MUX[3]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes HEX_H5_MUX[0]
BitsDestination
CLK[0][4][13]CLK[0][5][13]CLK[0][1][13]CLK[0][0][13]CLK[0][2][13]CLK[0][3][13]W.HEX_H5_MUX[0]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes HEX_H5_MUX[1]
BitsDestination
CLK[0][4][12]CLK[0][5][12]CLK[0][1][12]CLK[0][0][12]CLK[0][2][12]CLK[0][3][12]W.HEX_H5_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes HEX_H5_MUX[2]
BitsDestination
CLK[0][4][11]CLK[0][5][11]CLK[0][1][11]CLK[0][0][11]CLK[0][2][11]CLK[0][3][11]W.HEX_H5_MUX[2]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes HEX_H5_MUX[3]
BitsDestination
CLK[0][4][10]CLK[0][5][10]CLK[0][1][10]CLK[0][0][10]CLK[0][2][10]CLK[0][3][10]W.HEX_H5_MUX[3]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes LH_MUX[1]
BitsDestination
CLK[0][4][5]CLK[0][5][5]CLK[0][1][5]CLK[0][0][5]CLK[0][2][5]CLK[0][3][5]W.LH_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes LH_MUX[4]
BitsDestination
CLK[0][4][1]CLK[0][5][1]CLK[0][1][1]CLK[0][0][1]CLK[0][2][1]CLK[0][3][1]W.LH_MUX[4]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes LH_MUX[7]
BitsDestination
CLK[0][4][8]CLK[0][5][8]CLK[0][1][8]CLK[0][0][8]CLK[0][2][8]CLK[0][3][8]W.LH_MUX[7]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes LH_MUX[10]
BitsDestination
CLK[0][4][9]CLK[0][5][9]CLK[0][1][9]CLK[0][0][9]CLK[0][2][9]CLK[0][3][9]W.LH_MUX[10]
Source
000011E.OUT_CLKPAD[0]
000101DLLP_W.OUT_DLL_CLK2X90
000111E.OUT_BUFGCE_O[0]
001001DLLP_W.OUT_DLL_CLK90
001011DLLP_W.OUT_DLL_CLKDV
001101DLLP_E.OUT_DLL_CLK180
010010DLLS_W.OUT_DLL_CLK2X
010011DLLP_E.OUT_DLL_CLK270
010100DLLS_W.OUT_DLL_CLKDV
010101DLLP_E.OUT_DLL_CLK2X90
010110DLLS_E.OUT_DLL_CLK180
010111DLLP_W.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011001DLLP_E.OUT_DLL_CLK2X
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
011101DLLP_W.OUT_DLL_CLK0
100010DLLS_E.OUT_DLL_CLK2X
100011DLLP_E.OUT_DLL_CLK90
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
100111DLLP_E.OUT_DLL_CLK0
101000DLLS_E.OUT_DLL_CLK90
101001DLLP_W.OUT_DLL_LOCKED
101010DLLS_E.OUT_DLL_CLK2X90
101011DLLP_E.OUT_DLL_LOCKED
101100DLLS_W.OUT_DLL_CLK0
101101DLLP_E.OUT_DLL_CLKDV
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
110110DLLP_W.OUT_DLL_CLK2X
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
111100DLLP_W.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes IMUX_BUFGCE_CLK[0]
BitsDestination
CLK[0][7][0]CLK[0][1][2]CLK[0][4][2]CLK[0][5][2]CLK[0][6][2]CLK[0][3][2]CLK[0][2][2]CLK[0][0][2]CLK[0][6][0]CLK[0][6][3]CLK[0][4][6]E.IMUX_BUFGCE_CLK[0]
Source
00000000000E.OUT_CLKPAD[1]
00000000001E.OUT_CLKPAD[0]
00000000011off
00000001010DLLP_W.OUT_DLL_CLK270
00000001110DLLP_E.OUT_DLL_CLK270
00000001111W.HEX_H0[0]
00000010010DLLP_W.OUT_DLL_CLK90
00000010011W.HEX_H0[1]
00000010110DLLP_W.OUT_DLL_CLKDV
00000010111W.HEX_H5[0]
00000100010DLLP_E.OUT_DLL_CLK180
00000100011W.HEX_H4[1]
00000100110DLLP_E.OUT_DLL_CLK2X
00000100111W.HEX_H1[0]
00001000010DLLP_W.OUT_DLL_CLK2X
00001000011W.HEX_H1[1]
00001000110DLLP_W.OUT_DLL_CLK0
00001000111E.HEX_H3[0]
00010000010DLLP_W.OUT_DLL_CLK2X90
00010000011E.HEX_H3[1]
00010000110DLLP_E.OUT_DLL_CLK0
00010000111W.HEX_H3[0]
00100000010DLLP_E.OUT_DLL_CLK2X90
00100000011W.HEX_H3[1]
00100000110DLLP_E.OUT_DLL_CLK90
00100000111W.HEX_H4[0]
01000000010DLLP_W.OUT_DLL_CLK180
01000000011W.HEX_H5[1]
01000000110DLLP_E.OUT_DLL_CLKDV
10000001010DLLS_W.OUT_DLL_CLK270
10000001011DLLS_E.OUT_DLL_CLK180
10000010010DLLS_W.OUT_DLL_CLK90
10000010011DLLS_E.OUT_DLL_CLKDV
10000100010DLLS_W.OUT_DLL_CLKDV
10000100011DLLS_E.OUT_DLL_CLK2X90
10001000010DLLS_W.OUT_DLL_CLK2X90
10001000011DLLS_E.OUT_DLL_CLK0
10010000010DLLS_W.OUT_DLL_CLK0
10010000011DLLS_E.OUT_DLL_CLK90
10100000010DLLS_W.OUT_DLL_CLK2X
10100000011DLLS_E.OUT_DLL_CLK2X
11000000010DLLS_W.OUT_DLL_CLK180
11000000011DLLS_E.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes IMUX_BUFGCE_CLK[1]
BitsDestination
CLK[0][6][1]CLK[0][0][0]CLK[0][3][0]CLK[0][4][0]CLK[0][5][0]CLK[0][2][0]CLK[0][1][0]CLK[0][7][2]CLK[0][6][5]CLK[0][7][3]CLK[0][5][6]E.IMUX_BUFGCE_CLK[1]
Source
00000000000E.OUT_CLKPAD[0]
00000000001E.OUT_CLKPAD[1]
00000000011off
00000001010DLLP_W.OUT_DLL_CLK270
00000001110DLLP_E.OUT_DLL_CLK270
00000001111W.HEX_H0[0]
00000010010DLLP_W.OUT_DLL_CLK90
00000010011W.HEX_H0[1]
00000010110DLLP_W.OUT_DLL_CLKDV
00000010111W.HEX_H5[0]
00000100010DLLP_E.OUT_DLL_CLK180
00000100011W.HEX_H4[1]
00000100110DLLP_E.OUT_DLL_CLK2X
00000100111W.HEX_H1[0]
00001000010DLLP_W.OUT_DLL_CLK2X
00001000011W.HEX_H1[1]
00001000110DLLP_W.OUT_DLL_CLK0
00001000111E.HEX_H3[0]
00010000010DLLP_W.OUT_DLL_CLK2X90
00010000011E.HEX_H3[1]
00010000110DLLP_E.OUT_DLL_CLK0
00010000111W.HEX_H3[0]
00100000010DLLP_E.OUT_DLL_CLK2X90
00100000011W.HEX_H3[1]
00100000110DLLP_E.OUT_DLL_CLK90
00100000111W.HEX_H4[0]
01000000010DLLP_W.OUT_DLL_CLK180
01000000011W.HEX_H5[1]
01000000110DLLP_E.OUT_DLL_CLKDV
10000001010DLLS_W.OUT_DLL_CLK270
10000001011DLLS_E.OUT_DLL_CLK180
10000010010DLLS_W.OUT_DLL_CLK90
10000010011DLLS_E.OUT_DLL_CLKDV
10000100010DLLS_W.OUT_DLL_CLKDV
10000100011DLLS_E.OUT_DLL_CLK2X90
10001000010DLLS_W.OUT_DLL_CLK2X90
10001000011DLLS_E.OUT_DLL_CLK0
10010000010DLLS_W.OUT_DLL_CLK0
10010000011DLLS_E.OUT_DLL_CLK90
10100000010DLLS_W.OUT_DLL_CLK2X
10100000011DLLS_E.OUT_DLL_CLK2X
11000000010DLLS_W.OUT_DLL_CLK180
11000000011DLLS_E.OUT_DLL_CLK270
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes IMUX_BUFGCE_CE[0]
BitsDestination
CLK[0][5][4]CLK[0][0][4]CLK[0][3][4]CLK[0][2][4]CLK[0][1][4]CLK[0][7][7]CLK[0][6][7]E.IMUX_BUFGCE_CE[0]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]
virtex CLK_N_VE_4DLL switchbox CLK_INT muxes IMUX_BUFGCE_CE[1]
BitsDestination
CLK[0][4][4]CLK[0][2][7]CLK[0][5][7]CLK[0][4][7]CLK[0][3][7]CLK[0][1][7]CLK[0][0][7]E.IMUX_BUFGCE_CE[1]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]

Bels GCLK_IOB

virtex CLK_N_VE_4DLL bel GCLK_IOB pins
PinDirectionGCLK_IOB[0]GCLK_IOB[1]
IoutE.OUT_CLKPAD[0]E.OUT_CLKPAD[1]
virtex CLK_N_VE_4DLL bel GCLK_IOB attribute bits
AttributeGCLK_IOB[0]GCLK_IOB[1]
DELAY bit 0CLK[0][0][3]CLK[0][5][3]
DELAY bit 1CLK[0][1][3]CLK[0][0][6]
DELAY bit 2CLK[0][2][3]CLK[0][1][6]
DELAY bit 3CLK[0][3][3]CLK[0][7][6]
DELAY bit 4CLK[0][4][3]CLK[0][6][6]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_N_VE_4DLL enum IOB_IBUF_MODE
GCLK_IOB[0].IBUF_MODECLK[1][1][16]CLK[1][0][16]
GCLK_IOB[1].IBUF_MODECLK[1][1][17]CLK[1][0][17]
NONE11
VREF01
DIFF10
CMOS00

Bels IOFB

virtex CLK_N_VE_4DLL bel IOFB pins
PinDirectionIOFB[0]IOFB[1]
IoutE.OUT_IOFB[0]E.OUT_IOFB[1]
virtex CLK_N_VE_4DLL bel IOFB attribute bits
AttributeIOFB[0]IOFB[1]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_N_VE_4DLL enum IOB_IBUF_MODE
IOFB[0].IBUF_MODECLK[1][2][16]CLK[1][3][16]
IOFB[1].IBUF_MODECLK[1][2][17]CLK[1][3][17]
NONE11
VREF10
CMOS01

Bels BUFGCE

virtex CLK_N_VE_4DLL bel BUFGCE pins
PinDirectionBUFGCE[0]BUFGCE[1]
IinE.IMUX_BUFGCE_CLK[0]E.IMUX_BUFGCE_CLK[1]
CEinE.IMUX_BUFGCE_CE[0] invert by CLK[0][6][4]E.IMUX_BUFGCE_CE[1] invert by CLK[0][7][4]
OoutE.OUT_BUFGCE_O[0]E.OUT_BUFGCE_O[1]
virtex CLK_N_VE_4DLL bel BUFGCE attribute bits
AttributeBUFGCE[0]BUFGCE[1]
INIT_OUT bit 0CLK[0][2][6]CLK[0][3][6]

Bel wires

virtex CLK_N_VE_4DLL bel wires
WirePins
E.IMUX_BUFGCE_CLK[0]BUFGCE[0].I
E.IMUX_BUFGCE_CLK[1]BUFGCE[1].I
E.IMUX_BUFGCE_CE[0]BUFGCE[0].CE
E.IMUX_BUFGCE_CE[1]BUFGCE[1].CE
E.OUT_BUFGCE_O[0]BUFGCE[0].O
E.OUT_BUFGCE_O[1]BUFGCE[1].O
E.OUT_CLKPAD[0]GCLK_IOB[0].I
E.OUT_CLKPAD[1]GCLK_IOB[1].I
E.OUT_IOFB[0]IOFB[0].I
E.OUT_IOFB[1]IOFB[1].I

Bitstream

virtex CLK_N_VE_4DLL rect CLK[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 CLK_INT: mux W.HEX_H0_MUX[0] bit 2 CLK_INT: mux W.HEX_H0_MUX[0] bit 3 CLK_INT: mux W.HEX_H0_MUX[0] bit 1 CLK_INT: mux W.HEX_H0_MUX[0] bit 0 CLK_INT: mux W.HEX_H0_MUX[0] bit 5 CLK_INT: mux W.HEX_H0_MUX[0] bit 4 - CLK_INT: !buffer W.HEX_H0[0] ← W.HEX_H0_MUX[0]
B16 CLK_INT: mux W.HEX_H0_MUX[1] bit 2 CLK_INT: mux W.HEX_H0_MUX[1] bit 3 CLK_INT: mux W.HEX_H0_MUX[1] bit 1 CLK_INT: mux W.HEX_H0_MUX[1] bit 0 CLK_INT: mux W.HEX_H0_MUX[1] bit 5 CLK_INT: mux W.HEX_H0_MUX[1] bit 4 - CLK_INT: !buffer W.HEX_H0[1] ← W.HEX_H0_MUX[1]
B15 CLK_INT: mux W.HEX_H0_MUX[2] bit 2 CLK_INT: mux W.HEX_H0_MUX[2] bit 3 CLK_INT: mux W.HEX_H0_MUX[2] bit 1 CLK_INT: mux W.HEX_H0_MUX[2] bit 0 CLK_INT: mux W.HEX_H0_MUX[2] bit 5 CLK_INT: mux W.HEX_H0_MUX[2] bit 4 - CLK_INT: !buffer W.HEX_H0[2] ← W.HEX_H0_MUX[2]
B14 CLK_INT: mux W.HEX_H0_MUX[3] bit 2 CLK_INT: mux W.HEX_H0_MUX[3] bit 3 CLK_INT: mux W.HEX_H0_MUX[3] bit 1 CLK_INT: mux W.HEX_H0_MUX[3] bit 0 CLK_INT: mux W.HEX_H0_MUX[3] bit 5 CLK_INT: mux W.HEX_H0_MUX[3] bit 4 - CLK_INT: !buffer W.HEX_H0[3] ← W.HEX_H0_MUX[3]
B13 CLK_INT: mux W.HEX_H5_MUX[0] bit 2 CLK_INT: mux W.HEX_H5_MUX[0] bit 3 CLK_INT: mux W.HEX_H5_MUX[0] bit 1 CLK_INT: mux W.HEX_H5_MUX[0] bit 0 CLK_INT: mux W.HEX_H5_MUX[0] bit 5 CLK_INT: mux W.HEX_H5_MUX[0] bit 4 - CLK_INT: !buffer W.HEX_H5[0] ← W.HEX_H5_MUX[0]
B12 CLK_INT: mux W.HEX_H5_MUX[1] bit 2 CLK_INT: mux W.HEX_H5_MUX[1] bit 3 CLK_INT: mux W.HEX_H5_MUX[1] bit 1 CLK_INT: mux W.HEX_H5_MUX[1] bit 0 CLK_INT: mux W.HEX_H5_MUX[1] bit 5 CLK_INT: mux W.HEX_H5_MUX[1] bit 4 - CLK_INT: !buffer W.HEX_H5[1] ← W.HEX_H5_MUX[1]
B11 CLK_INT: mux W.HEX_H5_MUX[2] bit 2 CLK_INT: mux W.HEX_H5_MUX[2] bit 3 CLK_INT: mux W.HEX_H5_MUX[2] bit 1 CLK_INT: mux W.HEX_H5_MUX[2] bit 0 CLK_INT: mux W.HEX_H5_MUX[2] bit 5 CLK_INT: mux W.HEX_H5_MUX[2] bit 4 - CLK_INT: !buffer W.HEX_H5[2] ← W.HEX_H5_MUX[2]
B10 CLK_INT: mux W.HEX_H5_MUX[3] bit 2 CLK_INT: mux W.HEX_H5_MUX[3] bit 3 CLK_INT: mux W.HEX_H5_MUX[3] bit 1 CLK_INT: mux W.HEX_H5_MUX[3] bit 0 CLK_INT: mux W.HEX_H5_MUX[3] bit 5 CLK_INT: mux W.HEX_H5_MUX[3] bit 4 - CLK_INT: !buffer W.HEX_H5[3] ← W.HEX_H5_MUX[3]
B9 CLK_INT: mux W.LH_MUX[10] bit 2 CLK_INT: mux W.LH_MUX[10] bit 3 CLK_INT: mux W.LH_MUX[10] bit 1 CLK_INT: mux W.LH_MUX[10] bit 0 CLK_INT: mux W.LH_MUX[10] bit 5 CLK_INT: mux W.LH_MUX[10] bit 4 - CLK_INT: buffer W.LH[10] ← W.LH_MUX[10]
B8 CLK_INT: mux W.LH_MUX[7] bit 2 CLK_INT: mux W.LH_MUX[7] bit 3 CLK_INT: mux W.LH_MUX[7] bit 1 CLK_INT: mux W.LH_MUX[7] bit 0 CLK_INT: mux W.LH_MUX[7] bit 5 CLK_INT: mux W.LH_MUX[7] bit 4 - CLK_INT: buffer W.LH[7] ← W.LH_MUX[7]
B7 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 1
B6 GCLK_IOB[1]: DELAY bit 1 GCLK_IOB[1]: DELAY bit 2 BUFGCE[0]: INIT_OUT bit 0 BUFGCE[1]: INIT_OUT bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 0 GCLK_IOB[1]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 3
B5 CLK_INT: mux W.LH_MUX[1] bit 2 CLK_INT: mux W.LH_MUX[1] bit 3 CLK_INT: mux W.LH_MUX[1] bit 1 CLK_INT: mux W.LH_MUX[1] bit 0 CLK_INT: mux W.LH_MUX[1] bit 5 CLK_INT: mux W.LH_MUX[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 2 CLK_INT: buffer W.LH[1] ← W.LH_MUX[1]
B4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 6 BUFGCE[0]: invert CE BUFGCE[1]: invert CE
B3 GCLK_IOB[0]: DELAY bit 0 GCLK_IOB[0]: DELAY bit 1 GCLK_IOB[0]: DELAY bit 2 GCLK_IOB[0]: DELAY bit 3 GCLK_IOB[0]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 1
B2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 3
B1 CLK_INT: mux W.LH_MUX[4] bit 2 CLK_INT: mux W.LH_MUX[4] bit 3 CLK_INT: mux W.LH_MUX[4] bit 1 CLK_INT: mux W.LH_MUX[4] bit 0 CLK_INT: mux W.LH_MUX[4] bit 5 CLK_INT: mux W.LH_MUX[4] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 10 CLK_INT: buffer W.LH[4] ← W.LH_MUX[4]
B0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 10
virtex CLK_N_VE_4DLL rect CLK[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 GCLK_IOB[1]: IBUF_MODE bit 0 GCLK_IOB[1]: IBUF_MODE bit 1 IOFB[1]: IBUF_MODE bit 1 IOFB[1]: IBUF_MODE bit 0 - - - -
B16 GCLK_IOB[0]: IBUF_MODE bit 0 GCLK_IOB[0]: IBUF_MODE bit 1 IOFB[0]: IBUF_MODE bit 1 IOFB[0]: IBUF_MODE bit 0 - - - -
B15 - - - - - - - -
B14 - - - - - - - -
B13 - - - - - - - -
B12 - - - - - - - -
B11 - - - - - - - -
B10 - - - - - - - -
B9 - - - - - - - -
B8 - - - - - - - -
B7 - - - - - - - -
B6 - - - - - - - -
B5 - - - - - - - -
B4 - - - - - - - -
B3 - - - - - - - -
B2 - - - - - - - -
B1 - - - - - - - -
B0 - - - - - - - -

Tile CLK_N_VE_2DLL

Cells: 6

Switchbox CLK_INT

virtex CLK_N_VE_2DLL switchbox CLK_INT permanent buffers
DestinationSource
W.GCLK[2]E.OUT_BUFGCE_O[0]
W.GCLK[3]E.OUT_BUFGCE_O[1]
W.GCLK_LEAF[0]W.GCLK[0]
W.GCLK_LEAF[1]W.GCLK[1]
W.GCLK_LEAF[2]W.GCLK[2]
W.GCLK_LEAF[3]W.GCLK[3]
E.GCLK_LEAF[0]W.GCLK[0]
E.GCLK_LEAF[1]W.GCLK[1]
E.GCLK_LEAF[2]W.GCLK[2]
E.GCLK_LEAF[3]W.GCLK[3]
virtex CLK_N_VE_2DLL switchbox CLK_INT programmable buffers
DestinationSourceBit
W.HEX_H0[0]W.HEX_H0_MUX[0]!CLK[0][7][17]
W.HEX_H0[1]W.HEX_H0_MUX[1]!CLK[0][7][16]
W.HEX_H0[2]W.HEX_H0_MUX[2]!CLK[0][7][15]
W.HEX_H0[3]W.HEX_H0_MUX[3]!CLK[0][7][14]
W.HEX_H5[0]W.HEX_H5_MUX[0]!CLK[0][7][13]
W.HEX_H5[1]W.HEX_H5_MUX[1]!CLK[0][7][12]
W.HEX_H5[2]W.HEX_H5_MUX[2]!CLK[0][7][11]
W.HEX_H5[3]W.HEX_H5_MUX[3]!CLK[0][7][10]
W.LH[1]W.LH_MUX[1]CLK[0][7][5]
W.LH[4]W.LH_MUX[4]CLK[0][7][1]
W.LH[7]W.LH_MUX[7]CLK[0][7][8]
W.LH[10]W.LH_MUX[10]CLK[0][7][9]
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes HEX_H0_MUX[0]
BitsDestination
CLK[0][4][17]CLK[0][5][17]CLK[0][1][17]CLK[0][0][17]CLK[0][2][17]CLK[0][3][17]W.HEX_H0_MUX[0]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes HEX_H0_MUX[1]
BitsDestination
CLK[0][4][16]CLK[0][5][16]CLK[0][1][16]CLK[0][0][16]CLK[0][2][16]CLK[0][3][16]W.HEX_H0_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes HEX_H0_MUX[2]
BitsDestination
CLK[0][4][15]CLK[0][5][15]CLK[0][1][15]CLK[0][0][15]CLK[0][2][15]CLK[0][3][15]W.HEX_H0_MUX[2]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes HEX_H0_MUX[3]
BitsDestination
CLK[0][4][14]CLK[0][5][14]CLK[0][1][14]CLK[0][0][14]CLK[0][2][14]CLK[0][3][14]W.HEX_H0_MUX[3]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes HEX_H5_MUX[0]
BitsDestination
CLK[0][4][13]CLK[0][5][13]CLK[0][1][13]CLK[0][0][13]CLK[0][2][13]CLK[0][3][13]W.HEX_H5_MUX[0]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes HEX_H5_MUX[1]
BitsDestination
CLK[0][4][12]CLK[0][5][12]CLK[0][1][12]CLK[0][0][12]CLK[0][2][12]CLK[0][3][12]W.HEX_H5_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes HEX_H5_MUX[2]
BitsDestination
CLK[0][4][11]CLK[0][5][11]CLK[0][1][11]CLK[0][0][11]CLK[0][2][11]CLK[0][3][11]W.HEX_H5_MUX[2]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes HEX_H5_MUX[3]
BitsDestination
CLK[0][4][10]CLK[0][5][10]CLK[0][1][10]CLK[0][0][10]CLK[0][2][10]CLK[0][3][10]W.HEX_H5_MUX[3]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes LH_MUX[1]
BitsDestination
CLK[0][4][5]CLK[0][5][5]CLK[0][1][5]CLK[0][0][5]CLK[0][2][5]CLK[0][3][5]W.LH_MUX[1]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes LH_MUX[4]
BitsDestination
CLK[0][4][1]CLK[0][5][1]CLK[0][1][1]CLK[0][0][1]CLK[0][2][1]CLK[0][3][1]W.LH_MUX[4]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes LH_MUX[7]
BitsDestination
CLK[0][4][8]CLK[0][5][8]CLK[0][1][8]CLK[0][0][8]CLK[0][2][8]CLK[0][3][8]W.LH_MUX[7]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes LH_MUX[10]
BitsDestination
CLK[0][4][9]CLK[0][5][9]CLK[0][1][9]CLK[0][0][9]CLK[0][2][9]CLK[0][3][9]W.LH_MUX[10]
Source
000011E.OUT_CLKPAD[0]
000111E.OUT_BUFGCE_O[0]
010010DLLS_W.OUT_DLL_CLK2X
010100DLLS_W.OUT_DLL_CLKDV
010110DLLS_E.OUT_DLL_CLK180
011000DLLS_W.OUT_DLL_CLK270
011010DLLS_W.OUT_DLL_CLK90
011011E.OUT_BUFGCE_O[1]
011100DLLS_E.OUT_DLL_CLK270
100010DLLS_E.OUT_DLL_CLK2X
100100DLLS_W.OUT_DLL_CLK2X90
100101E.OUT_CLKPAD[1]
100110DLLS_W.OUT_DLL_CLK180
101000DLLS_E.OUT_DLL_CLK90
101010DLLS_E.OUT_DLL_CLK2X90
101100DLLS_W.OUT_DLL_CLK0
110010DLLS_E.OUT_DLL_LOCKED
110100DLLS_E.OUT_DLL_CLKDV
111000DLLS_W.OUT_DLL_LOCKED
111010DLLS_E.OUT_DLL_CLK0
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes IMUX_BUFGCE_CLK[0]
BitsDestination
CLK[0][7][0]CLK[0][1][2]CLK[0][4][2]CLK[0][5][2]CLK[0][6][2]CLK[0][3][2]CLK[0][2][2]CLK[0][0][2]CLK[0][6][0]CLK[0][6][3]CLK[0][4][6]E.IMUX_BUFGCE_CLK[0]
Source
00000000000E.OUT_CLKPAD[1]
00000000001E.OUT_CLKPAD[0]
00000000011off
00000001111W.HEX_H0[0]
00000010011W.HEX_H0[1]
00000010111W.HEX_H5[0]
00000100011W.HEX_H4[1]
00000100111W.HEX_H1[0]
00001000011W.HEX_H1[1]
00001000111E.HEX_H3[0]
00010000011E.HEX_H3[1]
00010000111W.HEX_H3[0]
00100000011W.HEX_H3[1]
00100000111W.HEX_H4[0]
01000000011W.HEX_H5[1]
10000001010DLLS_W.OUT_DLL_CLK270
10000001011DLLS_E.OUT_DLL_CLK180
10000010010DLLS_W.OUT_DLL_CLK90
10000010011DLLS_E.OUT_DLL_CLKDV
10000100010DLLS_W.OUT_DLL_CLKDV
10000100011DLLS_E.OUT_DLL_CLK2X90
10001000010DLLS_W.OUT_DLL_CLK2X90
10001000011DLLS_E.OUT_DLL_CLK0
10010000010DLLS_W.OUT_DLL_CLK0
10010000011DLLS_E.OUT_DLL_CLK90
10100000010DLLS_W.OUT_DLL_CLK2X
10100000011DLLS_E.OUT_DLL_CLK2X
11000000010DLLS_W.OUT_DLL_CLK180
11000000011DLLS_E.OUT_DLL_CLK270
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes IMUX_BUFGCE_CLK[1]
BitsDestination
CLK[0][6][1]CLK[0][0][0]CLK[0][3][0]CLK[0][4][0]CLK[0][5][0]CLK[0][2][0]CLK[0][1][0]CLK[0][7][2]CLK[0][6][5]CLK[0][7][3]CLK[0][5][6]E.IMUX_BUFGCE_CLK[1]
Source
00000000000E.OUT_CLKPAD[0]
00000000001E.OUT_CLKPAD[1]
00000000011off
00000001111W.HEX_H0[0]
00000010011W.HEX_H0[1]
00000010111W.HEX_H5[0]
00000100011W.HEX_H4[1]
00000100111W.HEX_H1[0]
00001000011W.HEX_H1[1]
00001000111E.HEX_H3[0]
00010000011E.HEX_H3[1]
00010000111W.HEX_H3[0]
00100000011W.HEX_H3[1]
00100000111W.HEX_H4[0]
01000000011W.HEX_H5[1]
10000001010DLLS_W.OUT_DLL_CLK270
10000001011DLLS_E.OUT_DLL_CLK180
10000010010DLLS_W.OUT_DLL_CLK90
10000010011DLLS_E.OUT_DLL_CLKDV
10000100010DLLS_W.OUT_DLL_CLKDV
10000100011DLLS_E.OUT_DLL_CLK2X90
10001000010DLLS_W.OUT_DLL_CLK2X90
10001000011DLLS_E.OUT_DLL_CLK0
10010000010DLLS_W.OUT_DLL_CLK0
10010000011DLLS_E.OUT_DLL_CLK90
10100000010DLLS_W.OUT_DLL_CLK2X
10100000011DLLS_E.OUT_DLL_CLK2X
11000000010DLLS_W.OUT_DLL_CLK180
11000000011DLLS_E.OUT_DLL_CLK270
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes IMUX_BUFGCE_CE[0]
BitsDestination
CLK[0][5][4]CLK[0][0][4]CLK[0][3][4]CLK[0][2][4]CLK[0][1][4]CLK[0][7][7]CLK[0][6][7]E.IMUX_BUFGCE_CE[0]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]
virtex CLK_N_VE_2DLL switchbox CLK_INT muxes IMUX_BUFGCE_CE[1]
BitsDestination
CLK[0][4][4]CLK[0][2][7]CLK[0][5][7]CLK[0][4][7]CLK[0][3][7]CLK[0][1][7]CLK[0][0][7]E.IMUX_BUFGCE_CE[1]
Source
0000000E.PULLUP
0000001W.HEX_H0[2]
0000010W.HEX_H1[2]
0000100W.HEX_H3[2]
0001000W.HEX_H4[2]
0010000W.HEX_H5[2]
0100000E.HEX_H3[2]
1000001W.HEX_H0[3]
1000010W.HEX_H1[3]
1000100W.HEX_H3[3]
1001000W.HEX_H4[3]
1010000W.HEX_H5[3]
1100000E.HEX_H3[3]

Bels GCLK_IOB

virtex CLK_N_VE_2DLL bel GCLK_IOB pins
PinDirectionGCLK_IOB[0]GCLK_IOB[1]
IoutE.OUT_CLKPAD[0]E.OUT_CLKPAD[1]
virtex CLK_N_VE_2DLL bel GCLK_IOB attribute bits
AttributeGCLK_IOB[0]GCLK_IOB[1]
DELAY bit 0CLK[0][0][3]CLK[0][5][3]
DELAY bit 1CLK[0][1][3]CLK[0][0][6]
DELAY bit 2CLK[0][2][3]CLK[0][1][6]
DELAY bit 3CLK[0][3][3]CLK[0][7][6]
DELAY bit 4CLK[0][4][3]CLK[0][6][6]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_N_VE_2DLL enum IOB_IBUF_MODE
GCLK_IOB[0].IBUF_MODECLK[1][1][16]CLK[1][0][16]
GCLK_IOB[1].IBUF_MODECLK[1][1][17]CLK[1][0][17]
NONE11
VREF01
DIFF10
CMOS00

Bels IOFB

virtex CLK_N_VE_2DLL bel IOFB pins
PinDirectionIOFB[0]IOFB[1]
IoutE.OUT_IOFB[0]E.OUT_IOFB[1]
virtex CLK_N_VE_2DLL bel IOFB attribute bits
AttributeIOFB[0]IOFB[1]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
virtex CLK_N_VE_2DLL enum IOB_IBUF_MODE
IOFB[0].IBUF_MODECLK[1][2][16]CLK[1][3][16]
IOFB[1].IBUF_MODECLK[1][2][17]CLK[1][3][17]
NONE11
VREF10
CMOS01

Bels BUFGCE

virtex CLK_N_VE_2DLL bel BUFGCE pins
PinDirectionBUFGCE[0]BUFGCE[1]
IinE.IMUX_BUFGCE_CLK[0]E.IMUX_BUFGCE_CLK[1]
CEinE.IMUX_BUFGCE_CE[0] invert by CLK[0][6][4]E.IMUX_BUFGCE_CE[1] invert by CLK[0][7][4]
OoutE.OUT_BUFGCE_O[0]E.OUT_BUFGCE_O[1]
virtex CLK_N_VE_2DLL bel BUFGCE attribute bits
AttributeBUFGCE[0]BUFGCE[1]
INIT_OUT bit 0CLK[0][2][6]CLK[0][3][6]

Bel wires

virtex CLK_N_VE_2DLL bel wires
WirePins
E.IMUX_BUFGCE_CLK[0]BUFGCE[0].I
E.IMUX_BUFGCE_CLK[1]BUFGCE[1].I
E.IMUX_BUFGCE_CE[0]BUFGCE[0].CE
E.IMUX_BUFGCE_CE[1]BUFGCE[1].CE
E.OUT_BUFGCE_O[0]BUFGCE[0].O
E.OUT_BUFGCE_O[1]BUFGCE[1].O
E.OUT_CLKPAD[0]GCLK_IOB[0].I
E.OUT_CLKPAD[1]GCLK_IOB[1].I
E.OUT_IOFB[0]IOFB[0].I
E.OUT_IOFB[1]IOFB[1].I

Bitstream

virtex CLK_N_VE_2DLL rect CLK[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 CLK_INT: mux W.HEX_H0_MUX[0] bit 2 CLK_INT: mux W.HEX_H0_MUX[0] bit 3 CLK_INT: mux W.HEX_H0_MUX[0] bit 1 CLK_INT: mux W.HEX_H0_MUX[0] bit 0 CLK_INT: mux W.HEX_H0_MUX[0] bit 5 CLK_INT: mux W.HEX_H0_MUX[0] bit 4 - CLK_INT: !buffer W.HEX_H0[0] ← W.HEX_H0_MUX[0]
B16 CLK_INT: mux W.HEX_H0_MUX[1] bit 2 CLK_INT: mux W.HEX_H0_MUX[1] bit 3 CLK_INT: mux W.HEX_H0_MUX[1] bit 1 CLK_INT: mux W.HEX_H0_MUX[1] bit 0 CLK_INT: mux W.HEX_H0_MUX[1] bit 5 CLK_INT: mux W.HEX_H0_MUX[1] bit 4 - CLK_INT: !buffer W.HEX_H0[1] ← W.HEX_H0_MUX[1]
B15 CLK_INT: mux W.HEX_H0_MUX[2] bit 2 CLK_INT: mux W.HEX_H0_MUX[2] bit 3 CLK_INT: mux W.HEX_H0_MUX[2] bit 1 CLK_INT: mux W.HEX_H0_MUX[2] bit 0 CLK_INT: mux W.HEX_H0_MUX[2] bit 5 CLK_INT: mux W.HEX_H0_MUX[2] bit 4 - CLK_INT: !buffer W.HEX_H0[2] ← W.HEX_H0_MUX[2]
B14 CLK_INT: mux W.HEX_H0_MUX[3] bit 2 CLK_INT: mux W.HEX_H0_MUX[3] bit 3 CLK_INT: mux W.HEX_H0_MUX[3] bit 1 CLK_INT: mux W.HEX_H0_MUX[3] bit 0 CLK_INT: mux W.HEX_H0_MUX[3] bit 5 CLK_INT: mux W.HEX_H0_MUX[3] bit 4 - CLK_INT: !buffer W.HEX_H0[3] ← W.HEX_H0_MUX[3]
B13 CLK_INT: mux W.HEX_H5_MUX[0] bit 2 CLK_INT: mux W.HEX_H5_MUX[0] bit 3 CLK_INT: mux W.HEX_H5_MUX[0] bit 1 CLK_INT: mux W.HEX_H5_MUX[0] bit 0 CLK_INT: mux W.HEX_H5_MUX[0] bit 5 CLK_INT: mux W.HEX_H5_MUX[0] bit 4 - CLK_INT: !buffer W.HEX_H5[0] ← W.HEX_H5_MUX[0]
B12 CLK_INT: mux W.HEX_H5_MUX[1] bit 2 CLK_INT: mux W.HEX_H5_MUX[1] bit 3 CLK_INT: mux W.HEX_H5_MUX[1] bit 1 CLK_INT: mux W.HEX_H5_MUX[1] bit 0 CLK_INT: mux W.HEX_H5_MUX[1] bit 5 CLK_INT: mux W.HEX_H5_MUX[1] bit 4 - CLK_INT: !buffer W.HEX_H5[1] ← W.HEX_H5_MUX[1]
B11 CLK_INT: mux W.HEX_H5_MUX[2] bit 2 CLK_INT: mux W.HEX_H5_MUX[2] bit 3 CLK_INT: mux W.HEX_H5_MUX[2] bit 1 CLK_INT: mux W.HEX_H5_MUX[2] bit 0 CLK_INT: mux W.HEX_H5_MUX[2] bit 5 CLK_INT: mux W.HEX_H5_MUX[2] bit 4 - CLK_INT: !buffer W.HEX_H5[2] ← W.HEX_H5_MUX[2]
B10 CLK_INT: mux W.HEX_H5_MUX[3] bit 2 CLK_INT: mux W.HEX_H5_MUX[3] bit 3 CLK_INT: mux W.HEX_H5_MUX[3] bit 1 CLK_INT: mux W.HEX_H5_MUX[3] bit 0 CLK_INT: mux W.HEX_H5_MUX[3] bit 5 CLK_INT: mux W.HEX_H5_MUX[3] bit 4 - CLK_INT: !buffer W.HEX_H5[3] ← W.HEX_H5_MUX[3]
B9 CLK_INT: mux W.LH_MUX[10] bit 2 CLK_INT: mux W.LH_MUX[10] bit 3 CLK_INT: mux W.LH_MUX[10] bit 1 CLK_INT: mux W.LH_MUX[10] bit 0 CLK_INT: mux W.LH_MUX[10] bit 5 CLK_INT: mux W.LH_MUX[10] bit 4 - CLK_INT: buffer W.LH[10] ← W.LH_MUX[10]
B8 CLK_INT: mux W.LH_MUX[7] bit 2 CLK_INT: mux W.LH_MUX[7] bit 3 CLK_INT: mux W.LH_MUX[7] bit 1 CLK_INT: mux W.LH_MUX[7] bit 0 CLK_INT: mux W.LH_MUX[7] bit 5 CLK_INT: mux W.LH_MUX[7] bit 4 - CLK_INT: buffer W.LH[7] ← W.LH_MUX[7]
B7 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 1
B6 GCLK_IOB[1]: DELAY bit 1 GCLK_IOB[1]: DELAY bit 2 BUFGCE[0]: INIT_OUT bit 0 BUFGCE[1]: INIT_OUT bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 0 GCLK_IOB[1]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 3
B5 CLK_INT: mux W.LH_MUX[1] bit 2 CLK_INT: mux W.LH_MUX[1] bit 3 CLK_INT: mux W.LH_MUX[1] bit 1 CLK_INT: mux W.LH_MUX[1] bit 0 CLK_INT: mux W.LH_MUX[1] bit 5 CLK_INT: mux W.LH_MUX[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 2 CLK_INT: buffer W.LH[1] ← W.LH_MUX[1]
B4 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CE[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CE[0] bit 6 BUFGCE[0]: invert CE BUFGCE[1]: invert CE
B3 GCLK_IOB[0]: DELAY bit 0 GCLK_IOB[0]: DELAY bit 1 GCLK_IOB[0]: DELAY bit 2 GCLK_IOB[0]: DELAY bit 3 GCLK_IOB[0]: DELAY bit 4 GCLK_IOB[1]: DELAY bit 0 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 1 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 1
B2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 3 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 3
B1 CLK_INT: mux W.LH_MUX[4] bit 2 CLK_INT: mux W.LH_MUX[4] bit 3 CLK_INT: mux W.LH_MUX[4] bit 1 CLK_INT: mux W.LH_MUX[4] bit 0 CLK_INT: mux W.LH_MUX[4] bit 5 CLK_INT: mux W.LH_MUX[4] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 10 CLK_INT: buffer W.LH[4] ← W.LH_MUX[4]
B0 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 9 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 4 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 5 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 8 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 7 CLK_INT: mux E.IMUX_BUFGCE_CLK[1] bit 6 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 2 CLK_INT: mux E.IMUX_BUFGCE_CLK[0] bit 10
virtex CLK_N_VE_2DLL rect CLK[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7
B17 GCLK_IOB[1]: IBUF_MODE bit 0 GCLK_IOB[1]: IBUF_MODE bit 1 IOFB[1]: IBUF_MODE bit 1 IOFB[1]: IBUF_MODE bit 0 - - - -
B16 GCLK_IOB[0]: IBUF_MODE bit 0 GCLK_IOB[0]: IBUF_MODE bit 1 IOFB[0]: IBUF_MODE bit 1 IOFB[0]: IBUF_MODE bit 0 - - - -
B15 - - - - - - - -
B14 - - - - - - - -
B13 - - - - - - - -
B12 - - - - - - - -
B11 - - - - - - - -
B10 - - - - - - - -
B9 - - - - - - - -
B8 - - - - - - - -
B7 - - - - - - - -
B6 - - - - - - - -
B5 - - - - - - - -
B4 - - - - - - - -
B3 - - - - - - - -
B2 - - - - - - - -
B1 - - - - - - - -
B0 - - - - - - - -

Tile CLKV_CLKV

Cells: 2

Switchbox CLK_INT

virtex CLKV_CLKV switchbox CLK_INT programmable buffers
DestinationSourceBit
W.GCLK_LEAF[0]W.GCLK[0]CLKV[0][8]
W.GCLK_LEAF[1]W.GCLK[1]CLKV[0][5]
W.GCLK_LEAF[2]W.GCLK[2]CLKV[0][11]
W.GCLK_LEAF[3]W.GCLK[3]CLKV[0][9]
E.GCLK_LEAF[0]W.GCLK[0]CLKV[0][6]
E.GCLK_LEAF[1]W.GCLK[1]CLKV[0][7]
E.GCLK_LEAF[2]W.GCLK[2]CLKV[0][12]
E.GCLK_LEAF[3]W.GCLK[3]CLKV[0][10]

Bitstream

virtex CLKV_CLKV rect CLKV
BitFrame
F0
B17 -
B16 -
B15 -
B14 -
B13 -
B12 CLK_INT: buffer E.GCLK_LEAF[2] ← W.GCLK[2]
B11 CLK_INT: buffer W.GCLK_LEAF[2] ← W.GCLK[2]
B10 CLK_INT: buffer E.GCLK_LEAF[3] ← W.GCLK[3]
B9 CLK_INT: buffer W.GCLK_LEAF[3] ← W.GCLK[3]
B8 CLK_INT: buffer W.GCLK_LEAF[0] ← W.GCLK[0]
B7 CLK_INT: buffer E.GCLK_LEAF[1] ← W.GCLK[1]
B6 CLK_INT: buffer E.GCLK_LEAF[0] ← W.GCLK[0]
B5 CLK_INT: buffer W.GCLK_LEAF[1] ← W.GCLK[1]
B4 -
B3 -
B2 -
B1 -
B0 -

Tile CLKV_GCLKV

Cells: 2

Switchbox CLK_INT

virtex CLKV_GCLKV switchbox CLK_INT programmable buffers
DestinationSourceBit
W.GCLK_LEAF[0]W.GCLK[0]CLKV[0][5]
W.GCLK_LEAF[1]W.GCLK[1]CLKV[0][7]
W.GCLK_LEAF[2]W.GCLK[2]CLKV[0][9]
W.GCLK_LEAF[3]W.GCLK[3]CLKV[0][11]
E.GCLK_LEAF[0]W.GCLK[0]CLKV[0][6]
E.GCLK_LEAF[1]W.GCLK[1]CLKV[0][8]
E.GCLK_LEAF[2]W.GCLK[2]CLKV[0][10]
E.GCLK_LEAF[3]W.GCLK[3]CLKV[0][12]

Bitstream

virtex CLKV_GCLKV rect CLKV
BitFrame
F0
B17 -
B16 -
B15 -
B14 -
B13 -
B12 CLK_INT: buffer E.GCLK_LEAF[3] ← W.GCLK[3]
B11 CLK_INT: buffer W.GCLK_LEAF[3] ← W.GCLK[3]
B10 CLK_INT: buffer E.GCLK_LEAF[2] ← W.GCLK[2]
B9 CLK_INT: buffer W.GCLK_LEAF[2] ← W.GCLK[2]
B8 CLK_INT: buffer E.GCLK_LEAF[1] ← W.GCLK[1]
B7 CLK_INT: buffer W.GCLK_LEAF[1] ← W.GCLK[1]
B6 CLK_INT: buffer E.GCLK_LEAF[0] ← W.GCLK[0]
B5 CLK_INT: buffer W.GCLK_LEAF[0] ← W.GCLK[0]
B4 -
B3 -
B2 -
B1 -
B0 -

Tile CLKV_BRAM_S

Cells: 2

Switchbox CLK_INT

virtex CLKV_BRAM_S switchbox CLK_INT permanent buffers
DestinationSource
W.GCLK_LEAF[0]W.GCLK[0]
W.GCLK_LEAF[1]W.GCLK[1]
W.GCLK_LEAF[2]W.GCLK[2]
W.GCLK_LEAF[3]W.GCLK[3]
E.GCLK_LEAF[0]W.GCLK[0]
E.GCLK_LEAF[1]W.GCLK[1]
E.GCLK_LEAF[2]W.GCLK[2]
E.GCLK_LEAF[3]W.GCLK[3]

Bitstream

virtex CLKV_BRAM_S rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLKV_BRAM_N

Cells: 2

Switchbox CLK_INT

virtex CLKV_BRAM_N switchbox CLK_INT permanent buffers
DestinationSource
W.GCLK_LEAF[0]W.GCLK[0]
W.GCLK_LEAF[1]W.GCLK[1]
W.GCLK_LEAF[2]W.GCLK[2]
W.GCLK_LEAF[3]W.GCLK[3]
E.GCLK_LEAF[0]W.GCLK[0]
E.GCLK_LEAF[1]W.GCLK[1]
E.GCLK_LEAF[2]W.GCLK[2]
E.GCLK_LEAF[3]W.GCLK[3]

Bitstream

virtex CLKV_BRAM_N rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLKV_BRAM_S_S2

Cells: 2

Switchbox CLK_INT

virtex CLKV_BRAM_S_S2 switchbox CLK_INT programmable buffers
DestinationSourceBit
W.GCLK_LEAF[0]W.GCLK[0]!MAIN[5][13]
W.GCLK_LEAF[1]W.GCLK[1]!MAIN[6][13]
W.GCLK_LEAF[2]W.GCLK[2]!MAIN[7][13]
W.GCLK_LEAF[3]W.GCLK[3]!MAIN[8][13]
E.GCLK_LEAF[0]W.GCLK[0]!MAIN[9][13]
E.GCLK_LEAF[1]W.GCLK[1]!MAIN[10][13]
E.GCLK_LEAF[2]W.GCLK[2]!MAIN[11][13]
E.GCLK_LEAF[3]W.GCLK[3]!MAIN[12][13]

Bitstream

virtex CLKV_BRAM_S_S2 rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - CLK_INT: !buffer W.GCLK_LEAF[0] ← W.GCLK[0] CLK_INT: !buffer W.GCLK_LEAF[1] ← W.GCLK[1] CLK_INT: !buffer W.GCLK_LEAF[2] ← W.GCLK[2] CLK_INT: !buffer W.GCLK_LEAF[3] ← W.GCLK[3] CLK_INT: !buffer E.GCLK_LEAF[0] ← W.GCLK[0] CLK_INT: !buffer E.GCLK_LEAF[1] ← W.GCLK[1] CLK_INT: !buffer E.GCLK_LEAF[2] ← W.GCLK[2] CLK_INT: !buffer E.GCLK_LEAF[3] ← W.GCLK[3] - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLKV_BRAM_N_S2

Cells: 2

Switchbox CLK_INT

virtex CLKV_BRAM_N_S2 switchbox CLK_INT programmable buffers
DestinationSourceBit
W.GCLK_LEAF[0]W.GCLK[0]!MAIN[5][13]
W.GCLK_LEAF[1]W.GCLK[1]!MAIN[6][13]
W.GCLK_LEAF[2]W.GCLK[2]!MAIN[7][13]
W.GCLK_LEAF[3]W.GCLK[3]!MAIN[8][13]
E.GCLK_LEAF[0]W.GCLK[0]!MAIN[9][13]
E.GCLK_LEAF[1]W.GCLK[1]!MAIN[10][13]
E.GCLK_LEAF[2]W.GCLK[2]!MAIN[11][13]
E.GCLK_LEAF[3]W.GCLK[3]!MAIN[12][13]

Bitstream

virtex CLKV_BRAM_N_S2 rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - CLK_INT: !buffer W.GCLK_LEAF[0] ← W.GCLK[0] CLK_INT: !buffer W.GCLK_LEAF[1] ← W.GCLK[1] CLK_INT: !buffer W.GCLK_LEAF[2] ← W.GCLK[2] CLK_INT: !buffer W.GCLK_LEAF[3] ← W.GCLK[3] CLK_INT: !buffer E.GCLK_LEAF[0] ← W.GCLK[0] CLK_INT: !buffer E.GCLK_LEAF[1] ← W.GCLK[1] CLK_INT: !buffer E.GCLK_LEAF[2] ← W.GCLK[2] CLK_INT: !buffer E.GCLK_LEAF[3] ← W.GCLK[3] - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLKV_IO

Cells: 2

Switchbox CLK_INT

virtex CLKV_IO switchbox CLK_INT
DestinationSourceKind
W.GCLK_LEAF[0]W.GCLK[0]fixed buffer
W.GCLK_LEAF[1]W.GCLK[1]fixed buffer
W.GCLK_LEAF[2]W.GCLK[2]fixed buffer
W.GCLK_LEAF[3]W.GCLK[3]fixed buffer
E.GCLK_LEAF[0]W.GCLK[0]fixed buffer
E.GCLK_LEAF[1]W.GCLK[1]fixed buffer
E.GCLK_LEAF[2]W.GCLK[2]fixed buffer
E.GCLK_LEAF[3]W.GCLK[3]fixed buffer