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South-east

Tile CNR_SE

Cells: 1

Switchbox INT

virtex CNR_SE switchbox INT programmable buffers
DestinationSourceBit
HEX_H1[0]HEX_H1_MUX[0]MAIN[35][4]
HEX_H1[1]HEX_H1_MUX[1]MAIN[30][4]
HEX_H1[2]HEX_H1_MUX[2]MAIN[17][4]
HEX_H1[3]HEX_H1_MUX[3]MAIN[12][4]
HEX_H1[4]HEX_H1_MUX[4]MAIN[2][9]
HEX_H1[5]HEX_H1_MUX[5]MAIN[0][9]
HEX_H2[0]HEX_H2_MUX[0]MAIN[29][4]
HEX_H2[1]HEX_H2_MUX[1]MAIN[24][4]
HEX_H2[2]HEX_H2_MUX[2]MAIN[11][4]
HEX_H2[3]HEX_H2_MUX[3]MAIN[6][4]
HEX_H2[4]HEX_H2_MUX[4]MAIN[5][9]
HEX_H2[5]HEX_H2_MUX[5]MAIN[3][9]
HEX_H3[0]HEX_H3_MUX[0]MAIN[23][4]
HEX_H3[1]HEX_H3_MUX[1]MAIN[18][4]
HEX_H3[2]HEX_H3_MUX[2]MAIN[5][4]
HEX_H3[3]HEX_H3_MUX[3]MAIN[0][4]
HEX_H3[4]HEX_H3_MUX[4]MAIN[8][9]
HEX_H3[5]HEX_H3_MUX[5]MAIN[6][9]
HEX_H4[0]HEX_H4_MUX[0]MAIN[35][8]
HEX_H4[1]HEX_H4_MUX[1]MAIN[30][8]
HEX_H4[2]HEX_H4_MUX[2]MAIN[17][8]
HEX_H4[3]HEX_H4_MUX[3]MAIN[12][8]
HEX_H4[4]HEX_H4_MUX[4]MAIN[11][9]
HEX_H4[5]HEX_H4_MUX[5]MAIN[9][9]
HEX_H5[0]HEX_H5_MUX[0]MAIN[29][8]
HEX_H5[1]HEX_H5_MUX[1]MAIN[24][8]
HEX_H5[2]HEX_H5_MUX[2]MAIN[11][8]
HEX_H5[3]HEX_H5_MUX[3]MAIN[6][8]
HEX_H5[4]HEX_H5_MUX[4]MAIN[22][9]
HEX_H5[5]HEX_H5_MUX[5]MAIN[12][9]
HEX_H6[0]HEX_H6_MUX[0]MAIN[23][8]
HEX_H6[1]HEX_H6_MUX[1]MAIN[18][8]
HEX_H6[2]HEX_H6_MUX[2]MAIN[5][8]
HEX_H6[3]PCI_CEMAIN[37][0]
HEX_H6[3]HEX_H6_MUX[3]MAIN[0][8]
HEX_H6[4]HEX_H6_MUX[4]MAIN[17][9]
HEX_H6[5]HEX_H6_MUX[5]MAIN[15][9]
HEX_V0[0]HEX_V0_MUX[0]MAIN[35][0]
HEX_V0[1]HEX_V0_MUX[1]MAIN[30][0]
HEX_V0[2]HEX_V0_MUX[2]MAIN[17][0]
HEX_V0[3]HEX_V0_MUX[3]MAIN[12][0]
HEX_V1[0]HEX_V1_MUX[0]MAIN[29][0]
HEX_V1[1]HEX_V1_MUX[1]MAIN[24][0]
HEX_V1[2]HEX_V1_MUX[2]MAIN[11][0]
HEX_V1[3]HEX_V1_MUX[3]MAIN[6][0]
HEX_V2[0]HEX_V2_MUX[0]MAIN[23][0]
HEX_V2[1]HEX_V2_MUX[1]MAIN[18][0]
HEX_V2[2]HEX_V2_MUX[2]MAIN[5][0]
HEX_V2[3]HEX_V2_MUX[3]MAIN[0][0]
HEX_V3[0]HEX_V3_MUX[0]MAIN[35][2]
HEX_V3[1]HEX_V3_MUX[1]MAIN[30][2]
HEX_V3[2]HEX_V3_MUX[2]MAIN[17][2]
HEX_V3[3]HEX_V3_MUX[3]MAIN[12][2]
HEX_V4[0]HEX_V4_MUX[0]MAIN[29][2]
HEX_V4[1]HEX_V4_MUX[1]MAIN[24][2]
HEX_V4[2]HEX_V4_MUX[2]MAIN[11][2]
HEX_V4[3]HEX_V4_MUX[3]MAIN[6][2]
HEX_V5[0]HEX_V5_MUX[0]MAIN[23][2]
HEX_V5[1]HEX_V5_MUX[1]MAIN[18][2]
HEX_V5[2]HEX_V5_MUX[2]MAIN[5][2]
HEX_V5[3]HEX_V5_MUX[3]MAIN[0][2]
LV[0]HEX_H6[5]MAIN[35][9]
LV[1]HEX_H5[5]MAIN[34][9]
LV[2]HEX_H4[5]MAIN[33][9]
LV[3]HEX_H3[5]MAIN[32][9]
LV[4]HEX_H2[5]MAIN[31][9]
LV[5]HEX_H1[5]MAIN[30][9]
LV[6]HEX_H6[4]MAIN[29][9]
LV[7]HEX_H5[4]MAIN[28][9]
LV[8]HEX_H4[4]MAIN[27][9]
LV[9]HEX_H3[4]MAIN[26][9]
LV[10]HEX_H2[4]MAIN[25][9]
LV[11]HEX_H1[4]MAIN[24][9]
virtex CNR_SE switchbox INT muxes HEX_H1_MUX[0]
BitsDestination
MAIN[33][4]MAIN[34][4]HEX_H1_MUX[0]
Source
01HEX_V0[0]
10off
11LH[5]
virtex CNR_SE switchbox INT muxes HEX_H1_MUX[1]
BitsDestination
MAIN[32][4]MAIN[31][4]HEX_H1_MUX[1]
Source
01HEX_V0[1]
10off
11LH[5]
virtex CNR_SE switchbox INT muxes HEX_H1_MUX[2]
BitsDestination
MAIN[15][4]MAIN[16][4]HEX_H1_MUX[2]
Source
01HEX_V0[2]
10off
11LH[11]
virtex CNR_SE switchbox INT muxes HEX_H1_MUX[3]
BitsDestination
MAIN[14][4]MAIN[13][4]HEX_H1_MUX[3]
Source
01HEX_V0[3]
10off
11LH[11]
virtex CNR_SE switchbox INT muxes HEX_H1_MUX[4]
BitsDestination
MAIN[18][9]HEX_H1_MUX[4]
Source
0LH[11]
1LH[5]
virtex CNR_SE switchbox INT muxes HEX_H1_MUX[5]
BitsDestination
MAIN[1][9]HEX_H1_MUX[5]
Source
0LH[11]
1LH[5]
virtex CNR_SE switchbox INT muxes HEX_H2_MUX[0]
BitsDestination
MAIN[27][4]MAIN[28][4]HEX_H2_MUX[0]
Source
01HEX_V1[0]
10off
11LH[4]
virtex CNR_SE switchbox INT muxes HEX_H2_MUX[1]
BitsDestination
MAIN[26][4]MAIN[25][4]HEX_H2_MUX[1]
Source
01HEX_V1[1]
10off
11LH[4]
virtex CNR_SE switchbox INT muxes HEX_H2_MUX[2]
BitsDestination
MAIN[9][4]MAIN[10][4]HEX_H2_MUX[2]
Source
01HEX_V1[2]
10off
11LH[10]
virtex CNR_SE switchbox INT muxes HEX_H2_MUX[3]
BitsDestination
MAIN[8][4]MAIN[7][4]HEX_H2_MUX[3]
Source
01HEX_V1[3]
10off
11LH[10]
virtex CNR_SE switchbox INT muxes HEX_H2_MUX[4]
BitsDestination
MAIN[4][9]HEX_H2_MUX[4]
Source
0LH[10]
1LH[4]
virtex CNR_SE switchbox INT muxes HEX_H2_MUX[5]
BitsDestination
MAIN[19][9]HEX_H2_MUX[5]
Source
0LH[10]
1LH[4]
virtex CNR_SE switchbox INT muxes HEX_H3_MUX[0]
BitsDestination
MAIN[21][4]MAIN[22][4]HEX_H3_MUX[0]
Source
01HEX_V2[0]
10off
11LH[3]
virtex CNR_SE switchbox INT muxes HEX_H3_MUX[1]
BitsDestination
MAIN[20][4]MAIN[19][4]HEX_H3_MUX[1]
Source
01HEX_V2[1]
10off
11LH[3]
virtex CNR_SE switchbox INT muxes HEX_H3_MUX[2]
BitsDestination
MAIN[3][4]MAIN[4][4]HEX_H3_MUX[2]
Source
01HEX_V2[2]
10off
11LH[9]
virtex CNR_SE switchbox INT muxes HEX_H3_MUX[3]
BitsDestination
MAIN[2][4]MAIN[1][4]HEX_H3_MUX[3]
Source
01HEX_V2[3]
10off
11LH[9]
virtex CNR_SE switchbox INT muxes HEX_H3_MUX[4]
BitsDestination
MAIN[20][9]HEX_H3_MUX[4]
Source
0LH[9]
1LH[3]
virtex CNR_SE switchbox INT muxes HEX_H3_MUX[5]
BitsDestination
MAIN[7][9]HEX_H3_MUX[5]
Source
0LH[9]
1LH[3]
virtex CNR_SE switchbox INT muxes HEX_H4_MUX[0]
BitsDestination
MAIN[33][8]MAIN[34][8]HEX_H4_MUX[0]
Source
01HEX_V3[0]
10off
11LH[2]
virtex CNR_SE switchbox INT muxes HEX_H4_MUX[1]
BitsDestination
MAIN[32][8]MAIN[31][8]HEX_H4_MUX[1]
Source
01HEX_V3[1]
10off
11LH[2]
virtex CNR_SE switchbox INT muxes HEX_H4_MUX[2]
BitsDestination
MAIN[15][8]MAIN[16][8]HEX_H4_MUX[2]
Source
01HEX_V3[2]
10off
11LH[8]
virtex CNR_SE switchbox INT muxes HEX_H4_MUX[3]
BitsDestination
MAIN[14][8]MAIN[13][8]HEX_H4_MUX[3]
Source
01HEX_V3[3]
10off
11LH[8]
virtex CNR_SE switchbox INT muxes HEX_H4_MUX[4]
BitsDestination
MAIN[21][9]HEX_H4_MUX[4]
Source
0LH[8]
1LH[2]
virtex CNR_SE switchbox INT muxes HEX_H4_MUX[5]
BitsDestination
MAIN[10][9]HEX_H4_MUX[5]
Source
0LH[8]
1LH[2]
virtex CNR_SE switchbox INT muxes HEX_H5_MUX[0]
BitsDestination
MAIN[27][8]MAIN[28][8]HEX_H5_MUX[0]
Source
01HEX_V4[0]
10off
11LH[1]
virtex CNR_SE switchbox INT muxes HEX_H5_MUX[1]
BitsDestination
MAIN[26][8]MAIN[25][8]HEX_H5_MUX[1]
Source
01HEX_V4[1]
10off
11LH[1]
virtex CNR_SE switchbox INT muxes HEX_H5_MUX[2]
BitsDestination
MAIN[9][8]MAIN[10][8]HEX_H5_MUX[2]
Source
01HEX_V4[2]
10off
11LH[7]
virtex CNR_SE switchbox INT muxes HEX_H5_MUX[3]
BitsDestination
MAIN[8][8]MAIN[7][8]HEX_H5_MUX[3]
Source
01HEX_V4[3]
10off
11LH[7]
virtex CNR_SE switchbox INT muxes HEX_H5_MUX[4]
BitsDestination
MAIN[14][9]HEX_H5_MUX[4]
Source
0LH[7]
1LH[1]
virtex CNR_SE switchbox INT muxes HEX_H5_MUX[5]
BitsDestination
MAIN[13][9]HEX_H5_MUX[5]
Source
0LH[7]
1LH[1]
virtex CNR_SE switchbox INT muxes HEX_H6_MUX[0]
BitsDestination
MAIN[21][8]MAIN[22][8]HEX_H6_MUX[0]
Source
01HEX_V5[0]
10off
11LH[0]
virtex CNR_SE switchbox INT muxes HEX_H6_MUX[1]
BitsDestination
MAIN[20][8]MAIN[19][8]HEX_H6_MUX[1]
Source
01HEX_V5[1]
10off
11LH[0]
virtex CNR_SE switchbox INT muxes HEX_H6_MUX[2]
BitsDestination
MAIN[3][8]MAIN[4][8]HEX_H6_MUX[2]
Source
01HEX_V5[2]
10off
11LH[6]
virtex CNR_SE switchbox INT muxes HEX_H6_MUX[3]
BitsDestination
MAIN[2][8]MAIN[1][8]HEX_H6_MUX[3]
Source
01HEX_V5[3]
10off
11LH[6]
virtex CNR_SE switchbox INT muxes HEX_H6_MUX[4]
BitsDestination
MAIN[23][9]HEX_H6_MUX[4]
Source
0LH[0]
1LH[6]
virtex CNR_SE switchbox INT muxes HEX_H6_MUX[5]
BitsDestination
MAIN[16][9]HEX_H6_MUX[5]
Source
0LH[0]
1LH[6]
virtex CNR_SE switchbox INT muxes HEX_V0_MUX[0]
BitsDestination
MAIN[33][0]MAIN[34][0]HEX_V0_MUX[0]
Source
01HEX_H1[0]
10off
11LV[0]
virtex CNR_SE switchbox INT muxes HEX_V0_MUX[1]
BitsDestination
MAIN[32][0]MAIN[31][0]HEX_V0_MUX[1]
Source
01HEX_H1[1]
10off
11LV[0]
virtex CNR_SE switchbox INT muxes HEX_V0_MUX[2]
BitsDestination
MAIN[15][0]MAIN[16][0]HEX_V0_MUX[2]
Source
01HEX_H1[2]
10off
11LV[6]
virtex CNR_SE switchbox INT muxes HEX_V0_MUX[3]
BitsDestination
MAIN[14][0]MAIN[13][0]HEX_V0_MUX[3]
Source
01HEX_H1[3]
10off
11LV[6]
virtex CNR_SE switchbox INT muxes HEX_V1_MUX[0]
BitsDestination
MAIN[27][0]MAIN[28][0]HEX_V1_MUX[0]
Source
01HEX_H2[0]
10off
11LV[11]
virtex CNR_SE switchbox INT muxes HEX_V1_MUX[1]
BitsDestination
MAIN[26][0]MAIN[25][0]HEX_V1_MUX[1]
Source
01HEX_H2[1]
10off
11LV[11]
virtex CNR_SE switchbox INT muxes HEX_V1_MUX[2]
BitsDestination
MAIN[9][0]MAIN[10][0]HEX_V1_MUX[2]
Source
01HEX_H2[2]
10off
11LV[5]
virtex CNR_SE switchbox INT muxes HEX_V1_MUX[3]
BitsDestination
MAIN[8][0]MAIN[7][0]HEX_V1_MUX[3]
Source
01HEX_H2[3]
10off
11LV[5]
virtex CNR_SE switchbox INT muxes HEX_V2_MUX[0]
BitsDestination
MAIN[21][0]MAIN[22][0]HEX_V2_MUX[0]
Source
01HEX_H3[0]
10off
11LV[10]
virtex CNR_SE switchbox INT muxes HEX_V2_MUX[1]
BitsDestination
MAIN[20][0]MAIN[19][0]HEX_V2_MUX[1]
Source
01HEX_H3[1]
10off
11LV[10]
virtex CNR_SE switchbox INT muxes HEX_V2_MUX[2]
BitsDestination
MAIN[3][0]MAIN[4][0]HEX_V2_MUX[2]
Source
01HEX_H3[2]
10off
11LV[4]
virtex CNR_SE switchbox INT muxes HEX_V2_MUX[3]
BitsDestination
MAIN[2][0]MAIN[1][0]HEX_V2_MUX[3]
Source
01HEX_H3[3]
10off
11LV[4]
virtex CNR_SE switchbox INT muxes HEX_V3_MUX[0]
BitsDestination
MAIN[33][2]MAIN[34][2]HEX_V3_MUX[0]
Source
01HEX_H4[0]
10off
11LV[9]
virtex CNR_SE switchbox INT muxes HEX_V3_MUX[1]
BitsDestination
MAIN[32][2]MAIN[31][2]HEX_V3_MUX[1]
Source
01HEX_H4[1]
10off
11LV[9]
virtex CNR_SE switchbox INT muxes HEX_V3_MUX[2]
BitsDestination
MAIN[15][2]MAIN[16][2]HEX_V3_MUX[2]
Source
01HEX_H4[2]
10off
11LV[3]
virtex CNR_SE switchbox INT muxes HEX_V3_MUX[3]
BitsDestination
MAIN[14][2]MAIN[13][2]HEX_V3_MUX[3]
Source
01HEX_H4[3]
10off
11LV[3]
virtex CNR_SE switchbox INT muxes HEX_V4_MUX[0]
BitsDestination
MAIN[27][2]MAIN[28][2]HEX_V4_MUX[0]
Source
01HEX_H5[0]
10off
11LV[8]
virtex CNR_SE switchbox INT muxes HEX_V4_MUX[1]
BitsDestination
MAIN[26][2]MAIN[25][2]HEX_V4_MUX[1]
Source
01HEX_H5[1]
10off
11LV[8]
virtex CNR_SE switchbox INT muxes HEX_V4_MUX[2]
BitsDestination
MAIN[9][2]MAIN[10][2]HEX_V4_MUX[2]
Source
01HEX_H5[2]
10off
11LV[2]
virtex CNR_SE switchbox INT muxes HEX_V4_MUX[3]
BitsDestination
MAIN[8][2]MAIN[7][2]HEX_V4_MUX[3]
Source
01HEX_H5[3]
10off
11LV[2]
virtex CNR_SE switchbox INT muxes HEX_V5_MUX[0]
BitsDestination
MAIN[21][2]MAIN[22][2]HEX_V5_MUX[0]
Source
01HEX_H6[0]
10off
11LV[7]
virtex CNR_SE switchbox INT muxes HEX_V5_MUX[1]
BitsDestination
MAIN[20][2]MAIN[19][2]HEX_V5_MUX[1]
Source
01HEX_H6[1]
10off
11LV[7]
virtex CNR_SE switchbox INT muxes HEX_V5_MUX[2]
BitsDestination
MAIN[3][2]MAIN[4][2]HEX_V5_MUX[2]
Source
01HEX_H6[2]
10off
11LV[1]
virtex CNR_SE switchbox INT muxes HEX_V5_MUX[3]
BitsDestination
MAIN[2][2]MAIN[1][2]HEX_V5_MUX[3]
Source
01HEX_H6[3]
10off
11LV[1]

Bels MISC_SE

virtex CNR_SE bel MISC_SE pins
PinDirectionMISC_SE
virtex CNR_SE bel MISC_SE attribute bits
AttributeMISC_SE
DONE_PULL[enum: IOB_PULL]
PROG_PULL[enum: IOB_PULL]
virtex CNR_SE enum IOB_PULL
MISC_SE.DONE_PULLMAIN[9][12]
MISC_SE.PROG_PULLMAIN[10][12]
NONE0
PULLUP1

Bitstream

virtex CNR_SE rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - MISC_SE: DONE_PULL bit 0 MISC_SE: PROG_PULL bit 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 INT: buffer HEX_H1[5] ← HEX_H1_MUX[5] INT: mux HEX_H1_MUX[5] bit 0 INT: buffer HEX_H1[4] ← HEX_H1_MUX[4] INT: buffer HEX_H2[5] ← HEX_H2_MUX[5] INT: mux HEX_H2_MUX[4] bit 0 INT: buffer HEX_H2[4] ← HEX_H2_MUX[4] INT: buffer HEX_H3[5] ← HEX_H3_MUX[5] INT: mux HEX_H3_MUX[5] bit 0 INT: buffer HEX_H3[4] ← HEX_H3_MUX[4] INT: buffer HEX_H4[5] ← HEX_H4_MUX[5] INT: mux HEX_H4_MUX[5] bit 0 INT: buffer HEX_H4[4] ← HEX_H4_MUX[4] INT: buffer HEX_H5[5] ← HEX_H5_MUX[5] INT: mux HEX_H5_MUX[5] bit 0 INT: mux HEX_H5_MUX[4] bit 0 INT: buffer HEX_H6[5] ← HEX_H6_MUX[5] INT: mux HEX_H6_MUX[5] bit 0 INT: buffer HEX_H6[4] ← HEX_H6_MUX[4] INT: mux HEX_H1_MUX[4] bit 0 INT: mux HEX_H2_MUX[5] bit 0 INT: mux HEX_H3_MUX[4] bit 0 INT: mux HEX_H4_MUX[4] bit 0 INT: buffer HEX_H5[4] ← HEX_H5_MUX[4] INT: mux HEX_H6_MUX[4] bit 0 INT: buffer LV[11] ← HEX_H1[4] INT: buffer LV[10] ← HEX_H2[4] INT: buffer LV[9] ← HEX_H3[4] INT: buffer LV[8] ← HEX_H4[4] INT: buffer LV[7] ← HEX_H5[4] INT: buffer LV[6] ← HEX_H6[4] INT: buffer LV[5] ← HEX_H1[5] INT: buffer LV[4] ← HEX_H2[5] INT: buffer LV[3] ← HEX_H3[5] INT: buffer LV[2] ← HEX_H4[5] INT: buffer LV[1] ← HEX_H5[5] INT: buffer LV[0] ← HEX_H6[5] - - - - - - - - - - - - - - - - - -
B8 INT: buffer HEX_H6[3] ← HEX_H6_MUX[3] INT: mux HEX_H6_MUX[3] bit 0 INT: mux HEX_H6_MUX[3] bit 1 INT: mux HEX_H6_MUX[2] bit 1 INT: mux HEX_H6_MUX[2] bit 0 INT: buffer HEX_H6[2] ← HEX_H6_MUX[2] INT: buffer HEX_H5[3] ← HEX_H5_MUX[3] INT: mux HEX_H5_MUX[3] bit 0 INT: mux HEX_H5_MUX[3] bit 1 INT: mux HEX_H5_MUX[2] bit 1 INT: mux HEX_H5_MUX[2] bit 0 INT: buffer HEX_H5[2] ← HEX_H5_MUX[2] INT: buffer HEX_H4[3] ← HEX_H4_MUX[3] INT: mux HEX_H4_MUX[3] bit 0 INT: mux HEX_H4_MUX[3] bit 1 INT: mux HEX_H4_MUX[2] bit 1 INT: mux HEX_H4_MUX[2] bit 0 INT: buffer HEX_H4[2] ← HEX_H4_MUX[2] INT: buffer HEX_H6[1] ← HEX_H6_MUX[1] INT: mux HEX_H6_MUX[1] bit 0 INT: mux HEX_H6_MUX[1] bit 1 INT: mux HEX_H6_MUX[0] bit 1 INT: mux HEX_H6_MUX[0] bit 0 INT: buffer HEX_H6[0] ← HEX_H6_MUX[0] INT: buffer HEX_H5[1] ← HEX_H5_MUX[1] INT: mux HEX_H5_MUX[1] bit 0 INT: mux HEX_H5_MUX[1] bit 1 INT: mux HEX_H5_MUX[0] bit 1 INT: mux HEX_H5_MUX[0] bit 0 INT: buffer HEX_H5[0] ← HEX_H5_MUX[0] INT: buffer HEX_H4[1] ← HEX_H4_MUX[1] INT: mux HEX_H4_MUX[1] bit 0 INT: mux HEX_H4_MUX[1] bit 1 INT: mux HEX_H4_MUX[0] bit 1 INT: mux HEX_H4_MUX[0] bit 0 INT: buffer HEX_H4[0] ← HEX_H4_MUX[0] - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 INT: buffer HEX_H3[3] ← HEX_H3_MUX[3] INT: mux HEX_H3_MUX[3] bit 0 INT: mux HEX_H3_MUX[3] bit 1 INT: mux HEX_H3_MUX[2] bit 1 INT: mux HEX_H3_MUX[2] bit 0 INT: buffer HEX_H3[2] ← HEX_H3_MUX[2] INT: buffer HEX_H2[3] ← HEX_H2_MUX[3] INT: mux HEX_H2_MUX[3] bit 0 INT: mux HEX_H2_MUX[3] bit 1 INT: mux HEX_H2_MUX[2] bit 1 INT: mux HEX_H2_MUX[2] bit 0 INT: buffer HEX_H2[2] ← HEX_H2_MUX[2] INT: buffer HEX_H1[3] ← HEX_H1_MUX[3] INT: mux HEX_H1_MUX[3] bit 0 INT: mux HEX_H1_MUX[3] bit 1 INT: mux HEX_H1_MUX[2] bit 1 INT: mux HEX_H1_MUX[2] bit 0 INT: buffer HEX_H1[2] ← HEX_H1_MUX[2] INT: buffer HEX_H3[1] ← HEX_H3_MUX[1] INT: mux HEX_H3_MUX[1] bit 0 INT: mux HEX_H3_MUX[1] bit 1 INT: mux HEX_H3_MUX[0] bit 1 INT: mux HEX_H3_MUX[0] bit 0 INT: buffer HEX_H3[0] ← HEX_H3_MUX[0] INT: buffer HEX_H2[1] ← HEX_H2_MUX[1] INT: mux HEX_H2_MUX[1] bit 0 INT: mux HEX_H2_MUX[1] bit 1 INT: mux HEX_H2_MUX[0] bit 1 INT: mux HEX_H2_MUX[0] bit 0 INT: buffer HEX_H2[0] ← HEX_H2_MUX[0] INT: buffer HEX_H1[1] ← HEX_H1_MUX[1] INT: mux HEX_H1_MUX[1] bit 0 INT: mux HEX_H1_MUX[1] bit 1 INT: mux HEX_H1_MUX[0] bit 1 INT: mux HEX_H1_MUX[0] bit 0 INT: buffer HEX_H1[0] ← HEX_H1_MUX[0] - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 INT: buffer HEX_V5[3] ← HEX_V5_MUX[3] INT: mux HEX_V5_MUX[3] bit 0 INT: mux HEX_V5_MUX[3] bit 1 INT: mux HEX_V5_MUX[2] bit 1 INT: mux HEX_V5_MUX[2] bit 0 INT: buffer HEX_V5[2] ← HEX_V5_MUX[2] INT: buffer HEX_V4[3] ← HEX_V4_MUX[3] INT: mux HEX_V4_MUX[3] bit 0 INT: mux HEX_V4_MUX[3] bit 1 INT: mux HEX_V4_MUX[2] bit 1 INT: mux HEX_V4_MUX[2] bit 0 INT: buffer HEX_V4[2] ← HEX_V4_MUX[2] INT: buffer HEX_V3[3] ← HEX_V3_MUX[3] INT: mux HEX_V3_MUX[3] bit 0 INT: mux HEX_V3_MUX[3] bit 1 INT: mux HEX_V3_MUX[2] bit 1 INT: mux HEX_V3_MUX[2] bit 0 INT: buffer HEX_V3[2] ← HEX_V3_MUX[2] INT: buffer HEX_V5[1] ← HEX_V5_MUX[1] INT: mux HEX_V5_MUX[1] bit 0 INT: mux HEX_V5_MUX[1] bit 1 INT: mux HEX_V5_MUX[0] bit 1 INT: mux HEX_V5_MUX[0] bit 0 INT: buffer HEX_V5[0] ← HEX_V5_MUX[0] INT: buffer HEX_V4[1] ← HEX_V4_MUX[1] INT: mux HEX_V4_MUX[1] bit 0 INT: mux HEX_V4_MUX[1] bit 1 INT: mux HEX_V4_MUX[0] bit 1 INT: mux HEX_V4_MUX[0] bit 0 INT: buffer HEX_V4[0] ← HEX_V4_MUX[0] INT: buffer HEX_V3[1] ← HEX_V3_MUX[1] INT: mux HEX_V3_MUX[1] bit 0 INT: mux HEX_V3_MUX[1] bit 1 INT: mux HEX_V3_MUX[0] bit 1 INT: mux HEX_V3_MUX[0] bit 0 INT: buffer HEX_V3[0] ← HEX_V3_MUX[0] - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 INT: buffer HEX_V2[3] ← HEX_V2_MUX[3] INT: mux HEX_V2_MUX[3] bit 0 INT: mux HEX_V2_MUX[3] bit 1 INT: mux HEX_V2_MUX[2] bit 1 INT: mux HEX_V2_MUX[2] bit 0 INT: buffer HEX_V2[2] ← HEX_V2_MUX[2] INT: buffer HEX_V1[3] ← HEX_V1_MUX[3] INT: mux HEX_V1_MUX[3] bit 0 INT: mux HEX_V1_MUX[3] bit 1 INT: mux HEX_V1_MUX[2] bit 1 INT: mux HEX_V1_MUX[2] bit 0 INT: buffer HEX_V1[2] ← HEX_V1_MUX[2] INT: buffer HEX_V0[3] ← HEX_V0_MUX[3] INT: mux HEX_V0_MUX[3] bit 0 INT: mux HEX_V0_MUX[3] bit 1 INT: mux HEX_V0_MUX[2] bit 1 INT: mux HEX_V0_MUX[2] bit 0 INT: buffer HEX_V0[2] ← HEX_V0_MUX[2] INT: buffer HEX_V2[1] ← HEX_V2_MUX[1] INT: mux HEX_V2_MUX[1] bit 0 INT: mux HEX_V2_MUX[1] bit 1 INT: mux HEX_V2_MUX[0] bit 1 INT: mux HEX_V2_MUX[0] bit 0 INT: buffer HEX_V2[0] ← HEX_V2_MUX[0] INT: buffer HEX_V1[1] ← HEX_V1_MUX[1] INT: mux HEX_V1_MUX[1] bit 0 INT: mux HEX_V1_MUX[1] bit 1 INT: mux HEX_V1_MUX[0] bit 1 INT: mux HEX_V1_MUX[0] bit 0 INT: buffer HEX_V1[0] ← HEX_V1_MUX[0] INT: buffer HEX_V0[1] ← HEX_V0_MUX[1] INT: mux HEX_V0_MUX[1] bit 0 INT: mux HEX_V0_MUX[1] bit 1 INT: mux HEX_V0_MUX[0] bit 1 INT: mux HEX_V0_MUX[0] bit 0 INT: buffer HEX_V0[0] ← HEX_V0_MUX[0] - INT: buffer HEX_H6[3] ← PCI_CE - - - - - - - - - - - - - - - -