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South-west

Tile CNR_SW

Cells: 1

Switchbox INT

virtex CNR_SW switchbox INT muxes HEX_H0[0]
BitsDestination
HEX_H0[0]
Source
LH[0]
virtex CNR_SW switchbox INT muxes HEX_H0[1]
BitsDestination
HEX_H0[1]
Source
LH[0]
virtex CNR_SW switchbox INT muxes HEX_H0[2]
BitsDestination
HEX_H0[2]
Source
LH[6]
virtex CNR_SW switchbox INT muxes HEX_H0[3]
BitsDestination
HEX_H0[3]
Source
LH[6]
virtex CNR_SW switchbox INT muxes HEX_H0[4]
BitsDestination
HEX_H0[4]
Source
LH[6]
virtex CNR_SW switchbox INT muxes HEX_H0[5]
BitsDestination
HEX_H0[5]
Source
LH[6]
virtex CNR_SW switchbox INT muxes HEX_H1[0]
BitsDestination
HEX_H1[0]
Source
LH[11]
virtex CNR_SW switchbox INT muxes HEX_H1[1]
BitsDestination
HEX_H1[1]
Source
LH[11]
virtex CNR_SW switchbox INT muxes HEX_H1[2]
BitsDestination
HEX_H1[2]
Source
LH[5]
virtex CNR_SW switchbox INT muxes HEX_H1[3]
BitsDestination
HEX_H1[3]
Source
LH[5]
virtex CNR_SW switchbox INT muxes HEX_H1[4]
BitsDestination
HEX_H1[4]
Source
LH[11]
virtex CNR_SW switchbox INT muxes HEX_H1[5]
BitsDestination
HEX_H1[5]
Source
LH[11]
virtex CNR_SW switchbox INT muxes HEX_H2[0]
BitsDestination
HEX_H2[0]
Source
LH[10]
virtex CNR_SW switchbox INT muxes HEX_H2[1]
BitsDestination
HEX_H2[1]
Source
LH[10]
virtex CNR_SW switchbox INT muxes HEX_H2[2]
BitsDestination
HEX_H2[2]
Source
LH[4]
virtex CNR_SW switchbox INT muxes HEX_H2[3]
BitsDestination
HEX_H2[3]
Source
LH[4]
virtex CNR_SW switchbox INT muxes HEX_H2[4]
BitsDestination
HEX_H2[4]
Source
LH[10]
virtex CNR_SW switchbox INT muxes HEX_H2[5]
BitsDestination
HEX_H2[5]
Source
LH[10]
virtex CNR_SW switchbox INT muxes HEX_H3[0]
BitsDestination
HEX_H3[0]
Source
LH[9]
virtex CNR_SW switchbox INT muxes HEX_H3[1]
BitsDestination
HEX_H3[1]
Source
LH[9]
virtex CNR_SW switchbox INT muxes HEX_H3[2]
BitsDestination
HEX_H3[2]
Source
LH[3]
virtex CNR_SW switchbox INT muxes HEX_H3[3]
BitsDestination
HEX_H3[3]
Source
LH[3]
virtex CNR_SW switchbox INT muxes HEX_H3[4]
BitsDestination
HEX_H3[4]
Source
LH[9]
virtex CNR_SW switchbox INT muxes HEX_H3[5]
BitsDestination
HEX_H3[5]
Source
LH[9]
virtex CNR_SW switchbox INT muxes HEX_H4[0]
BitsDestination
HEX_H4[0]
Source
LH[8]
virtex CNR_SW switchbox INT muxes HEX_H4[1]
BitsDestination
HEX_H4[1]
Source
LH[8]
virtex CNR_SW switchbox INT muxes HEX_H4[2]
BitsDestination
HEX_H4[2]
Source
LH[2]
virtex CNR_SW switchbox INT muxes HEX_H4[3]
BitsDestination
HEX_H4[3]
Source
LH[2]
virtex CNR_SW switchbox INT muxes HEX_H4[4]
BitsDestination
HEX_H4[4]
Source
LH[8]
virtex CNR_SW switchbox INT muxes HEX_H4[5]
BitsDestination
HEX_H4[5]
Source
LH[8]
virtex CNR_SW switchbox INT muxes HEX_H5[0]
BitsDestination
HEX_H5[0]
Source
LH[7]
virtex CNR_SW switchbox INT muxes HEX_H5[1]
BitsDestination
HEX_H5[1]
Source
LH[7]
virtex CNR_SW switchbox INT muxes HEX_H5[2]
BitsDestination
HEX_H5[2]
Source
LH[1]
virtex CNR_SW switchbox INT muxes HEX_H5[3]
BitsDestination
HEX_H5[3]
Source
LH[1]
virtex CNR_SW switchbox INT muxes HEX_H5[4]
BitsDestination
HEX_H5[4]
Source
LH[7]
virtex CNR_SW switchbox INT muxes HEX_H5[5]
BitsDestination
HEX_H5[5]
Source
LH[7]
virtex CNR_SW switchbox INT muxes HEX_V0[0]
BitsDestination
HEX_V0[0]
Source
LV[0]
virtex CNR_SW switchbox INT muxes HEX_V0[1]
BitsDestination
HEX_V0[1]
Source
LV[0]
virtex CNR_SW switchbox INT muxes HEX_V0[2]
BitsDestination
HEX_V0[2]
Source
LV[6]
virtex CNR_SW switchbox INT muxes HEX_V0[3]
BitsDestination
HEX_V0[3]
Source
LV[6]
virtex CNR_SW switchbox INT muxes HEX_V1[0]
BitsDestination
HEX_V1[0]
Source
LV[11]
virtex CNR_SW switchbox INT muxes HEX_V1[1]
BitsDestination
HEX_V1[1]
Source
LV[11]
virtex CNR_SW switchbox INT muxes HEX_V1[2]
BitsDestination
HEX_V1[2]
Source
LV[5]
virtex CNR_SW switchbox INT muxes HEX_V1[3]
BitsDestination
HEX_V1[3]
Source
LV[5]
virtex CNR_SW switchbox INT muxes HEX_V2[0]
BitsDestination
HEX_V2[0]
Source
LV[10]
virtex CNR_SW switchbox INT muxes HEX_V2[1]
BitsDestination
HEX_V2[1]
Source
LV[10]
virtex CNR_SW switchbox INT muxes HEX_V2[2]
BitsDestination
HEX_V2[2]
Source
LV[4]
virtex CNR_SW switchbox INT muxes HEX_V2[3]
BitsDestination
HEX_V2[3]
Source
LV[4]
virtex CNR_SW switchbox INT muxes HEX_V3[0]
BitsDestination
HEX_V3[0]
Source
LV[9]
virtex CNR_SW switchbox INT muxes HEX_V3[1]
BitsDestination
HEX_V3[1]
Source
LV[9]
virtex CNR_SW switchbox INT muxes HEX_V3[2]
BitsDestination
HEX_V3[2]
Source
LV[3]
virtex CNR_SW switchbox INT muxes HEX_V3[3]
BitsDestination
HEX_V3[3]
Source
LV[3]
virtex CNR_SW switchbox INT muxes HEX_V4[0]
BitsDestination
HEX_V4[0]
Source
LV[8]
virtex CNR_SW switchbox INT muxes HEX_V4[1]
BitsDestination
HEX_V4[1]
Source
LV[8]
virtex CNR_SW switchbox INT muxes HEX_V4[2]
BitsDestination
HEX_V4[2]
Source
LV[2]
virtex CNR_SW switchbox INT muxes HEX_V4[3]
BitsDestination
HEX_V4[3]
Source
LV[2]
virtex CNR_SW switchbox INT muxes HEX_V5[0]
BitsDestination
HEX_V5[0]
Source
LV[7]
virtex CNR_SW switchbox INT muxes HEX_V5[1]
BitsDestination
HEX_V5[1]
Source
LV[7]
virtex CNR_SW switchbox INT muxes HEX_V5[2]
BitsDestination
HEX_V5[2]
Source
LV[1]
virtex CNR_SW switchbox INT muxes HEX_V5[3]
BitsDestination
HEX_V5[3]
Source
LV[1]
virtex CNR_SW switchbox INT muxes LV[0]
BitsDestination
LV[0]
Source
HEX_H0[5]
virtex CNR_SW switchbox INT muxes LV[1]
BitsDestination
LV[1]
Source
HEX_H5[5]
virtex CNR_SW switchbox INT muxes LV[2]
BitsDestination
LV[2]
Source
HEX_H4[5]
virtex CNR_SW switchbox INT muxes LV[3]
BitsDestination
LV[3]
Source
HEX_H3[5]
virtex CNR_SW switchbox INT muxes LV[4]
BitsDestination
LV[4]
Source
HEX_H2[5]
virtex CNR_SW switchbox INT muxes LV[5]
BitsDestination
LV[5]
Source
HEX_H1[5]
virtex CNR_SW switchbox INT muxes LV[6]
BitsDestination
LV[6]
Source
HEX_H0[4]
virtex CNR_SW switchbox INT muxes LV[7]
BitsDestination
LV[7]
Source
HEX_H5[4]
virtex CNR_SW switchbox INT muxes LV[8]
BitsDestination
LV[8]
Source
HEX_H4[4]
virtex CNR_SW switchbox INT muxes LV[9]
BitsDestination
LV[9]
Source
HEX_H3[4]
virtex CNR_SW switchbox INT muxes LV[10]
BitsDestination
LV[10]
Source
HEX_H2[4]
virtex CNR_SW switchbox INT muxes LV[11]
BitsDestination
LV[11]
Source
HEX_H1[4]
virtex CNR_SW switchbox INT muxes IMUX_CAP_CLK
BitsDestination
IMUX_CAP_CLK
Source
HEX_V5[3]
virtex CNR_SW switchbox INT muxes IMUX_CAP_CAP
BitsDestination
IMUX_CAP_CAP
Source
HEX_V5[1]

Bel CAPTURE

virtex CNR_SW bel CAPTURE
PinDirectionWires
CAPinputIMUX_CAP_CAP
CLKinputIMUX_CAP_CLK

Bel wires

virtex CNR_SW bel wires
WirePins
IMUX_CAP_CLKCAPTURE.CLK
IMUX_CAP_CAPCAPTURE.CAP

Bitstream

virtex CNR_SW rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
### Bitstream
virtex CNR_SW rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47
B13 - - - - - - - - INT:MUX.IMUX_CAP_CLK[6] INT:MUX.IMUX_CAP_CLK[7] INT:MUX.IMUX_CAP_CLK[3] INT:MUX.IMUX_CAP_CLK[2] INT:MUX.IMUX_CAP_CLK[4] INT:MUX.IMUX_CAP_CLK[0] INT:MUX.IMUX_CAP_CLK[1] INT:MUX.IMUX_CAP_CLK[8] INT:MUX.IMUX_CAP_CLK[5] INT:MUX.IMUX_CAP_CLK[9] ~INT:INV.IMUX_CAP_CLK - - - - - - - - - - - INT:MUX.IMUX_CAP_CAP[4] INT:MUX.IMUX_CAP_CAP[5] INT:MUX.IMUX_CAP_CAP[1] INT:MUX.IMUX_CAP_CAP[3] INT:MUX.IMUX_CAP_CAP[2] INT:MUX.IMUX_CAP_CAP[0] INT:MUX.IMUX_CAP_CAP[6] INT:MUX.IMUX_CAP_CAP[7] ~INT:INV.IMUX_CAP_CAP - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - MISC:PDSTATUSPIN[0] MISC:M0PIN[0] MISC:M2PIN[1] MISC:M2PIN[0] INT:DRIVE.HEX_H0[5] INT:MUX.HEX_H0[5][0] INT:DRIVE.HEX_H0[4] INT:DRIVE.HEX_H1[5] INT:MUX.HEX_H1[4][0] INT:DRIVE.HEX_H1[4] INT:DRIVE.HEX_H2[5] INT:MUX.HEX_H2[5][0] INT:DRIVE.HEX_H2[4] INT:DRIVE.HEX_H3[5] INT:MUX.HEX_H3[5][0] INT:DRIVE.HEX_H3[4] INT:DRIVE.HEX_H4[5] INT:MUX.HEX_H4[5][0] INT:MUX.HEX_H4[4][0] INT:DRIVE.HEX_H5[5] INT:MUX.HEX_H5[5][0] INT:DRIVE.HEX_H5[4] INT:MUX.HEX_H0[4][0] INT:MUX.HEX_H1[5][0] INT:MUX.HEX_H2[4][0] INT:MUX.HEX_H3[4][0] INT:DRIVE.HEX_H4[4] INT:MUX.HEX_H5[4][0] INT:BUF.LV[11].HEX_H1[4] INT:BUF.LV[10].HEX_H2[4] INT:BUF.LV[9].HEX_H3[4] INT:BUF.LV[8].HEX_H4[4] INT:BUF.LV[7].HEX_H5[4] INT:BUF.LV[6].HEX_H0[4] INT:BUF.LV[5].HEX_H1[5] INT:BUF.LV[4].HEX_H2[5] INT:BUF.LV[3].HEX_H3[5] INT:BUF.LV[2].HEX_H4[5] INT:BUF.LV[1].HEX_H5[5] INT:BUF.LV[0].HEX_H0[5]
B8 - - - - - - - ~MISC:DRIVE_PD_STATUS MISC:POWERDOWNPIN[0] MISC:M0PIN[1] MISC:M1PIN[0] MISC:M1PIN[1] INT:DRIVE.HEX_H0[3] INT:MUX.HEX_H0[3][0] INT:MUX.HEX_H0[3][1] INT:MUX.HEX_H0[2][1] INT:MUX.HEX_H0[2][0] INT:DRIVE.HEX_H0[2] INT:DRIVE.HEX_H1[3] INT:MUX.HEX_H1[3][0] INT:MUX.HEX_H1[3][1] INT:MUX.HEX_H1[2][1] INT:MUX.HEX_H1[2][0] INT:DRIVE.HEX_H1[2] INT:DRIVE.HEX_H2[3] INT:MUX.HEX_H2[3][0] INT:MUX.HEX_H2[3][1] INT:MUX.HEX_H2[2][1] INT:MUX.HEX_H2[2][0] INT:DRIVE.HEX_H2[2] INT:DRIVE.HEX_H0[1] INT:MUX.HEX_H0[1][0] INT:MUX.HEX_H0[1][1] INT:MUX.HEX_H0[0][1] INT:MUX.HEX_H0[0][0] INT:DRIVE.HEX_H0[0] INT:DRIVE.HEX_H1[1] INT:MUX.HEX_H1[1][0] INT:MUX.HEX_H1[1][1] INT:MUX.HEX_H1[0][1] INT:MUX.HEX_H1[0][0] INT:DRIVE.HEX_H1[0] INT:DRIVE.HEX_H2[1] INT:MUX.HEX_H2[1][0] INT:MUX.HEX_H2[1][1] INT:MUX.HEX_H2[0][1] INT:MUX.HEX_H2[0][0] INT:DRIVE.HEX_H2[0]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - INT:DRIVE.HEX_H3[3] INT:MUX.HEX_H3[3][0] INT:MUX.HEX_H3[3][1] INT:MUX.HEX_H3[2][1] INT:MUX.HEX_H3[2][0] INT:DRIVE.HEX_H3[2] INT:DRIVE.HEX_H4[3] INT:MUX.HEX_H4[3][0] INT:MUX.HEX_H4[3][1] INT:MUX.HEX_H4[2][1] INT:MUX.HEX_H4[2][0] INT:DRIVE.HEX_H4[2] INT:DRIVE.HEX_H5[3] INT:MUX.HEX_H5[3][0] INT:MUX.HEX_H5[3][1] INT:MUX.HEX_H5[2][1] INT:MUX.HEX_H5[2][0] INT:DRIVE.HEX_H5[2] INT:DRIVE.HEX_H3[1] INT:MUX.HEX_H3[1][0] INT:MUX.HEX_H3[1][1] INT:MUX.HEX_H3[0][1] INT:MUX.HEX_H3[0][0] INT:DRIVE.HEX_H3[0] INT:DRIVE.HEX_H4[1] INT:MUX.HEX_H4[1][0] INT:MUX.HEX_H4[1][1] INT:MUX.HEX_H4[0][1] INT:MUX.HEX_H4[0][0] INT:DRIVE.HEX_H4[0] INT:DRIVE.HEX_H5[1] INT:MUX.HEX_H5[1][0] INT:MUX.HEX_H5[1][1] INT:MUX.HEX_H5[0][1] INT:MUX.HEX_H5[0][0] INT:DRIVE.HEX_H5[0]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - INT:DRIVE.HEX_V5[3] INT:MUX.HEX_V5[3][0] INT:MUX.HEX_V5[3][1] INT:MUX.HEX_V5[2][1] INT:MUX.HEX_V5[2][0] INT:DRIVE.HEX_V5[2] INT:DRIVE.HEX_V4[3] INT:MUX.HEX_V4[3][0] INT:MUX.HEX_V4[3][1] INT:MUX.HEX_V4[2][1] INT:MUX.HEX_V4[2][0] INT:DRIVE.HEX_V4[2] INT:DRIVE.HEX_V3[3] INT:MUX.HEX_V3[3][0] INT:MUX.HEX_V3[3][1] INT:MUX.HEX_V3[2][1] INT:MUX.HEX_V3[2][0] INT:DRIVE.HEX_V3[2] INT:DRIVE.HEX_V5[1] INT:MUX.HEX_V5[1][0] INT:MUX.HEX_V5[1][1] INT:MUX.HEX_V5[0][1] INT:MUX.HEX_V5[0][0] INT:DRIVE.HEX_V5[0] INT:DRIVE.HEX_V4[1] INT:MUX.HEX_V4[1][0] INT:MUX.HEX_V4[1][1] INT:MUX.HEX_V4[0][1] INT:MUX.HEX_V4[0][0] INT:DRIVE.HEX_V4[0] INT:DRIVE.HEX_V3[1] INT:MUX.HEX_V3[1][0] INT:MUX.HEX_V3[1][1] INT:MUX.HEX_V3[0][1] INT:MUX.HEX_V3[0][0] INT:DRIVE.HEX_V3[0]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - MISC:POWERUP_DELAY[1] MISC:POWERUP_DELAY[0] INT:BUF.HEX_H0[3].PCI_CE - - - - INT:DRIVE.HEX_V2[3] INT:MUX.HEX_V2[3][0] INT:MUX.HEX_V2[3][1] INT:MUX.HEX_V2[2][1] INT:MUX.HEX_V2[2][0] INT:DRIVE.HEX_V2[2] INT:DRIVE.HEX_V1[3] INT:MUX.HEX_V1[3][0] INT:MUX.HEX_V1[3][1] INT:MUX.HEX_V1[2][1] INT:MUX.HEX_V1[2][0] INT:DRIVE.HEX_V1[2] INT:DRIVE.HEX_V0[3] INT:MUX.HEX_V0[3][0] INT:MUX.HEX_V0[3][1] INT:MUX.HEX_V0[2][1] INT:MUX.HEX_V0[2][0] INT:DRIVE.HEX_V0[2] INT:DRIVE.HEX_V2[1] INT:MUX.HEX_V2[1][0] INT:MUX.HEX_V2[1][1] INT:MUX.HEX_V2[0][1] INT:MUX.HEX_V2[0][0] INT:DRIVE.HEX_V2[0] INT:DRIVE.HEX_V1[1] INT:MUX.HEX_V1[1][0] INT:MUX.HEX_V1[1][1] INT:MUX.HEX_V1[0][1] INT:MUX.HEX_V1[0][0] INT:DRIVE.HEX_V1[0] INT:DRIVE.HEX_V0[1] INT:MUX.HEX_V0[1][0] INT:MUX.HEX_V0[1][1] INT:MUX.HEX_V0[0][1] INT:MUX.HEX_V0[0][0] INT:DRIVE.HEX_V0[0]
INT:BUF.HEX_H0[3].PCI_CE 0.F7.B0
INT:BUF.LV[0].HEX_H0[5] 0.F47.B9
INT:BUF.LV[10].HEX_H2[4] 0.F37.B9
INT:BUF.LV[11].HEX_H1[4] 0.F36.B9
INT:BUF.LV[1].HEX_H5[5] 0.F46.B9
INT:BUF.LV[2].HEX_H4[5] 0.F45.B9
INT:BUF.LV[3].HEX_H3[5] 0.F44.B9
INT:BUF.LV[4].HEX_H2[5] 0.F43.B9
INT:BUF.LV[5].HEX_H1[5] 0.F42.B9
INT:BUF.LV[6].HEX_H0[4] 0.F41.B9
INT:BUF.LV[7].HEX_H5[4] 0.F40.B9
INT:BUF.LV[8].HEX_H4[4] 0.F39.B9
INT:BUF.LV[9].HEX_H3[4] 0.F38.B9
INT:DRIVE.HEX_H0[0] 0.F35.B8
INT:DRIVE.HEX_H0[1] 0.F30.B8
INT:DRIVE.HEX_H0[2] 0.F17.B8
INT:DRIVE.HEX_H0[3] 0.F12.B8
INT:DRIVE.HEX_H0[4] 0.F14.B9
INT:DRIVE.HEX_H0[5] 0.F12.B9
INT:DRIVE.HEX_H1[0] 0.F41.B8
INT:DRIVE.HEX_H1[1] 0.F36.B8
INT:DRIVE.HEX_H1[2] 0.F23.B8
INT:DRIVE.HEX_H1[3] 0.F18.B8
INT:DRIVE.HEX_H1[4] 0.F17.B9
INT:DRIVE.HEX_H1[5] 0.F15.B9
INT:DRIVE.HEX_H2[0] 0.F47.B8
INT:DRIVE.HEX_H2[1] 0.F42.B8
INT:DRIVE.HEX_H2[2] 0.F29.B8
INT:DRIVE.HEX_H2[3] 0.F24.B8
INT:DRIVE.HEX_H2[4] 0.F20.B9
INT:DRIVE.HEX_H2[5] 0.F18.B9
INT:DRIVE.HEX_H3[0] 0.F35.B4
INT:DRIVE.HEX_H3[1] 0.F30.B4
INT:DRIVE.HEX_H3[2] 0.F17.B4
INT:DRIVE.HEX_H3[3] 0.F12.B4
INT:DRIVE.HEX_H3[4] 0.F23.B9
INT:DRIVE.HEX_H3[5] 0.F21.B9
INT:DRIVE.HEX_H4[0] 0.F41.B4
INT:DRIVE.HEX_H4[1] 0.F36.B4
INT:DRIVE.HEX_H4[2] 0.F23.B4
INT:DRIVE.HEX_H4[3] 0.F18.B4
INT:DRIVE.HEX_H4[4] 0.F34.B9
INT:DRIVE.HEX_H4[5] 0.F24.B9
INT:DRIVE.HEX_H5[0] 0.F47.B4
INT:DRIVE.HEX_H5[1] 0.F42.B4
INT:DRIVE.HEX_H5[2] 0.F29.B4
INT:DRIVE.HEX_H5[3] 0.F24.B4
INT:DRIVE.HEX_H5[4] 0.F29.B9
INT:DRIVE.HEX_H5[5] 0.F27.B9
INT:DRIVE.HEX_V0[0] 0.F47.B0
INT:DRIVE.HEX_V0[1] 0.F42.B0
INT:DRIVE.HEX_V0[2] 0.F29.B0
INT:DRIVE.HEX_V0[3] 0.F24.B0
INT:DRIVE.HEX_V1[0] 0.F41.B0
INT:DRIVE.HEX_V1[1] 0.F36.B0
INT:DRIVE.HEX_V1[2] 0.F23.B0
INT:DRIVE.HEX_V1[3] 0.F18.B0
INT:DRIVE.HEX_V2[0] 0.F35.B0
INT:DRIVE.HEX_V2[1] 0.F30.B0
INT:DRIVE.HEX_V2[2] 0.F17.B0
INT:DRIVE.HEX_V2[3] 0.F12.B0
INT:DRIVE.HEX_V3[0] 0.F47.B2
INT:DRIVE.HEX_V3[1] 0.F42.B2
INT:DRIVE.HEX_V3[2] 0.F29.B2
INT:DRIVE.HEX_V3[3] 0.F24.B2
INT:DRIVE.HEX_V4[0] 0.F41.B2
INT:DRIVE.HEX_V4[1] 0.F36.B2
INT:DRIVE.HEX_V4[2] 0.F23.B2
INT:DRIVE.HEX_V4[3] 0.F18.B2
INT:DRIVE.HEX_V5[0] 0.F35.B2
INT:DRIVE.HEX_V5[1] 0.F30.B2
INT:DRIVE.HEX_V5[2] 0.F17.B2
INT:DRIVE.HEX_V5[3] 0.F12.B2
non-inverted [0]
INT:INV.IMUX_CAP_CAP 0.F38.B13
INT:INV.IMUX_CAP_CLK 0.F18.B13
MISC:DRIVE_PD_STATUS 0.F7.B8
inverted ~[0]
INT:MUX.HEX_H0[0] 0.F33.B8 0.F34.B8
HEX_V5[0] 0 1
NONE 1 0
LH[0] 1 1
INT:MUX.HEX_H0[1] 0.F32.B8 0.F31.B8
HEX_V5[1] 0 1
NONE 1 0
LH[0] 1 1
INT:MUX.HEX_H0[2] 0.F15.B8 0.F16.B8
HEX_V5[2] 0 1
NONE 1 0
LH[6] 1 1
INT:MUX.HEX_H0[3] 0.F14.B8 0.F13.B8
HEX_V5[3] 0 1
NONE 1 0
LH[6] 1 1
INT:MUX.HEX_H0[4] 0.F30.B9
INT:MUX.HEX_H0[5] 0.F13.B9
LH[0] 0
LH[6] 1
INT:MUX.HEX_H1[0] 0.F39.B8 0.F40.B8
HEX_V4[0] 0 1
NONE 1 0
LH[11] 1 1
INT:MUX.HEX_H1[1] 0.F38.B8 0.F37.B8
HEX_V4[1] 0 1
NONE 1 0
LH[11] 1 1
INT:MUX.HEX_H1[2] 0.F21.B8 0.F22.B8
HEX_V4[2] 0 1
NONE 1 0
LH[5] 1 1
INT:MUX.HEX_H1[3] 0.F20.B8 0.F19.B8
HEX_V4[3] 0 1
NONE 1 0
LH[5] 1 1
INT:MUX.HEX_H1[4] 0.F16.B9
INT:MUX.HEX_H1[5] 0.F31.B9
LH[11] 0
LH[5] 1
INT:MUX.HEX_H2[0] 0.F45.B8 0.F46.B8
HEX_V3[0] 0 1
NONE 1 0
LH[10] 1 1
INT:MUX.HEX_H2[1] 0.F44.B8 0.F43.B8
HEX_V3[1] 0 1
NONE 1 0
LH[10] 1 1
INT:MUX.HEX_H2[2] 0.F27.B8 0.F28.B8
HEX_V3[2] 0 1
NONE 1 0
LH[4] 1 1
INT:MUX.HEX_H2[3] 0.F26.B8 0.F25.B8
HEX_V3[3] 0 1
NONE 1 0
LH[4] 1 1
INT:MUX.HEX_H2[4] 0.F32.B9
INT:MUX.HEX_H2[5] 0.F19.B9
LH[10] 0
LH[4] 1
INT:MUX.HEX_H3[0] 0.F33.B4 0.F34.B4
HEX_V2[0] 0 1
NONE 1 0
LH[9] 1 1
INT:MUX.HEX_H3[1] 0.F32.B4 0.F31.B4
HEX_V2[1] 0 1
NONE 1 0
LH[9] 1 1
INT:MUX.HEX_H3[2] 0.F15.B4 0.F16.B4
HEX_V2[2] 0 1
NONE 1 0
LH[3] 1 1
INT:MUX.HEX_H3[3] 0.F14.B4 0.F13.B4
HEX_V2[3] 0 1
NONE 1 0
LH[3] 1 1
INT:MUX.HEX_H3[4] 0.F33.B9
INT:MUX.HEX_H3[5] 0.F22.B9
LH[9] 0
LH[3] 1
INT:MUX.HEX_H4[0] 0.F39.B4 0.F40.B4
HEX_V1[0] 0 1
NONE 1 0
LH[8] 1 1
INT:MUX.HEX_H4[1] 0.F38.B4 0.F37.B4
HEX_V1[1] 0 1
NONE 1 0
LH[8] 1 1
INT:MUX.HEX_H4[2] 0.F21.B4 0.F22.B4
HEX_V1[2] 0 1
NONE 1 0
LH[2] 1 1
INT:MUX.HEX_H4[3] 0.F20.B4 0.F19.B4
HEX_V1[3] 0 1
NONE 1 0
LH[2] 1 1
INT:MUX.HEX_H4[4] 0.F26.B9
INT:MUX.HEX_H4[5] 0.F25.B9
LH[8] 0
LH[2] 1
INT:MUX.HEX_H5[0] 0.F45.B4 0.F46.B4
HEX_V0[0] 0 1
NONE 1 0
LH[7] 1 1
INT:MUX.HEX_H5[1] 0.F44.B4 0.F43.B4
HEX_V0[1] 0 1
NONE 1 0
LH[7] 1 1
INT:MUX.HEX_H5[2] 0.F27.B4 0.F28.B4
HEX_V0[2] 0 1
NONE 1 0
LH[1] 1 1
INT:MUX.HEX_H5[3] 0.F26.B4 0.F25.B4
HEX_V0[3] 0 1
NONE 1 0
LH[1] 1 1
INT:MUX.HEX_H5[4] 0.F35.B9
INT:MUX.HEX_H5[5] 0.F28.B9
LH[7] 0
LH[1] 1
INT:MUX.HEX_V0[0] 0.F45.B0 0.F46.B0
HEX_H5[0] 0 1
NONE 1 0
LV[0] 1 1
INT:MUX.HEX_V0[1] 0.F44.B0 0.F43.B0
HEX_H5[1] 0 1
NONE 1 0
LV[0] 1 1
INT:MUX.HEX_V0[2] 0.F27.B0 0.F28.B0
HEX_H5[2] 0 1
NONE 1 0
LV[6] 1 1
INT:MUX.HEX_V0[3] 0.F26.B0 0.F25.B0
HEX_H5[3] 0 1
NONE 1 0
LV[6] 1 1
INT:MUX.HEX_V1[0] 0.F39.B0 0.F40.B0
HEX_H4[0] 0 1
NONE 1 0
LV[11] 1 1
INT:MUX.HEX_V1[1] 0.F38.B0 0.F37.B0
HEX_H4[1] 0 1
NONE 1 0
LV[11] 1 1
INT:MUX.HEX_V1[2] 0.F21.B0 0.F22.B0
HEX_H4[2] 0 1
NONE 1 0
LV[5] 1 1
INT:MUX.HEX_V1[3] 0.F20.B0 0.F19.B0
HEX_H4[3] 0 1
NONE 1 0
LV[5] 1 1
INT:MUX.HEX_V2[0] 0.F33.B0 0.F34.B0
HEX_H3[0] 0 1
NONE 1 0
LV[10] 1 1
INT:MUX.HEX_V2[1] 0.F32.B0 0.F31.B0
HEX_H3[1] 0 1
NONE 1 0
LV[10] 1 1
INT:MUX.HEX_V2[2] 0.F15.B0 0.F16.B0
HEX_H3[2] 0 1
NONE 1 0
LV[4] 1 1
INT:MUX.HEX_V2[3] 0.F14.B0 0.F13.B0
HEX_H3[3] 0 1
NONE 1 0
LV[4] 1 1
INT:MUX.HEX_V3[0] 0.F45.B2 0.F46.B2
HEX_H2[0] 0 1
NONE 1 0
LV[9] 1 1
INT:MUX.HEX_V3[1] 0.F44.B2 0.F43.B2
HEX_H2[1] 0 1
NONE 1 0
LV[9] 1 1
INT:MUX.HEX_V3[2] 0.F27.B2 0.F28.B2
HEX_H2[2] 0 1
NONE 1 0
LV[3] 1 1
INT:MUX.HEX_V3[3] 0.F26.B2 0.F25.B2
HEX_H2[3] 0 1
NONE 1 0
LV[3] 1 1
INT:MUX.HEX_V4[0] 0.F39.B2 0.F40.B2
HEX_H1[0] 0 1
NONE 1 0
LV[8] 1 1
INT:MUX.HEX_V4[1] 0.F38.B2 0.F37.B2
HEX_H1[1] 0 1
NONE 1 0
LV[8] 1 1
INT:MUX.HEX_V4[2] 0.F21.B2 0.F22.B2
HEX_H1[2] 0 1
NONE 1 0
LV[2] 1 1
INT:MUX.HEX_V4[3] 0.F20.B2 0.F19.B2
HEX_H1[3] 0 1
NONE 1 0
LV[2] 1 1
INT:MUX.HEX_V5[0] 0.F33.B2 0.F34.B2
HEX_H0[0] 0 1
NONE 1 0
LV[7] 1 1
INT:MUX.HEX_V5[1] 0.F32.B2 0.F31.B2
HEX_H0[1] 0 1
NONE 1 0
LV[7] 1 1
INT:MUX.HEX_V5[2] 0.F15.B2 0.F16.B2
HEX_H0[2] 0 1
NONE 1 0
LV[1] 1 1
INT:MUX.HEX_V5[3] 0.F14.B2 0.F13.B2
HEX_H0[3] 0 1
NONE 1 0
LV[1] 1 1
INT:MUX.IMUX_CAP_CAP 0.F37.B13 0.F36.B13 0.F31.B13 0.F30.B13 0.F33.B13 0.F34.B13 0.F32.B13 0.F35.B13
NONE 0 0 0 0 0 0 0 0
HEX_V0[0] 0 0 0 1 0 0 0 1
HEX_V4[1] 0 0 0 1 0 0 1 0
HEX_V1[0] 0 0 0 1 0 1 0 0
HEX_V5[1] 0 0 0 1 1 0 0 0
HEX_V2[1] 0 0 1 0 0 0 0 1
HEX_V0[1] 0 0 1 0 0 0 1 0
HEX_V3[1] 0 0 1 0 0 1 0 0
HEX_V1[1] 0 0 1 0 1 0 0 0
HEX_V4[0] 0 1 0 0 0 0 0 1
HEX_V2[0] 0 1 0 0 0 0 1 0
HEX_V5[0] 0 1 0 0 0 1 0 0
HEX_V3[0] 0 1 0 0 1 0 0 0
HEX_H0[2] 1 0 0 1 0 0 0 1
HEX_H4[3] 1 0 0 1 0 0 1 0
HEX_H1[2] 1 0 0 1 0 1 0 0
HEX_H5[3] 1 0 0 1 1 0 0 0
HEX_H2[3] 1 0 1 0 0 0 0 1
HEX_H0[3] 1 0 1 0 0 0 1 0
HEX_H3[3] 1 0 1 0 0 1 0 0
HEX_H1[3] 1 0 1 0 1 0 0 0
HEX_H4[2] 1 1 0 0 0 0 0 1
HEX_H2[2] 1 1 0 0 0 0 1 0
HEX_H5[2] 1 1 0 0 0 1 0 0
HEX_H3[2] 1 1 0 0 1 0 0 0
INT:MUX.IMUX_CAP_CLK 0.F17.B13 0.F15.B13 0.F9.B13 0.F8.B13 0.F16.B13 0.F12.B13 0.F10.B13 0.F11.B13 0.F14.B13 0.F13.B13
GCLK[0] 0 0 0 0 0 0 0 0 0 1
GCLK[1] 0 0 0 0 0 0 0 0 1 0
GCLK[2] 0 0 0 0 0 0 0 1 0 0
GCLK[3] 0 0 0 0 0 0 1 0 0 0
NONE 0 0 0 0 0 1 0 0 0 0
HEX_H1[0] 0 0 0 1 1 1 0 0 0 1
HEX_H0[0] 0 0 0 1 1 1 0 0 1 0
HEX_H5[1] 0 0 0 1 1 1 0 1 0 0
HEX_H4[1] 0 0 0 1 1 1 1 0 0 0
HEX_H3[1] 0 0 1 0 1 1 0 0 0 1
HEX_H2[1] 0 0 1 0 1 1 0 0 1 0
HEX_H1[1] 0 0 1 0 1 1 0 1 0 0
HEX_H0[1] 0 0 1 0 1 1 1 0 0 0
HEX_H5[0] 0 1 0 0 1 1 0 0 0 1
HEX_H4[0] 0 1 0 0 1 1 0 0 1 0
HEX_H3[0] 0 1 0 0 1 1 0 1 0 0
HEX_H2[0] 0 1 0 0 1 1 1 0 0 0
HEX_V1[2] 1 0 0 1 0 1 0 0 0 1
HEX_V0[2] 1 0 0 1 0 1 0 0 1 0
HEX_V5[3] 1 0 0 1 0 1 0 1 0 0
HEX_V4[3] 1 0 0 1 0 1 1 0 0 0
HEX_V3[3] 1 0 1 0 0 1 0 0 0 1
HEX_V2[3] 1 0 1 0 0 1 0 0 1 0
HEX_V1[3] 1 0 1 0 0 1 0 1 0 0
HEX_V0[3] 1 0 1 0 0 1 1 0 0 0
HEX_V5[2] 1 1 0 0 0 1 0 0 0 1
HEX_V4[2] 1 1 0 0 0 1 0 0 1 0
HEX_V3[2] 1 1 0 0 0 1 0 1 0 0
HEX_V2[2] 1 1 0 0 0 1 1 0 0 0
MISC:M0PIN 0.F9.B8 0.F9.B9
MISC:M1PIN 0.F11.B8 0.F10.B8
MISC:M2PIN 0.F10.B9 0.F11.B9
PULLDOWN 0 0
PULLNONE 0 1
PULLUP 1 1
MISC:PDSTATUSPIN 0.F8.B9
MISC:POWERDOWNPIN 0.F8.B8
PULLNONE 0
PULLUP 1
MISC:POWERUP_DELAY 0.F5.B0 0.F6.B0
100US 0 0
200US 0 1
400US 1 0