South-west

Tile CNR_SW

Cells: 1

Switchbox INT

virtex CNR_SW switchbox INT programmable buffers
Destination	Source	Bit
HEX_H0[0]	HEX_H0_MUX[0]	MAIN[35][8]
HEX_H0[1]	HEX_H0_MUX[1]	MAIN[30][8]
HEX_H0[2]	HEX_H0_MUX[2]	MAIN[17][8]
HEX_H0[3]	PCI_CE	MAIN[7][0]
HEX_H0[3]	HEX_H0_MUX[3]	MAIN[12][8]
HEX_H0[4]	HEX_H0_MUX[4]	MAIN[14][9]
HEX_H0[5]	HEX_H0_MUX[5]	MAIN[12][9]
HEX_H1[0]	HEX_H1_MUX[0]	MAIN[41][8]
HEX_H1[1]	HEX_H1_MUX[1]	MAIN[36][8]
HEX_H1[2]	HEX_H1_MUX[2]	MAIN[23][8]
HEX_H1[3]	HEX_H1_MUX[3]	MAIN[18][8]
HEX_H1[4]	HEX_H1_MUX[4]	MAIN[17][9]
HEX_H1[5]	HEX_H1_MUX[5]	MAIN[15][9]
HEX_H2[0]	HEX_H2_MUX[0]	MAIN[47][8]
HEX_H2[1]	HEX_H2_MUX[1]	MAIN[42][8]
HEX_H2[2]	HEX_H2_MUX[2]	MAIN[29][8]
HEX_H2[3]	HEX_H2_MUX[3]	MAIN[24][8]
HEX_H2[4]	HEX_H2_MUX[4]	MAIN[20][9]
HEX_H2[5]	HEX_H2_MUX[5]	MAIN[18][9]
HEX_H3[0]	HEX_H3_MUX[0]	MAIN[35][4]
HEX_H3[1]	HEX_H3_MUX[1]	MAIN[30][4]
HEX_H3[2]	HEX_H3_MUX[2]	MAIN[17][4]
HEX_H3[3]	HEX_H3_MUX[3]	MAIN[12][4]
HEX_H3[4]	HEX_H3_MUX[4]	MAIN[23][9]
HEX_H3[5]	HEX_H3_MUX[5]	MAIN[21][9]
HEX_H4[0]	HEX_H4_MUX[0]	MAIN[41][4]
HEX_H4[1]	HEX_H4_MUX[1]	MAIN[36][4]
HEX_H4[2]	HEX_H4_MUX[2]	MAIN[23][4]
HEX_H4[3]	HEX_H4_MUX[3]	MAIN[18][4]
HEX_H4[4]	HEX_H4_MUX[4]	MAIN[34][9]
HEX_H4[5]	HEX_H4_MUX[5]	MAIN[24][9]
HEX_H5[0]	HEX_H5_MUX[0]	MAIN[47][4]
HEX_H5[1]	HEX_H5_MUX[1]	MAIN[42][4]
HEX_H5[2]	HEX_H5_MUX[2]	MAIN[29][4]
HEX_H5[3]	HEX_H5_MUX[3]	MAIN[24][4]
HEX_H5[4]	HEX_H5_MUX[4]	MAIN[29][9]
HEX_H5[5]	HEX_H5_MUX[5]	MAIN[27][9]
HEX_V0[0]	HEX_V0_MUX[0]	MAIN[47][0]
HEX_V0[1]	HEX_V0_MUX[1]	MAIN[42][0]
HEX_V0[2]	HEX_V0_MUX[2]	MAIN[29][0]
HEX_V0[3]	HEX_V0_MUX[3]	MAIN[24][0]
HEX_V1[0]	HEX_V1_MUX[0]	MAIN[41][0]
HEX_V1[1]	HEX_V1_MUX[1]	MAIN[36][0]
HEX_V1[2]	HEX_V1_MUX[2]	MAIN[23][0]
HEX_V1[3]	HEX_V1_MUX[3]	MAIN[18][0]
HEX_V2[0]	HEX_V2_MUX[0]	MAIN[35][0]
HEX_V2[1]	HEX_V2_MUX[1]	MAIN[30][0]
HEX_V2[2]	HEX_V2_MUX[2]	MAIN[17][0]
HEX_V2[3]	HEX_V2_MUX[3]	MAIN[12][0]
HEX_V3[0]	HEX_V3_MUX[0]	MAIN[47][2]
HEX_V3[1]	HEX_V3_MUX[1]	MAIN[42][2]
HEX_V3[2]	HEX_V3_MUX[2]	MAIN[29][2]
HEX_V3[3]	HEX_V3_MUX[3]	MAIN[24][2]
HEX_V4[0]	HEX_V4_MUX[0]	MAIN[41][2]
HEX_V4[1]	HEX_V4_MUX[1]	MAIN[36][2]
HEX_V4[2]	HEX_V4_MUX[2]	MAIN[23][2]
HEX_V4[3]	HEX_V4_MUX[3]	MAIN[18][2]
HEX_V5[0]	HEX_V5_MUX[0]	MAIN[35][2]
HEX_V5[1]	HEX_V5_MUX[1]	MAIN[30][2]
HEX_V5[2]	HEX_V5_MUX[2]	MAIN[17][2]
HEX_V5[3]	HEX_V5_MUX[3]	MAIN[12][2]
LV[0]	HEX_H0[5]	MAIN[47][9]
LV[1]	HEX_H5[5]	MAIN[46][9]
LV[2]	HEX_H4[5]	MAIN[45][9]
LV[3]	HEX_H3[5]	MAIN[44][9]
LV[4]	HEX_H2[5]	MAIN[43][9]
LV[5]	HEX_H1[5]	MAIN[42][9]
LV[6]	HEX_H0[4]	MAIN[41][9]
LV[7]	HEX_H5[4]	MAIN[40][9]
LV[8]	HEX_H4[4]	MAIN[39][9]
LV[9]	HEX_H3[4]	MAIN[38][9]
LV[10]	HEX_H2[4]	MAIN[37][9]
LV[11]	HEX_H1[4]	MAIN[36][9]

virtex CNR_SW switchbox INT muxes HEX_H0_MUX[0]
Bits		Destination
MAIN[33][8]	MAIN[34][8]	HEX_H0_MUX[0]
		Source
0	1	HEX_V5[0]
1	0	off
1	1	LH[0]

virtex CNR_SW switchbox INT muxes HEX_H0_MUX[1]
Bits		Destination
MAIN[32][8]	MAIN[31][8]	HEX_H0_MUX[1]
		Source
0	1	HEX_V5[1]
1	0	off
1	1	LH[0]

virtex CNR_SW switchbox INT muxes HEX_H0_MUX[2]
Bits		Destination
MAIN[15][8]	MAIN[16][8]	HEX_H0_MUX[2]
		Source
0	1	HEX_V5[2]
1	0	off
1	1	LH[6]

virtex CNR_SW switchbox INT muxes HEX_H0_MUX[3]
Bits		Destination
MAIN[14][8]	MAIN[13][8]	HEX_H0_MUX[3]
		Source
0	1	HEX_V5[3]
1	0	off
1	1	LH[6]

virtex CNR_SW switchbox INT muxes HEX_H0_MUX[4]
Bits	Destination
MAIN[30][9]	HEX_H0_MUX[4]
	Source
0	LH[0]
1	LH[6]

virtex CNR_SW switchbox INT muxes HEX_H0_MUX[5]
Bits	Destination
MAIN[13][9]	HEX_H0_MUX[5]
	Source
0	LH[0]
1	LH[6]

virtex CNR_SW switchbox INT muxes HEX_H1_MUX[0]
Bits		Destination
MAIN[39][8]	MAIN[40][8]	HEX_H1_MUX[0]
		Source
0	1	HEX_V4[0]
1	0	off
1	1	LH[11]

virtex CNR_SW switchbox INT muxes HEX_H1_MUX[1]
Bits		Destination
MAIN[38][8]	MAIN[37][8]	HEX_H1_MUX[1]
		Source
0	1	HEX_V4[1]
1	0	off
1	1	LH[11]

virtex CNR_SW switchbox INT muxes HEX_H1_MUX[2]
Bits		Destination
MAIN[21][8]	MAIN[22][8]	HEX_H1_MUX[2]
		Source
0	1	HEX_V4[2]
1	0	off
1	1	LH[5]

virtex CNR_SW switchbox INT muxes HEX_H1_MUX[3]
Bits		Destination
MAIN[20][8]	MAIN[19][8]	HEX_H1_MUX[3]
		Source
0	1	HEX_V4[3]
1	0	off
1	1	LH[5]

virtex CNR_SW switchbox INT muxes HEX_H1_MUX[4]
Bits	Destination
MAIN[16][9]	HEX_H1_MUX[4]
	Source
0	LH[11]
1	LH[5]

virtex CNR_SW switchbox INT muxes HEX_H1_MUX[5]
Bits	Destination
MAIN[31][9]	HEX_H1_MUX[5]
	Source
0	LH[11]
1	LH[5]

virtex CNR_SW switchbox INT muxes HEX_H2_MUX[0]
Bits		Destination
MAIN[45][8]	MAIN[46][8]	HEX_H2_MUX[0]
		Source
0	1	HEX_V3[0]
1	0	off
1	1	LH[10]

virtex CNR_SW switchbox INT muxes HEX_H2_MUX[1]
Bits		Destination
MAIN[44][8]	MAIN[43][8]	HEX_H2_MUX[1]
		Source
0	1	HEX_V3[1]
1	0	off
1	1	LH[10]

virtex CNR_SW switchbox INT muxes HEX_H2_MUX[2]
Bits		Destination
MAIN[27][8]	MAIN[28][8]	HEX_H2_MUX[2]
		Source
0	1	HEX_V3[2]
1	0	off
1	1	LH[4]

virtex CNR_SW switchbox INT muxes HEX_H2_MUX[3]
Bits		Destination
MAIN[26][8]	MAIN[25][8]	HEX_H2_MUX[3]
		Source
0	1	HEX_V3[3]
1	0	off
1	1	LH[4]

virtex CNR_SW switchbox INT muxes HEX_H2_MUX[4]
Bits	Destination
MAIN[32][9]	HEX_H2_MUX[4]
	Source
0	LH[10]
1	LH[4]

virtex CNR_SW switchbox INT muxes HEX_H2_MUX[5]
Bits	Destination
MAIN[19][9]	HEX_H2_MUX[5]
	Source
0	LH[10]
1	LH[4]

virtex CNR_SW switchbox INT muxes HEX_H3_MUX[0]
Bits		Destination
MAIN[33][4]	MAIN[34][4]	HEX_H3_MUX[0]
		Source
0	1	HEX_V2[0]
1	0	off
1	1	LH[9]

virtex CNR_SW switchbox INT muxes HEX_H3_MUX[1]
Bits		Destination
MAIN[32][4]	MAIN[31][4]	HEX_H3_MUX[1]
		Source
0	1	HEX_V2[1]
1	0	off
1	1	LH[9]

virtex CNR_SW switchbox INT muxes HEX_H3_MUX[2]
Bits		Destination
MAIN[15][4]	MAIN[16][4]	HEX_H3_MUX[2]
		Source
0	1	HEX_V2[2]
1	0	off
1	1	LH[3]

virtex CNR_SW switchbox INT muxes HEX_H3_MUX[3]
Bits		Destination
MAIN[14][4]	MAIN[13][4]	HEX_H3_MUX[3]
		Source
0	1	HEX_V2[3]
1	0	off
1	1	LH[3]

virtex CNR_SW switchbox INT muxes HEX_H3_MUX[4]
Bits	Destination
MAIN[33][9]	HEX_H3_MUX[4]
	Source
0	LH[9]
1	LH[3]

virtex CNR_SW switchbox INT muxes HEX_H3_MUX[5]
Bits	Destination
MAIN[22][9]	HEX_H3_MUX[5]
	Source
0	LH[9]
1	LH[3]

virtex CNR_SW switchbox INT muxes HEX_H4_MUX[0]
Bits		Destination
MAIN[39][4]	MAIN[40][4]	HEX_H4_MUX[0]
		Source
0	1	HEX_V1[0]
1	0	off
1	1	LH[8]

virtex CNR_SW switchbox INT muxes HEX_H4_MUX[1]
Bits		Destination
MAIN[38][4]	MAIN[37][4]	HEX_H4_MUX[1]
		Source
0	1	HEX_V1[1]
1	0	off
1	1	LH[8]

virtex CNR_SW switchbox INT muxes HEX_H4_MUX[2]
Bits		Destination
MAIN[21][4]	MAIN[22][4]	HEX_H4_MUX[2]
		Source
0	1	HEX_V1[2]
1	0	off
1	1	LH[2]

virtex CNR_SW switchbox INT muxes HEX_H4_MUX[3]
Bits		Destination
MAIN[20][4]	MAIN[19][4]	HEX_H4_MUX[3]
		Source
0	1	HEX_V1[3]
1	0	off
1	1	LH[2]

virtex CNR_SW switchbox INT muxes HEX_H4_MUX[4]
Bits	Destination
MAIN[26][9]	HEX_H4_MUX[4]
	Source
0	LH[8]
1	LH[2]

virtex CNR_SW switchbox INT muxes HEX_H4_MUX[5]
Bits	Destination
MAIN[25][9]	HEX_H4_MUX[5]
	Source
0	LH[8]
1	LH[2]

virtex CNR_SW switchbox INT muxes HEX_H5_MUX[0]
Bits		Destination
MAIN[45][4]	MAIN[46][4]	HEX_H5_MUX[0]
		Source
0	1	HEX_V0[0]
1	0	off
1	1	LH[7]

virtex CNR_SW switchbox INT muxes HEX_H5_MUX[1]
Bits		Destination
MAIN[44][4]	MAIN[43][4]	HEX_H5_MUX[1]
		Source
0	1	HEX_V0[1]
1	0	off
1	1	LH[7]

virtex CNR_SW switchbox INT muxes HEX_H5_MUX[2]
Bits		Destination
MAIN[27][4]	MAIN[28][4]	HEX_H5_MUX[2]
		Source
0	1	HEX_V0[2]
1	0	off
1	1	LH[1]

virtex CNR_SW switchbox INT muxes HEX_H5_MUX[3]
Bits		Destination
MAIN[26][4]	MAIN[25][4]	HEX_H5_MUX[3]
		Source
0	1	HEX_V0[3]
1	0	off
1	1	LH[1]

virtex CNR_SW switchbox INT muxes HEX_H5_MUX[4]
Bits	Destination
MAIN[35][9]	HEX_H5_MUX[4]
	Source
0	LH[7]
1	LH[1]

virtex CNR_SW switchbox INT muxes HEX_H5_MUX[5]
Bits	Destination
MAIN[28][9]	HEX_H5_MUX[5]
	Source
0	LH[7]
1	LH[1]

virtex CNR_SW switchbox INT muxes HEX_V0_MUX[0]
Bits		Destination
MAIN[45][0]	MAIN[46][0]	HEX_V0_MUX[0]
		Source
0	1	HEX_H5[0]
1	0	off
1	1	LV[0]

virtex CNR_SW switchbox INT muxes HEX_V0_MUX[1]
Bits		Destination
MAIN[44][0]	MAIN[43][0]	HEX_V0_MUX[1]
		Source
0	1	HEX_H5[1]
1	0	off
1	1	LV[0]

virtex CNR_SW switchbox INT muxes HEX_V0_MUX[2]
Bits		Destination
MAIN[27][0]	MAIN[28][0]	HEX_V0_MUX[2]
		Source
0	1	HEX_H5[2]
1	0	off
1	1	LV[6]

virtex CNR_SW switchbox INT muxes HEX_V0_MUX[3]
Bits		Destination
MAIN[26][0]	MAIN[25][0]	HEX_V0_MUX[3]
		Source
0	1	HEX_H5[3]
1	0	off
1	1	LV[6]

virtex CNR_SW switchbox INT muxes HEX_V1_MUX[0]
Bits		Destination
MAIN[39][0]	MAIN[40][0]	HEX_V1_MUX[0]
		Source
0	1	HEX_H4[0]
1	0	off
1	1	LV[11]

virtex CNR_SW switchbox INT muxes HEX_V1_MUX[1]
Bits		Destination
MAIN[38][0]	MAIN[37][0]	HEX_V1_MUX[1]
		Source
0	1	HEX_H4[1]
1	0	off
1	1	LV[11]

virtex CNR_SW switchbox INT muxes HEX_V1_MUX[2]
Bits		Destination
MAIN[21][0]	MAIN[22][0]	HEX_V1_MUX[2]
		Source
0	1	HEX_H4[2]
1	0	off
1	1	LV[5]

virtex CNR_SW switchbox INT muxes HEX_V1_MUX[3]
Bits		Destination
MAIN[20][0]	MAIN[19][0]	HEX_V1_MUX[3]
		Source
0	1	HEX_H4[3]
1	0	off
1	1	LV[5]

virtex CNR_SW switchbox INT muxes HEX_V2_MUX[0]
Bits		Destination
MAIN[33][0]	MAIN[34][0]	HEX_V2_MUX[0]
		Source
0	1	HEX_H3[0]
1	0	off
1	1	LV[10]

virtex CNR_SW switchbox INT muxes HEX_V2_MUX[1]
Bits		Destination
MAIN[32][0]	MAIN[31][0]	HEX_V2_MUX[1]
		Source
0	1	HEX_H3[1]
1	0	off
1	1	LV[10]

virtex CNR_SW switchbox INT muxes HEX_V2_MUX[2]
Bits		Destination
MAIN[15][0]	MAIN[16][0]	HEX_V2_MUX[2]
		Source
0	1	HEX_H3[2]
1	0	off
1	1	LV[4]

virtex CNR_SW switchbox INT muxes HEX_V2_MUX[3]
Bits		Destination
MAIN[14][0]	MAIN[13][0]	HEX_V2_MUX[3]
		Source
0	1	HEX_H3[3]
1	0	off
1	1	LV[4]

virtex CNR_SW switchbox INT muxes HEX_V3_MUX[0]
Bits		Destination
MAIN[45][2]	MAIN[46][2]	HEX_V3_MUX[0]
		Source
0	1	HEX_H2[0]
1	0	off
1	1	LV[9]

virtex CNR_SW switchbox INT muxes HEX_V3_MUX[1]
Bits		Destination
MAIN[44][2]	MAIN[43][2]	HEX_V3_MUX[1]
		Source
0	1	HEX_H2[1]
1	0	off
1	1	LV[9]

virtex CNR_SW switchbox INT muxes HEX_V3_MUX[2]
Bits		Destination
MAIN[27][2]	MAIN[28][2]	HEX_V3_MUX[2]
		Source
0	1	HEX_H2[2]
1	0	off
1	1	LV[3]

virtex CNR_SW switchbox INT muxes HEX_V3_MUX[3]
Bits		Destination
MAIN[26][2]	MAIN[25][2]	HEX_V3_MUX[3]
		Source
0	1	HEX_H2[3]
1	0	off
1	1	LV[3]

virtex CNR_SW switchbox INT muxes HEX_V4_MUX[0]
Bits		Destination
MAIN[39][2]	MAIN[40][2]	HEX_V4_MUX[0]
		Source
0	1	HEX_H1[0]
1	0	off
1	1	LV[8]

virtex CNR_SW switchbox INT muxes HEX_V4_MUX[1]
Bits		Destination
MAIN[38][2]	MAIN[37][2]	HEX_V4_MUX[1]
		Source
0	1	HEX_H1[1]
1	0	off
1	1	LV[8]

virtex CNR_SW switchbox INT muxes HEX_V4_MUX[2]
Bits		Destination
MAIN[21][2]	MAIN[22][2]	HEX_V4_MUX[2]
		Source
0	1	HEX_H1[2]
1	0	off
1	1	LV[2]

virtex CNR_SW switchbox INT muxes HEX_V4_MUX[3]
Bits		Destination
MAIN[20][2]	MAIN[19][2]	HEX_V4_MUX[3]
		Source
0	1	HEX_H1[3]
1	0	off
1	1	LV[2]

virtex CNR_SW switchbox INT muxes HEX_V5_MUX[0]
Bits		Destination
MAIN[33][2]	MAIN[34][2]	HEX_V5_MUX[0]
		Source
0	1	HEX_H0[0]
1	0	off
1	1	LV[7]

virtex CNR_SW switchbox INT muxes HEX_V5_MUX[1]
Bits		Destination
MAIN[32][2]	MAIN[31][2]	HEX_V5_MUX[1]
		Source
0	1	HEX_H0[1]
1	0	off
1	1	LV[7]

virtex CNR_SW switchbox INT muxes HEX_V5_MUX[2]
Bits		Destination
MAIN[15][2]	MAIN[16][2]	HEX_V5_MUX[2]
		Source
0	1	HEX_H0[2]
1	0	off
1	1	LV[1]

virtex CNR_SW switchbox INT muxes HEX_V5_MUX[3]
Bits		Destination
MAIN[14][2]	MAIN[13][2]	HEX_V5_MUX[3]
		Source
0	1	HEX_H0[3]
1	0	off
1	1	LV[1]

virtex CNR_SW switchbox INT muxes IMUX_CAP_CLK
Bits										Destination
MAIN[17][13]	MAIN[15][13]	MAIN[9][13]	MAIN[8][13]	MAIN[16][13]	MAIN[10][13]	MAIN[11][13]	MAIN[14][13]	MAIN[13][13]	MAIN[12][13]	IMUX_CAP_CLK
										Source
0	0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	0	0	1	0	GCLK_LEAF[0]
0	0	0	0	0	0	0	1	0	0	GCLK_LEAF[1]
0	0	0	0	0	0	1	0	0	0	GCLK_LEAF[2]
0	0	0	0	0	1	0	0	0	0	GCLK_LEAF[3]
0	0	0	1	1	0	0	0	1	1	HEX_H1[0]
0	0	0	1	1	0	0	1	0	1	HEX_H0[0]
0	0	0	1	1	0	1	0	0	1	HEX_H5[1]
0	0	0	1	1	1	0	0	0	1	HEX_H4[1]
0	0	1	0	1	0	0	0	1	1	HEX_H3[1]
0	0	1	0	1	0	0	1	0	1	HEX_H2[1]
0	0	1	0	1	0	1	0	0	1	HEX_H1[1]
0	0	1	0	1	1	0	0	0	1	HEX_H0[1]
0	1	0	0	1	0	0	0	1	1	HEX_H5[0]
0	1	0	0	1	0	0	1	0	1	HEX_H4[0]
0	1	0	0	1	0	1	0	0	1	HEX_H3[0]
0	1	0	0	1	1	0	0	0	1	HEX_H2[0]
1	0	0	1	0	0	0	0	1	1	HEX_V1[2]
1	0	0	1	0	0	0	1	0	1	HEX_V0[2]
1	0	0	1	0	0	1	0	0	1	HEX_V5[3]
1	0	0	1	0	1	0	0	0	1	HEX_V4[3]
1	0	1	0	0	0	0	0	1	1	HEX_V3[3]
1	0	1	0	0	0	0	1	0	1	HEX_V2[3]
1	0	1	0	0	0	1	0	0	1	HEX_V1[3]
1	0	1	0	0	1	0	0	0	1	HEX_V0[3]
1	1	0	0	0	0	0	0	1	1	HEX_V5[2]
1	1	0	0	0	0	0	1	0	1	HEX_V4[2]
1	1	0	0	0	0	1	0	0	1	HEX_V3[2]
1	1	0	0	0	1	0	0	0	1	HEX_V2[2]

virtex CNR_SW switchbox INT muxes IMUX_CAP_CAP
Bits								Destination
MAIN[37][13]	MAIN[36][13]	MAIN[31][13]	MAIN[30][13]	MAIN[33][13]	MAIN[34][13]	MAIN[32][13]	MAIN[35][13]	IMUX_CAP_CAP
								Source
0	0	0	0	0	0	0	0	PULLUP
0	0	0	1	0	0	0	1	HEX_V0[0]
0	0	0	1	0	0	1	0	HEX_V4[1]
0	0	0	1	0	1	0	0	HEX_V1[0]
0	0	0	1	1	0	0	0	HEX_V5[1]
0	0	1	0	0	0	0	1	HEX_V2[1]
0	0	1	0	0	0	1	0	HEX_V0[1]
0	0	1	0	0	1	0	0	HEX_V3[1]
0	0	1	0	1	0	0	0	HEX_V1[1]
0	1	0	0	0	0	0	1	HEX_V4[0]
0	1	0	0	0	0	1	0	HEX_V2[0]
0	1	0	0	0	1	0	0	HEX_V5[0]
0	1	0	0	1	0	0	0	HEX_V3[0]
1	0	0	1	0	0	0	1	HEX_H0[2]
1	0	0	1	0	0	1	0	HEX_H4[3]
1	0	0	1	0	1	0	0	HEX_H1[2]
1	0	0	1	1	0	0	0	HEX_H5[3]
1	0	1	0	0	0	0	1	HEX_H2[3]
1	0	1	0	0	0	1	0	HEX_H0[3]
1	0	1	0	0	1	0	0	HEX_H3[3]
1	0	1	0	1	0	0	0	HEX_H1[3]
1	1	0	0	0	0	0	1	HEX_H4[2]
1	1	0	0	0	0	1	0	HEX_H2[2]
1	1	0	0	0	1	0	0	HEX_H5[2]
1	1	0	0	1	0	0	0	HEX_H3[2]

Bels CAPTURE

virtex CNR_SW bel CAPTURE pins
Pin	Direction	CAPTURE
CLK	in	IMUX_CAP_CLK invert by !MAIN[18][13]
CAP	in	IMUX_CAP_CAP invert by !MAIN[38][13]

Bels MISC_SW

virtex CNR_SW bel MISC_SW pins
Pin	Direction	MISC_SW

virtex CNR_SW bel MISC_SW attribute bits
Attribute	MISC_SW
M0_PULL	[enum: IOB_PULL]
M1_PULL	[enum: IOB_PULL]
M2_PULL	[enum: IOB_PULL]

virtex CNR_SW enum IOB_PULL
MISC_SW.M0_PULL	MAIN[9][8]	MAIN[9][9]
MISC_SW.M1_PULL	MAIN[11][8]	MAIN[10][8]
MISC_SW.M2_PULL	MAIN[10][9]	MAIN[11][9]
NONE	0	1
PULLUP	1	1
PULLDOWN	0	0

Bel wires

virtex CNR_SW bel wires
Wire	Pins
IMUX_CAP_CLK	CAPTURE.CLK
IMUX_CAP_CAP	CAPTURE.CAP

Bitstream

virtex CNR_SW rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	INT: mux IMUX_CAP_CLK bit 6	INT: mux IMUX_CAP_CLK bit 7	INT: mux IMUX_CAP_CLK bit 4	INT: mux IMUX_CAP_CLK bit 3	INT: mux IMUX_CAP_CLK bit 0	INT: mux IMUX_CAP_CLK bit 1	INT: mux IMUX_CAP_CLK bit 2	INT: mux IMUX_CAP_CLK bit 8	INT: mux IMUX_CAP_CLK bit 5	INT: mux IMUX_CAP_CLK bit 9	CAPTURE: !invert CLK	-	-	-	-	-	-	-	-	-	-	-	INT: mux IMUX_CAP_CAP bit 4	INT: mux IMUX_CAP_CAP bit 5	INT: mux IMUX_CAP_CAP bit 1	INT: mux IMUX_CAP_CAP bit 3	INT: mux IMUX_CAP_CAP bit 2	INT: mux IMUX_CAP_CAP bit 0	INT: mux IMUX_CAP_CAP bit 6	INT: mux IMUX_CAP_CAP bit 7	CAPTURE: !invert CAP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	MISC_SW: M0_PULL bit 0	MISC_SW: M2_PULL bit 1	MISC_SW: M2_PULL bit 0	INT: buffer HEX_H0[5] ← HEX_H0_MUX[5]	INT: mux HEX_H0_MUX[5] bit 0	INT: buffer HEX_H0[4] ← HEX_H0_MUX[4]	INT: buffer HEX_H1[5] ← HEX_H1_MUX[5]	INT: mux HEX_H1_MUX[4] bit 0	INT: buffer HEX_H1[4] ← HEX_H1_MUX[4]	INT: buffer HEX_H2[5] ← HEX_H2_MUX[5]	INT: mux HEX_H2_MUX[5] bit 0	INT: buffer HEX_H2[4] ← HEX_H2_MUX[4]	INT: buffer HEX_H3[5] ← HEX_H3_MUX[5]	INT: mux HEX_H3_MUX[5] bit 0	INT: buffer HEX_H3[4] ← HEX_H3_MUX[4]	INT: buffer HEX_H4[5] ← HEX_H4_MUX[5]	INT: mux HEX_H4_MUX[5] bit 0	INT: mux HEX_H4_MUX[4] bit 0	INT: buffer HEX_H5[5] ← HEX_H5_MUX[5]	INT: mux HEX_H5_MUX[5] bit 0	INT: buffer HEX_H5[4] ← HEX_H5_MUX[4]	INT: mux HEX_H0_MUX[4] bit 0	INT: mux HEX_H1_MUX[5] bit 0	INT: mux HEX_H2_MUX[4] bit 0	INT: mux HEX_H3_MUX[4] bit 0	INT: buffer HEX_H4[4] ← HEX_H4_MUX[4]	INT: mux HEX_H5_MUX[4] bit 0	INT: buffer LV[11] ← HEX_H1[4]	INT: buffer LV[10] ← HEX_H2[4]	INT: buffer LV[9] ← HEX_H3[4]	INT: buffer LV[8] ← HEX_H4[4]	INT: buffer LV[7] ← HEX_H5[4]	INT: buffer LV[6] ← HEX_H0[4]	INT: buffer LV[5] ← HEX_H1[5]	INT: buffer LV[4] ← HEX_H2[5]	INT: buffer LV[3] ← HEX_H3[5]	INT: buffer LV[2] ← HEX_H4[5]	INT: buffer LV[1] ← HEX_H5[5]	INT: buffer LV[0] ← HEX_H0[5]	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	MISC_SW: M0_PULL bit 1	MISC_SW: M1_PULL bit 0	MISC_SW: M1_PULL bit 1	INT: buffer HEX_H0[3] ← HEX_H0_MUX[3]	INT: mux HEX_H0_MUX[3] bit 0	INT: mux HEX_H0_MUX[3] bit 1	INT: mux HEX_H0_MUX[2] bit 1	INT: mux HEX_H0_MUX[2] bit 0	INT: buffer HEX_H0[2] ← HEX_H0_MUX[2]	INT: buffer HEX_H1[3] ← HEX_H1_MUX[3]	INT: mux HEX_H1_MUX[3] bit 0	INT: mux HEX_H1_MUX[3] bit 1	INT: mux HEX_H1_MUX[2] bit 1	INT: mux HEX_H1_MUX[2] bit 0	INT: buffer HEX_H1[2] ← HEX_H1_MUX[2]	INT: buffer HEX_H2[3] ← HEX_H2_MUX[3]	INT: mux HEX_H2_MUX[3] bit 0	INT: mux HEX_H2_MUX[3] bit 1	INT: mux HEX_H2_MUX[2] bit 1	INT: mux HEX_H2_MUX[2] bit 0	INT: buffer HEX_H2[2] ← HEX_H2_MUX[2]	INT: buffer HEX_H0[1] ← HEX_H0_MUX[1]	INT: mux HEX_H0_MUX[1] bit 0	INT: mux HEX_H0_MUX[1] bit 1	INT: mux HEX_H0_MUX[0] bit 1	INT: mux HEX_H0_MUX[0] bit 0	INT: buffer HEX_H0[0] ← HEX_H0_MUX[0]	INT: buffer HEX_H1[1] ← HEX_H1_MUX[1]	INT: mux HEX_H1_MUX[1] bit 0	INT: mux HEX_H1_MUX[1] bit 1	INT: mux HEX_H1_MUX[0] bit 1	INT: mux HEX_H1_MUX[0] bit 0	INT: buffer HEX_H1[0] ← HEX_H1_MUX[0]	INT: buffer HEX_H2[1] ← HEX_H2_MUX[1]	INT: mux HEX_H2_MUX[1] bit 0	INT: mux HEX_H2_MUX[1] bit 1	INT: mux HEX_H2_MUX[0] bit 1	INT: mux HEX_H2_MUX[0] bit 0	INT: buffer HEX_H2[0] ← HEX_H2_MUX[0]	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	INT: buffer HEX_H3[3] ← HEX_H3_MUX[3]	INT: mux HEX_H3_MUX[3] bit 0	INT: mux HEX_H3_MUX[3] bit 1	INT: mux HEX_H3_MUX[2] bit 1	INT: mux HEX_H3_MUX[2] bit 0	INT: buffer HEX_H3[2] ← HEX_H3_MUX[2]	INT: buffer HEX_H4[3] ← HEX_H4_MUX[3]	INT: mux HEX_H4_MUX[3] bit 0	INT: mux HEX_H4_MUX[3] bit 1	INT: mux HEX_H4_MUX[2] bit 1	INT: mux HEX_H4_MUX[2] bit 0	INT: buffer HEX_H4[2] ← HEX_H4_MUX[2]	INT: buffer HEX_H5[3] ← HEX_H5_MUX[3]	INT: mux HEX_H5_MUX[3] bit 0	INT: mux HEX_H5_MUX[3] bit 1	INT: mux HEX_H5_MUX[2] bit 1	INT: mux HEX_H5_MUX[2] bit 0	INT: buffer HEX_H5[2] ← HEX_H5_MUX[2]	INT: buffer HEX_H3[1] ← HEX_H3_MUX[1]	INT: mux HEX_H3_MUX[1] bit 0	INT: mux HEX_H3_MUX[1] bit 1	INT: mux HEX_H3_MUX[0] bit 1	INT: mux HEX_H3_MUX[0] bit 0	INT: buffer HEX_H3[0] ← HEX_H3_MUX[0]	INT: buffer HEX_H4[1] ← HEX_H4_MUX[1]	INT: mux HEX_H4_MUX[1] bit 0	INT: mux HEX_H4_MUX[1] bit 1	INT: mux HEX_H4_MUX[0] bit 1	INT: mux HEX_H4_MUX[0] bit 0	INT: buffer HEX_H4[0] ← HEX_H4_MUX[0]	INT: buffer HEX_H5[1] ← HEX_H5_MUX[1]	INT: mux HEX_H5_MUX[1] bit 0	INT: mux HEX_H5_MUX[1] bit 1	INT: mux HEX_H5_MUX[0] bit 1	INT: mux HEX_H5_MUX[0] bit 0	INT: buffer HEX_H5[0] ← HEX_H5_MUX[0]	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	INT: buffer HEX_V5[3] ← HEX_V5_MUX[3]	INT: mux HEX_V5_MUX[3] bit 0	INT: mux HEX_V5_MUX[3] bit 1	INT: mux HEX_V5_MUX[2] bit 1	INT: mux HEX_V5_MUX[2] bit 0	INT: buffer HEX_V5[2] ← HEX_V5_MUX[2]	INT: buffer HEX_V4[3] ← HEX_V4_MUX[3]	INT: mux HEX_V4_MUX[3] bit 0	INT: mux HEX_V4_MUX[3] bit 1	INT: mux HEX_V4_MUX[2] bit 1	INT: mux HEX_V4_MUX[2] bit 0	INT: buffer HEX_V4[2] ← HEX_V4_MUX[2]	INT: buffer HEX_V3[3] ← HEX_V3_MUX[3]	INT: mux HEX_V3_MUX[3] bit 0	INT: mux HEX_V3_MUX[3] bit 1	INT: mux HEX_V3_MUX[2] bit 1	INT: mux HEX_V3_MUX[2] bit 0	INT: buffer HEX_V3[2] ← HEX_V3_MUX[2]	INT: buffer HEX_V5[1] ← HEX_V5_MUX[1]	INT: mux HEX_V5_MUX[1] bit 0	INT: mux HEX_V5_MUX[1] bit 1	INT: mux HEX_V5_MUX[0] bit 1	INT: mux HEX_V5_MUX[0] bit 0	INT: buffer HEX_V5[0] ← HEX_V5_MUX[0]	INT: buffer HEX_V4[1] ← HEX_V4_MUX[1]	INT: mux HEX_V4_MUX[1] bit 0	INT: mux HEX_V4_MUX[1] bit 1	INT: mux HEX_V4_MUX[0] bit 1	INT: mux HEX_V4_MUX[0] bit 0	INT: buffer HEX_V4[0] ← HEX_V4_MUX[0]	INT: buffer HEX_V3[1] ← HEX_V3_MUX[1]	INT: mux HEX_V3_MUX[1] bit 0	INT: mux HEX_V3_MUX[1] bit 1	INT: mux HEX_V3_MUX[0] bit 1	INT: mux HEX_V3_MUX[0] bit 0	INT: buffer HEX_V3[0] ← HEX_V3_MUX[0]	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	INT: buffer HEX_H0[3] ← PCI_CE	-	-	-	-	INT: buffer HEX_V2[3] ← HEX_V2_MUX[3]	INT: mux HEX_V2_MUX[3] bit 0	INT: mux HEX_V2_MUX[3] bit 1	INT: mux HEX_V2_MUX[2] bit 1	INT: mux HEX_V2_MUX[2] bit 0	INT: buffer HEX_V2[2] ← HEX_V2_MUX[2]	INT: buffer HEX_V1[3] ← HEX_V1_MUX[3]	INT: mux HEX_V1_MUX[3] bit 0	INT: mux HEX_V1_MUX[3] bit 1	INT: mux HEX_V1_MUX[2] bit 1	INT: mux HEX_V1_MUX[2] bit 0	INT: buffer HEX_V1[2] ← HEX_V1_MUX[2]	INT: buffer HEX_V0[3] ← HEX_V0_MUX[3]	INT: mux HEX_V0_MUX[3] bit 0	INT: mux HEX_V0_MUX[3] bit 1	INT: mux HEX_V0_MUX[2] bit 1	INT: mux HEX_V0_MUX[2] bit 0	INT: buffer HEX_V0[2] ← HEX_V0_MUX[2]	INT: buffer HEX_V2[1] ← HEX_V2_MUX[1]	INT: mux HEX_V2_MUX[1] bit 0	INT: mux HEX_V2_MUX[1] bit 1	INT: mux HEX_V2_MUX[0] bit 1	INT: mux HEX_V2_MUX[0] bit 0	INT: buffer HEX_V2[0] ← HEX_V2_MUX[0]	INT: buffer HEX_V1[1] ← HEX_V1_MUX[1]	INT: mux HEX_V1_MUX[1] bit 0	INT: mux HEX_V1_MUX[1] bit 1	INT: mux HEX_V1_MUX[0] bit 1	INT: mux HEX_V1_MUX[0] bit 0	INT: buffer HEX_V1[0] ← HEX_V1_MUX[0]	INT: buffer HEX_V0[1] ← HEX_V0_MUX[1]	INT: mux HEX_V0_MUX[1] bit 0	INT: mux HEX_V0_MUX[1] bit 1	INT: mux HEX_V0_MUX[0] bit 1	INT: mux HEX_V0_MUX[0] bit 0	INT: buffer HEX_V0[0] ← HEX_V0_MUX[0]	-	-	-	-	-	-

Tile CNR_SW_S2

Cells: 1

Switchbox INT

virtex CNR_SW_S2 switchbox INT programmable buffers
Destination	Source	Bit
HEX_H0[0]	HEX_H0_MUX[0]	MAIN[35][8]
HEX_H0[1]	HEX_H0_MUX[1]	MAIN[30][8]
HEX_H0[2]	HEX_H0_MUX[2]	MAIN[17][8]
HEX_H0[3]	PCI_CE	MAIN[7][0]
HEX_H0[3]	HEX_H0_MUX[3]	MAIN[12][8]
HEX_H0[4]	HEX_H0_MUX[4]	MAIN[14][9]
HEX_H0[5]	HEX_H0_MUX[5]	MAIN[12][9]
HEX_H1[0]	HEX_H1_MUX[0]	MAIN[41][8]
HEX_H1[1]	HEX_H1_MUX[1]	MAIN[36][8]
HEX_H1[2]	HEX_H1_MUX[2]	MAIN[23][8]
HEX_H1[3]	HEX_H1_MUX[3]	MAIN[18][8]
HEX_H1[4]	HEX_H1_MUX[4]	MAIN[17][9]
HEX_H1[5]	HEX_H1_MUX[5]	MAIN[15][9]
HEX_H2[0]	HEX_H2_MUX[0]	MAIN[47][8]
HEX_H2[1]	HEX_H2_MUX[1]	MAIN[42][8]
HEX_H2[2]	HEX_H2_MUX[2]	MAIN[29][8]
HEX_H2[3]	HEX_H2_MUX[3]	MAIN[24][8]
HEX_H2[4]	HEX_H2_MUX[4]	MAIN[20][9]
HEX_H2[5]	HEX_H2_MUX[5]	MAIN[18][9]
HEX_H3[0]	HEX_H3_MUX[0]	MAIN[35][4]
HEX_H3[1]	HEX_H3_MUX[1]	MAIN[30][4]
HEX_H3[2]	HEX_H3_MUX[2]	MAIN[17][4]
HEX_H3[3]	HEX_H3_MUX[3]	MAIN[12][4]
HEX_H3[4]	HEX_H3_MUX[4]	MAIN[23][9]
HEX_H3[5]	HEX_H3_MUX[5]	MAIN[21][9]
HEX_H4[0]	HEX_H4_MUX[0]	MAIN[41][4]
HEX_H4[1]	HEX_H4_MUX[1]	MAIN[36][4]
HEX_H4[2]	HEX_H4_MUX[2]	MAIN[23][4]
HEX_H4[3]	HEX_H4_MUX[3]	MAIN[18][4]
HEX_H4[4]	HEX_H4_MUX[4]	MAIN[34][9]
HEX_H4[5]	HEX_H4_MUX[5]	MAIN[24][9]
HEX_H5[0]	HEX_H5_MUX[0]	MAIN[47][4]
HEX_H5[1]	HEX_H5_MUX[1]	MAIN[42][4]
HEX_H5[2]	HEX_H5_MUX[2]	MAIN[29][4]
HEX_H5[3]	HEX_H5_MUX[3]	MAIN[24][4]
HEX_H5[4]	HEX_H5_MUX[4]	MAIN[29][9]
HEX_H5[5]	HEX_H5_MUX[5]	MAIN[27][9]
HEX_V0[0]	HEX_V0_MUX[0]	MAIN[47][0]
HEX_V0[1]	HEX_V0_MUX[1]	MAIN[42][0]
HEX_V0[2]	HEX_V0_MUX[2]	MAIN[29][0]
HEX_V0[3]	HEX_V0_MUX[3]	MAIN[24][0]
HEX_V1[0]	HEX_V1_MUX[0]	MAIN[41][0]
HEX_V1[1]	HEX_V1_MUX[1]	MAIN[36][0]
HEX_V1[2]	HEX_V1_MUX[2]	MAIN[23][0]
HEX_V1[3]	HEX_V1_MUX[3]	MAIN[18][0]
HEX_V2[0]	HEX_V2_MUX[0]	MAIN[35][0]
HEX_V2[1]	HEX_V2_MUX[1]	MAIN[30][0]
HEX_V2[2]	HEX_V2_MUX[2]	MAIN[17][0]
HEX_V2[3]	HEX_V2_MUX[3]	MAIN[12][0]
HEX_V3[0]	HEX_V3_MUX[0]	MAIN[47][2]
HEX_V3[1]	HEX_V3_MUX[1]	MAIN[42][2]
HEX_V3[2]	HEX_V3_MUX[2]	MAIN[29][2]
HEX_V3[3]	HEX_V3_MUX[3]	MAIN[24][2]
HEX_V4[0]	HEX_V4_MUX[0]	MAIN[41][2]
HEX_V4[1]	HEX_V4_MUX[1]	MAIN[36][2]
HEX_V4[2]	HEX_V4_MUX[2]	MAIN[23][2]
HEX_V4[3]	HEX_V4_MUX[3]	MAIN[18][2]
HEX_V5[0]	HEX_V5_MUX[0]	MAIN[35][2]
HEX_V5[1]	HEX_V5_MUX[1]	MAIN[30][2]
HEX_V5[2]	HEX_V5_MUX[2]	MAIN[17][2]
HEX_V5[3]	HEX_V5_MUX[3]	MAIN[12][2]
LV[0]	HEX_H0[5]	MAIN[47][9]
LV[1]	HEX_H5[5]	MAIN[46][9]
LV[2]	HEX_H4[5]	MAIN[45][9]
LV[3]	HEX_H3[5]	MAIN[44][9]
LV[4]	HEX_H2[5]	MAIN[43][9]
LV[5]	HEX_H1[5]	MAIN[42][9]
LV[6]	HEX_H0[4]	MAIN[41][9]
LV[7]	HEX_H5[4]	MAIN[40][9]
LV[8]	HEX_H4[4]	MAIN[39][9]
LV[9]	HEX_H3[4]	MAIN[38][9]
LV[10]	HEX_H2[4]	MAIN[37][9]
LV[11]	HEX_H1[4]	MAIN[36][9]

virtex CNR_SW_S2 switchbox INT muxes HEX_H0_MUX[0]
Bits		Destination
MAIN[33][8]	MAIN[34][8]	HEX_H0_MUX[0]
		Source
0	1	HEX_V5[0]
1	0	off
1	1	LH[0]

virtex CNR_SW_S2 switchbox INT muxes HEX_H0_MUX[1]
Bits		Destination
MAIN[32][8]	MAIN[31][8]	HEX_H0_MUX[1]
		Source
0	1	HEX_V5[1]
1	0	off
1	1	LH[0]

virtex CNR_SW_S2 switchbox INT muxes HEX_H0_MUX[2]
Bits		Destination
MAIN[15][8]	MAIN[16][8]	HEX_H0_MUX[2]
		Source
0	1	HEX_V5[2]
1	0	off
1	1	LH[6]

virtex CNR_SW_S2 switchbox INT muxes HEX_H0_MUX[3]
Bits		Destination
MAIN[14][8]	MAIN[13][8]	HEX_H0_MUX[3]
		Source
0	1	HEX_V5[3]
1	0	off
1	1	LH[6]

virtex CNR_SW_S2 switchbox INT muxes HEX_H0_MUX[4]
Bits	Destination
MAIN[30][9]	HEX_H0_MUX[4]
	Source
0	LH[0]
1	LH[6]

virtex CNR_SW_S2 switchbox INT muxes HEX_H0_MUX[5]
Bits	Destination
MAIN[13][9]	HEX_H0_MUX[5]
	Source
0	LH[0]
1	LH[6]

virtex CNR_SW_S2 switchbox INT muxes HEX_H1_MUX[0]
Bits		Destination
MAIN[39][8]	MAIN[40][8]	HEX_H1_MUX[0]
		Source
0	1	HEX_V4[0]
1	0	off
1	1	LH[11]

virtex CNR_SW_S2 switchbox INT muxes HEX_H1_MUX[1]
Bits		Destination
MAIN[38][8]	MAIN[37][8]	HEX_H1_MUX[1]
		Source
0	1	HEX_V4[1]
1	0	off
1	1	LH[11]

virtex CNR_SW_S2 switchbox INT muxes HEX_H1_MUX[2]
Bits		Destination
MAIN[21][8]	MAIN[22][8]	HEX_H1_MUX[2]
		Source
0	1	HEX_V4[2]
1	0	off
1	1	LH[5]

virtex CNR_SW_S2 switchbox INT muxes HEX_H1_MUX[3]
Bits		Destination
MAIN[20][8]	MAIN[19][8]	HEX_H1_MUX[3]
		Source
0	1	HEX_V4[3]
1	0	off
1	1	LH[5]

virtex CNR_SW_S2 switchbox INT muxes HEX_H1_MUX[4]
Bits	Destination
MAIN[16][9]	HEX_H1_MUX[4]
	Source
0	LH[11]
1	LH[5]

virtex CNR_SW_S2 switchbox INT muxes HEX_H1_MUX[5]
Bits	Destination
MAIN[31][9]	HEX_H1_MUX[5]
	Source
0	LH[11]
1	LH[5]

virtex CNR_SW_S2 switchbox INT muxes HEX_H2_MUX[0]
Bits		Destination
MAIN[45][8]	MAIN[46][8]	HEX_H2_MUX[0]
		Source
0	1	HEX_V3[0]
1	0	off
1	1	LH[10]

virtex CNR_SW_S2 switchbox INT muxes HEX_H2_MUX[1]
Bits		Destination
MAIN[44][8]	MAIN[43][8]	HEX_H2_MUX[1]
		Source
0	1	HEX_V3[1]
1	0	off
1	1	LH[10]

virtex CNR_SW_S2 switchbox INT muxes HEX_H2_MUX[2]
Bits		Destination
MAIN[27][8]	MAIN[28][8]	HEX_H2_MUX[2]
		Source
0	1	HEX_V3[2]
1	0	off
1	1	LH[4]

virtex CNR_SW_S2 switchbox INT muxes HEX_H2_MUX[3]
Bits		Destination
MAIN[26][8]	MAIN[25][8]	HEX_H2_MUX[3]
		Source
0	1	HEX_V3[3]
1	0	off
1	1	LH[4]

virtex CNR_SW_S2 switchbox INT muxes HEX_H2_MUX[4]
Bits	Destination
MAIN[32][9]	HEX_H2_MUX[4]
	Source
0	LH[10]
1	LH[4]

virtex CNR_SW_S2 switchbox INT muxes HEX_H2_MUX[5]
Bits	Destination
MAIN[19][9]	HEX_H2_MUX[5]
	Source
0	LH[10]
1	LH[4]

virtex CNR_SW_S2 switchbox INT muxes HEX_H3_MUX[0]
Bits		Destination
MAIN[33][4]	MAIN[34][4]	HEX_H3_MUX[0]
		Source
0	1	HEX_V2[0]
1	0	off
1	1	LH[9]

virtex CNR_SW_S2 switchbox INT muxes HEX_H3_MUX[1]
Bits		Destination
MAIN[32][4]	MAIN[31][4]	HEX_H3_MUX[1]
		Source
0	1	HEX_V2[1]
1	0	off
1	1	LH[9]

virtex CNR_SW_S2 switchbox INT muxes HEX_H3_MUX[2]
Bits		Destination
MAIN[15][4]	MAIN[16][4]	HEX_H3_MUX[2]
		Source
0	1	HEX_V2[2]
1	0	off
1	1	LH[3]

virtex CNR_SW_S2 switchbox INT muxes HEX_H3_MUX[3]
Bits		Destination
MAIN[14][4]	MAIN[13][4]	HEX_H3_MUX[3]
		Source
0	1	HEX_V2[3]
1	0	off
1	1	LH[3]

virtex CNR_SW_S2 switchbox INT muxes HEX_H3_MUX[4]
Bits	Destination
MAIN[33][9]	HEX_H3_MUX[4]
	Source
0	LH[9]
1	LH[3]

virtex CNR_SW_S2 switchbox INT muxes HEX_H3_MUX[5]
Bits	Destination
MAIN[22][9]	HEX_H3_MUX[5]
	Source
0	LH[9]
1	LH[3]

virtex CNR_SW_S2 switchbox INT muxes HEX_H4_MUX[0]
Bits		Destination
MAIN[39][4]	MAIN[40][4]	HEX_H4_MUX[0]
		Source
0	1	HEX_V1[0]
1	0	off
1	1	LH[8]

virtex CNR_SW_S2 switchbox INT muxes HEX_H4_MUX[1]
Bits		Destination
MAIN[38][4]	MAIN[37][4]	HEX_H4_MUX[1]
		Source
0	1	HEX_V1[1]
1	0	off
1	1	LH[8]

virtex CNR_SW_S2 switchbox INT muxes HEX_H4_MUX[2]
Bits		Destination
MAIN[21][4]	MAIN[22][4]	HEX_H4_MUX[2]
		Source
0	1	HEX_V1[2]
1	0	off
1	1	LH[2]

virtex CNR_SW_S2 switchbox INT muxes HEX_H4_MUX[3]
Bits		Destination
MAIN[20][4]	MAIN[19][4]	HEX_H4_MUX[3]
		Source
0	1	HEX_V1[3]
1	0	off
1	1	LH[2]

virtex CNR_SW_S2 switchbox INT muxes HEX_H4_MUX[4]
Bits	Destination
MAIN[26][9]	HEX_H4_MUX[4]
	Source
0	LH[8]
1	LH[2]

virtex CNR_SW_S2 switchbox INT muxes HEX_H4_MUX[5]
Bits	Destination
MAIN[25][9]	HEX_H4_MUX[5]
	Source
0	LH[8]
1	LH[2]

virtex CNR_SW_S2 switchbox INT muxes HEX_H5_MUX[0]
Bits		Destination
MAIN[45][4]	MAIN[46][4]	HEX_H5_MUX[0]
		Source
0	1	HEX_V0[0]
1	0	off
1	1	LH[7]

virtex CNR_SW_S2 switchbox INT muxes HEX_H5_MUX[1]
Bits		Destination
MAIN[44][4]	MAIN[43][4]	HEX_H5_MUX[1]
		Source
0	1	HEX_V0[1]
1	0	off
1	1	LH[7]

virtex CNR_SW_S2 switchbox INT muxes HEX_H5_MUX[2]
Bits		Destination
MAIN[27][4]	MAIN[28][4]	HEX_H5_MUX[2]
		Source
0	1	HEX_V0[2]
1	0	off
1	1	LH[1]

virtex CNR_SW_S2 switchbox INT muxes HEX_H5_MUX[3]
Bits		Destination
MAIN[26][4]	MAIN[25][4]	HEX_H5_MUX[3]
		Source
0	1	HEX_V0[3]
1	0	off
1	1	LH[1]

virtex CNR_SW_S2 switchbox INT muxes HEX_H5_MUX[4]
Bits	Destination
MAIN[35][9]	HEX_H5_MUX[4]
	Source
0	LH[7]
1	LH[1]

virtex CNR_SW_S2 switchbox INT muxes HEX_H5_MUX[5]
Bits	Destination
MAIN[28][9]	HEX_H5_MUX[5]
	Source
0	LH[7]
1	LH[1]

virtex CNR_SW_S2 switchbox INT muxes HEX_V0_MUX[0]
Bits		Destination
MAIN[45][0]	MAIN[46][0]	HEX_V0_MUX[0]
		Source
0	1	HEX_H5[0]
1	0	off
1	1	LV[0]

virtex CNR_SW_S2 switchbox INT muxes HEX_V0_MUX[1]
Bits		Destination
MAIN[44][0]	MAIN[43][0]	HEX_V0_MUX[1]
		Source
0	1	HEX_H5[1]
1	0	off
1	1	LV[0]

virtex CNR_SW_S2 switchbox INT muxes HEX_V0_MUX[2]
Bits		Destination
MAIN[27][0]	MAIN[28][0]	HEX_V0_MUX[2]
		Source
0	1	HEX_H5[2]
1	0	off
1	1	LV[6]

virtex CNR_SW_S2 switchbox INT muxes HEX_V0_MUX[3]
Bits		Destination
MAIN[26][0]	MAIN[25][0]	HEX_V0_MUX[3]
		Source
0	1	HEX_H5[3]
1	0	off
1	1	LV[6]

virtex CNR_SW_S2 switchbox INT muxes HEX_V1_MUX[0]
Bits		Destination
MAIN[39][0]	MAIN[40][0]	HEX_V1_MUX[0]
		Source
0	1	HEX_H4[0]
1	0	off
1	1	LV[11]

virtex CNR_SW_S2 switchbox INT muxes HEX_V1_MUX[1]
Bits		Destination
MAIN[38][0]	MAIN[37][0]	HEX_V1_MUX[1]
		Source
0	1	HEX_H4[1]
1	0	off
1	1	LV[11]

virtex CNR_SW_S2 switchbox INT muxes HEX_V1_MUX[2]
Bits		Destination
MAIN[21][0]	MAIN[22][0]	HEX_V1_MUX[2]
		Source
0	1	HEX_H4[2]
1	0	off
1	1	LV[5]

virtex CNR_SW_S2 switchbox INT muxes HEX_V1_MUX[3]
Bits		Destination
MAIN[20][0]	MAIN[19][0]	HEX_V1_MUX[3]
		Source
0	1	HEX_H4[3]
1	0	off
1	1	LV[5]

virtex CNR_SW_S2 switchbox INT muxes HEX_V2_MUX[0]
Bits		Destination
MAIN[33][0]	MAIN[34][0]	HEX_V2_MUX[0]
		Source
0	1	HEX_H3[0]
1	0	off
1	1	LV[10]

virtex CNR_SW_S2 switchbox INT muxes HEX_V2_MUX[1]
Bits		Destination
MAIN[32][0]	MAIN[31][0]	HEX_V2_MUX[1]
		Source
0	1	HEX_H3[1]
1	0	off
1	1	LV[10]

virtex CNR_SW_S2 switchbox INT muxes HEX_V2_MUX[2]
Bits		Destination
MAIN[15][0]	MAIN[16][0]	HEX_V2_MUX[2]
		Source
0	1	HEX_H3[2]
1	0	off
1	1	LV[4]

virtex CNR_SW_S2 switchbox INT muxes HEX_V2_MUX[3]
Bits		Destination
MAIN[14][0]	MAIN[13][0]	HEX_V2_MUX[3]
		Source
0	1	HEX_H3[3]
1	0	off
1	1	LV[4]

virtex CNR_SW_S2 switchbox INT muxes HEX_V3_MUX[0]
Bits		Destination
MAIN[45][2]	MAIN[46][2]	HEX_V3_MUX[0]
		Source
0	1	HEX_H2[0]
1	0	off
1	1	LV[9]

virtex CNR_SW_S2 switchbox INT muxes HEX_V3_MUX[1]
Bits		Destination
MAIN[44][2]	MAIN[43][2]	HEX_V3_MUX[1]
		Source
0	1	HEX_H2[1]
1	0	off
1	1	LV[9]

virtex CNR_SW_S2 switchbox INT muxes HEX_V3_MUX[2]
Bits		Destination
MAIN[27][2]	MAIN[28][2]	HEX_V3_MUX[2]
		Source
0	1	HEX_H2[2]
1	0	off
1	1	LV[3]

virtex CNR_SW_S2 switchbox INT muxes HEX_V3_MUX[3]
Bits		Destination
MAIN[26][2]	MAIN[25][2]	HEX_V3_MUX[3]
		Source
0	1	HEX_H2[3]
1	0	off
1	1	LV[3]

virtex CNR_SW_S2 switchbox INT muxes HEX_V4_MUX[0]
Bits		Destination
MAIN[39][2]	MAIN[40][2]	HEX_V4_MUX[0]
		Source
0	1	HEX_H1[0]
1	0	off
1	1	LV[8]

virtex CNR_SW_S2 switchbox INT muxes HEX_V4_MUX[1]
Bits		Destination
MAIN[38][2]	MAIN[37][2]	HEX_V4_MUX[1]
		Source
0	1	HEX_H1[1]
1	0	off
1	1	LV[8]

virtex CNR_SW_S2 switchbox INT muxes HEX_V4_MUX[2]
Bits		Destination
MAIN[21][2]	MAIN[22][2]	HEX_V4_MUX[2]
		Source
0	1	HEX_H1[2]
1	0	off
1	1	LV[2]

virtex CNR_SW_S2 switchbox INT muxes HEX_V4_MUX[3]
Bits		Destination
MAIN[20][2]	MAIN[19][2]	HEX_V4_MUX[3]
		Source
0	1	HEX_H1[3]
1	0	off
1	1	LV[2]

virtex CNR_SW_S2 switchbox INT muxes HEX_V5_MUX[0]
Bits		Destination
MAIN[33][2]	MAIN[34][2]	HEX_V5_MUX[0]
		Source
0	1	HEX_H0[0]
1	0	off
1	1	LV[7]

virtex CNR_SW_S2 switchbox INT muxes HEX_V5_MUX[1]
Bits		Destination
MAIN[32][2]	MAIN[31][2]	HEX_V5_MUX[1]
		Source
0	1	HEX_H0[1]
1	0	off
1	1	LV[7]

virtex CNR_SW_S2 switchbox INT muxes HEX_V5_MUX[2]
Bits		Destination
MAIN[15][2]	MAIN[16][2]	HEX_V5_MUX[2]
		Source
0	1	HEX_H0[2]
1	0	off
1	1	LV[1]

virtex CNR_SW_S2 switchbox INT muxes HEX_V5_MUX[3]
Bits		Destination
MAIN[14][2]	MAIN[13][2]	HEX_V5_MUX[3]
		Source
0	1	HEX_H0[3]
1	0	off
1	1	LV[1]

virtex CNR_SW_S2 switchbox INT muxes IMUX_CAP_CLK
Bits										Destination
MAIN[17][13]	MAIN[15][13]	MAIN[9][13]	MAIN[8][13]	MAIN[16][13]	MAIN[10][13]	MAIN[11][13]	MAIN[14][13]	MAIN[13][13]	MAIN[12][13]	IMUX_CAP_CLK
										Source
0	0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	0	0	1	0	GCLK_LEAF[0]
0	0	0	0	0	0	0	1	0	0	GCLK_LEAF[1]
0	0	0	0	0	0	1	0	0	0	GCLK_LEAF[2]
0	0	0	0	0	1	0	0	0	0	GCLK_LEAF[3]
0	0	0	1	1	0	0	0	1	1	HEX_H1[0]
0	0	0	1	1	0	0	1	0	1	HEX_H0[0]
0	0	0	1	1	0	1	0	0	1	HEX_H5[1]
0	0	0	1	1	1	0	0	0	1	HEX_H4[1]
0	0	1	0	1	0	0	0	1	1	HEX_H3[1]
0	0	1	0	1	0	0	1	0	1	HEX_H2[1]
0	0	1	0	1	0	1	0	0	1	HEX_H1[1]
0	0	1	0	1	1	0	0	0	1	HEX_H0[1]
0	1	0	0	1	0	0	0	1	1	HEX_H5[0]
0	1	0	0	1	0	0	1	0	1	HEX_H4[0]
0	1	0	0	1	0	1	0	0	1	HEX_H3[0]
0	1	0	0	1	1	0	0	0	1	HEX_H2[0]
1	0	0	1	0	0	0	0	1	1	HEX_V1[2]
1	0	0	1	0	0	0	1	0	1	HEX_V0[2]
1	0	0	1	0	0	1	0	0	1	HEX_V5[3]
1	0	0	1	0	1	0	0	0	1	HEX_V4[3]
1	0	1	0	0	0	0	0	1	1	HEX_V3[3]
1	0	1	0	0	0	0	1	0	1	HEX_V2[3]
1	0	1	0	0	0	1	0	0	1	HEX_V1[3]
1	0	1	0	0	1	0	0	0	1	HEX_V0[3]
1	1	0	0	0	0	0	0	1	1	HEX_V5[2]
1	1	0	0	0	0	0	1	0	1	HEX_V4[2]
1	1	0	0	0	0	1	0	0	1	HEX_V3[2]
1	1	0	0	0	1	0	0	0	1	HEX_V2[2]

virtex CNR_SW_S2 switchbox INT muxes IMUX_CAP_CAP
Bits								Destination
MAIN[37][13]	MAIN[36][13]	MAIN[31][13]	MAIN[30][13]	MAIN[33][13]	MAIN[34][13]	MAIN[32][13]	MAIN[35][13]	IMUX_CAP_CAP
								Source
0	0	0	0	0	0	0	0	PULLUP
0	0	0	1	0	0	0	1	HEX_V0[0]
0	0	0	1	0	0	1	0	HEX_V4[1]
0	0	0	1	0	1	0	0	HEX_V1[0]
0	0	0	1	1	0	0	0	HEX_V5[1]
0	0	1	0	0	0	0	1	HEX_V2[1]
0	0	1	0	0	0	1	0	HEX_V0[1]
0	0	1	0	0	1	0	0	HEX_V3[1]
0	0	1	0	1	0	0	0	HEX_V1[1]
0	1	0	0	0	0	0	1	HEX_V4[0]
0	1	0	0	0	0	1	0	HEX_V2[0]
0	1	0	0	0	1	0	0	HEX_V5[0]
0	1	0	0	1	0	0	0	HEX_V3[0]
1	0	0	1	0	0	0	1	HEX_H0[2]
1	0	0	1	0	0	1	0	HEX_H4[3]
1	0	0	1	0	1	0	0	HEX_H1[2]
1	0	0	1	1	0	0	0	HEX_H5[3]
1	0	1	0	0	0	0	1	HEX_H2[3]
1	0	1	0	0	0	1	0	HEX_H0[3]
1	0	1	0	0	1	0	0	HEX_H3[3]
1	0	1	0	1	0	0	0	HEX_H1[3]
1	1	0	0	0	0	0	1	HEX_H4[2]
1	1	0	0	0	0	1	0	HEX_H2[2]
1	1	0	0	0	1	0	0	HEX_H5[2]
1	1	0	0	1	0	0	0	HEX_H3[2]

Bels CAPTURE

virtex CNR_SW_S2 bel CAPTURE pins
Pin	Direction	CAPTURE
CLK	in	IMUX_CAP_CLK invert by !MAIN[18][13]
CAP	in	IMUX_CAP_CAP invert by !MAIN[38][13]

Bels MISC_SW

virtex CNR_SW_S2 bel MISC_SW pins
Pin	Direction	MISC_SW

virtex CNR_SW_S2 bel MISC_SW attribute bits
Attribute	MISC_SW
M0_PULL	[enum: IOB_PULL]
M1_PULL	[enum: IOB_PULL]
M2_PULL	[enum: IOB_PULL]
POWERDOWN_PULL	[enum: IOB_PULL]
PDSTATUS_PULL	[enum: IOB_PULL]
DRIVE_PD_STATUS	!MAIN[7][8]
POWERUP_DELAY	[enum: POWERUP_DELAY]

virtex CNR_SW_S2 enum IOB_PULL
MISC_SW.M0_PULL	MAIN[9][8]	MAIN[9][9]
MISC_SW.M1_PULL	MAIN[11][8]	MAIN[10][8]
MISC_SW.M2_PULL	MAIN[10][9]	MAIN[11][9]
NONE	0	1
PULLUP	1	1
PULLDOWN	0	0

virtex CNR_SW_S2 enum IOB_PULL
MISC_SW.POWERDOWN_PULL	MAIN[8][8]
MISC_SW.PDSTATUS_PULL	MAIN[8][9]
NONE	0
PULLUP	1

virtex CNR_SW_S2 enum POWERUP_DELAY
MISC_SW.POWERUP_DELAY	MAIN[5][0]	MAIN[6][0]
_100US	0	0
_200US	0	1
_400US	1	0

Bel wires

virtex CNR_SW_S2 bel wires
Wire	Pins
IMUX_CAP_CLK	CAPTURE.CLK
IMUX_CAP_CAP	CAPTURE.CAP

Bitstream

virtex CNR_SW_S2 rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	INT: mux IMUX_CAP_CLK bit 6	INT: mux IMUX_CAP_CLK bit 7	INT: mux IMUX_CAP_CLK bit 4	INT: mux IMUX_CAP_CLK bit 3	INT: mux IMUX_CAP_CLK bit 0	INT: mux IMUX_CAP_CLK bit 1	INT: mux IMUX_CAP_CLK bit 2	INT: mux IMUX_CAP_CLK bit 8	INT: mux IMUX_CAP_CLK bit 5	INT: mux IMUX_CAP_CLK bit 9	CAPTURE: !invert CLK	-	-	-	-	-	-	-	-	-	-	-	INT: mux IMUX_CAP_CAP bit 4	INT: mux IMUX_CAP_CAP bit 5	INT: mux IMUX_CAP_CAP bit 1	INT: mux IMUX_CAP_CAP bit 3	INT: mux IMUX_CAP_CAP bit 2	INT: mux IMUX_CAP_CAP bit 0	INT: mux IMUX_CAP_CAP bit 6	INT: mux IMUX_CAP_CAP bit 7	CAPTURE: !invert CAP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	MISC_SW: PDSTATUS_PULL bit 0	MISC_SW: M0_PULL bit 0	MISC_SW: M2_PULL bit 1	MISC_SW: M2_PULL bit 0	INT: buffer HEX_H0[5] ← HEX_H0_MUX[5]	INT: mux HEX_H0_MUX[5] bit 0	INT: buffer HEX_H0[4] ← HEX_H0_MUX[4]	INT: buffer HEX_H1[5] ← HEX_H1_MUX[5]	INT: mux HEX_H1_MUX[4] bit 0	INT: buffer HEX_H1[4] ← HEX_H1_MUX[4]	INT: buffer HEX_H2[5] ← HEX_H2_MUX[5]	INT: mux HEX_H2_MUX[5] bit 0	INT: buffer HEX_H2[4] ← HEX_H2_MUX[4]	INT: buffer HEX_H3[5] ← HEX_H3_MUX[5]	INT: mux HEX_H3_MUX[5] bit 0	INT: buffer HEX_H3[4] ← HEX_H3_MUX[4]	INT: buffer HEX_H4[5] ← HEX_H4_MUX[5]	INT: mux HEX_H4_MUX[5] bit 0	INT: mux HEX_H4_MUX[4] bit 0	INT: buffer HEX_H5[5] ← HEX_H5_MUX[5]	INT: mux HEX_H5_MUX[5] bit 0	INT: buffer HEX_H5[4] ← HEX_H5_MUX[4]	INT: mux HEX_H0_MUX[4] bit 0	INT: mux HEX_H1_MUX[5] bit 0	INT: mux HEX_H2_MUX[4] bit 0	INT: mux HEX_H3_MUX[4] bit 0	INT: buffer HEX_H4[4] ← HEX_H4_MUX[4]	INT: mux HEX_H5_MUX[4] bit 0	INT: buffer LV[11] ← HEX_H1[4]	INT: buffer LV[10] ← HEX_H2[4]	INT: buffer LV[9] ← HEX_H3[4]	INT: buffer LV[8] ← HEX_H4[4]	INT: buffer LV[7] ← HEX_H5[4]	INT: buffer LV[6] ← HEX_H0[4]	INT: buffer LV[5] ← HEX_H1[5]	INT: buffer LV[4] ← HEX_H2[5]	INT: buffer LV[3] ← HEX_H3[5]	INT: buffer LV[2] ← HEX_H4[5]	INT: buffer LV[1] ← HEX_H5[5]	INT: buffer LV[0] ← HEX_H0[5]	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	MISC_SW: ! DRIVE_PD_STATUS	MISC_SW: POWERDOWN_PULL bit 0	MISC_SW: M0_PULL bit 1	MISC_SW: M1_PULL bit 0	MISC_SW: M1_PULL bit 1	INT: buffer HEX_H0[3] ← HEX_H0_MUX[3]	INT: mux HEX_H0_MUX[3] bit 0	INT: mux HEX_H0_MUX[3] bit 1	INT: mux HEX_H0_MUX[2] bit 1	INT: mux HEX_H0_MUX[2] bit 0	INT: buffer HEX_H0[2] ← HEX_H0_MUX[2]	INT: buffer HEX_H1[3] ← HEX_H1_MUX[3]	INT: mux HEX_H1_MUX[3] bit 0	INT: mux HEX_H1_MUX[3] bit 1	INT: mux HEX_H1_MUX[2] bit 1	INT: mux HEX_H1_MUX[2] bit 0	INT: buffer HEX_H1[2] ← HEX_H1_MUX[2]	INT: buffer HEX_H2[3] ← HEX_H2_MUX[3]	INT: mux HEX_H2_MUX[3] bit 0	INT: mux HEX_H2_MUX[3] bit 1	INT: mux HEX_H2_MUX[2] bit 1	INT: mux HEX_H2_MUX[2] bit 0	INT: buffer HEX_H2[2] ← HEX_H2_MUX[2]	INT: buffer HEX_H0[1] ← HEX_H0_MUX[1]	INT: mux HEX_H0_MUX[1] bit 0	INT: mux HEX_H0_MUX[1] bit 1	INT: mux HEX_H0_MUX[0] bit 1	INT: mux HEX_H0_MUX[0] bit 0	INT: buffer HEX_H0[0] ← HEX_H0_MUX[0]	INT: buffer HEX_H1[1] ← HEX_H1_MUX[1]	INT: mux HEX_H1_MUX[1] bit 0	INT: mux HEX_H1_MUX[1] bit 1	INT: mux HEX_H1_MUX[0] bit 1	INT: mux HEX_H1_MUX[0] bit 0	INT: buffer HEX_H1[0] ← HEX_H1_MUX[0]	INT: buffer HEX_H2[1] ← HEX_H2_MUX[1]	INT: mux HEX_H2_MUX[1] bit 0	INT: mux HEX_H2_MUX[1] bit 1	INT: mux HEX_H2_MUX[0] bit 1	INT: mux HEX_H2_MUX[0] bit 0	INT: buffer HEX_H2[0] ← HEX_H2_MUX[0]	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	INT: buffer HEX_H3[3] ← HEX_H3_MUX[3]	INT: mux HEX_H3_MUX[3] bit 0	INT: mux HEX_H3_MUX[3] bit 1	INT: mux HEX_H3_MUX[2] bit 1	INT: mux HEX_H3_MUX[2] bit 0	INT: buffer HEX_H3[2] ← HEX_H3_MUX[2]	INT: buffer HEX_H4[3] ← HEX_H4_MUX[3]	INT: mux HEX_H4_MUX[3] bit 0	INT: mux HEX_H4_MUX[3] bit 1	INT: mux HEX_H4_MUX[2] bit 1	INT: mux HEX_H4_MUX[2] bit 0	INT: buffer HEX_H4[2] ← HEX_H4_MUX[2]	INT: buffer HEX_H5[3] ← HEX_H5_MUX[3]	INT: mux HEX_H5_MUX[3] bit 0	INT: mux HEX_H5_MUX[3] bit 1	INT: mux HEX_H5_MUX[2] bit 1	INT: mux HEX_H5_MUX[2] bit 0	INT: buffer HEX_H5[2] ← HEX_H5_MUX[2]	INT: buffer HEX_H3[1] ← HEX_H3_MUX[1]	INT: mux HEX_H3_MUX[1] bit 0	INT: mux HEX_H3_MUX[1] bit 1	INT: mux HEX_H3_MUX[0] bit 1	INT: mux HEX_H3_MUX[0] bit 0	INT: buffer HEX_H3[0] ← HEX_H3_MUX[0]	INT: buffer HEX_H4[1] ← HEX_H4_MUX[1]	INT: mux HEX_H4_MUX[1] bit 0	INT: mux HEX_H4_MUX[1] bit 1	INT: mux HEX_H4_MUX[0] bit 1	INT: mux HEX_H4_MUX[0] bit 0	INT: buffer HEX_H4[0] ← HEX_H4_MUX[0]	INT: buffer HEX_H5[1] ← HEX_H5_MUX[1]	INT: mux HEX_H5_MUX[1] bit 0	INT: mux HEX_H5_MUX[1] bit 1	INT: mux HEX_H5_MUX[0] bit 1	INT: mux HEX_H5_MUX[0] bit 0	INT: buffer HEX_H5[0] ← HEX_H5_MUX[0]	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	INT: buffer HEX_V5[3] ← HEX_V5_MUX[3]	INT: mux HEX_V5_MUX[3] bit 0	INT: mux HEX_V5_MUX[3] bit 1	INT: mux HEX_V5_MUX[2] bit 1	INT: mux HEX_V5_MUX[2] bit 0	INT: buffer HEX_V5[2] ← HEX_V5_MUX[2]	INT: buffer HEX_V4[3] ← HEX_V4_MUX[3]	INT: mux HEX_V4_MUX[3] bit 0	INT: mux HEX_V4_MUX[3] bit 1	INT: mux HEX_V4_MUX[2] bit 1	INT: mux HEX_V4_MUX[2] bit 0	INT: buffer HEX_V4[2] ← HEX_V4_MUX[2]	INT: buffer HEX_V3[3] ← HEX_V3_MUX[3]	INT: mux HEX_V3_MUX[3] bit 0	INT: mux HEX_V3_MUX[3] bit 1	INT: mux HEX_V3_MUX[2] bit 1	INT: mux HEX_V3_MUX[2] bit 0	INT: buffer HEX_V3[2] ← HEX_V3_MUX[2]	INT: buffer HEX_V5[1] ← HEX_V5_MUX[1]	INT: mux HEX_V5_MUX[1] bit 0	INT: mux HEX_V5_MUX[1] bit 1	INT: mux HEX_V5_MUX[0] bit 1	INT: mux HEX_V5_MUX[0] bit 0	INT: buffer HEX_V5[0] ← HEX_V5_MUX[0]	INT: buffer HEX_V4[1] ← HEX_V4_MUX[1]	INT: mux HEX_V4_MUX[1] bit 0	INT: mux HEX_V4_MUX[1] bit 1	INT: mux HEX_V4_MUX[0] bit 1	INT: mux HEX_V4_MUX[0] bit 0	INT: buffer HEX_V4[0] ← HEX_V4_MUX[0]	INT: buffer HEX_V3[1] ← HEX_V3_MUX[1]	INT: mux HEX_V3_MUX[1] bit 0	INT: mux HEX_V3_MUX[1] bit 1	INT: mux HEX_V3_MUX[0] bit 1	INT: mux HEX_V3_MUX[0] bit 0	INT: buffer HEX_V3[0] ← HEX_V3_MUX[0]	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	MISC_SW: POWERUP_DELAY bit 1	MISC_SW: POWERUP_DELAY bit 0	INT: buffer HEX_H0[3] ← PCI_CE	-	-	-	-	INT: buffer HEX_V2[3] ← HEX_V2_MUX[3]	INT: mux HEX_V2_MUX[3] bit 0	INT: mux HEX_V2_MUX[3] bit 1	INT: mux HEX_V2_MUX[2] bit 1	INT: mux HEX_V2_MUX[2] bit 0	INT: buffer HEX_V2[2] ← HEX_V2_MUX[2]	INT: buffer HEX_V1[3] ← HEX_V1_MUX[3]	INT: mux HEX_V1_MUX[3] bit 0	INT: mux HEX_V1_MUX[3] bit 1	INT: mux HEX_V1_MUX[2] bit 1	INT: mux HEX_V1_MUX[2] bit 0	INT: buffer HEX_V1[2] ← HEX_V1_MUX[2]	INT: buffer HEX_V0[3] ← HEX_V0_MUX[3]	INT: mux HEX_V0_MUX[3] bit 0	INT: mux HEX_V0_MUX[3] bit 1	INT: mux HEX_V0_MUX[2] bit 1	INT: mux HEX_V0_MUX[2] bit 0	INT: buffer HEX_V0[2] ← HEX_V0_MUX[2]	INT: buffer HEX_V2[1] ← HEX_V2_MUX[1]	INT: mux HEX_V2_MUX[1] bit 0	INT: mux HEX_V2_MUX[1] bit 1	INT: mux HEX_V2_MUX[0] bit 1	INT: mux HEX_V2_MUX[0] bit 0	INT: buffer HEX_V2[0] ← HEX_V2_MUX[0]	INT: buffer HEX_V1[1] ← HEX_V1_MUX[1]	INT: mux HEX_V1_MUX[1] bit 0	INT: mux HEX_V1_MUX[1] bit 1	INT: mux HEX_V1_MUX[0] bit 1	INT: mux HEX_V1_MUX[0] bit 0	INT: buffer HEX_V1[0] ← HEX_V1_MUX[0]	INT: buffer HEX_V0[1] ← HEX_V0_MUX[1]	INT: mux HEX_V0_MUX[1] bit 0	INT: mux HEX_V0_MUX[1] bit 1	INT: mux HEX_V0_MUX[0] bit 1	INT: mux HEX_V0_MUX[0] bit 0	INT: buffer HEX_V0[0] ← HEX_V0_MUX[0]	-	-	-	-	-	-

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