I/O Interface

Tile IO_W

Cells: 1

Switchbox INT

virtex IO_W switchbox INT permanent buffers
Destination	Source
SINGLE_E_BUF[0]	SINGLE_E[0]
SINGLE_E_BUF[1]	SINGLE_E[1]
SINGLE_E_BUF[2]	SINGLE_E[2]
SINGLE_E_BUF[3]	SINGLE_E[3]
SINGLE_E_BUF[4]	SINGLE_E[4]
SINGLE_E_BUF[5]	SINGLE_E[5]
SINGLE_E_BUF[6]	SINGLE_E[6]
SINGLE_E_BUF[7]	SINGLE_E[7]
SINGLE_E_BUF[8]	SINGLE_E[8]
SINGLE_E_BUF[9]	SINGLE_E[9]
SINGLE_E_BUF[10]	SINGLE_E[10]
SINGLE_E_BUF[11]	SINGLE_E[11]
SINGLE_E_BUF[12]	SINGLE_E[12]
SINGLE_E_BUF[13]	SINGLE_E[13]
SINGLE_E_BUF[14]	SINGLE_E[14]
SINGLE_E_BUF[15]	SINGLE_E[15]
SINGLE_E_BUF[16]	SINGLE_E[16]
SINGLE_E_BUF[17]	SINGLE_E[17]
SINGLE_E_BUF[18]	SINGLE_E[18]
SINGLE_E_BUF[19]	SINGLE_E[19]
SINGLE_E_BUF[20]	SINGLE_E[20]
SINGLE_E_BUF[21]	SINGLE_E[21]
SINGLE_E_BUF[22]	SINGLE_E[22]
SINGLE_E_BUF[23]	SINGLE_E[23]
HEX_H0_BUF[0]	HEX_H0[0]
HEX_H0_BUF[1]	HEX_H0[1]
HEX_H0_BUF[2]	HEX_H0[2]
HEX_H0_BUF[3]	HEX_H0[3]
HEX_H1_BUF[0]	HEX_H1[0]
HEX_H1_BUF[1]	HEX_H1[1]
HEX_H1_BUF[2]	HEX_H1[2]
HEX_H1_BUF[3]	HEX_H1[3]
HEX_H2_BUF[0]	HEX_H2[0]
HEX_H2_BUF[1]	HEX_H2[1]
HEX_H2_BUF[2]	HEX_H2[2]
HEX_H2_BUF[3]	HEX_H2[3]
HEX_H3_BUF[0]	HEX_H3[0]
HEX_H3_BUF[1]	HEX_H3[1]
HEX_H3_BUF[2]	HEX_H3[2]
HEX_H3_BUF[3]	HEX_H3[3]
HEX_V1_BUF[0]	HEX_V1[0]
HEX_V1_BUF[1]	HEX_V1[1]
HEX_V1_BUF[2]	HEX_V1[2]
HEX_V1_BUF[3]	HEX_V1[3]
HEX_V2_BUF[0]	HEX_V2[0]
HEX_V2_BUF[1]	HEX_V2[1]
HEX_V2_BUF[2]	HEX_V2[2]
HEX_V2_BUF[3]	HEX_V2[3]
HEX_V3_BUF[0]	HEX_V3[0]
HEX_V3_BUF[1]	HEX_V3[1]
HEX_V3_BUF[2]	HEX_V3[2]
HEX_V3_BUF[3]	HEX_V3[3]
HEX_V4_BUF[0]	HEX_V4[0]
HEX_V4_BUF[1]	HEX_V4[1]
HEX_V4_BUF[2]	HEX_V4[2]
HEX_V4_BUF[3]	HEX_V4[3]
HEX_V5_BUF[0]	HEX_V5[0]
HEX_V5_BUF[1]	HEX_V5[1]
HEX_V5_BUF[2]	HEX_V5[2]
HEX_V5_BUF[3]	HEX_V5[3]
HEX_V6_BUF[0]	HEX_V6[0]
HEX_V6_BUF[1]	HEX_V6[1]
HEX_V6_BUF[2]	HEX_V6[2]
HEX_V6_BUF[3]	HEX_V6[3]

virtex IO_W switchbox INT pass gates
Destination	Source	Bit
SINGLE_E[0]	HEX_V6[0]	XXX57005[57005][57005]
SINGLE_E[0]	OUT_TBUF_W[3]	XXX57005[57005][57005]
SINGLE_E[0]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_E[1]	HEX_V3[0]	XXX57005[57005][57005]
SINGLE_E[1]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_E[2]	HEX_V0[0]	XXX57005[57005][57005]
SINGLE_E[2]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_E[3]	HEX_V6[0]	XXX57005[57005][57005]
SINGLE_E[3]	OUT_TBUF_W[3]	XXX57005[57005][57005]
SINGLE_E[3]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_E[4]	HEX_V3[0]	XXX57005[57005][57005]
SINGLE_E[4]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_E[5]	HEX_V0[0]	XXX57005[57005][57005]
SINGLE_E[5]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_E[6]	HEX_V6[1]	XXX57005[57005][57005]
SINGLE_E[6]	OUT_TBUF_W[2]	XXX57005[57005][57005]
SINGLE_E[6]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_E[7]	HEX_V3[1]	XXX57005[57005][57005]
SINGLE_E[7]	OUT_IO_IQ[0]	XXX57005[57005][57005]
SINGLE_E[8]	HEX_V0[1]	XXX57005[57005][57005]
SINGLE_E[8]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_E[9]	HEX_V6[1]	XXX57005[57005][57005]
SINGLE_E[9]	OUT_TBUF_W[2]	XXX57005[57005][57005]
SINGLE_E[9]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_E[10]	HEX_V3[1]	XXX57005[57005][57005]
SINGLE_E[10]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_E[11]	HEX_V0[1]	XXX57005[57005][57005]
SINGLE_E[11]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_E[12]	HEX_V6[2]	XXX57005[57005][57005]
SINGLE_E[12]	OUT_TBUF_W[1]	XXX57005[57005][57005]
SINGLE_E[12]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_E[13]	HEX_V3[2]	XXX57005[57005][57005]
SINGLE_E[13]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_E[14]	HEX_V0[2]	XXX57005[57005][57005]
SINGLE_E[14]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_E[15]	HEX_V6[2]	XXX57005[57005][57005]
SINGLE_E[15]	OUT_TBUF_W[1]	XXX57005[57005][57005]
SINGLE_E[15]	OUT_IO_IQ[0]	XXX57005[57005][57005]
SINGLE_E[16]	HEX_V3[2]	XXX57005[57005][57005]
SINGLE_E[16]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_E[17]	HEX_V0[2]	XXX57005[57005][57005]
SINGLE_E[17]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_E[18]	HEX_V6[3]	XXX57005[57005][57005]
SINGLE_E[18]	OUT_TBUF_W[0]	XXX57005[57005][57005]
SINGLE_E[18]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_E[19]	HEX_V3[3]	XXX57005[57005][57005]
SINGLE_E[19]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_E[20]	HEX_V0[3]	XXX57005[57005][57005]
SINGLE_E[20]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_E[21]	HEX_V6[3]	XXX57005[57005][57005]
SINGLE_E[21]	OUT_TBUF_W[0]	XXX57005[57005][57005]
SINGLE_E[21]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_E[22]	HEX_V3[3]	XXX57005[57005][57005]
SINGLE_E[22]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_E[23]	HEX_V0[3]	XXX57005[57005][57005]
SINGLE_E[23]	OUT_IO_IQ[0]	XXX57005[57005][57005]

virtex IO_W switchbox INT muxes HEX_H0[0]
Bits	Destination
HEX_H0[0]
	Source
OUT_IO_I[1]

virtex IO_W switchbox INT muxes HEX_H0[1]
Bits	Destination
HEX_H0[1]
	Source
OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H0[2]
Bits	Destination
HEX_H0[2]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H0[3]
Bits	Destination
HEX_H0[3]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H1[0]
Bits	Destination
HEX_H1[0]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H1[1]
Bits	Destination
HEX_H1[1]
	Source
OUT_IO_IQ[0]

virtex IO_W switchbox INT muxes HEX_H1[2]
Bits	Destination
HEX_H1[2]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H1[3]
Bits	Destination
HEX_H1[3]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H2[0]
Bits	Destination
HEX_H2[0]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H2[1]
Bits	Destination
HEX_H2[1]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H2[2]
Bits	Destination
HEX_H2[2]
	Source
OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H2[3]
Bits	Destination
HEX_H2[3]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H3[0]
Bits	Destination
HEX_H3[0]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H3[1]
Bits	Destination
HEX_H3[1]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H3[2]
Bits	Destination
HEX_H3[2]
	Source
OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H3[3]
Bits	Destination
HEX_H3[3]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H4[0]
Bits	Destination
HEX_H4[0]
	Source
OUT_IO_IQ[0]

virtex IO_W switchbox INT muxes HEX_H4[1]
Bits	Destination
HEX_H4[1]
	Source
OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes HEX_H4[2]
Bits	Destination
HEX_H4[2]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H4[3]
Bits	Destination
HEX_H4[3]
	Source
OUT_IO_I[2]

virtex IO_W switchbox INT muxes HEX_H5[0]
Bits	Destination
HEX_H5[0]
	Source
OUT_IO_IQ[0]

virtex IO_W switchbox INT muxes HEX_H5[1]
Bits	Destination
HEX_H5[1]
	Source
OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes HEX_H5[2]
Bits	Destination
HEX_H5[2]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H5[3]
Bits	Destination
HEX_H5[3]
	Source
OUT_IO_I[2]

virtex IO_W switchbox INT muxes HEX_E0[0]
Bits	Destination
HEX_E0[0]
	Source
OUT_IO_IQ[0]

virtex IO_W switchbox INT muxes HEX_E0[1]
Bits	Destination
HEX_E0[1]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_E0[2]
Bits	Destination
HEX_E0[2]
	Source
OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes HEX_E0[3]
Bits	Destination
HEX_E0[3]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_E1[0]
Bits	Destination
HEX_E1[0]
	Source
OUT_IO_IQ[0]

virtex IO_W switchbox INT muxes HEX_E1[1]
Bits	Destination
HEX_E1[1]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_E1[2]
Bits	Destination
HEX_E1[2]
	Source
OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes HEX_E1[3]
Bits	Destination
HEX_E1[3]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_E2[0]
Bits	Destination
HEX_E2[0]
	Source
HEX_W3[0]

virtex IO_W switchbox INT muxes HEX_E2[1]
Bits	Destination
HEX_E2[1]
	Source
HEX_W3[1]

virtex IO_W switchbox INT muxes HEX_E2[2]
Bits	Destination
HEX_E2[2]
	Source
HEX_W3[2]

virtex IO_W switchbox INT muxes HEX_E2[3]
Bits	Destination
HEX_E2[3]
	Source
HEX_W3[3]

virtex IO_W switchbox INT muxes HEX_E3[0]
Bits	Destination
HEX_E3[0]
	Source
HEX_W4[0]

virtex IO_W switchbox INT muxes HEX_E3[1]
Bits	Destination
HEX_E3[1]
	Source
HEX_W4[1]

virtex IO_W switchbox INT muxes HEX_E3[2]
Bits	Destination
HEX_E3[2]
	Source
HEX_W4[2]

virtex IO_W switchbox INT muxes HEX_E3[3]
Bits	Destination
HEX_E3[3]
	Source
HEX_W4[3]

virtex IO_W switchbox INT muxes HEX_E4[0]
Bits	Destination
HEX_E4[0]
	Source
HEX_W5[0]

virtex IO_W switchbox INT muxes HEX_E4[1]
Bits	Destination
HEX_E4[1]
	Source
HEX_W5[1]

virtex IO_W switchbox INT muxes HEX_E4[2]
Bits	Destination
HEX_E4[2]
	Source
HEX_W5[2]

virtex IO_W switchbox INT muxes HEX_E4[3]
Bits	Destination
HEX_E4[3]
	Source
HEX_W5[3]

virtex IO_W switchbox INT muxes HEX_E5[0]
Bits	Destination
HEX_E5[0]
	Source
HEX_W6[0]

virtex IO_W switchbox INT muxes HEX_E5[1]
Bits	Destination
HEX_E5[1]
	Source
HEX_W6[1]

virtex IO_W switchbox INT muxes HEX_E5[2]
Bits	Destination
HEX_E5[2]
	Source
HEX_W6[2]

virtex IO_W switchbox INT muxes HEX_E5[3]
Bits	Destination
HEX_E5[3]
	Source
HEX_W6[3]

virtex IO_W switchbox INT muxes HEX_V0[0]
Bits	Destination
HEX_V0[0]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V0[1]
Bits	Destination
HEX_V0[1]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V0[2]
Bits	Destination
HEX_V0[2]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V0[3]
Bits	Destination
HEX_V0[3]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V6[0]
Bits	Destination
HEX_V6[0]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V6[1]
Bits	Destination
HEX_V6[1]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V6[2]
Bits	Destination
HEX_V6[2]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V6[3]
Bits	Destination
HEX_V6[3]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LH[0]
Bits	Destination
LH[0]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LH[1]
Bits	Destination
LH[1]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LH[2]
Bits	Destination
LH[2]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes LH[3]
Bits	Destination
LH[3]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes LH[4]
Bits	Destination
LH[4]
	Source
OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes LH[5]
Bits	Destination
LH[5]
	Source
OUT_IO_I[2]

virtex IO_W switchbox INT muxes LH[6]
Bits	Destination
LH[6]
	Source
OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes LH[7]
Bits	Destination
LH[7]
	Source
OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes LH[8]
Bits	Destination
LH[8]
	Source
OUT_IO_IQ[0]

virtex IO_W switchbox INT muxes LH[9]
Bits	Destination
LH[9]
	Source
OUT_IO_IQ[0]

virtex IO_W switchbox INT muxes LH[10]
Bits	Destination
LH[10]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LH[11]
Bits	Destination
LH[11]
	Source
OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes LV[0]
Bits	Destination
LV[0]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LV[6]
Bits	Destination
LV[6]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes IMUX_TBUF_T[0]
Bits	Destination
IMUX_TBUF_T[0]
	Source
HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_TBUF_T[1]
Bits	Destination
IMUX_TBUF_T[1]
	Source
HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_TBUF_I[0]
Bits	Destination
IMUX_TBUF_I[0]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes IMUX_TBUF_I[1]
Bits	Destination
IMUX_TBUF_I[1]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes IMUX_IO_CLK[0]
Bits	Destination
IMUX_IO_CLK[0]
	Source
HEX_V6_BUF[2]

virtex IO_W switchbox INT muxes IMUX_IO_CLK[1]
Bits	Destination
IMUX_IO_CLK[1]
	Source
HEX_V6_BUF[2]

virtex IO_W switchbox INT muxes IMUX_IO_CLK[2]
Bits	Destination
IMUX_IO_CLK[2]
	Source
HEX_V6_BUF[2]

virtex IO_W switchbox INT muxes IMUX_IO_CLK[3]
Bits	Destination
IMUX_IO_CLK[3]
	Source
HEX_V6_BUF[2]

virtex IO_W switchbox INT muxes IMUX_IO_SR[0]
Bits	Destination
IMUX_IO_SR[0]
	Source
HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_IO_SR[1]
Bits	Destination
IMUX_IO_SR[1]
	Source
HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_IO_SR[2]
Bits	Destination
IMUX_IO_SR[2]
	Source
HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_IO_SR[3]
Bits	Destination
IMUX_IO_SR[3]
	Source
HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_IO_ICE[0]
Bits	Destination
IMUX_IO_ICE[0]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_ICE[1]
Bits	Destination
IMUX_IO_ICE[1]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_ICE[2]
Bits	Destination
IMUX_IO_ICE[2]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_ICE[3]
Bits	Destination
IMUX_IO_ICE[3]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_OCE[0]
Bits	Destination
IMUX_IO_OCE[0]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_OCE[1]
Bits	Destination
IMUX_IO_OCE[1]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_OCE[2]
Bits	Destination
IMUX_IO_OCE[2]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_OCE[3]
Bits	Destination
IMUX_IO_OCE[3]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_TCE[0]
Bits	Destination
IMUX_IO_TCE[0]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_TCE[1]
Bits	Destination
IMUX_IO_TCE[1]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_TCE[2]
Bits	Destination
IMUX_IO_TCE[2]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_TCE[3]
Bits	Destination
IMUX_IO_TCE[3]
	Source
HEX_V6_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_O[0]
Bits	Destination
IMUX_IO_O[0]
	Source
OUT_TBUF_W[3]

virtex IO_W switchbox INT muxes IMUX_IO_O[1]
Bits	Destination
IMUX_IO_O[1]
	Source
OUT_TBUF_W[3]

virtex IO_W switchbox INT muxes IMUX_IO_O[2]
Bits	Destination
IMUX_IO_O[2]
	Source
OUT_TBUF_W[3]

virtex IO_W switchbox INT muxes IMUX_IO_O[3]
Bits	Destination
IMUX_IO_O[3]
	Source
OUT_TBUF_W[3]

virtex IO_W switchbox INT muxes IMUX_IO_T[0]
Bits	Destination
IMUX_IO_T[0]
	Source
HEX_V6_BUF[0]

virtex IO_W switchbox INT muxes IMUX_IO_T[1]
Bits	Destination
IMUX_IO_T[1]
	Source
HEX_V6_BUF[0]

virtex IO_W switchbox INT muxes IMUX_IO_T[2]
Bits	Destination
IMUX_IO_T[2]
	Source
HEX_V6_BUF[0]

virtex IO_W switchbox INT muxes IMUX_IO_T[3]
Bits	Destination
IMUX_IO_T[3]
	Source
HEX_V6_BUF[0]

virtex IO_W switchbox INT muxes OMUX[0]
Bits	Destination
OMUX[0]
	Source
OUT_IO_I[3]

virtex IO_W switchbox INT muxes OMUX[1]
Bits	Destination
OMUX[1]
	Source
OUT_IO_I[3]

Bel TBUF[0]

virtex IO_W bel TBUF[0]
Pin	Direction	Wires
I	input	IMUX_TBUF_I[0]
T	input	IMUX_TBUF_T[0]

Bel TBUF[1]

virtex IO_W bel TBUF[1]
Pin	Direction	Wires
I	input	IMUX_TBUF_I[1]
T	input	IMUX_TBUF_T[1]

Bel TBUS

virtex IO_W bel TBUS
Pin	Direction	Wires
BUS0	output	OUT_TBUF_W[2]
BUS1	output	OUT_TBUF_W[3]
BUS2	output	OUT_TBUF_W[0]
BUS3	output	OUT_TBUF_W[1]

Bel IO[0]

virtex IO_W bel IO[0]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[0]
I	output	OUT_IO_I[0]
ICE	input	IMUX_IO_ICE[0]
IQ	output	OUT_IO_IQ[0]
O	input	IMUX_IO_O[0]
OCE	input	IMUX_IO_OCE[0]
SR	input	IMUX_IO_SR[0]
T	input	IMUX_IO_T[0]
TCE	input	IMUX_IO_TCE[0]

Bel IO[1]

virtex IO_W bel IO[1]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[1]
I	output	OUT_IO_I[1]
ICE	input	IMUX_IO_ICE[1]
IQ	output	OUT_IO_IQ[1]
O	input	IMUX_IO_O[1]
OCE	input	IMUX_IO_OCE[1]
SR	input	IMUX_IO_SR[1]
T	input	IMUX_IO_T[1]
TCE	input	IMUX_IO_TCE[1]

Bel IO[2]

virtex IO_W bel IO[2]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[2]
I	output	OUT_IO_I[2]
ICE	input	IMUX_IO_ICE[2]
IQ	output	OUT_IO_IQ[2]
O	input	IMUX_IO_O[2]
OCE	input	IMUX_IO_OCE[2]
SR	input	IMUX_IO_SR[2]
T	input	IMUX_IO_T[2]
TCE	input	IMUX_IO_TCE[2]

Bel IO[3]

virtex IO_W bel IO[3]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[3]
I	output	OUT_IO_I[3]
ICE	input	IMUX_IO_ICE[3]
IQ	output	OUT_IO_IQ[3]
O	input	IMUX_IO_O[3]
OCE	input	IMUX_IO_OCE[3]
SR	input	IMUX_IO_SR[3]
T	input	IMUX_IO_T[3]
TCE	input	IMUX_IO_TCE[3]

Bel wires

virtex IO_W bel wires
Wire	Pins
IMUX_TBUF_T[0]	TBUF[0].T
IMUX_TBUF_T[1]	TBUF[1].T
IMUX_TBUF_I[0]	TBUF[0].I
IMUX_TBUF_I[1]	TBUF[1].I
IMUX_IO_CLK[0]	IO[0].CLK
IMUX_IO_CLK[1]	IO[1].CLK
IMUX_IO_CLK[2]	IO[2].CLK
IMUX_IO_CLK[3]	IO[3].CLK
IMUX_IO_SR[0]	IO[0].SR
IMUX_IO_SR[1]	IO[1].SR
IMUX_IO_SR[2]	IO[2].SR
IMUX_IO_SR[3]	IO[3].SR
IMUX_IO_ICE[0]	IO[0].ICE
IMUX_IO_ICE[1]	IO[1].ICE
IMUX_IO_ICE[2]	IO[2].ICE
IMUX_IO_ICE[3]	IO[3].ICE
IMUX_IO_OCE[0]	IO[0].OCE
IMUX_IO_OCE[1]	IO[1].OCE
IMUX_IO_OCE[2]	IO[2].OCE
IMUX_IO_OCE[3]	IO[3].OCE
IMUX_IO_TCE[0]	IO[0].TCE
IMUX_IO_TCE[1]	IO[1].TCE
IMUX_IO_TCE[2]	IO[2].TCE
IMUX_IO_TCE[3]	IO[3].TCE
IMUX_IO_O[0]	IO[0].O
IMUX_IO_O[1]	IO[1].O
IMUX_IO_O[2]	IO[2].O
IMUX_IO_O[3]	IO[3].O
IMUX_IO_T[0]	IO[0].T
IMUX_IO_T[1]	IO[1].T
IMUX_IO_T[2]	IO[2].T
IMUX_IO_T[3]	IO[3].T
OUT_TBUF_W[0]	TBUS.BUS2
OUT_TBUF_W[1]	TBUS.BUS3
OUT_TBUF_W[2]	TBUS.BUS0
OUT_TBUF_W[3]	TBUS.BUS1
OUT_IO_I[0]	IO[0].I
OUT_IO_I[1]	IO[1].I
OUT_IO_I[2]	IO[2].I
OUT_IO_I[3]	IO[3].I
OUT_IO_IQ[0]	IO[0].IQ
OUT_IO_IQ[1]	IO[1].IQ
OUT_IO_IQ[2]	IO[2].IQ
OUT_IO_IQ[3]	IO[3].IQ

Bitstream

virtex IO_W rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

### Bitstream

virtex IO_W rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47
B17	-	-	-	-	-	IO[3]:READBACK_TFF	-	~IO[3]:SHORTEN_JTAG_CHAIN	IO[3]:IFF_DELAY_ENABLE	IO[3]:READBACK_OFF	-	-	-	-	-	IO[3]:READBACK_IFF	-	-	-	-	IO[2]:READBACK_IFF	-	-	-	-	-	IO[2]:READBACK_OFF	IO[2]:IFF_DELAY_ENABLE	~IO[2]:SHORTEN_JTAG_CHAIN	-	IO[2]:READBACK_TFF	-	-	-	-	IO[1]:READBACK_TFF	-	~IO[1]:SHORTEN_JTAG_CHAIN	IO[1]:IFF_DELAY_ENABLE	IO[1]:READBACK_OFF	-	-	-	-	-	IO[1]:READBACK_IFF	-	-
B16	-	-	-	IO[3]:TFF_SR_ENABLE	IO[3]:TFF_LATCH	IO[3]:TMUX[0]	~IO[3]:TFF_INIT	IO[3]:TFF_SR_SYNC	IO[3]:OFF_SR_SYNC	~IO[3]:OFF_INIT	IO[3]:OMUX[0]	IO[3]:OFF_LATCH	IO[3]:OFF_SR_ENABLE	IO[3]:IFF_SR_ENABLE	IO[3]:IFF_LATCH	IO[3]:I_DELAY_ENABLE	IO[3]:IFF_INIT	IO[3]:IFF_SR_SYNC	IO[2]:IFF_SR_SYNC	IO[2]:IFF_INIT	IO[2]:I_DELAY_ENABLE	IO[2]:IFF_LATCH	IO[2]:IFF_SR_ENABLE	IO[2]:OFF_SR_ENABLE	IO[2]:OFF_LATCH	IO[2]:OMUX[0]	~IO[2]:OFF_INIT	IO[2]:OFF_SR_SYNC	IO[2]:TFF_SR_SYNC	~IO[2]:TFF_INIT	IO[2]:TMUX[0]	IO[2]:TFF_LATCH	IO[2]:TFF_SR_ENABLE	IO[1]:TFF_SR_ENABLE	IO[1]:TFF_LATCH	IO[1]:TMUX[0]	~IO[1]:TFF_INIT	IO[1]:TFF_SR_SYNC	IO[1]:OFF_SR_SYNC	~IO[1]:OFF_INIT	IO[1]:OMUX[0]	IO[1]:OFF_LATCH	IO[1]:OFF_SR_ENABLE	IO[1]:IFF_SR_ENABLE	IO[1]:IFF_LATCH	IO[1]:I_DELAY_ENABLE	IO[1]:IFF_INIT	IO[1]:IFF_SR_SYNC
B15	INT:MUX.LV[0][0]	INT:MUX.LV[0][6]	INT:DRIVE.LV[0]	INT:MUX.LV[0][1]	INT:MUX.LV[0][8]	INT:MUX.LV[6][6]	INT:MUX.LV[6][5]	INT:MUX.LV[0][5]	INT:MUX.LV[6][8]	INT:MUX.LV[6][2]	INT:DRIVE.LV[6]	INT:MUX.LV[0][3]	INT:MUX.LV[0][2]	INT:MUX.LV[6][1]	INT:MUX.LV[0][4]	INT:MUX.LV[6][4]	INT:MUX.IMUX_TBUF_I[0][0]	INT:MUX.IMUX_TBUF_I[0][1]	~INT:INV.IMUX_TBUF_I[0]	INT:MUX.IMUX_TBUF_I[0][4]	INT:MUX.IMUX_TBUF_I[0][3]	INT:MUX.IMUX_TBUF_I[1][3]	INT:MUX.IMUX_TBUF_I[1][4]	~INT:INV.IMUX_TBUF_I[1]	INT:MUX.IMUX_TBUF_I[1][0]	INT:INV.IMUX_TBUF_T[0]	INT:MUX.IMUX_TBUF_T[0][4]	INT:MUX.IMUX_TBUF_T[0][3]	INT:MUX.IMUX_TBUF_T[1][3]	INT:MUX.IMUX_TBUF_T[1][4]	INT:MUX.OMUX[0][2]	INT:INV.IMUX_TBUF_T[1]	INT:MUX.OMUX[1][2]	INT:MUX.OMUX[0][0]	INT:MUX.OMUX[1][1]	-	-	INT:MUX.IMUX_TBUF_I[0][2]	INT:MUX.IMUX_TBUF_I[1][2]	INT:MUX.IMUX_TBUF_I[1][1]	INT:MUX.IMUX_TBUF_T[0][2]	INT:MUX.OMUX[0][1]	INT:MUX.OMUX[1][0]	INT:MUX.IMUX_TBUF_T[1][2]	~TBUS:JOINER	~TBUF[1]:OUT_A	~TBUF[0]:OUT_B	~TBUS:JOINER_E
B14	~INT:INV.IMUX_IO_O[3]	INT:MUX.IMUX_IO_O[3][0]	INT:MUX.IMUX_IO_O[3][2]	INT:MUX.IMUX_IO_O[3][5]	INT:MUX.IMUX_IO_O[2][3]	INT:MUX.IMUX_IO_O[2][4]	INT:MUX.IMUX_IO_O[2][2]	INT:MUX.IMUX_IO_O[2][5]	INT:MUX.IMUX_IO_O[2][0]	~INT:INV.IMUX_IO_O[2]	IO[3]:INV.IFF.CLK	IO[3]:INV.OFF.CLK	IO[3]:INV.TFF.CLK	IO[2]:INV.IFF.CLK	IO[2]:INV.OFF.CLK	IO[2]:INV.TFF.CLK	INT:MUX.IMUX_IO_CLK[2][9]	INT:MUX.IMUX_IO_CLK[3][9]	INT:MUX.IMUX_IO_CLK[3][8]	INT:MUX.IMUX_IO_CLK[2][10]	INT:MUX.IMUX_IO_CLK[3][0]	INT:MUX.IMUX_IO_CLK[3][6]	INT:MUX.IMUX_IO_CLK[3][3]	INT:MUX.IMUX_IO_CLK[2][5]	INT:MUX.IMUX_IO_CLK[1][5]	INT:MUX.IMUX_IO_CLK[0][3]	INT:MUX.IMUX_IO_CLK[0][6]	INT:MUX.IMUX_IO_CLK[0][0]	INT:MUX.IMUX_IO_CLK[1][10]	INT:MUX.IMUX_IO_CLK[0][8]	INT:MUX.IMUX_IO_CLK[0][9]	INT:MUX.IMUX_IO_CLK[1][9]	IO[1]:INV.TFF.CLK	IO[1]:INV.OFF.CLK	IO[1]:INV.IFF.CLK	-	-	-	~INT:INV.IMUX_IO_O[1]	INT:MUX.IMUX_IO_O[1][0]	INT:MUX.IMUX_IO_O[1][2]	INT:MUX.IMUX_IO_O[1][5]	INT:MUX.IMUX_IO_O[1][8]	INT:MUX.IMUX_IO_O[1][9]	INT:MUX.IMUX_IO_O[0][2]	INT:MUX.IMUX_IO_O[0][5]	INT:MUX.IMUX_IO_O[0][0]	-
B13	INT:MUX.IMUX_IO_O[3][7]	INT:MUX.IMUX_IO_O[3][6]	INT:MUX.IMUX_IO_O[3][1]	INT:MUX.IMUX_IO_O[3][9]	INT:MUX.IMUX_IO_O[3][8]	INT:MUX.IMUX_IO_O[3][4]	INT:MUX.IMUX_IO_O[3][3]	INT:MUX.IMUX_IO_O[2][1]	INT:MUX.IMUX_IO_O[2][9]	INT:MUX.IMUX_IO_O[2][8]	-	INT:MUX.IMUX_IO_CLK[3][7]	-	INT:MUX.IMUX_IO_CLK[2][3]	INT:MUX.IMUX_IO_CLK[2][7]	INT:MUX.IMUX_IO_CLK[2][1]	INT:MUX.IMUX_IO_CLK[2][4]	INT:MUX.IMUX_IO_CLK[3][5]	INT:MUX.IMUX_IO_CLK[2][0]	INT:MUX.IMUX_IO_CLK[2][8]	INT:MUX.IMUX_IO_CLK[3][1]	INT:MUX.IMUX_IO_CLK[2][2]	INT:MUX.IMUX_IO_CLK[3][2]	INT:MUX.IMUX_IO_CLK[3][4]	INT:MUX.IMUX_IO_CLK[0][4]	INT:MUX.IMUX_IO_CLK[0][2]	INT:MUX.IMUX_IO_CLK[1][2]	INT:MUX.IMUX_IO_CLK[0][1]	INT:MUX.IMUX_IO_CLK[1][8]	INT:MUX.IMUX_IO_CLK[1][0]	INT:MUX.IMUX_IO_CLK[0][5]	INT:MUX.IMUX_IO_CLK[1][4]	INT:MUX.IMUX_IO_CLK[1][1]	INT:MUX.IMUX_IO_CLK[1][7]	INT:MUX.IMUX_IO_CLK[1][3]	-	INT:MUX.IMUX_IO_CLK[0][7]	-	INT:MUX.IMUX_IO_O[1][3]	INT:MUX.IMUX_IO_O[1][4]	INT:MUX.IMUX_IO_O[1][1]	INT:MUX.IMUX_IO_O[0][9]	INT:MUX.IMUX_IO_O[0][8]	INT:MUX.IMUX_IO_O[0][3]	INT:MUX.IMUX_IO_O[0][4]	INT:MUX.IMUX_IO_O[0][1]	INT:MUX.IMUX_IO_O[0][6]	INT:MUX.IMUX_IO_O[0][7]
B12	INT:MUX.LH[6][0]	INT:MUX.LV[6][0]	INT:DRIVE.LH[6]	-	INT:MUX.IMUX_IO_O[2][7]	INT:DRIVE.LH[5]	INT:MUX.IMUX_IO_O[2][6]	INT:MUX.LH[5][0]	INT:MUX.LH[4][0]	INT:MUX.LV[0][7]	INT:DRIVE.LH[4]	-	INT:MUX.LV[6][7]	INT:DRIVE.LH[3]	INT:MUX.LV[6][3]	INT:MUX.LH[3][0]	INT:MUX.LH[2][0]	INT:MUX.IMUX_IO_CLK[3][10]	INT:DRIVE.LH[2]	-	-	INT:DRIVE.LH[1]	INT:MUX.IMUX_IO_CLK[2][6]	-	-	INT:MUX.IMUX_IO_CLK[1][6]	INT:DRIVE.LH[0]	INT:MUX.IMUX_TBUF_T[0][0]	INT:MUX.IMUX_TBUF_T[1][0]	INT:DRIVE.LH[7]	INT:MUX.IMUX_IO_CLK[0][10]	INT:MUX.LH[7][0]	INT:MUX.LH[8][0]	INT:MUX.IMUX_TBUF_T[1][1]	INT:DRIVE.LH[8]	INT:MUX.IMUX_TBUF_T[0][1]	-	INT:DRIVE.LH[9]	~TBUF[1]:OUT_B	INT:MUX.LH[9][0]	INT:MUX.LH[10][0]	INT:MUX.IMUX_IO_O[1][6]	INT:DRIVE.LH[10]	INT:MUX.IMUX_IO_O[1][7]	-	INT:DRIVE.LH[11]	~TBUF[0]:OUT_A	INT:MUX.LH[11][0]
B11	INT:MUX.IMUX_IO_ICE[2][3]	INT:MUX.IMUX_IO_ICE[2][4]	INT:MUX.IMUX_IO_ICE[2][5]	INT:MUX.IMUX_IO_ICE[3][3]	INT:MUX.IMUX_IO_ICE[3][2]	INT:MUX.IMUX_IO_ICE[0][3]	INT:MUX.IMUX_IO_ICE[0][2]	INT:MUX.IMUX_IO_ICE[1][5]	INT:MUX.IMUX_IO_ICE[1][4]	INT:MUX.IMUX_IO_ICE[1][3]	INT:MUX.IMUX_IO_OCE[2][3]	INT:MUX.IMUX_IO_OCE[2][4]	INT:MUX.IMUX_IO_OCE[2][5]	INT:MUX.IMUX_IO_OCE[3][3]	INT:MUX.IMUX_IO_OCE[0][3]	INT:MUX.IMUX_IO_OCE[0][2]	INT:MUX.IMUX_IO_TCE[3][2]	INT:MUX.IMUX_IO_OCE[1][5]	INT:MUX.IMUX_IO_OCE[1][4]	INT:MUX.IMUX_IO_OCE[1][3]	INT:MUX.IMUX_IO_TCE[2][3]	INT:MUX.IMUX_IO_TCE[2][4]	INT:MUX.IMUX_IO_TCE[2][5]	INT:MUX.IMUX_IO_TCE[3][3]	INT:MUX.IMUX_IO_TCE[1][3]	INT:MUX.IMUX_IO_TCE[0][5]	INT:MUX.IMUX_IO_TCE[0][4]	INT:MUX.IMUX_IO_TCE[0][3]	INT:MUX.IMUX_IO_SR[1][0]	INT:MUX.IMUX_IO_SR[1][4]	INT:MUX.IMUX_IO_SR[1][5]	INT:MUX.IMUX_IO_TCE[1][2]	INT:MUX.IMUX_IO_SR[0][1]	INT:MUX.IMUX_IO_SR[0][0]	INT:MUX.IMUX_IO_SR[3][0]	INT:MUX.IMUX_IO_SR[2][5]	INT:MUX.IMUX_IO_SR[2][4]	INT:MUX.IMUX_IO_SR[2][0]	INT:MUX.IMUX_IO_T[1][0]	INT:MUX.IMUX_IO_T[1][4]	INT:MUX.IMUX_IO_T[1][5]	INT:MUX.IMUX_IO_T[0][1]	INT:MUX.IMUX_IO_T[0][0]	INT:MUX.IMUX_IO_T[3][1]	INT:MUX.IMUX_IO_T[3][0]	INT:MUX.IMUX_IO_T[2][5]	INT:MUX.IMUX_IO_T[2][4]	INT:MUX.IMUX_IO_T[2][0]
B10	INT:MUX.IMUX_IO_ICE[2][0]	INT:MUX.IMUX_IO_ICE[3][5]	INT:MUX.IMUX_IO_ICE[3][4]	INT:MUX.IMUX_IO_ICE[3][0]	~INT:INV.IMUX_IO_ICE[2]	~INT:INV.IMUX_IO_ICE[1]	INT:MUX.IMUX_IO_ICE[0][0]	INT:MUX.IMUX_IO_ICE[0][4]	INT:MUX.IMUX_IO_ICE[0][5]	INT:MUX.IMUX_IO_ICE[1][0]	INT:MUX.IMUX_IO_OCE[2][1]	INT:MUX.IMUX_IO_OCE[3][5]	INT:MUX.IMUX_IO_OCE[3][4]	INT:MUX.IMUX_IO_OCE[3][1]	~INT:INV.IMUX_IO_OCE[1]	-	INT:MUX.IMUX_IO_OCE[0][1]	INT:MUX.IMUX_IO_OCE[0][4]	INT:MUX.IMUX_IO_OCE[0][5]	INT:MUX.IMUX_IO_TCE[2][0]	INT:MUX.IMUX_IO_TCE[3][5]	INT:MUX.IMUX_IO_TCE[3][4]	~INT:INV.IMUX_IO_TCE[3]	INT:MUX.IMUX_IO_TCE[3][0]	INT:MUX.IMUX_IO_TCE[1][0]	~INT:INV.IMUX_IO_TCE[1]	INT:MUX.IMUX_IO_TCE[1][4]	INT:MUX.IMUX_IO_TCE[1][5]	INT:MUX.IMUX_IO_TCE[0][0]	INT:MUX.IMUX_IO_SR[0][5]	INT:MUX.IMUX_IO_SR[0][4]	INT:MUX.IMUX_IO_SR[0][3]	-	INT:INV.IMUX_IO_SR[1]	INT:MUX.IMUX_IO_SR[3][3]	INT:MUX.IMUX_IO_SR[3][4]	INT:MUX.IMUX_IO_SR[3][5]	INT:MUX.IMUX_IO_SR[2][3]	INT:MUX.IMUX_IO_T[1][3]	INT:MUX.IMUX_IO_T[0][5]	INT:MUX.IMUX_IO_T[0][4]	INT:MUX.IMUX_IO_T[0][3]	~INT:INV.IMUX_IO_T[1]	~INT:INV.IMUX_IO_T[2]	INT:MUX.IMUX_IO_T[3][3]	INT:MUX.IMUX_IO_T[3][4]	INT:MUX.IMUX_IO_T[3][5]	INT:MUX.IMUX_IO_T[2][3]
B9	INT:MUX.IMUX_IO_ICE[2][2]	INT:MUX.IMUX_IO_ICE[2][1]	INT:MUX.IMUX_IO_ICE[3][1]	~INT:INV.IMUX_IO_ICE[3]	INT:MUX.IMUX_IO_ICE[1][2]	INT:MUX.IMUX_IO_ICE[1][1]	-	INT:MUX.IMUX_IO_ICE[0][1]	INT:MUX.IMUX_IO_OCE[3][2]	INT:MUX.IMUX_IO_OCE[2][0]	~INT:INV.IMUX_IO_OCE[3]	INT:MUX.IMUX_IO_OCE[2][2]	INT:MUX.IMUX_IO_OCE[3][0]	~INT:INV.IMUX_IO_OCE[2]	INT:MUX.IMUX_IO_OCE[0][0]	INT:MUX.IMUX_IO_OCE[1][0]	INT:MUX.IMUX_IO_OCE[1][2]	-	-	INT:MUX.IMUX_IO_OCE[1][1]	INT:MUX.IMUX_IO_TCE[3][1]	INT:MUX.IMUX_IO_TCE[2][1]	INT:MUX.IMUX_IO_TCE[2][2]	~INT:INV.IMUX_IO_TCE[2]	-	INT:MUX.IMUX_IO_TCE[0][2]	INT:MUX.IMUX_IO_TCE[0][1]	INT:MUX.IMUX_IO_TCE[1][1]	INT:MUX.IMUX_IO_SR[1][3]	-	-	INT:MUX.IMUX_IO_SR[1][1]	INT:MUX.IMUX_IO_SR[1][2]	INT:MUX.IMUX_IO_SR[0][2]	INT:INV.IMUX_IO_SR[2]	INT:MUX.IMUX_IO_SR[3][2]	INT:MUX.IMUX_IO_SR[2][1]	INT:INV.IMUX_IO_SR[3]	INT:MUX.IMUX_IO_SR[2][2]	INT:MUX.IMUX_IO_SR[3][1]	INT:MUX.IMUX_IO_T[0][2]	-	INT:MUX.IMUX_IO_T[1][2]	INT:MUX.IMUX_IO_T[1][1]	~INT:INV.IMUX_IO_T[3]	INT:MUX.IMUX_IO_T[3][2]	INT:MUX.IMUX_IO_T[2][2]	INT:MUX.IMUX_IO_T[2][1]
B8	INT:PASS.SINGLE_E[23].HEX_V0[3]	INT:PASS.SINGLE_E[22].HEX_V3[3]	INT:PASS.SINGLE_E[22].OUT_IO_IQ[1]	INT:PASS.SINGLE_E[21].HEX_V6[3]	INT:PASS.SINGLE_E[21].OUT_IO_IQ[2]	INT:PASS.SINGLE_E[21].OUT_TBUF_W[0]	INT:PASS.SINGLE_E[20].OUT_IO_IQ[3]	INT:PASS.SINGLE_E[20].HEX_V0[3]	-	INT:PASS.SINGLE_E[19].HEX_V3[3]	INT:PASS.SINGLE_E[18].OUT_IO_I[1]	INT:PASS.SINGLE_E[18].OUT_TBUF_W[0]	INT:PASS.SINGLE_E[17].HEX_V0[2]	INT:PASS.SINGLE_E[16].HEX_V3[2]	INT:PASS.SINGLE_E[16].OUT_IO_I[3]	INT:PASS.SINGLE_E[15].HEX_V6[2]	-	INT:PASS.SINGLE_E[15].OUT_TBUF_W[1]	INT:PASS.SINGLE_E[14].OUT_IO_IQ[1]	INT:PASS.SINGLE_E[14].HEX_V0[2]	INT:PASS.SINGLE_E[13].OUT_IO_IQ[2]	INT:PASS.SINGLE_E[13].HEX_V3[2]	INT:PASS.SINGLE_E[12].OUT_IO_IQ[3]	INT:PASS.SINGLE_E[12].OUT_TBUF_W[1]	INT:PASS.SINGLE_E[11].HEX_V0[1]	INT:PASS.SINGLE_E[10].HEX_V3[1]	INT:PASS.SINGLE_E[10].OUT_IO_I[1]	INT:PASS.SINGLE_E[9].HEX_V6[1]	INT:PASS.SINGLE_E[9].OUT_IO_I[2]	INT:PASS.SINGLE_E[9].OUT_TBUF_W[2]	INT:PASS.SINGLE_E[8].OUT_IO_I[3]	INT:PASS.SINGLE_E[8].HEX_V0[1]	-	INT:PASS.SINGLE_E[7].HEX_V3[1]	INT:PASS.SINGLE_E[6].OUT_IO_IQ[1]	INT:PASS.SINGLE_E[6].OUT_TBUF_W[2]	INT:PASS.SINGLE_E[5].HEX_V0[0]	INT:PASS.SINGLE_E[4].HEX_V3[0]	INT:PASS.SINGLE_E[4].OUT_IO_IQ[3]	INT:PASS.SINGLE_E[3].HEX_V6[0]	-	INT:PASS.SINGLE_E[3].OUT_TBUF_W[3]	INT:PASS.SINGLE_E[2].OUT_IO_I[1]	INT:PASS.SINGLE_E[2].HEX_V0[0]	INT:PASS.SINGLE_E[1].OUT_IO_I[2]	INT:PASS.SINGLE_E[1].HEX_V3[0]	INT:PASS.SINGLE_E[0].OUT_IO_I[3]	INT:PASS.SINGLE_E[0].OUT_TBUF_W[3]
B7	-	-	-	-	-	-	-	-	-	-	-	INT:PASS.SINGLE_E[18].HEX_V6[3]	INT:PASS.SINGLE_E[17].OUT_IO_I[2]	-	-	-	-	-	-	-	-	-	-	INT:PASS.SINGLE_E[12].HEX_V6[2]	-	-	-	-	-	-	-	-	-	-	-	INT:PASS.SINGLE_E[6].HEX_V6[1]	INT:PASS.SINGLE_E[5].OUT_IO_IQ[2]	-	-	-	-	-	-	-	-	-	-	INT:PASS.SINGLE_E[0].HEX_V6[0]
B6	INT:DRIVE.HEX_V0[3]	INT:MUX.HEX_V6[3][5]	INT:MUX.HEX_V6[3][3]	INT:MUX.HEX_V0[3][0]	INT:MUX.HEX_V0[3][5]	INT:MUX.HEX_V0[3][6]	INT:MUX.HEX_V0[3][4]	INT:MUX.HEX_V0[3][2]	INT:MUX.HEX_V0[3][3]	INT:MUX.HEX_V6[3][1]	INT:MUX.HEX_V6[3][6]	INT:DRIVE.HEX_V6[3]	INT:DRIVE.HEX_V0[2]	INT:MUX.HEX_V6[2][5]	INT:MUX.HEX_V6[2][3]	INT:MUX.HEX_V0[2][0]	INT:MUX.HEX_V0[2][5]	INT:MUX.HEX_V0[2][6]	INT:MUX.HEX_V0[2][4]	INT:MUX.HEX_V0[2][2]	INT:MUX.HEX_V0[2][3]	INT:MUX.HEX_V6[2][1]	INT:MUX.HEX_V6[2][6]	INT:DRIVE.HEX_V6[2]	INT:DRIVE.HEX_V0[1]	INT:MUX.HEX_V6[1][5]	INT:MUX.HEX_V6[1][3]	INT:MUX.HEX_V0[1][0]	INT:MUX.HEX_V0[1][5]	INT:MUX.HEX_V0[1][6]	INT:MUX.HEX_V0[1][4]	INT:MUX.HEX_V0[1][2]	INT:MUX.HEX_V0[1][3]	INT:MUX.HEX_V6[1][1]	INT:MUX.HEX_V6[1][6]	INT:DRIVE.HEX_V6[1]	INT:DRIVE.HEX_V0[0]	INT:MUX.HEX_V6[0][5]	INT:MUX.HEX_V6[0][3]	INT:MUX.HEX_V0[0][0]	INT:MUX.HEX_V0[0][5]	INT:MUX.HEX_V0[0][6]	INT:MUX.HEX_V0[0][4]	INT:MUX.HEX_V0[0][2]	INT:MUX.HEX_V0[0][3]	INT:MUX.HEX_V6[0][1]	INT:MUX.HEX_V6[0][6]	INT:DRIVE.HEX_V6[0]
B5	INT:MUX.HEX_V6[3][2]	INT:MUX.HEX_V0[3][1]	-	-	-	-	-	-	-	-	INT:MUX.HEX_V6[3][4]	INT:MUX.HEX_V6[3][0]	INT:MUX.HEX_V6[2][2]	INT:MUX.HEX_V0[2][1]	-	-	-	-	-	-	-	-	INT:MUX.HEX_V6[2][4]	INT:MUX.HEX_V6[2][0]	INT:MUX.HEX_V6[1][2]	INT:MUX.HEX_V0[1][1]	-	-	-	-	-	-	-	-	INT:MUX.HEX_V6[1][4]	INT:MUX.HEX_V6[1][0]	INT:MUX.HEX_V6[0][2]	INT:MUX.HEX_V0[0][1]	-	-	-	-	-	-	-	-	INT:MUX.HEX_V6[0][4]	INT:MUX.HEX_V6[0][0]
B4	INT:DRIVE.HEX_H0[3]	INT:MUX.HEX_H1[3][3]	INT:MUX.HEX_H0[3][1]	INT:DRIVE.HEX_H1[3]	INT:DRIVE.HEX_H2[3]	-	-	INT:DRIVE.HEX_H3[3]	INT:DRIVE.HEX_H4[3]	-	-	INT:DRIVE.HEX_H5[3]	INT:DRIVE.HEX_H5[2]	-	-	INT:DRIVE.HEX_H4[2]	INT:DRIVE.HEX_H3[2]	-	-	INT:DRIVE.HEX_H2[2]	INT:DRIVE.HEX_H1[2]	INT:MUX.HEX_H0[2][3]	INT:MUX.HEX_H1[2][2]	INT:DRIVE.HEX_H0[2]	INT:DRIVE.HEX_H0[1]	INT:MUX.HEX_H1[1][2]	INT:MUX.HEX_H0[1][3]	INT:DRIVE.HEX_H1[1]	INT:DRIVE.HEX_H2[1]	-	-	INT:DRIVE.HEX_H3[1]	INT:DRIVE.HEX_H4[1]	-	-	INT:DRIVE.HEX_H5[1]	INT:DRIVE.HEX_H5[0]	-	-	INT:DRIVE.HEX_H4[0]	INT:DRIVE.HEX_H3[0]	-	-	INT:DRIVE.HEX_H2[0]	INT:DRIVE.HEX_H1[0]	INT:MUX.HEX_H0[0][2]	INT:MUX.HEX_H1[0][1]	INT:DRIVE.HEX_H0[0]
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	INT:MUX.HEX_H0[3][0]	INT:MUX.HEX_H0[3][5]	INT:MUX.HEX_H0[3][4]	INT:MUX.HEX_H1[3][0]	INT:MUX.HEX_H2[3][2]	INT:MUX.HEX_H3[3][2]	INT:MUX.HEX_H3[3][1]	INT:MUX.HEX_H3[3][0]	INT:MUX.HEX_H4[3][2]	INT:MUX.HEX_H5[3][2]	-	INT:MUX.HEX_H5[3][0]	INT:MUX.HEX_H5[2][0]	INT:MUX.HEX_H5[2][1]	-	-	INT:MUX.HEX_H3[2][0]	INT:MUX.HEX_H3[2][1]	INT:MUX.HEX_H3[2][3]	INT:MUX.HEX_H2[2][3]	INT:MUX.HEX_H1[2][0]	-	INT:MUX.HEX_H0[2][4]	INT:MUX.HEX_H0[2][0]	INT:MUX.HEX_H0[1][0]	INT:MUX.HEX_H0[1][5]	INT:MUX.HEX_H0[1][4]	INT:MUX.HEX_H1[1][0]	INT:MUX.HEX_H2[1][1]	INT:MUX.HEX_H3[1][1]	INT:MUX.HEX_H3[1][2]	INT:MUX.HEX_H3[1][0]	INT:MUX.HEX_H4[1][2]	INT:MUX.HEX_H5[1][2]	-	INT:MUX.HEX_H5[1][0]	INT:MUX.HEX_H5[0][0]	INT:MUX.HEX_H5[0][1]	-	-	INT:MUX.HEX_H3[0][0]	INT:MUX.HEX_H3[0][1]	INT:MUX.HEX_H3[0][3]	INT:MUX.HEX_H2[0][3]	INT:MUX.HEX_H1[0][0]	-	INT:MUX.HEX_H0[0][4]	INT:MUX.HEX_H0[0][0]
B1	INT:MUX.HEX_E0[3][3]	INT:MUX.HEX_E0[3][0]	INT:MUX.HEX_E1[3][0]	INT:MUX.HEX_E1[3][1]	INT:MUX.HEX_E0[3][1]	INT:MUX.HEX_E0[3][2]	INT:MUX.HEX_E1[3][2]	INT:MUX.HEX_E1[3][5]	INT:MUX.HEX_E0[3][5]	INT:MUX.HEX_E0[3][4]	INT:MUX.HEX_E1[3][4]	INT:MUX.HEX_E1[3][3]	INT:MUX.HEX_E0[1][3]	INT:MUX.HEX_E0[1][1]	INT:MUX.HEX_E1[1][1]	INT:MUX.HEX_E1[1][2]	INT:MUX.HEX_E0[1][2]	INT:MUX.HEX_E0[1][0]	INT:MUX.HEX_E1[1][0]	INT:MUX.HEX_E1[1][5]	INT:MUX.HEX_E0[1][5]	INT:MUX.HEX_E0[1][4]	INT:MUX.HEX_E1[1][4]	INT:MUX.HEX_E1[1][3]	INT:MUX.HEX_E0[2][3]	INT:MUX.HEX_E0[2][2]	INT:MUX.HEX_E1[2][2]	INT:MUX.HEX_E1[2][0]	INT:MUX.HEX_E0[2][0]	INT:MUX.HEX_E0[2][1]	INT:MUX.HEX_E1[2][1]	INT:MUX.HEX_E1[2][5]	INT:MUX.HEX_E0[2][5]	INT:MUX.HEX_E0[2][4]	INT:MUX.HEX_E1[2][4]	INT:MUX.HEX_E1[2][3]	INT:MUX.HEX_E0[0][3]	INT:MUX.HEX_E0[0][0]	INT:MUX.HEX_E1[0][0]	INT:MUX.HEX_E1[0][1]	INT:MUX.HEX_E0[0][1]	INT:MUX.HEX_E0[0][2]	INT:MUX.HEX_E1[0][2]	-	-	-	-	INT:MUX.HEX_E1[0][3]
B0	INT:MUX.HEX_H0[3][3]	INT:MUX.HEX_H0[3][2]	INT:MUX.HEX_H1[3][2]	INT:MUX.HEX_H1[3][1]	INT:MUX.HEX_H2[3][0]	-	-	INT:MUX.HEX_H2[3][1]	INT:MUX.HEX_H4[3][0]	INT:MUX.HEX_H5[3][1]	INT:MUX.HEX_H4[3][1]	-	INT:MUX.HEX_H4[2][1]	INT:MUX.HEX_H4[2][2]	INT:MUX.HEX_H5[2][2]	INT:MUX.HEX_H4[2][0]	INT:MUX.HEX_H2[2][1]	INT:MUX.HEX_H2[2][2]	INT:MUX.HEX_H3[2][2]	INT:MUX.HEX_H2[2][0]	INT:MUX.HEX_H1[2][1]	-	INT:MUX.HEX_H0[2][1]	INT:MUX.HEX_H0[2][2]	INT:MUX.HEX_H0[1][2]	INT:MUX.HEX_H0[1][1]	INT:MUX.HEX_H1[1][1]	-	INT:MUX.HEX_H2[1][0]	-	-	INT:MUX.HEX_H2[1][2]	INT:MUX.HEX_H4[1][0]	INT:MUX.HEX_H5[1][1]	INT:MUX.HEX_H4[1][1]	-	INT:MUX.HEX_H4[0][1]	INT:MUX.HEX_H4[0][2]	INT:MUX.HEX_H5[0][2]	INT:MUX.HEX_H4[0][0]	INT:MUX.HEX_H2[0][1]	INT:MUX.HEX_H2[0][2]	INT:MUX.HEX_H3[0][2]	INT:MUX.HEX_H2[0][0]	INT:MUX.HEX_H1[0][2]	-	INT:MUX.HEX_H0[0][3]	INT:MUX.HEX_H0[0][1]

INT:DRIVE.HEX_H0[0]	0.F47.B4
INT:DRIVE.HEX_H0[1]	0.F24.B4
INT:DRIVE.HEX_H0[2]	0.F23.B4
INT:DRIVE.HEX_H0[3]	0.F0.B4
INT:DRIVE.HEX_H1[0]	0.F44.B4
INT:DRIVE.HEX_H1[1]	0.F27.B4
INT:DRIVE.HEX_H1[2]	0.F20.B4
INT:DRIVE.HEX_H1[3]	0.F3.B4
INT:DRIVE.HEX_H2[0]	0.F43.B4
INT:DRIVE.HEX_H2[1]	0.F28.B4
INT:DRIVE.HEX_H2[2]	0.F19.B4
INT:DRIVE.HEX_H2[3]	0.F4.B4
INT:DRIVE.HEX_H3[0]	0.F40.B4
INT:DRIVE.HEX_H3[1]	0.F31.B4
INT:DRIVE.HEX_H3[2]	0.F16.B4
INT:DRIVE.HEX_H3[3]	0.F7.B4
INT:DRIVE.HEX_H4[0]	0.F39.B4
INT:DRIVE.HEX_H4[1]	0.F32.B4
INT:DRIVE.HEX_H4[2]	0.F15.B4
INT:DRIVE.HEX_H4[3]	0.F8.B4
INT:DRIVE.HEX_H5[0]	0.F36.B4
INT:DRIVE.HEX_H5[1]	0.F35.B4
INT:DRIVE.HEX_H5[2]	0.F12.B4
INT:DRIVE.HEX_H5[3]	0.F11.B4
INT:DRIVE.HEX_V0[0]	0.F36.B6
INT:DRIVE.HEX_V0[1]	0.F24.B6
INT:DRIVE.HEX_V0[2]	0.F12.B6
INT:DRIVE.HEX_V0[3]	0.F0.B6
INT:DRIVE.HEX_V6[0]	0.F47.B6
INT:DRIVE.HEX_V6[1]	0.F35.B6
INT:DRIVE.HEX_V6[2]	0.F23.B6
INT:DRIVE.HEX_V6[3]	0.F11.B6
INT:DRIVE.LH[0]	0.F26.B12
INT:DRIVE.LH[10]	0.F42.B12
INT:DRIVE.LH[11]	0.F45.B12
INT:DRIVE.LH[1]	0.F21.B12
INT:DRIVE.LH[2]	0.F18.B12
INT:DRIVE.LH[3]	0.F13.B12
INT:DRIVE.LH[4]	0.F10.B12
INT:DRIVE.LH[5]	0.F5.B12
INT:DRIVE.LH[6]	0.F2.B12
INT:DRIVE.LH[7]	0.F29.B12
INT:DRIVE.LH[8]	0.F34.B12
INT:DRIVE.LH[9]	0.F37.B12
INT:DRIVE.LV[0]	0.F2.B15
INT:DRIVE.LV[6]	0.F10.B15
INT:INV.IMUX_IO_SR[1]	0.F33.B10
INT:INV.IMUX_IO_SR[2]	0.F34.B9
INT:INV.IMUX_IO_SR[3]	0.F37.B9
INT:INV.IMUX_TBUF_T[0]	0.F25.B15
INT:INV.IMUX_TBUF_T[1]	0.F31.B15
INT:PASS.SINGLE_E[0].HEX_V6[0]	0.F47.B7
INT:PASS.SINGLE_E[0].OUT_IO_I[3]	0.F46.B8
INT:PASS.SINGLE_E[0].OUT_TBUF_W[3]	0.F47.B8
INT:PASS.SINGLE_E[10].HEX_V3[1]	0.F25.B8
INT:PASS.SINGLE_E[10].OUT_IO_I[1]	0.F26.B8
INT:PASS.SINGLE_E[11].HEX_V0[1]	0.F24.B8
INT:PASS.SINGLE_E[12].HEX_V6[2]	0.F23.B7
INT:PASS.SINGLE_E[12].OUT_IO_IQ[3]	0.F22.B8
INT:PASS.SINGLE_E[12].OUT_TBUF_W[1]	0.F23.B8
INT:PASS.SINGLE_E[13].HEX_V3[2]	0.F21.B8
INT:PASS.SINGLE_E[13].OUT_IO_IQ[2]	0.F20.B8
INT:PASS.SINGLE_E[14].HEX_V0[2]	0.F19.B8
INT:PASS.SINGLE_E[14].OUT_IO_IQ[1]	0.F18.B8
INT:PASS.SINGLE_E[15].HEX_V6[2]	0.F15.B8
INT:PASS.SINGLE_E[15].OUT_TBUF_W[1]	0.F17.B8
INT:PASS.SINGLE_E[16].HEX_V3[2]	0.F13.B8
INT:PASS.SINGLE_E[16].OUT_IO_I[3]	0.F14.B8
INT:PASS.SINGLE_E[17].HEX_V0[2]	0.F12.B8
INT:PASS.SINGLE_E[17].OUT_IO_I[2]	0.F12.B7
INT:PASS.SINGLE_E[18].HEX_V6[3]	0.F11.B7
INT:PASS.SINGLE_E[18].OUT_IO_I[1]	0.F10.B8
INT:PASS.SINGLE_E[18].OUT_TBUF_W[0]	0.F11.B8
INT:PASS.SINGLE_E[19].HEX_V3[3]	0.F9.B8
INT:PASS.SINGLE_E[1].HEX_V3[0]	0.F45.B8
INT:PASS.SINGLE_E[1].OUT_IO_I[2]	0.F44.B8
INT:PASS.SINGLE_E[20].HEX_V0[3]	0.F7.B8
INT:PASS.SINGLE_E[20].OUT_IO_IQ[3]	0.F6.B8
INT:PASS.SINGLE_E[21].HEX_V6[3]	0.F3.B8
INT:PASS.SINGLE_E[21].OUT_IO_IQ[2]	0.F4.B8
INT:PASS.SINGLE_E[21].OUT_TBUF_W[0]	0.F5.B8
INT:PASS.SINGLE_E[22].HEX_V3[3]	0.F1.B8
INT:PASS.SINGLE_E[22].OUT_IO_IQ[1]	0.F2.B8
INT:PASS.SINGLE_E[23].HEX_V0[3]	0.F0.B8
INT:PASS.SINGLE_E[2].HEX_V0[0]	0.F43.B8
INT:PASS.SINGLE_E[2].OUT_IO_I[1]	0.F42.B8
INT:PASS.SINGLE_E[3].HEX_V6[0]	0.F39.B8
INT:PASS.SINGLE_E[3].OUT_TBUF_W[3]	0.F41.B8
INT:PASS.SINGLE_E[4].HEX_V3[0]	0.F37.B8
INT:PASS.SINGLE_E[4].OUT_IO_IQ[3]	0.F38.B8
INT:PASS.SINGLE_E[5].HEX_V0[0]	0.F36.B8
INT:PASS.SINGLE_E[5].OUT_IO_IQ[2]	0.F36.B7
INT:PASS.SINGLE_E[6].HEX_V6[1]	0.F35.B7
INT:PASS.SINGLE_E[6].OUT_IO_IQ[1]	0.F34.B8
INT:PASS.SINGLE_E[6].OUT_TBUF_W[2]	0.F35.B8
INT:PASS.SINGLE_E[7].HEX_V3[1]	0.F33.B8
INT:PASS.SINGLE_E[8].HEX_V0[1]	0.F31.B8
INT:PASS.SINGLE_E[8].OUT_IO_I[3]	0.F30.B8
INT:PASS.SINGLE_E[9].HEX_V6[1]	0.F27.B8
INT:PASS.SINGLE_E[9].OUT_IO_I[2]	0.F28.B8
INT:PASS.SINGLE_E[9].OUT_TBUF_W[2]	0.F29.B8
IO[1]:IFF_DELAY_ENABLE	0.F38.B17
IO[1]:IFF_INIT	0.F46.B16
IO[1]:IFF_LATCH	0.F44.B16
IO[1]:IFF_SR_ENABLE	0.F43.B16
IO[1]:IFF_SR_SYNC	0.F47.B16
IO[1]:INV.IFF.CLK	0.F34.B14
IO[1]:INV.OFF.CLK	0.F33.B14
IO[1]:INV.TFF.CLK	0.F32.B14
IO[1]:I_DELAY_ENABLE	0.F45.B16
IO[1]:OFF_LATCH	0.F41.B16
IO[1]:OFF_SR_ENABLE	0.F42.B16
IO[1]:OFF_SR_SYNC	0.F38.B16
IO[1]:READBACK_IFF	0.F45.B17
IO[1]:READBACK_OFF	0.F39.B17
IO[1]:READBACK_TFF	0.F35.B17
IO[1]:TFF_LATCH	0.F34.B16
IO[1]:TFF_SR_ENABLE	0.F33.B16
IO[1]:TFF_SR_SYNC	0.F37.B16
IO[2]:IFF_DELAY_ENABLE	0.F27.B17
IO[2]:IFF_INIT	0.F19.B16
IO[2]:IFF_LATCH	0.F21.B16
IO[2]:IFF_SR_ENABLE	0.F22.B16
IO[2]:IFF_SR_SYNC	0.F18.B16
IO[2]:INV.IFF.CLK	0.F13.B14
IO[2]:INV.OFF.CLK	0.F14.B14
IO[2]:INV.TFF.CLK	0.F15.B14
IO[2]:I_DELAY_ENABLE	0.F20.B16
IO[2]:OFF_LATCH	0.F24.B16
IO[2]:OFF_SR_ENABLE	0.F23.B16
IO[2]:OFF_SR_SYNC	0.F27.B16
IO[2]:READBACK_IFF	0.F20.B17
IO[2]:READBACK_OFF	0.F26.B17
IO[2]:READBACK_TFF	0.F30.B17
IO[2]:TFF_LATCH	0.F31.B16
IO[2]:TFF_SR_ENABLE	0.F32.B16
IO[2]:TFF_SR_SYNC	0.F28.B16
IO[3]:IFF_DELAY_ENABLE	0.F8.B17
IO[3]:IFF_INIT	0.F16.B16
IO[3]:IFF_LATCH	0.F14.B16
IO[3]:IFF_SR_ENABLE	0.F13.B16
IO[3]:IFF_SR_SYNC	0.F17.B16
IO[3]:INV.IFF.CLK	0.F10.B14
IO[3]:INV.OFF.CLK	0.F11.B14
IO[3]:INV.TFF.CLK	0.F12.B14
IO[3]:I_DELAY_ENABLE	0.F15.B16
IO[3]:OFF_LATCH	0.F11.B16
IO[3]:OFF_SR_ENABLE	0.F12.B16
IO[3]:OFF_SR_SYNC	0.F8.B16
IO[3]:READBACK_IFF	0.F15.B17
IO[3]:READBACK_OFF	0.F9.B17
IO[3]:READBACK_TFF	0.F5.B17
IO[3]:TFF_LATCH	0.F4.B16
IO[3]:TFF_SR_ENABLE	0.F3.B16
IO[3]:TFF_SR_SYNC	0.F7.B16
non-inverted	[0]

INT:INV.IMUX_IO_ICE[1]	0.F5.B10
INT:INV.IMUX_IO_ICE[2]	0.F4.B10
INT:INV.IMUX_IO_ICE[3]	0.F3.B9
INT:INV.IMUX_IO_OCE[1]	0.F14.B10
INT:INV.IMUX_IO_OCE[2]	0.F13.B9
INT:INV.IMUX_IO_OCE[3]	0.F10.B9
INT:INV.IMUX_IO_O[1]	0.F38.B14
INT:INV.IMUX_IO_O[2]	0.F9.B14
INT:INV.IMUX_IO_O[3]	0.F0.B14
INT:INV.IMUX_IO_TCE[1]	0.F25.B10
INT:INV.IMUX_IO_TCE[2]	0.F23.B9
INT:INV.IMUX_IO_TCE[3]	0.F22.B10
INT:INV.IMUX_IO_T[1]	0.F42.B10
INT:INV.IMUX_IO_T[2]	0.F43.B10
INT:INV.IMUX_IO_T[3]	0.F44.B9
INT:INV.IMUX_TBUF_I[0]	0.F18.B15
INT:INV.IMUX_TBUF_I[1]	0.F23.B15
IO[1]:OFF_INIT	0.F39.B16
IO[1]:SHORTEN_JTAG_CHAIN	0.F37.B17
IO[1]:TFF_INIT	0.F36.B16
IO[2]:OFF_INIT	0.F26.B16
IO[2]:SHORTEN_JTAG_CHAIN	0.F28.B17
IO[2]:TFF_INIT	0.F29.B16
IO[3]:OFF_INIT	0.F9.B16
IO[3]:SHORTEN_JTAG_CHAIN	0.F7.B17
IO[3]:TFF_INIT	0.F6.B16
TBUF[0]:OUT_A	0.F46.B12
TBUF[0]:OUT_B	0.F46.B15
TBUF[1]:OUT_A	0.F45.B15
TBUF[1]:OUT_B	0.F38.B12
TBUS:JOINER	0.F44.B15
TBUS:JOINER_E	0.F47.B15
inverted	~[0]

INT:MUX.HEX_E0[0]	0.F36.B1	0.F41.B1	0.F40.B1	0.F37.B1
HEX_W1[0]	0	1	1	1
HEX_V0[2]	1	0	1	1
HEX_V3[1]	1	1	0	1
HEX_V6[0]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_E0[1]	0.F20.B1	0.F21.B1	0.F12.B1	0.F16.B1	0.F13.B1	0.F17.B1
HEX_W1[1]	0	0	0	1	1	1
HEX_V0[1]	0	0	1	0	1	1
HEX_V3[0]	0	0	1	1	0	1
HEX_V6[3]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[1]	0	1	1	1	1	1
OUT_IO_IQ[1]	1	0	1	1	1	1

INT:MUX.HEX_E0[2]	0.F32.B1	0.F33.B1	0.F24.B1	0.F25.B1	0.F29.B1	0.F28.B1
HEX_W1[2]	0	0	0	1	1	1
HEX_V0[0]	0	0	1	0	1	1
HEX_V3[3]	0	0	1	1	0	1
HEX_V6[2]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_IQ[2]	1	0	1	1	1	1

INT:MUX.HEX_E0[3]	0.F8.B1	0.F9.B1	0.F0.B1	0.F5.B1	0.F4.B1	0.F1.B1
HEX_W1[3]	0	0	0	1	1	1
HEX_V0[3]	0	0	1	0	1	1
HEX_V3[2]	0	0	1	1	0	1
HEX_V6[1]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[3]	0	1	1	1	1	1
OUT_IO_IQ[3]	1	0	1	1	1	1

INT:MUX.HEX_E1[0]	0.F47.B1	0.F42.B1	0.F39.B1	0.F38.B1
HEX_W2[0]	0	1	1	1
HEX_V0[2]	1	0	1	1
HEX_V3[1]	1	1	0	1
HEX_V6[0]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_E1[1]	0.F19.B1	0.F22.B1	0.F23.B1	0.F15.B1	0.F14.B1	0.F18.B1
HEX_W2[1]	0	0	0	1	1	1
HEX_V0[1]	0	0	1	0	1	1
HEX_V3[0]	0	0	1	1	0	1
HEX_V6[3]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[1]	0	1	1	1	1	1
OUT_IO_IQ[1]	1	0	1	1	1	1

INT:MUX.HEX_E1[2]	0.F31.B1	0.F34.B1	0.F35.B1	0.F26.B1	0.F30.B1	0.F27.B1
HEX_W2[2]	0	0	0	1	1	1
HEX_V0[0]	0	0	1	0	1	1
HEX_V3[3]	0	0	1	1	0	1
HEX_V6[2]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_IQ[2]	1	0	1	1	1	1

INT:MUX.HEX_E1[3]	0.F7.B1	0.F10.B1	0.F11.B1	0.F6.B1	0.F3.B1	0.F2.B1
HEX_W2[3]	0	0	0	1	1	1
HEX_V0[3]	0	0	1	0	1	1
HEX_V3[2]	0	0	1	1	0	1
HEX_V6[1]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[3]	0	1	1	1	1	1
OUT_IO_IQ[3]	1	0	1	1	1	1

INT:MUX.HEX_H0[0]	0.F46.B2	0.F46.B0	0.F45.B4	0.F47.B0	0.F47.B2
HEX_V0[1]	0	0	1	1	1
HEX_V3[3]	0	1	0	1	1
HEX_V6[0]	0	1	1	0	1
LH[0]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_I[1]	1	1	1	1	1

INT:MUX.HEX_H0[1]	0.F25.B2	0.F26.B2	0.F26.B4	0.F24.B0	0.F25.B0	0.F24.B2
HEX_V0[2]	0	0	0	1	1	1
HEX_V3[0]	0	0	1	0	1	1
HEX_V6[1]	0	0	1	1	0	1
LH[0]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_I[3]	1	0	1	1	1	1

INT:MUX.HEX_H0[2]	0.F22.B2	0.F21.B4	0.F23.B0	0.F22.B0	0.F23.B2
HEX_V0[3]	0	0	1	1	1
HEX_V3[1]	0	1	0	1	1
HEX_V6[2]	0	1	1	0	1
LH[6]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_IQ[1]	1	1	1	1	1

INT:MUX.HEX_H0[3]	0.F1.B2	0.F2.B2	0.F0.B0	0.F1.B0	0.F2.B4	0.F0.B2
HEX_V0[0]	0	0	0	1	1	1
HEX_V3[2]	0	0	1	0	1	1
HEX_V6[3]	0	0	1	1	0	1
LH[6]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_IQ[2]	0	1	1	1	1	1
OUT_IO_IQ[3]	1	0	1	1	1	1

INT:MUX.HEX_H1[0]	0.F44.B0	0.F46.B4	0.F44.B2
LH[11]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_H1[1]	0.F25.B4	0.F26.B0	0.F27.B2
LH[11]	0	0	0
NONE	0	0	1
OUT_IO_I[2]	0	1	1
OUT_IO_I[3]	1	0	1

INT:MUX.HEX_H1[2]	0.F22.B4	0.F20.B0	0.F20.B2
LH[5]	0	0	0
NONE	0	0	1
OUT_IO_I[3]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_H1[3]	0.F1.B4	0.F2.B0	0.F3.B0	0.F3.B2
LH[5]	0	0	0	0
NONE	0	0	0	1
OUT_IO_I[2]	0	0	1	1
OUT_IO_IQ[2]	0	1	0	1
OUT_IO_IQ[3]	1	0	0	1

INT:MUX.HEX_H2[0]	0.F43.B2	0.F41.B0	0.F40.B0	0.F43.B0
LH[10]	0	0	0	0
NONE	0	0	0	1
OUT_IO_IQ[1]	0	0	1	1
OUT_IO_IQ[2]	0	1	0	1
OUT_IO_IQ[3]	1	0	0	1

INT:MUX.HEX_H2[1]	0.F31.B0	0.F28.B2	0.F28.B0
LH[10]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_IQ[3]	1	0	1

INT:MUX.HEX_H2[2]	0.F19.B2	0.F17.B0	0.F16.B0	0.F19.B0
LH[4]	0	0	0	0
NONE	0	0	0	1
OUT_IO_I[1]	0	0	1	1
OUT_IO_I[2]	0	1	0	1
OUT_IO_I[3]	1	0	0	1

INT:MUX.HEX_H2[3]	0.F4.B2	0.F7.B0	0.F4.B0
LH[4]	0	0	0
NONE	0	0	1
OUT_IO_I[3]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_H3[0]	0.F42.B2	0.F42.B0	0.F41.B2	0.F40.B2
LH[9]	0	0	0	0
NONE	0	0	0	1
OUT_IO_IQ[1]	0	0	1	1
OUT_IO_IQ[2]	0	1	0	1
OUT_IO_IQ[3]	1	0	0	1

INT:MUX.HEX_H3[1]	0.F30.B2	0.F29.B2	0.F31.B2
LH[9]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_IQ[3]	1	0	1

INT:MUX.HEX_H3[2]	0.F18.B2	0.F18.B0	0.F17.B2	0.F16.B2
LH[3]	0	0	0	0
NONE	0	0	0	1
OUT_IO_I[1]	0	0	1	1
OUT_IO_I[2]	0	1	0	1
OUT_IO_I[3]	1	0	0	1

INT:MUX.HEX_H3[3]	0.F5.B2	0.F6.B2	0.F7.B2
LH[3]	0	0	0
NONE	0	0	1
OUT_IO_I[3]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_H4[0]	0.F37.B0	0.F36.B0	0.F39.B0
LH[8]	0	0	0
NONE	0	0	1
OUT_IO_I[2]	0	1	1
OUT_IO_I[3]	1	0	1

INT:MUX.HEX_H4[1]	0.F32.B2	0.F34.B0	0.F32.B0
LH[8]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_H4[2]	0.F13.B0	0.F12.B0	0.F15.B0
LH[2]	0	0	0
NONE	0	0	1
OUT_IO_IQ[2]	0	1	1
OUT_IO_IQ[3]	1	0	1

INT:MUX.HEX_H4[3]	0.F8.B2	0.F10.B0	0.F8.B0
LH[2]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_H5[0]	0.F38.B0	0.F37.B2	0.F36.B2
LH[7]	0	0	0
NONE	0	0	1
OUT_IO_I[2]	0	1	1
OUT_IO_I[3]	1	0	1

INT:MUX.HEX_H5[1]	0.F33.B2	0.F33.B0	0.F35.B2
LH[7]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_H5[2]	0.F14.B0	0.F13.B2	0.F12.B2
LH[1]	0	0	0
NONE	0	0	1
OUT_IO_IQ[2]	0	1	1
OUT_IO_IQ[3]	1	0	1

INT:MUX.HEX_H5[3]	0.F9.B2	0.F9.B0	0.F11.B2
LH[1]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_V0[0]	0.F41.B6	0.F40.B6	0.F42.B6	0.F44.B6	0.F43.B6	0.F37.B5	0.F39.B6
HEX_H0[3]	0	0	0	0	0	0	1
HEX_H3[2]	0	0	0	0	0	1	0
HEX_V6[0]	0	0	0	0	1	0	0
LV[0]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V0[1]	0.F29.B6	0.F28.B6	0.F30.B6	0.F32.B6	0.F31.B6	0.F25.B5	0.F27.B6
HEX_H0[0]	0	0	0	0	0	0	1
HEX_H3[3]	0	0	0	0	0	1	0
HEX_V6[1]	0	0	0	0	1	0	0
LV[0]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V0[2]	0.F17.B6	0.F16.B6	0.F18.B6	0.F20.B6	0.F19.B6	0.F13.B5	0.F15.B6
HEX_H0[1]	0	0	0	0	0	0	1
HEX_H3[0]	0	0	0	0	0	1	0
HEX_V6[2]	0	0	0	0	1	0	0
LV[6]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V0[3]	0.F5.B6	0.F4.B6	0.F6.B6	0.F8.B6	0.F7.B6	0.F1.B5	0.F3.B6
HEX_H0[2]	0	0	0	0	0	0	1
HEX_H3[1]	0	0	0	0	0	1	0
HEX_V6[3]	0	0	0	0	1	0	0
LV[6]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V6[0]	0.F46.B6	0.F37.B6	0.F46.B5	0.F38.B6	0.F36.B5	0.F45.B6	0.F47.B5
HEX_H0[0]	0	0	0	0	0	0	1
HEX_H3[2]	0	0	0	0	0	1	0
HEX_V0[0]	0	0	0	0	1	0	0
LV[0]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V6[1]	0.F34.B6	0.F25.B6	0.F34.B5	0.F26.B6	0.F24.B5	0.F33.B6	0.F35.B5
HEX_H0[1]	0	0	0	0	0	0	1
HEX_H3[3]	0	0	0	0	0	1	0
HEX_V0[1]	0	0	0	0	1	0	0
LV[0]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V6[2]	0.F22.B6	0.F13.B6	0.F22.B5	0.F14.B6	0.F12.B5	0.F21.B6	0.F23.B5
HEX_H0[2]	0	0	0	0	0	0	1
HEX_H3[0]	0	0	0	0	0	1	0
HEX_V0[2]	0	0	0	0	1	0	0
LV[6]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V6[3]	0.F10.B6	0.F1.B6	0.F10.B5	0.F2.B6	0.F0.B5	0.F9.B6	0.F11.B5
HEX_H0[3]	0	0	0	0	0	0	1
HEX_H3[1]	0	0	0	0	0	1	0
HEX_V0[3]	0	0	0	0	1	0	0
LV[6]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.IMUX_IO_CLK[0]	0.F30.B12	0.F30.B14	0.F29.B14	0.F36.B13	0.F26.B14	0.F30.B13	0.F24.B13	0.F25.B14	0.F25.B13	0.F27.B13	0.F27.B14
INT:MUX.IMUX_IO_CLK[1]	0.F28.B14	0.F31.B14	0.F28.B13	0.F33.B13	0.F25.B12	0.F24.B14	0.F31.B13	0.F34.B13	0.F26.B13	0.F32.B13	0.F29.B13
INT:MUX.IMUX_IO_CLK[2]	0.F19.B14	0.F16.B14	0.F19.B13	0.F14.B13	0.F22.B12	0.F23.B14	0.F16.B13	0.F13.B13	0.F21.B13	0.F15.B13	0.F18.B13
INT:MUX.IMUX_IO_CLK[3]	0.F17.B12	0.F17.B14	0.F18.B14	0.F11.B13	0.F21.B14	0.F17.B13	0.F23.B13	0.F22.B14	0.F22.B13	0.F20.B13	0.F20.B14
GCLK[0]	0	0	0	0	0	0	1	1	1	1	1
GCLK[1]	0	0	0	0	0	1	0	1	1	1	1
GCLK[2]	0	0	0	0	0	1	1	0	1	1	1
GCLK[3]	0	0	0	0	0	1	1	1	0	1	1
NONE	0	0	0	0	0	1	1	1	1	1	1
HEX_V5_BUF[2]	0	0	0	1	0	1	1	1	1	1	0
SINGLE_E_BUF[8]	0	0	0	1	1	1	1	1	1	1	1
HEX_V1_BUF[2]	0	0	1	0	0	1	1	1	1	0	1
HEX_V4_BUF[2]	0	0	1	0	0	1	1	1	1	1	0
SINGLE_E_BUF[9]	0	0	1	0	1	1	1	1	1	1	1
HEX_V6_BUF[2]	0	1	0	0	0	1	1	1	1	1	0
SINGLE_E_BUF[14]	0	1	0	0	1	1	1	1	1	1	1
HEX_V2_BUF[2]	1	0	0	0	0	1	1	1	1	0	1
HEX_V3_BUF[2]	1	0	0	0	0	1	1	1	1	1	0
SINGLE_E_BUF[15]	1	0	0	0	1	1	1	1	1	1	1

INT:MUX.IMUX_IO_ICE[0]	0.F8.B10	0.F7.B10	0.F5.B11	0.F6.B11	0.F7.B9	0.F6.B10
INT:MUX.IMUX_IO_ICE[1]	0.F7.B11	0.F8.B11	0.F9.B11	0.F4.B9	0.F5.B9	0.F9.B10
INT:MUX.IMUX_IO_ICE[2]	0.F2.B11	0.F1.B11	0.F0.B11	0.F0.B9	0.F1.B9	0.F0.B10
INT:MUX.IMUX_IO_ICE[3]	0.F1.B10	0.F2.B10	0.F3.B11	0.F4.B11	0.F2.B9	0.F3.B10
NONE	0	0	0	0	0	0
SINGLE_E_BUF[20]	0	0	0	0	0	1
SINGLE_E_BUF[21]	0	0	0	0	1	0
SINGLE_E_BUF[22]	0	0	0	1	0	0
SINGLE_E_BUF[23]	0	0	1	0	0	0
HEX_V4_BUF[3]	0	1	0	1	0	0
HEX_V1_BUF[3]	0	1	1	0	0	0
HEX_V6_BUF[3]	1	1	0	0	0	1
HEX_V5_BUF[3]	1	1	0	0	1	0
HEX_V3_BUF[3]	1	1	0	1	0	0
HEX_V2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_OCE[0]	0.F18.B10	0.F17.B10	0.F14.B11	0.F15.B11	0.F16.B10	0.F14.B9
INT:MUX.IMUX_IO_OCE[1]	0.F17.B11	0.F18.B11	0.F19.B11	0.F16.B9	0.F19.B9	0.F15.B9
INT:MUX.IMUX_IO_OCE[2]	0.F12.B11	0.F11.B11	0.F10.B11	0.F11.B9	0.F10.B10	0.F9.B9
INT:MUX.IMUX_IO_OCE[3]	0.F11.B10	0.F12.B10	0.F13.B11	0.F8.B9	0.F13.B10	0.F12.B9
NONE	0	0	0	0	0	0
SINGLE_E_BUF[17]	0	0	0	0	0	1
SINGLE_E_BUF[16]	0	0	0	0	1	0
SINGLE_E_BUF[18]	0	0	0	1	0	0
SINGLE_E_BUF[19]	0	0	1	0	0	0
PCI_CE	0	1	0	0	0	1
HEX_V4_BUF[3]	0	1	0	1	0	0
HEX_V1_BUF[3]	0	1	1	0	0	0
HEX_V5_BUF[3]	1	1	0	0	0	1
HEX_V6_BUF[3]	1	1	0	0	1	0
HEX_V3_BUF[3]	1	1	0	1	0	0
HEX_V2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_O[0]	0.F41.B13	0.F42.B13	0.F47.B13	0.F46.B13	0.F45.B14	0.F44.B13	0.F43.B13	0.F44.B14	0.F45.B13	0.F46.B14
NONE	0	0	0	0	0	0	0	0	1	1
HEX_H0_BUF[0]	0	0	0	0	0	0	1	0	0	1
OMUX_W7	0	0	0	0	0	0	1	0	1	0
SINGLE_E_BUF[0]	0	0	0	0	0	0	1	1	1	1
HEX_H3_BUF[0]	0	0	0	0	0	1	0	0	0	1
OMUX_W6	0	0	0	0	0	1	0	0	1	0
SINGLE_E_BUF[1]	0	0	0	0	0	1	0	1	1	1
SINGLE_E_BUF[3]	0	0	0	0	1	0	1	0	1	1
SINGLE_E_BUF[2]	0	0	0	0	1	1	0	0	1	1
HEX_H1_BUF[0]	0	0	0	1	0	0	0	0	0	1
OUT_TBUF_W[2]	0	0	0	1	0	0	0	0	1	0
SINGLE_E_BUF[9]	0	0	0	1	0	0	0	1	1	1
SINGLE_E_BUF[4]	0	0	0	1	1	0	0	0	1	1
HEX_H2_BUF[0]	0	0	1	0	0	0	0	0	0	1
OUT_TBUF_W[3]	0	0	1	0	0	0	0	0	1	0
SINGLE_E_BUF[8]	0	0	1	0	0	0	0	1	1	1
SINGLE_E_BUF[5]	0	0	1	0	1	0	0	0	1	1
OUT_TBUF_W[0]	0	1	0	0	0	0	0	0	1	0
SINGLE_E_BUF[6]	0	1	0	0	0	0	0	1	1	1
SINGLE_E_BUF[10]	0	1	0	0	1	0	0	0	1	1
OUT_TBUF_W[1]	1	0	0	0	0	0	0	0	1	0
SINGLE_E_BUF[7]	1	0	0	0	0	0	0	1	1	1
SINGLE_E_BUF[11]	1	0	0	0	1	0	0	0	1	1

INT:MUX.IMUX_IO_O[1]	0.F43.B14	0.F42.B14	0.F43.B12	0.F41.B12	0.F41.B14	0.F39.B13	0.F38.B13	0.F40.B14	0.F40.B13	0.F39.B14
NONE	0	0	0	0	0	0	0	0	1	1
HEX_H2_BUF[1]	0	0	0	0	0	0	1	0	0	1
OMUX_W7	0	0	0	0	0	0	1	0	1	0
SINGLE_E_BUF[0]	0	0	0	0	0	0	1	1	1	1
HEX_H3_BUF[1]	0	0	0	0	0	1	0	0	0	1
OMUX_W6	0	0	0	0	0	1	0	0	1	0
SINGLE_E_BUF[1]	0	0	0	0	0	1	0	1	1	1
SINGLE_E_BUF[3]	0	0	0	0	1	0	1	0	1	1
SINGLE_E_BUF[2]	0	0	0	0	1	1	0	0	1	1
HEX_H1_BUF[1]	0	0	0	1	0	0	0	0	0	1
OUT_TBUF_W[2]	0	0	0	1	0	0	0	0	1	0
SINGLE_E_BUF[9]	0	0	0	1	0	0	0	1	1	1
SINGLE_E_BUF[4]	0	0	0	1	1	0	0	0	1	1
HEX_H0_BUF[1]	0	0	1	0	0	0	0	0	0	1
OUT_TBUF_W[3]	0	0	1	0	0	0	0	0	1	0
SINGLE_E_BUF[8]	0	0	1	0	0	0	0	1	1	1
SINGLE_E_BUF[5]	0	0	1	0	1	0	0	0	1	1
OUT_TBUF_W[0]	0	1	0	0	0	0	0	0	1	0
SINGLE_E_BUF[6]	0	1	0	0	0	0	0	1	1	1
SINGLE_E_BUF[10]	0	1	0	0	1	0	0	0	1	1
OUT_TBUF_W[1]	1	0	0	0	0	0	0	0	1	0
SINGLE_E_BUF[7]	1	0	0	0	0	0	0	1	1	1
SINGLE_E_BUF[11]	1	0	0	0	1	0	0	0	1	1

INT:MUX.IMUX_IO_O[2]	0.F8.B13	0.F9.B13	0.F4.B12	0.F6.B12	0.F7.B14	0.F5.B14	0.F4.B14	0.F6.B14	0.F7.B13	0.F8.B14
NONE	0	0	0	0	0	0	0	0	1	1
OUT_TBUF_W[1]	0	0	0	0	0	0	1	0	1	0
SINGLE_E_BUF[12]	0	0	0	0	0	0	1	1	1	1
OUT_TBUF_W[0]	0	0	0	0	0	1	0	0	1	0
SINGLE_E_BUF[13]	0	0	0	0	0	1	0	1	1	1
SINGLE_E_BUF[16]	0	0	0	0	1	0	1	0	1	1
SINGLE_E_BUF[17]	0	0	0	0	1	1	0	0	1	1
HEX_H1_BUF[2]	0	0	0	1	0	0	0	0	0	1
OUT_TBUF_W[2]	0	0	0	1	0	0	0	0	1	0
SINGLE_E_BUF[19]	0	0	0	1	0	0	0	1	1	1
SINGLE_E_BUF[14]	0	0	0	1	1	0	0	0	1	1
HEX_H0_BUF[2]	0	0	1	0	0	0	0	0	0	1
OUT_TBUF_W[3]	0	0	1	0	0	0	0	0	1	0
SINGLE_E_BUF[18]	0	0	1	0	0	0	0	1	1	1
SINGLE_E_BUF[15]	0	0	1	0	1	0	0	0	1	1
HEX_H2_BUF[2]	0	1	0	0	0	0	0	0	0	1
OMUX_W7	0	1	0	0	0	0	0	0	1	0
SINGLE_E_BUF[20]	0	1	0	0	0	0	0	1	1	1
SINGLE_E_BUF[23]	0	1	0	0	1	0	0	0	1	1
HEX_H3_BUF[2]	1	0	0	0	0	0	0	0	0	1
OMUX_W6	1	0	0	0	0	0	0	0	1	0
SINGLE_E_BUF[21]	1	0	0	0	0	0	0	1	1	1
SINGLE_E_BUF[22]	1	0	0	0	1	0	0	0	1	1

INT:MUX.IMUX_IO_O[3]	0.F3.B13	0.F4.B13	0.F0.B13	0.F1.B13	0.F3.B14	0.F5.B13	0.F6.B13	0.F2.B14	0.F2.B13	0.F1.B14
NONE	0	0	0	0	0	0	0	0	1	1
OUT_TBUF_W[1]	0	0	0	0	0	0	1	0	1	0
SINGLE_E_BUF[12]	0	0	0	0	0	0	1	1	1	1
OUT_TBUF_W[0]	0	0	0	0	0	1	0	0	1	0
SINGLE_E_BUF[13]	0	0	0	0	0	1	0	1	1	1
SINGLE_E_BUF[16]	0	0	0	0	1	0	1	0	1	1
SINGLE_E_BUF[17]	0	0	0	0	1	1	0	0	1	1
HEX_H1_BUF[3]	0	0	0	1	0	0	0	0	0	1
OUT_TBUF_W[2]	0	0	0	1	0	0	0	0	1	0
SINGLE_E_BUF[19]	0	0	0	1	0	0	0	1	1	1
SINGLE_E_BUF[14]	0	0	0	1	1	0	0	0	1	1
HEX_H2_BUF[3]	0	0	1	0	0	0	0	0	0	1
OUT_TBUF_W[3]	0	0	1	0	0	0	0	0	1	0
SINGLE_E_BUF[18]	0	0	1	0	0	0	0	1	1	1
SINGLE_E_BUF[15]	0	0	1	0	1	0	0	0	1	1
HEX_H0_BUF[3]	0	1	0	0	0	0	0	0	0	1
OMUX_W7	0	1	0	0	0	0	0	0	1	0
SINGLE_E_BUF[20]	0	1	0	0	0	0	0	1	1	1
SINGLE_E_BUF[23]	0	1	0	0	1	0	0	0	1	1
HEX_H3_BUF[3]	1	0	0	0	0	0	0	0	0	1
OMUX_W6	1	0	0	0	0	0	0	0	1	0
SINGLE_E_BUF[21]	1	0	0	0	0	0	0	1	1	1
SINGLE_E_BUF[22]	1	0	0	0	1	0	0	0	1	1

INT:MUX.IMUX_IO_SR[0]	0.F29.B10	0.F30.B10	0.F31.B10	0.F33.B9	0.F32.B11	0.F33.B11
INT:MUX.IMUX_IO_SR[1]	0.F30.B11	0.F29.B11	0.F28.B9	0.F32.B9	0.F31.B9	0.F28.B11
INT:MUX.IMUX_IO_SR[2]	0.F35.B11	0.F36.B11	0.F37.B10	0.F38.B9	0.F36.B9	0.F37.B11
INT:MUX.IMUX_IO_SR[3]	0.F36.B10	0.F35.B10	0.F34.B10	0.F35.B9	0.F39.B9	0.F34.B11
NONE	0	0	0	0	0	0
SINGLE_E_BUF[4]	0	0	0	0	0	1
SINGLE_E_BUF[5]	0	0	0	0	1	0
SINGLE_E_BUF[6]	0	0	0	1	0	0
SINGLE_E_BUF[7]	0	0	1	0	0	0
HEX_V1_BUF[1]	0	1	0	0	0	1
HEX_V4_BUF[1]	0	1	0	0	1	0
HEX_V2_BUF[1]	1	1	0	0	0	1
HEX_V3_BUF[1]	1	1	0	0	1	0
HEX_V5_BUF[1]	1	1	0	1	0	0
HEX_V6_BUF[1]	1	1	1	0	0	0

INT:MUX.IMUX_IO_TCE[0]	0.F25.B11	0.F26.B11	0.F27.B11	0.F25.B9	0.F26.B9	0.F28.B10
INT:MUX.IMUX_IO_TCE[1]	0.F27.B10	0.F26.B10	0.F24.B11	0.F31.B11	0.F27.B9	0.F24.B10
INT:MUX.IMUX_IO_TCE[2]	0.F22.B11	0.F21.B11	0.F20.B11	0.F22.B9	0.F21.B9	0.F19.B10
INT:MUX.IMUX_IO_TCE[3]	0.F20.B10	0.F21.B10	0.F23.B11	0.F16.B11	0.F20.B9	0.F23.B10
NONE	0	0	0	0	0	0
SINGLE_E_BUF[10]	0	0	0	0	0	1
SINGLE_E_BUF[11]	0	0	0	0	1	0
SINGLE_E_BUF[12]	0	0	0	1	0	0
SINGLE_E_BUF[13]	0	0	1	0	0	0
HEX_V4_BUF[3]	0	1	0	1	0	0
HEX_V1_BUF[3]	0	1	1	0	0	0
HEX_V6_BUF[3]	1	1	0	0	0	1
HEX_V5_BUF[3]	1	1	0	0	1	0
HEX_V3_BUF[3]	1	1	0	1	0	0
HEX_V2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_T[0]	0.F39.B10	0.F40.B10	0.F41.B10	0.F40.B9	0.F41.B11	0.F42.B11
INT:MUX.IMUX_IO_T[1]	0.F40.B11	0.F39.B11	0.F38.B10	0.F42.B9	0.F43.B9	0.F38.B11
INT:MUX.IMUX_IO_T[2]	0.F45.B11	0.F46.B11	0.F47.B10	0.F46.B9	0.F47.B9	0.F47.B11
INT:MUX.IMUX_IO_T[3]	0.F46.B10	0.F45.B10	0.F44.B10	0.F45.B9	0.F43.B11	0.F44.B11
NONE	0	0	0	0	0	0
SINGLE_E_BUF[0]	0	0	0	0	0	1
SINGLE_E_BUF[1]	0	0	0	0	1	0
SINGLE_E_BUF[2]	0	0	0	1	0	0
SINGLE_E_BUF[3]	0	0	1	0	0	0
HEX_V1_BUF[0]	0	1	0	0	0	1
HEX_V4_BUF[0]	0	1	0	0	1	0
HEX_V2_BUF[0]	1	1	0	0	0	1
HEX_V3_BUF[0]	1	1	0	0	1	0
HEX_V5_BUF[0]	1	1	0	1	0	0
HEX_V6_BUF[0]	1	1	1	0	0	0

INT:MUX.IMUX_TBUF_I[0]	0.F19.B15	0.F20.B15	0.F37.B15	0.F17.B15	0.F16.B15
NONE	0	0	0	0	0
SINGLE_E_BUF[17]	0	0	0	0	1
SINGLE_E_BUF[18]	0	0	0	1	0
SINGLE_E_BUF[22]	0	0	1	0	0
OUT_IO_I[3]	0	1	0	0	1
OUT_IO_I[2]	0	1	0	1	0
SINGLE_E_BUF[23]	0	1	1	0	0
OUT_IO_IQ[2]	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	0
OUT_IO_IQ[1]	1	1	0	1	0
OUT_IO_I[1]	1	1	1	0	0

INT:MUX.IMUX_TBUF_I[1]	0.F22.B15	0.F21.B15	0.F38.B15	0.F39.B15	0.F24.B15
NONE	0	0	0	0	0
SINGLE_E_BUF[5]	0	0	0	0	1
SINGLE_E_BUF[6]	0	0	0	1	0
SINGLE_E_BUF[11]	0	0	1	0	0
OUT_IO_I[2]	0	1	0	0	1
OUT_IO_I[3]	0	1	0	1	0
SINGLE_E_BUF[10]	0	1	1	0	0
OUT_IO_IQ[2]	1	0	0	0	1
OUT_IO_IQ[3]	1	0	1	0	0
OUT_IO_IQ[1]	1	1	0	0	1
OUT_IO_I[1]	1	1	1	0	0

INT:MUX.IMUX_TBUF_T[0]	0.F26.B15	0.F27.B15	0.F40.B15	0.F35.B12	0.F27.B12
INT:MUX.IMUX_TBUF_T[1]	0.F29.B15	0.F28.B15	0.F43.B15	0.F33.B12	0.F28.B12
NONE	0	0	0	0	0
HEX_V6_BUF[1]	0	0	0	0	1
HEX_V5_BUF[1]	0	0	0	1	0
HEX_V1_BUF[1]	0	0	1	0	0
SINGLE_E_BUF[0]	0	1	0	0	1
SINGLE_E_BUF[7]	0	1	0	1	0
HEX_V2_BUF[1]	1	0	0	0	1
HEX_V3_BUF[1]	1	0	0	1	0
HEX_V4_BUF[1]	1	0	1	0	0
SINGLE_E_BUF[19]	1	1	0	0	1
SINGLE_E_BUF[12]	1	1	0	1	0

INT:MUX.LH[0]
INT:MUX.LH[1]
OUT_IO_IQ[3]

INT:MUX.LH[10]	0.F40.B12
NONE	0
OUT_IO_IQ[3]	1

INT:MUX.LH[11]	0.F47.B12
OUT_IO_IQ[1]	0
OUT_IO_I[3]	1

INT:MUX.LH[2]	0.F16.B12
INT:MUX.LH[3]	0.F15.B12
OUT_IO_I[3]	0
OUT_IO_IQ[1]	1

INT:MUX.LH[4]	0.F8.B12
OUT_IO_IQ[2]	0
OUT_IO_I[1]	1

INT:MUX.LH[5]	0.F7.B12
OUT_IO_I[2]	0
OUT_IO_I[1]	1

INT:MUX.LH[6]	0.F0.B12
NONE	0
OUT_IO_IQ[2]	1

INT:MUX.LH[7]	0.F31.B12
OUT_IO_I[1]	0
OUT_IO_IQ[2]	1

INT:MUX.LH[8]	0.F32.B12
INT:MUX.LH[9]	0.F39.B12
NONE	0
OUT_IO_I[2]	1

INT:MUX.LV[0]	0.F4.B15	0.F9.B12	0.F1.B15	0.F7.B15	0.F14.B15	0.F11.B15	0.F12.B15	0.F3.B15	0.F0.B15
INT:MUX.LV[6]	0.F8.B15	0.F12.B12	0.F5.B15	0.F6.B15	0.F15.B15	0.F14.B12	0.F9.B15	0.F13.B15	0.F1.B12
NONE	0	0	0	0	0	0	0	0	0
SINGLE_E_BUF[5]	0	0	0	0	0	0	0	0	1
SINGLE_E_BUF[6]	0	0	0	0	0	0	0	1	0
SINGLE_E_BUF[10]	0	0	0	0	0	0	1	0	0
SINGLE_E_BUF[11]	0	0	0	0	0	1	0	0	0
SINGLE_E_BUF[17]	0	0	0	0	1	0	0	0	0
SINGLE_E_BUF[18]	0	0	0	1	0	0	0	0	0
SINGLE_E_BUF[22]	0	0	1	0	0	0	0	0	0
SINGLE_E_BUF[23]	0	1	0	0	0	0	0	0	0
OUT_IO_IQ[3]	1	0	0	0	0	0	0	0	1
OUT_IO_IQ[2]	1	0	0	0	0	0	0	1	0
OUT_IO_I[2]	1	0	0	0	0	0	1	0	0
OUT_IO_IQ[1]	1	0	0	0	1	0	0	0	0
OUT_IO_I[3]	1	0	0	1	0	0	0	0	0
OUT_IO_I[1]	1	0	1	0	0	0	0	0	0

INT:MUX.OMUX[0]	0.F30.B15	0.F41.B15	0.F33.B15
INT:MUX.OMUX[1]	0.F32.B15	0.F34.B15	0.F42.B15
NONE	0	0	0
OUT_IO_I[1]	0	0	1
OUT_IO_I[2]	0	1	0
OUT_IO_I[3]	1	0	0

IO[1]:OMUX	0.F40.B16
IO[2]:OMUX	0.F25.B16
IO[3]:OMUX	0.F10.B16
O	0
OFF	1

IO[1]:TMUX	0.F35.B16
IO[2]:TMUX	0.F30.B16
IO[3]:TMUX	0.F5.B16
T	0
TFF	1

Tile IO_E

Cells: 1

Switchbox INT

virtex IO_E switchbox INT permanent buffers
Destination	Source
SINGLE_W_BUF[0]	SINGLE_W[0]
SINGLE_W_BUF[1]	SINGLE_W[1]
SINGLE_W_BUF[2]	SINGLE_W[2]
SINGLE_W_BUF[3]	SINGLE_W[3]
SINGLE_W_BUF[4]	SINGLE_W[4]
SINGLE_W_BUF[5]	SINGLE_W[5]
SINGLE_W_BUF[6]	SINGLE_W[6]
SINGLE_W_BUF[7]	SINGLE_W[7]
SINGLE_W_BUF[8]	SINGLE_W[8]
SINGLE_W_BUF[9]	SINGLE_W[9]
SINGLE_W_BUF[10]	SINGLE_W[10]
SINGLE_W_BUF[11]	SINGLE_W[11]
SINGLE_W_BUF[12]	SINGLE_W[12]
SINGLE_W_BUF[13]	SINGLE_W[13]
SINGLE_W_BUF[14]	SINGLE_W[14]
SINGLE_W_BUF[15]	SINGLE_W[15]
SINGLE_W_BUF[16]	SINGLE_W[16]
SINGLE_W_BUF[17]	SINGLE_W[17]
SINGLE_W_BUF[18]	SINGLE_W[18]
SINGLE_W_BUF[19]	SINGLE_W[19]
SINGLE_W_BUF[20]	SINGLE_W[20]
SINGLE_W_BUF[21]	SINGLE_W[21]
SINGLE_W_BUF[22]	SINGLE_W[22]
SINGLE_W_BUF[23]	SINGLE_W[23]
HEX_H3_BUF[0]	HEX_H3[0]
HEX_H3_BUF[1]	HEX_H3[1]
HEX_H3_BUF[2]	HEX_H3[2]
HEX_H3_BUF[3]	HEX_H3[3]
HEX_H4_BUF[0]	HEX_H4[0]
HEX_H4_BUF[1]	HEX_H4[1]
HEX_H4_BUF[2]	HEX_H4[2]
HEX_H4_BUF[3]	HEX_H4[3]
HEX_H5_BUF[0]	HEX_H5[0]
HEX_H5_BUF[1]	HEX_H5[1]
HEX_H5_BUF[2]	HEX_H5[2]
HEX_H5_BUF[3]	HEX_H5[3]
HEX_H6_BUF[0]	HEX_H6[0]
HEX_H6_BUF[1]	HEX_H6[1]
HEX_H6_BUF[2]	HEX_H6[2]
HEX_H6_BUF[3]	HEX_H6[3]
HEX_V1_BUF[0]	HEX_V1[0]
HEX_V1_BUF[1]	HEX_V1[1]
HEX_V1_BUF[2]	HEX_V1[2]
HEX_V1_BUF[3]	HEX_V1[3]
HEX_V2_BUF[0]	HEX_V2[0]
HEX_V2_BUF[1]	HEX_V2[1]
HEX_V2_BUF[2]	HEX_V2[2]
HEX_V2_BUF[3]	HEX_V2[3]
HEX_V3_BUF[0]	HEX_V3[0]
HEX_V3_BUF[1]	HEX_V3[1]
HEX_V3_BUF[2]	HEX_V3[2]
HEX_V3_BUF[3]	HEX_V3[3]
HEX_V4_BUF[0]	HEX_V4[0]
HEX_V4_BUF[1]	HEX_V4[1]
HEX_V4_BUF[2]	HEX_V4[2]
HEX_V4_BUF[3]	HEX_V4[3]
HEX_V5_BUF[0]	HEX_V5[0]
HEX_V5_BUF[1]	HEX_V5[1]
HEX_V5_BUF[2]	HEX_V5[2]
HEX_V5_BUF[3]	HEX_V5[3]
HEX_V6_BUF[0]	HEX_V6[0]
HEX_V6_BUF[1]	HEX_V6[1]
HEX_V6_BUF[2]	HEX_V6[2]
HEX_V6_BUF[3]	HEX_V6[3]

virtex IO_E switchbox INT pass gates
Destination	Source	Bit
SINGLE_W[0]	HEX_V6[0]	XXX57005[57005][57005]
SINGLE_W[0]	OUT_TBUF_E[3]	XXX57005[57005][57005]
SINGLE_W[0]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_W[1]	HEX_V3[0]	XXX57005[57005][57005]
SINGLE_W[1]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_W[2]	HEX_V0[0]	XXX57005[57005][57005]
SINGLE_W[2]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_W[3]	HEX_V6[0]	XXX57005[57005][57005]
SINGLE_W[3]	OUT_TBUF_E[3]	XXX57005[57005][57005]
SINGLE_W[3]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_W[4]	HEX_V3[0]	XXX57005[57005][57005]
SINGLE_W[4]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_W[5]	HEX_V0[0]	XXX57005[57005][57005]
SINGLE_W[5]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_W[6]	HEX_V6[1]	XXX57005[57005][57005]
SINGLE_W[6]	OUT_TBUF_E[2]	XXX57005[57005][57005]
SINGLE_W[6]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_W[7]	HEX_V3[1]	XXX57005[57005][57005]
SINGLE_W[7]	OUT_IO_IQ[0]	XXX57005[57005][57005]
SINGLE_W[8]	HEX_V0[1]	XXX57005[57005][57005]
SINGLE_W[8]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_W[9]	HEX_V6[1]	XXX57005[57005][57005]
SINGLE_W[9]	OUT_TBUF_E[2]	XXX57005[57005][57005]
SINGLE_W[9]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_W[10]	HEX_V3[1]	XXX57005[57005][57005]
SINGLE_W[10]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_W[11]	HEX_V0[1]	XXX57005[57005][57005]
SINGLE_W[11]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_W[12]	HEX_V6[2]	XXX57005[57005][57005]
SINGLE_W[12]	OUT_TBUF_E[1]	XXX57005[57005][57005]
SINGLE_W[12]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_W[13]	HEX_V3[2]	XXX57005[57005][57005]
SINGLE_W[13]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_W[14]	HEX_V0[2]	XXX57005[57005][57005]
SINGLE_W[14]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_W[15]	HEX_V6[2]	XXX57005[57005][57005]
SINGLE_W[15]	OUT_TBUF_E[1]	XXX57005[57005][57005]
SINGLE_W[15]	OUT_IO_IQ[0]	XXX57005[57005][57005]
SINGLE_W[16]	HEX_V3[2]	XXX57005[57005][57005]
SINGLE_W[16]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_W[17]	HEX_V0[2]	XXX57005[57005][57005]
SINGLE_W[17]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_W[18]	HEX_V6[3]	XXX57005[57005][57005]
SINGLE_W[18]	OUT_TBUF_E[0]	XXX57005[57005][57005]
SINGLE_W[18]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_W[19]	HEX_V3[3]	XXX57005[57005][57005]
SINGLE_W[19]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_W[20]	HEX_V0[3]	XXX57005[57005][57005]
SINGLE_W[20]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_W[21]	HEX_V6[3]	XXX57005[57005][57005]
SINGLE_W[21]	OUT_TBUF_E[0]	XXX57005[57005][57005]
SINGLE_W[21]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_W[22]	HEX_V3[3]	XXX57005[57005][57005]
SINGLE_W[22]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_W[23]	HEX_V0[3]	XXX57005[57005][57005]
SINGLE_W[23]	OUT_IO_IQ[0]	XXX57005[57005][57005]

virtex IO_E switchbox INT muxes HEX_H1[0]
Bits	Destination
HEX_H1[0]
	Source
OUT_IO_IQ[0]

virtex IO_E switchbox INT muxes HEX_H1[1]
Bits	Destination
HEX_H1[1]
	Source
OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes HEX_H1[2]
Bits	Destination
HEX_H1[2]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H1[3]
Bits	Destination
HEX_H1[3]
	Source
OUT_IO_I[2]

virtex IO_E switchbox INT muxes HEX_H2[0]
Bits	Destination
HEX_H2[0]
	Source
OUT_IO_IQ[0]

virtex IO_E switchbox INT muxes HEX_H2[1]
Bits	Destination
HEX_H2[1]
	Source
OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes HEX_H2[2]
Bits	Destination
HEX_H2[2]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H2[3]
Bits	Destination
HEX_H2[3]
	Source
OUT_IO_I[2]

virtex IO_E switchbox INT muxes HEX_H3[0]
Bits	Destination
HEX_H3[0]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H3[1]
Bits	Destination
HEX_H3[1]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H3[2]
Bits	Destination
HEX_H3[2]
	Source
OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H3[3]
Bits	Destination
HEX_H3[3]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H4[0]
Bits	Destination
HEX_H4[0]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H4[1]
Bits	Destination
HEX_H4[1]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H4[2]
Bits	Destination
HEX_H4[2]
	Source
OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H4[3]
Bits	Destination
HEX_H4[3]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H5[0]
Bits	Destination
HEX_H5[0]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H5[1]
Bits	Destination
HEX_H5[1]
	Source
OUT_IO_IQ[0]

virtex IO_E switchbox INT muxes HEX_H5[2]
Bits	Destination
HEX_H5[2]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H5[3]
Bits	Destination
HEX_H5[3]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H6[0]
Bits	Destination
HEX_H6[0]
	Source
OUT_IO_I[1]

virtex IO_E switchbox INT muxes HEX_H6[1]
Bits	Destination
HEX_H6[1]
	Source
OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H6[2]
Bits	Destination
HEX_H6[2]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H6[3]
Bits	Destination
HEX_H6[3]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_W0[0]
Bits	Destination
HEX_W0[0]
	Source
OUT_IO_IQ[0]

virtex IO_E switchbox INT muxes HEX_W0[1]
Bits	Destination
HEX_W0[1]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_W0[2]
Bits	Destination
HEX_W0[2]
	Source
OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes HEX_W0[3]
Bits	Destination
HEX_W0[3]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_W1[0]
Bits	Destination
HEX_W1[0]
	Source
OUT_IO_IQ[0]

virtex IO_E switchbox INT muxes HEX_W1[1]
Bits	Destination
HEX_W1[1]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_W1[2]
Bits	Destination
HEX_W1[2]
	Source
OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes HEX_W1[3]
Bits	Destination
HEX_W1[3]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_W2[0]
Bits	Destination
HEX_W2[0]
	Source
HEX_E3[0]

virtex IO_E switchbox INT muxes HEX_W2[1]
Bits	Destination
HEX_W2[1]
	Source
HEX_E3[1]

virtex IO_E switchbox INT muxes HEX_W2[2]
Bits	Destination
HEX_W2[2]
	Source
HEX_E3[2]

virtex IO_E switchbox INT muxes HEX_W2[3]
Bits	Destination
HEX_W2[3]
	Source
HEX_E3[3]

virtex IO_E switchbox INT muxes HEX_W3[0]
Bits	Destination
HEX_W3[0]
	Source
HEX_E4[0]

virtex IO_E switchbox INT muxes HEX_W3[1]
Bits	Destination
HEX_W3[1]
	Source
HEX_E4[1]

virtex IO_E switchbox INT muxes HEX_W3[2]
Bits	Destination
HEX_W3[2]
	Source
HEX_E4[2]

virtex IO_E switchbox INT muxes HEX_W3[3]
Bits	Destination
HEX_W3[3]
	Source
HEX_E4[3]

virtex IO_E switchbox INT muxes HEX_W4[0]
Bits	Destination
HEX_W4[0]
	Source
HEX_E5[0]

virtex IO_E switchbox INT muxes HEX_W4[1]
Bits	Destination
HEX_W4[1]
	Source
HEX_E5[1]

virtex IO_E switchbox INT muxes HEX_W4[2]
Bits	Destination
HEX_W4[2]
	Source
HEX_E5[2]

virtex IO_E switchbox INT muxes HEX_W4[3]
Bits	Destination
HEX_W4[3]
	Source
HEX_E5[3]

virtex IO_E switchbox INT muxes HEX_W5[0]
Bits	Destination
HEX_W5[0]
	Source
HEX_E6[0]

virtex IO_E switchbox INT muxes HEX_W5[1]
Bits	Destination
HEX_W5[1]
	Source
HEX_E6[1]

virtex IO_E switchbox INT muxes HEX_W5[2]
Bits	Destination
HEX_W5[2]
	Source
HEX_E6[2]

virtex IO_E switchbox INT muxes HEX_W5[3]
Bits	Destination
HEX_W5[3]
	Source
HEX_E6[3]

virtex IO_E switchbox INT muxes HEX_V0[0]
Bits	Destination
HEX_V0[0]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V0[1]
Bits	Destination
HEX_V0[1]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V0[2]
Bits	Destination
HEX_V0[2]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V0[3]
Bits	Destination
HEX_V0[3]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V6[0]
Bits	Destination
HEX_V6[0]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V6[1]
Bits	Destination
HEX_V6[1]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V6[2]
Bits	Destination
HEX_V6[2]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V6[3]
Bits	Destination
HEX_V6[3]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LH[0]
Bits	Destination
LH[0]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LH[1]
Bits	Destination
LH[1]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LH[2]
Bits	Destination
LH[2]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes LH[3]
Bits	Destination
LH[3]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes LH[4]
Bits	Destination
LH[4]
	Source
OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes LH[5]
Bits	Destination
LH[5]
	Source
OUT_IO_I[2]

virtex IO_E switchbox INT muxes LH[6]
Bits	Destination
LH[6]
	Source
OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes LH[7]
Bits	Destination
LH[7]
	Source
OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes LH[8]
Bits	Destination
LH[8]
	Source
OUT_IO_IQ[0]

virtex IO_E switchbox INT muxes LH[9]
Bits	Destination
LH[9]
	Source
OUT_IO_IQ[0]

virtex IO_E switchbox INT muxes LH[10]
Bits	Destination
LH[10]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LH[11]
Bits	Destination
LH[11]
	Source
OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes LV[0]
Bits	Destination
LV[0]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LV[6]
Bits	Destination
LV[6]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes IMUX_TBUF_T[0]
Bits	Destination
IMUX_TBUF_T[0]
	Source
HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_TBUF_T[1]
Bits	Destination
IMUX_TBUF_T[1]
	Source
HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_TBUF_I[0]
Bits	Destination
IMUX_TBUF_I[0]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes IMUX_TBUF_I[1]
Bits	Destination
IMUX_TBUF_I[1]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes IMUX_IO_CLK[0]
Bits	Destination
IMUX_IO_CLK[0]
	Source
HEX_V6_BUF[2]

virtex IO_E switchbox INT muxes IMUX_IO_CLK[1]
Bits	Destination
IMUX_IO_CLK[1]
	Source
HEX_V6_BUF[2]

virtex IO_E switchbox INT muxes IMUX_IO_CLK[2]
Bits	Destination
IMUX_IO_CLK[2]
	Source
HEX_V6_BUF[2]

virtex IO_E switchbox INT muxes IMUX_IO_CLK[3]
Bits	Destination
IMUX_IO_CLK[3]
	Source
HEX_V6_BUF[2]

virtex IO_E switchbox INT muxes IMUX_IO_SR[0]
Bits	Destination
IMUX_IO_SR[0]
	Source
HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_IO_SR[1]
Bits	Destination
IMUX_IO_SR[1]
	Source
HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_IO_SR[2]
Bits	Destination
IMUX_IO_SR[2]
	Source
HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_IO_SR[3]
Bits	Destination
IMUX_IO_SR[3]
	Source
HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_IO_ICE[0]
Bits	Destination
IMUX_IO_ICE[0]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_ICE[1]
Bits	Destination
IMUX_IO_ICE[1]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_ICE[2]
Bits	Destination
IMUX_IO_ICE[2]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_ICE[3]
Bits	Destination
IMUX_IO_ICE[3]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_OCE[0]
Bits	Destination
IMUX_IO_OCE[0]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_OCE[1]
Bits	Destination
IMUX_IO_OCE[1]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_OCE[2]
Bits	Destination
IMUX_IO_OCE[2]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_OCE[3]
Bits	Destination
IMUX_IO_OCE[3]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_TCE[0]
Bits	Destination
IMUX_IO_TCE[0]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_TCE[1]
Bits	Destination
IMUX_IO_TCE[1]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_TCE[2]
Bits	Destination
IMUX_IO_TCE[2]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_TCE[3]
Bits	Destination
IMUX_IO_TCE[3]
	Source
HEX_V6_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_O[0]
Bits	Destination
IMUX_IO_O[0]
	Source
OUT_TBUF_E[3]

virtex IO_E switchbox INT muxes IMUX_IO_O[1]
Bits	Destination
IMUX_IO_O[1]
	Source
OUT_TBUF_E[3]

virtex IO_E switchbox INT muxes IMUX_IO_O[2]
Bits	Destination
IMUX_IO_O[2]
	Source
OUT_TBUF_E[3]

virtex IO_E switchbox INT muxes IMUX_IO_O[3]
Bits	Destination
IMUX_IO_O[3]
	Source
OUT_TBUF_E[3]

virtex IO_E switchbox INT muxes IMUX_IO_T[0]
Bits	Destination
IMUX_IO_T[0]
	Source
HEX_V6_BUF[0]

virtex IO_E switchbox INT muxes IMUX_IO_T[1]
Bits	Destination
IMUX_IO_T[1]
	Source
HEX_V6_BUF[0]

virtex IO_E switchbox INT muxes IMUX_IO_T[2]
Bits	Destination
IMUX_IO_T[2]
	Source
HEX_V6_BUF[0]

virtex IO_E switchbox INT muxes IMUX_IO_T[3]
Bits	Destination
IMUX_IO_T[3]
	Source
HEX_V6_BUF[0]

virtex IO_E switchbox INT muxes OMUX[6]
Bits	Destination
OMUX[6]
	Source
OUT_IO_I[3]

virtex IO_E switchbox INT muxes OMUX[7]
Bits	Destination
OMUX[7]
	Source
OUT_IO_I[3]

Bel TBUF[0]

virtex IO_E bel TBUF[0]
Pin	Direction	Wires
I	input	IMUX_TBUF_I[0]
T	input	IMUX_TBUF_T[0]

Bel TBUF[1]

virtex IO_E bel TBUF[1]
Pin	Direction	Wires
I	input	IMUX_TBUF_I[1]
T	input	IMUX_TBUF_T[1]

Bel TBUS

virtex IO_E bel TBUS
Pin	Direction	Wires
BUS0	output	OUT_TBUF_E[2]
BUS1	output	OUT_TBUF_E[3]
BUS2	output	OUT_TBUF_E[0]
BUS3	output	OUT_TBUF_E[1]

Bel IO[0]

virtex IO_E bel IO[0]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[0]
I	output	OUT_IO_I[0]
ICE	input	IMUX_IO_ICE[0]
IQ	output	OUT_IO_IQ[0]
O	input	IMUX_IO_O[0]
OCE	input	IMUX_IO_OCE[0]
SR	input	IMUX_IO_SR[0]
T	input	IMUX_IO_T[0]
TCE	input	IMUX_IO_TCE[0]

Bel IO[1]

virtex IO_E bel IO[1]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[1]
I	output	OUT_IO_I[1]
ICE	input	IMUX_IO_ICE[1]
IQ	output	OUT_IO_IQ[1]
O	input	IMUX_IO_O[1]
OCE	input	IMUX_IO_OCE[1]
SR	input	IMUX_IO_SR[1]
T	input	IMUX_IO_T[1]
TCE	input	IMUX_IO_TCE[1]

Bel IO[2]

virtex IO_E bel IO[2]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[2]
I	output	OUT_IO_I[2]
ICE	input	IMUX_IO_ICE[2]
IQ	output	OUT_IO_IQ[2]
O	input	IMUX_IO_O[2]
OCE	input	IMUX_IO_OCE[2]
SR	input	IMUX_IO_SR[2]
T	input	IMUX_IO_T[2]
TCE	input	IMUX_IO_TCE[2]

Bel IO[3]

virtex IO_E bel IO[3]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[3]
I	output	OUT_IO_I[3]
ICE	input	IMUX_IO_ICE[3]
IQ	output	OUT_IO_IQ[3]
O	input	IMUX_IO_O[3]
OCE	input	IMUX_IO_OCE[3]
SR	input	IMUX_IO_SR[3]
T	input	IMUX_IO_T[3]
TCE	input	IMUX_IO_TCE[3]

Bel wires

virtex IO_E bel wires
Wire	Pins
IMUX_TBUF_T[0]	TBUF[0].T
IMUX_TBUF_T[1]	TBUF[1].T
IMUX_TBUF_I[0]	TBUF[0].I
IMUX_TBUF_I[1]	TBUF[1].I
IMUX_IO_CLK[0]	IO[0].CLK
IMUX_IO_CLK[1]	IO[1].CLK
IMUX_IO_CLK[2]	IO[2].CLK
IMUX_IO_CLK[3]	IO[3].CLK
IMUX_IO_SR[0]	IO[0].SR
IMUX_IO_SR[1]	IO[1].SR
IMUX_IO_SR[2]	IO[2].SR
IMUX_IO_SR[3]	IO[3].SR
IMUX_IO_ICE[0]	IO[0].ICE
IMUX_IO_ICE[1]	IO[1].ICE
IMUX_IO_ICE[2]	IO[2].ICE
IMUX_IO_ICE[3]	IO[3].ICE
IMUX_IO_OCE[0]	IO[0].OCE
IMUX_IO_OCE[1]	IO[1].OCE
IMUX_IO_OCE[2]	IO[2].OCE
IMUX_IO_OCE[3]	IO[3].OCE
IMUX_IO_TCE[0]	IO[0].TCE
IMUX_IO_TCE[1]	IO[1].TCE
IMUX_IO_TCE[2]	IO[2].TCE
IMUX_IO_TCE[3]	IO[3].TCE
IMUX_IO_O[0]	IO[0].O
IMUX_IO_O[1]	IO[1].O
IMUX_IO_O[2]	IO[2].O
IMUX_IO_O[3]	IO[3].O
IMUX_IO_T[0]	IO[0].T
IMUX_IO_T[1]	IO[1].T
IMUX_IO_T[2]	IO[2].T
IMUX_IO_T[3]	IO[3].T
OUT_TBUF_E[0]	TBUS.BUS2
OUT_TBUF_E[1]	TBUS.BUS3
OUT_TBUF_E[2]	TBUS.BUS0
OUT_TBUF_E[3]	TBUS.BUS1
OUT_IO_I[0]	IO[0].I
OUT_IO_I[1]	IO[1].I
OUT_IO_I[2]	IO[2].I
OUT_IO_I[3]	IO[3].I
OUT_IO_IQ[0]	IO[0].IQ
OUT_IO_IQ[1]	IO[1].IQ
OUT_IO_IQ[2]	IO[2].IQ
OUT_IO_IQ[3]	IO[3].IQ

Bitstream

virtex IO_E rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

### Bitstream

virtex IO_E rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47
B17	-	-	IO[1]:READBACK_IFF	-	-	-	-	-	IO[1]:READBACK_OFF	IO[1]:IFF_DELAY_ENABLE	~IO[1]:SHORTEN_JTAG_CHAIN	-	IO[1]:READBACK_TFF	-	-	-	-	IO[2]:READBACK_TFF	-	~IO[2]:SHORTEN_JTAG_CHAIN	IO[2]:IFF_DELAY_ENABLE	IO[2]:READBACK_OFF	-	-	-	-	-	IO[2]:READBACK_IFF	-	-	-	-	IO[3]:READBACK_IFF	-	-	-	-	-	IO[3]:READBACK_OFF	IO[3]:IFF_DELAY_ENABLE	~IO[3]:SHORTEN_JTAG_CHAIN	-	IO[3]:READBACK_TFF	-	-	-	-	-
B16	IO[1]:IFF_SR_SYNC	IO[1]:IFF_INIT	IO[1]:I_DELAY_ENABLE	IO[1]:IFF_LATCH	IO[1]:IFF_SR_ENABLE	IO[1]:OFF_SR_ENABLE	IO[1]:OFF_LATCH	IO[1]:OMUX[0]	~IO[1]:OFF_INIT	IO[1]:OFF_SR_SYNC	IO[1]:TFF_SR_SYNC	~IO[1]:TFF_INIT	IO[1]:TMUX[0]	IO[1]:TFF_LATCH	IO[1]:TFF_SR_ENABLE	IO[2]:TFF_SR_ENABLE	IO[2]:TFF_LATCH	IO[2]:TMUX[0]	~IO[2]:TFF_INIT	IO[2]:TFF_SR_SYNC	IO[2]:OFF_SR_SYNC	~IO[2]:OFF_INIT	IO[2]:OMUX[0]	IO[2]:OFF_LATCH	IO[2]:OFF_SR_ENABLE	IO[2]:IFF_SR_ENABLE	IO[2]:IFF_LATCH	IO[2]:I_DELAY_ENABLE	IO[2]:IFF_INIT	IO[2]:IFF_SR_SYNC	IO[3]:IFF_SR_SYNC	IO[3]:IFF_INIT	IO[3]:I_DELAY_ENABLE	IO[3]:IFF_LATCH	IO[3]:IFF_SR_ENABLE	IO[3]:OFF_SR_ENABLE	IO[3]:OFF_LATCH	IO[3]:OMUX[0]	~IO[3]:OFF_INIT	IO[3]:OFF_SR_SYNC	IO[3]:TFF_SR_SYNC	~IO[3]:TFF_INIT	IO[3]:TMUX[0]	IO[3]:TFF_LATCH	IO[3]:TFF_SR_ENABLE	-	-	-
B15	INT:MUX.LV[0][0]	INT:MUX.LV[0][6]	INT:DRIVE.LV[0]	INT:MUX.LV[0][1]	INT:MUX.LV[0][8]	INT:MUX.LV[6][6]	INT:MUX.LV[6][5]	INT:MUX.LV[0][5]	INT:MUX.LV[6][8]	INT:MUX.LV[6][2]	INT:DRIVE.LV[6]	INT:MUX.LV[0][3]	INT:MUX.LV[0][2]	INT:MUX.LV[6][1]	INT:MUX.LV[0][4]	INT:MUX.LV[6][4]	INT:MUX.IMUX_TBUF_I[0][0]	INT:MUX.IMUX_TBUF_I[0][1]	~INT:INV.IMUX_TBUF_I[0]	INT:MUX.IMUX_TBUF_I[0][4]	INT:MUX.IMUX_TBUF_I[0][3]	INT:MUX.IMUX_TBUF_I[1][3]	INT:MUX.IMUX_TBUF_I[1][4]	~INT:INV.IMUX_TBUF_I[1]	INT:MUX.IMUX_TBUF_I[1][0]	INT:INV.IMUX_TBUF_T[0]	INT:MUX.IMUX_TBUF_T[0][4]	INT:MUX.IMUX_TBUF_T[0][3]	INT:MUX.IMUX_TBUF_T[1][3]	INT:MUX.IMUX_TBUF_T[1][4]	INT:MUX.OMUX[6][2]	INT:INV.IMUX_TBUF_T[1]	INT:MUX.OMUX[7][2]	INT:MUX.OMUX[6][0]	INT:MUX.OMUX[7][1]	-	-	INT:MUX.IMUX_TBUF_I[0][2]	INT:MUX.IMUX_TBUF_I[1][2]	INT:MUX.IMUX_TBUF_I[1][1]	INT:MUX.IMUX_TBUF_T[0][2]	INT:MUX.OMUX[6][1]	INT:MUX.OMUX[7][0]	INT:MUX.IMUX_TBUF_T[1][2]	~TBUF[1]:OUT_A	~TBUF[1]:OUT_B	~TBUF[0]:OUT_B	~TBUF[0]:OUT_A
B14	~INT:INV.IMUX_IO_O[3]	INT:MUX.IMUX_IO_O[3][0]	INT:MUX.IMUX_IO_O[3][2]	INT:MUX.IMUX_IO_O[3][5]	INT:MUX.IMUX_IO_O[2][3]	INT:MUX.IMUX_IO_O[2][4]	INT:MUX.IMUX_IO_O[2][2]	INT:MUX.IMUX_IO_O[2][5]	INT:MUX.IMUX_IO_O[2][0]	~INT:INV.IMUX_IO_O[2]	IO[3]:INV.IFF.CLK	IO[3]:INV.OFF.CLK	IO[3]:INV.TFF.CLK	IO[2]:INV.IFF.CLK	IO[2]:INV.OFF.CLK	IO[2]:INV.TFF.CLK	INT:MUX.IMUX_IO_CLK[2][9]	INT:MUX.IMUX_IO_CLK[3][9]	INT:MUX.IMUX_IO_CLK[3][8]	INT:MUX.IMUX_IO_CLK[2][10]	INT:MUX.IMUX_IO_CLK[3][0]	INT:MUX.IMUX_IO_CLK[3][6]	INT:MUX.IMUX_IO_CLK[3][3]	INT:MUX.IMUX_IO_CLK[2][5]	INT:MUX.IMUX_IO_CLK[1][5]	INT:MUX.IMUX_IO_CLK[0][3]	INT:MUX.IMUX_IO_CLK[0][6]	INT:MUX.IMUX_IO_CLK[0][0]	INT:MUX.IMUX_IO_CLK[1][10]	INT:MUX.IMUX_IO_CLK[0][8]	INT:MUX.IMUX_IO_CLK[0][9]	INT:MUX.IMUX_IO_CLK[1][9]	IO[1]:INV.TFF.CLK	IO[1]:INV.OFF.CLK	IO[1]:INV.IFF.CLK	-	-	-	~INT:INV.IMUX_IO_O[1]	INT:MUX.IMUX_IO_O[1][0]	INT:MUX.IMUX_IO_O[1][2]	INT:MUX.IMUX_IO_O[1][5]	INT:MUX.IMUX_IO_O[1][8]	INT:MUX.IMUX_IO_O[1][9]	INT:MUX.IMUX_IO_O[0][2]	INT:MUX.IMUX_IO_O[0][5]	INT:MUX.IMUX_IO_O[0][0]	-
B13	INT:MUX.IMUX_IO_O[3][7]	INT:MUX.IMUX_IO_O[3][6]	INT:MUX.IMUX_IO_O[3][1]	INT:MUX.IMUX_IO_O[3][9]	INT:MUX.IMUX_IO_O[3][8]	INT:MUX.IMUX_IO_O[3][4]	INT:MUX.IMUX_IO_O[3][3]	INT:MUX.IMUX_IO_O[2][1]	INT:MUX.IMUX_IO_O[2][9]	INT:MUX.IMUX_IO_O[2][8]	-	INT:MUX.IMUX_IO_CLK[3][7]	-	INT:MUX.IMUX_IO_CLK[2][3]	INT:MUX.IMUX_IO_CLK[2][7]	INT:MUX.IMUX_IO_CLK[2][1]	INT:MUX.IMUX_IO_CLK[2][4]	INT:MUX.IMUX_IO_CLK[3][5]	INT:MUX.IMUX_IO_CLK[2][0]	INT:MUX.IMUX_IO_CLK[2][8]	INT:MUX.IMUX_IO_CLK[3][1]	INT:MUX.IMUX_IO_CLK[2][2]	INT:MUX.IMUX_IO_CLK[3][2]	INT:MUX.IMUX_IO_CLK[3][4]	INT:MUX.IMUX_IO_CLK[0][4]	INT:MUX.IMUX_IO_CLK[0][2]	INT:MUX.IMUX_IO_CLK[1][2]	INT:MUX.IMUX_IO_CLK[0][1]	INT:MUX.IMUX_IO_CLK[1][8]	INT:MUX.IMUX_IO_CLK[1][0]	INT:MUX.IMUX_IO_CLK[0][5]	INT:MUX.IMUX_IO_CLK[1][4]	INT:MUX.IMUX_IO_CLK[1][1]	INT:MUX.IMUX_IO_CLK[1][7]	INT:MUX.IMUX_IO_CLK[1][3]	-	INT:MUX.IMUX_IO_CLK[0][7]	-	INT:MUX.IMUX_IO_O[1][3]	INT:MUX.IMUX_IO_O[1][4]	INT:MUX.IMUX_IO_O[1][1]	INT:MUX.IMUX_IO_O[0][9]	INT:MUX.IMUX_IO_O[0][8]	INT:MUX.IMUX_IO_O[0][3]	INT:MUX.IMUX_IO_O[0][4]	INT:MUX.IMUX_IO_O[0][1]	INT:MUX.IMUX_IO_O[0][6]	INT:MUX.IMUX_IO_O[0][7]
B12	INT:MUX.LH[6][0]	INT:MUX.LV[6][0]	INT:DRIVE.LH[6]	-	INT:MUX.IMUX_IO_O[2][7]	INT:DRIVE.LH[5]	INT:MUX.IMUX_IO_O[2][6]	INT:MUX.LH[5][0]	INT:MUX.LH[4][0]	INT:MUX.LV[0][7]	INT:DRIVE.LH[4]	-	INT:MUX.LV[6][7]	INT:DRIVE.LH[3]	INT:MUX.LV[6][3]	INT:MUX.LH[3][0]	INT:MUX.LH[2][0]	INT:MUX.IMUX_IO_CLK[3][10]	INT:DRIVE.LH[2]	-	-	INT:DRIVE.LH[1]	INT:MUX.IMUX_IO_CLK[2][6]	-	-	INT:MUX.IMUX_IO_CLK[1][6]	INT:DRIVE.LH[0]	INT:MUX.IMUX_TBUF_T[0][0]	INT:MUX.IMUX_TBUF_T[1][0]	INT:DRIVE.LH[7]	INT:MUX.IMUX_IO_CLK[0][10]	INT:MUX.LH[7][0]	INT:MUX.LH[8][0]	INT:MUX.IMUX_TBUF_T[1][1]	INT:DRIVE.LH[8]	INT:MUX.IMUX_TBUF_T[0][1]	-	INT:DRIVE.LH[9]	-	INT:MUX.LH[9][0]	INT:MUX.LH[10][0]	INT:MUX.IMUX_IO_O[1][6]	INT:DRIVE.LH[10]	INT:MUX.IMUX_IO_O[1][7]	-	INT:DRIVE.LH[11]	-	INT:MUX.LH[11][0]
B11	INT:MUX.IMUX_IO_ICE[2][3]	INT:MUX.IMUX_IO_ICE[2][4]	INT:MUX.IMUX_IO_ICE[2][5]	INT:MUX.IMUX_IO_ICE[3][3]	INT:MUX.IMUX_IO_ICE[3][2]	INT:MUX.IMUX_IO_ICE[0][3]	INT:MUX.IMUX_IO_ICE[0][2]	INT:MUX.IMUX_IO_ICE[1][5]	INT:MUX.IMUX_IO_ICE[1][4]	INT:MUX.IMUX_IO_ICE[1][3]	INT:MUX.IMUX_IO_OCE[2][3]	INT:MUX.IMUX_IO_OCE[2][4]	INT:MUX.IMUX_IO_OCE[2][5]	INT:MUX.IMUX_IO_OCE[3][3]	INT:MUX.IMUX_IO_OCE[0][3]	INT:MUX.IMUX_IO_OCE[0][2]	INT:MUX.IMUX_IO_TCE[3][2]	INT:MUX.IMUX_IO_OCE[1][5]	INT:MUX.IMUX_IO_OCE[1][4]	INT:MUX.IMUX_IO_OCE[1][3]	INT:MUX.IMUX_IO_TCE[2][3]	INT:MUX.IMUX_IO_TCE[2][4]	INT:MUX.IMUX_IO_TCE[2][5]	INT:MUX.IMUX_IO_TCE[3][3]	INT:MUX.IMUX_IO_TCE[1][3]	INT:MUX.IMUX_IO_TCE[0][5]	INT:MUX.IMUX_IO_TCE[0][4]	INT:MUX.IMUX_IO_TCE[0][3]	INT:MUX.IMUX_IO_SR[1][0]	INT:MUX.IMUX_IO_SR[1][4]	INT:MUX.IMUX_IO_SR[1][5]	INT:MUX.IMUX_IO_TCE[1][2]	INT:MUX.IMUX_IO_SR[0][1]	INT:MUX.IMUX_IO_SR[0][0]	INT:MUX.IMUX_IO_SR[3][0]	INT:MUX.IMUX_IO_SR[2][5]	INT:MUX.IMUX_IO_SR[2][4]	INT:MUX.IMUX_IO_SR[2][0]	INT:MUX.IMUX_IO_T[1][0]	INT:MUX.IMUX_IO_T[1][4]	INT:MUX.IMUX_IO_T[1][5]	INT:MUX.IMUX_IO_T[0][1]	INT:MUX.IMUX_IO_T[0][0]	INT:MUX.IMUX_IO_T[3][1]	INT:MUX.IMUX_IO_T[3][0]	INT:MUX.IMUX_IO_T[2][5]	INT:MUX.IMUX_IO_T[2][4]	INT:MUX.IMUX_IO_T[2][0]
B10	INT:MUX.IMUX_IO_ICE[2][0]	INT:MUX.IMUX_IO_ICE[3][5]	INT:MUX.IMUX_IO_ICE[3][4]	INT:MUX.IMUX_IO_ICE[3][0]	~INT:INV.IMUX_IO_ICE[2]	~INT:INV.IMUX_IO_ICE[1]	INT:MUX.IMUX_IO_ICE[0][0]	INT:MUX.IMUX_IO_ICE[0][4]	INT:MUX.IMUX_IO_ICE[0][5]	INT:MUX.IMUX_IO_ICE[1][0]	INT:MUX.IMUX_IO_OCE[2][1]	INT:MUX.IMUX_IO_OCE[3][5]	INT:MUX.IMUX_IO_OCE[3][4]	INT:MUX.IMUX_IO_OCE[3][1]	~INT:INV.IMUX_IO_OCE[1]	-	INT:MUX.IMUX_IO_OCE[0][1]	INT:MUX.IMUX_IO_OCE[0][4]	INT:MUX.IMUX_IO_OCE[0][5]	INT:MUX.IMUX_IO_TCE[2][0]	INT:MUX.IMUX_IO_TCE[3][5]	INT:MUX.IMUX_IO_TCE[3][4]	~INT:INV.IMUX_IO_TCE[3]	INT:MUX.IMUX_IO_TCE[3][0]	INT:MUX.IMUX_IO_TCE[1][0]	~INT:INV.IMUX_IO_TCE[1]	INT:MUX.IMUX_IO_TCE[1][4]	INT:MUX.IMUX_IO_TCE[1][5]	INT:MUX.IMUX_IO_TCE[0][0]	INT:MUX.IMUX_IO_SR[0][5]	INT:MUX.IMUX_IO_SR[0][4]	INT:MUX.IMUX_IO_SR[0][3]	-	INT:INV.IMUX_IO_SR[1]	INT:MUX.IMUX_IO_SR[3][3]	INT:MUX.IMUX_IO_SR[3][4]	INT:MUX.IMUX_IO_SR[3][5]	INT:MUX.IMUX_IO_SR[2][3]	INT:MUX.IMUX_IO_T[1][3]	INT:MUX.IMUX_IO_T[0][5]	INT:MUX.IMUX_IO_T[0][4]	INT:MUX.IMUX_IO_T[0][3]	~INT:INV.IMUX_IO_T[1]	~INT:INV.IMUX_IO_T[2]	INT:MUX.IMUX_IO_T[3][3]	INT:MUX.IMUX_IO_T[3][4]	INT:MUX.IMUX_IO_T[3][5]	INT:MUX.IMUX_IO_T[2][3]
B9	INT:MUX.IMUX_IO_ICE[2][2]	INT:MUX.IMUX_IO_ICE[2][1]	INT:MUX.IMUX_IO_ICE[3][1]	~INT:INV.IMUX_IO_ICE[3]	INT:MUX.IMUX_IO_ICE[1][2]	INT:MUX.IMUX_IO_ICE[1][1]	-	INT:MUX.IMUX_IO_ICE[0][1]	INT:MUX.IMUX_IO_OCE[3][2]	INT:MUX.IMUX_IO_OCE[2][0]	~INT:INV.IMUX_IO_OCE[3]	INT:MUX.IMUX_IO_OCE[2][2]	INT:MUX.IMUX_IO_OCE[3][0]	~INT:INV.IMUX_IO_OCE[2]	INT:MUX.IMUX_IO_OCE[0][0]	INT:MUX.IMUX_IO_OCE[1][0]	INT:MUX.IMUX_IO_OCE[1][2]	-	-	INT:MUX.IMUX_IO_OCE[1][1]	INT:MUX.IMUX_IO_TCE[3][1]	INT:MUX.IMUX_IO_TCE[2][1]	INT:MUX.IMUX_IO_TCE[2][2]	~INT:INV.IMUX_IO_TCE[2]	-	INT:MUX.IMUX_IO_TCE[0][2]	INT:MUX.IMUX_IO_TCE[0][1]	INT:MUX.IMUX_IO_TCE[1][1]	INT:MUX.IMUX_IO_SR[1][3]	-	-	INT:MUX.IMUX_IO_SR[1][1]	INT:MUX.IMUX_IO_SR[1][2]	INT:MUX.IMUX_IO_SR[0][2]	INT:INV.IMUX_IO_SR[2]	INT:MUX.IMUX_IO_SR[3][2]	INT:MUX.IMUX_IO_SR[2][1]	INT:INV.IMUX_IO_SR[3]	INT:MUX.IMUX_IO_SR[2][2]	INT:MUX.IMUX_IO_SR[3][1]	INT:MUX.IMUX_IO_T[0][2]	-	INT:MUX.IMUX_IO_T[1][2]	INT:MUX.IMUX_IO_T[1][1]	~INT:INV.IMUX_IO_T[3]	INT:MUX.IMUX_IO_T[3][2]	INT:MUX.IMUX_IO_T[2][2]	INT:MUX.IMUX_IO_T[2][1]
B8	INT:PASS.SINGLE_W[23].HEX_V0[3]	INT:PASS.SINGLE_W[22].HEX_V3[3]	INT:PASS.SINGLE_W[22].OUT_IO_IQ[1]	INT:PASS.SINGLE_W[21].HEX_V6[3]	INT:PASS.SINGLE_W[21].OUT_IO_IQ[2]	INT:PASS.SINGLE_W[21].OUT_TBUF_E[0]	INT:PASS.SINGLE_W[20].OUT_IO_IQ[3]	INT:PASS.SINGLE_W[20].HEX_V0[3]	-	INT:PASS.SINGLE_W[19].HEX_V3[3]	INT:PASS.SINGLE_W[18].OUT_IO_I[1]	INT:PASS.SINGLE_W[18].OUT_TBUF_E[0]	INT:PASS.SINGLE_W[17].HEX_V0[2]	INT:PASS.SINGLE_W[16].HEX_V3[2]	INT:PASS.SINGLE_W[16].OUT_IO_I[3]	INT:PASS.SINGLE_W[15].HEX_V6[2]	-	INT:PASS.SINGLE_W[15].OUT_TBUF_E[1]	INT:PASS.SINGLE_W[14].OUT_IO_IQ[1]	INT:PASS.SINGLE_W[14].HEX_V0[2]	INT:PASS.SINGLE_W[13].OUT_IO_IQ[2]	INT:PASS.SINGLE_W[13].HEX_V3[2]	INT:PASS.SINGLE_W[12].OUT_IO_IQ[3]	INT:PASS.SINGLE_W[12].OUT_TBUF_E[1]	INT:PASS.SINGLE_W[11].HEX_V0[1]	INT:PASS.SINGLE_W[10].HEX_V3[1]	INT:PASS.SINGLE_W[10].OUT_IO_I[1]	INT:PASS.SINGLE_W[9].HEX_V6[1]	INT:PASS.SINGLE_W[9].OUT_IO_I[2]	INT:PASS.SINGLE_W[9].OUT_TBUF_E[2]	INT:PASS.SINGLE_W[8].OUT_IO_I[3]	INT:PASS.SINGLE_W[8].HEX_V0[1]	-	INT:PASS.SINGLE_W[7].HEX_V3[1]	INT:PASS.SINGLE_W[6].OUT_IO_IQ[1]	INT:PASS.SINGLE_W[6].OUT_TBUF_E[2]	INT:PASS.SINGLE_W[5].HEX_V0[0]	INT:PASS.SINGLE_W[4].HEX_V3[0]	INT:PASS.SINGLE_W[4].OUT_IO_IQ[3]	INT:PASS.SINGLE_W[3].HEX_V6[0]	-	INT:PASS.SINGLE_W[3].OUT_TBUF_E[3]	INT:PASS.SINGLE_W[2].OUT_IO_I[1]	INT:PASS.SINGLE_W[2].HEX_V0[0]	INT:PASS.SINGLE_W[1].OUT_IO_I[2]	INT:PASS.SINGLE_W[1].HEX_V3[0]	INT:PASS.SINGLE_W[0].OUT_IO_I[3]	INT:PASS.SINGLE_W[0].OUT_TBUF_E[3]
B7	-	-	-	-	-	-	-	-	-	-	-	INT:PASS.SINGLE_W[18].HEX_V6[3]	INT:PASS.SINGLE_W[17].OUT_IO_I[2]	-	-	-	-	-	-	-	-	-	-	INT:PASS.SINGLE_W[12].HEX_V6[2]	-	-	-	-	-	-	-	-	-	-	-	INT:PASS.SINGLE_W[6].HEX_V6[1]	INT:PASS.SINGLE_W[5].OUT_IO_IQ[2]	-	-	-	-	-	-	-	-	-	-	INT:PASS.SINGLE_W[0].HEX_V6[0]
B6	INT:DRIVE.HEX_V0[3]	INT:MUX.HEX_V6[3][5]	INT:MUX.HEX_V6[3][3]	INT:MUX.HEX_V0[3][1]	INT:MUX.HEX_V0[3][5]	INT:MUX.HEX_V0[3][6]	INT:MUX.HEX_V0[3][4]	INT:MUX.HEX_V0[3][2]	INT:MUX.HEX_V0[3][3]	INT:MUX.HEX_V6[3][0]	INT:MUX.HEX_V6[3][6]	INT:DRIVE.HEX_V6[3]	INT:DRIVE.HEX_V0[2]	INT:MUX.HEX_V6[2][5]	INT:MUX.HEX_V6[2][3]	INT:MUX.HEX_V0[2][1]	INT:MUX.HEX_V0[2][5]	INT:MUX.HEX_V0[2][6]	INT:MUX.HEX_V0[2][4]	INT:MUX.HEX_V0[2][2]	INT:MUX.HEX_V0[2][3]	INT:MUX.HEX_V6[2][0]	INT:MUX.HEX_V6[2][6]	INT:DRIVE.HEX_V6[2]	INT:DRIVE.HEX_V0[1]	INT:MUX.HEX_V6[1][5]	INT:MUX.HEX_V6[1][3]	INT:MUX.HEX_V0[1][1]	INT:MUX.HEX_V0[1][5]	INT:MUX.HEX_V0[1][6]	INT:MUX.HEX_V0[1][4]	INT:MUX.HEX_V0[1][2]	INT:MUX.HEX_V0[1][3]	INT:MUX.HEX_V6[1][0]	INT:MUX.HEX_V6[1][6]	INT:DRIVE.HEX_V6[1]	INT:DRIVE.HEX_V0[0]	INT:MUX.HEX_V6[0][5]	INT:MUX.HEX_V6[0][3]	INT:MUX.HEX_V0[0][1]	INT:MUX.HEX_V0[0][5]	INT:MUX.HEX_V0[0][6]	INT:MUX.HEX_V0[0][4]	INT:MUX.HEX_V0[0][2]	INT:MUX.HEX_V0[0][3]	INT:MUX.HEX_V6[0][0]	INT:MUX.HEX_V6[0][6]	INT:DRIVE.HEX_V6[0]
B5	INT:MUX.HEX_V6[3][2]	INT:MUX.HEX_V0[3][0]	-	-	-	-	-	-	-	-	INT:MUX.HEX_V6[3][4]	INT:MUX.HEX_V6[3][1]	INT:MUX.HEX_V6[2][2]	INT:MUX.HEX_V0[2][0]	-	-	-	-	-	-	-	-	INT:MUX.HEX_V6[2][4]	INT:MUX.HEX_V6[2][1]	INT:MUX.HEX_V6[1][2]	INT:MUX.HEX_V0[1][0]	-	-	-	-	-	-	-	-	INT:MUX.HEX_V6[1][4]	INT:MUX.HEX_V6[1][1]	INT:MUX.HEX_V6[0][2]	INT:MUX.HEX_V0[0][0]	-	-	-	-	-	-	-	-	INT:MUX.HEX_V6[0][4]	INT:MUX.HEX_V6[0][1]
B4	INT:DRIVE.HEX_H6[3]	INT:MUX.HEX_H5[3][3]	INT:MUX.HEX_H6[3][1]	INT:DRIVE.HEX_H5[3]	INT:DRIVE.HEX_H4[3]	-	-	INT:DRIVE.HEX_H3[3]	INT:DRIVE.HEX_H2[3]	-	-	INT:DRIVE.HEX_H1[3]	INT:DRIVE.HEX_H1[2]	-	-	INT:DRIVE.HEX_H2[2]	INT:DRIVE.HEX_H3[2]	-	-	INT:DRIVE.HEX_H4[2]	INT:DRIVE.HEX_H5[2]	INT:MUX.HEX_H6[2][3]	INT:MUX.HEX_H5[2][2]	INT:DRIVE.HEX_H6[2]	INT:DRIVE.HEX_H6[1]	INT:MUX.HEX_H5[1][2]	INT:MUX.HEX_H6[1][3]	INT:DRIVE.HEX_H5[1]	INT:DRIVE.HEX_H4[1]	-	-	INT:DRIVE.HEX_H3[1]	INT:DRIVE.HEX_H2[1]	-	-	INT:DRIVE.HEX_H1[1]	INT:DRIVE.HEX_H1[0]	-	-	INT:DRIVE.HEX_H2[0]	INT:DRIVE.HEX_H3[0]	-	-	INT:DRIVE.HEX_H4[0]	INT:DRIVE.HEX_H5[0]	INT:MUX.HEX_H6[0][2]	INT:MUX.HEX_H5[0][1]	INT:DRIVE.HEX_H6[0]
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	INT:MUX.HEX_H6[3][0]	INT:MUX.HEX_H6[3][5]	INT:MUX.HEX_H6[3][4]	INT:MUX.HEX_H5[3][0]	INT:MUX.HEX_H4[3][2]	INT:MUX.HEX_H3[3][2]	INT:MUX.HEX_H3[3][1]	INT:MUX.HEX_H3[3][0]	INT:MUX.HEX_H2[3][2]	INT:MUX.HEX_H1[3][2]	-	INT:MUX.HEX_H1[3][0]	INT:MUX.HEX_H1[2][0]	INT:MUX.HEX_H1[2][1]	-	-	INT:MUX.HEX_H3[2][0]	INT:MUX.HEX_H3[2][1]	INT:MUX.HEX_H3[2][3]	INT:MUX.HEX_H4[2][3]	INT:MUX.HEX_H5[2][0]	-	INT:MUX.HEX_H6[2][4]	INT:MUX.HEX_H6[2][0]	INT:MUX.HEX_H6[1][0]	INT:MUX.HEX_H6[1][5]	INT:MUX.HEX_H6[1][4]	INT:MUX.HEX_H5[1][0]	INT:MUX.HEX_H4[1][1]	INT:MUX.HEX_H3[1][1]	INT:MUX.HEX_H3[1][2]	INT:MUX.HEX_H3[1][0]	INT:MUX.HEX_H2[1][2]	INT:MUX.HEX_H1[1][2]	-	INT:MUX.HEX_H1[1][0]	INT:MUX.HEX_H1[0][0]	INT:MUX.HEX_H1[0][1]	-	-	INT:MUX.HEX_H3[0][0]	INT:MUX.HEX_H3[0][1]	INT:MUX.HEX_H3[0][3]	INT:MUX.HEX_H4[0][3]	INT:MUX.HEX_H5[0][0]	-	INT:MUX.HEX_H6[0][4]	INT:MUX.HEX_H6[0][0]
B1	INT:MUX.HEX_W0[3][3]	INT:MUX.HEX_W0[3][0]	INT:MUX.HEX_W1[3][0]	INT:MUX.HEX_W1[3][1]	INT:MUX.HEX_W0[3][1]	INT:MUX.HEX_W0[3][2]	INT:MUX.HEX_W1[3][2]	INT:MUX.HEX_W1[3][5]	INT:MUX.HEX_W0[3][5]	INT:MUX.HEX_W0[3][4]	INT:MUX.HEX_W1[3][4]	INT:MUX.HEX_W1[3][3]	INT:MUX.HEX_W0[1][3]	INT:MUX.HEX_W0[1][1]	INT:MUX.HEX_W1[1][1]	INT:MUX.HEX_W1[1][2]	INT:MUX.HEX_W0[1][2]	INT:MUX.HEX_W0[1][0]	INT:MUX.HEX_W1[1][0]	INT:MUX.HEX_W1[1][5]	INT:MUX.HEX_W0[1][5]	INT:MUX.HEX_W0[1][4]	INT:MUX.HEX_W1[1][4]	INT:MUX.HEX_W1[1][3]	INT:MUX.HEX_W0[2][3]	INT:MUX.HEX_W0[2][2]	INT:MUX.HEX_W1[2][2]	INT:MUX.HEX_W1[2][0]	INT:MUX.HEX_W0[2][0]	INT:MUX.HEX_W0[2][1]	INT:MUX.HEX_W1[2][1]	INT:MUX.HEX_W1[2][5]	INT:MUX.HEX_W0[2][5]	INT:MUX.HEX_W0[2][4]	INT:MUX.HEX_W1[2][4]	INT:MUX.HEX_W1[2][3]	INT:MUX.HEX_W0[0][3]	INT:MUX.HEX_W0[0][0]	INT:MUX.HEX_W1[0][0]	INT:MUX.HEX_W1[0][1]	INT:MUX.HEX_W0[0][1]	INT:MUX.HEX_W0[0][2]	INT:MUX.HEX_W1[0][2]	-	-	-	-	INT:MUX.HEX_W1[0][3]
B0	INT:MUX.HEX_H6[3][3]	INT:MUX.HEX_H6[3][2]	INT:MUX.HEX_H5[3][2]	INT:MUX.HEX_H5[3][1]	INT:MUX.HEX_H4[3][0]	-	-	INT:MUX.HEX_H4[3][1]	INT:MUX.HEX_H2[3][0]	INT:MUX.HEX_H1[3][1]	INT:MUX.HEX_H2[3][1]	-	INT:MUX.HEX_H2[2][1]	INT:MUX.HEX_H2[2][2]	INT:MUX.HEX_H1[2][2]	INT:MUX.HEX_H2[2][0]	INT:MUX.HEX_H4[2][1]	INT:MUX.HEX_H4[2][2]	INT:MUX.HEX_H3[2][2]	INT:MUX.HEX_H4[2][0]	INT:MUX.HEX_H5[2][1]	-	INT:MUX.HEX_H6[2][1]	INT:MUX.HEX_H6[2][2]	INT:MUX.HEX_H6[1][2]	INT:MUX.HEX_H6[1][1]	INT:MUX.HEX_H5[1][1]	-	INT:MUX.HEX_H4[1][0]	-	-	INT:MUX.HEX_H4[1][2]	INT:MUX.HEX_H2[1][0]	INT:MUX.HEX_H1[1][1]	INT:MUX.HEX_H2[1][1]	-	INT:MUX.HEX_H2[0][1]	INT:MUX.HEX_H2[0][2]	INT:MUX.HEX_H1[0][2]	INT:MUX.HEX_H2[0][0]	INT:MUX.HEX_H4[0][1]	INT:MUX.HEX_H4[0][2]	INT:MUX.HEX_H3[0][2]	INT:MUX.HEX_H4[0][0]	INT:MUX.HEX_H5[0][2]	-	INT:MUX.HEX_H6[0][3]	INT:MUX.HEX_H6[0][1]

INT:DRIVE.HEX_H1[0]	0.F36.B4
INT:DRIVE.HEX_H1[1]	0.F35.B4
INT:DRIVE.HEX_H1[2]	0.F12.B4
INT:DRIVE.HEX_H1[3]	0.F11.B4
INT:DRIVE.HEX_H2[0]	0.F39.B4
INT:DRIVE.HEX_H2[1]	0.F32.B4
INT:DRIVE.HEX_H2[2]	0.F15.B4
INT:DRIVE.HEX_H2[3]	0.F8.B4
INT:DRIVE.HEX_H3[0]	0.F40.B4
INT:DRIVE.HEX_H3[1]	0.F31.B4
INT:DRIVE.HEX_H3[2]	0.F16.B4
INT:DRIVE.HEX_H3[3]	0.F7.B4
INT:DRIVE.HEX_H4[0]	0.F43.B4
INT:DRIVE.HEX_H4[1]	0.F28.B4
INT:DRIVE.HEX_H4[2]	0.F19.B4
INT:DRIVE.HEX_H4[3]	0.F4.B4
INT:DRIVE.HEX_H5[0]	0.F44.B4
INT:DRIVE.HEX_H5[1]	0.F27.B4
INT:DRIVE.HEX_H5[2]	0.F20.B4
INT:DRIVE.HEX_H5[3]	0.F3.B4
INT:DRIVE.HEX_H6[0]	0.F47.B4
INT:DRIVE.HEX_H6[1]	0.F24.B4
INT:DRIVE.HEX_H6[2]	0.F23.B4
INT:DRIVE.HEX_H6[3]	0.F0.B4
INT:DRIVE.HEX_V0[0]	0.F36.B6
INT:DRIVE.HEX_V0[1]	0.F24.B6
INT:DRIVE.HEX_V0[2]	0.F12.B6
INT:DRIVE.HEX_V0[3]	0.F0.B6
INT:DRIVE.HEX_V6[0]	0.F47.B6
INT:DRIVE.HEX_V6[1]	0.F35.B6
INT:DRIVE.HEX_V6[2]	0.F23.B6
INT:DRIVE.HEX_V6[3]	0.F11.B6
INT:DRIVE.LH[0]	0.F26.B12
INT:DRIVE.LH[10]	0.F42.B12
INT:DRIVE.LH[11]	0.F45.B12
INT:DRIVE.LH[1]	0.F21.B12
INT:DRIVE.LH[2]	0.F18.B12
INT:DRIVE.LH[3]	0.F13.B12
INT:DRIVE.LH[4]	0.F10.B12
INT:DRIVE.LH[5]	0.F5.B12
INT:DRIVE.LH[6]	0.F2.B12
INT:DRIVE.LH[7]	0.F29.B12
INT:DRIVE.LH[8]	0.F34.B12
INT:DRIVE.LH[9]	0.F37.B12
INT:DRIVE.LV[0]	0.F2.B15
INT:DRIVE.LV[6]	0.F10.B15
INT:INV.IMUX_IO_SR[1]	0.F33.B10
INT:INV.IMUX_IO_SR[2]	0.F34.B9
INT:INV.IMUX_IO_SR[3]	0.F37.B9
INT:INV.IMUX_TBUF_T[0]	0.F25.B15
INT:INV.IMUX_TBUF_T[1]	0.F31.B15
INT:PASS.SINGLE_W[0].HEX_V6[0]	0.F47.B7
INT:PASS.SINGLE_W[0].OUT_IO_I[3]	0.F46.B8
INT:PASS.SINGLE_W[0].OUT_TBUF_E[3]	0.F47.B8
INT:PASS.SINGLE_W[10].HEX_V3[1]	0.F25.B8
INT:PASS.SINGLE_W[10].OUT_IO_I[1]	0.F26.B8
INT:PASS.SINGLE_W[11].HEX_V0[1]	0.F24.B8
INT:PASS.SINGLE_W[12].HEX_V6[2]	0.F23.B7
INT:PASS.SINGLE_W[12].OUT_IO_IQ[3]	0.F22.B8
INT:PASS.SINGLE_W[12].OUT_TBUF_E[1]	0.F23.B8
INT:PASS.SINGLE_W[13].HEX_V3[2]	0.F21.B8
INT:PASS.SINGLE_W[13].OUT_IO_IQ[2]	0.F20.B8
INT:PASS.SINGLE_W[14].HEX_V0[2]	0.F19.B8
INT:PASS.SINGLE_W[14].OUT_IO_IQ[1]	0.F18.B8
INT:PASS.SINGLE_W[15].HEX_V6[2]	0.F15.B8
INT:PASS.SINGLE_W[15].OUT_TBUF_E[1]	0.F17.B8
INT:PASS.SINGLE_W[16].HEX_V3[2]	0.F13.B8
INT:PASS.SINGLE_W[16].OUT_IO_I[3]	0.F14.B8
INT:PASS.SINGLE_W[17].HEX_V0[2]	0.F12.B8
INT:PASS.SINGLE_W[17].OUT_IO_I[2]	0.F12.B7
INT:PASS.SINGLE_W[18].HEX_V6[3]	0.F11.B7
INT:PASS.SINGLE_W[18].OUT_IO_I[1]	0.F10.B8
INT:PASS.SINGLE_W[18].OUT_TBUF_E[0]	0.F11.B8
INT:PASS.SINGLE_W[19].HEX_V3[3]	0.F9.B8
INT:PASS.SINGLE_W[1].HEX_V3[0]	0.F45.B8
INT:PASS.SINGLE_W[1].OUT_IO_I[2]	0.F44.B8
INT:PASS.SINGLE_W[20].HEX_V0[3]	0.F7.B8
INT:PASS.SINGLE_W[20].OUT_IO_IQ[3]	0.F6.B8
INT:PASS.SINGLE_W[21].HEX_V6[3]	0.F3.B8
INT:PASS.SINGLE_W[21].OUT_IO_IQ[2]	0.F4.B8
INT:PASS.SINGLE_W[21].OUT_TBUF_E[0]	0.F5.B8
INT:PASS.SINGLE_W[22].HEX_V3[3]	0.F1.B8
INT:PASS.SINGLE_W[22].OUT_IO_IQ[1]	0.F2.B8
INT:PASS.SINGLE_W[23].HEX_V0[3]	0.F0.B8
INT:PASS.SINGLE_W[2].HEX_V0[0]	0.F43.B8
INT:PASS.SINGLE_W[2].OUT_IO_I[1]	0.F42.B8
INT:PASS.SINGLE_W[3].HEX_V6[0]	0.F39.B8
INT:PASS.SINGLE_W[3].OUT_TBUF_E[3]	0.F41.B8
INT:PASS.SINGLE_W[4].HEX_V3[0]	0.F37.B8
INT:PASS.SINGLE_W[4].OUT_IO_IQ[3]	0.F38.B8
INT:PASS.SINGLE_W[5].HEX_V0[0]	0.F36.B8
INT:PASS.SINGLE_W[5].OUT_IO_IQ[2]	0.F36.B7
INT:PASS.SINGLE_W[6].HEX_V6[1]	0.F35.B7
INT:PASS.SINGLE_W[6].OUT_IO_IQ[1]	0.F34.B8
INT:PASS.SINGLE_W[6].OUT_TBUF_E[2]	0.F35.B8
INT:PASS.SINGLE_W[7].HEX_V3[1]	0.F33.B8
INT:PASS.SINGLE_W[8].HEX_V0[1]	0.F31.B8
INT:PASS.SINGLE_W[8].OUT_IO_I[3]	0.F30.B8
INT:PASS.SINGLE_W[9].HEX_V6[1]	0.F27.B8
INT:PASS.SINGLE_W[9].OUT_IO_I[2]	0.F28.B8
INT:PASS.SINGLE_W[9].OUT_TBUF_E[2]	0.F29.B8
IO[1]:IFF_DELAY_ENABLE	0.F9.B17
IO[1]:IFF_INIT	0.F1.B16
IO[1]:IFF_LATCH	0.F3.B16
IO[1]:IFF_SR_ENABLE	0.F4.B16
IO[1]:IFF_SR_SYNC	0.F0.B16
IO[1]:INV.IFF.CLK	0.F34.B14
IO[1]:INV.OFF.CLK	0.F33.B14
IO[1]:INV.TFF.CLK	0.F32.B14
IO[1]:I_DELAY_ENABLE	0.F2.B16
IO[1]:OFF_LATCH	0.F6.B16
IO[1]:OFF_SR_ENABLE	0.F5.B16
IO[1]:OFF_SR_SYNC	0.F9.B16
IO[1]:READBACK_IFF	0.F2.B17
IO[1]:READBACK_OFF	0.F8.B17
IO[1]:READBACK_TFF	0.F12.B17
IO[1]:TFF_LATCH	0.F13.B16
IO[1]:TFF_SR_ENABLE	0.F14.B16
IO[1]:TFF_SR_SYNC	0.F10.B16
IO[2]:IFF_DELAY_ENABLE	0.F20.B17
IO[2]:IFF_INIT	0.F28.B16
IO[2]:IFF_LATCH	0.F26.B16
IO[2]:IFF_SR_ENABLE	0.F25.B16
IO[2]:IFF_SR_SYNC	0.F29.B16
IO[2]:INV.IFF.CLK	0.F13.B14
IO[2]:INV.OFF.CLK	0.F14.B14
IO[2]:INV.TFF.CLK	0.F15.B14
IO[2]:I_DELAY_ENABLE	0.F27.B16
IO[2]:OFF_LATCH	0.F23.B16
IO[2]:OFF_SR_ENABLE	0.F24.B16
IO[2]:OFF_SR_SYNC	0.F20.B16
IO[2]:READBACK_IFF	0.F27.B17
IO[2]:READBACK_OFF	0.F21.B17
IO[2]:READBACK_TFF	0.F17.B17
IO[2]:TFF_LATCH	0.F16.B16
IO[2]:TFF_SR_ENABLE	0.F15.B16
IO[2]:TFF_SR_SYNC	0.F19.B16
IO[3]:IFF_DELAY_ENABLE	0.F39.B17
IO[3]:IFF_INIT	0.F31.B16
IO[3]:IFF_LATCH	0.F33.B16
IO[3]:IFF_SR_ENABLE	0.F34.B16
IO[3]:IFF_SR_SYNC	0.F30.B16
IO[3]:INV.IFF.CLK	0.F10.B14
IO[3]:INV.OFF.CLK	0.F11.B14
IO[3]:INV.TFF.CLK	0.F12.B14
IO[3]:I_DELAY_ENABLE	0.F32.B16
IO[3]:OFF_LATCH	0.F36.B16
IO[3]:OFF_SR_ENABLE	0.F35.B16
IO[3]:OFF_SR_SYNC	0.F39.B16
IO[3]:READBACK_IFF	0.F32.B17
IO[3]:READBACK_OFF	0.F38.B17
IO[3]:READBACK_TFF	0.F42.B17
IO[3]:TFF_LATCH	0.F43.B16
IO[3]:TFF_SR_ENABLE	0.F44.B16
IO[3]:TFF_SR_SYNC	0.F40.B16
non-inverted	[0]

INT:INV.IMUX_IO_ICE[1]	0.F5.B10
INT:INV.IMUX_IO_ICE[2]	0.F4.B10
INT:INV.IMUX_IO_ICE[3]	0.F3.B9
INT:INV.IMUX_IO_OCE[1]	0.F14.B10
INT:INV.IMUX_IO_OCE[2]	0.F13.B9
INT:INV.IMUX_IO_OCE[3]	0.F10.B9
INT:INV.IMUX_IO_O[1]	0.F38.B14
INT:INV.IMUX_IO_O[2]	0.F9.B14
INT:INV.IMUX_IO_O[3]	0.F0.B14
INT:INV.IMUX_IO_TCE[1]	0.F25.B10
INT:INV.IMUX_IO_TCE[2]	0.F23.B9
INT:INV.IMUX_IO_TCE[3]	0.F22.B10
INT:INV.IMUX_IO_T[1]	0.F42.B10
INT:INV.IMUX_IO_T[2]	0.F43.B10
INT:INV.IMUX_IO_T[3]	0.F44.B9
INT:INV.IMUX_TBUF_I[0]	0.F18.B15
INT:INV.IMUX_TBUF_I[1]	0.F23.B15
IO[1]:OFF_INIT	0.F8.B16
IO[1]:SHORTEN_JTAG_CHAIN	0.F10.B17
IO[1]:TFF_INIT	0.F11.B16
IO[2]:OFF_INIT	0.F21.B16
IO[2]:SHORTEN_JTAG_CHAIN	0.F19.B17
IO[2]:TFF_INIT	0.F18.B16
IO[3]:OFF_INIT	0.F38.B16
IO[3]:SHORTEN_JTAG_CHAIN	0.F40.B17
IO[3]:TFF_INIT	0.F41.B16
TBUF[0]:OUT_A	0.F47.B15
TBUF[0]:OUT_B	0.F46.B15
TBUF[1]:OUT_A	0.F44.B15
TBUF[1]:OUT_B	0.F45.B15
inverted	~[0]

INT:MUX.HEX_H1[0]	0.F38.B0	0.F37.B2	0.F36.B2
LH[5]	0	0	0
NONE	0	0	1
OUT_IO_I[2]	0	1	1
OUT_IO_I[3]	1	0	1

INT:MUX.HEX_H1[1]	0.F33.B2	0.F33.B0	0.F35.B2
LH[5]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_H1[2]	0.F14.B0	0.F13.B2	0.F12.B2
LH[11]	0	0	0
NONE	0	0	1
OUT_IO_IQ[2]	0	1	1
OUT_IO_IQ[3]	1	0	1

INT:MUX.HEX_H1[3]	0.F9.B2	0.F9.B0	0.F11.B2
LH[11]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_H2[0]	0.F37.B0	0.F36.B0	0.F39.B0
LH[4]	0	0	0
NONE	0	0	1
OUT_IO_I[2]	0	1	1
OUT_IO_I[3]	1	0	1

INT:MUX.HEX_H2[1]	0.F32.B2	0.F34.B0	0.F32.B0
LH[4]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_H2[2]	0.F13.B0	0.F12.B0	0.F15.B0
LH[10]	0	0	0
NONE	0	0	1
OUT_IO_IQ[2]	0	1	1
OUT_IO_IQ[3]	1	0	1

INT:MUX.HEX_H2[3]	0.F8.B2	0.F10.B0	0.F8.B0
LH[10]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_H3[0]	0.F42.B2	0.F42.B0	0.F41.B2	0.F40.B2
LH[3]	0	0	0	0
NONE	0	0	0	1
OUT_IO_IQ[1]	0	0	1	1
OUT_IO_IQ[2]	0	1	0	1
OUT_IO_IQ[3]	1	0	0	1

INT:MUX.HEX_H3[1]	0.F30.B2	0.F29.B2	0.F31.B2
LH[3]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_IQ[3]	1	0	1

INT:MUX.HEX_H3[2]	0.F18.B2	0.F18.B0	0.F17.B2	0.F16.B2
LH[9]	0	0	0	0
NONE	0	0	0	1
OUT_IO_I[1]	0	0	1	1
OUT_IO_I[2]	0	1	0	1
OUT_IO_I[3]	1	0	0	1

INT:MUX.HEX_H3[3]	0.F5.B2	0.F6.B2	0.F7.B2
LH[9]	0	0	0
NONE	0	0	1
OUT_IO_I[3]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_H4[0]	0.F43.B2	0.F41.B0	0.F40.B0	0.F43.B0
LH[2]	0	0	0	0
NONE	0	0	0	1
OUT_IO_IQ[1]	0	0	1	1
OUT_IO_IQ[2]	0	1	0	1
OUT_IO_IQ[3]	1	0	0	1

INT:MUX.HEX_H4[1]	0.F31.B0	0.F28.B2	0.F28.B0
LH[2]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_IQ[3]	1	0	1

INT:MUX.HEX_H4[2]	0.F19.B2	0.F17.B0	0.F16.B0	0.F19.B0
LH[8]	0	0	0	0
NONE	0	0	0	1
OUT_IO_I[1]	0	0	1	1
OUT_IO_I[2]	0	1	0	1
OUT_IO_I[3]	1	0	0	1

INT:MUX.HEX_H4[3]	0.F4.B2	0.F7.B0	0.F4.B0
LH[8]	0	0	0
NONE	0	0	1
OUT_IO_I[3]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_H5[0]	0.F44.B0	0.F46.B4	0.F44.B2
LH[1]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_H5[1]	0.F25.B4	0.F26.B0	0.F27.B2
LH[1]	0	0	0
NONE	0	0	1
OUT_IO_I[2]	0	1	1
OUT_IO_I[3]	1	0	1

INT:MUX.HEX_H5[2]	0.F22.B4	0.F20.B0	0.F20.B2
LH[7]	0	0	0
NONE	0	0	1
OUT_IO_I[3]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_H5[3]	0.F1.B4	0.F2.B0	0.F3.B0	0.F3.B2
LH[7]	0	0	0	0
NONE	0	0	0	1
OUT_IO_I[2]	0	0	1	1
OUT_IO_IQ[2]	0	1	0	1
OUT_IO_IQ[3]	1	0	0	1

INT:MUX.HEX_H6[0]	0.F46.B2	0.F46.B0	0.F45.B4	0.F47.B0	0.F47.B2
HEX_V0[1]	0	0	1	1	1
HEX_V3[3]	0	1	0	1	1
HEX_V6[0]	0	1	1	0	1
LH[0]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_I[1]	1	1	1	1	1

INT:MUX.HEX_H6[1]	0.F25.B2	0.F26.B2	0.F26.B4	0.F24.B0	0.F25.B0	0.F24.B2
HEX_V0[2]	0	0	0	1	1	1
HEX_V3[0]	0	0	1	0	1	1
HEX_V6[1]	0	0	1	1	0	1
LH[0]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_I[3]	1	0	1	1	1	1

INT:MUX.HEX_H6[2]	0.F22.B2	0.F21.B4	0.F23.B0	0.F22.B0	0.F23.B2
HEX_V0[3]	0	0	1	1	1
HEX_V3[1]	0	1	0	1	1
HEX_V6[2]	0	1	1	0	1
LH[6]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_IQ[1]	1	1	1	1	1

INT:MUX.HEX_H6[3]	0.F1.B2	0.F2.B2	0.F0.B0	0.F1.B0	0.F2.B4	0.F0.B2
HEX_V0[0]	0	0	0	1	1	1
HEX_V3[2]	0	0	1	0	1	1
HEX_V6[3]	0	0	1	1	0	1
LH[6]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_IQ[2]	0	1	1	1	1	1
OUT_IO_IQ[3]	1	0	1	1	1	1

INT:MUX.HEX_V0[0]	0.F41.B6	0.F40.B6	0.F42.B6	0.F44.B6	0.F43.B6	0.F39.B6	0.F37.B5
HEX_H3[2]	0	0	0	0	0	0	1
HEX_H6[3]	0	0	0	0	0	1	0
HEX_V6[0]	0	0	0	0	1	0	0
LV[0]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	0	1
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	0	1
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V0[1]	0.F29.B6	0.F28.B6	0.F30.B6	0.F32.B6	0.F31.B6	0.F27.B6	0.F25.B5
HEX_H3[3]	0	0	0	0	0	0	1
HEX_H6[0]	0	0	0	0	0	1	0
HEX_V6[1]	0	0	0	0	1	0	0
LV[0]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	0	1
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	0	1
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V0[2]	0.F17.B6	0.F16.B6	0.F18.B6	0.F20.B6	0.F19.B6	0.F15.B6	0.F13.B5
HEX_H3[0]	0	0	0	0	0	0	1
HEX_H6[1]	0	0	0	0	0	1	0
HEX_V6[2]	0	0	0	0	1	0	0
LV[6]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	0	1
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	0	1
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V0[3]	0.F5.B6	0.F4.B6	0.F6.B6	0.F8.B6	0.F7.B6	0.F3.B6	0.F1.B5
HEX_H3[1]	0	0	0	0	0	0	1
HEX_H6[2]	0	0	0	0	0	1	0
HEX_V6[3]	0	0	0	0	1	0	0
LV[6]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	0	1
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	0	1
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V6[0]	0.F46.B6	0.F37.B6	0.F46.B5	0.F38.B6	0.F36.B5	0.F47.B5	0.F45.B6
HEX_H3[2]	0	0	0	0	0	0	1
HEX_H6[0]	0	0	0	0	0	1	0
HEX_V0[0]	0	0	0	0	1	0	0
LV[0]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	0	1
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	0	1
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V6[1]	0.F34.B6	0.F25.B6	0.F34.B5	0.F26.B6	0.F24.B5	0.F35.B5	0.F33.B6
HEX_H3[3]	0	0	0	0	0	0	1
HEX_H6[1]	0	0	0	0	0	1	0
HEX_V0[1]	0	0	0	0	1	0	0
LV[0]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	0	1
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	0	1
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V6[2]	0.F22.B6	0.F13.B6	0.F22.B5	0.F14.B6	0.F12.B5	0.F23.B5	0.F21.B6
HEX_H3[0]	0	0	0	0	0	0	1
HEX_H6[2]	0	0	0	0	0	1	0
HEX_V0[2]	0	0	0	0	1	0	0
LV[6]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	0	1
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	0	1
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_V6[3]	0.F10.B6	0.F1.B6	0.F10.B5	0.F2.B6	0.F0.B5	0.F11.B5	0.F9.B6
HEX_H3[1]	0	0	0	0	0	0	1
HEX_H6[3]	0	0	0	0	0	1	0
HEX_V0[3]	0	0	0	0	1	0	0
LV[6]	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	0	1
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[3]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	0	1
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	1	0	0

INT:MUX.HEX_W0[0]	0.F36.B1	0.F41.B1	0.F40.B1	0.F37.B1
HEX_E1[0]	0	1	1	1
HEX_V0[2]	1	0	1	1
HEX_V3[1]	1	1	0	1
HEX_V6[0]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_W0[1]	0.F20.B1	0.F21.B1	0.F12.B1	0.F16.B1	0.F13.B1	0.F17.B1
HEX_E1[1]	0	0	0	1	1	1
HEX_V0[1]	0	0	1	0	1	1
HEX_V3[0]	0	0	1	1	0	1
HEX_V6[3]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[1]	0	1	1	1	1	1
OUT_IO_IQ[1]	1	0	1	1	1	1

INT:MUX.HEX_W0[2]	0.F32.B1	0.F33.B1	0.F24.B1	0.F25.B1	0.F29.B1	0.F28.B1
HEX_E1[2]	0	0	0	1	1	1
HEX_V0[0]	0	0	1	0	1	1
HEX_V3[3]	0	0	1	1	0	1
HEX_V6[2]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_IQ[2]	1	0	1	1	1	1

INT:MUX.HEX_W0[3]	0.F8.B1	0.F9.B1	0.F0.B1	0.F5.B1	0.F4.B1	0.F1.B1
HEX_E1[3]	0	0	0	1	1	1
HEX_V0[3]	0	0	1	0	1	1
HEX_V3[2]	0	0	1	1	0	1
HEX_V6[1]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[3]	0	1	1	1	1	1
OUT_IO_IQ[3]	1	0	1	1	1	1

INT:MUX.HEX_W1[0]	0.F47.B1	0.F42.B1	0.F39.B1	0.F38.B1
HEX_E2[0]	0	1	1	1
HEX_V0[2]	1	0	1	1
HEX_V3[1]	1	1	0	1
HEX_V6[0]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_W1[1]	0.F19.B1	0.F22.B1	0.F23.B1	0.F15.B1	0.F14.B1	0.F18.B1
HEX_E2[1]	0	0	0	1	1	1
HEX_V0[1]	0	0	1	0	1	1
HEX_V3[0]	0	0	1	1	0	1
HEX_V6[3]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[1]	0	1	1	1	1	1
OUT_IO_IQ[1]	1	0	1	1	1	1

INT:MUX.HEX_W1[2]	0.F31.B1	0.F34.B1	0.F35.B1	0.F26.B1	0.F30.B1	0.F27.B1
HEX_E2[2]	0	0	0	1	1	1
HEX_V0[0]	0	0	1	0	1	1
HEX_V3[3]	0	0	1	1	0	1
HEX_V6[2]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_IQ[2]	1	0	1	1	1	1

INT:MUX.HEX_W1[3]	0.F7.B1	0.F10.B1	0.F11.B1	0.F6.B1	0.F3.B1	0.F2.B1
HEX_E2[3]	0	0	0	1	1	1
HEX_V0[3]	0	0	1	0	1	1
HEX_V3[2]	0	0	1	1	0	1
HEX_V6[1]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[3]	0	1	1	1	1	1
OUT_IO_IQ[3]	1	0	1	1	1	1

INT:MUX.IMUX_IO_CLK[0]	0.F30.B12	0.F30.B14	0.F29.B14	0.F36.B13	0.F26.B14	0.F30.B13	0.F24.B13	0.F25.B14	0.F25.B13	0.F27.B13	0.F27.B14
INT:MUX.IMUX_IO_CLK[1]	0.F28.B14	0.F31.B14	0.F28.B13	0.F33.B13	0.F25.B12	0.F24.B14	0.F31.B13	0.F34.B13	0.F26.B13	0.F32.B13	0.F29.B13
INT:MUX.IMUX_IO_CLK[2]	0.F19.B14	0.F16.B14	0.F19.B13	0.F14.B13	0.F22.B12	0.F23.B14	0.F16.B13	0.F13.B13	0.F21.B13	0.F15.B13	0.F18.B13
INT:MUX.IMUX_IO_CLK[3]	0.F17.B12	0.F17.B14	0.F18.B14	0.F11.B13	0.F21.B14	0.F17.B13	0.F23.B13	0.F22.B14	0.F22.B13	0.F20.B13	0.F20.B14
GCLK[0]	0	0	0	0	0	0	1	1	1	1	1
GCLK[1]	0	0	0	0	0	1	0	1	1	1	1
GCLK[2]	0	0	0	0	0	1	1	0	1	1	1
GCLK[3]	0	0	0	0	0	1	1	1	0	1	1
NONE	0	0	0	0	0	1	1	1	1	1	1
HEX_V5_BUF[2]	0	0	0	1	0	1	1	1	1	1	0
SINGLE_W_BUF[8]	0	0	0	1	1	1	1	1	1	1	1
HEX_V1_BUF[2]	0	0	1	0	0	1	1	1	1	0	1
HEX_V4_BUF[2]	0	0	1	0	0	1	1	1	1	1	0
SINGLE_W_BUF[9]	0	0	1	0	1	1	1	1	1	1	1
HEX_V6_BUF[2]	0	1	0	0	0	1	1	1	1	1	0
SINGLE_W_BUF[14]	0	1	0	0	1	1	1	1	1	1	1
HEX_V2_BUF[2]	1	0	0	0	0	1	1	1	1	0	1
HEX_V3_BUF[2]	1	0	0	0	0	1	1	1	1	1	0
SINGLE_W_BUF[15]	1	0	0	0	1	1	1	1	1	1	1

INT:MUX.IMUX_IO_ICE[0]	0.F8.B10	0.F7.B10	0.F5.B11	0.F6.B11	0.F7.B9	0.F6.B10
INT:MUX.IMUX_IO_ICE[1]	0.F7.B11	0.F8.B11	0.F9.B11	0.F4.B9	0.F5.B9	0.F9.B10
INT:MUX.IMUX_IO_ICE[2]	0.F2.B11	0.F1.B11	0.F0.B11	0.F0.B9	0.F1.B9	0.F0.B10
INT:MUX.IMUX_IO_ICE[3]	0.F1.B10	0.F2.B10	0.F3.B11	0.F4.B11	0.F2.B9	0.F3.B10
NONE	0	0	0	0	0	0
SINGLE_W_BUF[20]	0	0	0	0	0	1
SINGLE_W_BUF[21]	0	0	0	0	1	0
SINGLE_W_BUF[22]	0	0	0	1	0	0
SINGLE_W_BUF[23]	0	0	1	0	0	0
HEX_V4_BUF[3]	0	1	0	1	0	0
HEX_V1_BUF[3]	0	1	1	0	0	0
HEX_V6_BUF[3]	1	1	0	0	0	1
HEX_V5_BUF[3]	1	1	0	0	1	0
HEX_V3_BUF[3]	1	1	0	1	0	0
HEX_V2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_OCE[0]	0.F18.B10	0.F17.B10	0.F14.B11	0.F15.B11	0.F16.B10	0.F14.B9
INT:MUX.IMUX_IO_OCE[1]	0.F17.B11	0.F18.B11	0.F19.B11	0.F16.B9	0.F19.B9	0.F15.B9
INT:MUX.IMUX_IO_OCE[2]	0.F12.B11	0.F11.B11	0.F10.B11	0.F11.B9	0.F10.B10	0.F9.B9
INT:MUX.IMUX_IO_OCE[3]	0.F11.B10	0.F12.B10	0.F13.B11	0.F8.B9	0.F13.B10	0.F12.B9
NONE	0	0	0	0	0	0
SINGLE_W_BUF[17]	0	0	0	0	0	1
SINGLE_W_BUF[16]	0	0	0	0	1	0
SINGLE_W_BUF[18]	0	0	0	1	0	0
SINGLE_W_BUF[19]	0	0	1	0	0	0
PCI_CE	0	1	0	0	0	1
HEX_V4_BUF[3]	0	1	0	1	0	0
HEX_V1_BUF[3]	0	1	1	0	0	0
HEX_V5_BUF[3]	1	1	0	0	0	1
HEX_V6_BUF[3]	1	1	0	0	1	0
HEX_V3_BUF[3]	1	1	0	1	0	0
HEX_V2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_O[0]	0.F41.B13	0.F42.B13	0.F47.B13	0.F46.B13	0.F45.B14	0.F44.B13	0.F43.B13	0.F44.B14	0.F45.B13	0.F46.B14
NONE	0	0	0	0	0	0	0	0	1	1
HEX_H6_BUF[0]	0	0	0	0	0	0	1	0	0	1
OMUX_E1	0	0	0	0	0	0	1	0	1	0
SINGLE_W_BUF[0]	0	0	0	0	0	0	1	1	1	1
HEX_H3_BUF[0]	0	0	0	0	0	1	0	0	0	1
OMUX_E0	0	0	0	0	0	1	0	0	1	0
SINGLE_W_BUF[1]	0	0	0	0	0	1	0	1	1	1
SINGLE_W_BUF[3]	0	0	0	0	1	0	1	0	1	1
SINGLE_W_BUF[2]	0	0	0	0	1	1	0	0	1	1
HEX_H5_BUF[0]	0	0	0	1	0	0	0	0	0	1
OUT_TBUF_E[2]	0	0	0	1	0	0	0	0	1	0
SINGLE_W_BUF[9]	0	0	0	1	0	0	0	1	1	1
SINGLE_W_BUF[4]	0	0	0	1	1	0	0	0	1	1
HEX_H4_BUF[0]	0	0	1	0	0	0	0	0	0	1
OUT_TBUF_E[3]	0	0	1	0	0	0	0	0	1	0
SINGLE_W_BUF[8]	0	0	1	0	0	0	0	1	1	1
SINGLE_W_BUF[5]	0	0	1	0	1	0	0	0	1	1
OUT_TBUF_E[0]	0	1	0	0	0	0	0	0	1	0
SINGLE_W_BUF[6]	0	1	0	0	0	0	0	1	1	1
SINGLE_W_BUF[10]	0	1	0	0	1	0	0	0	1	1
OUT_TBUF_E[1]	1	0	0	0	0	0	0	0	1	0
SINGLE_W_BUF[7]	1	0	0	0	0	0	0	1	1	1
SINGLE_W_BUF[11]	1	0	0	0	1	0	0	0	1	1

INT:MUX.IMUX_IO_O[1]	0.F43.B14	0.F42.B14	0.F43.B12	0.F41.B12	0.F41.B14	0.F39.B13	0.F38.B13	0.F40.B14	0.F40.B13	0.F39.B14
NONE	0	0	0	0	0	0	0	0	1	1
HEX_H4_BUF[1]	0	0	0	0	0	0	1	0	0	1
OMUX_E1	0	0	0	0	0	0	1	0	1	0
SINGLE_W_BUF[0]	0	0	0	0	0	0	1	1	1	1
HEX_H3_BUF[1]	0	0	0	0	0	1	0	0	0	1
OMUX_E0	0	0	0	0	0	1	0	0	1	0
SINGLE_W_BUF[1]	0	0	0	0	0	1	0	1	1	1
SINGLE_W_BUF[3]	0	0	0	0	1	0	1	0	1	1
SINGLE_W_BUF[2]	0	0	0	0	1	1	0	0	1	1
HEX_H5_BUF[1]	0	0	0	1	0	0	0	0	0	1
OUT_TBUF_E[2]	0	0	0	1	0	0	0	0	1	0
SINGLE_W_BUF[9]	0	0	0	1	0	0	0	1	1	1
SINGLE_W_BUF[4]	0	0	0	1	1	0	0	0	1	1
HEX_H6_BUF[1]	0	0	1	0	0	0	0	0	0	1
OUT_TBUF_E[3]	0	0	1	0	0	0	0	0	1	0
SINGLE_W_BUF[8]	0	0	1	0	0	0	0	1	1	1
SINGLE_W_BUF[5]	0	0	1	0	1	0	0	0	1	1
OUT_TBUF_E[0]	0	1	0	0	0	0	0	0	1	0
SINGLE_W_BUF[6]	0	1	0	0	0	0	0	1	1	1
SINGLE_W_BUF[10]	0	1	0	0	1	0	0	0	1	1
OUT_TBUF_E[1]	1	0	0	0	0	0	0	0	1	0
SINGLE_W_BUF[7]	1	0	0	0	0	0	0	1	1	1
SINGLE_W_BUF[11]	1	0	0	0	1	0	0	0	1	1

INT:MUX.IMUX_IO_O[2]	0.F8.B13	0.F9.B13	0.F4.B12	0.F6.B12	0.F7.B14	0.F5.B14	0.F4.B14	0.F6.B14	0.F7.B13	0.F8.B14
NONE	0	0	0	0	0	0	0	0	1	1
OUT_TBUF_E[1]	0	0	0	0	0	0	1	0	1	0
SINGLE_W_BUF[12]	0	0	0	0	0	0	1	1	1	1
OUT_TBUF_E[0]	0	0	0	0	0	1	0	0	1	0
SINGLE_W_BUF[13]	0	0	0	0	0	1	0	1	1	1
SINGLE_W_BUF[16]	0	0	0	0	1	0	1	0	1	1
SINGLE_W_BUF[17]	0	0	0	0	1	1	0	0	1	1
HEX_H5_BUF[2]	0	0	0	1	0	0	0	0	0	1
OUT_TBUF_E[2]	0	0	0	1	0	0	0	0	1	0
SINGLE_W_BUF[19]	0	0	0	1	0	0	0	1	1	1
SINGLE_W_BUF[14]	0	0	0	1	1	0	0	0	1	1
HEX_H6_BUF[2]	0	0	1	0	0	0	0	0	0	1
OUT_TBUF_E[3]	0	0	1	0	0	0	0	0	1	0
SINGLE_W_BUF[18]	0	0	1	0	0	0	0	1	1	1
SINGLE_W_BUF[15]	0	0	1	0	1	0	0	0	1	1
HEX_H4_BUF[2]	0	1	0	0	0	0	0	0	0	1
OMUX_E1	0	1	0	0	0	0	0	0	1	0
SINGLE_W_BUF[20]	0	1	0	0	0	0	0	1	1	1
SINGLE_W_BUF[23]	0	1	0	0	1	0	0	0	1	1
HEX_H3_BUF[2]	1	0	0	0	0	0	0	0	0	1
OMUX_E0	1	0	0	0	0	0	0	0	1	0
SINGLE_W_BUF[21]	1	0	0	0	0	0	0	1	1	1
SINGLE_W_BUF[22]	1	0	0	0	1	0	0	0	1	1

INT:MUX.IMUX_IO_O[3]	0.F3.B13	0.F4.B13	0.F0.B13	0.F1.B13	0.F3.B14	0.F5.B13	0.F6.B13	0.F2.B14	0.F2.B13	0.F1.B14
NONE	0	0	0	0	0	0	0	0	1	1
OUT_TBUF_E[1]	0	0	0	0	0	0	1	0	1	0
SINGLE_W_BUF[12]	0	0	0	0	0	0	1	1	1	1
OUT_TBUF_E[0]	0	0	0	0	0	1	0	0	1	0
SINGLE_W_BUF[13]	0	0	0	0	0	1	0	1	1	1
SINGLE_W_BUF[16]	0	0	0	0	1	0	1	0	1	1
SINGLE_W_BUF[17]	0	0	0	0	1	1	0	0	1	1
HEX_H5_BUF[3]	0	0	0	1	0	0	0	0	0	1
OUT_TBUF_E[2]	0	0	0	1	0	0	0	0	1	0
SINGLE_W_BUF[19]	0	0	0	1	0	0	0	1	1	1
SINGLE_W_BUF[14]	0	0	0	1	1	0	0	0	1	1
HEX_H4_BUF[3]	0	0	1	0	0	0	0	0	0	1
OUT_TBUF_E[3]	0	0	1	0	0	0	0	0	1	0
SINGLE_W_BUF[18]	0	0	1	0	0	0	0	1	1	1
SINGLE_W_BUF[15]	0	0	1	0	1	0	0	0	1	1
HEX_H6_BUF[3]	0	1	0	0	0	0	0	0	0	1
OMUX_E1	0	1	0	0	0	0	0	0	1	0
SINGLE_W_BUF[20]	0	1	0	0	0	0	0	1	1	1
SINGLE_W_BUF[23]	0	1	0	0	1	0	0	0	1	1
HEX_H3_BUF[3]	1	0	0	0	0	0	0	0	0	1
OMUX_E0	1	0	0	0	0	0	0	0	1	0
SINGLE_W_BUF[21]	1	0	0	0	0	0	0	1	1	1
SINGLE_W_BUF[22]	1	0	0	0	1	0	0	0	1	1

INT:MUX.IMUX_IO_SR[0]	0.F29.B10	0.F30.B10	0.F31.B10	0.F33.B9	0.F32.B11	0.F33.B11
INT:MUX.IMUX_IO_SR[1]	0.F30.B11	0.F29.B11	0.F28.B9	0.F32.B9	0.F31.B9	0.F28.B11
INT:MUX.IMUX_IO_SR[2]	0.F35.B11	0.F36.B11	0.F37.B10	0.F38.B9	0.F36.B9	0.F37.B11
INT:MUX.IMUX_IO_SR[3]	0.F36.B10	0.F35.B10	0.F34.B10	0.F35.B9	0.F39.B9	0.F34.B11
NONE	0	0	0	0	0	0
SINGLE_W_BUF[4]	0	0	0	0	0	1
SINGLE_W_BUF[5]	0	0	0	0	1	0
SINGLE_W_BUF[6]	0	0	0	1	0	0
SINGLE_W_BUF[7]	0	0	1	0	0	0
HEX_V1_BUF[1]	0	1	0	0	0	1
HEX_V4_BUF[1]	0	1	0	0	1	0
HEX_V2_BUF[1]	1	1	0	0	0	1
HEX_V3_BUF[1]	1	1	0	0	1	0
HEX_V5_BUF[1]	1	1	0	1	0	0
HEX_V6_BUF[1]	1	1	1	0	0	0

INT:MUX.IMUX_IO_TCE[0]	0.F25.B11	0.F26.B11	0.F27.B11	0.F25.B9	0.F26.B9	0.F28.B10
INT:MUX.IMUX_IO_TCE[1]	0.F27.B10	0.F26.B10	0.F24.B11	0.F31.B11	0.F27.B9	0.F24.B10
INT:MUX.IMUX_IO_TCE[2]	0.F22.B11	0.F21.B11	0.F20.B11	0.F22.B9	0.F21.B9	0.F19.B10
INT:MUX.IMUX_IO_TCE[3]	0.F20.B10	0.F21.B10	0.F23.B11	0.F16.B11	0.F20.B9	0.F23.B10
NONE	0	0	0	0	0	0
SINGLE_W_BUF[10]	0	0	0	0	0	1
SINGLE_W_BUF[11]	0	0	0	0	1	0
SINGLE_W_BUF[12]	0	0	0	1	0	0
SINGLE_W_BUF[13]	0	0	1	0	0	0
HEX_V4_BUF[3]	0	1	0	1	0	0
HEX_V1_BUF[3]	0	1	1	0	0	0
HEX_V6_BUF[3]	1	1	0	0	0	1
HEX_V5_BUF[3]	1	1	0	0	1	0
HEX_V3_BUF[3]	1	1	0	1	0	0
HEX_V2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_T[0]	0.F39.B10	0.F40.B10	0.F41.B10	0.F40.B9	0.F41.B11	0.F42.B11
INT:MUX.IMUX_IO_T[1]	0.F40.B11	0.F39.B11	0.F38.B10	0.F42.B9	0.F43.B9	0.F38.B11
INT:MUX.IMUX_IO_T[2]	0.F45.B11	0.F46.B11	0.F47.B10	0.F46.B9	0.F47.B9	0.F47.B11
INT:MUX.IMUX_IO_T[3]	0.F46.B10	0.F45.B10	0.F44.B10	0.F45.B9	0.F43.B11	0.F44.B11
NONE	0	0	0	0	0	0
SINGLE_W_BUF[0]	0	0	0	0	0	1
SINGLE_W_BUF[1]	0	0	0	0	1	0
SINGLE_W_BUF[2]	0	0	0	1	0	0
SINGLE_W_BUF[3]	0	0	1	0	0	0
HEX_V1_BUF[0]	0	1	0	0	0	1
HEX_V4_BUF[0]	0	1	0	0	1	0
HEX_V2_BUF[0]	1	1	0	0	0	1
HEX_V3_BUF[0]	1	1	0	0	1	0
HEX_V5_BUF[0]	1	1	0	1	0	0
HEX_V6_BUF[0]	1	1	1	0	0	0

INT:MUX.IMUX_TBUF_I[0]	0.F19.B15	0.F20.B15	0.F37.B15	0.F17.B15	0.F16.B15
NONE	0	0	0	0	0
SINGLE_W_BUF[17]	0	0	0	0	1
SINGLE_W_BUF[18]	0	0	0	1	0
SINGLE_W_BUF[22]	0	0	1	0	0
OUT_IO_I[3]	0	1	0	0	1
OUT_IO_I[2]	0	1	0	1	0
SINGLE_W_BUF[23]	0	1	1	0	0
OUT_IO_IQ[2]	1	0	0	1	0
OUT_IO_IQ[3]	1	0	1	0	0
OUT_IO_IQ[1]	1	1	0	1	0
OUT_IO_I[1]	1	1	1	0	0

INT:MUX.IMUX_TBUF_I[1]	0.F22.B15	0.F21.B15	0.F38.B15	0.F39.B15	0.F24.B15
NONE	0	0	0	0	0
SINGLE_W_BUF[5]	0	0	0	0	1
SINGLE_W_BUF[6]	0	0	0	1	0
SINGLE_W_BUF[11]	0	0	1	0	0
OUT_IO_I[2]	0	1	0	0	1
OUT_IO_I[3]	0	1	0	1	0
SINGLE_W_BUF[10]	0	1	1	0	0
OUT_IO_IQ[2]	1	0	0	0	1
OUT_IO_IQ[3]	1	0	1	0	0
OUT_IO_IQ[1]	1	1	0	0	1
OUT_IO_I[1]	1	1	1	0	0

INT:MUX.IMUX_TBUF_T[0]	0.F26.B15	0.F27.B15	0.F40.B15	0.F35.B12	0.F27.B12
INT:MUX.IMUX_TBUF_T[1]	0.F29.B15	0.F28.B15	0.F43.B15	0.F33.B12	0.F28.B12
NONE	0	0	0	0	0
HEX_V6_BUF[1]	0	0	0	0	1
HEX_V5_BUF[1]	0	0	0	1	0
HEX_V1_BUF[1]	0	0	1	0	0
SINGLE_W_BUF[0]	0	1	0	0	1
SINGLE_W_BUF[7]	0	1	0	1	0
HEX_V2_BUF[1]	1	0	0	0	1
HEX_V3_BUF[1]	1	0	0	1	0
HEX_V4_BUF[1]	1	0	1	0	0
SINGLE_W_BUF[19]	1	1	0	0	1
SINGLE_W_BUF[12]	1	1	0	1	0

INT:MUX.LH[0]
INT:MUX.LH[1]
OUT_IO_IQ[3]

INT:MUX.LH[10]	0.F40.B12
NONE	0
OUT_IO_IQ[3]	1

INT:MUX.LH[11]	0.F47.B12
OUT_IO_IQ[1]	0
OUT_IO_I[3]	1

INT:MUX.LH[2]	0.F16.B12
INT:MUX.LH[3]	0.F15.B12
OUT_IO_I[3]	0
OUT_IO_IQ[1]	1

INT:MUX.LH[4]	0.F8.B12
OUT_IO_IQ[2]	0
OUT_IO_I[1]	1

INT:MUX.LH[5]	0.F7.B12
OUT_IO_I[2]	0
OUT_IO_I[1]	1

INT:MUX.LH[6]	0.F0.B12
NONE	0
OUT_IO_IQ[2]	1

INT:MUX.LH[7]	0.F31.B12
OUT_IO_I[1]	0
OUT_IO_IQ[2]	1

INT:MUX.LH[8]	0.F32.B12
INT:MUX.LH[9]	0.F39.B12
NONE	0
OUT_IO_I[2]	1

INT:MUX.LV[0]	0.F4.B15	0.F9.B12	0.F1.B15	0.F7.B15	0.F14.B15	0.F11.B15	0.F12.B15	0.F3.B15	0.F0.B15
INT:MUX.LV[6]	0.F8.B15	0.F12.B12	0.F5.B15	0.F6.B15	0.F15.B15	0.F14.B12	0.F9.B15	0.F13.B15	0.F1.B12
NONE	0	0	0	0	0	0	0	0	0
SINGLE_W_BUF[5]	0	0	0	0	0	0	0	0	1
SINGLE_W_BUF[6]	0	0	0	0	0	0	0	1	0
SINGLE_W_BUF[10]	0	0	0	0	0	0	1	0	0
SINGLE_W_BUF[11]	0	0	0	0	0	1	0	0	0
SINGLE_W_BUF[17]	0	0	0	0	1	0	0	0	0
SINGLE_W_BUF[18]	0	0	0	1	0	0	0	0	0
SINGLE_W_BUF[22]	0	0	1	0	0	0	0	0	0
SINGLE_W_BUF[23]	0	1	0	0	0	0	0	0	0
OUT_IO_IQ[3]	1	0	0	0	0	0	0	0	1
OUT_IO_IQ[2]	1	0	0	0	0	0	0	1	0
OUT_IO_I[2]	1	0	0	0	0	0	1	0	0
OUT_IO_IQ[1]	1	0	0	0	1	0	0	0	0
OUT_IO_I[3]	1	0	0	1	0	0	0	0	0
OUT_IO_I[1]	1	0	1	0	0	0	0	0	0

INT:MUX.OMUX[6]	0.F30.B15	0.F41.B15	0.F33.B15
INT:MUX.OMUX[7]	0.F32.B15	0.F34.B15	0.F42.B15
NONE	0	0	0
OUT_IO_I[1]	0	0	1
OUT_IO_I[2]	0	1	0
OUT_IO_I[3]	1	0	0

IO[1]:OMUX	0.F7.B16
IO[2]:OMUX	0.F22.B16
IO[3]:OMUX	0.F37.B16
O	0
OFF	1

IO[1]:TMUX	0.F12.B16
IO[2]:TMUX	0.F17.B16
IO[3]:TMUX	0.F42.B16
T	0
TFF	1

Tile IO_S

Cells: 1

Switchbox INT

virtex IO_S switchbox INT permanent buffers
Destination	Source
GCLK_BUF[0]	GCLK[0]
GCLK_BUF[1]	GCLK[1]
GCLK_BUF[2]	GCLK[2]
GCLK_BUF[3]	GCLK[3]
SINGLE_N_BUF[0]	SINGLE_N[0]
SINGLE_N_BUF[1]	SINGLE_N[1]
SINGLE_N_BUF[2]	SINGLE_N[2]
SINGLE_N_BUF[3]	SINGLE_N[3]
SINGLE_N_BUF[4]	SINGLE_N[4]
SINGLE_N_BUF[5]	SINGLE_N[5]
SINGLE_N_BUF[6]	SINGLE_N[6]
SINGLE_N_BUF[7]	SINGLE_N[7]
SINGLE_N_BUF[8]	SINGLE_N[8]
SINGLE_N_BUF[9]	SINGLE_N[9]
SINGLE_N_BUF[10]	SINGLE_N[10]
SINGLE_N_BUF[11]	SINGLE_N[11]
SINGLE_N_BUF[12]	SINGLE_N[12]
SINGLE_N_BUF[13]	SINGLE_N[13]
SINGLE_N_BUF[14]	SINGLE_N[14]
SINGLE_N_BUF[15]	SINGLE_N[15]
SINGLE_N_BUF[16]	SINGLE_N[16]
SINGLE_N_BUF[17]	SINGLE_N[17]
SINGLE_N_BUF[18]	SINGLE_N[18]
SINGLE_N_BUF[19]	SINGLE_N[19]
SINGLE_N_BUF[20]	SINGLE_N[20]
SINGLE_N_BUF[21]	SINGLE_N[21]
SINGLE_N_BUF[22]	SINGLE_N[22]
SINGLE_N_BUF[23]	SINGLE_N[23]
HEX_H1_BUF[0]	HEX_H1[0]
HEX_H1_BUF[1]	HEX_H1[1]
HEX_H1_BUF[2]	HEX_H1[2]
HEX_H1_BUF[3]	HEX_H1[3]
HEX_H2_BUF[0]	HEX_H2[0]
HEX_H2_BUF[1]	HEX_H2[1]
HEX_H2_BUF[2]	HEX_H2[2]
HEX_H2_BUF[3]	HEX_H2[3]
HEX_H3_BUF[0]	HEX_H3[0]
HEX_H3_BUF[1]	HEX_H3[1]
HEX_H3_BUF[2]	HEX_H3[2]
HEX_H3_BUF[3]	HEX_H3[3]
HEX_H4_BUF[0]	HEX_H4[0]
HEX_H4_BUF[1]	HEX_H4[1]
HEX_H4_BUF[2]	HEX_H4[2]
HEX_H4_BUF[3]	HEX_H4[3]
HEX_H5_BUF[0]	HEX_H5[0]
HEX_H5_BUF[1]	HEX_H5[1]
HEX_H5_BUF[2]	HEX_H5[2]
HEX_H5_BUF[3]	HEX_H5[3]
HEX_H6_BUF[0]	HEX_H6[0]
HEX_H6_BUF[1]	HEX_H6[1]
HEX_H6_BUF[2]	HEX_H6[2]
HEX_H6_BUF[3]	HEX_H6[3]
HEX_V0_BUF[0]	HEX_V0[0]
HEX_V0_BUF[1]	HEX_V0[1]
HEX_V0_BUF[2]	HEX_V0[2]
HEX_V0_BUF[3]	HEX_V0[3]
HEX_V1_BUF[0]	HEX_V1[0]
HEX_V1_BUF[1]	HEX_V1[1]
HEX_V1_BUF[2]	HEX_V1[2]
HEX_V1_BUF[3]	HEX_V1[3]
HEX_V2_BUF[0]	HEX_V2[0]
HEX_V2_BUF[1]	HEX_V2[1]
HEX_V2_BUF[2]	HEX_V2[2]
HEX_V2_BUF[3]	HEX_V2[3]
HEX_V3_BUF[0]	HEX_V3[0]
HEX_V3_BUF[1]	HEX_V3[1]
HEX_V3_BUF[2]	HEX_V3[2]
HEX_V3_BUF[3]	HEX_V3[3]
HEX_V4_BUF[0]	HEX_V4[0]
HEX_V4_BUF[1]	HEX_V4[1]
HEX_V4_BUF[2]	HEX_V4[2]
HEX_V4_BUF[3]	HEX_V4[3]
HEX_V5_BUF[0]	HEX_V5[0]
HEX_V5_BUF[1]	HEX_V5[1]
HEX_V5_BUF[2]	HEX_V5[2]
HEX_V5_BUF[3]	HEX_V5[3]
LH_FAKE0	LH[0]
LH_FAKE6	LH[6]

virtex IO_S switchbox INT pass gates
Destination	Source	Bit
SINGLE_N[0]	HEX_H6[0]	XXX57005[57005][57005]
SINGLE_N[0]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_N[1]	HEX_H3[0]	XXX57005[57005][57005]
SINGLE_N[1]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_N[2]	HEX_H0[0]	XXX57005[57005][57005]
SINGLE_N[2]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_N[3]	HEX_H6[0]	XXX57005[57005][57005]
SINGLE_N[3]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_N[4]	HEX_H3[0]	XXX57005[57005][57005]
SINGLE_N[4]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_N[5]	HEX_H0[0]	XXX57005[57005][57005]
SINGLE_N[5]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_N[6]	HEX_H6[1]	XXX57005[57005][57005]
SINGLE_N[6]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_N[7]	HEX_H3[1]	XXX57005[57005][57005]
SINGLE_N[7]	OUT_IO_IQ[0]	XXX57005[57005][57005]
SINGLE_N[8]	HEX_H0[1]	XXX57005[57005][57005]
SINGLE_N[8]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_N[9]	HEX_H6[1]	XXX57005[57005][57005]
SINGLE_N[9]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_N[10]	HEX_H3[1]	XXX57005[57005][57005]
SINGLE_N[10]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_N[11]	HEX_H0[1]	XXX57005[57005][57005]
SINGLE_N[11]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_N[12]	HEX_H6[2]	XXX57005[57005][57005]
SINGLE_N[12]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_N[13]	HEX_H3[2]	XXX57005[57005][57005]
SINGLE_N[13]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_N[14]	HEX_H0[2]	XXX57005[57005][57005]
SINGLE_N[14]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_N[15]	HEX_H6[2]	XXX57005[57005][57005]
SINGLE_N[15]	OUT_IO_IQ[0]	XXX57005[57005][57005]
SINGLE_N[16]	HEX_H3[2]	XXX57005[57005][57005]
SINGLE_N[16]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_N[17]	HEX_H0[2]	XXX57005[57005][57005]
SINGLE_N[17]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_N[18]	HEX_H6[3]	XXX57005[57005][57005]
SINGLE_N[18]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_N[19]	HEX_H3[3]	XXX57005[57005][57005]
SINGLE_N[19]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_N[20]	HEX_H0[3]	XXX57005[57005][57005]
SINGLE_N[20]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_N[21]	HEX_H6[3]	XXX57005[57005][57005]
SINGLE_N[21]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_N[22]	HEX_H3[3]	XXX57005[57005][57005]
SINGLE_N[22]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_N[23]	HEX_H0[3]	XXX57005[57005][57005]
SINGLE_N[23]	OUT_IO_IQ[0]	XXX57005[57005][57005]

virtex IO_S switchbox INT muxes HEX_H0[0]
Bits	Destination
HEX_H0[0]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H0[1]
Bits	Destination
HEX_H0[1]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H0[2]
Bits	Destination
HEX_H0[2]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H0[3]
Bits	Destination
HEX_H0[3]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H0[4]
Bits	Destination
HEX_H0[4]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H0[5]
Bits	Destination
HEX_H0[5]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H6[0]
Bits	Destination
HEX_H6[0]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H6[1]
Bits	Destination
HEX_H6[1]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H6[2]
Bits	Destination
HEX_H6[2]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H6[3]
Bits	Destination
HEX_H6[3]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H6[4]
Bits	Destination
HEX_H6[4]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_H6[5]
Bits	Destination
HEX_H6[5]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V0[0]
Bits	Destination
HEX_V0[0]
	Source
OUT_IO_I[1]

virtex IO_S switchbox INT muxes HEX_V0[1]
Bits	Destination
HEX_V0[1]
	Source
OUT_IO_I[3]

virtex IO_S switchbox INT muxes HEX_V0[2]
Bits	Destination
HEX_V0[2]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V0[3]
Bits	Destination
HEX_V0[3]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V1[0]
Bits	Destination
HEX_V1[0]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V1[1]
Bits	Destination
HEX_V1[1]
	Source
OUT_IO_IQ[0]

virtex IO_S switchbox INT muxes HEX_V1[2]
Bits	Destination
HEX_V1[2]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V1[3]
Bits	Destination
HEX_V1[3]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V2[0]
Bits	Destination
HEX_V2[0]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V2[1]
Bits	Destination
HEX_V2[1]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V2[2]
Bits	Destination
HEX_V2[2]
	Source
OUT_IO_I[3]

virtex IO_S switchbox INT muxes HEX_V2[3]
Bits	Destination
HEX_V2[3]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V3[0]
Bits	Destination
HEX_V3[0]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V3[1]
Bits	Destination
HEX_V3[1]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V3[2]
Bits	Destination
HEX_V3[2]
	Source
OUT_IO_I[3]

virtex IO_S switchbox INT muxes HEX_V3[3]
Bits	Destination
HEX_V3[3]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V4[0]
Bits	Destination
HEX_V4[0]
	Source
OUT_IO_IQ[0]

virtex IO_S switchbox INT muxes HEX_V4[1]
Bits	Destination
HEX_V4[1]
	Source
OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V4[2]
Bits	Destination
HEX_V4[2]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V4[3]
Bits	Destination
HEX_V4[3]
	Source
OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_V5[0]
Bits	Destination
HEX_V5[0]
	Source
OUT_IO_IQ[0]

virtex IO_S switchbox INT muxes HEX_V5[1]
Bits	Destination
HEX_V5[1]
	Source
OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V5[2]
Bits	Destination
HEX_V5[2]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_V5[3]
Bits	Destination
HEX_V5[3]
	Source
OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_N0[0]
Bits	Destination
HEX_N0[0]
	Source
OUT_IO_IQ[0]

virtex IO_S switchbox INT muxes HEX_N0[1]
Bits	Destination
HEX_N0[1]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_N0[2]
Bits	Destination
HEX_N0[2]
	Source
OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_N0[3]
Bits	Destination
HEX_N0[3]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_N1[0]
Bits	Destination
HEX_N1[0]
	Source
OUT_IO_IQ[0]

virtex IO_S switchbox INT muxes HEX_N1[1]
Bits	Destination
HEX_N1[1]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_N1[2]
Bits	Destination
HEX_N1[2]
	Source
OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_N1[3]
Bits	Destination
HEX_N1[3]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes HEX_N2[0]
Bits	Destination
HEX_N2[0]
	Source
HEX_S3[0]

virtex IO_S switchbox INT muxes HEX_N2[1]
Bits	Destination
HEX_N2[1]
	Source
HEX_S3[1]

virtex IO_S switchbox INT muxes HEX_N2[2]
Bits	Destination
HEX_N2[2]
	Source
HEX_S3[2]

virtex IO_S switchbox INT muxes HEX_N2[3]
Bits	Destination
HEX_N2[3]
	Source
HEX_S3[3]

virtex IO_S switchbox INT muxes HEX_N3[0]
Bits	Destination
HEX_N3[0]
	Source
HEX_S4[0]

virtex IO_S switchbox INT muxes HEX_N3[1]
Bits	Destination
HEX_N3[1]
	Source
HEX_S4[1]

virtex IO_S switchbox INT muxes HEX_N3[2]
Bits	Destination
HEX_N3[2]
	Source
HEX_S4[2]

virtex IO_S switchbox INT muxes HEX_N3[3]
Bits	Destination
HEX_N3[3]
	Source
HEX_S4[3]

virtex IO_S switchbox INT muxes HEX_N4[0]
Bits	Destination
HEX_N4[0]
	Source
HEX_S5[0]

virtex IO_S switchbox INT muxes HEX_N4[1]
Bits	Destination
HEX_N4[1]
	Source
HEX_S5[1]

virtex IO_S switchbox INT muxes HEX_N4[2]
Bits	Destination
HEX_N4[2]
	Source
HEX_S5[2]

virtex IO_S switchbox INT muxes HEX_N4[3]
Bits	Destination
HEX_N4[3]
	Source
HEX_S5[3]

virtex IO_S switchbox INT muxes HEX_N5[0]
Bits	Destination
HEX_N5[0]
	Source
HEX_S6[0]

virtex IO_S switchbox INT muxes HEX_N5[1]
Bits	Destination
HEX_N5[1]
	Source
HEX_S6[1]

virtex IO_S switchbox INT muxes HEX_N5[2]
Bits	Destination
HEX_N5[2]
	Source
HEX_S6[2]

virtex IO_S switchbox INT muxes HEX_N5[3]
Bits	Destination
HEX_N5[3]
	Source
HEX_S6[3]

virtex IO_S switchbox INT muxes LH[0]
Bits	Destination
LH[0]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes LH[6]
Bits	Destination
LH[6]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes LV[0]
Bits	Destination
LV[0]
	Source
OUT_IO_IQ[0]

virtex IO_S switchbox INT muxes LV[1]
Bits	Destination
LV[1]
	Source
OUT_IO_I[0]

virtex IO_S switchbox INT muxes LV[2]
Bits	Destination
LV[2]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes LV[3]
Bits	Destination
LV[3]
	Source
OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes LV[4]
Bits	Destination
LV[4]
	Source
OUT_IO_I[1]

virtex IO_S switchbox INT muxes LV[5]
Bits	Destination
LV[5]
	Source
OUT_IO_I[1]

virtex IO_S switchbox INT muxes LV[6]
Bits	Destination
LV[6]
	Source
OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes LV[7]
Bits	Destination
LV[7]
	Source
OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes LV[8]
Bits	Destination
LV[8]
	Source
OUT_IO_I[2]

virtex IO_S switchbox INT muxes LV[9]
Bits	Destination
LV[9]
	Source
OUT_IO_I[2]

virtex IO_S switchbox INT muxes LV[10]
Bits	Destination
LV[10]
	Source
OUT_IO_IQ[3]

virtex IO_S switchbox INT muxes LV[11]
Bits	Destination
LV[11]
	Source
OUT_IO_I[3]

virtex IO_S switchbox INT muxes IMUX_IO_CLK[0]
Bits	Destination
IMUX_IO_CLK[0]
	Source
HEX_V5_BUF[2]

virtex IO_S switchbox INT muxes IMUX_IO_CLK[1]
Bits	Destination
IMUX_IO_CLK[1]
	Source
HEX_V5_BUF[2]

virtex IO_S switchbox INT muxes IMUX_IO_CLK[2]
Bits	Destination
IMUX_IO_CLK[2]
	Source
HEX_V5_BUF[2]

virtex IO_S switchbox INT muxes IMUX_IO_CLK[3]
Bits	Destination
IMUX_IO_CLK[3]
	Source
HEX_V5_BUF[2]

virtex IO_S switchbox INT muxes IMUX_IO_SR[0]
Bits	Destination
IMUX_IO_SR[0]
	Source
HEX_V5_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_SR[1]
Bits	Destination
IMUX_IO_SR[1]
	Source
HEX_V5_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_SR[2]
Bits	Destination
IMUX_IO_SR[2]
	Source
HEX_V5_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_SR[3]
Bits	Destination
IMUX_IO_SR[3]
	Source
HEX_V5_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_ICE[0]
Bits	Destination
IMUX_IO_ICE[0]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_ICE[1]
Bits	Destination
IMUX_IO_ICE[1]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_ICE[2]
Bits	Destination
IMUX_IO_ICE[2]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_ICE[3]
Bits	Destination
IMUX_IO_ICE[3]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_OCE[0]
Bits	Destination
IMUX_IO_OCE[0]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_OCE[1]
Bits	Destination
IMUX_IO_OCE[1]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_OCE[2]
Bits	Destination
IMUX_IO_OCE[2]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_OCE[3]
Bits	Destination
IMUX_IO_OCE[3]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_TCE[0]
Bits	Destination
IMUX_IO_TCE[0]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_TCE[1]
Bits	Destination
IMUX_IO_TCE[1]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_TCE[2]
Bits	Destination
IMUX_IO_TCE[2]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_TCE[3]
Bits	Destination
IMUX_IO_TCE[3]
	Source
HEX_V5_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_O[0]
Bits	Destination
IMUX_IO_O[0]
	Source
HEX_V3_BUF[0]

virtex IO_S switchbox INT muxes IMUX_IO_O[1]
Bits	Destination
IMUX_IO_O[1]
	Source
HEX_V3_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_O[2]
Bits	Destination
IMUX_IO_O[2]
	Source
HEX_V3_BUF[2]

virtex IO_S switchbox INT muxes IMUX_IO_O[3]
Bits	Destination
IMUX_IO_O[3]
	Source
HEX_V3_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_T[0]
Bits	Destination
IMUX_IO_T[0]
	Source
HEX_V5_BUF[0]

virtex IO_S switchbox INT muxes IMUX_IO_T[1]
Bits	Destination
IMUX_IO_T[1]
	Source
HEX_V5_BUF[0]

virtex IO_S switchbox INT muxes IMUX_IO_T[2]
Bits	Destination
IMUX_IO_T[2]
	Source
HEX_V5_BUF[0]

virtex IO_S switchbox INT muxes IMUX_IO_T[3]
Bits	Destination
IMUX_IO_T[3]
	Source
HEX_V5_BUF[0]

Bel IO[0]

virtex IO_S bel IO[0]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[0]
I	output	OUT_IO_I[0]
ICE	input	IMUX_IO_ICE[0]
IQ	output	OUT_IO_IQ[0]
O	input	IMUX_IO_O[0]
OCE	input	IMUX_IO_OCE[0]
SR	input	IMUX_IO_SR[0]
T	input	IMUX_IO_T[0]
TCE	input	IMUX_IO_TCE[0]

Bel IO[1]

virtex IO_S bel IO[1]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[1]
I	output	OUT_IO_I[1]
ICE	input	IMUX_IO_ICE[1]
IQ	output	OUT_IO_IQ[1]
O	input	IMUX_IO_O[1]
OCE	input	IMUX_IO_OCE[1]
SR	input	IMUX_IO_SR[1]
T	input	IMUX_IO_T[1]
TCE	input	IMUX_IO_TCE[1]

Bel IO[2]

virtex IO_S bel IO[2]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[2]
I	output	OUT_IO_I[2]
ICE	input	IMUX_IO_ICE[2]
IQ	output	OUT_IO_IQ[2]
O	input	IMUX_IO_O[2]
OCE	input	IMUX_IO_OCE[2]
SR	input	IMUX_IO_SR[2]
T	input	IMUX_IO_T[2]
TCE	input	IMUX_IO_TCE[2]

Bel IO[3]

virtex IO_S bel IO[3]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[3]
I	output	OUT_IO_I[3]
ICE	input	IMUX_IO_ICE[3]
IQ	output	OUT_IO_IQ[3]
O	input	IMUX_IO_O[3]
OCE	input	IMUX_IO_OCE[3]
SR	input	IMUX_IO_SR[3]
T	input	IMUX_IO_T[3]
TCE	input	IMUX_IO_TCE[3]

Bel wires

virtex IO_S bel wires
Wire	Pins
IMUX_IO_CLK[0]	IO[0].CLK
IMUX_IO_CLK[1]	IO[1].CLK
IMUX_IO_CLK[2]	IO[2].CLK
IMUX_IO_CLK[3]	IO[3].CLK
IMUX_IO_SR[0]	IO[0].SR
IMUX_IO_SR[1]	IO[1].SR
IMUX_IO_SR[2]	IO[2].SR
IMUX_IO_SR[3]	IO[3].SR
IMUX_IO_ICE[0]	IO[0].ICE
IMUX_IO_ICE[1]	IO[1].ICE
IMUX_IO_ICE[2]	IO[2].ICE
IMUX_IO_ICE[3]	IO[3].ICE
IMUX_IO_OCE[0]	IO[0].OCE
IMUX_IO_OCE[1]	IO[1].OCE
IMUX_IO_OCE[2]	IO[2].OCE
IMUX_IO_OCE[3]	IO[3].OCE
IMUX_IO_TCE[0]	IO[0].TCE
IMUX_IO_TCE[1]	IO[1].TCE
IMUX_IO_TCE[2]	IO[2].TCE
IMUX_IO_TCE[3]	IO[3].TCE
IMUX_IO_O[0]	IO[0].O
IMUX_IO_O[1]	IO[1].O
IMUX_IO_O[2]	IO[2].O
IMUX_IO_O[3]	IO[3].O
IMUX_IO_T[0]	IO[0].T
IMUX_IO_T[1]	IO[1].T
IMUX_IO_T[2]	IO[2].T
IMUX_IO_T[3]	IO[3].T
OUT_IO_I[0]	IO[0].I
OUT_IO_I[1]	IO[1].I
OUT_IO_I[2]	IO[2].I
OUT_IO_I[3]	IO[3].I
OUT_IO_IQ[0]	IO[0].IQ
OUT_IO_IQ[1]	IO[1].IQ
OUT_IO_IQ[2]	IO[2].IQ
OUT_IO_IQ[3]	IO[3].IQ

Bitstream

virtex IO_S rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

### Bitstream

virtex IO_S rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IO[2]:READBACK_IFF	-	-	-	-	-	IO[2]:READBACK_OFF	IO[2]:IFF_DELAY_ENABLE	~IO[2]:SHORTEN_JTAG_CHAIN	-	IO[2]:READBACK_TFF	-	-	-	-	IO[1]:READBACK_TFF	-	~IO[1]:SHORTEN_JTAG_CHAIN	IO[1]:IFF_DELAY_ENABLE	IO[1]:READBACK_OFF	-	-	-	-	-	IO[1]:READBACK_IFF	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IO[2]:IFF_SR_SYNC	IO[2]:IFF_INIT	IO[2]:I_DELAY_ENABLE	IO[2]:IFF_LATCH	IO[2]:IFF_SR_ENABLE	IO[2]:OFF_SR_ENABLE	IO[2]:OFF_LATCH	IO[2]:OMUX[0]	~IO[2]:OFF_INIT	IO[2]:OFF_SR_SYNC	IO[2]:TFF_SR_SYNC	~IO[2]:TFF_INIT	IO[2]:TMUX[0]	IO[2]:TFF_LATCH	IO[2]:TFF_SR_ENABLE	IO[1]:TFF_SR_ENABLE	IO[1]:TFF_LATCH	IO[1]:TMUX[0]	~IO[1]:TFF_INIT	IO[1]:TFF_SR_SYNC	IO[1]:OFF_SR_SYNC	~IO[1]:OFF_INIT	IO[1]:OMUX[0]	IO[1]:OFF_LATCH	IO[1]:OFF_SR_ENABLE	IO[1]:IFF_SR_ENABLE	IO[1]:IFF_LATCH	IO[1]:I_DELAY_ENABLE	IO[1]:IFF_INIT	IO[1]:IFF_SR_SYNC
B15	INT:MUX.LH[6][0]	INT:MUX.LH[6][6]	INT:MUX.LH[6][1]	INT:DRIVE.LH[6]	INT:MUX.LH[0][6]	INT:MUX.LH[6][8]	INT:MUX.LH[0][5]	INT:MUX.LH[6][5]	INT:MUX.LH[0][2]	INT:MUX.LH[0][8]	INT:DRIVE.LH[0]	INT:MUX.LH[6][3]	INT:MUX.LH[6][2]	INT:MUX.LH[0][1]	INT:MUX.LH[6][4]	INT:MUX.LH[0][4]	INT:MUX.HEX_H6[4][4]	INT:MUX.HEX_H6[4][2]	INT:MUX.HEX_H0[5][2]	INT:DRIVE.HEX_H0[5]	INT:MUX.HEX_H0[5][3]	INT:MUX.HEX_H6[4][3]	INT:MUX.HEX_H0[5][4]	INT:MUX.HEX_H0[5][6]	INT:MUX.HEX_H6[4][6]	INT:MUX.HEX_H0[5][5]	INT:MUX.HEX_H6[4][1]	INT:MUX.HEX_H0[5][1]	INT:DRIVE.HEX_H6[4]	INT:MUX.HEX_H0[5][0]	INT:MUX.HEX_H6[4][0]	INT:MUX.HEX_H6[4][5]	INT:MUX.HEX_H6[5][5]	INT:MUX.HEX_H6[5][0]	INT:MUX.HEX_H0[4][0]	INT:MUX.HEX_H0[4][1]	INT:MUX.HEX_H6[5][6]	INT:DRIVE.HEX_H6[5]	INT:MUX.HEX_H6[5][1]	INT:MUX.HEX_H0[4][5]	INT:MUX.HEX_H0[4][4]	INT:MUX.HEX_H0[4][6]	INT:MUX.HEX_H6[5][3]	INT:MUX.HEX_H0[4][3]	INT:MUX.HEX_H0[4][2]	INT:DRIVE.HEX_H0[4]	INT:MUX.HEX_H6[5][2]	INT:MUX.HEX_H6[5][4]
B14	-	-	INT:MUX.IMUX_IO_O[3][1]	INT:MUX.IMUX_IO_O[3][4]	INT:MUX.IMUX_IO_O[2][2]	INT:MUX.IMUX_IO_O[2][3]	INT:MUX.IMUX_IO_O[2][1]	INT:MUX.IMUX_IO_O[2][4]	-	~INT:INV.IMUX_IO_O[2]	-	-	-	IO[2]:INV.IFF.CLK	IO[2]:INV.OFF.CLK	IO[2]:INV.TFF.CLK	INT:MUX.IMUX_IO_CLK[2][10]	INT:MUX.IMUX_IO_CLK[3][10]	INT:MUX.IMUX_IO_CLK[3][9]	INT:MUX.IMUX_IO_CLK[2][11]	INT:MUX.IMUX_IO_CLK[3][1]	INT:MUX.IMUX_IO_CLK[3][7]	INT:MUX.IMUX_IO_CLK[3][4]	INT:MUX.IMUX_IO_CLK[2][6]	INT:MUX.IMUX_IO_CLK[1][6]	INT:MUX.IMUX_IO_CLK[0][4]	INT:MUX.IMUX_IO_CLK[0][7]	INT:MUX.IMUX_IO_CLK[0][1]	INT:MUX.IMUX_IO_CLK[1][11]	INT:MUX.IMUX_IO_CLK[0][9]	INT:MUX.IMUX_IO_CLK[0][10]	INT:MUX.IMUX_IO_CLK[1][10]	IO[1]:INV.TFF.CLK	IO[1]:INV.OFF.CLK	IO[1]:INV.IFF.CLK	-	-	-	~INT:INV.IMUX_IO_O[1]	-	INT:MUX.IMUX_IO_O[1][1]	INT:MUX.IMUX_IO_O[1][4]	INT:MUX.IMUX_IO_O[1][7]	INT:MUX.IMUX_IO_O[1][8]	INT:MUX.IMUX_IO_O[0][1]	INT:MUX.IMUX_IO_O[0][4]	-	-
B13	INT:MUX.IMUX_IO_O[3][6]	INT:MUX.IMUX_IO_O[3][5]	INT:MUX.IMUX_IO_O[3][0]	INT:MUX.IMUX_IO_O[3][8]	INT:MUX.IMUX_IO_O[3][7]	INT:MUX.IMUX_IO_O[3][3]	INT:MUX.IMUX_IO_O[3][2]	INT:MUX.IMUX_IO_O[2][0]	INT:MUX.IMUX_IO_O[2][8]	INT:MUX.IMUX_IO_O[2][7]	INT:MUX.IMUX_IO_CLK[2][0]	INT:MUX.IMUX_IO_CLK[3][8]	INT:MUX.IMUX_IO_CLK[3][0]	INT:MUX.IMUX_IO_CLK[2][4]	INT:MUX.IMUX_IO_CLK[2][8]	INT:MUX.IMUX_IO_CLK[2][2]	INT:MUX.IMUX_IO_CLK[2][5]	INT:MUX.IMUX_IO_CLK[3][6]	INT:MUX.IMUX_IO_CLK[2][1]	INT:MUX.IMUX_IO_CLK[2][9]	INT:MUX.IMUX_IO_CLK[3][2]	INT:MUX.IMUX_IO_CLK[2][3]	INT:MUX.IMUX_IO_CLK[3][3]	INT:MUX.IMUX_IO_CLK[3][5]	INT:MUX.IMUX_IO_CLK[0][5]	INT:MUX.IMUX_IO_CLK[0][3]	INT:MUX.IMUX_IO_CLK[1][3]	INT:MUX.IMUX_IO_CLK[0][2]	INT:MUX.IMUX_IO_CLK[1][9]	INT:MUX.IMUX_IO_CLK[1][1]	INT:MUX.IMUX_IO_CLK[0][6]	INT:MUX.IMUX_IO_CLK[1][5]	INT:MUX.IMUX_IO_CLK[1][2]	INT:MUX.IMUX_IO_CLK[1][8]	INT:MUX.IMUX_IO_CLK[1][4]	INT:MUX.IMUX_IO_CLK[0][0]	INT:MUX.IMUX_IO_CLK[0][8]	INT:MUX.IMUX_IO_CLK[1][0]	INT:MUX.IMUX_IO_O[1][2]	INT:MUX.IMUX_IO_O[1][3]	INT:MUX.IMUX_IO_O[1][0]	INT:MUX.IMUX_IO_O[0][8]	INT:MUX.IMUX_IO_O[0][7]	INT:MUX.IMUX_IO_O[0][2]	INT:MUX.IMUX_IO_O[0][3]	INT:MUX.IMUX_IO_O[0][0]	INT:MUX.IMUX_IO_O[0][5]	INT:MUX.IMUX_IO_O[0][6]
B12	-	INT:MUX.LH[0][0]	INT:DRIVE.LV[11]	-	INT:MUX.IMUX_IO_O[2][6]	INT:DRIVE.LV[10]	INT:MUX.IMUX_IO_O[2][5]	-	INT:MUX.LV[9][0]	INT:MUX.LH[6][7]	INT:DRIVE.LV[9]	-	INT:MUX.LH[0][7]	INT:DRIVE.LV[8]	INT:MUX.LH[0][3]	INT:MUX.LV[8][0]	INT:MUX.LV[7][0]	INT:MUX.IMUX_IO_CLK[3][11]	INT:DRIVE.LV[7]	-	-	INT:DRIVE.LV[6]	INT:MUX.IMUX_IO_CLK[2][7]	INT:MUX.LV[6][0]	-	INT:MUX.IMUX_IO_CLK[1][7]	INT:DRIVE.LV[0]	-	-	INT:DRIVE.LV[1]	INT:MUX.IMUX_IO_CLK[0][11]	-	INT:MUX.LV[2][0]	-	INT:DRIVE.LV[2]	-	-	INT:DRIVE.LV[3]	-	INT:MUX.LV[3][0]	INT:MUX.LV[4][0]	INT:MUX.IMUX_IO_O[1][5]	INT:DRIVE.LV[4]	INT:MUX.IMUX_IO_O[1][6]	-	INT:DRIVE.LV[5]	-	INT:MUX.LV[5][0]
B11	INT:MUX.IMUX_IO_ICE[2][3]	INT:MUX.IMUX_IO_ICE[2][4]	INT:MUX.IMUX_IO_ICE[2][5]	INT:MUX.IMUX_IO_ICE[3][3]	INT:MUX.IMUX_IO_ICE[3][2]	INT:MUX.IMUX_IO_ICE[0][3]	INT:MUX.IMUX_IO_ICE[0][2]	INT:MUX.IMUX_IO_ICE[1][5]	INT:MUX.IMUX_IO_ICE[1][4]	INT:MUX.IMUX_IO_ICE[1][3]	INT:MUX.IMUX_IO_OCE[2][3]	INT:MUX.IMUX_IO_OCE[2][4]	INT:MUX.IMUX_IO_OCE[2][5]	INT:MUX.IMUX_IO_OCE[3][3]	INT:MUX.IMUX_IO_OCE[0][3]	INT:MUX.IMUX_IO_OCE[0][2]	INT:MUX.IMUX_IO_TCE[3][2]	INT:MUX.IMUX_IO_OCE[1][5]	INT:MUX.IMUX_IO_OCE[1][4]	INT:MUX.IMUX_IO_OCE[1][3]	INT:MUX.IMUX_IO_TCE[2][3]	INT:MUX.IMUX_IO_TCE[2][4]	INT:MUX.IMUX_IO_TCE[2][5]	INT:MUX.IMUX_IO_TCE[3][3]	INT:MUX.IMUX_IO_TCE[1][3]	INT:MUX.IMUX_IO_TCE[0][5]	INT:MUX.IMUX_IO_TCE[0][4]	INT:MUX.IMUX_IO_TCE[0][3]	INT:MUX.IMUX_IO_SR[1][0]	INT:MUX.IMUX_IO_SR[1][4]	INT:MUX.IMUX_IO_SR[1][5]	INT:MUX.IMUX_IO_TCE[1][2]	INT:MUX.IMUX_IO_SR[0][1]	INT:MUX.IMUX_IO_SR[0][0]	INT:MUX.IMUX_IO_SR[3][0]	INT:MUX.IMUX_IO_SR[2][5]	INT:MUX.IMUX_IO_SR[2][4]	INT:MUX.IMUX_IO_SR[2][0]	INT:MUX.IMUX_IO_T[1][0]	INT:MUX.IMUX_IO_T[1][4]	INT:MUX.IMUX_IO_T[1][5]	INT:MUX.IMUX_IO_T[0][1]	INT:MUX.IMUX_IO_T[0][0]	INT:MUX.IMUX_IO_T[3][1]	INT:MUX.IMUX_IO_T[3][0]	INT:MUX.IMUX_IO_T[2][5]	INT:MUX.IMUX_IO_T[2][4]	INT:MUX.IMUX_IO_T[2][0]
B10	INT:MUX.IMUX_IO_ICE[2][0]	INT:MUX.IMUX_IO_ICE[3][5]	INT:MUX.IMUX_IO_ICE[3][4]	INT:MUX.IMUX_IO_ICE[3][0]	~INT:INV.IMUX_IO_ICE[2]	~INT:INV.IMUX_IO_ICE[1]	INT:MUX.IMUX_IO_ICE[0][0]	INT:MUX.IMUX_IO_ICE[0][4]	INT:MUX.IMUX_IO_ICE[0][5]	INT:MUX.IMUX_IO_ICE[1][0]	INT:MUX.IMUX_IO_OCE[2][0]	INT:MUX.IMUX_IO_OCE[3][5]	INT:MUX.IMUX_IO_OCE[3][4]	INT:MUX.IMUX_IO_OCE[3][0]	~INT:INV.IMUX_IO_OCE[1]	-	INT:MUX.IMUX_IO_OCE[0][0]	INT:MUX.IMUX_IO_OCE[0][4]	INT:MUX.IMUX_IO_OCE[0][5]	INT:MUX.IMUX_IO_TCE[2][0]	INT:MUX.IMUX_IO_TCE[3][5]	INT:MUX.IMUX_IO_TCE[3][4]	-	INT:MUX.IMUX_IO_TCE[3][0]	INT:MUX.IMUX_IO_TCE[1][0]	~INT:INV.IMUX_IO_TCE[1]	INT:MUX.IMUX_IO_TCE[1][4]	INT:MUX.IMUX_IO_TCE[1][5]	INT:MUX.IMUX_IO_TCE[0][0]	INT:MUX.IMUX_IO_SR[0][5]	INT:MUX.IMUX_IO_SR[0][4]	INT:MUX.IMUX_IO_SR[0][3]	-	INT:INV.IMUX_IO_SR[1]	INT:MUX.IMUX_IO_SR[3][3]	INT:MUX.IMUX_IO_SR[3][4]	INT:MUX.IMUX_IO_SR[3][5]	INT:MUX.IMUX_IO_SR[2][3]	INT:MUX.IMUX_IO_T[1][3]	INT:MUX.IMUX_IO_T[0][5]	INT:MUX.IMUX_IO_T[0][4]	INT:MUX.IMUX_IO_T[0][3]	~INT:INV.IMUX_IO_T[1]	~INT:INV.IMUX_IO_T[2]	INT:MUX.IMUX_IO_T[3][3]	INT:MUX.IMUX_IO_T[3][4]	INT:MUX.IMUX_IO_T[3][5]	INT:MUX.IMUX_IO_T[2][3]
B9	INT:MUX.IMUX_IO_ICE[2][2]	INT:MUX.IMUX_IO_ICE[2][1]	INT:MUX.IMUX_IO_ICE[3][1]	-	INT:MUX.IMUX_IO_ICE[1][2]	INT:MUX.IMUX_IO_ICE[1][1]	-	INT:MUX.IMUX_IO_ICE[0][1]	INT:MUX.IMUX_IO_OCE[3][2]	INT:MUX.IMUX_IO_OCE[2][1]	-	INT:MUX.IMUX_IO_OCE[2][2]	INT:MUX.IMUX_IO_OCE[3][1]	~INT:INV.IMUX_IO_OCE[2]	INT:MUX.IMUX_IO_OCE[0][1]	INT:MUX.IMUX_IO_OCE[1][1]	INT:MUX.IMUX_IO_OCE[1][2]	-	-	INT:MUX.IMUX_IO_OCE[1][0]	INT:MUX.IMUX_IO_TCE[3][1]	INT:MUX.IMUX_IO_TCE[2][1]	INT:MUX.IMUX_IO_TCE[2][2]	~INT:INV.IMUX_IO_TCE[2]	-	INT:MUX.IMUX_IO_TCE[0][2]	INT:MUX.IMUX_IO_TCE[0][1]	INT:MUX.IMUX_IO_TCE[1][1]	INT:MUX.IMUX_IO_SR[1][3]	-	-	INT:MUX.IMUX_IO_SR[1][1]	INT:MUX.IMUX_IO_SR[1][2]	INT:MUX.IMUX_IO_SR[0][2]	INT:INV.IMUX_IO_SR[2]	INT:MUX.IMUX_IO_SR[3][2]	INT:MUX.IMUX_IO_SR[2][1]	-	INT:MUX.IMUX_IO_SR[2][2]	INT:MUX.IMUX_IO_SR[3][1]	INT:MUX.IMUX_IO_T[0][2]	-	INT:MUX.IMUX_IO_T[1][2]	INT:MUX.IMUX_IO_T[1][1]	-	INT:MUX.IMUX_IO_T[3][2]	INT:MUX.IMUX_IO_T[2][2]	INT:MUX.IMUX_IO_T[2][1]
B8	INT:PASS.SINGLE_N[23].HEX_H0[3]	-	INT:PASS.SINGLE_N[22].HEX_H3[3]	INT:PASS.SINGLE_N[22].OUT_IO_IQ[1]	INT:PASS.SINGLE_N[21].OUT_IO_IQ[2]	INT:PASS.SINGLE_N[21].HEX_H6[3]	-	INT:PASS.SINGLE_N[20].HEX_H0[3]	-	INT:PASS.SINGLE_N[19].HEX_H3[3]	INT:PASS.SINGLE_N[18].OUT_IO_I[1]	INT:PASS.SINGLE_N[18].HEX_H6[3]	INT:PASS.SINGLE_N[17].HEX_H0[2]	INT:PASS.SINGLE_N[17].OUT_IO_I[2]	INT:PASS.SINGLE_N[16].HEX_H3[2]	-	-	INT:PASS.SINGLE_N[15].HEX_H6[2]	INT:PASS.SINGLE_N[14].OUT_IO_IQ[1]	INT:PASS.SINGLE_N[14].HEX_H0[2]	INT:PASS.SINGLE_N[13].OUT_IO_IQ[2]	INT:PASS.SINGLE_N[13].HEX_H3[2]	-	INT:PASS.SINGLE_N[12].HEX_H6[2]	INT:PASS.SINGLE_N[11].HEX_H0[1]	-	INT:PASS.SINGLE_N[10].HEX_H3[1]	INT:PASS.SINGLE_N[10].OUT_IO_I[1]	INT:PASS.SINGLE_N[9].OUT_IO_I[2]	INT:PASS.SINGLE_N[9].HEX_H6[1]	-	INT:PASS.SINGLE_N[8].HEX_H0[1]	-	INT:PASS.SINGLE_N[7].HEX_H3[1]	INT:PASS.SINGLE_N[6].OUT_IO_IQ[1]	INT:PASS.SINGLE_N[6].HEX_H6[1]	INT:PASS.SINGLE_N[5].HEX_H0[0]	INT:PASS.SINGLE_N[5].OUT_IO_IQ[2]	INT:PASS.SINGLE_N[4].HEX_H3[0]	-	-	INT:PASS.SINGLE_N[3].HEX_H6[0]	INT:PASS.SINGLE_N[2].OUT_IO_I[1]	INT:PASS.SINGLE_N[2].HEX_H0[0]	INT:PASS.SINGLE_N[1].OUT_IO_I[2]	INT:PASS.SINGLE_N[1].HEX_H3[0]	-	INT:PASS.SINGLE_N[0].HEX_H6[0]
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT:DRIVE.HEX_H0[3]	INT:MUX.HEX_H6[3][5]	INT:MUX.HEX_H6[3][3]	INT:MUX.HEX_H0[3][1]	INT:MUX.HEX_H0[3][5]	INT:MUX.HEX_H0[3][6]	INT:MUX.HEX_H0[3][4]	INT:MUX.HEX_H0[3][0]	INT:MUX.HEX_H0[3][3]	INT:MUX.HEX_H6[3][2]	INT:MUX.HEX_H6[3][6]	INT:DRIVE.HEX_H6[3]	INT:DRIVE.HEX_H0[2]	INT:MUX.HEX_H6[2][5]	INT:MUX.HEX_H6[2][3]	INT:MUX.HEX_H0[2][1]	INT:MUX.HEX_H0[2][5]	INT:MUX.HEX_H0[2][6]	INT:MUX.HEX_H0[2][4]	INT:MUX.HEX_H0[2][0]	INT:MUX.HEX_H0[2][3]	INT:MUX.HEX_H6[2][2]	INT:MUX.HEX_H6[2][6]	INT:DRIVE.HEX_H6[2]	INT:DRIVE.HEX_H0[1]	INT:MUX.HEX_H6[1][5]	INT:MUX.HEX_H6[1][3]	INT:MUX.HEX_H0[1][1]	INT:MUX.HEX_H0[1][5]	INT:MUX.HEX_H0[1][6]	INT:MUX.HEX_H0[1][4]	INT:MUX.HEX_H0[1][0]	INT:MUX.HEX_H0[1][3]	INT:MUX.HEX_H6[1][2]	INT:MUX.HEX_H6[1][6]	INT:DRIVE.HEX_H6[1]	INT:DRIVE.HEX_H0[0]	INT:MUX.HEX_H6[0][5]	INT:MUX.HEX_H6[0][3]	INT:MUX.HEX_H0[0][1]	INT:MUX.HEX_H0[0][5]	INT:MUX.HEX_H0[0][6]	INT:MUX.HEX_H0[0][4]	INT:MUX.HEX_H0[0][0]	INT:MUX.HEX_H0[0][3]	INT:MUX.HEX_H6[0][2]	INT:MUX.HEX_H6[0][6]	INT:DRIVE.HEX_H6[0]
B5	INT:MUX.HEX_H6[3][0]	INT:MUX.HEX_H0[3][2]	-	-	-	-	-	-	-	-	INT:MUX.HEX_H6[3][4]	INT:MUX.HEX_H6[3][1]	INT:MUX.HEX_H6[2][0]	INT:MUX.HEX_H0[2][2]	-	-	-	-	-	-	-	-	INT:MUX.HEX_H6[2][4]	INT:MUX.HEX_H6[2][1]	INT:MUX.HEX_H6[1][0]	INT:MUX.HEX_H0[1][2]	-	-	-	-	-	-	-	-	INT:MUX.HEX_H6[1][4]	INT:MUX.HEX_H6[1][1]	INT:MUX.HEX_H6[0][0]	INT:MUX.HEX_H0[0][2]	-	-	-	-	-	-	-	-	INT:MUX.HEX_H6[0][4]	INT:MUX.HEX_H6[0][1]
B4	INT:DRIVE.HEX_V0[3]	-	INT:MUX.HEX_V0[3][1]	INT:DRIVE.HEX_V1[3]	INT:DRIVE.HEX_V2[3]	-	-	INT:DRIVE.HEX_V3[3]	INT:DRIVE.HEX_V4[3]	-	-	INT:DRIVE.HEX_V5[3]	INT:DRIVE.HEX_V5[2]	-	-	INT:DRIVE.HEX_V4[2]	INT:DRIVE.HEX_V3[2]	-	-	INT:DRIVE.HEX_V2[2]	INT:DRIVE.HEX_V1[2]	INT:MUX.HEX_V0[2][3]	INT:MUX.HEX_V1[2][1]	INT:DRIVE.HEX_V0[2]	INT:DRIVE.HEX_V0[1]	-	INT:MUX.HEX_V0[1][3]	INT:DRIVE.HEX_V1[1]	INT:DRIVE.HEX_V2[1]	-	-	INT:DRIVE.HEX_V3[1]	INT:DRIVE.HEX_V4[1]	-	-	INT:DRIVE.HEX_V5[1]	INT:DRIVE.HEX_V5[0]	-	-	INT:DRIVE.HEX_V4[0]	INT:DRIVE.HEX_V3[0]	-	-	INT:DRIVE.HEX_V2[0]	INT:DRIVE.HEX_V1[0]	INT:MUX.HEX_V0[0][2]	INT:MUX.HEX_V1[0][1]	INT:DRIVE.HEX_V0[0]
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	INT:MUX.HEX_V0[3][0]	-	INT:MUX.HEX_V0[3][4]	INT:MUX.HEX_V1[3][0]	INT:MUX.HEX_V2[3][1]	INT:MUX.HEX_V3[3][1]	-	INT:MUX.HEX_V3[3][0]	INT:MUX.HEX_V4[3][2]	INT:MUX.HEX_V5[3][2]	-	INT:MUX.HEX_V5[3][0]	INT:MUX.HEX_V5[2][0]	INT:MUX.HEX_V5[2][1]	-	-	INT:MUX.HEX_V3[2][0]	INT:MUX.HEX_V3[2][1]	-	-	INT:MUX.HEX_V1[2][0]	-	INT:MUX.HEX_V0[2][4]	INT:MUX.HEX_V0[2][0]	INT:MUX.HEX_V0[1][0]	-	INT:MUX.HEX_V0[1][4]	INT:MUX.HEX_V1[1][0]	INT:MUX.HEX_V2[1][1]	INT:MUX.HEX_V3[1][1]	-	INT:MUX.HEX_V3[1][0]	INT:MUX.HEX_V4[1][2]	INT:MUX.HEX_V5[1][2]	-	INT:MUX.HEX_V5[1][0]	INT:MUX.HEX_V5[0][0]	INT:MUX.HEX_V5[0][1]	-	-	INT:MUX.HEX_V3[0][0]	INT:MUX.HEX_V3[0][1]	-	-	INT:MUX.HEX_V1[0][0]	-	INT:MUX.HEX_V0[0][4]	INT:MUX.HEX_V0[0][0]
B1	INT:MUX.HEX_N0[3][0]	INT:MUX.HEX_N0[3][1]	INT:MUX.HEX_N1[3][1]	INT:MUX.HEX_N1[3][2]	INT:MUX.HEX_N0[3][2]	INT:MUX.HEX_N0[3][3]	INT:MUX.HEX_N1[3][3]	-	-	-	-	INT:MUX.HEX_N1[3][0]	INT:MUX.HEX_N0[1][0]	INT:MUX.HEX_N0[1][2]	INT:MUX.HEX_N1[1][2]	INT:MUX.HEX_N1[1][3]	INT:MUX.HEX_N0[1][3]	INT:MUX.HEX_N0[1][1]	INT:MUX.HEX_N1[1][1]	INT:MUX.HEX_N1[1][5]	INT:MUX.HEX_N0[1][5]	INT:MUX.HEX_N0[1][4]	INT:MUX.HEX_N1[1][4]	INT:MUX.HEX_N1[1][0]	INT:MUX.HEX_N0[2][0]	INT:MUX.HEX_N0[2][3]	INT:MUX.HEX_N1[2][3]	INT:MUX.HEX_N1[2][1]	INT:MUX.HEX_N0[2][1]	INT:MUX.HEX_N0[2][2]	INT:MUX.HEX_N1[2][2]	INT:MUX.HEX_N1[2][5]	INT:MUX.HEX_N0[2][5]	INT:MUX.HEX_N0[2][4]	INT:MUX.HEX_N1[2][4]	INT:MUX.HEX_N1[2][0]	INT:MUX.HEX_N0[0][0]	INT:MUX.HEX_N0[0][1]	INT:MUX.HEX_N1[0][1]	INT:MUX.HEX_N1[0][2]	INT:MUX.HEX_N0[0][2]	INT:MUX.HEX_N0[0][3]	INT:MUX.HEX_N1[0][3]	-	-	-	-	INT:MUX.HEX_N1[0][0]
B0	INT:MUX.HEX_V0[3][3]	INT:MUX.HEX_V0[3][2]	INT:MUX.HEX_V1[3][2]	INT:MUX.HEX_V1[3][1]	INT:MUX.HEX_V2[3][0]	-	-	-	INT:MUX.HEX_V4[3][0]	INT:MUX.HEX_V5[3][1]	INT:MUX.HEX_V4[3][1]	-	INT:MUX.HEX_V4[2][1]	-	-	INT:MUX.HEX_V4[2][0]	INT:MUX.HEX_V2[2][1]	INT:MUX.HEX_V2[2][2]	INT:MUX.HEX_V3[2][2]	INT:MUX.HEX_V2[2][0]	-	-	INT:MUX.HEX_V0[2][1]	INT:MUX.HEX_V0[2][2]	INT:MUX.HEX_V0[1][2]	INT:MUX.HEX_V0[1][1]	INT:MUX.HEX_V1[1][1]	-	INT:MUX.HEX_V2[1][0]	-	-	-	INT:MUX.HEX_V4[1][0]	INT:MUX.HEX_V5[1][1]	INT:MUX.HEX_V4[1][1]	-	INT:MUX.HEX_V4[0][1]	-	-	INT:MUX.HEX_V4[0][0]	INT:MUX.HEX_V2[0][1]	INT:MUX.HEX_V2[0][2]	INT:MUX.HEX_V3[0][2]	INT:MUX.HEX_V2[0][0]	INT:MUX.HEX_V1[0][2]	-	INT:MUX.HEX_V0[0][3]	INT:MUX.HEX_V0[0][1]

INT:DRIVE.HEX_H0[0]	0.F36.B6
INT:DRIVE.HEX_H0[1]	0.F24.B6
INT:DRIVE.HEX_H0[2]	0.F12.B6
INT:DRIVE.HEX_H0[3]	0.F0.B6
INT:DRIVE.HEX_H0[4]	0.F45.B15
INT:DRIVE.HEX_H0[5]	0.F19.B15
INT:DRIVE.HEX_H6[0]	0.F47.B6
INT:DRIVE.HEX_H6[1]	0.F35.B6
INT:DRIVE.HEX_H6[2]	0.F23.B6
INT:DRIVE.HEX_H6[3]	0.F11.B6
INT:DRIVE.HEX_H6[4]	0.F28.B15
INT:DRIVE.HEX_H6[5]	0.F37.B15
INT:DRIVE.HEX_V0[0]	0.F47.B4
INT:DRIVE.HEX_V0[1]	0.F24.B4
INT:DRIVE.HEX_V0[2]	0.F23.B4
INT:DRIVE.HEX_V0[3]	0.F0.B4
INT:DRIVE.HEX_V1[0]	0.F44.B4
INT:DRIVE.HEX_V1[1]	0.F27.B4
INT:DRIVE.HEX_V1[2]	0.F20.B4
INT:DRIVE.HEX_V1[3]	0.F3.B4
INT:DRIVE.HEX_V2[0]	0.F43.B4
INT:DRIVE.HEX_V2[1]	0.F28.B4
INT:DRIVE.HEX_V2[2]	0.F19.B4
INT:DRIVE.HEX_V2[3]	0.F4.B4
INT:DRIVE.HEX_V3[0]	0.F40.B4
INT:DRIVE.HEX_V3[1]	0.F31.B4
INT:DRIVE.HEX_V3[2]	0.F16.B4
INT:DRIVE.HEX_V3[3]	0.F7.B4
INT:DRIVE.HEX_V4[0]	0.F39.B4
INT:DRIVE.HEX_V4[1]	0.F32.B4
INT:DRIVE.HEX_V4[2]	0.F15.B4
INT:DRIVE.HEX_V4[3]	0.F8.B4
INT:DRIVE.HEX_V5[0]	0.F36.B4
INT:DRIVE.HEX_V5[1]	0.F35.B4
INT:DRIVE.HEX_V5[2]	0.F12.B4
INT:DRIVE.HEX_V5[3]	0.F11.B4
INT:DRIVE.LH[0]	0.F10.B15
INT:DRIVE.LH[6]	0.F3.B15
INT:DRIVE.LV[0]	0.F26.B12
INT:DRIVE.LV[10]	0.F5.B12
INT:DRIVE.LV[11]	0.F2.B12
INT:DRIVE.LV[1]	0.F29.B12
INT:DRIVE.LV[2]	0.F34.B12
INT:DRIVE.LV[3]	0.F37.B12
INT:DRIVE.LV[4]	0.F42.B12
INT:DRIVE.LV[5]	0.F45.B12
INT:DRIVE.LV[6]	0.F21.B12
INT:DRIVE.LV[7]	0.F18.B12
INT:DRIVE.LV[8]	0.F13.B12
INT:DRIVE.LV[9]	0.F10.B12
INT:INV.IMUX_IO_SR[1]	0.F33.B10
INT:INV.IMUX_IO_SR[2]	0.F34.B9
INT:PASS.SINGLE_N[0].HEX_H6[0]	0.F47.B8
INT:PASS.SINGLE_N[10].HEX_H3[1]	0.F26.B8
INT:PASS.SINGLE_N[10].OUT_IO_I[1]	0.F27.B8
INT:PASS.SINGLE_N[11].HEX_H0[1]	0.F24.B8
INT:PASS.SINGLE_N[12].HEX_H6[2]	0.F23.B8
INT:PASS.SINGLE_N[13].HEX_H3[2]	0.F21.B8
INT:PASS.SINGLE_N[13].OUT_IO_IQ[2]	0.F20.B8
INT:PASS.SINGLE_N[14].HEX_H0[2]	0.F19.B8
INT:PASS.SINGLE_N[14].OUT_IO_IQ[1]	0.F18.B8
INT:PASS.SINGLE_N[15].HEX_H6[2]	0.F17.B8
INT:PASS.SINGLE_N[16].HEX_H3[2]	0.F14.B8
INT:PASS.SINGLE_N[17].HEX_H0[2]	0.F12.B8
INT:PASS.SINGLE_N[17].OUT_IO_I[2]	0.F13.B8
INT:PASS.SINGLE_N[18].HEX_H6[3]	0.F11.B8
INT:PASS.SINGLE_N[18].OUT_IO_I[1]	0.F10.B8
INT:PASS.SINGLE_N[19].HEX_H3[3]	0.F9.B8
INT:PASS.SINGLE_N[1].HEX_H3[0]	0.F45.B8
INT:PASS.SINGLE_N[1].OUT_IO_I[2]	0.F44.B8
INT:PASS.SINGLE_N[20].HEX_H0[3]	0.F7.B8
INT:PASS.SINGLE_N[21].HEX_H6[3]	0.F5.B8
INT:PASS.SINGLE_N[21].OUT_IO_IQ[2]	0.F4.B8
INT:PASS.SINGLE_N[22].HEX_H3[3]	0.F2.B8
INT:PASS.SINGLE_N[22].OUT_IO_IQ[1]	0.F3.B8
INT:PASS.SINGLE_N[23].HEX_H0[3]	0.F0.B8
INT:PASS.SINGLE_N[2].HEX_H0[0]	0.F43.B8
INT:PASS.SINGLE_N[2].OUT_IO_I[1]	0.F42.B8
INT:PASS.SINGLE_N[3].HEX_H6[0]	0.F41.B8
INT:PASS.SINGLE_N[4].HEX_H3[0]	0.F38.B8
INT:PASS.SINGLE_N[5].HEX_H0[0]	0.F36.B8
INT:PASS.SINGLE_N[5].OUT_IO_IQ[2]	0.F37.B8
INT:PASS.SINGLE_N[6].HEX_H6[1]	0.F35.B8
INT:PASS.SINGLE_N[6].OUT_IO_IQ[1]	0.F34.B8
INT:PASS.SINGLE_N[7].HEX_H3[1]	0.F33.B8
INT:PASS.SINGLE_N[8].HEX_H0[1]	0.F31.B8
INT:PASS.SINGLE_N[9].HEX_H6[1]	0.F29.B8
INT:PASS.SINGLE_N[9].OUT_IO_I[2]	0.F28.B8
IO[1]:IFF_DELAY_ENABLE	0.F38.B17
IO[1]:IFF_INIT	0.F46.B16
IO[1]:IFF_LATCH	0.F44.B16
IO[1]:IFF_SR_ENABLE	0.F43.B16
IO[1]:IFF_SR_SYNC	0.F47.B16
IO[1]:INV.IFF.CLK	0.F34.B14
IO[1]:INV.OFF.CLK	0.F33.B14
IO[1]:INV.TFF.CLK	0.F32.B14
IO[1]:I_DELAY_ENABLE	0.F45.B16
IO[1]:OFF_LATCH	0.F41.B16
IO[1]:OFF_SR_ENABLE	0.F42.B16
IO[1]:OFF_SR_SYNC	0.F38.B16
IO[1]:READBACK_IFF	0.F45.B17
IO[1]:READBACK_OFF	0.F39.B17
IO[1]:READBACK_TFF	0.F35.B17
IO[1]:TFF_LATCH	0.F34.B16
IO[1]:TFF_SR_ENABLE	0.F33.B16
IO[1]:TFF_SR_SYNC	0.F37.B16
IO[2]:IFF_DELAY_ENABLE	0.F27.B17
IO[2]:IFF_INIT	0.F19.B16
IO[2]:IFF_LATCH	0.F21.B16
IO[2]:IFF_SR_ENABLE	0.F22.B16
IO[2]:IFF_SR_SYNC	0.F18.B16
IO[2]:INV.IFF.CLK	0.F13.B14
IO[2]:INV.OFF.CLK	0.F14.B14
IO[2]:INV.TFF.CLK	0.F15.B14
IO[2]:I_DELAY_ENABLE	0.F20.B16
IO[2]:OFF_LATCH	0.F24.B16
IO[2]:OFF_SR_ENABLE	0.F23.B16
IO[2]:OFF_SR_SYNC	0.F27.B16
IO[2]:READBACK_IFF	0.F20.B17
IO[2]:READBACK_OFF	0.F26.B17
IO[2]:READBACK_TFF	0.F30.B17
IO[2]:TFF_LATCH	0.F31.B16
IO[2]:TFF_SR_ENABLE	0.F32.B16
IO[2]:TFF_SR_SYNC	0.F28.B16
non-inverted	[0]

INT:INV.IMUX_IO_ICE[1]	0.F5.B10
INT:INV.IMUX_IO_ICE[2]	0.F4.B10
INT:INV.IMUX_IO_OCE[1]	0.F14.B10
INT:INV.IMUX_IO_OCE[2]	0.F13.B9
INT:INV.IMUX_IO_O[1]	0.F38.B14
INT:INV.IMUX_IO_O[2]	0.F9.B14
INT:INV.IMUX_IO_TCE[1]	0.F25.B10
INT:INV.IMUX_IO_TCE[2]	0.F23.B9
INT:INV.IMUX_IO_T[1]	0.F42.B10
INT:INV.IMUX_IO_T[2]	0.F43.B10
IO[1]:OFF_INIT	0.F39.B16
IO[1]:SHORTEN_JTAG_CHAIN	0.F37.B17
IO[1]:TFF_INIT	0.F36.B16
IO[2]:OFF_INIT	0.F26.B16
IO[2]:SHORTEN_JTAG_CHAIN	0.F28.B17
IO[2]:TFF_INIT	0.F29.B16
inverted	~[0]

INT:MUX.HEX_H0[0]	0.F41.B6	0.F40.B6	0.F42.B6	0.F44.B6	0.F37.B5	0.F39.B6	0.F43.B6
HEX_H6[0]	0	0	0	0	0	0	1
HEX_V0[3]	0	0	0	0	0	1	0
HEX_V3[2]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[1]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[1]	1	0	1	0	1	0	0

INT:MUX.HEX_H0[1]	0.F29.B6	0.F28.B6	0.F30.B6	0.F32.B6	0.F25.B5	0.F27.B6	0.F31.B6
HEX_H6[1]	0	0	0	0	0	0	1
HEX_V0[0]	0	0	0	0	0	1	0
HEX_V3[3]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[1]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[1]	1	0	1	0	1	0	0

INT:MUX.HEX_H0[2]	0.F17.B6	0.F16.B6	0.F18.B6	0.F20.B6	0.F13.B5	0.F15.B6	0.F19.B6
HEX_H6[2]	0	0	0	0	0	0	1
HEX_V0[1]	0	0	0	0	0	1	0
HEX_V3[0]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[1]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[1]	1	0	1	0	1	0	0

INT:MUX.HEX_H0[3]	0.F5.B6	0.F4.B6	0.F6.B6	0.F8.B6	0.F1.B5	0.F3.B6	0.F7.B6
HEX_H6[3]	0	0	0	0	0	0	1
HEX_V0[2]	0	0	0	0	0	1	0
HEX_V3[1]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[1]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[1]	1	0	1	0	1	0	0

INT:MUX.HEX_H0[4]	0.F41.B15	0.F39.B15	0.F40.B15	0.F43.B15	0.F44.B15	0.F35.B15	0.F34.B15
SINGLE_N_BUF[0]	0	0	0	0	0	0	1
SINGLE_N_BUF[7]	0	0	0	0	0	1	0
HEX_H6[4]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	1	0	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	1	0	0	0

INT:MUX.HEX_H0[5]	0.F23.B15	0.F25.B15	0.F22.B15	0.F20.B15	0.F18.B15	0.F27.B15	0.F29.B15
SINGLE_N_BUF[12]	0	0	0	0	0	0	1
SINGLE_N_BUF[19]	0	0	0	0	0	1	0
HEX_H6[5]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	1	0	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	1	0	0	0

INT:MUX.HEX_H6[0]	0.F46.B6	0.F37.B6	0.F46.B5	0.F38.B6	0.F45.B6	0.F47.B5	0.F36.B5
HEX_H0[0]	0	0	0	0	0	0	1
HEX_V0[0]	0	0	0	0	0	1	0
HEX_V3[2]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[1]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[1]	1	0	1	0	1	0	0

INT:MUX.HEX_H6[1]	0.F34.B6	0.F25.B6	0.F34.B5	0.F26.B6	0.F33.B6	0.F35.B5	0.F24.B5
HEX_H0[1]	0	0	0	0	0	0	1
HEX_V0[1]	0	0	0	0	0	1	0
HEX_V3[3]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[1]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[1]	1	0	1	0	1	0	0

INT:MUX.HEX_H6[2]	0.F22.B6	0.F13.B6	0.F22.B5	0.F14.B6	0.F21.B6	0.F23.B5	0.F12.B5
HEX_H0[2]	0	0	0	0	0	0	1
HEX_V0[2]	0	0	0	0	0	1	0
HEX_V3[0]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[1]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[1]	1	0	1	0	1	0	0

INT:MUX.HEX_H6[3]	0.F10.B6	0.F1.B6	0.F10.B5	0.F2.B6	0.F9.B6	0.F11.B5	0.F0.B5
HEX_H0[3]	0	0	0	0	0	0	1
HEX_V0[3]	0	0	0	0	0	1	0
HEX_V3[1]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	1	0
OUT_IO_I[1]	0	1	1	0	1	0	0
OUT_IO_IQ[2]	1	0	1	0	0	1	0
OUT_IO_IQ[1]	1	0	1	0	1	0	0

INT:MUX.HEX_H6[4]	0.F24.B15	0.F31.B15	0.F16.B15	0.F21.B15	0.F17.B15	0.F26.B15	0.F30.B15
SINGLE_N_BUF[12]	0	0	0	0	0	0	1
SINGLE_N_BUF[19]	0	0	0	0	0	1	0
HEX_H0[4]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	1	0	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	1	0	0	0

INT:MUX.HEX_H6[5]	0.F36.B15	0.F32.B15	0.F47.B15	0.F42.B15	0.F46.B15	0.F38.B15	0.F33.B15
SINGLE_N_BUF[0]	0	0	0	0	0	0	1
SINGLE_N_BUF[7]	0	0	0	0	0	1	0
HEX_H0[5]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	1	0	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	1	0	0	0

INT:MUX.HEX_N0[0]	0.F41.B1	0.F40.B1	0.F37.B1	0.F36.B1
HEX_H0[2]	0	1	1	1
HEX_H3[1]	1	0	1	1
HEX_H6[0]	1	1	0	1
HEX_S1[0]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_N0[1]	0.F20.B1	0.F21.B1	0.F16.B1	0.F13.B1	0.F17.B1	0.F12.B1
HEX_H0[1]	0	0	0	1	1	1
HEX_H3[0]	0	0	1	0	1	1
HEX_H6[3]	0	0	1	1	0	1
HEX_S1[1]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[1]	0	1	1	1	1	1
OUT_IO_IQ[1]	1	0	1	1	1	1

INT:MUX.HEX_N0[2]	0.F32.B1	0.F33.B1	0.F25.B1	0.F29.B1	0.F28.B1	0.F24.B1
HEX_H0[0]	0	0	0	1	1	1
HEX_H3[3]	0	0	1	0	1	1
HEX_H6[2]	0	0	1	1	0	1
HEX_S1[2]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_IQ[2]	1	0	1	1	1	1

INT:MUX.HEX_N0[3]	0.F5.B1	0.F4.B1	0.F1.B1	0.F0.B1
HEX_H0[3]	0	1	1	1
HEX_H3[2]	1	0	1	1
HEX_H6[1]	1	1	0	1
HEX_S1[3]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_N1[0]	0.F42.B1	0.F39.B1	0.F38.B1	0.F47.B1
HEX_H0[2]	0	1	1	1
HEX_H3[1]	1	0	1	1
HEX_H6[0]	1	1	0	1
HEX_S2[0]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_N1[1]	0.F19.B1	0.F22.B1	0.F15.B1	0.F14.B1	0.F18.B1	0.F23.B1
HEX_H0[1]	0	0	0	1	1	1
HEX_H3[0]	0	0	1	0	1	1
HEX_H6[3]	0	0	1	1	0	1
HEX_S2[1]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[1]	0	1	1	1	1	1
OUT_IO_IQ[1]	1	0	1	1	1	1

INT:MUX.HEX_N1[2]	0.F31.B1	0.F34.B1	0.F26.B1	0.F30.B1	0.F27.B1	0.F35.B1
HEX_H0[0]	0	0	0	1	1	1
HEX_H3[3]	0	0	1	0	1	1
HEX_H6[2]	0	0	1	1	0	1
HEX_S2[2]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_IQ[2]	1	0	1	1	1	1

INT:MUX.HEX_N1[3]	0.F6.B1	0.F3.B1	0.F2.B1	0.F11.B1
HEX_H0[3]	0	1	1	1
HEX_H3[2]	1	0	1	1
HEX_H6[1]	1	1	0	1
HEX_S2[3]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_V0[0]	0.F46.B2	0.F46.B0	0.F45.B4	0.F47.B0	0.F47.B2
HEX_H0[1]	0	0	1	1	1
HEX_H3[3]	0	1	0	1	1
HEX_H6[0]	0	1	1	0	1
LV[0]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_I[1]	1	1	1	1	1

INT:MUX.HEX_V0[1]	0.F26.B2	0.F26.B4	0.F24.B0	0.F25.B0	0.F24.B2
HEX_H0[2]	0	0	1	1	1
HEX_H3[0]	0	1	0	1	1
HEX_H6[1]	0	1	1	0	1
LV[0]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_I[2]	1	1	1	1	1

INT:MUX.HEX_V0[2]	0.F22.B2	0.F21.B4	0.F23.B0	0.F22.B0	0.F23.B2
HEX_H0[3]	0	0	1	1	1
HEX_H3[1]	0	1	0	1	1
HEX_H6[2]	0	1	1	0	1
LV[6]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_IQ[1]	1	1	1	1	1

INT:MUX.HEX_V0[3]	0.F2.B2	0.F0.B0	0.F1.B0	0.F2.B4	0.F0.B2
HEX_H0[0]	0	0	1	1	1
HEX_H3[2]	0	1	0	1	1
HEX_H6[3]	0	1	1	0	1
LV[6]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_IQ[2]	1	1	1	1	1

INT:MUX.HEX_V1[0]	0.F44.B0	0.F46.B4	0.F44.B2
LV[11]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_V1[1]	0.F26.B0	0.F27.B2
LV[11]	0	0
NONE	0	1
OUT_IO_I[2]	1	1

INT:MUX.HEX_V1[2]	0.F22.B4	0.F20.B2
LV[5]	0	0
NONE	0	1
OUT_IO_IQ[1]	1	1

INT:MUX.HEX_V1[3]	0.F2.B0	0.F3.B0	0.F3.B2
LV[5]	0	0	0
NONE	0	0	1
OUT_IO_I[2]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V2[0]	0.F41.B0	0.F40.B0	0.F43.B0
LV[10]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V2[1]	0.F28.B2	0.F28.B0
LV[10]	0	0
NONE	0	1
OUT_IO_I[1]	1	1

INT:MUX.HEX_V2[2]	0.F17.B0	0.F16.B0	0.F19.B0
LV[4]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_V2[3]	0.F4.B2	0.F4.B0
LV[4]	0	0
NONE	0	1
OUT_IO_IQ[1]	1	1

INT:MUX.HEX_V3[0]	0.F42.B0	0.F41.B2	0.F40.B2
LV[9]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V3[1]	0.F29.B2	0.F31.B2
LV[9]	0	0
NONE	0	1
OUT_IO_I[1]	1	1

INT:MUX.HEX_V3[2]	0.F18.B0	0.F17.B2	0.F16.B2
LV[3]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_V3[3]	0.F5.B2	0.F7.B2
LV[3]	0	0
NONE	0	1
OUT_IO_IQ[1]	1	1

INT:MUX.HEX_V4[0]	0.F36.B0	0.F39.B0
LV[8]	0	0
NONE	0	1
OUT_IO_I[2]	1	1

INT:MUX.HEX_V4[1]	0.F32.B2	0.F34.B0	0.F32.B0
LV[8]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V4[2]	0.F12.B0	0.F15.B0
LV[2]	0	0
NONE	0	1
OUT_IO_IQ[2]	1	1

INT:MUX.HEX_V4[3]	0.F8.B2	0.F10.B0	0.F8.B0
LV[2]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_V5[0]	0.F37.B2	0.F36.B2
LV[7]	0	0
NONE	0	1
OUT_IO_I[2]	1	1

INT:MUX.HEX_V5[1]	0.F33.B2	0.F33.B0	0.F35.B2
LV[7]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V5[2]	0.F13.B2	0.F12.B2
LV[1]	0	0
NONE	0	1
OUT_IO_IQ[2]	1	1

INT:MUX.HEX_V5[3]	0.F9.B2	0.F9.B0	0.F11.B2
LV[1]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.IMUX_IO_CLK[0]	0.F30.B12	0.F30.B14	0.F29.B14	0.F36.B13	0.F26.B14	0.F30.B13	0.F24.B13	0.F25.B14	0.F25.B13	0.F27.B13	0.F27.B14	0.F35.B13
INT:MUX.IMUX_IO_CLK[1]	0.F28.B14	0.F31.B14	0.F28.B13	0.F33.B13	0.F25.B12	0.F24.B14	0.F31.B13	0.F34.B13	0.F26.B13	0.F32.B13	0.F29.B13	0.F37.B13
INT:MUX.IMUX_IO_CLK[2]	0.F19.B14	0.F16.B14	0.F19.B13	0.F14.B13	0.F22.B12	0.F23.B14	0.F16.B13	0.F13.B13	0.F21.B13	0.F15.B13	0.F18.B13	0.F10.B13
INT:MUX.IMUX_IO_CLK[3]	0.F17.B12	0.F17.B14	0.F18.B14	0.F11.B13	0.F21.B14	0.F17.B13	0.F23.B13	0.F22.B14	0.F22.B13	0.F20.B13	0.F20.B14	0.F12.B13
GCLK_BUF[0]	0	0	0	0	0	0	1	1	1	1	1	1
GCLK_BUF[1]	0	0	0	0	0	1	0	1	1	1	1	1
GCLK_BUF[2]	0	0	0	0	0	1	1	0	1	1	1	1
GCLK_BUF[3]	0	0	0	0	0	1	1	1	0	1	1	1
NONE	0	0	0	0	0	1	1	1	1	1	1	1
HEX_V4_BUF[2]	0	0	0	1	0	1	1	1	1	0	1	1
HEX_H5_BUF[2]	0	0	0	1	0	1	1	1	1	1	0	1
HEX_V5_BUF[2]	0	0	0	1	0	1	1	1	1	1	1	0
SINGLE_N_BUF[8]	0	0	0	1	1	1	1	1	1	1	1	1
HEX_H1_BUF[2]	0	0	1	0	0	1	1	1	1	0	1	1
HEX_H4_BUF[2]	0	0	1	0	0	1	1	1	1	1	0	1
HEX_V1_BUF[2]	0	0	1	0	0	1	1	1	1	1	1	0
SINGLE_N_BUF[9]	0	0	1	0	1	1	1	1	1	1	1	1
HEX_V0_BUF[2]	0	1	0	0	0	1	1	1	1	0	1	1
HEX_H6_BUF[2]	0	1	0	0	0	1	1	1	1	1	0	1
HEX_V3_BUF[2]	0	1	0	0	0	1	1	1	1	1	1	0
SINGLE_N_BUF[14]	0	1	0	0	1	1	1	1	1	1	1	1
HEX_H2_BUF[2]	1	0	0	0	0	1	1	1	1	0	1	1
HEX_H3_BUF[2]	1	0	0	0	0	1	1	1	1	1	0	1
HEX_V2_BUF[2]	1	0	0	0	0	1	1	1	1	1	1	0
SINGLE_N_BUF[15]	1	0	0	0	1	1	1	1	1	1	1	1

INT:MUX.IMUX_IO_ICE[0]	0.F8.B10	0.F7.B10	0.F5.B11	0.F6.B11	0.F7.B9	0.F6.B10
INT:MUX.IMUX_IO_ICE[1]	0.F7.B11	0.F8.B11	0.F9.B11	0.F4.B9	0.F5.B9	0.F9.B10
INT:MUX.IMUX_IO_ICE[2]	0.F2.B11	0.F1.B11	0.F0.B11	0.F0.B9	0.F1.B9	0.F0.B10
INT:MUX.IMUX_IO_ICE[3]	0.F1.B10	0.F2.B10	0.F3.B11	0.F4.B11	0.F2.B9	0.F3.B10
NONE	0	0	0	0	0	0
SINGLE_N_BUF[20]	0	0	0	0	0	1
SINGLE_N_BUF[21]	0	0	0	0	1	0
SINGLE_N_BUF[22]	0	0	0	1	0	0
SINGLE_N_BUF[23]	0	0	1	0	0	0
HEX_V1_BUF[3]	0	1	0	0	0	1
HEX_V0_BUF[3]	0	1	0	0	1	0
HEX_H4_BUF[3]	0	1	0	1	0	0
HEX_H1_BUF[3]	0	1	1	0	0	0
HEX_V5_BUF[3]	1	0	0	0	0	1
HEX_V4_BUF[3]	1	0	0	0	1	0
HEX_V2_BUF[3]	1	0	0	1	0	0
HEX_V3_BUF[3]	1	0	1	0	0	0
HEX_H6_BUF[3]	1	1	0	0	0	1
HEX_H5_BUF[3]	1	1	0	0	1	0
HEX_H3_BUF[3]	1	1	0	1	0	0
HEX_H2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_OCE[0]	0.F18.B10	0.F17.B10	0.F14.B11	0.F15.B11	0.F14.B9	0.F16.B10
INT:MUX.IMUX_IO_OCE[1]	0.F17.B11	0.F18.B11	0.F19.B11	0.F16.B9	0.F15.B9	0.F19.B9
INT:MUX.IMUX_IO_OCE[2]	0.F12.B11	0.F11.B11	0.F10.B11	0.F11.B9	0.F9.B9	0.F10.B10
INT:MUX.IMUX_IO_OCE[3]	0.F11.B10	0.F12.B10	0.F13.B11	0.F8.B9	0.F12.B9	0.F13.B10
NONE	0	0	0	0	0	0
SINGLE_N_BUF[16]	0	0	0	0	0	1
SINGLE_N_BUF[17]	0	0	0	0	1	0
SINGLE_N_BUF[18]	0	0	0	1	0	0
SINGLE_N_BUF[19]	0	0	1	0	0	0
HEX_V1_BUF[3]	0	1	0	0	0	1
HEX_V0_BUF[3]	0	1	0	0	1	0
HEX_H4_BUF[3]	0	1	0	1	0	0
HEX_H1_BUF[3]	0	1	1	0	0	0
HEX_V5_BUF[3]	1	0	0	0	0	1
HEX_V4_BUF[3]	1	0	0	0	1	0
HEX_V2_BUF[3]	1	0	0	1	0	0
HEX_V3_BUF[3]	1	0	1	0	0	0
HEX_H6_BUF[3]	1	1	0	0	0	1
HEX_H5_BUF[3]	1	1	0	0	1	0
HEX_H3_BUF[3]	1	1	0	1	0	0
HEX_H2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_O[0]	0.F41.B13	0.F42.B13	0.F47.B13	0.F46.B13	0.F45.B14	0.F44.B13	0.F43.B13	0.F44.B14	0.F45.B13
NONE	0	0	0	0	0	0	0	0	1
HEX_V0_BUF[0]	0	0	0	0	0	0	1	0	0
SINGLE_N_BUF[0]	0	0	0	0	0	0	1	1	1
HEX_V3_BUF[0]	0	0	0	0	0	1	0	0	0
SINGLE_N_BUF[1]	0	0	0	0	0	1	0	1	1
SINGLE_N_BUF[3]	0	0	0	0	1	0	1	0	1
SINGLE_N_BUF[2]	0	0	0	0	1	1	0	0	1
HEX_V1_BUF[0]	0	0	0	1	0	0	0	0	0
SINGLE_N_BUF[9]	0	0	0	1	0	0	0	1	1
SINGLE_N_BUF[4]	0	0	0	1	1	0	0	0	1
HEX_V2_BUF[0]	0	0	1	0	0	0	0	0	0
SINGLE_N_BUF[8]	0	0	1	0	0	0	0	1	1
SINGLE_N_BUF[5]	0	0	1	0	1	0	0	0	1
SINGLE_N_BUF[6]	0	1	0	0	0	0	0	1	1
SINGLE_N_BUF[10]	0	1	0	0	1	0	0	0	1
SINGLE_N_BUF[7]	1	0	0	0	0	0	0	1	1
SINGLE_N_BUF[11]	1	0	0	0	1	0	0	0	1

INT:MUX.IMUX_IO_O[1]	0.F43.B14	0.F42.B14	0.F43.B12	0.F41.B12	0.F41.B14	0.F39.B13	0.F38.B13	0.F40.B14	0.F40.B13
NONE	0	0	0	0	0	0	0	0	1
HEX_V2_BUF[1]	0	0	0	0	0	0	1	0	0
SINGLE_N_BUF[0]	0	0	0	0	0	0	1	1	1
HEX_V3_BUF[1]	0	0	0	0	0	1	0	0	0
SINGLE_N_BUF[1]	0	0	0	0	0	1	0	1	1
SINGLE_N_BUF[3]	0	0	0	0	1	0	1	0	1
SINGLE_N_BUF[2]	0	0	0	0	1	1	0	0	1
HEX_V1_BUF[1]	0	0	0	1	0	0	0	0	0
SINGLE_N_BUF[9]	0	0	0	1	0	0	0	1	1
SINGLE_N_BUF[4]	0	0	0	1	1	0	0	0	1
HEX_V0_BUF[1]	0	0	1	0	0	0	0	0	0
SINGLE_N_BUF[8]	0	0	1	0	0	0	0	1	1
SINGLE_N_BUF[5]	0	0	1	0	1	0	0	0	1
SINGLE_N_BUF[6]	0	1	0	0	0	0	0	1	1
SINGLE_N_BUF[10]	0	1	0	0	1	0	0	0	1
SINGLE_N_BUF[7]	1	0	0	0	0	0	0	1	1
SINGLE_N_BUF[11]	1	0	0	0	1	0	0	0	1

INT:MUX.IMUX_IO_O[2]	0.F8.B13	0.F9.B13	0.F4.B12	0.F6.B12	0.F7.B14	0.F5.B14	0.F4.B14	0.F6.B14	0.F7.B13
NONE	0	0	0	0	0	0	0	0	1
SINGLE_N_BUF[12]	0	0	0	0	0	0	1	1	1
SINGLE_N_BUF[13]	0	0	0	0	0	1	0	1	1
SINGLE_N_BUF[16]	0	0	0	0	1	0	1	0	1
SINGLE_N_BUF[17]	0	0	0	0	1	1	0	0	1
HEX_V1_BUF[2]	0	0	0	1	0	0	0	0	0
SINGLE_N_BUF[19]	0	0	0	1	0	0	0	1	1
SINGLE_N_BUF[14]	0	0	0	1	1	0	0	0	1
HEX_V0_BUF[2]	0	0	1	0	0	0	0	0	0
SINGLE_N_BUF[18]	0	0	1	0	0	0	0	1	1
SINGLE_N_BUF[15]	0	0	1	0	1	0	0	0	1
HEX_V2_BUF[2]	0	1	0	0	0	0	0	0	0
SINGLE_N_BUF[20]	0	1	0	0	0	0	0	1	1
SINGLE_N_BUF[23]	0	1	0	0	1	0	0	0	1
HEX_V3_BUF[2]	1	0	0	0	0	0	0	0	0
SINGLE_N_BUF[21]	1	0	0	0	0	0	0	1	1
SINGLE_N_BUF[22]	1	0	0	0	1	0	0	0	1

INT:MUX.IMUX_IO_O[3]	0.F3.B13	0.F4.B13	0.F0.B13	0.F1.B13	0.F3.B14	0.F5.B13	0.F6.B13	0.F2.B14	0.F2.B13
NONE	0	0	0	0	0	0	0	0	1
SINGLE_N_BUF[12]	0	0	0	0	0	0	1	1	1
SINGLE_N_BUF[13]	0	0	0	0	0	1	0	1	1
SINGLE_N_BUF[16]	0	0	0	0	1	0	1	0	1
SINGLE_N_BUF[17]	0	0	0	0	1	1	0	0	1
HEX_V1_BUF[3]	0	0	0	1	0	0	0	0	0
SINGLE_N_BUF[19]	0	0	0	1	0	0	0	1	1
SINGLE_N_BUF[14]	0	0	0	1	1	0	0	0	1
HEX_V2_BUF[3]	0	0	1	0	0	0	0	0	0
SINGLE_N_BUF[18]	0	0	1	0	0	0	0	1	1
SINGLE_N_BUF[15]	0	0	1	0	1	0	0	0	1
HEX_V0_BUF[3]	0	1	0	0	0	0	0	0	0
SINGLE_N_BUF[20]	0	1	0	0	0	0	0	1	1
SINGLE_N_BUF[23]	0	1	0	0	1	0	0	0	1
HEX_V3_BUF[3]	1	0	0	0	0	0	0	0	0
SINGLE_N_BUF[21]	1	0	0	0	0	0	0	1	1
SINGLE_N_BUF[22]	1	0	0	0	1	0	0	0	1

INT:MUX.IMUX_IO_SR[0]	0.F29.B10	0.F30.B10	0.F31.B10	0.F33.B9	0.F32.B11	0.F33.B11
INT:MUX.IMUX_IO_SR[1]	0.F30.B11	0.F29.B11	0.F28.B9	0.F32.B9	0.F31.B9	0.F28.B11
INT:MUX.IMUX_IO_SR[2]	0.F35.B11	0.F36.B11	0.F37.B10	0.F38.B9	0.F36.B9	0.F37.B11
INT:MUX.IMUX_IO_SR[3]	0.F36.B10	0.F35.B10	0.F34.B10	0.F35.B9	0.F39.B9	0.F34.B11
NONE	0	0	0	0	0	0
SINGLE_N_BUF[4]	0	0	0	0	0	1
SINGLE_N_BUF[5]	0	0	0	0	1	0
SINGLE_N_BUF[6]	0	0	0	1	0	0
SINGLE_N_BUF[7]	0	0	1	0	0	0
HEX_H1_BUF[1]	0	1	0	0	0	1
HEX_H4_BUF[1]	0	1	0	0	1	0
HEX_V5_BUF[1]	0	1	0	1	0	0
HEX_V4_BUF[1]	0	1	1	0	0	0
HEX_V2_BUF[1]	1	0	0	0	0	1
HEX_V3_BUF[1]	1	0	0	0	1	0
HEX_V1_BUF[1]	1	0	0	1	0	0
HEX_V0_BUF[1]	1	0	1	0	0	0
HEX_H2_BUF[1]	1	1	0	0	0	1
HEX_H3_BUF[1]	1	1	0	0	1	0
HEX_H5_BUF[1]	1	1	0	1	0	0
HEX_H6_BUF[1]	1	1	1	0	0	0

INT:MUX.IMUX_IO_TCE[0]	0.F25.B11	0.F26.B11	0.F27.B11	0.F25.B9	0.F26.B9	0.F28.B10
INT:MUX.IMUX_IO_TCE[1]	0.F27.B10	0.F26.B10	0.F24.B11	0.F31.B11	0.F27.B9	0.F24.B10
INT:MUX.IMUX_IO_TCE[2]	0.F22.B11	0.F21.B11	0.F20.B11	0.F22.B9	0.F21.B9	0.F19.B10
INT:MUX.IMUX_IO_TCE[3]	0.F20.B10	0.F21.B10	0.F23.B11	0.F16.B11	0.F20.B9	0.F23.B10
NONE	0	0	0	0	0	0
SINGLE_N_BUF[10]	0	0	0	0	0	1
SINGLE_N_BUF[11]	0	0	0	0	1	0
SINGLE_N_BUF[12]	0	0	0	1	0	0
SINGLE_N_BUF[13]	0	0	1	0	0	0
HEX_V1_BUF[3]	0	1	0	0	0	1
HEX_V0_BUF[3]	0	1	0	0	1	0
HEX_H4_BUF[3]	0	1	0	1	0	0
HEX_H1_BUF[3]	0	1	1	0	0	0
HEX_V5_BUF[3]	1	0	0	0	0	1
HEX_V4_BUF[3]	1	0	0	0	1	0
HEX_V2_BUF[3]	1	0	0	1	0	0
HEX_V3_BUF[3]	1	0	1	0	0	0
HEX_H6_BUF[3]	1	1	0	0	0	1
HEX_H5_BUF[3]	1	1	0	0	1	0
HEX_H3_BUF[3]	1	1	0	1	0	0
HEX_H2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_T[0]	0.F39.B10	0.F40.B10	0.F41.B10	0.F40.B9	0.F41.B11	0.F42.B11
INT:MUX.IMUX_IO_T[1]	0.F40.B11	0.F39.B11	0.F38.B10	0.F42.B9	0.F43.B9	0.F38.B11
INT:MUX.IMUX_IO_T[2]	0.F45.B11	0.F46.B11	0.F47.B10	0.F46.B9	0.F47.B9	0.F47.B11
INT:MUX.IMUX_IO_T[3]	0.F46.B10	0.F45.B10	0.F44.B10	0.F45.B9	0.F43.B11	0.F44.B11
NONE	0	0	0	0	0	0
SINGLE_N_BUF[0]	0	0	0	0	0	1
SINGLE_N_BUF[1]	0	0	0	0	1	0
SINGLE_N_BUF[2]	0	0	0	1	0	0
SINGLE_N_BUF[3]	0	0	1	0	0	0
HEX_H1_BUF[0]	0	1	0	0	0	1
HEX_H4_BUF[0]	0	1	0	0	1	0
HEX_V0_BUF[0]	0	1	0	1	0	0
HEX_V1_BUF[0]	0	1	1	0	0	0
HEX_V3_BUF[0]	1	0	0	0	0	1
HEX_V2_BUF[0]	1	0	0	0	1	0
HEX_V4_BUF[0]	1	0	0	1	0	0
HEX_V5_BUF[0]	1	0	1	0	0	0
HEX_H2_BUF[0]	1	1	0	0	0	1
HEX_H3_BUF[0]	1	1	0	0	1	0
HEX_H5_BUF[0]	1	1	0	1	0	0
HEX_H6_BUF[0]	1	1	1	0	0	0

INT:MUX.LH[0]	0.F9.B15	0.F12.B12	0.F4.B15	0.F6.B15	0.F15.B15	0.F14.B12	0.F8.B15	0.F13.B15	0.F1.B12
INT:MUX.LH[6]	0.F5.B15	0.F9.B12	0.F1.B15	0.F7.B15	0.F14.B15	0.F11.B15	0.F12.B15	0.F2.B15	0.F0.B15
NONE	0	0	0	0	0	0	0	0	0
SINGLE_N_BUF[5]	0	0	0	0	0	0	0	0	1
SINGLE_N_BUF[6]	0	0	0	0	0	0	0	1	0
SINGLE_N_BUF[10]	0	0	0	0	0	0	1	0	0
SINGLE_N_BUF[11]	0	0	0	0	0	1	0	0	0
SINGLE_N_BUF[17]	0	0	0	0	1	0	0	0	0
SINGLE_N_BUF[18]	0	0	0	1	0	0	0	0	0
SINGLE_N_BUF[22]	0	0	1	0	0	0	0	0	0
SINGLE_N_BUF[23]	0	1	0	0	0	0	0	0	0
OUT_IO_IQ[2]	1	0	0	0	0	0	0	1	0
OUT_IO_I[2]	1	0	0	0	0	0	1	0	0
OUT_IO_IQ[1]	1	0	0	0	1	0	0	0	0
OUT_IO_I[1]	1	0	1	0	0	0	0	0	0

INT:MUX.LV[0]
HEX_H6[5]

INT:MUX.LV[10]
HEX_H2[4]

INT:MUX.LV[11]
HEX_H1[4]

INT:MUX.LV[1]
HEX_H5[5]

INT:MUX.LV[2]	0.F32.B12
HEX_H4[5]	0
OUT_IO_IQ[1]	1

INT:MUX.LV[3]	0.F39.B12
HEX_H3[5]	0
OUT_IO_IQ[1]	1

INT:MUX.LV[4]	0.F40.B12
HEX_H2[5]	0
OUT_IO_I[1]	1

INT:MUX.LV[5]	0.F47.B12
HEX_H1[5]	0
OUT_IO_I[1]	1

INT:MUX.LV[6]	0.F23.B12
HEX_H6[4]	0
OUT_IO_IQ[2]	1

INT:MUX.LV[7]	0.F16.B12
HEX_H5[4]	0
OUT_IO_IQ[2]	1

INT:MUX.LV[8]	0.F15.B12
HEX_H4[4]	0
OUT_IO_I[2]	1

INT:MUX.LV[9]	0.F8.B12
HEX_H3[4]	0
OUT_IO_I[2]	1

IO[1]:OMUX	0.F40.B16
IO[2]:OMUX	0.F25.B16
O	0
OFF	1

IO[1]:TMUX	0.F35.B16
IO[2]:TMUX	0.F30.B16
T	0
TFF	1

Tile IO_N

Cells: 1

Switchbox INT

virtex IO_N switchbox INT permanent buffers
Destination	Source
GCLK_BUF[0]	GCLK[0]
GCLK_BUF[1]	GCLK[1]
GCLK_BUF[2]	GCLK[2]
GCLK_BUF[3]	GCLK[3]
SINGLE_S_BUF[0]	SINGLE_S[0]
SINGLE_S_BUF[1]	SINGLE_S[1]
SINGLE_S_BUF[2]	SINGLE_S[2]
SINGLE_S_BUF[3]	SINGLE_S[3]
SINGLE_S_BUF[4]	SINGLE_S[4]
SINGLE_S_BUF[5]	SINGLE_S[5]
SINGLE_S_BUF[6]	SINGLE_S[6]
SINGLE_S_BUF[7]	SINGLE_S[7]
SINGLE_S_BUF[8]	SINGLE_S[8]
SINGLE_S_BUF[9]	SINGLE_S[9]
SINGLE_S_BUF[10]	SINGLE_S[10]
SINGLE_S_BUF[11]	SINGLE_S[11]
SINGLE_S_BUF[12]	SINGLE_S[12]
SINGLE_S_BUF[13]	SINGLE_S[13]
SINGLE_S_BUF[14]	SINGLE_S[14]
SINGLE_S_BUF[15]	SINGLE_S[15]
SINGLE_S_BUF[16]	SINGLE_S[16]
SINGLE_S_BUF[17]	SINGLE_S[17]
SINGLE_S_BUF[18]	SINGLE_S[18]
SINGLE_S_BUF[19]	SINGLE_S[19]
SINGLE_S_BUF[20]	SINGLE_S[20]
SINGLE_S_BUF[21]	SINGLE_S[21]
SINGLE_S_BUF[22]	SINGLE_S[22]
SINGLE_S_BUF[23]	SINGLE_S[23]
HEX_H1_BUF[0]	HEX_H1[0]
HEX_H1_BUF[1]	HEX_H1[1]
HEX_H1_BUF[2]	HEX_H1[2]
HEX_H1_BUF[3]	HEX_H1[3]
HEX_H2_BUF[0]	HEX_H2[0]
HEX_H2_BUF[1]	HEX_H2[1]
HEX_H2_BUF[2]	HEX_H2[2]
HEX_H2_BUF[3]	HEX_H2[3]
HEX_H3_BUF[0]	HEX_H3[0]
HEX_H3_BUF[1]	HEX_H3[1]
HEX_H3_BUF[2]	HEX_H3[2]
HEX_H3_BUF[3]	HEX_H3[3]
HEX_H4_BUF[0]	HEX_H4[0]
HEX_H4_BUF[1]	HEX_H4[1]
HEX_H4_BUF[2]	HEX_H4[2]
HEX_H4_BUF[3]	HEX_H4[3]
HEX_H5_BUF[0]	HEX_H5[0]
HEX_H5_BUF[1]	HEX_H5[1]
HEX_H5_BUF[2]	HEX_H5[2]
HEX_H5_BUF[3]	HEX_H5[3]
HEX_H6_BUF[0]	HEX_H6[0]
HEX_H6_BUF[1]	HEX_H6[1]
HEX_H6_BUF[2]	HEX_H6[2]
HEX_H6_BUF[3]	HEX_H6[3]
HEX_V1_BUF[0]	HEX_V1[0]
HEX_V1_BUF[1]	HEX_V1[1]
HEX_V1_BUF[2]	HEX_V1[2]
HEX_V1_BUF[3]	HEX_V1[3]
HEX_V2_BUF[0]	HEX_V2[0]
HEX_V2_BUF[1]	HEX_V2[1]
HEX_V2_BUF[2]	HEX_V2[2]
HEX_V2_BUF[3]	HEX_V2[3]
HEX_V3_BUF[0]	HEX_V3[0]
HEX_V3_BUF[1]	HEX_V3[1]
HEX_V3_BUF[2]	HEX_V3[2]
HEX_V3_BUF[3]	HEX_V3[3]
HEX_V4_BUF[0]	HEX_V4[0]
HEX_V4_BUF[1]	HEX_V4[1]
HEX_V4_BUF[2]	HEX_V4[2]
HEX_V4_BUF[3]	HEX_V4[3]
HEX_V5_BUF[0]	HEX_V5[0]
HEX_V5_BUF[1]	HEX_V5[1]
HEX_V5_BUF[2]	HEX_V5[2]
HEX_V5_BUF[3]	HEX_V5[3]
HEX_V6_BUF[0]	HEX_V6[0]
HEX_V6_BUF[1]	HEX_V6[1]
HEX_V6_BUF[2]	HEX_V6[2]
HEX_V6_BUF[3]	HEX_V6[3]
LH_FAKE0	LH[0]
LH_FAKE6	LH[6]

virtex IO_N switchbox INT pass gates
Destination	Source	Bit
SINGLE_S[0]	HEX_H6[0]	XXX57005[57005][57005]
SINGLE_S[0]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_S[1]	HEX_H3[0]	XXX57005[57005][57005]
SINGLE_S[1]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_S[2]	HEX_H0[0]	XXX57005[57005][57005]
SINGLE_S[2]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_S[3]	HEX_H6[0]	XXX57005[57005][57005]
SINGLE_S[3]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_S[4]	HEX_H3[0]	XXX57005[57005][57005]
SINGLE_S[4]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_S[5]	HEX_H0[0]	XXX57005[57005][57005]
SINGLE_S[5]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_S[6]	HEX_H6[1]	XXX57005[57005][57005]
SINGLE_S[6]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_S[7]	HEX_H3[1]	XXX57005[57005][57005]
SINGLE_S[7]	OUT_IO_IQ[0]	XXX57005[57005][57005]
SINGLE_S[8]	HEX_H0[1]	XXX57005[57005][57005]
SINGLE_S[8]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_S[9]	HEX_H6[1]	XXX57005[57005][57005]
SINGLE_S[9]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_S[10]	HEX_H3[1]	XXX57005[57005][57005]
SINGLE_S[10]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_S[11]	HEX_H0[1]	XXX57005[57005][57005]
SINGLE_S[11]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_S[12]	HEX_H6[2]	XXX57005[57005][57005]
SINGLE_S[12]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_S[13]	HEX_H3[2]	XXX57005[57005][57005]
SINGLE_S[13]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_S[14]	HEX_H0[2]	XXX57005[57005][57005]
SINGLE_S[14]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_S[15]	HEX_H6[2]	XXX57005[57005][57005]
SINGLE_S[15]	OUT_IO_IQ[0]	XXX57005[57005][57005]
SINGLE_S[16]	HEX_H3[2]	XXX57005[57005][57005]
SINGLE_S[16]	OUT_IO_I[3]	XXX57005[57005][57005]
SINGLE_S[17]	HEX_H0[2]	XXX57005[57005][57005]
SINGLE_S[17]	OUT_IO_I[2]	XXX57005[57005][57005]
SINGLE_S[18]	HEX_H6[3]	XXX57005[57005][57005]
SINGLE_S[18]	OUT_IO_I[1]	XXX57005[57005][57005]
SINGLE_S[19]	HEX_H3[3]	XXX57005[57005][57005]
SINGLE_S[19]	OUT_IO_I[0]	XXX57005[57005][57005]
SINGLE_S[20]	HEX_H0[3]	XXX57005[57005][57005]
SINGLE_S[20]	OUT_IO_IQ[3]	XXX57005[57005][57005]
SINGLE_S[21]	HEX_H6[3]	XXX57005[57005][57005]
SINGLE_S[21]	OUT_IO_IQ[2]	XXX57005[57005][57005]
SINGLE_S[22]	HEX_H3[3]	XXX57005[57005][57005]
SINGLE_S[22]	OUT_IO_IQ[1]	XXX57005[57005][57005]
SINGLE_S[23]	HEX_H0[3]	XXX57005[57005][57005]
SINGLE_S[23]	OUT_IO_IQ[0]	XXX57005[57005][57005]

virtex IO_N switchbox INT muxes HEX_H0[0]
Bits	Destination
HEX_H0[0]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H0[1]
Bits	Destination
HEX_H0[1]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H0[2]
Bits	Destination
HEX_H0[2]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H0[3]
Bits	Destination
HEX_H0[3]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H0[4]
Bits	Destination
HEX_H0[4]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H0[5]
Bits	Destination
HEX_H0[5]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H6[0]
Bits	Destination
HEX_H6[0]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H6[1]
Bits	Destination
HEX_H6[1]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H6[2]
Bits	Destination
HEX_H6[2]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H6[3]
Bits	Destination
HEX_H6[3]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H6[4]
Bits	Destination
HEX_H6[4]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_H6[5]
Bits	Destination
HEX_H6[5]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_V1[0]
Bits	Destination
HEX_V1[0]
	Source
OUT_IO_IQ[0]

virtex IO_N switchbox INT muxes HEX_V1[1]
Bits	Destination
HEX_V1[1]
	Source
OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V1[2]
Bits	Destination
HEX_V1[2]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_V1[3]
Bits	Destination
HEX_V1[3]
	Source
OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V2[0]
Bits	Destination
HEX_V2[0]
	Source
OUT_IO_IQ[0]

virtex IO_N switchbox INT muxes HEX_V2[1]
Bits	Destination
HEX_V2[1]
	Source
OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V2[2]
Bits	Destination
HEX_V2[2]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_V2[3]
Bits	Destination
HEX_V2[3]
	Source
OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V3[0]
Bits	Destination
HEX_V3[0]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_V3[1]
Bits	Destination
HEX_V3[1]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_V3[2]
Bits	Destination
HEX_V3[2]
	Source
OUT_IO_I[3]

virtex IO_N switchbox INT muxes HEX_V3[3]
Bits	Destination
HEX_V3[3]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V4[0]
Bits	Destination
HEX_V4[0]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_V4[1]
Bits	Destination
HEX_V4[1]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_V4[2]
Bits	Destination
HEX_V4[2]
	Source
OUT_IO_I[3]

virtex IO_N switchbox INT muxes HEX_V4[3]
Bits	Destination
HEX_V4[3]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V5[0]
Bits	Destination
HEX_V5[0]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V5[1]
Bits	Destination
HEX_V5[1]
	Source
OUT_IO_IQ[0]

virtex IO_N switchbox INT muxes HEX_V5[2]
Bits	Destination
HEX_V5[2]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V5[3]
Bits	Destination
HEX_V5[3]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_V6[0]
Bits	Destination
HEX_V6[0]
	Source
OUT_IO_I[1]

virtex IO_N switchbox INT muxes HEX_V6[1]
Bits	Destination
HEX_V6[1]
	Source
OUT_IO_I[3]

virtex IO_N switchbox INT muxes HEX_V6[2]
Bits	Destination
HEX_V6[2]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V6[3]
Bits	Destination
HEX_V6[3]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_S0[0]
Bits	Destination
HEX_S0[0]
	Source
OUT_IO_IQ[0]

virtex IO_N switchbox INT muxes HEX_S0[1]
Bits	Destination
HEX_S0[1]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_S0[2]
Bits	Destination
HEX_S0[2]
	Source
OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_S0[3]
Bits	Destination
HEX_S0[3]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_S1[0]
Bits	Destination
HEX_S1[0]
	Source
OUT_IO_IQ[0]

virtex IO_N switchbox INT muxes HEX_S1[1]
Bits	Destination
HEX_S1[1]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_S1[2]
Bits	Destination
HEX_S1[2]
	Source
OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_S1[3]
Bits	Destination
HEX_S1[3]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes HEX_S2[0]
Bits	Destination
HEX_S2[0]
	Source
HEX_N3[0]

virtex IO_N switchbox INT muxes HEX_S2[1]
Bits	Destination
HEX_S2[1]
	Source
HEX_N3[1]

virtex IO_N switchbox INT muxes HEX_S2[2]
Bits	Destination
HEX_S2[2]
	Source
HEX_N3[2]

virtex IO_N switchbox INT muxes HEX_S2[3]
Bits	Destination
HEX_S2[3]
	Source
HEX_N3[3]

virtex IO_N switchbox INT muxes HEX_S3[0]
Bits	Destination
HEX_S3[0]
	Source
HEX_N4[0]

virtex IO_N switchbox INT muxes HEX_S3[1]
Bits	Destination
HEX_S3[1]
	Source
HEX_N4[1]

virtex IO_N switchbox INT muxes HEX_S3[2]
Bits	Destination
HEX_S3[2]
	Source
HEX_N4[2]

virtex IO_N switchbox INT muxes HEX_S3[3]
Bits	Destination
HEX_S3[3]
	Source
HEX_N4[3]

virtex IO_N switchbox INT muxes HEX_S4[0]
Bits	Destination
HEX_S4[0]
	Source
HEX_N5[0]

virtex IO_N switchbox INT muxes HEX_S4[1]
Bits	Destination
HEX_S4[1]
	Source
HEX_N5[1]

virtex IO_N switchbox INT muxes HEX_S4[2]
Bits	Destination
HEX_S4[2]
	Source
HEX_N5[2]

virtex IO_N switchbox INT muxes HEX_S4[3]
Bits	Destination
HEX_S4[3]
	Source
HEX_N5[3]

virtex IO_N switchbox INT muxes HEX_S5[0]
Bits	Destination
HEX_S5[0]
	Source
HEX_N6[0]

virtex IO_N switchbox INT muxes HEX_S5[1]
Bits	Destination
HEX_S5[1]
	Source
HEX_N6[1]

virtex IO_N switchbox INT muxes HEX_S5[2]
Bits	Destination
HEX_S5[2]
	Source
HEX_N6[2]

virtex IO_N switchbox INT muxes HEX_S5[3]
Bits	Destination
HEX_S5[3]
	Source
HEX_N6[3]

virtex IO_N switchbox INT muxes LH[0]
Bits	Destination
LH[0]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes LH[6]
Bits	Destination
LH[6]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes LV[0]
Bits	Destination
LV[0]
	Source
OUT_IO_IQ[0]

virtex IO_N switchbox INT muxes LV[1]
Bits	Destination
LV[1]
	Source
OUT_IO_I[0]

virtex IO_N switchbox INT muxes LV[2]
Bits	Destination
LV[2]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes LV[3]
Bits	Destination
LV[3]
	Source
OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes LV[4]
Bits	Destination
LV[4]
	Source
OUT_IO_I[1]

virtex IO_N switchbox INT muxes LV[5]
Bits	Destination
LV[5]
	Source
OUT_IO_I[1]

virtex IO_N switchbox INT muxes LV[6]
Bits	Destination
LV[6]
	Source
OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes LV[7]
Bits	Destination
LV[7]
	Source
OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes LV[8]
Bits	Destination
LV[8]
	Source
OUT_IO_I[2]

virtex IO_N switchbox INT muxes LV[9]
Bits	Destination
LV[9]
	Source
OUT_IO_I[2]

virtex IO_N switchbox INT muxes LV[10]
Bits	Destination
LV[10]
	Source
OUT_IO_IQ[3]

virtex IO_N switchbox INT muxes LV[11]
Bits	Destination
LV[11]
	Source
OUT_IO_I[3]

virtex IO_N switchbox INT muxes IMUX_IO_CLK[0]
Bits	Destination
IMUX_IO_CLK[0]
	Source
HEX_V6_BUF[2]

virtex IO_N switchbox INT muxes IMUX_IO_CLK[1]
Bits	Destination
IMUX_IO_CLK[1]
	Source
HEX_V6_BUF[2]

virtex IO_N switchbox INT muxes IMUX_IO_CLK[2]
Bits	Destination
IMUX_IO_CLK[2]
	Source
HEX_V6_BUF[2]

virtex IO_N switchbox INT muxes IMUX_IO_CLK[3]
Bits	Destination
IMUX_IO_CLK[3]
	Source
HEX_V6_BUF[2]

virtex IO_N switchbox INT muxes IMUX_IO_SR[0]
Bits	Destination
IMUX_IO_SR[0]
	Source
HEX_V6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_SR[1]
Bits	Destination
IMUX_IO_SR[1]
	Source
HEX_V6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_SR[2]
Bits	Destination
IMUX_IO_SR[2]
	Source
HEX_V6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_SR[3]
Bits	Destination
IMUX_IO_SR[3]
	Source
HEX_V6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_ICE[0]
Bits	Destination
IMUX_IO_ICE[0]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_ICE[1]
Bits	Destination
IMUX_IO_ICE[1]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_ICE[2]
Bits	Destination
IMUX_IO_ICE[2]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_ICE[3]
Bits	Destination
IMUX_IO_ICE[3]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_OCE[0]
Bits	Destination
IMUX_IO_OCE[0]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_OCE[1]
Bits	Destination
IMUX_IO_OCE[1]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_OCE[2]
Bits	Destination
IMUX_IO_OCE[2]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_OCE[3]
Bits	Destination
IMUX_IO_OCE[3]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_TCE[0]
Bits	Destination
IMUX_IO_TCE[0]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_TCE[1]
Bits	Destination
IMUX_IO_TCE[1]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_TCE[2]
Bits	Destination
IMUX_IO_TCE[2]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_TCE[3]
Bits	Destination
IMUX_IO_TCE[3]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_O[0]
Bits	Destination
IMUX_IO_O[0]
	Source
HEX_V6_BUF[0]

virtex IO_N switchbox INT muxes IMUX_IO_O[1]
Bits	Destination
IMUX_IO_O[1]
	Source
HEX_V6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_O[2]
Bits	Destination
IMUX_IO_O[2]
	Source
HEX_V6_BUF[2]

virtex IO_N switchbox INT muxes IMUX_IO_O[3]
Bits	Destination
IMUX_IO_O[3]
	Source
HEX_V6_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_T[0]
Bits	Destination
IMUX_IO_T[0]
	Source
HEX_V6_BUF[0]

virtex IO_N switchbox INT muxes IMUX_IO_T[1]
Bits	Destination
IMUX_IO_T[1]
	Source
HEX_V6_BUF[0]

virtex IO_N switchbox INT muxes IMUX_IO_T[2]
Bits	Destination
IMUX_IO_T[2]
	Source
HEX_V6_BUF[0]

virtex IO_N switchbox INT muxes IMUX_IO_T[3]
Bits	Destination
IMUX_IO_T[3]
	Source
HEX_V6_BUF[0]

Bel IO[0]

virtex IO_N bel IO[0]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[0]
I	output	OUT_IO_I[0]
ICE	input	IMUX_IO_ICE[0]
IQ	output	OUT_IO_IQ[0]
O	input	IMUX_IO_O[0]
OCE	input	IMUX_IO_OCE[0]
SR	input	IMUX_IO_SR[0]
T	input	IMUX_IO_T[0]
TCE	input	IMUX_IO_TCE[0]

Bel IO[1]

virtex IO_N bel IO[1]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[1]
I	output	OUT_IO_I[1]
ICE	input	IMUX_IO_ICE[1]
IQ	output	OUT_IO_IQ[1]
O	input	IMUX_IO_O[1]
OCE	input	IMUX_IO_OCE[1]
SR	input	IMUX_IO_SR[1]
T	input	IMUX_IO_T[1]
TCE	input	IMUX_IO_TCE[1]

Bel IO[2]

virtex IO_N bel IO[2]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[2]
I	output	OUT_IO_I[2]
ICE	input	IMUX_IO_ICE[2]
IQ	output	OUT_IO_IQ[2]
O	input	IMUX_IO_O[2]
OCE	input	IMUX_IO_OCE[2]
SR	input	IMUX_IO_SR[2]
T	input	IMUX_IO_T[2]
TCE	input	IMUX_IO_TCE[2]

Bel IO[3]

virtex IO_N bel IO[3]
Pin	Direction	Wires
CLK	input	IMUX_IO_CLK[3]
I	output	OUT_IO_I[3]
ICE	input	IMUX_IO_ICE[3]
IQ	output	OUT_IO_IQ[3]
O	input	IMUX_IO_O[3]
OCE	input	IMUX_IO_OCE[3]
SR	input	IMUX_IO_SR[3]
T	input	IMUX_IO_T[3]
TCE	input	IMUX_IO_TCE[3]

Bel wires

virtex IO_N bel wires
Wire	Pins
IMUX_IO_CLK[0]	IO[0].CLK
IMUX_IO_CLK[1]	IO[1].CLK
IMUX_IO_CLK[2]	IO[2].CLK
IMUX_IO_CLK[3]	IO[3].CLK
IMUX_IO_SR[0]	IO[0].SR
IMUX_IO_SR[1]	IO[1].SR
IMUX_IO_SR[2]	IO[2].SR
IMUX_IO_SR[3]	IO[3].SR
IMUX_IO_ICE[0]	IO[0].ICE
IMUX_IO_ICE[1]	IO[1].ICE
IMUX_IO_ICE[2]	IO[2].ICE
IMUX_IO_ICE[3]	IO[3].ICE
IMUX_IO_OCE[0]	IO[0].OCE
IMUX_IO_OCE[1]	IO[1].OCE
IMUX_IO_OCE[2]	IO[2].OCE
IMUX_IO_OCE[3]	IO[3].OCE
IMUX_IO_TCE[0]	IO[0].TCE
IMUX_IO_TCE[1]	IO[1].TCE
IMUX_IO_TCE[2]	IO[2].TCE
IMUX_IO_TCE[3]	IO[3].TCE
IMUX_IO_O[0]	IO[0].O
IMUX_IO_O[1]	IO[1].O
IMUX_IO_O[2]	IO[2].O
IMUX_IO_O[3]	IO[3].O
IMUX_IO_T[0]	IO[0].T
IMUX_IO_T[1]	IO[1].T
IMUX_IO_T[2]	IO[2].T
IMUX_IO_T[3]	IO[3].T
OUT_IO_I[0]	IO[0].I
OUT_IO_I[1]	IO[1].I
OUT_IO_I[2]	IO[2].I
OUT_IO_I[3]	IO[3].I
OUT_IO_IQ[0]	IO[0].IQ
OUT_IO_IQ[1]	IO[1].IQ
OUT_IO_IQ[2]	IO[2].IQ
OUT_IO_IQ[3]	IO[3].IQ

Bitstream

virtex IO_N rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

### Bitstream

virtex IO_N rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IO[2]:READBACK_IFF	-	-	-	-	-	IO[2]:READBACK_OFF	IO[2]:IFF_DELAY_ENABLE	~IO[2]:SHORTEN_JTAG_CHAIN	-	IO[2]:READBACK_TFF	-	-	-	-	IO[1]:READBACK_TFF	-	~IO[1]:SHORTEN_JTAG_CHAIN	IO[1]:IFF_DELAY_ENABLE	IO[1]:READBACK_OFF	-	-	-	-	-	IO[1]:READBACK_IFF	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IO[2]:IFF_SR_SYNC	IO[2]:IFF_INIT	IO[2]:I_DELAY_ENABLE	IO[2]:IFF_LATCH	IO[2]:IFF_SR_ENABLE	IO[2]:OFF_SR_ENABLE	IO[2]:OFF_LATCH	IO[2]:OMUX[0]	~IO[2]:OFF_INIT	IO[2]:OFF_SR_SYNC	IO[2]:TFF_SR_SYNC	~IO[2]:TFF_INIT	IO[2]:TMUX[0]	IO[2]:TFF_LATCH	IO[2]:TFF_SR_ENABLE	IO[1]:TFF_SR_ENABLE	IO[1]:TFF_LATCH	IO[1]:TMUX[0]	~IO[1]:TFF_INIT	IO[1]:TFF_SR_SYNC	IO[1]:OFF_SR_SYNC	~IO[1]:OFF_INIT	IO[1]:OMUX[0]	IO[1]:OFF_LATCH	IO[1]:OFF_SR_ENABLE	IO[1]:IFF_SR_ENABLE	IO[1]:IFF_LATCH	IO[1]:I_DELAY_ENABLE	IO[1]:IFF_INIT	IO[1]:IFF_SR_SYNC
B15	INT:MUX.LH[6][0]	INT:MUX.LH[6][6]	INT:MUX.LH[6][1]	INT:DRIVE.LH[6]	INT:MUX.LH[0][6]	INT:MUX.LH[6][8]	INT:MUX.LH[0][5]	INT:MUX.LH[6][5]	INT:MUX.LH[0][2]	INT:MUX.LH[0][8]	INT:DRIVE.LH[0]	INT:MUX.LH[6][3]	INT:MUX.LH[6][2]	INT:MUX.LH[0][1]	INT:MUX.LH[6][4]	INT:MUX.LH[0][4]	INT:MUX.HEX_H6[4][4]	INT:MUX.HEX_H6[4][2]	INT:MUX.HEX_H0[5][2]	INT:DRIVE.HEX_H0[5]	INT:MUX.HEX_H0[5][3]	INT:MUX.HEX_H6[4][3]	INT:MUX.HEX_H0[5][4]	INT:MUX.HEX_H0[5][6]	INT:MUX.HEX_H6[4][6]	INT:MUX.HEX_H0[5][5]	INT:MUX.HEX_H6[4][1]	INT:MUX.HEX_H0[5][1]	INT:DRIVE.HEX_H6[4]	INT:MUX.HEX_H0[5][0]	INT:MUX.HEX_H6[4][0]	INT:MUX.HEX_H6[4][5]	INT:MUX.HEX_H6[5][5]	INT:MUX.HEX_H6[5][0]	INT:MUX.HEX_H0[4][0]	INT:MUX.HEX_H0[4][1]	INT:MUX.HEX_H6[5][6]	INT:DRIVE.HEX_H6[5]	INT:MUX.HEX_H6[5][1]	INT:MUX.HEX_H0[4][5]	INT:MUX.HEX_H0[4][4]	INT:MUX.HEX_H0[4][6]	INT:MUX.HEX_H6[5][3]	INT:MUX.HEX_H0[4][3]	INT:MUX.HEX_H0[4][2]	INT:DRIVE.HEX_H0[4]	INT:MUX.HEX_H6[5][2]	INT:MUX.HEX_H6[5][4]
B14	-	-	INT:MUX.IMUX_IO_O[3][1]	INT:MUX.IMUX_IO_O[3][4]	INT:MUX.IMUX_IO_O[2][2]	INT:MUX.IMUX_IO_O[2][3]	INT:MUX.IMUX_IO_O[2][1]	INT:MUX.IMUX_IO_O[2][4]	-	~INT:INV.IMUX_IO_O[2]	-	-	-	IO[2]:INV.IFF.CLK	IO[2]:INV.OFF.CLK	IO[2]:INV.TFF.CLK	INT:MUX.IMUX_IO_CLK[2][10]	INT:MUX.IMUX_IO_CLK[3][10]	INT:MUX.IMUX_IO_CLK[3][9]	INT:MUX.IMUX_IO_CLK[2][11]	INT:MUX.IMUX_IO_CLK[3][1]	INT:MUX.IMUX_IO_CLK[3][7]	INT:MUX.IMUX_IO_CLK[3][4]	INT:MUX.IMUX_IO_CLK[2][6]	INT:MUX.IMUX_IO_CLK[1][6]	INT:MUX.IMUX_IO_CLK[0][4]	INT:MUX.IMUX_IO_CLK[0][7]	INT:MUX.IMUX_IO_CLK[0][1]	INT:MUX.IMUX_IO_CLK[1][11]	INT:MUX.IMUX_IO_CLK[0][9]	INT:MUX.IMUX_IO_CLK[0][10]	INT:MUX.IMUX_IO_CLK[1][10]	IO[1]:INV.TFF.CLK	IO[1]:INV.OFF.CLK	IO[1]:INV.IFF.CLK	-	-	-	~INT:INV.IMUX_IO_O[1]	-	INT:MUX.IMUX_IO_O[1][1]	INT:MUX.IMUX_IO_O[1][4]	INT:MUX.IMUX_IO_O[1][7]	INT:MUX.IMUX_IO_O[1][8]	INT:MUX.IMUX_IO_O[0][1]	INT:MUX.IMUX_IO_O[0][4]	-	-
B13	INT:MUX.IMUX_IO_O[3][6]	INT:MUX.IMUX_IO_O[3][5]	INT:MUX.IMUX_IO_O[3][0]	INT:MUX.IMUX_IO_O[3][8]	INT:MUX.IMUX_IO_O[3][7]	INT:MUX.IMUX_IO_O[3][3]	INT:MUX.IMUX_IO_O[3][2]	INT:MUX.IMUX_IO_O[2][0]	INT:MUX.IMUX_IO_O[2][8]	INT:MUX.IMUX_IO_O[2][7]	INT:MUX.IMUX_IO_CLK[2][0]	INT:MUX.IMUX_IO_CLK[3][8]	INT:MUX.IMUX_IO_CLK[3][0]	INT:MUX.IMUX_IO_CLK[2][4]	INT:MUX.IMUX_IO_CLK[2][8]	INT:MUX.IMUX_IO_CLK[2][2]	INT:MUX.IMUX_IO_CLK[2][5]	INT:MUX.IMUX_IO_CLK[3][6]	INT:MUX.IMUX_IO_CLK[2][1]	INT:MUX.IMUX_IO_CLK[2][9]	INT:MUX.IMUX_IO_CLK[3][2]	INT:MUX.IMUX_IO_CLK[2][3]	INT:MUX.IMUX_IO_CLK[3][3]	INT:MUX.IMUX_IO_CLK[3][5]	INT:MUX.IMUX_IO_CLK[0][5]	INT:MUX.IMUX_IO_CLK[0][3]	INT:MUX.IMUX_IO_CLK[1][3]	INT:MUX.IMUX_IO_CLK[0][2]	INT:MUX.IMUX_IO_CLK[1][9]	INT:MUX.IMUX_IO_CLK[1][1]	INT:MUX.IMUX_IO_CLK[0][6]	INT:MUX.IMUX_IO_CLK[1][5]	INT:MUX.IMUX_IO_CLK[1][2]	INT:MUX.IMUX_IO_CLK[1][8]	INT:MUX.IMUX_IO_CLK[1][4]	INT:MUX.IMUX_IO_CLK[0][0]	INT:MUX.IMUX_IO_CLK[0][8]	INT:MUX.IMUX_IO_CLK[1][0]	INT:MUX.IMUX_IO_O[1][2]	INT:MUX.IMUX_IO_O[1][3]	INT:MUX.IMUX_IO_O[1][0]	INT:MUX.IMUX_IO_O[0][8]	INT:MUX.IMUX_IO_O[0][7]	INT:MUX.IMUX_IO_O[0][2]	INT:MUX.IMUX_IO_O[0][3]	INT:MUX.IMUX_IO_O[0][0]	INT:MUX.IMUX_IO_O[0][5]	INT:MUX.IMUX_IO_O[0][6]
B12	-	INT:MUX.LH[0][0]	INT:DRIVE.LV[11]	-	INT:MUX.IMUX_IO_O[2][6]	INT:DRIVE.LV[10]	INT:MUX.IMUX_IO_O[2][5]	-	INT:MUX.LV[9][0]	INT:MUX.LH[6][7]	INT:DRIVE.LV[9]	-	INT:MUX.LH[0][7]	INT:DRIVE.LV[8]	INT:MUX.LH[0][3]	INT:MUX.LV[8][0]	INT:MUX.LV[7][0]	INT:MUX.IMUX_IO_CLK[3][11]	INT:DRIVE.LV[7]	-	-	INT:DRIVE.LV[6]	INT:MUX.IMUX_IO_CLK[2][7]	INT:MUX.LV[6][0]	-	INT:MUX.IMUX_IO_CLK[1][7]	INT:DRIVE.LV[0]	-	-	INT:DRIVE.LV[1]	INT:MUX.IMUX_IO_CLK[0][11]	-	INT:MUX.LV[2][0]	-	INT:DRIVE.LV[2]	-	-	INT:DRIVE.LV[3]	-	INT:MUX.LV[3][0]	INT:MUX.LV[4][0]	INT:MUX.IMUX_IO_O[1][5]	INT:DRIVE.LV[4]	INT:MUX.IMUX_IO_O[1][6]	-	INT:DRIVE.LV[5]	-	INT:MUX.LV[5][0]
B11	INT:MUX.IMUX_IO_ICE[2][3]	INT:MUX.IMUX_IO_ICE[2][4]	INT:MUX.IMUX_IO_ICE[2][5]	INT:MUX.IMUX_IO_ICE[3][3]	INT:MUX.IMUX_IO_ICE[3][2]	INT:MUX.IMUX_IO_ICE[0][3]	INT:MUX.IMUX_IO_ICE[0][2]	INT:MUX.IMUX_IO_ICE[1][5]	INT:MUX.IMUX_IO_ICE[1][4]	INT:MUX.IMUX_IO_ICE[1][3]	INT:MUX.IMUX_IO_OCE[2][3]	INT:MUX.IMUX_IO_OCE[2][4]	INT:MUX.IMUX_IO_OCE[2][5]	INT:MUX.IMUX_IO_OCE[3][3]	INT:MUX.IMUX_IO_OCE[0][3]	INT:MUX.IMUX_IO_OCE[0][2]	INT:MUX.IMUX_IO_TCE[3][2]	INT:MUX.IMUX_IO_OCE[1][5]	INT:MUX.IMUX_IO_OCE[1][4]	INT:MUX.IMUX_IO_OCE[1][3]	INT:MUX.IMUX_IO_TCE[2][3]	INT:MUX.IMUX_IO_TCE[2][4]	INT:MUX.IMUX_IO_TCE[2][5]	INT:MUX.IMUX_IO_TCE[3][3]	INT:MUX.IMUX_IO_TCE[1][3]	INT:MUX.IMUX_IO_TCE[0][5]	INT:MUX.IMUX_IO_TCE[0][4]	INT:MUX.IMUX_IO_TCE[0][3]	INT:MUX.IMUX_IO_SR[1][0]	INT:MUX.IMUX_IO_SR[1][4]	INT:MUX.IMUX_IO_SR[1][5]	INT:MUX.IMUX_IO_TCE[1][2]	INT:MUX.IMUX_IO_SR[0][1]	INT:MUX.IMUX_IO_SR[0][0]	INT:MUX.IMUX_IO_SR[3][0]	INT:MUX.IMUX_IO_SR[2][5]	INT:MUX.IMUX_IO_SR[2][4]	INT:MUX.IMUX_IO_SR[2][0]	INT:MUX.IMUX_IO_T[1][0]	INT:MUX.IMUX_IO_T[1][4]	INT:MUX.IMUX_IO_T[1][5]	INT:MUX.IMUX_IO_T[0][1]	INT:MUX.IMUX_IO_T[0][0]	INT:MUX.IMUX_IO_T[3][1]	INT:MUX.IMUX_IO_T[3][0]	INT:MUX.IMUX_IO_T[2][5]	INT:MUX.IMUX_IO_T[2][4]	INT:MUX.IMUX_IO_T[2][0]
B10	INT:MUX.IMUX_IO_ICE[2][0]	INT:MUX.IMUX_IO_ICE[3][5]	INT:MUX.IMUX_IO_ICE[3][4]	INT:MUX.IMUX_IO_ICE[3][0]	~INT:INV.IMUX_IO_ICE[2]	~INT:INV.IMUX_IO_ICE[1]	INT:MUX.IMUX_IO_ICE[0][0]	INT:MUX.IMUX_IO_ICE[0][4]	INT:MUX.IMUX_IO_ICE[0][5]	INT:MUX.IMUX_IO_ICE[1][0]	INT:MUX.IMUX_IO_OCE[2][0]	INT:MUX.IMUX_IO_OCE[3][5]	INT:MUX.IMUX_IO_OCE[3][4]	INT:MUX.IMUX_IO_OCE[3][0]	~INT:INV.IMUX_IO_OCE[1]	-	INT:MUX.IMUX_IO_OCE[0][0]	INT:MUX.IMUX_IO_OCE[0][4]	INT:MUX.IMUX_IO_OCE[0][5]	INT:MUX.IMUX_IO_TCE[2][0]	INT:MUX.IMUX_IO_TCE[3][5]	INT:MUX.IMUX_IO_TCE[3][4]	-	INT:MUX.IMUX_IO_TCE[3][0]	INT:MUX.IMUX_IO_TCE[1][0]	~INT:INV.IMUX_IO_TCE[1]	INT:MUX.IMUX_IO_TCE[1][4]	INT:MUX.IMUX_IO_TCE[1][5]	INT:MUX.IMUX_IO_TCE[0][0]	INT:MUX.IMUX_IO_SR[0][5]	INT:MUX.IMUX_IO_SR[0][4]	INT:MUX.IMUX_IO_SR[0][3]	-	INT:INV.IMUX_IO_SR[1]	INT:MUX.IMUX_IO_SR[3][3]	INT:MUX.IMUX_IO_SR[3][4]	INT:MUX.IMUX_IO_SR[3][5]	INT:MUX.IMUX_IO_SR[2][3]	INT:MUX.IMUX_IO_T[1][3]	INT:MUX.IMUX_IO_T[0][5]	INT:MUX.IMUX_IO_T[0][4]	INT:MUX.IMUX_IO_T[0][3]	~INT:INV.IMUX_IO_T[1]	~INT:INV.IMUX_IO_T[2]	INT:MUX.IMUX_IO_T[3][3]	INT:MUX.IMUX_IO_T[3][4]	INT:MUX.IMUX_IO_T[3][5]	INT:MUX.IMUX_IO_T[2][3]
B9	INT:MUX.IMUX_IO_ICE[2][2]	INT:MUX.IMUX_IO_ICE[2][1]	INT:MUX.IMUX_IO_ICE[3][1]	-	INT:MUX.IMUX_IO_ICE[1][2]	INT:MUX.IMUX_IO_ICE[1][1]	-	INT:MUX.IMUX_IO_ICE[0][1]	INT:MUX.IMUX_IO_OCE[3][2]	INT:MUX.IMUX_IO_OCE[2][1]	-	INT:MUX.IMUX_IO_OCE[2][2]	INT:MUX.IMUX_IO_OCE[3][1]	~INT:INV.IMUX_IO_OCE[2]	INT:MUX.IMUX_IO_OCE[0][1]	INT:MUX.IMUX_IO_OCE[1][1]	INT:MUX.IMUX_IO_OCE[1][2]	-	-	INT:MUX.IMUX_IO_OCE[1][0]	INT:MUX.IMUX_IO_TCE[3][1]	INT:MUX.IMUX_IO_TCE[2][1]	INT:MUX.IMUX_IO_TCE[2][2]	~INT:INV.IMUX_IO_TCE[2]	-	INT:MUX.IMUX_IO_TCE[0][2]	INT:MUX.IMUX_IO_TCE[0][1]	INT:MUX.IMUX_IO_TCE[1][1]	INT:MUX.IMUX_IO_SR[1][3]	-	-	INT:MUX.IMUX_IO_SR[1][1]	INT:MUX.IMUX_IO_SR[1][2]	INT:MUX.IMUX_IO_SR[0][2]	INT:INV.IMUX_IO_SR[2]	INT:MUX.IMUX_IO_SR[3][2]	INT:MUX.IMUX_IO_SR[2][1]	-	INT:MUX.IMUX_IO_SR[2][2]	INT:MUX.IMUX_IO_SR[3][1]	INT:MUX.IMUX_IO_T[0][2]	-	INT:MUX.IMUX_IO_T[1][2]	INT:MUX.IMUX_IO_T[1][1]	-	INT:MUX.IMUX_IO_T[3][2]	INT:MUX.IMUX_IO_T[2][2]	INT:MUX.IMUX_IO_T[2][1]
B8	INT:PASS.SINGLE_S[23].HEX_H0[3]	-	INT:PASS.SINGLE_S[22].HEX_H3[3]	INT:PASS.SINGLE_S[22].OUT_IO_IQ[1]	INT:PASS.SINGLE_S[21].OUT_IO_IQ[2]	INT:PASS.SINGLE_S[21].HEX_H6[3]	-	INT:PASS.SINGLE_S[20].HEX_H0[3]	-	INT:PASS.SINGLE_S[19].HEX_H3[3]	INT:PASS.SINGLE_S[18].OUT_IO_I[1]	INT:PASS.SINGLE_S[18].HEX_H6[3]	INT:PASS.SINGLE_S[17].HEX_H0[2]	INT:PASS.SINGLE_S[17].OUT_IO_I[2]	INT:PASS.SINGLE_S[16].HEX_H3[2]	-	-	INT:PASS.SINGLE_S[15].HEX_H6[2]	INT:PASS.SINGLE_S[14].OUT_IO_IQ[1]	INT:PASS.SINGLE_S[14].HEX_H0[2]	INT:PASS.SINGLE_S[13].OUT_IO_IQ[2]	INT:PASS.SINGLE_S[13].HEX_H3[2]	-	INT:PASS.SINGLE_S[12].HEX_H6[2]	INT:PASS.SINGLE_S[11].HEX_H0[1]	-	INT:PASS.SINGLE_S[10].HEX_H3[1]	INT:PASS.SINGLE_S[10].OUT_IO_I[1]	INT:PASS.SINGLE_S[9].OUT_IO_I[2]	INT:PASS.SINGLE_S[9].HEX_H6[1]	-	INT:PASS.SINGLE_S[8].HEX_H0[1]	-	INT:PASS.SINGLE_S[7].HEX_H3[1]	INT:PASS.SINGLE_S[6].OUT_IO_IQ[1]	INT:PASS.SINGLE_S[6].HEX_H6[1]	INT:PASS.SINGLE_S[5].HEX_H0[0]	INT:PASS.SINGLE_S[5].OUT_IO_IQ[2]	INT:PASS.SINGLE_S[4].HEX_H3[0]	-	-	INT:PASS.SINGLE_S[3].HEX_H6[0]	INT:PASS.SINGLE_S[2].OUT_IO_I[1]	INT:PASS.SINGLE_S[2].HEX_H0[0]	INT:PASS.SINGLE_S[1].OUT_IO_I[2]	INT:PASS.SINGLE_S[1].HEX_H3[0]	-	INT:PASS.SINGLE_S[0].HEX_H6[0]
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT:DRIVE.HEX_H0[3]	INT:MUX.HEX_H6[3][5]	INT:MUX.HEX_H6[3][3]	INT:MUX.HEX_H0[3][2]	INT:MUX.HEX_H0[3][5]	INT:MUX.HEX_H0[3][6]	INT:MUX.HEX_H0[3][4]	INT:MUX.HEX_H0[3][0]	INT:MUX.HEX_H0[3][3]	INT:MUX.HEX_H6[3][1]	INT:MUX.HEX_H6[3][6]	INT:DRIVE.HEX_H6[3]	INT:DRIVE.HEX_H0[2]	INT:MUX.HEX_H6[2][5]	INT:MUX.HEX_H6[2][3]	INT:MUX.HEX_H0[2][2]	INT:MUX.HEX_H0[2][5]	INT:MUX.HEX_H0[2][6]	INT:MUX.HEX_H0[2][4]	INT:MUX.HEX_H0[2][0]	INT:MUX.HEX_H0[2][3]	INT:MUX.HEX_H6[2][1]	INT:MUX.HEX_H6[2][6]	INT:DRIVE.HEX_H6[2]	INT:DRIVE.HEX_H0[1]	INT:MUX.HEX_H6[1][5]	INT:MUX.HEX_H6[1][3]	INT:MUX.HEX_H0[1][2]	INT:MUX.HEX_H0[1][5]	INT:MUX.HEX_H0[1][6]	INT:MUX.HEX_H0[1][4]	INT:MUX.HEX_H0[1][0]	INT:MUX.HEX_H0[1][3]	INT:MUX.HEX_H6[1][1]	INT:MUX.HEX_H6[1][6]	INT:DRIVE.HEX_H6[1]	INT:DRIVE.HEX_H0[0]	INT:MUX.HEX_H6[0][5]	INT:MUX.HEX_H6[0][3]	INT:MUX.HEX_H0[0][2]	INT:MUX.HEX_H0[0][5]	INT:MUX.HEX_H0[0][6]	INT:MUX.HEX_H0[0][4]	INT:MUX.HEX_H0[0][0]	INT:MUX.HEX_H0[0][3]	INT:MUX.HEX_H6[0][1]	INT:MUX.HEX_H6[0][6]	INT:DRIVE.HEX_H6[0]
B5	INT:MUX.HEX_H6[3][0]	INT:MUX.HEX_H0[3][1]	-	-	-	-	-	-	-	-	INT:MUX.HEX_H6[3][4]	INT:MUX.HEX_H6[3][2]	INT:MUX.HEX_H6[2][0]	INT:MUX.HEX_H0[2][1]	-	-	-	-	-	-	-	-	INT:MUX.HEX_H6[2][4]	INT:MUX.HEX_H6[2][2]	INT:MUX.HEX_H6[1][0]	INT:MUX.HEX_H0[1][1]	-	-	-	-	-	-	-	-	INT:MUX.HEX_H6[1][4]	INT:MUX.HEX_H6[1][2]	INT:MUX.HEX_H6[0][0]	INT:MUX.HEX_H0[0][1]	-	-	-	-	-	-	-	-	INT:MUX.HEX_H6[0][4]	INT:MUX.HEX_H6[0][2]
B4	INT:DRIVE.HEX_V6[3]	-	INT:MUX.HEX_V6[3][1]	INT:DRIVE.HEX_V5[3]	INT:DRIVE.HEX_V4[3]	-	-	INT:DRIVE.HEX_V3[3]	INT:DRIVE.HEX_V2[3]	-	-	INT:DRIVE.HEX_V1[3]	INT:DRIVE.HEX_V1[2]	-	-	INT:DRIVE.HEX_V2[2]	INT:DRIVE.HEX_V3[2]	-	-	INT:DRIVE.HEX_V4[2]	INT:DRIVE.HEX_V5[2]	INT:MUX.HEX_V6[2][3]	INT:MUX.HEX_V5[2][1]	INT:DRIVE.HEX_V6[2]	INT:DRIVE.HEX_V6[1]	-	INT:MUX.HEX_V6[1][3]	INT:DRIVE.HEX_V5[1]	INT:DRIVE.HEX_V4[1]	-	-	INT:DRIVE.HEX_V3[1]	INT:DRIVE.HEX_V2[1]	-	-	INT:DRIVE.HEX_V1[1]	INT:DRIVE.HEX_V1[0]	-	-	INT:DRIVE.HEX_V2[0]	INT:DRIVE.HEX_V3[0]	-	-	INT:DRIVE.HEX_V4[0]	INT:DRIVE.HEX_V5[0]	INT:MUX.HEX_V6[0][2]	INT:MUX.HEX_V5[0][1]	INT:DRIVE.HEX_V6[0]
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	INT:MUX.HEX_V6[3][0]	-	INT:MUX.HEX_V6[3][4]	INT:MUX.HEX_V5[3][0]	INT:MUX.HEX_V4[3][1]	INT:MUX.HEX_V3[3][1]	-	INT:MUX.HEX_V3[3][0]	INT:MUX.HEX_V2[3][2]	INT:MUX.HEX_V1[3][2]	-	INT:MUX.HEX_V1[3][0]	INT:MUX.HEX_V1[2][0]	INT:MUX.HEX_V1[2][1]	-	-	INT:MUX.HEX_V3[2][0]	INT:MUX.HEX_V3[2][1]	-	-	INT:MUX.HEX_V5[2][0]	-	INT:MUX.HEX_V6[2][4]	INT:MUX.HEX_V6[2][0]	INT:MUX.HEX_V6[1][0]	-	INT:MUX.HEX_V6[1][4]	INT:MUX.HEX_V5[1][0]	INT:MUX.HEX_V4[1][1]	INT:MUX.HEX_V3[1][1]	-	INT:MUX.HEX_V3[1][0]	INT:MUX.HEX_V2[1][2]	INT:MUX.HEX_V1[1][2]	-	INT:MUX.HEX_V1[1][0]	INT:MUX.HEX_V1[0][0]	INT:MUX.HEX_V1[0][1]	-	-	INT:MUX.HEX_V3[0][0]	INT:MUX.HEX_V3[0][1]	-	-	INT:MUX.HEX_V5[0][0]	-	INT:MUX.HEX_V6[0][4]	INT:MUX.HEX_V6[0][0]
B1	INT:MUX.HEX_S1[3][0]	INT:MUX.HEX_S1[3][1]	INT:MUX.HEX_S0[3][1]	INT:MUX.HEX_S0[3][2]	INT:MUX.HEX_S1[3][2]	INT:MUX.HEX_S1[3][3]	INT:MUX.HEX_S0[3][3]	-	-	-	-	INT:MUX.HEX_S0[3][0]	INT:MUX.HEX_S1[1][0]	INT:MUX.HEX_S1[1][2]	INT:MUX.HEX_S0[1][2]	INT:MUX.HEX_S0[1][3]	INT:MUX.HEX_S1[1][3]	INT:MUX.HEX_S1[1][1]	INT:MUX.HEX_S0[1][1]	INT:MUX.HEX_S0[1][5]	INT:MUX.HEX_S1[1][5]	INT:MUX.HEX_S1[1][4]	INT:MUX.HEX_S0[1][4]	INT:MUX.HEX_S0[1][0]	INT:MUX.HEX_S1[2][0]	INT:MUX.HEX_S1[2][3]	INT:MUX.HEX_S0[2][3]	INT:MUX.HEX_S0[2][1]	INT:MUX.HEX_S1[2][1]	INT:MUX.HEX_S1[2][2]	INT:MUX.HEX_S0[2][2]	INT:MUX.HEX_S0[2][5]	INT:MUX.HEX_S1[2][5]	INT:MUX.HEX_S1[2][4]	INT:MUX.HEX_S0[2][4]	INT:MUX.HEX_S0[2][0]	INT:MUX.HEX_S1[0][0]	INT:MUX.HEX_S1[0][1]	INT:MUX.HEX_S0[0][1]	INT:MUX.HEX_S0[0][2]	INT:MUX.HEX_S1[0][2]	INT:MUX.HEX_S1[0][3]	INT:MUX.HEX_S0[0][3]	-	-	-	-	INT:MUX.HEX_S0[0][0]
B0	INT:MUX.HEX_V6[3][3]	INT:MUX.HEX_V6[3][2]	INT:MUX.HEX_V5[3][2]	INT:MUX.HEX_V5[3][1]	INT:MUX.HEX_V4[3][0]	-	-	-	INT:MUX.HEX_V2[3][0]	INT:MUX.HEX_V1[3][1]	INT:MUX.HEX_V2[3][1]	-	INT:MUX.HEX_V2[2][1]	-	-	INT:MUX.HEX_V2[2][0]	INT:MUX.HEX_V4[2][1]	INT:MUX.HEX_V4[2][2]	INT:MUX.HEX_V3[2][2]	INT:MUX.HEX_V4[2][0]	-	-	INT:MUX.HEX_V6[2][1]	INT:MUX.HEX_V6[2][2]	INT:MUX.HEX_V6[1][2]	INT:MUX.HEX_V6[1][1]	INT:MUX.HEX_V5[1][1]	-	INT:MUX.HEX_V4[1][0]	-	-	-	INT:MUX.HEX_V2[1][0]	INT:MUX.HEX_V1[1][1]	INT:MUX.HEX_V2[1][1]	-	INT:MUX.HEX_V2[0][1]	-	-	INT:MUX.HEX_V2[0][0]	INT:MUX.HEX_V4[0][1]	INT:MUX.HEX_V4[0][2]	INT:MUX.HEX_V3[0][2]	INT:MUX.HEX_V4[0][0]	INT:MUX.HEX_V5[0][2]	-	INT:MUX.HEX_V6[0][3]	INT:MUX.HEX_V6[0][1]

INT:DRIVE.HEX_H0[0]	0.F36.B6
INT:DRIVE.HEX_H0[1]	0.F24.B6
INT:DRIVE.HEX_H0[2]	0.F12.B6
INT:DRIVE.HEX_H0[3]	0.F0.B6
INT:DRIVE.HEX_H0[4]	0.F45.B15
INT:DRIVE.HEX_H0[5]	0.F19.B15
INT:DRIVE.HEX_H6[0]	0.F47.B6
INT:DRIVE.HEX_H6[1]	0.F35.B6
INT:DRIVE.HEX_H6[2]	0.F23.B6
INT:DRIVE.HEX_H6[3]	0.F11.B6
INT:DRIVE.HEX_H6[4]	0.F28.B15
INT:DRIVE.HEX_H6[5]	0.F37.B15
INT:DRIVE.HEX_V1[0]	0.F36.B4
INT:DRIVE.HEX_V1[1]	0.F35.B4
INT:DRIVE.HEX_V1[2]	0.F12.B4
INT:DRIVE.HEX_V1[3]	0.F11.B4
INT:DRIVE.HEX_V2[0]	0.F39.B4
INT:DRIVE.HEX_V2[1]	0.F32.B4
INT:DRIVE.HEX_V2[2]	0.F15.B4
INT:DRIVE.HEX_V2[3]	0.F8.B4
INT:DRIVE.HEX_V3[0]	0.F40.B4
INT:DRIVE.HEX_V3[1]	0.F31.B4
INT:DRIVE.HEX_V3[2]	0.F16.B4
INT:DRIVE.HEX_V3[3]	0.F7.B4
INT:DRIVE.HEX_V4[0]	0.F43.B4
INT:DRIVE.HEX_V4[1]	0.F28.B4
INT:DRIVE.HEX_V4[2]	0.F19.B4
INT:DRIVE.HEX_V4[3]	0.F4.B4
INT:DRIVE.HEX_V5[0]	0.F44.B4
INT:DRIVE.HEX_V5[1]	0.F27.B4
INT:DRIVE.HEX_V5[2]	0.F20.B4
INT:DRIVE.HEX_V5[3]	0.F3.B4
INT:DRIVE.HEX_V6[0]	0.F47.B4
INT:DRIVE.HEX_V6[1]	0.F24.B4
INT:DRIVE.HEX_V6[2]	0.F23.B4
INT:DRIVE.HEX_V6[3]	0.F0.B4
INT:DRIVE.LH[0]	0.F10.B15
INT:DRIVE.LH[6]	0.F3.B15
INT:DRIVE.LV[0]	0.F26.B12
INT:DRIVE.LV[10]	0.F5.B12
INT:DRIVE.LV[11]	0.F2.B12
INT:DRIVE.LV[1]	0.F29.B12
INT:DRIVE.LV[2]	0.F34.B12
INT:DRIVE.LV[3]	0.F37.B12
INT:DRIVE.LV[4]	0.F42.B12
INT:DRIVE.LV[5]	0.F45.B12
INT:DRIVE.LV[6]	0.F21.B12
INT:DRIVE.LV[7]	0.F18.B12
INT:DRIVE.LV[8]	0.F13.B12
INT:DRIVE.LV[9]	0.F10.B12
INT:INV.IMUX_IO_SR[1]	0.F33.B10
INT:INV.IMUX_IO_SR[2]	0.F34.B9
INT:PASS.SINGLE_S[0].HEX_H6[0]	0.F47.B8
INT:PASS.SINGLE_S[10].HEX_H3[1]	0.F26.B8
INT:PASS.SINGLE_S[10].OUT_IO_I[1]	0.F27.B8
INT:PASS.SINGLE_S[11].HEX_H0[1]	0.F24.B8
INT:PASS.SINGLE_S[12].HEX_H6[2]	0.F23.B8
INT:PASS.SINGLE_S[13].HEX_H3[2]	0.F21.B8
INT:PASS.SINGLE_S[13].OUT_IO_IQ[2]	0.F20.B8
INT:PASS.SINGLE_S[14].HEX_H0[2]	0.F19.B8
INT:PASS.SINGLE_S[14].OUT_IO_IQ[1]	0.F18.B8
INT:PASS.SINGLE_S[15].HEX_H6[2]	0.F17.B8
INT:PASS.SINGLE_S[16].HEX_H3[2]	0.F14.B8
INT:PASS.SINGLE_S[17].HEX_H0[2]	0.F12.B8
INT:PASS.SINGLE_S[17].OUT_IO_I[2]	0.F13.B8
INT:PASS.SINGLE_S[18].HEX_H6[3]	0.F11.B8
INT:PASS.SINGLE_S[18].OUT_IO_I[1]	0.F10.B8
INT:PASS.SINGLE_S[19].HEX_H3[3]	0.F9.B8
INT:PASS.SINGLE_S[1].HEX_H3[0]	0.F45.B8
INT:PASS.SINGLE_S[1].OUT_IO_I[2]	0.F44.B8
INT:PASS.SINGLE_S[20].HEX_H0[3]	0.F7.B8
INT:PASS.SINGLE_S[21].HEX_H6[3]	0.F5.B8
INT:PASS.SINGLE_S[21].OUT_IO_IQ[2]	0.F4.B8
INT:PASS.SINGLE_S[22].HEX_H3[3]	0.F2.B8
INT:PASS.SINGLE_S[22].OUT_IO_IQ[1]	0.F3.B8
INT:PASS.SINGLE_S[23].HEX_H0[3]	0.F0.B8
INT:PASS.SINGLE_S[2].HEX_H0[0]	0.F43.B8
INT:PASS.SINGLE_S[2].OUT_IO_I[1]	0.F42.B8
INT:PASS.SINGLE_S[3].HEX_H6[0]	0.F41.B8
INT:PASS.SINGLE_S[4].HEX_H3[0]	0.F38.B8
INT:PASS.SINGLE_S[5].HEX_H0[0]	0.F36.B8
INT:PASS.SINGLE_S[5].OUT_IO_IQ[2]	0.F37.B8
INT:PASS.SINGLE_S[6].HEX_H6[1]	0.F35.B8
INT:PASS.SINGLE_S[6].OUT_IO_IQ[1]	0.F34.B8
INT:PASS.SINGLE_S[7].HEX_H3[1]	0.F33.B8
INT:PASS.SINGLE_S[8].HEX_H0[1]	0.F31.B8
INT:PASS.SINGLE_S[9].HEX_H6[1]	0.F29.B8
INT:PASS.SINGLE_S[9].OUT_IO_I[2]	0.F28.B8
IO[1]:IFF_DELAY_ENABLE	0.F38.B17
IO[1]:IFF_INIT	0.F46.B16
IO[1]:IFF_LATCH	0.F44.B16
IO[1]:IFF_SR_ENABLE	0.F43.B16
IO[1]:IFF_SR_SYNC	0.F47.B16
IO[1]:INV.IFF.CLK	0.F34.B14
IO[1]:INV.OFF.CLK	0.F33.B14
IO[1]:INV.TFF.CLK	0.F32.B14
IO[1]:I_DELAY_ENABLE	0.F45.B16
IO[1]:OFF_LATCH	0.F41.B16
IO[1]:OFF_SR_ENABLE	0.F42.B16
IO[1]:OFF_SR_SYNC	0.F38.B16
IO[1]:READBACK_IFF	0.F45.B17
IO[1]:READBACK_OFF	0.F39.B17
IO[1]:READBACK_TFF	0.F35.B17
IO[1]:TFF_LATCH	0.F34.B16
IO[1]:TFF_SR_ENABLE	0.F33.B16
IO[1]:TFF_SR_SYNC	0.F37.B16
IO[2]:IFF_DELAY_ENABLE	0.F27.B17
IO[2]:IFF_INIT	0.F19.B16
IO[2]:IFF_LATCH	0.F21.B16
IO[2]:IFF_SR_ENABLE	0.F22.B16
IO[2]:IFF_SR_SYNC	0.F18.B16
IO[2]:INV.IFF.CLK	0.F13.B14
IO[2]:INV.OFF.CLK	0.F14.B14
IO[2]:INV.TFF.CLK	0.F15.B14
IO[2]:I_DELAY_ENABLE	0.F20.B16
IO[2]:OFF_LATCH	0.F24.B16
IO[2]:OFF_SR_ENABLE	0.F23.B16
IO[2]:OFF_SR_SYNC	0.F27.B16
IO[2]:READBACK_IFF	0.F20.B17
IO[2]:READBACK_OFF	0.F26.B17
IO[2]:READBACK_TFF	0.F30.B17
IO[2]:TFF_LATCH	0.F31.B16
IO[2]:TFF_SR_ENABLE	0.F32.B16
IO[2]:TFF_SR_SYNC	0.F28.B16
non-inverted	[0]

INT:INV.IMUX_IO_ICE[1]	0.F5.B10
INT:INV.IMUX_IO_ICE[2]	0.F4.B10
INT:INV.IMUX_IO_OCE[1]	0.F14.B10
INT:INV.IMUX_IO_OCE[2]	0.F13.B9
INT:INV.IMUX_IO_O[1]	0.F38.B14
INT:INV.IMUX_IO_O[2]	0.F9.B14
INT:INV.IMUX_IO_TCE[1]	0.F25.B10
INT:INV.IMUX_IO_TCE[2]	0.F23.B9
INT:INV.IMUX_IO_T[1]	0.F42.B10
INT:INV.IMUX_IO_T[2]	0.F43.B10
IO[1]:OFF_INIT	0.F39.B16
IO[1]:SHORTEN_JTAG_CHAIN	0.F37.B17
IO[1]:TFF_INIT	0.F36.B16
IO[2]:OFF_INIT	0.F26.B16
IO[2]:SHORTEN_JTAG_CHAIN	0.F28.B17
IO[2]:TFF_INIT	0.F29.B16
inverted	~[0]

INT:MUX.HEX_H0[0]	0.F41.B6	0.F40.B6	0.F42.B6	0.F44.B6	0.F39.B6	0.F37.B5	0.F43.B6
HEX_H6[0]	0	0	0	0	0	0	1
HEX_V3[2]	0	0	0	0	0	1	0
HEX_V6[3]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[2]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[2]	1	0	1	0	1	0	0

INT:MUX.HEX_H0[1]	0.F29.B6	0.F28.B6	0.F30.B6	0.F32.B6	0.F27.B6	0.F25.B5	0.F31.B6
HEX_H6[1]	0	0	0	0	0	0	1
HEX_V3[3]	0	0	0	0	0	1	0
HEX_V6[0]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[2]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[2]	1	0	1	0	1	0	0

INT:MUX.HEX_H0[2]	0.F17.B6	0.F16.B6	0.F18.B6	0.F20.B6	0.F15.B6	0.F13.B5	0.F19.B6
HEX_H6[2]	0	0	0	0	0	0	1
HEX_V3[0]	0	0	0	0	0	1	0
HEX_V6[1]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[2]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[2]	1	0	1	0	1	0	0

INT:MUX.HEX_H0[3]	0.F5.B6	0.F4.B6	0.F6.B6	0.F8.B6	0.F3.B6	0.F1.B5	0.F7.B6
HEX_H6[3]	0	0	0	0	0	0	1
HEX_V3[1]	0	0	0	0	0	1	0
HEX_V6[2]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[2]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[2]	1	0	1	0	1	0	0

INT:MUX.HEX_H0[4]	0.F41.B15	0.F39.B15	0.F40.B15	0.F43.B15	0.F44.B15	0.F35.B15	0.F34.B15
SINGLE_S_BUF[0]	0	0	0	0	0	0	1
SINGLE_S_BUF[7]	0	0	0	0	0	1	0
HEX_H6[4]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	1	0	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	1	0	0	0

INT:MUX.HEX_H0[5]	0.F23.B15	0.F25.B15	0.F22.B15	0.F20.B15	0.F18.B15	0.F27.B15	0.F29.B15
SINGLE_S_BUF[12]	0	0	0	0	0	0	1
SINGLE_S_BUF[19]	0	0	0	0	0	1	0
HEX_H6[5]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	1	0	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	1	0	0	0

INT:MUX.HEX_H6[0]	0.F46.B6	0.F37.B6	0.F46.B5	0.F38.B6	0.F47.B5	0.F45.B6	0.F36.B5
HEX_H0[0]	0	0	0	0	0	0	1
HEX_V3[2]	0	0	0	0	0	1	0
HEX_V6[0]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[2]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[2]	1	0	1	0	1	0	0

INT:MUX.HEX_H6[1]	0.F34.B6	0.F25.B6	0.F34.B5	0.F26.B6	0.F35.B5	0.F33.B6	0.F24.B5
HEX_H0[1]	0	0	0	0	0	0	1
HEX_V3[3]	0	0	0	0	0	1	0
HEX_V6[1]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[2]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[2]	1	0	1	0	1	0	0

INT:MUX.HEX_H6[2]	0.F22.B6	0.F13.B6	0.F22.B5	0.F14.B6	0.F23.B5	0.F21.B6	0.F12.B5
HEX_H0[2]	0	0	0	0	0	0	1
HEX_V3[0]	0	0	0	0	0	1	0
HEX_V6[2]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[2]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[2]	1	0	1	0	1	0	0

INT:MUX.HEX_H6[3]	0.F10.B6	0.F1.B6	0.F10.B5	0.F2.B6	0.F11.B5	0.F9.B6	0.F0.B5
HEX_H0[3]	0	0	0	0	0	0	1
HEX_V3[1]	0	0	0	0	0	1	0
HEX_V6[3]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[1]	0	1	1	0	0	1	0
OUT_IO_I[2]	0	1	1	0	1	0	0
OUT_IO_IQ[1]	1	0	1	0	0	1	0
OUT_IO_IQ[2]	1	0	1	0	1	0	0

INT:MUX.HEX_H6[4]	0.F24.B15	0.F31.B15	0.F16.B15	0.F21.B15	0.F17.B15	0.F26.B15	0.F30.B15
SINGLE_S_BUF[12]	0	0	0	0	0	0	1
SINGLE_S_BUF[19]	0	0	0	0	0	1	0
HEX_H0[4]	0	0	0	0	1	0	0
LH_FAKE0	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	1	0	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	1	0	0	0

INT:MUX.HEX_H6[5]	0.F36.B15	0.F32.B15	0.F47.B15	0.F42.B15	0.F46.B15	0.F38.B15	0.F33.B15
SINGLE_S_BUF[0]	0	0	0	0	0	0	1
SINGLE_S_BUF[7]	0	0	0	0	0	1	0
HEX_H0[5]	0	0	0	0	1	0	0
LH_FAKE6	0	0	0	1	0	0	0
NONE	0	0	1	0	0	0	0
OUT_IO_I[2]	0	1	1	0	0	0	1
OUT_IO_I[1]	0	1	1	1	0	0	0
OUT_IO_IQ[2]	1	0	1	0	0	0	1
OUT_IO_IQ[1]	1	0	1	1	0	0	0

INT:MUX.HEX_S0[0]	0.F42.B1	0.F39.B1	0.F38.B1	0.F47.B1
HEX_H0[2]	0	1	1	1
HEX_H3[1]	1	0	1	1
HEX_H6[0]	1	1	0	1
HEX_N1[0]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_S0[1]	0.F19.B1	0.F22.B1	0.F15.B1	0.F14.B1	0.F18.B1	0.F23.B1
HEX_H0[1]	0	0	0	1	1	1
HEX_H3[0]	0	0	1	0	1	1
HEX_H6[3]	0	0	1	1	0	1
HEX_N1[1]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[1]	0	1	1	1	1	1
OUT_IO_IQ[1]	1	0	1	1	1	1

INT:MUX.HEX_S0[2]	0.F31.B1	0.F34.B1	0.F26.B1	0.F30.B1	0.F27.B1	0.F35.B1
HEX_H0[0]	0	0	0	1	1	1
HEX_H3[3]	0	0	1	0	1	1
HEX_H6[2]	0	0	1	1	0	1
HEX_N1[2]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_IQ[2]	1	0	1	1	1	1

INT:MUX.HEX_S0[3]	0.F6.B1	0.F3.B1	0.F2.B1	0.F11.B1
HEX_H0[3]	0	1	1	1
HEX_H3[2]	1	0	1	1
HEX_H6[1]	1	1	0	1
HEX_N1[3]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_S1[0]	0.F41.B1	0.F40.B1	0.F37.B1	0.F36.B1
HEX_H0[2]	0	1	1	1
HEX_H3[1]	1	0	1	1
HEX_H6[0]	1	1	0	1
HEX_N2[0]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_S1[1]	0.F20.B1	0.F21.B1	0.F16.B1	0.F13.B1	0.F17.B1	0.F12.B1
HEX_H0[1]	0	0	0	1	1	1
HEX_H3[0]	0	0	1	0	1	1
HEX_H6[3]	0	0	1	1	0	1
HEX_N2[1]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[1]	0	1	1	1	1	1
OUT_IO_IQ[1]	1	0	1	1	1	1

INT:MUX.HEX_S1[2]	0.F32.B1	0.F33.B1	0.F25.B1	0.F29.B1	0.F28.B1	0.F24.B1
HEX_H0[0]	0	0	0	1	1	1
HEX_H3[3]	0	0	1	0	1	1
HEX_H6[2]	0	0	1	1	0	1
HEX_N2[2]	0	0	1	1	1	0
NONE	0	0	1	1	1	1
OUT_IO_I[2]	0	1	1	1	1	1
OUT_IO_IQ[2]	1	0	1	1	1	1

INT:MUX.HEX_S1[3]	0.F5.B1	0.F4.B1	0.F1.B1	0.F0.B1
HEX_H0[3]	0	1	1	1
HEX_H3[2]	1	0	1	1
HEX_H6[1]	1	1	0	1
HEX_N2[3]	1	1	1	0
NONE	1	1	1	1

INT:MUX.HEX_V1[0]	0.F37.B2	0.F36.B2
LV[5]	0	0
NONE	0	1
OUT_IO_I[2]	1	1

INT:MUX.HEX_V1[1]	0.F33.B2	0.F33.B0	0.F35.B2
LV[5]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V1[2]	0.F13.B2	0.F12.B2
LV[11]	0	0
NONE	0	1
OUT_IO_IQ[2]	1	1

INT:MUX.HEX_V1[3]	0.F9.B2	0.F9.B0	0.F11.B2
LV[11]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_V2[0]	0.F36.B0	0.F39.B0
LV[4]	0	0
NONE	0	1
OUT_IO_I[2]	1	1

INT:MUX.HEX_V2[1]	0.F32.B2	0.F34.B0	0.F32.B0
LV[4]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V2[2]	0.F12.B0	0.F15.B0
LV[10]	0	0
NONE	0	1
OUT_IO_IQ[2]	1	1

INT:MUX.HEX_V2[3]	0.F8.B2	0.F10.B0	0.F8.B0
LV[10]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_V3[0]	0.F42.B0	0.F41.B2	0.F40.B2
LV[3]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V3[1]	0.F29.B2	0.F31.B2
LV[3]	0	0
NONE	0	1
OUT_IO_I[1]	1	1

INT:MUX.HEX_V3[2]	0.F18.B0	0.F17.B2	0.F16.B2
LV[9]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_V3[3]	0.F5.B2	0.F7.B2
LV[9]	0	0
NONE	0	1
OUT_IO_IQ[1]	1	1

INT:MUX.HEX_V4[0]	0.F41.B0	0.F40.B0	0.F43.B0
LV[2]	0	0	0
NONE	0	0	1
OUT_IO_IQ[1]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V4[1]	0.F28.B2	0.F28.B0
LV[2]	0	0
NONE	0	1
OUT_IO_I[1]	1	1

INT:MUX.HEX_V4[2]	0.F17.B0	0.F16.B0	0.F19.B0
LV[8]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_I[2]	1	0	1

INT:MUX.HEX_V4[3]	0.F4.B2	0.F4.B0
LV[8]	0	0
NONE	0	1
OUT_IO_IQ[1]	1	1

INT:MUX.HEX_V5[0]	0.F44.B0	0.F46.B4	0.F44.B2
LV[1]	0	0	0
NONE	0	0	1
OUT_IO_I[1]	0	1	1
OUT_IO_IQ[1]	1	0	1

INT:MUX.HEX_V5[1]	0.F26.B0	0.F27.B2
LV[1]	0	0
NONE	0	1
OUT_IO_I[2]	1	1

INT:MUX.HEX_V5[2]	0.F22.B4	0.F20.B2
LV[7]	0	0
NONE	0	1
OUT_IO_IQ[1]	1	1

INT:MUX.HEX_V5[3]	0.F2.B0	0.F3.B0	0.F3.B2
LV[7]	0	0	0
NONE	0	0	1
OUT_IO_I[2]	0	1	1
OUT_IO_IQ[2]	1	0	1

INT:MUX.HEX_V6[0]	0.F46.B2	0.F46.B0	0.F45.B4	0.F47.B0	0.F47.B2
HEX_H0[1]	0	0	1	1	1
HEX_H3[3]	0	1	0	1	1
HEX_H6[0]	0	1	1	0	1
LV[0]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_I[1]	1	1	1	1	1

INT:MUX.HEX_V6[1]	0.F26.B2	0.F26.B4	0.F24.B0	0.F25.B0	0.F24.B2
HEX_H0[2]	0	0	1	1	1
HEX_H3[0]	0	1	0	1	1
HEX_H6[1]	0	1	1	0	1
LV[0]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_I[2]	1	1	1	1	1

INT:MUX.HEX_V6[2]	0.F22.B2	0.F21.B4	0.F23.B0	0.F22.B0	0.F23.B2
HEX_H0[3]	0	0	1	1	1
HEX_H3[1]	0	1	0	1	1
HEX_H6[2]	0	1	1	0	1
LV[6]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_IQ[1]	1	1	1	1	1

INT:MUX.HEX_V6[3]	0.F2.B2	0.F0.B0	0.F1.B0	0.F2.B4	0.F0.B2
HEX_H0[0]	0	0	1	1	1
HEX_H3[2]	0	1	0	1	1
HEX_H6[3]	0	1	1	0	1
LV[6]	0	1	1	1	0
NONE	0	1	1	1	1
OUT_IO_IQ[2]	1	1	1	1	1

INT:MUX.IMUX_IO_CLK[0]	0.F30.B12	0.F30.B14	0.F29.B14	0.F36.B13	0.F26.B14	0.F30.B13	0.F24.B13	0.F25.B14	0.F25.B13	0.F27.B13	0.F27.B14	0.F35.B13
INT:MUX.IMUX_IO_CLK[1]	0.F28.B14	0.F31.B14	0.F28.B13	0.F33.B13	0.F25.B12	0.F24.B14	0.F31.B13	0.F34.B13	0.F26.B13	0.F32.B13	0.F29.B13	0.F37.B13
INT:MUX.IMUX_IO_CLK[2]	0.F19.B14	0.F16.B14	0.F19.B13	0.F14.B13	0.F22.B12	0.F23.B14	0.F16.B13	0.F13.B13	0.F21.B13	0.F15.B13	0.F18.B13	0.F10.B13
INT:MUX.IMUX_IO_CLK[3]	0.F17.B12	0.F17.B14	0.F18.B14	0.F11.B13	0.F21.B14	0.F17.B13	0.F23.B13	0.F22.B14	0.F22.B13	0.F20.B13	0.F20.B14	0.F12.B13
GCLK_BUF[0]	0	0	0	0	0	0	1	1	1	1	1	1
GCLK_BUF[1]	0	0	0	0	0	1	0	1	1	1	1	1
GCLK_BUF[2]	0	0	0	0	0	1	1	0	1	1	1	1
GCLK_BUF[3]	0	0	0	0	0	1	1	1	0	1	1	1
NONE	0	0	0	0	0	1	1	1	1	1	1	1
HEX_V2_BUF[2]	0	0	0	1	0	1	1	1	1	0	1	1
HEX_H5_BUF[2]	0	0	0	1	0	1	1	1	1	1	0	1
HEX_V1_BUF[2]	0	0	0	1	0	1	1	1	1	1	1	0
SINGLE_S_BUF[8]	0	0	0	1	1	1	1	1	1	1	1	1
HEX_H1_BUF[2]	0	0	1	0	0	1	1	1	1	0	1	1
HEX_H4_BUF[2]	0	0	1	0	0	1	1	1	1	1	0	1
HEX_V5_BUF[2]	0	0	1	0	0	1	1	1	1	1	1	0
SINGLE_S_BUF[9]	0	0	1	0	1	1	1	1	1	1	1	1
HEX_V6_BUF[2]	0	1	0	0	0	1	1	1	1	0	1	1
HEX_H6_BUF[2]	0	1	0	0	0	1	1	1	1	1	0	1
HEX_V3_BUF[2]	0	1	0	0	0	1	1	1	1	1	1	0
SINGLE_S_BUF[14]	0	1	0	0	1	1	1	1	1	1	1	1
HEX_H2_BUF[2]	1	0	0	0	0	1	1	1	1	0	1	1
HEX_H3_BUF[2]	1	0	0	0	0	1	1	1	1	1	0	1
HEX_V4_BUF[2]	1	0	0	0	0	1	1	1	1	1	1	0
SINGLE_S_BUF[15]	1	0	0	0	1	1	1	1	1	1	1	1

INT:MUX.IMUX_IO_ICE[0]	0.F8.B10	0.F7.B10	0.F5.B11	0.F6.B11	0.F7.B9	0.F6.B10
INT:MUX.IMUX_IO_ICE[1]	0.F7.B11	0.F8.B11	0.F9.B11	0.F4.B9	0.F5.B9	0.F9.B10
INT:MUX.IMUX_IO_ICE[2]	0.F2.B11	0.F1.B11	0.F0.B11	0.F0.B9	0.F1.B9	0.F0.B10
INT:MUX.IMUX_IO_ICE[3]	0.F1.B10	0.F2.B10	0.F3.B11	0.F4.B11	0.F2.B9	0.F3.B10
NONE	0	0	0	0	0	0
SINGLE_S_BUF[20]	0	0	0	0	0	1
SINGLE_S_BUF[21]	0	0	0	0	1	0
SINGLE_S_BUF[22]	0	0	0	1	0	0
SINGLE_S_BUF[23]	0	0	1	0	0	0
HEX_V5_BUF[3]	0	1	0	0	0	1
HEX_V6_BUF[3]	0	1	0	0	1	0
HEX_H4_BUF[3]	0	1	0	1	0	0
HEX_H1_BUF[3]	0	1	1	0	0	0
HEX_V1_BUF[3]	1	0	0	0	0	1
HEX_V2_BUF[3]	1	0	0	0	1	0
HEX_V4_BUF[3]	1	0	0	1	0	0
HEX_V3_BUF[3]	1	0	1	0	0	0
HEX_H6_BUF[3]	1	1	0	0	0	1
HEX_H5_BUF[3]	1	1	0	0	1	0
HEX_H3_BUF[3]	1	1	0	1	0	0
HEX_H2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_OCE[0]	0.F18.B10	0.F17.B10	0.F14.B11	0.F15.B11	0.F14.B9	0.F16.B10
INT:MUX.IMUX_IO_OCE[1]	0.F17.B11	0.F18.B11	0.F19.B11	0.F16.B9	0.F15.B9	0.F19.B9
INT:MUX.IMUX_IO_OCE[2]	0.F12.B11	0.F11.B11	0.F10.B11	0.F11.B9	0.F9.B9	0.F10.B10
INT:MUX.IMUX_IO_OCE[3]	0.F11.B10	0.F12.B10	0.F13.B11	0.F8.B9	0.F12.B9	0.F13.B10
NONE	0	0	0	0	0	0
SINGLE_S_BUF[16]	0	0	0	0	0	1
SINGLE_S_BUF[17]	0	0	0	0	1	0
SINGLE_S_BUF[18]	0	0	0	1	0	0
SINGLE_S_BUF[19]	0	0	1	0	0	0
HEX_V5_BUF[3]	0	1	0	0	0	1
HEX_V6_BUF[3]	0	1	0	0	1	0
HEX_H4_BUF[3]	0	1	0	1	0	0
HEX_H1_BUF[3]	0	1	1	0	0	0
HEX_V1_BUF[3]	1	0	0	0	0	1
HEX_V2_BUF[3]	1	0	0	0	1	0
HEX_V4_BUF[3]	1	0	0	1	0	0
HEX_V3_BUF[3]	1	0	1	0	0	0
HEX_H6_BUF[3]	1	1	0	0	0	1
HEX_H5_BUF[3]	1	1	0	0	1	0
HEX_H3_BUF[3]	1	1	0	1	0	0
HEX_H2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_O[0]	0.F41.B13	0.F42.B13	0.F47.B13	0.F46.B13	0.F45.B14	0.F44.B13	0.F43.B13	0.F44.B14	0.F45.B13
NONE	0	0	0	0	0	0	0	0	1
HEX_V6_BUF[0]	0	0	0	0	0	0	1	0	0
SINGLE_S_BUF[0]	0	0	0	0	0	0	1	1	1
HEX_V3_BUF[0]	0	0	0	0	0	1	0	0	0
SINGLE_S_BUF[1]	0	0	0	0	0	1	0	1	1
SINGLE_S_BUF[3]	0	0	0	0	1	0	1	0	1
SINGLE_S_BUF[2]	0	0	0	0	1	1	0	0	1
HEX_V5_BUF[0]	0	0	0	1	0	0	0	0	0
SINGLE_S_BUF[9]	0	0	0	1	0	0	0	1	1
SINGLE_S_BUF[4]	0	0	0	1	1	0	0	0	1
HEX_V4_BUF[0]	0	0	1	0	0	0	0	0	0
SINGLE_S_BUF[8]	0	0	1	0	0	0	0	1	1
SINGLE_S_BUF[5]	0	0	1	0	1	0	0	0	1
SINGLE_S_BUF[6]	0	1	0	0	0	0	0	1	1
SINGLE_S_BUF[10]	0	1	0	0	1	0	0	0	1
SINGLE_S_BUF[7]	1	0	0	0	0	0	0	1	1
SINGLE_S_BUF[11]	1	0	0	0	1	0	0	0	1

INT:MUX.IMUX_IO_O[1]	0.F43.B14	0.F42.B14	0.F43.B12	0.F41.B12	0.F41.B14	0.F39.B13	0.F38.B13	0.F40.B14	0.F40.B13
NONE	0	0	0	0	0	0	0	0	1
HEX_V4_BUF[1]	0	0	0	0	0	0	1	0	0
SINGLE_S_BUF[0]	0	0	0	0	0	0	1	1	1
HEX_V3_BUF[1]	0	0	0	0	0	1	0	0	0
SINGLE_S_BUF[1]	0	0	0	0	0	1	0	1	1
SINGLE_S_BUF[3]	0	0	0	0	1	0	1	0	1
SINGLE_S_BUF[2]	0	0	0	0	1	1	0	0	1
HEX_V5_BUF[1]	0	0	0	1	0	0	0	0	0
SINGLE_S_BUF[9]	0	0	0	1	0	0	0	1	1
SINGLE_S_BUF[4]	0	0	0	1	1	0	0	0	1
HEX_V6_BUF[1]	0	0	1	0	0	0	0	0	0
SINGLE_S_BUF[8]	0	0	1	0	0	0	0	1	1
SINGLE_S_BUF[5]	0	0	1	0	1	0	0	0	1
SINGLE_S_BUF[6]	0	1	0	0	0	0	0	1	1
SINGLE_S_BUF[10]	0	1	0	0	1	0	0	0	1
SINGLE_S_BUF[7]	1	0	0	0	0	0	0	1	1
SINGLE_S_BUF[11]	1	0	0	0	1	0	0	0	1

INT:MUX.IMUX_IO_O[2]	0.F8.B13	0.F9.B13	0.F4.B12	0.F6.B12	0.F7.B14	0.F5.B14	0.F4.B14	0.F6.B14	0.F7.B13
NONE	0	0	0	0	0	0	0	0	1
SINGLE_S_BUF[12]	0	0	0	0	0	0	1	1	1
SINGLE_S_BUF[13]	0	0	0	0	0	1	0	1	1
SINGLE_S_BUF[16]	0	0	0	0	1	0	1	0	1
SINGLE_S_BUF[17]	0	0	0	0	1	1	0	0	1
HEX_V5_BUF[2]	0	0	0	1	0	0	0	0	0
SINGLE_S_BUF[19]	0	0	0	1	0	0	0	1	1
SINGLE_S_BUF[14]	0	0	0	1	1	0	0	0	1
HEX_V6_BUF[2]	0	0	1	0	0	0	0	0	0
SINGLE_S_BUF[18]	0	0	1	0	0	0	0	1	1
SINGLE_S_BUF[15]	0	0	1	0	1	0	0	0	1
HEX_V4_BUF[2]	0	1	0	0	0	0	0	0	0
SINGLE_S_BUF[20]	0	1	0	0	0	0	0	1	1
SINGLE_S_BUF[23]	0	1	0	0	1	0	0	0	1
HEX_V3_BUF[2]	1	0	0	0	0	0	0	0	0
SINGLE_S_BUF[21]	1	0	0	0	0	0	0	1	1
SINGLE_S_BUF[22]	1	0	0	0	1	0	0	0	1

INT:MUX.IMUX_IO_O[3]	0.F3.B13	0.F4.B13	0.F0.B13	0.F1.B13	0.F3.B14	0.F5.B13	0.F6.B13	0.F2.B14	0.F2.B13
NONE	0	0	0	0	0	0	0	0	1
SINGLE_S_BUF[12]	0	0	0	0	0	0	1	1	1
SINGLE_S_BUF[13]	0	0	0	0	0	1	0	1	1
SINGLE_S_BUF[16]	0	0	0	0	1	0	1	0	1
SINGLE_S_BUF[17]	0	0	0	0	1	1	0	0	1
HEX_V5_BUF[3]	0	0	0	1	0	0	0	0	0
SINGLE_S_BUF[19]	0	0	0	1	0	0	0	1	1
SINGLE_S_BUF[14]	0	0	0	1	1	0	0	0	1
HEX_V4_BUF[3]	0	0	1	0	0	0	0	0	0
SINGLE_S_BUF[18]	0	0	1	0	0	0	0	1	1
SINGLE_S_BUF[15]	0	0	1	0	1	0	0	0	1
HEX_V6_BUF[3]	0	1	0	0	0	0	0	0	0
SINGLE_S_BUF[20]	0	1	0	0	0	0	0	1	1
SINGLE_S_BUF[23]	0	1	0	0	1	0	0	0	1
HEX_V3_BUF[3]	1	0	0	0	0	0	0	0	0
SINGLE_S_BUF[21]	1	0	0	0	0	0	0	1	1
SINGLE_S_BUF[22]	1	0	0	0	1	0	0	0	1

INT:MUX.IMUX_IO_SR[0]	0.F29.B10	0.F30.B10	0.F31.B10	0.F33.B9	0.F32.B11	0.F33.B11
INT:MUX.IMUX_IO_SR[1]	0.F30.B11	0.F29.B11	0.F28.B9	0.F32.B9	0.F31.B9	0.F28.B11
INT:MUX.IMUX_IO_SR[2]	0.F35.B11	0.F36.B11	0.F37.B10	0.F38.B9	0.F36.B9	0.F37.B11
INT:MUX.IMUX_IO_SR[3]	0.F36.B10	0.F35.B10	0.F34.B10	0.F35.B9	0.F39.B9	0.F34.B11
NONE	0	0	0	0	0	0
SINGLE_S_BUF[4]	0	0	0	0	0	1
SINGLE_S_BUF[5]	0	0	0	0	1	0
SINGLE_S_BUF[6]	0	0	0	1	0	0
SINGLE_S_BUF[7]	0	0	1	0	0	0
HEX_H1_BUF[1]	0	1	0	0	0	1
HEX_H4_BUF[1]	0	1	0	0	1	0
HEX_V1_BUF[1]	0	1	0	1	0	0
HEX_V2_BUF[1]	0	1	1	0	0	0
HEX_V4_BUF[1]	1	0	0	0	0	1
HEX_V3_BUF[1]	1	0	0	0	1	0
HEX_V5_BUF[1]	1	0	0	1	0	0
HEX_V6_BUF[1]	1	0	1	0	0	0
HEX_H2_BUF[1]	1	1	0	0	0	1
HEX_H3_BUF[1]	1	1	0	0	1	0
HEX_H5_BUF[1]	1	1	0	1	0	0
HEX_H6_BUF[1]	1	1	1	0	0	0

INT:MUX.IMUX_IO_TCE[0]	0.F25.B11	0.F26.B11	0.F27.B11	0.F25.B9	0.F26.B9	0.F28.B10
INT:MUX.IMUX_IO_TCE[1]	0.F27.B10	0.F26.B10	0.F24.B11	0.F31.B11	0.F27.B9	0.F24.B10
INT:MUX.IMUX_IO_TCE[2]	0.F22.B11	0.F21.B11	0.F20.B11	0.F22.B9	0.F21.B9	0.F19.B10
INT:MUX.IMUX_IO_TCE[3]	0.F20.B10	0.F21.B10	0.F23.B11	0.F16.B11	0.F20.B9	0.F23.B10
NONE	0	0	0	0	0	0
SINGLE_S_BUF[10]	0	0	0	0	0	1
SINGLE_S_BUF[11]	0	0	0	0	1	0
SINGLE_S_BUF[12]	0	0	0	1	0	0
SINGLE_S_BUF[13]	0	0	1	0	0	0
HEX_V5_BUF[3]	0	1	0	0	0	1
HEX_V6_BUF[3]	0	1	0	0	1	0
HEX_H4_BUF[3]	0	1	0	1	0	0
HEX_H1_BUF[3]	0	1	1	0	0	0
HEX_V1_BUF[3]	1	0	0	0	0	1
HEX_V2_BUF[3]	1	0	0	0	1	0
HEX_V4_BUF[3]	1	0	0	1	0	0
HEX_V3_BUF[3]	1	0	1	0	0	0
HEX_H6_BUF[3]	1	1	0	0	0	1
HEX_H5_BUF[3]	1	1	0	0	1	0
HEX_H3_BUF[3]	1	1	0	1	0	0
HEX_H2_BUF[3]	1	1	1	0	0	0

INT:MUX.IMUX_IO_T[0]	0.F39.B10	0.F40.B10	0.F41.B10	0.F40.B9	0.F41.B11	0.F42.B11
INT:MUX.IMUX_IO_T[1]	0.F40.B11	0.F39.B11	0.F38.B10	0.F42.B9	0.F43.B9	0.F38.B11
INT:MUX.IMUX_IO_T[2]	0.F45.B11	0.F46.B11	0.F47.B10	0.F46.B9	0.F47.B9	0.F47.B11
INT:MUX.IMUX_IO_T[3]	0.F46.B10	0.F45.B10	0.F44.B10	0.F45.B9	0.F43.B11	0.F44.B11
NONE	0	0	0	0	0	0
SINGLE_S_BUF[0]	0	0	0	0	0	1
SINGLE_S_BUF[1]	0	0	0	0	1	0
SINGLE_S_BUF[2]	0	0	0	1	0	0
SINGLE_S_BUF[3]	0	0	1	0	0	0
HEX_H1_BUF[0]	0	1	0	0	0	1
HEX_H4_BUF[0]	0	1	0	0	1	0
HEX_V6_BUF[0]	0	1	0	1	0	0
HEX_V5_BUF[0]	0	1	1	0	0	0
HEX_V3_BUF[0]	1	0	0	0	0	1
HEX_V4_BUF[0]	1	0	0	0	1	0
HEX_V2_BUF[0]	1	0	0	1	0	0
HEX_V1_BUF[0]	1	0	1	0	0	0
HEX_H2_BUF[0]	1	1	0	0	0	1
HEX_H3_BUF[0]	1	1	0	0	1	0
HEX_H5_BUF[0]	1	1	0	1	0	0
HEX_H6_BUF[0]	1	1	1	0	0	0

INT:MUX.LH[0]	0.F9.B15	0.F12.B12	0.F4.B15	0.F6.B15	0.F15.B15	0.F14.B12	0.F8.B15	0.F13.B15	0.F1.B12
INT:MUX.LH[6]	0.F5.B15	0.F9.B12	0.F1.B15	0.F7.B15	0.F14.B15	0.F11.B15	0.F12.B15	0.F2.B15	0.F0.B15
NONE	0	0	0	0	0	0	0	0	0
SINGLE_S_BUF[5]	0	0	0	0	0	0	0	0	1
SINGLE_S_BUF[6]	0	0	0	0	0	0	0	1	0
SINGLE_S_BUF[10]	0	0	0	0	0	0	1	0	0
SINGLE_S_BUF[11]	0	0	0	0	0	1	0	0	0
SINGLE_S_BUF[17]	0	0	0	0	1	0	0	0	0
SINGLE_S_BUF[18]	0	0	0	1	0	0	0	0	0
SINGLE_S_BUF[22]	0	0	1	0	0	0	0	0	0
SINGLE_S_BUF[23]	0	1	0	0	0	0	0	0	0
OUT_IO_IQ[2]	1	0	0	0	0	0	0	1	0
OUT_IO_I[2]	1	0	0	0	0	0	1	0	0
OUT_IO_IQ[1]	1	0	0	0	1	0	0	0	0
OUT_IO_I[1]	1	0	1	0	0	0	0	0	0

INT:MUX.LV[0]
HEX_H6[5]

INT:MUX.LV[10]
HEX_H2[4]

INT:MUX.LV[11]
HEX_H1[4]

INT:MUX.LV[1]
HEX_H5[5]

INT:MUX.LV[2]	0.F32.B12
HEX_H4[5]	0
OUT_IO_IQ[1]	1

INT:MUX.LV[3]	0.F39.B12
HEX_H3[5]	0
OUT_IO_IQ[1]	1

INT:MUX.LV[4]	0.F40.B12
HEX_H2[5]	0
OUT_IO_I[1]	1

INT:MUX.LV[5]	0.F47.B12
HEX_H1[5]	0
OUT_IO_I[1]	1

INT:MUX.LV[6]	0.F23.B12
HEX_H6[4]	0
OUT_IO_IQ[2]	1

INT:MUX.LV[7]	0.F16.B12
HEX_H5[4]	0
OUT_IO_IQ[2]	1

INT:MUX.LV[8]	0.F15.B12
HEX_H4[4]	0
OUT_IO_I[2]	1

INT:MUX.LV[9]	0.F8.B12
HEX_H3[4]	0
OUT_IO_I[2]	1

IO[1]:OMUX	0.F40.B16
IO[2]:OMUX	0.F25.B16
O	0
OFF	1

IO[1]:TMUX	0.F35.B16
IO[2]:TMUX	0.F30.B16
T	0
TFF	1

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