I/O Interface

Tile IO_W

Cells: 1

Switchbox INT

virtex IO_W switchbox INT permanent buffers
Destination	Source
SINGLE_E_BUF[0]	SINGLE_E[0]
SINGLE_E_BUF[1]	SINGLE_E[1]
SINGLE_E_BUF[2]	SINGLE_E[2]
SINGLE_E_BUF[3]	SINGLE_E[3]
SINGLE_E_BUF[4]	SINGLE_E[4]
SINGLE_E_BUF[5]	SINGLE_E[5]
SINGLE_E_BUF[6]	SINGLE_E[6]
SINGLE_E_BUF[7]	SINGLE_E[7]
SINGLE_E_BUF[8]	SINGLE_E[8]
SINGLE_E_BUF[9]	SINGLE_E[9]
SINGLE_E_BUF[10]	SINGLE_E[10]
SINGLE_E_BUF[11]	SINGLE_E[11]
SINGLE_E_BUF[12]	SINGLE_E[12]
SINGLE_E_BUF[13]	SINGLE_E[13]
SINGLE_E_BUF[14]	SINGLE_E[14]
SINGLE_E_BUF[15]	SINGLE_E[15]
SINGLE_E_BUF[16]	SINGLE_E[16]
SINGLE_E_BUF[17]	SINGLE_E[17]
SINGLE_E_BUF[18]	SINGLE_E[18]
SINGLE_E_BUF[19]	SINGLE_E[19]
SINGLE_E_BUF[20]	SINGLE_E[20]
SINGLE_E_BUF[21]	SINGLE_E[21]
SINGLE_E_BUF[22]	SINGLE_E[22]
SINGLE_E_BUF[23]	SINGLE_E[23]
HEX_H0_BUF[0]	HEX_H0[0]
HEX_H0_BUF[1]	HEX_H0[1]
HEX_H0_BUF[2]	HEX_H0[2]
HEX_H0_BUF[3]	HEX_H0[3]
HEX_H1_BUF[0]	HEX_H1[0]
HEX_H1_BUF[1]	HEX_H1[1]
HEX_H1_BUF[2]	HEX_H1[2]
HEX_H1_BUF[3]	HEX_H1[3]
HEX_H2_BUF[0]	HEX_H2[0]
HEX_H2_BUF[1]	HEX_H2[1]
HEX_H2_BUF[2]	HEX_H2[2]
HEX_H2_BUF[3]	HEX_H2[3]
HEX_H3_BUF[0]	HEX_H3[0]
HEX_H3_BUF[1]	HEX_H3[1]
HEX_H3_BUF[2]	HEX_H3[2]
HEX_H3_BUF[3]	HEX_H3[3]
HEX_E2[0]	HEX_W3[0]
HEX_E2[1]	HEX_W3[1]
HEX_E2[2]	HEX_W3[2]
HEX_E2[3]	HEX_W3[3]
HEX_E3[0]	HEX_W4[0]
HEX_E3[1]	HEX_W4[1]
HEX_E3[2]	HEX_W4[2]
HEX_E3[3]	HEX_W4[3]
HEX_E4[0]	HEX_W5[0]
HEX_E4[1]	HEX_W5[1]
HEX_E4[2]	HEX_W5[2]
HEX_E4[3]	HEX_W5[3]
HEX_E5[0]	HEX_W6[0]
HEX_E5[1]	HEX_W6[1]
HEX_E5[2]	HEX_W6[2]
HEX_E5[3]	HEX_W6[3]
HEX_V1_BUF[0]	HEX_V1[0]
HEX_V1_BUF[1]	HEX_V1[1]
HEX_V1_BUF[2]	HEX_V1[2]
HEX_V1_BUF[3]	HEX_V1[3]
HEX_V2_BUF[0]	HEX_V2[0]
HEX_V2_BUF[1]	HEX_V2[1]
HEX_V2_BUF[2]	HEX_V2[2]
HEX_V2_BUF[3]	HEX_V2[3]
HEX_V3_BUF[0]	HEX_V3[0]
HEX_V3_BUF[1]	HEX_V3[1]
HEX_V3_BUF[2]	HEX_V3[2]
HEX_V3_BUF[3]	HEX_V3[3]
HEX_V4_BUF[0]	HEX_V4[0]
HEX_V4_BUF[1]	HEX_V4[1]
HEX_V4_BUF[2]	HEX_V4[2]
HEX_V4_BUF[3]	HEX_V4[3]
HEX_V5_BUF[0]	HEX_V5[0]
HEX_V5_BUF[1]	HEX_V5[1]
HEX_V5_BUF[2]	HEX_V5[2]
HEX_V5_BUF[3]	HEX_V5[3]
HEX_V6_BUF[0]	HEX_V6[0]
HEX_V6_BUF[1]	HEX_V6[1]
HEX_V6_BUF[2]	HEX_V6[2]
HEX_V6_BUF[3]	HEX_V6[3]

virtex IO_W switchbox INT programmable buffers
Destination	Source	Bit
HEX_H0[0]	HEX_H0_MUX[0]	MAIN[47][4]
HEX_H0[1]	HEX_H0_MUX[1]	MAIN[24][4]
HEX_H0[2]	HEX_H0_MUX[2]	MAIN[23][4]
HEX_H0[3]	HEX_H0_MUX[3]	MAIN[0][4]
HEX_H1[0]	HEX_H1_MUX[0]	MAIN[44][4]
HEX_H1[1]	HEX_H1_MUX[1]	MAIN[27][4]
HEX_H1[2]	HEX_H1_MUX[2]	MAIN[20][4]
HEX_H1[3]	HEX_H1_MUX[3]	MAIN[3][4]
HEX_H2[0]	HEX_H2_MUX[0]	MAIN[43][4]
HEX_H2[1]	HEX_H2_MUX[1]	MAIN[28][4]
HEX_H2[2]	HEX_H2_MUX[2]	MAIN[19][4]
HEX_H2[3]	HEX_H2_MUX[3]	MAIN[4][4]
HEX_H3[0]	HEX_H3_MUX[0]	MAIN[40][4]
HEX_H3[1]	HEX_H3_MUX[1]	MAIN[31][4]
HEX_H3[2]	HEX_H3_MUX[2]	MAIN[16][4]
HEX_H3[3]	HEX_H3_MUX[3]	MAIN[7][4]
HEX_H4[0]	HEX_H4_MUX[0]	MAIN[39][4]
HEX_H4[1]	HEX_H4_MUX[1]	MAIN[32][4]
HEX_H4[2]	HEX_H4_MUX[2]	MAIN[15][4]
HEX_H4[3]	HEX_H4_MUX[3]	MAIN[8][4]
HEX_H5[0]	HEX_H5_MUX[0]	MAIN[36][4]
HEX_H5[1]	HEX_H5_MUX[1]	MAIN[35][4]
HEX_H5[2]	HEX_H5_MUX[2]	MAIN[12][4]
HEX_H5[3]	HEX_H5_MUX[3]	MAIN[11][4]
HEX_V0[0]	HEX_V0_MUX[0]	MAIN[36][6]
HEX_V0[1]	HEX_V0_MUX[1]	MAIN[24][6]
HEX_V0[2]	HEX_V0_MUX[2]	MAIN[12][6]
HEX_V0[3]	HEX_V0_MUX[3]	MAIN[0][6]
HEX_V6[0]	HEX_V6_MUX[0]	MAIN[47][6]
HEX_V6[1]	HEX_V6_MUX[1]	MAIN[35][6]
HEX_V6[2]	HEX_V6_MUX[2]	MAIN[23][6]
HEX_V6[3]	HEX_V6_MUX[3]	MAIN[11][6]
LH[0]	LH_MUX[0]	MAIN[26][12]
LH[1]	LH_MUX[1]	MAIN[21][12]
LH[2]	LH_MUX[2]	MAIN[18][12]
LH[3]	LH_MUX[3]	MAIN[13][12]
LH[4]	LH_MUX[4]	MAIN[10][12]
LH[5]	LH_MUX[5]	MAIN[5][12]
LH[6]	LH_MUX[6]	MAIN[2][12]
LH[7]	LH_MUX[7]	MAIN[29][12]
LH[8]	LH_MUX[8]	MAIN[34][12]
LH[9]	LH_MUX[9]	MAIN[37][12]
LH[10]	LH_MUX[10]	MAIN[42][12]
LH[11]	LH_MUX[11]	MAIN[45][12]
LV[0]	LV_MUX[0]	MAIN[2][15]
LV[6]	LV_MUX[6]	MAIN[10][15]

virtex IO_W switchbox INT pass gates
Destination	Source	Bit
SINGLE_E[0]	HEX_V6[0]	MAIN[47][7]
SINGLE_E[0]	OUT_TBUF_W[3]	MAIN[47][8]
SINGLE_E[0]	OUT_IO_I[3]	MAIN[46][8]
SINGLE_E[1]	HEX_V3[0]	MAIN[45][8]
SINGLE_E[1]	OUT_IO_I[2]	MAIN[44][8]
SINGLE_E[2]	HEX_V0[0]	MAIN[43][8]
SINGLE_E[2]	OUT_IO_I[1]	MAIN[42][8]
SINGLE_E[3]	HEX_V6[0]	MAIN[39][8]
SINGLE_E[3]	OUT_TBUF_W[3]	MAIN[41][8]
SINGLE_E[4]	HEX_V3[0]	MAIN[37][8]
SINGLE_E[4]	OUT_IO_IQ[3]	MAIN[38][8]
SINGLE_E[5]	HEX_V0[0]	MAIN[36][8]
SINGLE_E[5]	OUT_IO_IQ[2]	MAIN[36][7]
SINGLE_E[6]	HEX_V6[1]	MAIN[35][7]
SINGLE_E[6]	OUT_TBUF_W[2]	MAIN[35][8]
SINGLE_E[6]	OUT_IO_IQ[1]	MAIN[34][8]
SINGLE_E[7]	HEX_V3[1]	MAIN[33][8]
SINGLE_E[8]	HEX_V0[1]	MAIN[31][8]
SINGLE_E[8]	OUT_IO_I[3]	MAIN[30][8]
SINGLE_E[9]	HEX_V6[1]	MAIN[27][8]
SINGLE_E[9]	OUT_TBUF_W[2]	MAIN[29][8]
SINGLE_E[9]	OUT_IO_I[2]	MAIN[28][8]
SINGLE_E[10]	HEX_V3[1]	MAIN[25][8]
SINGLE_E[10]	OUT_IO_I[1]	MAIN[26][8]
SINGLE_E[11]	HEX_V0[1]	MAIN[24][8]
SINGLE_E[12]	HEX_V6[2]	MAIN[23][7]
SINGLE_E[12]	OUT_TBUF_W[1]	MAIN[23][8]
SINGLE_E[12]	OUT_IO_IQ[3]	MAIN[22][8]
SINGLE_E[13]	HEX_V3[2]	MAIN[21][8]
SINGLE_E[13]	OUT_IO_IQ[2]	MAIN[20][8]
SINGLE_E[14]	HEX_V0[2]	MAIN[19][8]
SINGLE_E[14]	OUT_IO_IQ[1]	MAIN[18][8]
SINGLE_E[15]	HEX_V6[2]	MAIN[15][8]
SINGLE_E[15]	OUT_TBUF_W[1]	MAIN[17][8]
SINGLE_E[16]	HEX_V3[2]	MAIN[13][8]
SINGLE_E[16]	OUT_IO_I[3]	MAIN[14][8]
SINGLE_E[17]	HEX_V0[2]	MAIN[12][8]
SINGLE_E[17]	OUT_IO_I[2]	MAIN[12][7]
SINGLE_E[18]	HEX_V6[3]	MAIN[11][7]
SINGLE_E[18]	OUT_TBUF_W[0]	MAIN[11][8]
SINGLE_E[18]	OUT_IO_I[1]	MAIN[10][8]
SINGLE_E[19]	HEX_V3[3]	MAIN[9][8]
SINGLE_E[20]	HEX_V0[3]	MAIN[7][8]
SINGLE_E[20]	OUT_IO_IQ[3]	MAIN[6][8]
SINGLE_E[21]	HEX_V6[3]	MAIN[3][8]
SINGLE_E[21]	OUT_TBUF_W[0]	MAIN[5][8]
SINGLE_E[21]	OUT_IO_IQ[2]	MAIN[4][8]
SINGLE_E[22]	HEX_V3[3]	MAIN[1][8]
SINGLE_E[22]	OUT_IO_IQ[1]	MAIN[2][8]
SINGLE_E[23]	HEX_V0[3]	MAIN[0][8]

virtex IO_W switchbox INT muxes HEX_H0_MUX[0]
Bits					Destination
MAIN[46][2]	MAIN[46][0]	MAIN[45][4]	MAIN[47][0]	MAIN[47][2]	HEX_H0_MUX[0]
					Source
0	0	1	1	1	HEX_V0[1]
0	1	0	1	1	HEX_V3[3]
0	1	1	0	1	HEX_V6[0]
0	1	1	1	0	LH[0]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_I[1]

virtex IO_W switchbox INT muxes HEX_H0_MUX[1]
Bits						Destination
MAIN[25][2]	MAIN[26][2]	MAIN[26][4]	MAIN[24][0]	MAIN[25][0]	MAIN[24][2]	HEX_H0_MUX[1]
						Source
0	0	0	1	1	1	HEX_V0[2]
0	0	1	0	1	1	HEX_V3[0]
0	0	1	1	0	1	HEX_V6[1]
0	0	1	1	1	0	LH[0]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H0_MUX[2]
Bits					Destination
MAIN[22][2]	MAIN[21][4]	MAIN[23][0]	MAIN[22][0]	MAIN[23][2]	HEX_H0_MUX[2]
					Source
0	0	1	1	1	HEX_V0[3]
0	1	0	1	1	HEX_V3[1]
0	1	1	0	1	HEX_V6[2]
0	1	1	1	0	LH[6]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H0_MUX[3]
Bits						Destination
MAIN[1][2]	MAIN[2][2]	MAIN[0][0]	MAIN[1][0]	MAIN[2][4]	MAIN[0][2]	HEX_H0_MUX[3]
						Source
0	0	0	1	1	1	HEX_V0[0]
0	0	1	0	1	1	HEX_V3[2]
0	0	1	1	0	1	HEX_V6[3]
0	0	1	1	1	0	LH[6]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_IQ[2]
1	0	1	1	1	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H1_MUX[0]
Bits			Destination
MAIN[44][0]	MAIN[46][4]	MAIN[44][2]	HEX_H1_MUX[0]
			Source
0	0	0	LH[11]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H1_MUX[1]
Bits			Destination
MAIN[25][4]	MAIN[26][0]	MAIN[27][2]	HEX_H1_MUX[1]
			Source
0	0	0	LH[11]
0	0	1	off
0	1	1	OUT_IO_I[2]
1	0	1	OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H1_MUX[2]
Bits			Destination
MAIN[22][4]	MAIN[20][0]	MAIN[20][2]	HEX_H1_MUX[2]
			Source
0	0	0	LH[5]
0	0	1	off
0	1	1	OUT_IO_I[3]
1	0	1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H1_MUX[3]
Bits				Destination
MAIN[1][4]	MAIN[2][0]	MAIN[3][0]	MAIN[3][2]	HEX_H1_MUX[3]
				Source
0	0	0	0	LH[5]
0	0	0	1	off
0	0	1	1	OUT_IO_I[2]
0	1	0	1	OUT_IO_IQ[2]
1	0	0	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H2_MUX[0]
Bits				Destination
MAIN[43][2]	MAIN[41][0]	MAIN[40][0]	MAIN[43][0]	HEX_H2_MUX[0]
				Source
0	0	0	0	LH[10]
0	0	0	1	off
0	0	1	1	OUT_IO_IQ[1]
0	1	0	1	OUT_IO_IQ[2]
1	0	0	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H2_MUX[1]
Bits			Destination
MAIN[31][0]	MAIN[28][2]	MAIN[28][0]	HEX_H2_MUX[1]
			Source
0	0	0	LH[10]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H2_MUX[2]
Bits				Destination
MAIN[19][2]	MAIN[17][0]	MAIN[16][0]	MAIN[19][0]	HEX_H2_MUX[2]
				Source
0	0	0	0	LH[4]
0	0	0	1	off
0	0	1	1	OUT_IO_I[1]
0	1	0	1	OUT_IO_I[2]
1	0	0	1	OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H2_MUX[3]
Bits			Destination
MAIN[4][2]	MAIN[7][0]	MAIN[4][0]	HEX_H2_MUX[3]
			Source
0	0	0	LH[4]
0	0	1	off
0	1	1	OUT_IO_I[3]
1	0	1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H3_MUX[0]
Bits				Destination
MAIN[42][2]	MAIN[42][0]	MAIN[41][2]	MAIN[40][2]	HEX_H3_MUX[0]
				Source
0	0	0	0	LH[9]
0	0	0	1	off
0	0	1	1	OUT_IO_IQ[1]
0	1	0	1	OUT_IO_IQ[2]
1	0	0	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H3_MUX[1]
Bits			Destination
MAIN[30][2]	MAIN[29][2]	MAIN[31][2]	HEX_H3_MUX[1]
			Source
0	0	0	LH[9]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H3_MUX[2]
Bits				Destination
MAIN[18][2]	MAIN[18][0]	MAIN[17][2]	MAIN[16][2]	HEX_H3_MUX[2]
				Source
0	0	0	0	LH[3]
0	0	0	1	off
0	0	1	1	OUT_IO_I[1]
0	1	0	1	OUT_IO_I[2]
1	0	0	1	OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H3_MUX[3]
Bits			Destination
MAIN[5][2]	MAIN[6][2]	MAIN[7][2]	HEX_H3_MUX[3]
			Source
0	0	0	LH[3]
0	0	1	off
0	1	1	OUT_IO_I[3]
1	0	1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_H4_MUX[0]
Bits			Destination
MAIN[37][0]	MAIN[36][0]	MAIN[39][0]	HEX_H4_MUX[0]
			Source
0	0	0	LH[8]
0	0	1	off
0	1	1	OUT_IO_I[2]
1	0	1	OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H4_MUX[1]
Bits			Destination
MAIN[32][2]	MAIN[34][0]	MAIN[32][0]	HEX_H4_MUX[1]
			Source
0	0	0	LH[8]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes HEX_H4_MUX[2]
Bits			Destination
MAIN[13][0]	MAIN[12][0]	MAIN[15][0]	HEX_H4_MUX[2]
			Source
0	0	0	LH[2]
0	0	1	off
0	1	1	OUT_IO_IQ[2]
1	0	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H4_MUX[3]
Bits			Destination
MAIN[8][2]	MAIN[10][0]	MAIN[8][0]	HEX_H4_MUX[3]
			Source
0	0	0	LH[2]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_W switchbox INT muxes HEX_H5_MUX[0]
Bits			Destination
MAIN[38][0]	MAIN[37][2]	MAIN[36][2]	HEX_H5_MUX[0]
			Source
0	0	0	LH[7]
0	0	1	off
0	1	1	OUT_IO_I[2]
1	0	1	OUT_IO_I[3]

virtex IO_W switchbox INT muxes HEX_H5_MUX[1]
Bits			Destination
MAIN[33][2]	MAIN[33][0]	MAIN[35][2]	HEX_H5_MUX[1]
			Source
0	0	0	LH[7]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes HEX_H5_MUX[2]
Bits			Destination
MAIN[14][0]	MAIN[13][2]	MAIN[12][2]	HEX_H5_MUX[2]
			Source
0	0	0	LH[1]
0	0	1	off
0	1	1	OUT_IO_IQ[2]
1	0	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_H5_MUX[3]
Bits			Destination
MAIN[9][2]	MAIN[9][0]	MAIN[11][2]	HEX_H5_MUX[3]
			Source
0	0	0	LH[1]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_W switchbox INT muxes HEX_E0[0]
Bits				Destination
MAIN[36][1]	MAIN[41][1]	MAIN[40][1]	MAIN[37][1]	HEX_E0[0]
				Source
0	1	1	1	HEX_W1[0]
1	0	1	1	HEX_V0[2]
1	1	0	1	HEX_V3[1]
1	1	1	0	HEX_V6[0]
1	1	1	1	off

virtex IO_W switchbox INT muxes HEX_E0[1]
Bits						Destination
MAIN[20][1]	MAIN[21][1]	MAIN[12][1]	MAIN[16][1]	MAIN[13][1]	MAIN[17][1]	HEX_E0[1]
						Source
0	0	0	1	1	1	HEX_W1[1]
0	0	1	0	1	1	HEX_V0[1]
0	0	1	1	0	1	HEX_V3[0]
0	0	1	1	1	0	HEX_V6[3]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[1]
1	0	1	1	1	1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_E0[2]
Bits						Destination
MAIN[32][1]	MAIN[33][1]	MAIN[24][1]	MAIN[25][1]	MAIN[29][1]	MAIN[28][1]	HEX_E0[2]
						Source
0	0	0	1	1	1	HEX_W1[2]
0	0	1	0	1	1	HEX_V0[0]
0	0	1	1	0	1	HEX_V3[3]
0	0	1	1	1	0	HEX_V6[2]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes HEX_E0[3]
Bits						Destination
MAIN[8][1]	MAIN[9][1]	MAIN[0][1]	MAIN[5][1]	MAIN[4][1]	MAIN[1][1]	HEX_E0[3]
						Source
0	0	0	1	1	1	HEX_W1[3]
0	0	1	0	1	1	HEX_V0[3]
0	0	1	1	0	1	HEX_V3[2]
0	0	1	1	1	0	HEX_V6[1]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[3]
1	0	1	1	1	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_E1[0]
Bits				Destination
MAIN[47][1]	MAIN[42][1]	MAIN[39][1]	MAIN[38][1]	HEX_E1[0]
				Source
0	1	1	1	HEX_W2[0]
1	0	1	1	HEX_V0[2]
1	1	0	1	HEX_V3[1]
1	1	1	0	HEX_V6[0]
1	1	1	1	off

virtex IO_W switchbox INT muxes HEX_E1[1]
Bits						Destination
MAIN[19][1]	MAIN[22][1]	MAIN[23][1]	MAIN[15][1]	MAIN[14][1]	MAIN[18][1]	HEX_E1[1]
						Source
0	0	0	1	1	1	HEX_W2[1]
0	0	1	0	1	1	HEX_V0[1]
0	0	1	1	0	1	HEX_V3[0]
0	0	1	1	1	0	HEX_V6[3]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[1]
1	0	1	1	1	1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes HEX_E1[2]
Bits						Destination
MAIN[31][1]	MAIN[34][1]	MAIN[35][1]	MAIN[26][1]	MAIN[30][1]	MAIN[27][1]	HEX_E1[2]
						Source
0	0	0	1	1	1	HEX_W2[2]
0	0	1	0	1	1	HEX_V0[0]
0	0	1	1	0	1	HEX_V3[3]
0	0	1	1	1	0	HEX_V6[2]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes HEX_E1[3]
Bits						Destination
MAIN[7][1]	MAIN[10][1]	MAIN[11][1]	MAIN[6][1]	MAIN[3][1]	MAIN[2][1]	HEX_E1[3]
						Source
0	0	0	1	1	1	HEX_W2[3]
0	0	1	0	1	1	HEX_V0[3]
0	0	1	1	0	1	HEX_V3[2]
0	0	1	1	1	0	HEX_V6[1]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[3]
1	0	1	1	1	1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V0_MUX[0]
Bits							Destination
MAIN[41][6]	MAIN[40][6]	MAIN[42][6]	MAIN[44][6]	MAIN[43][6]	MAIN[37][5]	MAIN[39][6]	HEX_V0_MUX[0]
							Source
0	0	0	0	0	0	1	HEX_H0[3]
0	0	0	0	0	1	0	HEX_H3[2]
0	0	0	0	1	0	0	HEX_V6[0]
0	0	0	1	0	0	0	LV[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V0_MUX[1]
Bits							Destination
MAIN[29][6]	MAIN[28][6]	MAIN[30][6]	MAIN[32][6]	MAIN[31][6]	MAIN[25][5]	MAIN[27][6]	HEX_V0_MUX[1]
							Source
0	0	0	0	0	0	1	HEX_H0[0]
0	0	0	0	0	1	0	HEX_H3[3]
0	0	0	0	1	0	0	HEX_V6[1]
0	0	0	1	0	0	0	LV[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V0_MUX[2]
Bits							Destination
MAIN[17][6]	MAIN[16][6]	MAIN[18][6]	MAIN[20][6]	MAIN[19][6]	MAIN[13][5]	MAIN[15][6]	HEX_V0_MUX[2]
							Source
0	0	0	0	0	0	1	HEX_H0[1]
0	0	0	0	0	1	0	HEX_H3[0]
0	0	0	0	1	0	0	HEX_V6[2]
0	0	0	1	0	0	0	LV[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V0_MUX[3]
Bits							Destination
MAIN[5][6]	MAIN[4][6]	MAIN[6][6]	MAIN[8][6]	MAIN[7][6]	MAIN[1][5]	MAIN[3][6]	HEX_V0_MUX[3]
							Source
0	0	0	0	0	0	1	HEX_H0[2]
0	0	0	0	0	1	0	HEX_H3[1]
0	0	0	0	1	0	0	HEX_V6[3]
0	0	0	1	0	0	0	LV[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V6_MUX[0]
Bits							Destination
MAIN[46][6]	MAIN[37][6]	MAIN[46][5]	MAIN[38][6]	MAIN[36][5]	MAIN[45][6]	MAIN[47][5]	HEX_V6_MUX[0]
							Source
0	0	0	0	0	0	1	HEX_H0[0]
0	0	0	0	0	1	0	HEX_H3[2]
0	0	0	0	1	0	0	HEX_V0[0]
0	0	0	1	0	0	0	LV[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V6_MUX[1]
Bits							Destination
MAIN[34][6]	MAIN[25][6]	MAIN[34][5]	MAIN[26][6]	MAIN[24][5]	MAIN[33][6]	MAIN[35][5]	HEX_V6_MUX[1]
							Source
0	0	0	0	0	0	1	HEX_H0[1]
0	0	0	0	0	1	0	HEX_H3[3]
0	0	0	0	1	0	0	HEX_V0[1]
0	0	0	1	0	0	0	LV[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V6_MUX[2]
Bits							Destination
MAIN[22][6]	MAIN[13][6]	MAIN[22][5]	MAIN[14][6]	MAIN[12][5]	MAIN[21][6]	MAIN[23][5]	HEX_V6_MUX[2]
							Source
0	0	0	0	0	0	1	HEX_H0[2]
0	0	0	0	0	1	0	HEX_H3[0]
0	0	0	0	1	0	0	HEX_V0[2]
0	0	0	1	0	0	0	LV[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes HEX_V6_MUX[3]
Bits							Destination
MAIN[10][6]	MAIN[1][6]	MAIN[10][5]	MAIN[2][6]	MAIN[0][5]	MAIN[9][6]	MAIN[11][5]	HEX_V6_MUX[3]
							Source
0	0	0	0	0	0	1	HEX_H0[3]
0	0	0	0	0	1	0	HEX_H3[1]
0	0	0	0	1	0	0	HEX_V0[3]
0	0	0	1	0	0	0	LV[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LH_MUX[0]
Bits	Destination
LH_MUX[0]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LH_MUX[1]
Bits	Destination
LH_MUX[1]
	Source
OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LH_MUX[2]
Bits	Destination
MAIN[16][12]	LH_MUX[2]
	Source
0	OUT_IO_I[3]
1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes LH_MUX[3]
Bits	Destination
MAIN[15][12]	LH_MUX[3]
	Source
0	OUT_IO_I[3]
1	OUT_IO_IQ[1]

virtex IO_W switchbox INT muxes LH_MUX[4]
Bits	Destination
MAIN[8][12]	LH_MUX[4]
	Source
0	OUT_IO_IQ[2]
1	OUT_IO_I[1]

virtex IO_W switchbox INT muxes LH_MUX[5]
Bits	Destination
MAIN[7][12]	LH_MUX[5]
	Source
0	OUT_IO_I[2]
1	OUT_IO_I[1]

virtex IO_W switchbox INT muxes LH_MUX[6]
Bits	Destination
MAIN[0][12]	LH_MUX[6]
	Source
0	off
1	OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes LH_MUX[7]
Bits	Destination
MAIN[31][12]	LH_MUX[7]
	Source
0	OUT_IO_I[1]
1	OUT_IO_IQ[2]

virtex IO_W switchbox INT muxes LH_MUX[8]
Bits	Destination
MAIN[32][12]	LH_MUX[8]
	Source
0	off
1	OUT_IO_I[2]

virtex IO_W switchbox INT muxes LH_MUX[9]
Bits	Destination
MAIN[39][12]	LH_MUX[9]
	Source
0	off
1	OUT_IO_I[2]

virtex IO_W switchbox INT muxes LH_MUX[10]
Bits	Destination
MAIN[40][12]	LH_MUX[10]
	Source
0	off
1	OUT_IO_IQ[3]

virtex IO_W switchbox INT muxes LH_MUX[11]
Bits	Destination
MAIN[47][12]	LH_MUX[11]
	Source
0	OUT_IO_IQ[1]
1	OUT_IO_I[3]

virtex IO_W switchbox INT muxes LV_MUX[0]
Bits									Destination
MAIN[4][15]	MAIN[9][12]	MAIN[1][15]	MAIN[7][15]	MAIN[14][15]	MAIN[11][15]	MAIN[12][15]	MAIN[3][15]	MAIN[0][15]	LV_MUX[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	1	SINGLE_E_BUF[5]
0	0	0	0	0	0	0	1	0	SINGLE_E_BUF[6]
0	0	0	0	0	0	1	0	0	SINGLE_E_BUF[10]
0	0	0	0	0	1	0	0	0	SINGLE_E_BUF[11]
0	0	0	0	1	0	0	0	0	SINGLE_E_BUF[17]
0	0	0	1	0	0	0	0	0	SINGLE_E_BUF[18]
0	0	1	0	0	0	0	0	0	SINGLE_E_BUF[22]
0	1	0	0	0	0	0	0	0	SINGLE_E_BUF[23]
1	0	0	0	0	0	0	0	1	OUT_IO_IQ[3]
1	0	0	0	0	0	0	1	0	OUT_IO_IQ[2]
1	0	0	0	0	0	1	0	0	OUT_IO_I[2]
1	0	0	0	1	0	0	0	0	OUT_IO_IQ[1]
1	0	0	1	0	0	0	0	0	OUT_IO_I[3]
1	0	1	0	0	0	0	0	0	OUT_IO_I[1]

virtex IO_W switchbox INT muxes LV_MUX[6]
Bits									Destination
MAIN[8][15]	MAIN[12][12]	MAIN[5][15]	MAIN[6][15]	MAIN[15][15]	MAIN[14][12]	MAIN[9][15]	MAIN[13][15]	MAIN[1][12]	LV_MUX[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	1	SINGLE_E_BUF[5]
0	0	0	0	0	0	0	1	0	SINGLE_E_BUF[6]
0	0	0	0	0	0	1	0	0	SINGLE_E_BUF[10]
0	0	0	0	0	1	0	0	0	SINGLE_E_BUF[11]
0	0	0	0	1	0	0	0	0	SINGLE_E_BUF[17]
0	0	0	1	0	0	0	0	0	SINGLE_E_BUF[18]
0	0	1	0	0	0	0	0	0	SINGLE_E_BUF[22]
0	1	0	0	0	0	0	0	0	SINGLE_E_BUF[23]
1	0	0	0	0	0	0	0	1	OUT_IO_IQ[3]
1	0	0	0	0	0	0	1	0	OUT_IO_IQ[2]
1	0	0	0	0	0	1	0	0	OUT_IO_I[2]
1	0	0	0	1	0	0	0	0	OUT_IO_IQ[1]
1	0	0	1	0	0	0	0	0	OUT_IO_I[3]
1	0	1	0	0	0	0	0	0	OUT_IO_I[1]

virtex IO_W switchbox INT muxes IMUX_TBUF_T[0]
Bits					Destination
MAIN[26][15]	MAIN[27][15]	MAIN[40][15]	MAIN[35][12]	MAIN[27][12]	IMUX_TBUF_T[0]
					Source
0	0	0	0	0	PULLUP
0	0	0	0	1	HEX_V6_BUF[1]
0	0	0	1	0	HEX_V5_BUF[1]
0	0	1	0	0	HEX_V1_BUF[1]
0	1	0	0	1	SINGLE_E_BUF[0]
0	1	0	1	0	SINGLE_E_BUF[7]
1	0	0	0	1	HEX_V2_BUF[1]
1	0	0	1	0	HEX_V3_BUF[1]
1	0	1	0	0	HEX_V4_BUF[1]
1	1	0	0	1	SINGLE_E_BUF[19]
1	1	0	1	0	SINGLE_E_BUF[12]

virtex IO_W switchbox INT muxes IMUX_TBUF_T[1]
Bits					Destination
MAIN[29][15]	MAIN[28][15]	MAIN[43][15]	MAIN[33][12]	MAIN[28][12]	IMUX_TBUF_T[1]
					Source
0	0	0	0	0	PULLUP
0	0	0	0	1	HEX_V6_BUF[1]
0	0	0	1	0	HEX_V5_BUF[1]
0	0	1	0	0	HEX_V1_BUF[1]
0	1	0	0	1	SINGLE_E_BUF[0]
0	1	0	1	0	SINGLE_E_BUF[7]
1	0	0	0	1	HEX_V2_BUF[1]
1	0	0	1	0	HEX_V3_BUF[1]
1	0	1	0	0	HEX_V4_BUF[1]
1	1	0	0	1	SINGLE_E_BUF[19]
1	1	0	1	0	SINGLE_E_BUF[12]

virtex IO_W switchbox INT muxes IMUX_TBUF_I[0]
Bits					Destination
MAIN[19][15]	MAIN[20][15]	MAIN[37][15]	MAIN[17][15]	MAIN[16][15]	IMUX_TBUF_I[0]
					Source
0	0	0	0	0	PULLUP
0	0	0	0	1	SINGLE_E_BUF[17]
0	0	0	1	0	SINGLE_E_BUF[18]
0	0	1	0	0	SINGLE_E_BUF[22]
0	1	0	0	1	OUT_IO_I[3]
0	1	0	1	0	OUT_IO_I[2]
0	1	1	0	0	SINGLE_E_BUF[23]
1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	0	OUT_IO_IQ[3]
1	1	0	1	0	OUT_IO_IQ[1]
1	1	1	0	0	OUT_IO_I[1]

virtex IO_W switchbox INT muxes IMUX_TBUF_I[1]
Bits					Destination
MAIN[22][15]	MAIN[21][15]	MAIN[38][15]	MAIN[39][15]	MAIN[24][15]	IMUX_TBUF_I[1]
					Source
0	0	0	0	0	PULLUP
0	0	0	0	1	SINGLE_E_BUF[5]
0	0	0	1	0	SINGLE_E_BUF[6]
0	0	1	0	0	SINGLE_E_BUF[11]
0	1	0	0	1	OUT_IO_I[2]
0	1	0	1	0	OUT_IO_I[3]
0	1	1	0	0	SINGLE_E_BUF[10]
1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	OUT_IO_IQ[3]
1	1	0	0	1	OUT_IO_IQ[1]
1	1	1	0	0	OUT_IO_I[1]

virtex IO_W switchbox INT muxes IMUX_IO_CLK[0]
Bits											Destination
MAIN[30][12]	MAIN[30][14]	MAIN[29][14]	MAIN[36][13]	MAIN[26][14]	MAIN[30][13]	MAIN[24][13]	MAIN[25][14]	MAIN[25][13]	MAIN[27][13]	MAIN[27][14]	IMUX_IO_CLK[0]
											Source
0	0	0	0	0	0	1	1	1	1	1	GCLK_LEAF[0]
0	0	0	0	0	1	0	1	1	1	1	GCLK_LEAF[1]
0	0	0	0	0	1	1	0	1	1	1	GCLK_LEAF[2]
0	0	0	0	0	1	1	1	0	1	1	GCLK_LEAF[3]
0	0	0	0	0	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	SINGLE_E_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	HEX_V1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	HEX_V4_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	SINGLE_E_BUF[9]
0	1	0	0	0	1	1	1	1	1	0	HEX_V6_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	SINGLE_E_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	HEX_V2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	HEX_V3_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	SINGLE_E_BUF[15]

virtex IO_W switchbox INT muxes IMUX_IO_CLK[1]
Bits											Destination
MAIN[28][14]	MAIN[31][14]	MAIN[28][13]	MAIN[33][13]	MAIN[25][12]	MAIN[24][14]	MAIN[31][13]	MAIN[34][13]	MAIN[26][13]	MAIN[32][13]	MAIN[29][13]	IMUX_IO_CLK[1]
											Source
0	0	0	0	0	0	1	1	1	1	1	GCLK_LEAF[0]
0	0	0	0	0	1	0	1	1	1	1	GCLK_LEAF[1]
0	0	0	0	0	1	1	0	1	1	1	GCLK_LEAF[2]
0	0	0	0	0	1	1	1	0	1	1	GCLK_LEAF[3]
0	0	0	0	0	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	SINGLE_E_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	HEX_V1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	HEX_V4_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	SINGLE_E_BUF[9]
0	1	0	0	0	1	1	1	1	1	0	HEX_V6_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	SINGLE_E_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	HEX_V2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	HEX_V3_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	SINGLE_E_BUF[15]

virtex IO_W switchbox INT muxes IMUX_IO_CLK[2]
Bits											Destination
MAIN[19][14]	MAIN[16][14]	MAIN[19][13]	MAIN[14][13]	MAIN[22][12]	MAIN[23][14]	MAIN[16][13]	MAIN[13][13]	MAIN[21][13]	MAIN[15][13]	MAIN[18][13]	IMUX_IO_CLK[2]
											Source
0	0	0	0	0	0	1	1	1	1	1	GCLK_LEAF[0]
0	0	0	0	0	1	0	1	1	1	1	GCLK_LEAF[1]
0	0	0	0	0	1	1	0	1	1	1	GCLK_LEAF[2]
0	0	0	0	0	1	1	1	0	1	1	GCLK_LEAF[3]
0	0	0	0	0	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	SINGLE_E_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	HEX_V1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	HEX_V4_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	SINGLE_E_BUF[9]
0	1	0	0	0	1	1	1	1	1	0	HEX_V6_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	SINGLE_E_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	HEX_V2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	HEX_V3_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	SINGLE_E_BUF[15]

virtex IO_W switchbox INT muxes IMUX_IO_CLK[3]
Bits											Destination
MAIN[17][12]	MAIN[17][14]	MAIN[18][14]	MAIN[11][13]	MAIN[21][14]	MAIN[17][13]	MAIN[23][13]	MAIN[22][14]	MAIN[22][13]	MAIN[20][13]	MAIN[20][14]	IMUX_IO_CLK[3]
											Source
0	0	0	0	0	0	1	1	1	1	1	GCLK_LEAF[0]
0	0	0	0	0	1	0	1	1	1	1	GCLK_LEAF[1]
0	0	0	0	0	1	1	0	1	1	1	GCLK_LEAF[2]
0	0	0	0	0	1	1	1	0	1	1	GCLK_LEAF[3]
0	0	0	0	0	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	SINGLE_E_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	HEX_V1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	HEX_V4_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	SINGLE_E_BUF[9]
0	1	0	0	0	1	1	1	1	1	0	HEX_V6_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	SINGLE_E_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	HEX_V2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	HEX_V3_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	SINGLE_E_BUF[15]

virtex IO_W switchbox INT muxes IMUX_IO_SR[0]
Bits						Destination
MAIN[29][10]	MAIN[30][10]	MAIN[31][10]	MAIN[33][9]	MAIN[32][11]	MAIN[33][11]	IMUX_IO_SR[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[4]
0	0	0	0	1	0	SINGLE_E_BUF[5]
0	0	0	1	0	0	SINGLE_E_BUF[6]
0	0	1	0	0	0	SINGLE_E_BUF[7]
0	1	0	0	0	1	HEX_V1_BUF[1]
0	1	0	0	1	0	HEX_V4_BUF[1]
1	1	0	0	0	1	HEX_V2_BUF[1]
1	1	0	0	1	0	HEX_V3_BUF[1]
1	1	0	1	0	0	HEX_V5_BUF[1]
1	1	1	0	0	0	HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_IO_SR[1]
Bits						Destination
MAIN[30][11]	MAIN[29][11]	MAIN[28][9]	MAIN[32][9]	MAIN[31][9]	MAIN[28][11]	IMUX_IO_SR[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[4]
0	0	0	0	1	0	SINGLE_E_BUF[5]
0	0	0	1	0	0	SINGLE_E_BUF[6]
0	0	1	0	0	0	SINGLE_E_BUF[7]
0	1	0	0	0	1	HEX_V1_BUF[1]
0	1	0	0	1	0	HEX_V4_BUF[1]
1	1	0	0	0	1	HEX_V2_BUF[1]
1	1	0	0	1	0	HEX_V3_BUF[1]
1	1	0	1	0	0	HEX_V5_BUF[1]
1	1	1	0	0	0	HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_IO_SR[2]
Bits						Destination
MAIN[35][11]	MAIN[36][11]	MAIN[37][10]	MAIN[38][9]	MAIN[36][9]	MAIN[37][11]	IMUX_IO_SR[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[4]
0	0	0	0	1	0	SINGLE_E_BUF[5]
0	0	0	1	0	0	SINGLE_E_BUF[6]
0	0	1	0	0	0	SINGLE_E_BUF[7]
0	1	0	0	0	1	HEX_V1_BUF[1]
0	1	0	0	1	0	HEX_V4_BUF[1]
1	1	0	0	0	1	HEX_V2_BUF[1]
1	1	0	0	1	0	HEX_V3_BUF[1]
1	1	0	1	0	0	HEX_V5_BUF[1]
1	1	1	0	0	0	HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_IO_SR[3]
Bits						Destination
MAIN[36][10]	MAIN[35][10]	MAIN[34][10]	MAIN[35][9]	MAIN[39][9]	MAIN[34][11]	IMUX_IO_SR[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[4]
0	0	0	0	1	0	SINGLE_E_BUF[5]
0	0	0	1	0	0	SINGLE_E_BUF[6]
0	0	1	0	0	0	SINGLE_E_BUF[7]
0	1	0	0	0	1	HEX_V1_BUF[1]
0	1	0	0	1	0	HEX_V4_BUF[1]
1	1	0	0	0	1	HEX_V2_BUF[1]
1	1	0	0	1	0	HEX_V3_BUF[1]
1	1	0	1	0	0	HEX_V5_BUF[1]
1	1	1	0	0	0	HEX_V6_BUF[1]

virtex IO_W switchbox INT muxes IMUX_IO_ICE[0]
Bits						Destination
MAIN[8][10]	MAIN[7][10]	MAIN[5][11]	MAIN[6][11]	MAIN[7][9]	MAIN[6][10]	IMUX_IO_ICE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[20]
0	0	0	0	1	0	SINGLE_E_BUF[21]
0	0	0	1	0	0	SINGLE_E_BUF[22]
0	0	1	0	0	0	SINGLE_E_BUF[23]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_ICE[1]
Bits						Destination
MAIN[7][11]	MAIN[8][11]	MAIN[9][11]	MAIN[4][9]	MAIN[5][9]	MAIN[9][10]	IMUX_IO_ICE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[20]
0	0	0	0	1	0	SINGLE_E_BUF[21]
0	0	0	1	0	0	SINGLE_E_BUF[22]
0	0	1	0	0	0	SINGLE_E_BUF[23]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_ICE[2]
Bits						Destination
MAIN[2][11]	MAIN[1][11]	MAIN[0][11]	MAIN[0][9]	MAIN[1][9]	MAIN[0][10]	IMUX_IO_ICE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[20]
0	0	0	0	1	0	SINGLE_E_BUF[21]
0	0	0	1	0	0	SINGLE_E_BUF[22]
0	0	1	0	0	0	SINGLE_E_BUF[23]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_ICE[3]
Bits						Destination
MAIN[1][10]	MAIN[2][10]	MAIN[3][11]	MAIN[4][11]	MAIN[2][9]	MAIN[3][10]	IMUX_IO_ICE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[20]
0	0	0	0	1	0	SINGLE_E_BUF[21]
0	0	0	1	0	0	SINGLE_E_BUF[22]
0	0	1	0	0	0	SINGLE_E_BUF[23]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_OCE[0]
Bits						Destination
MAIN[18][10]	MAIN[17][10]	MAIN[14][11]	MAIN[15][11]	MAIN[16][10]	MAIN[14][9]	IMUX_IO_OCE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[17]
0	0	0	0	1	0	SINGLE_E_BUF[16]
0	0	0	1	0	0	SINGLE_E_BUF[18]
0	0	1	0	0	0	SINGLE_E_BUF[19]
0	1	0	0	0	1	PCI_CE
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V5_BUF[3]
1	1	0	0	1	0	HEX_V6_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_OCE[1]
Bits						Destination
MAIN[17][11]	MAIN[18][11]	MAIN[19][11]	MAIN[16][9]	MAIN[19][9]	MAIN[15][9]	IMUX_IO_OCE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[17]
0	0	0	0	1	0	SINGLE_E_BUF[16]
0	0	0	1	0	0	SINGLE_E_BUF[18]
0	0	1	0	0	0	SINGLE_E_BUF[19]
0	1	0	0	0	1	PCI_CE
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V5_BUF[3]
1	1	0	0	1	0	HEX_V6_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_OCE[2]
Bits						Destination
MAIN[12][11]	MAIN[11][11]	MAIN[10][11]	MAIN[11][9]	MAIN[10][10]	MAIN[9][9]	IMUX_IO_OCE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[17]
0	0	0	0	1	0	SINGLE_E_BUF[16]
0	0	0	1	0	0	SINGLE_E_BUF[18]
0	0	1	0	0	0	SINGLE_E_BUF[19]
0	1	0	0	0	1	PCI_CE
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V5_BUF[3]
1	1	0	0	1	0	HEX_V6_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_OCE[3]
Bits						Destination
MAIN[11][10]	MAIN[12][10]	MAIN[13][11]	MAIN[8][9]	MAIN[13][10]	MAIN[12][9]	IMUX_IO_OCE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[17]
0	0	0	0	1	0	SINGLE_E_BUF[16]
0	0	0	1	0	0	SINGLE_E_BUF[18]
0	0	1	0	0	0	SINGLE_E_BUF[19]
0	1	0	0	0	1	PCI_CE
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V5_BUF[3]
1	1	0	0	1	0	HEX_V6_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_TCE[0]
Bits						Destination
MAIN[25][11]	MAIN[26][11]	MAIN[27][11]	MAIN[25][9]	MAIN[26][9]	MAIN[28][10]	IMUX_IO_TCE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[10]
0	0	0	0	1	0	SINGLE_E_BUF[11]
0	0	0	1	0	0	SINGLE_E_BUF[12]
0	0	1	0	0	0	SINGLE_E_BUF[13]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_TCE[1]
Bits						Destination
MAIN[27][10]	MAIN[26][10]	MAIN[24][11]	MAIN[31][11]	MAIN[27][9]	MAIN[24][10]	IMUX_IO_TCE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[10]
0	0	0	0	1	0	SINGLE_E_BUF[11]
0	0	0	1	0	0	SINGLE_E_BUF[12]
0	0	1	0	0	0	SINGLE_E_BUF[13]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_TCE[2]
Bits						Destination
MAIN[22][11]	MAIN[21][11]	MAIN[20][11]	MAIN[22][9]	MAIN[21][9]	MAIN[19][10]	IMUX_IO_TCE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[10]
0	0	0	0	1	0	SINGLE_E_BUF[11]
0	0	0	1	0	0	SINGLE_E_BUF[12]
0	0	1	0	0	0	SINGLE_E_BUF[13]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_TCE[3]
Bits						Destination
MAIN[20][10]	MAIN[21][10]	MAIN[23][11]	MAIN[16][11]	MAIN[20][9]	MAIN[23][10]	IMUX_IO_TCE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[10]
0	0	0	0	1	0	SINGLE_E_BUF[11]
0	0	0	1	0	0	SINGLE_E_BUF[12]
0	0	1	0	0	0	SINGLE_E_BUF[13]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_W switchbox INT muxes IMUX_IO_O[0]
Bits										Destination
MAIN[41][13]	MAIN[42][13]	MAIN[47][13]	MAIN[46][13]	MAIN[45][14]	MAIN[44][13]	MAIN[43][13]	MAIN[44][14]	MAIN[45][13]	MAIN[46][14]	IMUX_IO_O[0]
										Source
0	0	0	0	0	0	0	0	1	1	PULLUP
0	0	0	0	0	0	1	0	0	1	HEX_H0_BUF[0]
0	0	0	0	0	0	1	0	1	0	OMUX_W7
0	0	0	0	0	0	1	1	1	1	SINGLE_E_BUF[0]
0	0	0	0	0	1	0	0	0	1	HEX_H3_BUF[0]
0	0	0	0	0	1	0	0	1	0	OMUX_W6
0	0	0	0	0	1	0	1	1	1	SINGLE_E_BUF[1]
0	0	0	0	1	0	1	0	1	1	SINGLE_E_BUF[3]
0	0	0	0	1	1	0	0	1	1	SINGLE_E_BUF[2]
0	0	0	1	0	0	0	0	0	1	HEX_H1_BUF[0]
0	0	0	1	0	0	0	0	1	0	OUT_TBUF_W[2]
0	0	0	1	0	0	0	1	1	1	SINGLE_E_BUF[9]
0	0	0	1	1	0	0	0	1	1	SINGLE_E_BUF[4]
0	0	1	0	0	0	0	0	0	1	HEX_H2_BUF[0]
0	0	1	0	0	0	0	0	1	0	OUT_TBUF_W[3]
0	0	1	0	0	0	0	1	1	1	SINGLE_E_BUF[8]
0	0	1	0	1	0	0	0	1	1	SINGLE_E_BUF[5]
0	1	0	0	0	0	0	0	1	0	OUT_TBUF_W[0]
0	1	0	0	0	0	0	1	1	1	SINGLE_E_BUF[6]
0	1	0	0	1	0	0	0	1	1	SINGLE_E_BUF[10]
1	0	0	0	0	0	0	0	1	0	OUT_TBUF_W[1]
1	0	0	0	0	0	0	1	1	1	SINGLE_E_BUF[7]
1	0	0	0	1	0	0	0	1	1	SINGLE_E_BUF[11]

virtex IO_W switchbox INT muxes IMUX_IO_O[1]
Bits										Destination
MAIN[43][14]	MAIN[42][14]	MAIN[43][12]	MAIN[41][12]	MAIN[41][14]	MAIN[39][13]	MAIN[38][13]	MAIN[40][14]	MAIN[40][13]	MAIN[39][14]	IMUX_IO_O[1]
										Source
0	0	0	0	0	0	0	0	1	1	PULLUP
0	0	0	0	0	0	1	0	0	1	HEX_H2_BUF[1]
0	0	0	0	0	0	1	0	1	0	OMUX_W7
0	0	0	0	0	0	1	1	1	1	SINGLE_E_BUF[0]
0	0	0	0	0	1	0	0	0	1	HEX_H3_BUF[1]
0	0	0	0	0	1	0	0	1	0	OMUX_W6
0	0	0	0	0	1	0	1	1	1	SINGLE_E_BUF[1]
0	0	0	0	1	0	1	0	1	1	SINGLE_E_BUF[3]
0	0	0	0	1	1	0	0	1	1	SINGLE_E_BUF[2]
0	0	0	1	0	0	0	0	0	1	HEX_H1_BUF[1]
0	0	0	1	0	0	0	0	1	0	OUT_TBUF_W[2]
0	0	0	1	0	0	0	1	1	1	SINGLE_E_BUF[9]
0	0	0	1	1	0	0	0	1	1	SINGLE_E_BUF[4]
0	0	1	0	0	0	0	0	0	1	HEX_H0_BUF[1]
0	0	1	0	0	0	0	0	1	0	OUT_TBUF_W[3]
0	0	1	0	0	0	0	1	1	1	SINGLE_E_BUF[8]
0	0	1	0	1	0	0	0	1	1	SINGLE_E_BUF[5]
0	1	0	0	0	0	0	0	1	0	OUT_TBUF_W[0]
0	1	0	0	0	0	0	1	1	1	SINGLE_E_BUF[6]
0	1	0	0	1	0	0	0	1	1	SINGLE_E_BUF[10]
1	0	0	0	0	0	0	0	1	0	OUT_TBUF_W[1]
1	0	0	0	0	0	0	1	1	1	SINGLE_E_BUF[7]
1	0	0	0	1	0	0	0	1	1	SINGLE_E_BUF[11]

virtex IO_W switchbox INT muxes IMUX_IO_O[2]
Bits										Destination
MAIN[8][13]	MAIN[9][13]	MAIN[4][12]	MAIN[6][12]	MAIN[7][14]	MAIN[5][14]	MAIN[4][14]	MAIN[6][14]	MAIN[7][13]	MAIN[8][14]	IMUX_IO_O[2]
										Source
0	0	0	0	0	0	0	0	1	1	PULLUP
0	0	0	0	0	0	1	0	1	0	OUT_TBUF_W[1]
0	0	0	0	0	0	1	1	1	1	SINGLE_E_BUF[12]
0	0	0	0	0	1	0	0	1	0	OUT_TBUF_W[0]
0	0	0	0	0	1	0	1	1	1	SINGLE_E_BUF[13]
0	0	0	0	1	0	1	0	1	1	SINGLE_E_BUF[16]
0	0	0	0	1	1	0	0	1	1	SINGLE_E_BUF[17]
0	0	0	1	0	0	0	0	0	1	HEX_H1_BUF[2]
0	0	0	1	0	0	0	0	1	0	OUT_TBUF_W[2]
0	0	0	1	0	0	0	1	1	1	SINGLE_E_BUF[19]
0	0	0	1	1	0	0	0	1	1	SINGLE_E_BUF[14]
0	0	1	0	0	0	0	0	0	1	HEX_H0_BUF[2]
0	0	1	0	0	0	0	0	1	0	OUT_TBUF_W[3]
0	0	1	0	0	0	0	1	1	1	SINGLE_E_BUF[18]
0	0	1	0	1	0	0	0	1	1	SINGLE_E_BUF[15]
0	1	0	0	0	0	0	0	0	1	HEX_H2_BUF[2]
0	1	0	0	0	0	0	0	1	0	OMUX_W7
0	1	0	0	0	0	0	1	1	1	SINGLE_E_BUF[20]
0	1	0	0	1	0	0	0	1	1	SINGLE_E_BUF[23]
1	0	0	0	0	0	0	0	0	1	HEX_H3_BUF[2]
1	0	0	0	0	0	0	0	1	0	OMUX_W6
1	0	0	0	0	0	0	1	1	1	SINGLE_E_BUF[21]
1	0	0	0	1	0	0	0	1	1	SINGLE_E_BUF[22]

virtex IO_W switchbox INT muxes IMUX_IO_O[3]
Bits										Destination
MAIN[3][13]	MAIN[4][13]	MAIN[0][13]	MAIN[1][13]	MAIN[3][14]	MAIN[5][13]	MAIN[6][13]	MAIN[2][14]	MAIN[2][13]	MAIN[1][14]	IMUX_IO_O[3]
										Source
0	0	0	0	0	0	0	0	1	1	PULLUP
0	0	0	0	0	0	1	0	1	0	OUT_TBUF_W[1]
0	0	0	0	0	0	1	1	1	1	SINGLE_E_BUF[12]
0	0	0	0	0	1	0	0	1	0	OUT_TBUF_W[0]
0	0	0	0	0	1	0	1	1	1	SINGLE_E_BUF[13]
0	0	0	0	1	0	1	0	1	1	SINGLE_E_BUF[16]
0	0	0	0	1	1	0	0	1	1	SINGLE_E_BUF[17]
0	0	0	1	0	0	0	0	0	1	HEX_H1_BUF[3]
0	0	0	1	0	0	0	0	1	0	OUT_TBUF_W[2]
0	0	0	1	0	0	0	1	1	1	SINGLE_E_BUF[19]
0	0	0	1	1	0	0	0	1	1	SINGLE_E_BUF[14]
0	0	1	0	0	0	0	0	0	1	HEX_H2_BUF[3]
0	0	1	0	0	0	0	0	1	0	OUT_TBUF_W[3]
0	0	1	0	0	0	0	1	1	1	SINGLE_E_BUF[18]
0	0	1	0	1	0	0	0	1	1	SINGLE_E_BUF[15]
0	1	0	0	0	0	0	0	0	1	HEX_H0_BUF[3]
0	1	0	0	0	0	0	0	1	0	OMUX_W7
0	1	0	0	0	0	0	1	1	1	SINGLE_E_BUF[20]
0	1	0	0	1	0	0	0	1	1	SINGLE_E_BUF[23]
1	0	0	0	0	0	0	0	0	1	HEX_H3_BUF[3]
1	0	0	0	0	0	0	0	1	0	OMUX_W6
1	0	0	0	0	0	0	1	1	1	SINGLE_E_BUF[21]
1	0	0	0	1	0	0	0	1	1	SINGLE_E_BUF[22]

virtex IO_W switchbox INT muxes IMUX_IO_T[0]
Bits						Destination
MAIN[39][10]	MAIN[40][10]	MAIN[41][10]	MAIN[40][9]	MAIN[41][11]	MAIN[42][11]	IMUX_IO_T[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[0]
0	0	0	0	1	0	SINGLE_E_BUF[1]
0	0	0	1	0	0	SINGLE_E_BUF[2]
0	0	1	0	0	0	SINGLE_E_BUF[3]
0	1	0	0	0	1	HEX_V1_BUF[0]
0	1	0	0	1	0	HEX_V4_BUF[0]
1	1	0	0	0	1	HEX_V2_BUF[0]
1	1	0	0	1	0	HEX_V3_BUF[0]
1	1	0	1	0	0	HEX_V5_BUF[0]
1	1	1	0	0	0	HEX_V6_BUF[0]

virtex IO_W switchbox INT muxes IMUX_IO_T[1]
Bits						Destination
MAIN[40][11]	MAIN[39][11]	MAIN[38][10]	MAIN[42][9]	MAIN[43][9]	MAIN[38][11]	IMUX_IO_T[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[0]
0	0	0	0	1	0	SINGLE_E_BUF[1]
0	0	0	1	0	0	SINGLE_E_BUF[2]
0	0	1	0	0	0	SINGLE_E_BUF[3]
0	1	0	0	0	1	HEX_V1_BUF[0]
0	1	0	0	1	0	HEX_V4_BUF[0]
1	1	0	0	0	1	HEX_V2_BUF[0]
1	1	0	0	1	0	HEX_V3_BUF[0]
1	1	0	1	0	0	HEX_V5_BUF[0]
1	1	1	0	0	0	HEX_V6_BUF[0]

virtex IO_W switchbox INT muxes IMUX_IO_T[2]
Bits						Destination
MAIN[45][11]	MAIN[46][11]	MAIN[47][10]	MAIN[46][9]	MAIN[47][9]	MAIN[47][11]	IMUX_IO_T[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[0]
0	0	0	0	1	0	SINGLE_E_BUF[1]
0	0	0	1	0	0	SINGLE_E_BUF[2]
0	0	1	0	0	0	SINGLE_E_BUF[3]
0	1	0	0	0	1	HEX_V1_BUF[0]
0	1	0	0	1	0	HEX_V4_BUF[0]
1	1	0	0	0	1	HEX_V2_BUF[0]
1	1	0	0	1	0	HEX_V3_BUF[0]
1	1	0	1	0	0	HEX_V5_BUF[0]
1	1	1	0	0	0	HEX_V6_BUF[0]

virtex IO_W switchbox INT muxes IMUX_IO_T[3]
Bits						Destination
MAIN[46][10]	MAIN[45][10]	MAIN[44][10]	MAIN[45][9]	MAIN[43][11]	MAIN[44][11]	IMUX_IO_T[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_E_BUF[0]
0	0	0	0	1	0	SINGLE_E_BUF[1]
0	0	0	1	0	0	SINGLE_E_BUF[2]
0	0	1	0	0	0	SINGLE_E_BUF[3]
0	1	0	0	0	1	HEX_V1_BUF[0]
0	1	0	0	1	0	HEX_V4_BUF[0]
1	1	0	0	0	1	HEX_V2_BUF[0]
1	1	0	0	1	0	HEX_V3_BUF[0]
1	1	0	1	0	0	HEX_V5_BUF[0]
1	1	1	0	0	0	HEX_V6_BUF[0]

virtex IO_W switchbox INT muxes OMUX[0]
Bits			Destination
MAIN[30][15]	MAIN[41][15]	MAIN[33][15]	OMUX[0]
			Source
0	0	0	off
0	0	1	OUT_IO_I[1]
0	1	0	OUT_IO_I[2]
1	0	0	OUT_IO_I[3]

virtex IO_W switchbox INT muxes OMUX[1]
Bits			Destination
MAIN[32][15]	MAIN[34][15]	MAIN[42][15]	OMUX[1]
			Source
0	0	0	off
0	0	1	OUT_IO_I[1]
0	1	0	OUT_IO_I[2]
1	0	0	OUT_IO_I[3]

Bels TBUF

virtex IO_W bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	IMUX_TBUF_I[0] invert by !MAIN[18][15]	IMUX_TBUF_I[1] invert by !MAIN[23][15]
T	in	IMUX_TBUF_T[0] invert by MAIN[25][15]	IMUX_TBUF_T[1] invert by MAIN[31][15]

virtex IO_W bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
OUT_A	!MAIN[46][12]	!MAIN[45][15]
OUT_B	!MAIN[46][15]	!MAIN[38][12]

Bels TBUS_WE

virtex IO_W bel TBUS_WE pins
Pin	Direction	TBUS_WE
BUS0	out	OUT_TBUF_W[2]
BUS1	out	OUT_TBUF_W[3]
BUS2	out	OUT_TBUF_W[0]
BUS3	out	OUT_TBUF_W[1]

virtex IO_W bel TBUS_WE attribute bits
Attribute	TBUS_WE
JOINER	!MAIN[44][15]
JOINER_E	!MAIN[47][15]

Bels IOI

virtex IO_W bel IOI pins
Pin	Direction	IOI[0]	IOI[1]	IOI[2]	IOI[3]
ICLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[34][14]	IMUX_IO_CLK[2] invert by MAIN[13][14]	IMUX_IO_CLK[3] invert by MAIN[10][14]
OCLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[33][14]	IMUX_IO_CLK[2] invert by MAIN[14][14]	IMUX_IO_CLK[3] invert by MAIN[11][14]
TCLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[32][14]	IMUX_IO_CLK[2] invert by MAIN[15][14]	IMUX_IO_CLK[3] invert by MAIN[12][14]
SR	in	IMUX_IO_SR[0]	IMUX_IO_SR[1] invert by MAIN[33][10]	IMUX_IO_SR[2] invert by MAIN[34][9]	IMUX_IO_SR[3] invert by MAIN[37][9]
ICE	in	IMUX_IO_ICE[0]	IMUX_IO_ICE[1] invert by !MAIN[5][10]	IMUX_IO_ICE[2] invert by !MAIN[4][10]	IMUX_IO_ICE[3] invert by !MAIN[3][9]
OCE	in	IMUX_IO_OCE[0]	IMUX_IO_OCE[1] invert by !MAIN[14][10]	IMUX_IO_OCE[2] invert by !MAIN[13][9]	IMUX_IO_OCE[3] invert by !MAIN[10][9]
TCE	in	IMUX_IO_TCE[0]	IMUX_IO_TCE[1] invert by !MAIN[25][10]	IMUX_IO_TCE[2] invert by !MAIN[23][9]	IMUX_IO_TCE[3] invert by !MAIN[22][10]
O	in	IMUX_IO_O[0]	IMUX_IO_O[1] invert by !MAIN[38][14]	IMUX_IO_O[2] invert by !MAIN[9][14]	IMUX_IO_O[3] invert by !MAIN[0][14]
T	in	IMUX_IO_T[0]	IMUX_IO_T[1] invert by !MAIN[42][10]	IMUX_IO_T[2] invert by !MAIN[43][10]	IMUX_IO_T[3] invert by !MAIN[44][9]
I	out	OUT_IO_I[0]	OUT_IO_I[1]	OUT_IO_I[2]	OUT_IO_I[3]
IQ	out	OUT_IO_IQ[0]	OUT_IO_IQ[1]	OUT_IO_IQ[2]	OUT_IO_IQ[3]

virtex IO_W bel IOI attribute bits
Attribute	IOI[0]	IOI[1]	IOI[2]	IOI[3]
SHORTEN_JTAG_CHAIN	-	!MAIN[37][17]	!MAIN[28][17]	!MAIN[7][17]
FFI_INIT bit 0	-	MAIN[46][16]	MAIN[19][16]	MAIN[16][16]
FFI_READBACK bit 0	-	MAIN[45][17]	MAIN[20][17]	MAIN[15][17]
FFI_LATCH	-	MAIN[44][16]	MAIN[21][16]	MAIN[14][16]
FFI_SR_ENABLE	-	MAIN[43][16]	MAIN[22][16]	MAIN[13][16]
FFI_SR_SYNC	-	MAIN[47][16]	MAIN[18][16]	MAIN[17][16]
FFI_DELAY_ENABLE	-	MAIN[38][17]	MAIN[27][17]	MAIN[8][17]
I_DELAY_ENABLE	-	MAIN[45][16]	MAIN[20][16]	MAIN[15][16]
FFO_INIT bit 0	-	!MAIN[39][16]	!MAIN[26][16]	!MAIN[9][16]
FFO_READBACK bit 0	-	MAIN[39][17]	MAIN[26][17]	MAIN[9][17]
FFO_LATCH	-	MAIN[41][16]	MAIN[24][16]	MAIN[11][16]
FFO_SR_ENABLE	-	MAIN[42][16]	MAIN[23][16]	MAIN[12][16]
FFO_SR_SYNC	-	MAIN[38][16]	MAIN[27][16]	MAIN[8][16]
FFT_INIT bit 0	-	!MAIN[36][16]	!MAIN[29][16]	!MAIN[6][16]
FFT_READBACK bit 0	-	MAIN[35][17]	MAIN[30][17]	MAIN[5][17]
FFT_LATCH	-	MAIN[34][16]	MAIN[31][16]	MAIN[4][16]
FFT_SR_ENABLE	-	MAIN[33][16]	MAIN[32][16]	MAIN[3][16]
FFT_SR_SYNC	-	MAIN[37][16]	MAIN[28][16]	MAIN[7][16]
MUX_O	-	[enum: IO_MUX_O]	[enum: IO_MUX_O]	[enum: IO_MUX_O]
MUX_T	-	[enum: IO_MUX_T]	[enum: IO_MUX_T]	[enum: IO_MUX_T]

virtex IO_W enum IO_MUX_O
IOI[1].MUX_O	MAIN[40][16]
IOI[2].MUX_O	MAIN[25][16]
IOI[3].MUX_O	MAIN[10][16]
O	0
FFO	1

virtex IO_W enum IO_MUX_T
IOI[1].MUX_T	MAIN[35][16]
IOI[2].MUX_T	MAIN[30][16]
IOI[3].MUX_T	MAIN[5][16]
T	0
FFT	1

Bel wires

virtex IO_W bel wires
Wire	Pins
IMUX_TBUF_T[0]	TBUF[0].T
IMUX_TBUF_T[1]	TBUF[1].T
IMUX_TBUF_I[0]	TBUF[0].I
IMUX_TBUF_I[1]	TBUF[1].I
IMUX_IO_CLK[0]	IOI[0].ICLK, IOI[0].OCLK, IOI[0].TCLK
IMUX_IO_CLK[1]	IOI[1].ICLK, IOI[1].OCLK, IOI[1].TCLK
IMUX_IO_CLK[2]	IOI[2].ICLK, IOI[2].OCLK, IOI[2].TCLK
IMUX_IO_CLK[3]	IOI[3].ICLK, IOI[3].OCLK, IOI[3].TCLK
IMUX_IO_SR[0]	IOI[0].SR
IMUX_IO_SR[1]	IOI[1].SR
IMUX_IO_SR[2]	IOI[2].SR
IMUX_IO_SR[3]	IOI[3].SR
IMUX_IO_ICE[0]	IOI[0].ICE
IMUX_IO_ICE[1]	IOI[1].ICE
IMUX_IO_ICE[2]	IOI[2].ICE
IMUX_IO_ICE[3]	IOI[3].ICE
IMUX_IO_OCE[0]	IOI[0].OCE
IMUX_IO_OCE[1]	IOI[1].OCE
IMUX_IO_OCE[2]	IOI[2].OCE
IMUX_IO_OCE[3]	IOI[3].OCE
IMUX_IO_TCE[0]	IOI[0].TCE
IMUX_IO_TCE[1]	IOI[1].TCE
IMUX_IO_TCE[2]	IOI[2].TCE
IMUX_IO_TCE[3]	IOI[3].TCE
IMUX_IO_O[0]	IOI[0].O
IMUX_IO_O[1]	IOI[1].O
IMUX_IO_O[2]	IOI[2].O
IMUX_IO_O[3]	IOI[3].O
IMUX_IO_T[0]	IOI[0].T
IMUX_IO_T[1]	IOI[1].T
IMUX_IO_T[2]	IOI[2].T
IMUX_IO_T[3]	IOI[3].T
OUT_TBUF_W[0]	TBUS_WE.BUS2
OUT_TBUF_W[1]	TBUS_WE.BUS3
OUT_TBUF_W[2]	TBUS_WE.BUS0
OUT_TBUF_W[3]	TBUS_WE.BUS1
OUT_IO_I[0]	IOI[0].I
OUT_IO_I[1]	IOI[1].I
OUT_IO_I[2]	IOI[2].I
OUT_IO_I[3]	IOI[3].I
OUT_IO_IQ[0]	IOI[0].IQ
OUT_IO_IQ[1]	IOI[1].IQ
OUT_IO_IQ[2]	IOI[2].IQ
OUT_IO_IQ[3]	IOI[3].IQ

Bitstream

virtex IO_W rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B17	-	-	-	-	-	IOI[3]: FFT_READBACK bit 0	-	IOI[3]: ! SHORTEN_JTAG_CHAIN	IOI[3]: FFI_DELAY_ENABLE	IOI[3]: FFO_READBACK bit 0	-	-	-	-	-	IOI[3]: FFI_READBACK bit 0	-	-	-	-	IOI[2]: FFI_READBACK bit 0	-	-	-	-	-	IOI[2]: FFO_READBACK bit 0	IOI[2]: FFI_DELAY_ENABLE	IOI[2]: ! SHORTEN_JTAG_CHAIN	-	IOI[2]: FFT_READBACK bit 0	-	-	-	-	IOI[1]: FFT_READBACK bit 0	-	IOI[1]: ! SHORTEN_JTAG_CHAIN	IOI[1]: FFI_DELAY_ENABLE	IOI[1]: FFO_READBACK bit 0	-	-	-	-	-	IOI[1]: FFI_READBACK bit 0	-	-	-	-	-	-	-	-
B16	-	-	-	IOI[3]: FFT_SR_ENABLE	IOI[3]: FFT_LATCH	IOI[3]: MUX_T bit 0	IOI[3]: ! FFT_INIT bit 0	IOI[3]: FFT_SR_SYNC	IOI[3]: FFO_SR_SYNC	IOI[3]: ! FFO_INIT bit 0	IOI[3]: MUX_O bit 0	IOI[3]: FFO_LATCH	IOI[3]: FFO_SR_ENABLE	IOI[3]: FFI_SR_ENABLE	IOI[3]: FFI_LATCH	IOI[3]: I_DELAY_ENABLE	IOI[3]: FFI_INIT bit 0	IOI[3]: FFI_SR_SYNC	IOI[2]: FFI_SR_SYNC	IOI[2]: FFI_INIT bit 0	IOI[2]: I_DELAY_ENABLE	IOI[2]: FFI_LATCH	IOI[2]: FFI_SR_ENABLE	IOI[2]: FFO_SR_ENABLE	IOI[2]: FFO_LATCH	IOI[2]: MUX_O bit 0	IOI[2]: ! FFO_INIT bit 0	IOI[2]: FFO_SR_SYNC	IOI[2]: FFT_SR_SYNC	IOI[2]: ! FFT_INIT bit 0	IOI[2]: MUX_T bit 0	IOI[2]: FFT_LATCH	IOI[2]: FFT_SR_ENABLE	IOI[1]: FFT_SR_ENABLE	IOI[1]: FFT_LATCH	IOI[1]: MUX_T bit 0	IOI[1]: ! FFT_INIT bit 0	IOI[1]: FFT_SR_SYNC	IOI[1]: FFO_SR_SYNC	IOI[1]: ! FFO_INIT bit 0	IOI[1]: MUX_O bit 0	IOI[1]: FFO_LATCH	IOI[1]: FFO_SR_ENABLE	IOI[1]: FFI_SR_ENABLE	IOI[1]: FFI_LATCH	IOI[1]: I_DELAY_ENABLE	IOI[1]: FFI_INIT bit 0	IOI[1]: FFI_SR_SYNC	-	-	-	-	-	-
B15	INT: mux LV_MUX[0] bit 0	INT: mux LV_MUX[0] bit 6	INT: buffer LV[0] ← LV_MUX[0]	INT: mux LV_MUX[0] bit 1	INT: mux LV_MUX[0] bit 8	INT: mux LV_MUX[6] bit 6	INT: mux LV_MUX[6] bit 5	INT: mux LV_MUX[0] bit 5	INT: mux LV_MUX[6] bit 8	INT: mux LV_MUX[6] bit 2	INT: buffer LV[6] ← LV_MUX[6]	INT: mux LV_MUX[0] bit 3	INT: mux LV_MUX[0] bit 2	INT: mux LV_MUX[6] bit 1	INT: mux LV_MUX[0] bit 4	INT: mux LV_MUX[6] bit 4	INT: mux IMUX_TBUF_I[0] bit 0	INT: mux IMUX_TBUF_I[0] bit 1	TBUF[0]: !invert I	INT: mux IMUX_TBUF_I[0] bit 4	INT: mux IMUX_TBUF_I[0] bit 3	INT: mux IMUX_TBUF_I[1] bit 3	INT: mux IMUX_TBUF_I[1] bit 4	TBUF[1]: !invert I	INT: mux IMUX_TBUF_I[1] bit 0	TBUF[0]: invert T	INT: mux IMUX_TBUF_T[0] bit 4	INT: mux IMUX_TBUF_T[0] bit 3	INT: mux IMUX_TBUF_T[1] bit 3	INT: mux IMUX_TBUF_T[1] bit 4	INT: mux OMUX[0] bit 2	TBUF[1]: invert T	INT: mux OMUX[1] bit 2	INT: mux OMUX[0] bit 0	INT: mux OMUX[1] bit 1	-	-	INT: mux IMUX_TBUF_I[0] bit 2	INT: mux IMUX_TBUF_I[1] bit 2	INT: mux IMUX_TBUF_I[1] bit 1	INT: mux IMUX_TBUF_T[0] bit 2	INT: mux OMUX[0] bit 1	INT: mux OMUX[1] bit 0	INT: mux IMUX_TBUF_T[1] bit 2	TBUS_WE: ! JOINER	TBUF[1]: ! OUT_A	TBUF[0]: ! OUT_B	TBUS_WE: ! JOINER_E	-	-	-	-	-	-
B14	IOI[3]: !invert O	INT: mux IMUX_IO_O[3] bit 0	INT: mux IMUX_IO_O[3] bit 2	INT: mux IMUX_IO_O[3] bit 5	INT: mux IMUX_IO_O[2] bit 3	INT: mux IMUX_IO_O[2] bit 4	INT: mux IMUX_IO_O[2] bit 2	INT: mux IMUX_IO_O[2] bit 5	INT: mux IMUX_IO_O[2] bit 0	IOI[2]: !invert O	IOI[3]: invert ICLK	IOI[3]: invert OCLK	IOI[3]: invert TCLK	IOI[2]: invert ICLK	IOI[2]: invert OCLK	IOI[2]: invert TCLK	INT: mux IMUX_IO_CLK[2] bit 9	INT: mux IMUX_IO_CLK[3] bit 9	INT: mux IMUX_IO_CLK[3] bit 8	INT: mux IMUX_IO_CLK[2] bit 10	INT: mux IMUX_IO_CLK[3] bit 0	INT: mux IMUX_IO_CLK[3] bit 6	INT: mux IMUX_IO_CLK[3] bit 3	INT: mux IMUX_IO_CLK[2] bit 5	INT: mux IMUX_IO_CLK[1] bit 5	INT: mux IMUX_IO_CLK[0] bit 3	INT: mux IMUX_IO_CLK[0] bit 6	INT: mux IMUX_IO_CLK[0] bit 0	INT: mux IMUX_IO_CLK[1] bit 10	INT: mux IMUX_IO_CLK[0] bit 8	INT: mux IMUX_IO_CLK[0] bit 9	INT: mux IMUX_IO_CLK[1] bit 9	IOI[1]: invert TCLK	IOI[1]: invert OCLK	IOI[1]: invert ICLK	-	-	-	IOI[1]: !invert O	INT: mux IMUX_IO_O[1] bit 0	INT: mux IMUX_IO_O[1] bit 2	INT: mux IMUX_IO_O[1] bit 5	INT: mux IMUX_IO_O[1] bit 8	INT: mux IMUX_IO_O[1] bit 9	INT: mux IMUX_IO_O[0] bit 2	INT: mux IMUX_IO_O[0] bit 5	INT: mux IMUX_IO_O[0] bit 0	-	-	-	-	-	-	-
B13	INT: mux IMUX_IO_O[3] bit 7	INT: mux IMUX_IO_O[3] bit 6	INT: mux IMUX_IO_O[3] bit 1	INT: mux IMUX_IO_O[3] bit 9	INT: mux IMUX_IO_O[3] bit 8	INT: mux IMUX_IO_O[3] bit 4	INT: mux IMUX_IO_O[3] bit 3	INT: mux IMUX_IO_O[2] bit 1	INT: mux IMUX_IO_O[2] bit 9	INT: mux IMUX_IO_O[2] bit 8	-	INT: mux IMUX_IO_CLK[3] bit 7	-	INT: mux IMUX_IO_CLK[2] bit 3	INT: mux IMUX_IO_CLK[2] bit 7	INT: mux IMUX_IO_CLK[2] bit 1	INT: mux IMUX_IO_CLK[2] bit 4	INT: mux IMUX_IO_CLK[3] bit 5	INT: mux IMUX_IO_CLK[2] bit 0	INT: mux IMUX_IO_CLK[2] bit 8	INT: mux IMUX_IO_CLK[3] bit 1	INT: mux IMUX_IO_CLK[2] bit 2	INT: mux IMUX_IO_CLK[3] bit 2	INT: mux IMUX_IO_CLK[3] bit 4	INT: mux IMUX_IO_CLK[0] bit 4	INT: mux IMUX_IO_CLK[0] bit 2	INT: mux IMUX_IO_CLK[1] bit 2	INT: mux IMUX_IO_CLK[0] bit 1	INT: mux IMUX_IO_CLK[1] bit 8	INT: mux IMUX_IO_CLK[1] bit 0	INT: mux IMUX_IO_CLK[0] bit 5	INT: mux IMUX_IO_CLK[1] bit 4	INT: mux IMUX_IO_CLK[1] bit 1	INT: mux IMUX_IO_CLK[1] bit 7	INT: mux IMUX_IO_CLK[1] bit 3	-	INT: mux IMUX_IO_CLK[0] bit 7	-	INT: mux IMUX_IO_O[1] bit 3	INT: mux IMUX_IO_O[1] bit 4	INT: mux IMUX_IO_O[1] bit 1	INT: mux IMUX_IO_O[0] bit 9	INT: mux IMUX_IO_O[0] bit 8	INT: mux IMUX_IO_O[0] bit 3	INT: mux IMUX_IO_O[0] bit 4	INT: mux IMUX_IO_O[0] bit 1	INT: mux IMUX_IO_O[0] bit 6	INT: mux IMUX_IO_O[0] bit 7	-	-	-	-	-	-
B12	INT: mux LH_MUX[6] bit 0	INT: mux LV_MUX[6] bit 0	INT: buffer LH[6] ← LH_MUX[6]	-	INT: mux IMUX_IO_O[2] bit 7	INT: buffer LH[5] ← LH_MUX[5]	INT: mux IMUX_IO_O[2] bit 6	INT: mux LH_MUX[5] bit 0	INT: mux LH_MUX[4] bit 0	INT: mux LV_MUX[0] bit 7	INT: buffer LH[4] ← LH_MUX[4]	-	INT: mux LV_MUX[6] bit 7	INT: buffer LH[3] ← LH_MUX[3]	INT: mux LV_MUX[6] bit 3	INT: mux LH_MUX[3] bit 0	INT: mux LH_MUX[2] bit 0	INT: mux IMUX_IO_CLK[3] bit 10	INT: buffer LH[2] ← LH_MUX[2]	-	-	INT: buffer LH[1] ← LH_MUX[1]	INT: mux IMUX_IO_CLK[2] bit 6	-	-	INT: mux IMUX_IO_CLK[1] bit 6	INT: buffer LH[0] ← LH_MUX[0]	INT: mux IMUX_TBUF_T[0] bit 0	INT: mux IMUX_TBUF_T[1] bit 0	INT: buffer LH[7] ← LH_MUX[7]	INT: mux IMUX_IO_CLK[0] bit 10	INT: mux LH_MUX[7] bit 0	INT: mux LH_MUX[8] bit 0	INT: mux IMUX_TBUF_T[1] bit 1	INT: buffer LH[8] ← LH_MUX[8]	INT: mux IMUX_TBUF_T[0] bit 1	-	INT: buffer LH[9] ← LH_MUX[9]	TBUF[1]: ! OUT_B	INT: mux LH_MUX[9] bit 0	INT: mux LH_MUX[10] bit 0	INT: mux IMUX_IO_O[1] bit 6	INT: buffer LH[10] ← LH_MUX[10]	INT: mux IMUX_IO_O[1] bit 7	-	INT: buffer LH[11] ← LH_MUX[11]	TBUF[0]: ! OUT_A	INT: mux LH_MUX[11] bit 0	-	-	-	-	-	-
B11	INT: mux IMUX_IO_ICE[2] bit 3	INT: mux IMUX_IO_ICE[2] bit 4	INT: mux IMUX_IO_ICE[2] bit 5	INT: mux IMUX_IO_ICE[3] bit 3	INT: mux IMUX_IO_ICE[3] bit 2	INT: mux IMUX_IO_ICE[0] bit 3	INT: mux IMUX_IO_ICE[0] bit 2	INT: mux IMUX_IO_ICE[1] bit 5	INT: mux IMUX_IO_ICE[1] bit 4	INT: mux IMUX_IO_ICE[1] bit 3	INT: mux IMUX_IO_OCE[2] bit 3	INT: mux IMUX_IO_OCE[2] bit 4	INT: mux IMUX_IO_OCE[2] bit 5	INT: mux IMUX_IO_OCE[3] bit 3	INT: mux IMUX_IO_OCE[0] bit 3	INT: mux IMUX_IO_OCE[0] bit 2	INT: mux IMUX_IO_TCE[3] bit 2	INT: mux IMUX_IO_OCE[1] bit 5	INT: mux IMUX_IO_OCE[1] bit 4	INT: mux IMUX_IO_OCE[1] bit 3	INT: mux IMUX_IO_TCE[2] bit 3	INT: mux IMUX_IO_TCE[2] bit 4	INT: mux IMUX_IO_TCE[2] bit 5	INT: mux IMUX_IO_TCE[3] bit 3	INT: mux IMUX_IO_TCE[1] bit 3	INT: mux IMUX_IO_TCE[0] bit 5	INT: mux IMUX_IO_TCE[0] bit 4	INT: mux IMUX_IO_TCE[0] bit 3	INT: mux IMUX_IO_SR[1] bit 0	INT: mux IMUX_IO_SR[1] bit 4	INT: mux IMUX_IO_SR[1] bit 5	INT: mux IMUX_IO_TCE[1] bit 2	INT: mux IMUX_IO_SR[0] bit 1	INT: mux IMUX_IO_SR[0] bit 0	INT: mux IMUX_IO_SR[3] bit 0	INT: mux IMUX_IO_SR[2] bit 5	INT: mux IMUX_IO_SR[2] bit 4	INT: mux IMUX_IO_SR[2] bit 0	INT: mux IMUX_IO_T[1] bit 0	INT: mux IMUX_IO_T[1] bit 4	INT: mux IMUX_IO_T[1] bit 5	INT: mux IMUX_IO_T[0] bit 1	INT: mux IMUX_IO_T[0] bit 0	INT: mux IMUX_IO_T[3] bit 1	INT: mux IMUX_IO_T[3] bit 0	INT: mux IMUX_IO_T[2] bit 5	INT: mux IMUX_IO_T[2] bit 4	INT: mux IMUX_IO_T[2] bit 0	-	-	-	-	-	-
B10	INT: mux IMUX_IO_ICE[2] bit 0	INT: mux IMUX_IO_ICE[3] bit 5	INT: mux IMUX_IO_ICE[3] bit 4	INT: mux IMUX_IO_ICE[3] bit 0	IOI[2]: !invert ICE	IOI[1]: !invert ICE	INT: mux IMUX_IO_ICE[0] bit 0	INT: mux IMUX_IO_ICE[0] bit 4	INT: mux IMUX_IO_ICE[0] bit 5	INT: mux IMUX_IO_ICE[1] bit 0	INT: mux IMUX_IO_OCE[2] bit 1	INT: mux IMUX_IO_OCE[3] bit 5	INT: mux IMUX_IO_OCE[3] bit 4	INT: mux IMUX_IO_OCE[3] bit 1	IOI[1]: !invert OCE	-	INT: mux IMUX_IO_OCE[0] bit 1	INT: mux IMUX_IO_OCE[0] bit 4	INT: mux IMUX_IO_OCE[0] bit 5	INT: mux IMUX_IO_TCE[2] bit 0	INT: mux IMUX_IO_TCE[3] bit 5	INT: mux IMUX_IO_TCE[3] bit 4	IOI[3]: !invert TCE	INT: mux IMUX_IO_TCE[3] bit 0	INT: mux IMUX_IO_TCE[1] bit 0	IOI[1]: !invert TCE	INT: mux IMUX_IO_TCE[1] bit 4	INT: mux IMUX_IO_TCE[1] bit 5	INT: mux IMUX_IO_TCE[0] bit 0	INT: mux IMUX_IO_SR[0] bit 5	INT: mux IMUX_IO_SR[0] bit 4	INT: mux IMUX_IO_SR[0] bit 3	-	IOI[1]: invert SR	INT: mux IMUX_IO_SR[3] bit 3	INT: mux IMUX_IO_SR[3] bit 4	INT: mux IMUX_IO_SR[3] bit 5	INT: mux IMUX_IO_SR[2] bit 3	INT: mux IMUX_IO_T[1] bit 3	INT: mux IMUX_IO_T[0] bit 5	INT: mux IMUX_IO_T[0] bit 4	INT: mux IMUX_IO_T[0] bit 3	IOI[1]: !invert T	IOI[2]: !invert T	INT: mux IMUX_IO_T[3] bit 3	INT: mux IMUX_IO_T[3] bit 4	INT: mux IMUX_IO_T[3] bit 5	INT: mux IMUX_IO_T[2] bit 3	-	-	-	-	-	-
B9	INT: mux IMUX_IO_ICE[2] bit 2	INT: mux IMUX_IO_ICE[2] bit 1	INT: mux IMUX_IO_ICE[3] bit 1	IOI[3]: !invert ICE	INT: mux IMUX_IO_ICE[1] bit 2	INT: mux IMUX_IO_ICE[1] bit 1	-	INT: mux IMUX_IO_ICE[0] bit 1	INT: mux IMUX_IO_OCE[3] bit 2	INT: mux IMUX_IO_OCE[2] bit 0	IOI[3]: !invert OCE	INT: mux IMUX_IO_OCE[2] bit 2	INT: mux IMUX_IO_OCE[3] bit 0	IOI[2]: !invert OCE	INT: mux IMUX_IO_OCE[0] bit 0	INT: mux IMUX_IO_OCE[1] bit 0	INT: mux IMUX_IO_OCE[1] bit 2	-	-	INT: mux IMUX_IO_OCE[1] bit 1	INT: mux IMUX_IO_TCE[3] bit 1	INT: mux IMUX_IO_TCE[2] bit 1	INT: mux IMUX_IO_TCE[2] bit 2	IOI[2]: !invert TCE	-	INT: mux IMUX_IO_TCE[0] bit 2	INT: mux IMUX_IO_TCE[0] bit 1	INT: mux IMUX_IO_TCE[1] bit 1	INT: mux IMUX_IO_SR[1] bit 3	-	-	INT: mux IMUX_IO_SR[1] bit 1	INT: mux IMUX_IO_SR[1] bit 2	INT: mux IMUX_IO_SR[0] bit 2	IOI[2]: invert SR	INT: mux IMUX_IO_SR[3] bit 2	INT: mux IMUX_IO_SR[2] bit 1	IOI[3]: invert SR	INT: mux IMUX_IO_SR[2] bit 2	INT: mux IMUX_IO_SR[3] bit 1	INT: mux IMUX_IO_T[0] bit 2	-	INT: mux IMUX_IO_T[1] bit 2	INT: mux IMUX_IO_T[1] bit 1	IOI[3]: !invert T	INT: mux IMUX_IO_T[3] bit 2	INT: mux IMUX_IO_T[2] bit 2	INT: mux IMUX_IO_T[2] bit 1	-	-	-	-	-	-
B8	INT: pass SINGLE_E[23] ← HEX_V0[3]	INT: pass SINGLE_E[22] ← HEX_V3[3]	INT: pass SINGLE_E[22] ← OUT_IO_IQ[1]	INT: pass SINGLE_E[21] ← HEX_V6[3]	INT: pass SINGLE_E[21] ← OUT_IO_IQ[2]	INT: pass SINGLE_E[21] ← OUT_TBUF_W[0]	INT: pass SINGLE_E[20] ← OUT_IO_IQ[3]	INT: pass SINGLE_E[20] ← HEX_V0[3]	-	INT: pass SINGLE_E[19] ← HEX_V3[3]	INT: pass SINGLE_E[18] ← OUT_IO_I[1]	INT: pass SINGLE_E[18] ← OUT_TBUF_W[0]	INT: pass SINGLE_E[17] ← HEX_V0[2]	INT: pass SINGLE_E[16] ← HEX_V3[2]	INT: pass SINGLE_E[16] ← OUT_IO_I[3]	INT: pass SINGLE_E[15] ← HEX_V6[2]	-	INT: pass SINGLE_E[15] ← OUT_TBUF_W[1]	INT: pass SINGLE_E[14] ← OUT_IO_IQ[1]	INT: pass SINGLE_E[14] ← HEX_V0[2]	INT: pass SINGLE_E[13] ← OUT_IO_IQ[2]	INT: pass SINGLE_E[13] ← HEX_V3[2]	INT: pass SINGLE_E[12] ← OUT_IO_IQ[3]	INT: pass SINGLE_E[12] ← OUT_TBUF_W[1]	INT: pass SINGLE_E[11] ← HEX_V0[1]	INT: pass SINGLE_E[10] ← HEX_V3[1]	INT: pass SINGLE_E[10] ← OUT_IO_I[1]	INT: pass SINGLE_E[9] ← HEX_V6[1]	INT: pass SINGLE_E[9] ← OUT_IO_I[2]	INT: pass SINGLE_E[9] ← OUT_TBUF_W[2]	INT: pass SINGLE_E[8] ← OUT_IO_I[3]	INT: pass SINGLE_E[8] ← HEX_V0[1]	-	INT: pass SINGLE_E[7] ← HEX_V3[1]	INT: pass SINGLE_E[6] ← OUT_IO_IQ[1]	INT: pass SINGLE_E[6] ← OUT_TBUF_W[2]	INT: pass SINGLE_E[5] ← HEX_V0[0]	INT: pass SINGLE_E[4] ← HEX_V3[0]	INT: pass SINGLE_E[4] ← OUT_IO_IQ[3]	INT: pass SINGLE_E[3] ← HEX_V6[0]	-	INT: pass SINGLE_E[3] ← OUT_TBUF_W[3]	INT: pass SINGLE_E[2] ← OUT_IO_I[1]	INT: pass SINGLE_E[2] ← HEX_V0[0]	INT: pass SINGLE_E[1] ← OUT_IO_I[2]	INT: pass SINGLE_E[1] ← HEX_V3[0]	INT: pass SINGLE_E[0] ← OUT_IO_I[3]	INT: pass SINGLE_E[0] ← OUT_TBUF_W[3]	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	INT: pass SINGLE_E[18] ← HEX_V6[3]	INT: pass SINGLE_E[17] ← OUT_IO_I[2]	-	-	-	-	-	-	-	-	-	-	INT: pass SINGLE_E[12] ← HEX_V6[2]	-	-	-	-	-	-	-	-	-	-	-	INT: pass SINGLE_E[6] ← HEX_V6[1]	INT: pass SINGLE_E[5] ← OUT_IO_IQ[2]	-	-	-	-	-	-	-	-	-	-	INT: pass SINGLE_E[0] ← HEX_V6[0]	-	-	-	-	-	-
B6	INT: buffer HEX_V0[3] ← HEX_V0_MUX[3]	INT: mux HEX_V6_MUX[3] bit 5	INT: mux HEX_V6_MUX[3] bit 3	INT: mux HEX_V0_MUX[3] bit 0	INT: mux HEX_V0_MUX[3] bit 5	INT: mux HEX_V0_MUX[3] bit 6	INT: mux HEX_V0_MUX[3] bit 4	INT: mux HEX_V0_MUX[3] bit 2	INT: mux HEX_V0_MUX[3] bit 3	INT: mux HEX_V6_MUX[3] bit 1	INT: mux HEX_V6_MUX[3] bit 6	INT: buffer HEX_V6[3] ← HEX_V6_MUX[3]	INT: buffer HEX_V0[2] ← HEX_V0_MUX[2]	INT: mux HEX_V6_MUX[2] bit 5	INT: mux HEX_V6_MUX[2] bit 3	INT: mux HEX_V0_MUX[2] bit 0	INT: mux HEX_V0_MUX[2] bit 5	INT: mux HEX_V0_MUX[2] bit 6	INT: mux HEX_V0_MUX[2] bit 4	INT: mux HEX_V0_MUX[2] bit 2	INT: mux HEX_V0_MUX[2] bit 3	INT: mux HEX_V6_MUX[2] bit 1	INT: mux HEX_V6_MUX[2] bit 6	INT: buffer HEX_V6[2] ← HEX_V6_MUX[2]	INT: buffer HEX_V0[1] ← HEX_V0_MUX[1]	INT: mux HEX_V6_MUX[1] bit 5	INT: mux HEX_V6_MUX[1] bit 3	INT: mux HEX_V0_MUX[1] bit 0	INT: mux HEX_V0_MUX[1] bit 5	INT: mux HEX_V0_MUX[1] bit 6	INT: mux HEX_V0_MUX[1] bit 4	INT: mux HEX_V0_MUX[1] bit 2	INT: mux HEX_V0_MUX[1] bit 3	INT: mux HEX_V6_MUX[1] bit 1	INT: mux HEX_V6_MUX[1] bit 6	INT: buffer HEX_V6[1] ← HEX_V6_MUX[1]	INT: buffer HEX_V0[0] ← HEX_V0_MUX[0]	INT: mux HEX_V6_MUX[0] bit 5	INT: mux HEX_V6_MUX[0] bit 3	INT: mux HEX_V0_MUX[0] bit 0	INT: mux HEX_V0_MUX[0] bit 5	INT: mux HEX_V0_MUX[0] bit 6	INT: mux HEX_V0_MUX[0] bit 4	INT: mux HEX_V0_MUX[0] bit 2	INT: mux HEX_V0_MUX[0] bit 3	INT: mux HEX_V6_MUX[0] bit 1	INT: mux HEX_V6_MUX[0] bit 6	INT: buffer HEX_V6[0] ← HEX_V6_MUX[0]	-	-	-	-	-	-
B5	INT: mux HEX_V6_MUX[3] bit 2	INT: mux HEX_V0_MUX[3] bit 1	-	-	-	-	-	-	-	-	INT: mux HEX_V6_MUX[3] bit 4	INT: mux HEX_V6_MUX[3] bit 0	INT: mux HEX_V6_MUX[2] bit 2	INT: mux HEX_V0_MUX[2] bit 1	-	-	-	-	-	-	-	-	INT: mux HEX_V6_MUX[2] bit 4	INT: mux HEX_V6_MUX[2] bit 0	INT: mux HEX_V6_MUX[1] bit 2	INT: mux HEX_V0_MUX[1] bit 1	-	-	-	-	-	-	-	-	INT: mux HEX_V6_MUX[1] bit 4	INT: mux HEX_V6_MUX[1] bit 0	INT: mux HEX_V6_MUX[0] bit 2	INT: mux HEX_V0_MUX[0] bit 1	-	-	-	-	-	-	-	-	INT: mux HEX_V6_MUX[0] bit 4	INT: mux HEX_V6_MUX[0] bit 0	-	-	-	-	-	-
B4	INT: buffer HEX_H0[3] ← HEX_H0_MUX[3]	INT: mux HEX_H1_MUX[3] bit 3	INT: mux HEX_H0_MUX[3] bit 1	INT: buffer HEX_H1[3] ← HEX_H1_MUX[3]	INT: buffer HEX_H2[3] ← HEX_H2_MUX[3]	-	-	INT: buffer HEX_H3[3] ← HEX_H3_MUX[3]	INT: buffer HEX_H4[3] ← HEX_H4_MUX[3]	-	-	INT: buffer HEX_H5[3] ← HEX_H5_MUX[3]	INT: buffer HEX_H5[2] ← HEX_H5_MUX[2]	-	-	INT: buffer HEX_H4[2] ← HEX_H4_MUX[2]	INT: buffer HEX_H3[2] ← HEX_H3_MUX[2]	-	-	INT: buffer HEX_H2[2] ← HEX_H2_MUX[2]	INT: buffer HEX_H1[2] ← HEX_H1_MUX[2]	INT: mux HEX_H0_MUX[2] bit 3	INT: mux HEX_H1_MUX[2] bit 2	INT: buffer HEX_H0[2] ← HEX_H0_MUX[2]	INT: buffer HEX_H0[1] ← HEX_H0_MUX[1]	INT: mux HEX_H1_MUX[1] bit 2	INT: mux HEX_H0_MUX[1] bit 3	INT: buffer HEX_H1[1] ← HEX_H1_MUX[1]	INT: buffer HEX_H2[1] ← HEX_H2_MUX[1]	-	-	INT: buffer HEX_H3[1] ← HEX_H3_MUX[1]	INT: buffer HEX_H4[1] ← HEX_H4_MUX[1]	-	-	INT: buffer HEX_H5[1] ← HEX_H5_MUX[1]	INT: buffer HEX_H5[0] ← HEX_H5_MUX[0]	-	-	INT: buffer HEX_H4[0] ← HEX_H4_MUX[0]	INT: buffer HEX_H3[0] ← HEX_H3_MUX[0]	-	-	INT: buffer HEX_H2[0] ← HEX_H2_MUX[0]	INT: buffer HEX_H1[0] ← HEX_H1_MUX[0]	INT: mux HEX_H0_MUX[0] bit 2	INT: mux HEX_H1_MUX[0] bit 1	INT: buffer HEX_H0[0] ← HEX_H0_MUX[0]	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	INT: mux HEX_H0_MUX[3] bit 0	INT: mux HEX_H0_MUX[3] bit 5	INT: mux HEX_H0_MUX[3] bit 4	INT: mux HEX_H1_MUX[3] bit 0	INT: mux HEX_H2_MUX[3] bit 2	INT: mux HEX_H3_MUX[3] bit 2	INT: mux HEX_H3_MUX[3] bit 1	INT: mux HEX_H3_MUX[3] bit 0	INT: mux HEX_H4_MUX[3] bit 2	INT: mux HEX_H5_MUX[3] bit 2	-	INT: mux HEX_H5_MUX[3] bit 0	INT: mux HEX_H5_MUX[2] bit 0	INT: mux HEX_H5_MUX[2] bit 1	-	-	INT: mux HEX_H3_MUX[2] bit 0	INT: mux HEX_H3_MUX[2] bit 1	INT: mux HEX_H3_MUX[2] bit 3	INT: mux HEX_H2_MUX[2] bit 3	INT: mux HEX_H1_MUX[2] bit 0	-	INT: mux HEX_H0_MUX[2] bit 4	INT: mux HEX_H0_MUX[2] bit 0	INT: mux HEX_H0_MUX[1] bit 0	INT: mux HEX_H0_MUX[1] bit 5	INT: mux HEX_H0_MUX[1] bit 4	INT: mux HEX_H1_MUX[1] bit 0	INT: mux HEX_H2_MUX[1] bit 1	INT: mux HEX_H3_MUX[1] bit 1	INT: mux HEX_H3_MUX[1] bit 2	INT: mux HEX_H3_MUX[1] bit 0	INT: mux HEX_H4_MUX[1] bit 2	INT: mux HEX_H5_MUX[1] bit 2	-	INT: mux HEX_H5_MUX[1] bit 0	INT: mux HEX_H5_MUX[0] bit 0	INT: mux HEX_H5_MUX[0] bit 1	-	-	INT: mux HEX_H3_MUX[0] bit 0	INT: mux HEX_H3_MUX[0] bit 1	INT: mux HEX_H3_MUX[0] bit 3	INT: mux HEX_H2_MUX[0] bit 3	INT: mux HEX_H1_MUX[0] bit 0	-	INT: mux HEX_H0_MUX[0] bit 4	INT: mux HEX_H0_MUX[0] bit 0	-	-	-	-	-	-
B1	INT: mux HEX_E0[3] bit 3	INT: mux HEX_E0[3] bit 0	INT: mux HEX_E1[3] bit 0	INT: mux HEX_E1[3] bit 1	INT: mux HEX_E0[3] bit 1	INT: mux HEX_E0[3] bit 2	INT: mux HEX_E1[3] bit 2	INT: mux HEX_E1[3] bit 5	INT: mux HEX_E0[3] bit 5	INT: mux HEX_E0[3] bit 4	INT: mux HEX_E1[3] bit 4	INT: mux HEX_E1[3] bit 3	INT: mux HEX_E0[1] bit 3	INT: mux HEX_E0[1] bit 1	INT: mux HEX_E1[1] bit 1	INT: mux HEX_E1[1] bit 2	INT: mux HEX_E0[1] bit 2	INT: mux HEX_E0[1] bit 0	INT: mux HEX_E1[1] bit 0	INT: mux HEX_E1[1] bit 5	INT: mux HEX_E0[1] bit 5	INT: mux HEX_E0[1] bit 4	INT: mux HEX_E1[1] bit 4	INT: mux HEX_E1[1] bit 3	INT: mux HEX_E0[2] bit 3	INT: mux HEX_E0[2] bit 2	INT: mux HEX_E1[2] bit 2	INT: mux HEX_E1[2] bit 0	INT: mux HEX_E0[2] bit 0	INT: mux HEX_E0[2] bit 1	INT: mux HEX_E1[2] bit 1	INT: mux HEX_E1[2] bit 5	INT: mux HEX_E0[2] bit 5	INT: mux HEX_E0[2] bit 4	INT: mux HEX_E1[2] bit 4	INT: mux HEX_E1[2] bit 3	INT: mux HEX_E0[0] bit 3	INT: mux HEX_E0[0] bit 0	INT: mux HEX_E1[0] bit 0	INT: mux HEX_E1[0] bit 1	INT: mux HEX_E0[0] bit 1	INT: mux HEX_E0[0] bit 2	INT: mux HEX_E1[0] bit 2	-	-	-	-	INT: mux HEX_E1[0] bit 3	-	-	-	-	-	-
B0	INT: mux HEX_H0_MUX[3] bit 3	INT: mux HEX_H0_MUX[3] bit 2	INT: mux HEX_H1_MUX[3] bit 2	INT: mux HEX_H1_MUX[3] bit 1	INT: mux HEX_H2_MUX[3] bit 0	-	-	INT: mux HEX_H2_MUX[3] bit 1	INT: mux HEX_H4_MUX[3] bit 0	INT: mux HEX_H5_MUX[3] bit 1	INT: mux HEX_H4_MUX[3] bit 1	-	INT: mux HEX_H4_MUX[2] bit 1	INT: mux HEX_H4_MUX[2] bit 2	INT: mux HEX_H5_MUX[2] bit 2	INT: mux HEX_H4_MUX[2] bit 0	INT: mux HEX_H2_MUX[2] bit 1	INT: mux HEX_H2_MUX[2] bit 2	INT: mux HEX_H3_MUX[2] bit 2	INT: mux HEX_H2_MUX[2] bit 0	INT: mux HEX_H1_MUX[2] bit 1	-	INT: mux HEX_H0_MUX[2] bit 1	INT: mux HEX_H0_MUX[2] bit 2	INT: mux HEX_H0_MUX[1] bit 2	INT: mux HEX_H0_MUX[1] bit 1	INT: mux HEX_H1_MUX[1] bit 1	-	INT: mux HEX_H2_MUX[1] bit 0	-	-	INT: mux HEX_H2_MUX[1] bit 2	INT: mux HEX_H4_MUX[1] bit 0	INT: mux HEX_H5_MUX[1] bit 1	INT: mux HEX_H4_MUX[1] bit 1	-	INT: mux HEX_H4_MUX[0] bit 1	INT: mux HEX_H4_MUX[0] bit 2	INT: mux HEX_H5_MUX[0] bit 2	INT: mux HEX_H4_MUX[0] bit 0	INT: mux HEX_H2_MUX[0] bit 1	INT: mux HEX_H2_MUX[0] bit 2	INT: mux HEX_H3_MUX[0] bit 2	INT: mux HEX_H2_MUX[0] bit 0	INT: mux HEX_H1_MUX[0] bit 2	-	INT: mux HEX_H0_MUX[0] bit 3	INT: mux HEX_H0_MUX[0] bit 1	-	-	-	-	-	-

Tile IO_E

Cells: 1

Switchbox INT

virtex IO_E switchbox INT permanent buffers
Destination	Source
SINGLE_W_BUF[0]	SINGLE_W[0]
SINGLE_W_BUF[1]	SINGLE_W[1]
SINGLE_W_BUF[2]	SINGLE_W[2]
SINGLE_W_BUF[3]	SINGLE_W[3]
SINGLE_W_BUF[4]	SINGLE_W[4]
SINGLE_W_BUF[5]	SINGLE_W[5]
SINGLE_W_BUF[6]	SINGLE_W[6]
SINGLE_W_BUF[7]	SINGLE_W[7]
SINGLE_W_BUF[8]	SINGLE_W[8]
SINGLE_W_BUF[9]	SINGLE_W[9]
SINGLE_W_BUF[10]	SINGLE_W[10]
SINGLE_W_BUF[11]	SINGLE_W[11]
SINGLE_W_BUF[12]	SINGLE_W[12]
SINGLE_W_BUF[13]	SINGLE_W[13]
SINGLE_W_BUF[14]	SINGLE_W[14]
SINGLE_W_BUF[15]	SINGLE_W[15]
SINGLE_W_BUF[16]	SINGLE_W[16]
SINGLE_W_BUF[17]	SINGLE_W[17]
SINGLE_W_BUF[18]	SINGLE_W[18]
SINGLE_W_BUF[19]	SINGLE_W[19]
SINGLE_W_BUF[20]	SINGLE_W[20]
SINGLE_W_BUF[21]	SINGLE_W[21]
SINGLE_W_BUF[22]	SINGLE_W[22]
SINGLE_W_BUF[23]	SINGLE_W[23]
HEX_H3_BUF[0]	HEX_H3[0]
HEX_H3_BUF[1]	HEX_H3[1]
HEX_H3_BUF[2]	HEX_H3[2]
HEX_H3_BUF[3]	HEX_H3[3]
HEX_H4_BUF[0]	HEX_H4[0]
HEX_H4_BUF[1]	HEX_H4[1]
HEX_H4_BUF[2]	HEX_H4[2]
HEX_H4_BUF[3]	HEX_H4[3]
HEX_H5_BUF[0]	HEX_H5[0]
HEX_H5_BUF[1]	HEX_H5[1]
HEX_H5_BUF[2]	HEX_H5[2]
HEX_H5_BUF[3]	HEX_H5[3]
HEX_H6_BUF[0]	HEX_H6[0]
HEX_H6_BUF[1]	HEX_H6[1]
HEX_H6_BUF[2]	HEX_H6[2]
HEX_H6_BUF[3]	HEX_H6[3]
HEX_W2[0]	HEX_E3[0]
HEX_W2[1]	HEX_E3[1]
HEX_W2[2]	HEX_E3[2]
HEX_W2[3]	HEX_E3[3]
HEX_W3[0]	HEX_E4[0]
HEX_W3[1]	HEX_E4[1]
HEX_W3[2]	HEX_E4[2]
HEX_W3[3]	HEX_E4[3]
HEX_W4[0]	HEX_E5[0]
HEX_W4[1]	HEX_E5[1]
HEX_W4[2]	HEX_E5[2]
HEX_W4[3]	HEX_E5[3]
HEX_W5[0]	HEX_E6[0]
HEX_W5[1]	HEX_E6[1]
HEX_W5[2]	HEX_E6[2]
HEX_W5[3]	HEX_E6[3]
HEX_V1_BUF[0]	HEX_V1[0]
HEX_V1_BUF[1]	HEX_V1[1]
HEX_V1_BUF[2]	HEX_V1[2]
HEX_V1_BUF[3]	HEX_V1[3]
HEX_V2_BUF[0]	HEX_V2[0]
HEX_V2_BUF[1]	HEX_V2[1]
HEX_V2_BUF[2]	HEX_V2[2]
HEX_V2_BUF[3]	HEX_V2[3]
HEX_V3_BUF[0]	HEX_V3[0]
HEX_V3_BUF[1]	HEX_V3[1]
HEX_V3_BUF[2]	HEX_V3[2]
HEX_V3_BUF[3]	HEX_V3[3]
HEX_V4_BUF[0]	HEX_V4[0]
HEX_V4_BUF[1]	HEX_V4[1]
HEX_V4_BUF[2]	HEX_V4[2]
HEX_V4_BUF[3]	HEX_V4[3]
HEX_V5_BUF[0]	HEX_V5[0]
HEX_V5_BUF[1]	HEX_V5[1]
HEX_V5_BUF[2]	HEX_V5[2]
HEX_V5_BUF[3]	HEX_V5[3]
HEX_V6_BUF[0]	HEX_V6[0]
HEX_V6_BUF[1]	HEX_V6[1]
HEX_V6_BUF[2]	HEX_V6[2]
HEX_V6_BUF[3]	HEX_V6[3]

virtex IO_E switchbox INT programmable buffers
Destination	Source	Bit
HEX_H1[0]	HEX_H1_MUX[0]	MAIN[36][4]
HEX_H1[1]	HEX_H1_MUX[1]	MAIN[35][4]
HEX_H1[2]	HEX_H1_MUX[2]	MAIN[12][4]
HEX_H1[3]	HEX_H1_MUX[3]	MAIN[11][4]
HEX_H2[0]	HEX_H2_MUX[0]	MAIN[39][4]
HEX_H2[1]	HEX_H2_MUX[1]	MAIN[32][4]
HEX_H2[2]	HEX_H2_MUX[2]	MAIN[15][4]
HEX_H2[3]	HEX_H2_MUX[3]	MAIN[8][4]
HEX_H3[0]	HEX_H3_MUX[0]	MAIN[40][4]
HEX_H3[1]	HEX_H3_MUX[1]	MAIN[31][4]
HEX_H3[2]	HEX_H3_MUX[2]	MAIN[16][4]
HEX_H3[3]	HEX_H3_MUX[3]	MAIN[7][4]
HEX_H4[0]	HEX_H4_MUX[0]	MAIN[43][4]
HEX_H4[1]	HEX_H4_MUX[1]	MAIN[28][4]
HEX_H4[2]	HEX_H4_MUX[2]	MAIN[19][4]
HEX_H4[3]	HEX_H4_MUX[3]	MAIN[4][4]
HEX_H5[0]	HEX_H5_MUX[0]	MAIN[44][4]
HEX_H5[1]	HEX_H5_MUX[1]	MAIN[27][4]
HEX_H5[2]	HEX_H5_MUX[2]	MAIN[20][4]
HEX_H5[3]	HEX_H5_MUX[3]	MAIN[3][4]
HEX_H6[0]	HEX_H6_MUX[0]	MAIN[47][4]
HEX_H6[1]	HEX_H6_MUX[1]	MAIN[24][4]
HEX_H6[2]	HEX_H6_MUX[2]	MAIN[23][4]
HEX_H6[3]	HEX_H6_MUX[3]	MAIN[0][4]
HEX_V0[0]	HEX_V0_MUX[0]	MAIN[36][6]
HEX_V0[1]	HEX_V0_MUX[1]	MAIN[24][6]
HEX_V0[2]	HEX_V0_MUX[2]	MAIN[12][6]
HEX_V0[3]	HEX_V0_MUX[3]	MAIN[0][6]
HEX_V6[0]	HEX_V6_MUX[0]	MAIN[47][6]
HEX_V6[1]	HEX_V6_MUX[1]	MAIN[35][6]
HEX_V6[2]	HEX_V6_MUX[2]	MAIN[23][6]
HEX_V6[3]	HEX_V6_MUX[3]	MAIN[11][6]
LH[0]	LH_MUX[0]	MAIN[26][12]
LH[1]	LH_MUX[1]	MAIN[21][12]
LH[2]	LH_MUX[2]	MAIN[18][12]
LH[3]	LH_MUX[3]	MAIN[13][12]
LH[4]	LH_MUX[4]	MAIN[10][12]
LH[5]	LH_MUX[5]	MAIN[5][12]
LH[6]	LH_MUX[6]	MAIN[2][12]
LH[7]	LH_MUX[7]	MAIN[29][12]
LH[8]	LH_MUX[8]	MAIN[34][12]
LH[9]	LH_MUX[9]	MAIN[37][12]
LH[10]	LH_MUX[10]	MAIN[42][12]
LH[11]	LH_MUX[11]	MAIN[45][12]
LV[0]	LV_MUX[0]	MAIN[2][15]
LV[6]	LV_MUX[6]	MAIN[10][15]

virtex IO_E switchbox INT pass gates
Destination	Source	Bit
SINGLE_W[0]	HEX_V6[0]	MAIN[47][7]
SINGLE_W[0]	OUT_TBUF_E[3]	MAIN[47][8]
SINGLE_W[0]	OUT_IO_I[3]	MAIN[46][8]
SINGLE_W[1]	HEX_V3[0]	MAIN[45][8]
SINGLE_W[1]	OUT_IO_I[2]	MAIN[44][8]
SINGLE_W[2]	HEX_V0[0]	MAIN[43][8]
SINGLE_W[2]	OUT_IO_I[1]	MAIN[42][8]
SINGLE_W[3]	HEX_V6[0]	MAIN[39][8]
SINGLE_W[3]	OUT_TBUF_E[3]	MAIN[41][8]
SINGLE_W[4]	HEX_V3[0]	MAIN[37][8]
SINGLE_W[4]	OUT_IO_IQ[3]	MAIN[38][8]
SINGLE_W[5]	HEX_V0[0]	MAIN[36][8]
SINGLE_W[5]	OUT_IO_IQ[2]	MAIN[36][7]
SINGLE_W[6]	HEX_V6[1]	MAIN[35][7]
SINGLE_W[6]	OUT_TBUF_E[2]	MAIN[35][8]
SINGLE_W[6]	OUT_IO_IQ[1]	MAIN[34][8]
SINGLE_W[7]	HEX_V3[1]	MAIN[33][8]
SINGLE_W[8]	HEX_V0[1]	MAIN[31][8]
SINGLE_W[8]	OUT_IO_I[3]	MAIN[30][8]
SINGLE_W[9]	HEX_V6[1]	MAIN[27][8]
SINGLE_W[9]	OUT_TBUF_E[2]	MAIN[29][8]
SINGLE_W[9]	OUT_IO_I[2]	MAIN[28][8]
SINGLE_W[10]	HEX_V3[1]	MAIN[25][8]
SINGLE_W[10]	OUT_IO_I[1]	MAIN[26][8]
SINGLE_W[11]	HEX_V0[1]	MAIN[24][8]
SINGLE_W[12]	HEX_V6[2]	MAIN[23][7]
SINGLE_W[12]	OUT_TBUF_E[1]	MAIN[23][8]
SINGLE_W[12]	OUT_IO_IQ[3]	MAIN[22][8]
SINGLE_W[13]	HEX_V3[2]	MAIN[21][8]
SINGLE_W[13]	OUT_IO_IQ[2]	MAIN[20][8]
SINGLE_W[14]	HEX_V0[2]	MAIN[19][8]
SINGLE_W[14]	OUT_IO_IQ[1]	MAIN[18][8]
SINGLE_W[15]	HEX_V6[2]	MAIN[15][8]
SINGLE_W[15]	OUT_TBUF_E[1]	MAIN[17][8]
SINGLE_W[16]	HEX_V3[2]	MAIN[13][8]
SINGLE_W[16]	OUT_IO_I[3]	MAIN[14][8]
SINGLE_W[17]	HEX_V0[2]	MAIN[12][8]
SINGLE_W[17]	OUT_IO_I[2]	MAIN[12][7]
SINGLE_W[18]	HEX_V6[3]	MAIN[11][7]
SINGLE_W[18]	OUT_TBUF_E[0]	MAIN[11][8]
SINGLE_W[18]	OUT_IO_I[1]	MAIN[10][8]
SINGLE_W[19]	HEX_V3[3]	MAIN[9][8]
SINGLE_W[20]	HEX_V0[3]	MAIN[7][8]
SINGLE_W[20]	OUT_IO_IQ[3]	MAIN[6][8]
SINGLE_W[21]	HEX_V6[3]	MAIN[3][8]
SINGLE_W[21]	OUT_TBUF_E[0]	MAIN[5][8]
SINGLE_W[21]	OUT_IO_IQ[2]	MAIN[4][8]
SINGLE_W[22]	HEX_V3[3]	MAIN[1][8]
SINGLE_W[22]	OUT_IO_IQ[1]	MAIN[2][8]
SINGLE_W[23]	HEX_V0[3]	MAIN[0][8]

virtex IO_E switchbox INT muxes HEX_H1_MUX[0]
Bits			Destination
MAIN[38][0]	MAIN[37][2]	MAIN[36][2]	HEX_H1_MUX[0]
			Source
0	0	0	LH[5]
0	0	1	off
0	1	1	OUT_IO_I[2]
1	0	1	OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H1_MUX[1]
Bits			Destination
MAIN[33][2]	MAIN[33][0]	MAIN[35][2]	HEX_H1_MUX[1]
			Source
0	0	0	LH[5]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes HEX_H1_MUX[2]
Bits			Destination
MAIN[14][0]	MAIN[13][2]	MAIN[12][2]	HEX_H1_MUX[2]
			Source
0	0	0	LH[11]
0	0	1	off
0	1	1	OUT_IO_IQ[2]
1	0	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H1_MUX[3]
Bits			Destination
MAIN[9][2]	MAIN[9][0]	MAIN[11][2]	HEX_H1_MUX[3]
			Source
0	0	0	LH[11]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_E switchbox INT muxes HEX_H2_MUX[0]
Bits			Destination
MAIN[37][0]	MAIN[36][0]	MAIN[39][0]	HEX_H2_MUX[0]
			Source
0	0	0	LH[4]
0	0	1	off
0	1	1	OUT_IO_I[2]
1	0	1	OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H2_MUX[1]
Bits			Destination
MAIN[32][2]	MAIN[34][0]	MAIN[32][0]	HEX_H2_MUX[1]
			Source
0	0	0	LH[4]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes HEX_H2_MUX[2]
Bits			Destination
MAIN[13][0]	MAIN[12][0]	MAIN[15][0]	HEX_H2_MUX[2]
			Source
0	0	0	LH[10]
0	0	1	off
0	1	1	OUT_IO_IQ[2]
1	0	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H2_MUX[3]
Bits			Destination
MAIN[8][2]	MAIN[10][0]	MAIN[8][0]	HEX_H2_MUX[3]
			Source
0	0	0	LH[10]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_E switchbox INT muxes HEX_H3_MUX[0]
Bits				Destination
MAIN[42][2]	MAIN[42][0]	MAIN[41][2]	MAIN[40][2]	HEX_H3_MUX[0]
				Source
0	0	0	0	LH[3]
0	0	0	1	off
0	0	1	1	OUT_IO_IQ[1]
0	1	0	1	OUT_IO_IQ[2]
1	0	0	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H3_MUX[1]
Bits			Destination
MAIN[30][2]	MAIN[29][2]	MAIN[31][2]	HEX_H3_MUX[1]
			Source
0	0	0	LH[3]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H3_MUX[2]
Bits				Destination
MAIN[18][2]	MAIN[18][0]	MAIN[17][2]	MAIN[16][2]	HEX_H3_MUX[2]
				Source
0	0	0	0	LH[9]
0	0	0	1	off
0	0	1	1	OUT_IO_I[1]
0	1	0	1	OUT_IO_I[2]
1	0	0	1	OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H3_MUX[3]
Bits			Destination
MAIN[5][2]	MAIN[6][2]	MAIN[7][2]	HEX_H3_MUX[3]
			Source
0	0	0	LH[9]
0	0	1	off
0	1	1	OUT_IO_I[3]
1	0	1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H4_MUX[0]
Bits				Destination
MAIN[43][2]	MAIN[41][0]	MAIN[40][0]	MAIN[43][0]	HEX_H4_MUX[0]
				Source
0	0	0	0	LH[2]
0	0	0	1	off
0	0	1	1	OUT_IO_IQ[1]
0	1	0	1	OUT_IO_IQ[2]
1	0	0	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H4_MUX[1]
Bits			Destination
MAIN[31][0]	MAIN[28][2]	MAIN[28][0]	HEX_H4_MUX[1]
			Source
0	0	0	LH[2]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H4_MUX[2]
Bits				Destination
MAIN[19][2]	MAIN[17][0]	MAIN[16][0]	MAIN[19][0]	HEX_H4_MUX[2]
				Source
0	0	0	0	LH[8]
0	0	0	1	off
0	0	1	1	OUT_IO_I[1]
0	1	0	1	OUT_IO_I[2]
1	0	0	1	OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H4_MUX[3]
Bits			Destination
MAIN[4][2]	MAIN[7][0]	MAIN[4][0]	HEX_H4_MUX[3]
			Source
0	0	0	LH[8]
0	0	1	off
0	1	1	OUT_IO_I[3]
1	0	1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H5_MUX[0]
Bits			Destination
MAIN[44][0]	MAIN[46][4]	MAIN[44][2]	HEX_H5_MUX[0]
			Source
0	0	0	LH[1]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H5_MUX[1]
Bits			Destination
MAIN[25][4]	MAIN[26][0]	MAIN[27][2]	HEX_H5_MUX[1]
			Source
0	0	0	LH[1]
0	0	1	off
0	1	1	OUT_IO_I[2]
1	0	1	OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H5_MUX[2]
Bits			Destination
MAIN[22][4]	MAIN[20][0]	MAIN[20][2]	HEX_H5_MUX[2]
			Source
0	0	0	LH[7]
0	0	1	off
0	1	1	OUT_IO_I[3]
1	0	1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H5_MUX[3]
Bits				Destination
MAIN[1][4]	MAIN[2][0]	MAIN[3][0]	MAIN[3][2]	HEX_H5_MUX[3]
				Source
0	0	0	0	LH[7]
0	0	0	1	off
0	0	1	1	OUT_IO_I[2]
0	1	0	1	OUT_IO_IQ[2]
1	0	0	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_H6_MUX[0]
Bits					Destination
MAIN[46][2]	MAIN[46][0]	MAIN[45][4]	MAIN[47][0]	MAIN[47][2]	HEX_H6_MUX[0]
					Source
0	0	1	1	1	HEX_V0[1]
0	1	0	1	1	HEX_V3[3]
0	1	1	0	1	HEX_V6[0]
0	1	1	1	0	LH[0]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_I[1]

virtex IO_E switchbox INT muxes HEX_H6_MUX[1]
Bits						Destination
MAIN[25][2]	MAIN[26][2]	MAIN[26][4]	MAIN[24][0]	MAIN[25][0]	MAIN[24][2]	HEX_H6_MUX[1]
						Source
0	0	0	1	1	1	HEX_V0[2]
0	0	1	0	1	1	HEX_V3[0]
0	0	1	1	0	1	HEX_V6[1]
0	0	1	1	1	0	LH[0]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_I[3]

virtex IO_E switchbox INT muxes HEX_H6_MUX[2]
Bits					Destination
MAIN[22][2]	MAIN[21][4]	MAIN[23][0]	MAIN[22][0]	MAIN[23][2]	HEX_H6_MUX[2]
					Source
0	0	1	1	1	HEX_V0[3]
0	1	0	1	1	HEX_V3[1]
0	1	1	0	1	HEX_V6[2]
0	1	1	1	0	LH[6]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_H6_MUX[3]
Bits						Destination
MAIN[1][2]	MAIN[2][2]	MAIN[0][0]	MAIN[1][0]	MAIN[2][4]	MAIN[0][2]	HEX_H6_MUX[3]
						Source
0	0	0	1	1	1	HEX_V0[0]
0	0	1	0	1	1	HEX_V3[2]
0	0	1	1	0	1	HEX_V6[3]
0	0	1	1	1	0	LH[6]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_IQ[2]
1	0	1	1	1	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_W0[0]
Bits				Destination
MAIN[36][1]	MAIN[41][1]	MAIN[40][1]	MAIN[37][1]	HEX_W0[0]
				Source
0	1	1	1	HEX_E1[0]
1	0	1	1	HEX_V0[2]
1	1	0	1	HEX_V3[1]
1	1	1	0	HEX_V6[0]
1	1	1	1	off

virtex IO_E switchbox INT muxes HEX_W0[1]
Bits						Destination
MAIN[20][1]	MAIN[21][1]	MAIN[12][1]	MAIN[16][1]	MAIN[13][1]	MAIN[17][1]	HEX_W0[1]
						Source
0	0	0	1	1	1	HEX_E1[1]
0	0	1	0	1	1	HEX_V0[1]
0	0	1	1	0	1	HEX_V3[0]
0	0	1	1	1	0	HEX_V6[3]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[1]
1	0	1	1	1	1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_W0[2]
Bits						Destination
MAIN[32][1]	MAIN[33][1]	MAIN[24][1]	MAIN[25][1]	MAIN[29][1]	MAIN[28][1]	HEX_W0[2]
						Source
0	0	0	1	1	1	HEX_E1[2]
0	0	1	0	1	1	HEX_V0[0]
0	0	1	1	0	1	HEX_V3[3]
0	0	1	1	1	0	HEX_V6[2]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes HEX_W0[3]
Bits						Destination
MAIN[8][1]	MAIN[9][1]	MAIN[0][1]	MAIN[5][1]	MAIN[4][1]	MAIN[1][1]	HEX_W0[3]
						Source
0	0	0	1	1	1	HEX_E1[3]
0	0	1	0	1	1	HEX_V0[3]
0	0	1	1	0	1	HEX_V3[2]
0	0	1	1	1	0	HEX_V6[1]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[3]
1	0	1	1	1	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_W1[0]
Bits				Destination
MAIN[47][1]	MAIN[42][1]	MAIN[39][1]	MAIN[38][1]	HEX_W1[0]
				Source
0	1	1	1	HEX_E2[0]
1	0	1	1	HEX_V0[2]
1	1	0	1	HEX_V3[1]
1	1	1	0	HEX_V6[0]
1	1	1	1	off

virtex IO_E switchbox INT muxes HEX_W1[1]
Bits						Destination
MAIN[19][1]	MAIN[22][1]	MAIN[23][1]	MAIN[15][1]	MAIN[14][1]	MAIN[18][1]	HEX_W1[1]
						Source
0	0	0	1	1	1	HEX_E2[1]
0	0	1	0	1	1	HEX_V0[1]
0	0	1	1	0	1	HEX_V3[0]
0	0	1	1	1	0	HEX_V6[3]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[1]
1	0	1	1	1	1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes HEX_W1[2]
Bits						Destination
MAIN[31][1]	MAIN[34][1]	MAIN[35][1]	MAIN[26][1]	MAIN[30][1]	MAIN[27][1]	HEX_W1[2]
						Source
0	0	0	1	1	1	HEX_E2[2]
0	0	1	0	1	1	HEX_V0[0]
0	0	1	1	0	1	HEX_V3[3]
0	0	1	1	1	0	HEX_V6[2]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes HEX_W1[3]
Bits						Destination
MAIN[7][1]	MAIN[10][1]	MAIN[11][1]	MAIN[6][1]	MAIN[3][1]	MAIN[2][1]	HEX_W1[3]
						Source
0	0	0	1	1	1	HEX_E2[3]
0	0	1	0	1	1	HEX_V0[3]
0	0	1	1	0	1	HEX_V3[2]
0	0	1	1	1	0	HEX_V6[1]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[3]
1	0	1	1	1	1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V0_MUX[0]
Bits							Destination
MAIN[41][6]	MAIN[40][6]	MAIN[42][6]	MAIN[44][6]	MAIN[43][6]	MAIN[39][6]	MAIN[37][5]	HEX_V0_MUX[0]
							Source
0	0	0	0	0	0	1	HEX_H3[2]
0	0	0	0	0	1	0	HEX_H6[3]
0	0	0	0	1	0	0	HEX_V6[0]
0	0	0	1	0	0	0	LV[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[1]
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V0_MUX[1]
Bits							Destination
MAIN[29][6]	MAIN[28][6]	MAIN[30][6]	MAIN[32][6]	MAIN[31][6]	MAIN[27][6]	MAIN[25][5]	HEX_V0_MUX[1]
							Source
0	0	0	0	0	0	1	HEX_H3[3]
0	0	0	0	0	1	0	HEX_H6[0]
0	0	0	0	1	0	0	HEX_V6[1]
0	0	0	1	0	0	0	LV[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[1]
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V0_MUX[2]
Bits							Destination
MAIN[17][6]	MAIN[16][6]	MAIN[18][6]	MAIN[20][6]	MAIN[19][6]	MAIN[15][6]	MAIN[13][5]	HEX_V0_MUX[2]
							Source
0	0	0	0	0	0	1	HEX_H3[0]
0	0	0	0	0	1	0	HEX_H6[1]
0	0	0	0	1	0	0	HEX_V6[2]
0	0	0	1	0	0	0	LV[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[1]
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V0_MUX[3]
Bits							Destination
MAIN[5][6]	MAIN[4][6]	MAIN[6][6]	MAIN[8][6]	MAIN[7][6]	MAIN[3][6]	MAIN[1][5]	HEX_V0_MUX[3]
							Source
0	0	0	0	0	0	1	HEX_H3[1]
0	0	0	0	0	1	0	HEX_H6[2]
0	0	0	0	1	0	0	HEX_V6[3]
0	0	0	1	0	0	0	LV[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[1]
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V6_MUX[0]
Bits							Destination
MAIN[46][6]	MAIN[37][6]	MAIN[46][5]	MAIN[38][6]	MAIN[36][5]	MAIN[47][5]	MAIN[45][6]	HEX_V6_MUX[0]
							Source
0	0	0	0	0	0	1	HEX_H3[2]
0	0	0	0	0	1	0	HEX_H6[0]
0	0	0	0	1	0	0	HEX_V0[0]
0	0	0	1	0	0	0	LV[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[1]
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V6_MUX[1]
Bits							Destination
MAIN[34][6]	MAIN[25][6]	MAIN[34][5]	MAIN[26][6]	MAIN[24][5]	MAIN[35][5]	MAIN[33][6]	HEX_V6_MUX[1]
							Source
0	0	0	0	0	0	1	HEX_H3[3]
0	0	0	0	0	1	0	HEX_H6[1]
0	0	0	0	1	0	0	HEX_V0[1]
0	0	0	1	0	0	0	LV[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[1]
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V6_MUX[2]
Bits							Destination
MAIN[22][6]	MAIN[13][6]	MAIN[22][5]	MAIN[14][6]	MAIN[12][5]	MAIN[23][5]	MAIN[21][6]	HEX_V6_MUX[2]
							Source
0	0	0	0	0	0	1	HEX_H3[0]
0	0	0	0	0	1	0	HEX_H6[2]
0	0	0	0	1	0	0	HEX_V0[2]
0	0	0	1	0	0	0	LV[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[1]
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes HEX_V6_MUX[3]
Bits							Destination
MAIN[10][6]	MAIN[1][6]	MAIN[10][5]	MAIN[2][6]	MAIN[0][5]	MAIN[11][5]	MAIN[9][6]	HEX_V6_MUX[3]
							Source
0	0	0	0	0	0	1	HEX_H3[1]
0	0	0	0	0	1	0	HEX_H6[3]
0	0	0	0	1	0	0	HEX_V0[3]
0	0	0	1	0	0	0	LV[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[1]
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[3]
1	0	1	0	0	0	1	OUT_IO_IQ[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LH_MUX[0]
Bits	Destination
LH_MUX[0]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LH_MUX[1]
Bits	Destination
LH_MUX[1]
	Source
OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LH_MUX[2]
Bits	Destination
MAIN[16][12]	LH_MUX[2]
	Source
0	OUT_IO_I[3]
1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes LH_MUX[3]
Bits	Destination
MAIN[15][12]	LH_MUX[3]
	Source
0	OUT_IO_I[3]
1	OUT_IO_IQ[1]

virtex IO_E switchbox INT muxes LH_MUX[4]
Bits	Destination
MAIN[8][12]	LH_MUX[4]
	Source
0	OUT_IO_IQ[2]
1	OUT_IO_I[1]

virtex IO_E switchbox INT muxes LH_MUX[5]
Bits	Destination
MAIN[7][12]	LH_MUX[5]
	Source
0	OUT_IO_I[2]
1	OUT_IO_I[1]

virtex IO_E switchbox INT muxes LH_MUX[6]
Bits	Destination
MAIN[0][12]	LH_MUX[6]
	Source
0	off
1	OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes LH_MUX[7]
Bits	Destination
MAIN[31][12]	LH_MUX[7]
	Source
0	OUT_IO_I[1]
1	OUT_IO_IQ[2]

virtex IO_E switchbox INT muxes LH_MUX[8]
Bits	Destination
MAIN[32][12]	LH_MUX[8]
	Source
0	off
1	OUT_IO_I[2]

virtex IO_E switchbox INT muxes LH_MUX[9]
Bits	Destination
MAIN[39][12]	LH_MUX[9]
	Source
0	off
1	OUT_IO_I[2]

virtex IO_E switchbox INT muxes LH_MUX[10]
Bits	Destination
MAIN[40][12]	LH_MUX[10]
	Source
0	off
1	OUT_IO_IQ[3]

virtex IO_E switchbox INT muxes LH_MUX[11]
Bits	Destination
MAIN[47][12]	LH_MUX[11]
	Source
0	OUT_IO_IQ[1]
1	OUT_IO_I[3]

virtex IO_E switchbox INT muxes LV_MUX[0]
Bits									Destination
MAIN[4][15]	MAIN[9][12]	MAIN[1][15]	MAIN[7][15]	MAIN[14][15]	MAIN[11][15]	MAIN[12][15]	MAIN[3][15]	MAIN[0][15]	LV_MUX[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	1	SINGLE_W_BUF[5]
0	0	0	0	0	0	0	1	0	SINGLE_W_BUF[6]
0	0	0	0	0	0	1	0	0	SINGLE_W_BUF[10]
0	0	0	0	0	1	0	0	0	SINGLE_W_BUF[11]
0	0	0	0	1	0	0	0	0	SINGLE_W_BUF[17]
0	0	0	1	0	0	0	0	0	SINGLE_W_BUF[18]
0	0	1	0	0	0	0	0	0	SINGLE_W_BUF[22]
0	1	0	0	0	0	0	0	0	SINGLE_W_BUF[23]
1	0	0	0	0	0	0	0	1	OUT_IO_IQ[3]
1	0	0	0	0	0	0	1	0	OUT_IO_IQ[2]
1	0	0	0	0	0	1	0	0	OUT_IO_I[2]
1	0	0	0	1	0	0	0	0	OUT_IO_IQ[1]
1	0	0	1	0	0	0	0	0	OUT_IO_I[3]
1	0	1	0	0	0	0	0	0	OUT_IO_I[1]

virtex IO_E switchbox INT muxes LV_MUX[6]
Bits									Destination
MAIN[8][15]	MAIN[12][12]	MAIN[5][15]	MAIN[6][15]	MAIN[15][15]	MAIN[14][12]	MAIN[9][15]	MAIN[13][15]	MAIN[1][12]	LV_MUX[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	1	SINGLE_W_BUF[5]
0	0	0	0	0	0	0	1	0	SINGLE_W_BUF[6]
0	0	0	0	0	0	1	0	0	SINGLE_W_BUF[10]
0	0	0	0	0	1	0	0	0	SINGLE_W_BUF[11]
0	0	0	0	1	0	0	0	0	SINGLE_W_BUF[17]
0	0	0	1	0	0	0	0	0	SINGLE_W_BUF[18]
0	0	1	0	0	0	0	0	0	SINGLE_W_BUF[22]
0	1	0	0	0	0	0	0	0	SINGLE_W_BUF[23]
1	0	0	0	0	0	0	0	1	OUT_IO_IQ[3]
1	0	0	0	0	0	0	1	0	OUT_IO_IQ[2]
1	0	0	0	0	0	1	0	0	OUT_IO_I[2]
1	0	0	0	1	0	0	0	0	OUT_IO_IQ[1]
1	0	0	1	0	0	0	0	0	OUT_IO_I[3]
1	0	1	0	0	0	0	0	0	OUT_IO_I[1]

virtex IO_E switchbox INT muxes IMUX_TBUF_T[0]
Bits					Destination
MAIN[26][15]	MAIN[27][15]	MAIN[40][15]	MAIN[35][12]	MAIN[27][12]	IMUX_TBUF_T[0]
					Source
0	0	0	0	0	PULLUP
0	0	0	0	1	HEX_V6_BUF[1]
0	0	0	1	0	HEX_V5_BUF[1]
0	0	1	0	0	HEX_V1_BUF[1]
0	1	0	0	1	SINGLE_W_BUF[0]
0	1	0	1	0	SINGLE_W_BUF[7]
1	0	0	0	1	HEX_V2_BUF[1]
1	0	0	1	0	HEX_V3_BUF[1]
1	0	1	0	0	HEX_V4_BUF[1]
1	1	0	0	1	SINGLE_W_BUF[19]
1	1	0	1	0	SINGLE_W_BUF[12]

virtex IO_E switchbox INT muxes IMUX_TBUF_T[1]
Bits					Destination
MAIN[29][15]	MAIN[28][15]	MAIN[43][15]	MAIN[33][12]	MAIN[28][12]	IMUX_TBUF_T[1]
					Source
0	0	0	0	0	PULLUP
0	0	0	0	1	HEX_V6_BUF[1]
0	0	0	1	0	HEX_V5_BUF[1]
0	0	1	0	0	HEX_V1_BUF[1]
0	1	0	0	1	SINGLE_W_BUF[0]
0	1	0	1	0	SINGLE_W_BUF[7]
1	0	0	0	1	HEX_V2_BUF[1]
1	0	0	1	0	HEX_V3_BUF[1]
1	0	1	0	0	HEX_V4_BUF[1]
1	1	0	0	1	SINGLE_W_BUF[19]
1	1	0	1	0	SINGLE_W_BUF[12]

virtex IO_E switchbox INT muxes IMUX_TBUF_I[0]
Bits					Destination
MAIN[19][15]	MAIN[20][15]	MAIN[37][15]	MAIN[17][15]	MAIN[16][15]	IMUX_TBUF_I[0]
					Source
0	0	0	0	0	PULLUP
0	0	0	0	1	SINGLE_W_BUF[17]
0	0	0	1	0	SINGLE_W_BUF[18]
0	0	1	0	0	SINGLE_W_BUF[22]
0	1	0	0	1	OUT_IO_I[3]
0	1	0	1	0	OUT_IO_I[2]
0	1	1	0	0	SINGLE_W_BUF[23]
1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	0	OUT_IO_IQ[3]
1	1	0	1	0	OUT_IO_IQ[1]
1	1	1	0	0	OUT_IO_I[1]

virtex IO_E switchbox INT muxes IMUX_TBUF_I[1]
Bits					Destination
MAIN[22][15]	MAIN[21][15]	MAIN[38][15]	MAIN[39][15]	MAIN[24][15]	IMUX_TBUF_I[1]
					Source
0	0	0	0	0	PULLUP
0	0	0	0	1	SINGLE_W_BUF[5]
0	0	0	1	0	SINGLE_W_BUF[6]
0	0	1	0	0	SINGLE_W_BUF[11]
0	1	0	0	1	OUT_IO_I[2]
0	1	0	1	0	OUT_IO_I[3]
0	1	1	0	0	SINGLE_W_BUF[10]
1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	0	0	OUT_IO_IQ[3]
1	1	0	0	1	OUT_IO_IQ[1]
1	1	1	0	0	OUT_IO_I[1]

virtex IO_E switchbox INT muxes IMUX_IO_CLK[0]
Bits											Destination
MAIN[30][12]	MAIN[30][14]	MAIN[29][14]	MAIN[36][13]	MAIN[26][14]	MAIN[30][13]	MAIN[24][13]	MAIN[25][14]	MAIN[25][13]	MAIN[27][13]	MAIN[27][14]	IMUX_IO_CLK[0]
											Source
0	0	0	0	0	0	1	1	1	1	1	GCLK_LEAF[0]
0	0	0	0	0	1	0	1	1	1	1	GCLK_LEAF[1]
0	0	0	0	0	1	1	0	1	1	1	GCLK_LEAF[2]
0	0	0	0	0	1	1	1	0	1	1	GCLK_LEAF[3]
0	0	0	0	0	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	SINGLE_W_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	HEX_V1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	HEX_V4_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	SINGLE_W_BUF[9]
0	1	0	0	0	1	1	1	1	1	0	HEX_V6_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	SINGLE_W_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	HEX_V2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	HEX_V3_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	SINGLE_W_BUF[15]

virtex IO_E switchbox INT muxes IMUX_IO_CLK[1]
Bits											Destination
MAIN[28][14]	MAIN[31][14]	MAIN[28][13]	MAIN[33][13]	MAIN[25][12]	MAIN[24][14]	MAIN[31][13]	MAIN[34][13]	MAIN[26][13]	MAIN[32][13]	MAIN[29][13]	IMUX_IO_CLK[1]
											Source
0	0	0	0	0	0	1	1	1	1	1	GCLK_LEAF[0]
0	0	0	0	0	1	0	1	1	1	1	GCLK_LEAF[1]
0	0	0	0	0	1	1	0	1	1	1	GCLK_LEAF[2]
0	0	0	0	0	1	1	1	0	1	1	GCLK_LEAF[3]
0	0	0	0	0	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	SINGLE_W_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	HEX_V1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	HEX_V4_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	SINGLE_W_BUF[9]
0	1	0	0	0	1	1	1	1	1	0	HEX_V6_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	SINGLE_W_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	HEX_V2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	HEX_V3_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	SINGLE_W_BUF[15]

virtex IO_E switchbox INT muxes IMUX_IO_CLK[2]
Bits											Destination
MAIN[19][14]	MAIN[16][14]	MAIN[19][13]	MAIN[14][13]	MAIN[22][12]	MAIN[23][14]	MAIN[16][13]	MAIN[13][13]	MAIN[21][13]	MAIN[15][13]	MAIN[18][13]	IMUX_IO_CLK[2]
											Source
0	0	0	0	0	0	1	1	1	1	1	GCLK_LEAF[0]
0	0	0	0	0	1	0	1	1	1	1	GCLK_LEAF[1]
0	0	0	0	0	1	1	0	1	1	1	GCLK_LEAF[2]
0	0	0	0	0	1	1	1	0	1	1	GCLK_LEAF[3]
0	0	0	0	0	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	SINGLE_W_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	HEX_V1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	HEX_V4_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	SINGLE_W_BUF[9]
0	1	0	0	0	1	1	1	1	1	0	HEX_V6_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	SINGLE_W_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	HEX_V2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	HEX_V3_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	SINGLE_W_BUF[15]

virtex IO_E switchbox INT muxes IMUX_IO_CLK[3]
Bits											Destination
MAIN[17][12]	MAIN[17][14]	MAIN[18][14]	MAIN[11][13]	MAIN[21][14]	MAIN[17][13]	MAIN[23][13]	MAIN[22][14]	MAIN[22][13]	MAIN[20][13]	MAIN[20][14]	IMUX_IO_CLK[3]
											Source
0	0	0	0	0	0	1	1	1	1	1	GCLK_LEAF[0]
0	0	0	0	0	1	0	1	1	1	1	GCLK_LEAF[1]
0	0	0	0	0	1	1	0	1	1	1	GCLK_LEAF[2]
0	0	0	0	0	1	1	1	0	1	1	GCLK_LEAF[3]
0	0	0	0	0	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	SINGLE_W_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	HEX_V1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	HEX_V4_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	SINGLE_W_BUF[9]
0	1	0	0	0	1	1	1	1	1	0	HEX_V6_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	SINGLE_W_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	HEX_V2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	HEX_V3_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	SINGLE_W_BUF[15]

virtex IO_E switchbox INT muxes IMUX_IO_SR[0]
Bits						Destination
MAIN[29][10]	MAIN[30][10]	MAIN[31][10]	MAIN[33][9]	MAIN[32][11]	MAIN[33][11]	IMUX_IO_SR[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[4]
0	0	0	0	1	0	SINGLE_W_BUF[5]
0	0	0	1	0	0	SINGLE_W_BUF[6]
0	0	1	0	0	0	SINGLE_W_BUF[7]
0	1	0	0	0	1	HEX_V1_BUF[1]
0	1	0	0	1	0	HEX_V4_BUF[1]
1	1	0	0	0	1	HEX_V2_BUF[1]
1	1	0	0	1	0	HEX_V3_BUF[1]
1	1	0	1	0	0	HEX_V5_BUF[1]
1	1	1	0	0	0	HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_IO_SR[1]
Bits						Destination
MAIN[30][11]	MAIN[29][11]	MAIN[28][9]	MAIN[32][9]	MAIN[31][9]	MAIN[28][11]	IMUX_IO_SR[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[4]
0	0	0	0	1	0	SINGLE_W_BUF[5]
0	0	0	1	0	0	SINGLE_W_BUF[6]
0	0	1	0	0	0	SINGLE_W_BUF[7]
0	1	0	0	0	1	HEX_V1_BUF[1]
0	1	0	0	1	0	HEX_V4_BUF[1]
1	1	0	0	0	1	HEX_V2_BUF[1]
1	1	0	0	1	0	HEX_V3_BUF[1]
1	1	0	1	0	0	HEX_V5_BUF[1]
1	1	1	0	0	0	HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_IO_SR[2]
Bits						Destination
MAIN[35][11]	MAIN[36][11]	MAIN[37][10]	MAIN[38][9]	MAIN[36][9]	MAIN[37][11]	IMUX_IO_SR[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[4]
0	0	0	0	1	0	SINGLE_W_BUF[5]
0	0	0	1	0	0	SINGLE_W_BUF[6]
0	0	1	0	0	0	SINGLE_W_BUF[7]
0	1	0	0	0	1	HEX_V1_BUF[1]
0	1	0	0	1	0	HEX_V4_BUF[1]
1	1	0	0	0	1	HEX_V2_BUF[1]
1	1	0	0	1	0	HEX_V3_BUF[1]
1	1	0	1	0	0	HEX_V5_BUF[1]
1	1	1	0	0	0	HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_IO_SR[3]
Bits						Destination
MAIN[36][10]	MAIN[35][10]	MAIN[34][10]	MAIN[35][9]	MAIN[39][9]	MAIN[34][11]	IMUX_IO_SR[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[4]
0	0	0	0	1	0	SINGLE_W_BUF[5]
0	0	0	1	0	0	SINGLE_W_BUF[6]
0	0	1	0	0	0	SINGLE_W_BUF[7]
0	1	0	0	0	1	HEX_V1_BUF[1]
0	1	0	0	1	0	HEX_V4_BUF[1]
1	1	0	0	0	1	HEX_V2_BUF[1]
1	1	0	0	1	0	HEX_V3_BUF[1]
1	1	0	1	0	0	HEX_V5_BUF[1]
1	1	1	0	0	0	HEX_V6_BUF[1]

virtex IO_E switchbox INT muxes IMUX_IO_ICE[0]
Bits						Destination
MAIN[8][10]	MAIN[7][10]	MAIN[5][11]	MAIN[6][11]	MAIN[7][9]	MAIN[6][10]	IMUX_IO_ICE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[20]
0	0	0	0	1	0	SINGLE_W_BUF[21]
0	0	0	1	0	0	SINGLE_W_BUF[22]
0	0	1	0	0	0	SINGLE_W_BUF[23]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_ICE[1]
Bits						Destination
MAIN[7][11]	MAIN[8][11]	MAIN[9][11]	MAIN[4][9]	MAIN[5][9]	MAIN[9][10]	IMUX_IO_ICE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[20]
0	0	0	0	1	0	SINGLE_W_BUF[21]
0	0	0	1	0	0	SINGLE_W_BUF[22]
0	0	1	0	0	0	SINGLE_W_BUF[23]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_ICE[2]
Bits						Destination
MAIN[2][11]	MAIN[1][11]	MAIN[0][11]	MAIN[0][9]	MAIN[1][9]	MAIN[0][10]	IMUX_IO_ICE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[20]
0	0	0	0	1	0	SINGLE_W_BUF[21]
0	0	0	1	0	0	SINGLE_W_BUF[22]
0	0	1	0	0	0	SINGLE_W_BUF[23]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_ICE[3]
Bits						Destination
MAIN[1][10]	MAIN[2][10]	MAIN[3][11]	MAIN[4][11]	MAIN[2][9]	MAIN[3][10]	IMUX_IO_ICE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[20]
0	0	0	0	1	0	SINGLE_W_BUF[21]
0	0	0	1	0	0	SINGLE_W_BUF[22]
0	0	1	0	0	0	SINGLE_W_BUF[23]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_OCE[0]
Bits						Destination
MAIN[18][10]	MAIN[17][10]	MAIN[14][11]	MAIN[15][11]	MAIN[16][10]	MAIN[14][9]	IMUX_IO_OCE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[17]
0	0	0	0	1	0	SINGLE_W_BUF[16]
0	0	0	1	0	0	SINGLE_W_BUF[18]
0	0	1	0	0	0	SINGLE_W_BUF[19]
0	1	0	0	0	1	PCI_CE
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V5_BUF[3]
1	1	0	0	1	0	HEX_V6_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_OCE[1]
Bits						Destination
MAIN[17][11]	MAIN[18][11]	MAIN[19][11]	MAIN[16][9]	MAIN[19][9]	MAIN[15][9]	IMUX_IO_OCE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[17]
0	0	0	0	1	0	SINGLE_W_BUF[16]
0	0	0	1	0	0	SINGLE_W_BUF[18]
0	0	1	0	0	0	SINGLE_W_BUF[19]
0	1	0	0	0	1	PCI_CE
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V5_BUF[3]
1	1	0	0	1	0	HEX_V6_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_OCE[2]
Bits						Destination
MAIN[12][11]	MAIN[11][11]	MAIN[10][11]	MAIN[11][9]	MAIN[10][10]	MAIN[9][9]	IMUX_IO_OCE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[17]
0	0	0	0	1	0	SINGLE_W_BUF[16]
0	0	0	1	0	0	SINGLE_W_BUF[18]
0	0	1	0	0	0	SINGLE_W_BUF[19]
0	1	0	0	0	1	PCI_CE
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V5_BUF[3]
1	1	0	0	1	0	HEX_V6_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_OCE[3]
Bits						Destination
MAIN[11][10]	MAIN[12][10]	MAIN[13][11]	MAIN[8][9]	MAIN[13][10]	MAIN[12][9]	IMUX_IO_OCE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[17]
0	0	0	0	1	0	SINGLE_W_BUF[16]
0	0	0	1	0	0	SINGLE_W_BUF[18]
0	0	1	0	0	0	SINGLE_W_BUF[19]
0	1	0	0	0	1	PCI_CE
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V5_BUF[3]
1	1	0	0	1	0	HEX_V6_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_TCE[0]
Bits						Destination
MAIN[25][11]	MAIN[26][11]	MAIN[27][11]	MAIN[25][9]	MAIN[26][9]	MAIN[28][10]	IMUX_IO_TCE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[10]
0	0	0	0	1	0	SINGLE_W_BUF[11]
0	0	0	1	0	0	SINGLE_W_BUF[12]
0	0	1	0	0	0	SINGLE_W_BUF[13]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_TCE[1]
Bits						Destination
MAIN[27][10]	MAIN[26][10]	MAIN[24][11]	MAIN[31][11]	MAIN[27][9]	MAIN[24][10]	IMUX_IO_TCE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[10]
0	0	0	0	1	0	SINGLE_W_BUF[11]
0	0	0	1	0	0	SINGLE_W_BUF[12]
0	0	1	0	0	0	SINGLE_W_BUF[13]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_TCE[2]
Bits						Destination
MAIN[22][11]	MAIN[21][11]	MAIN[20][11]	MAIN[22][9]	MAIN[21][9]	MAIN[19][10]	IMUX_IO_TCE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[10]
0	0	0	0	1	0	SINGLE_W_BUF[11]
0	0	0	1	0	0	SINGLE_W_BUF[12]
0	0	1	0	0	0	SINGLE_W_BUF[13]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_TCE[3]
Bits						Destination
MAIN[20][10]	MAIN[21][10]	MAIN[23][11]	MAIN[16][11]	MAIN[20][9]	MAIN[23][10]	IMUX_IO_TCE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[10]
0	0	0	0	1	0	SINGLE_W_BUF[11]
0	0	0	1	0	0	SINGLE_W_BUF[12]
0	0	1	0	0	0	SINGLE_W_BUF[13]
0	1	0	1	0	0	HEX_V4_BUF[3]
0	1	1	0	0	0	HEX_V1_BUF[3]
1	1	0	0	0	1	HEX_V6_BUF[3]
1	1	0	0	1	0	HEX_V5_BUF[3]
1	1	0	1	0	0	HEX_V3_BUF[3]
1	1	1	0	0	0	HEX_V2_BUF[3]

virtex IO_E switchbox INT muxes IMUX_IO_O[0]
Bits										Destination
MAIN[41][13]	MAIN[42][13]	MAIN[47][13]	MAIN[46][13]	MAIN[45][14]	MAIN[44][13]	MAIN[43][13]	MAIN[44][14]	MAIN[45][13]	MAIN[46][14]	IMUX_IO_O[0]
										Source
0	0	0	0	0	0	0	0	1	1	PULLUP
0	0	0	0	0	0	1	0	0	1	HEX_H6_BUF[0]
0	0	0	0	0	0	1	0	1	0	OMUX_E1
0	0	0	0	0	0	1	1	1	1	SINGLE_W_BUF[0]
0	0	0	0	0	1	0	0	0	1	HEX_H3_BUF[0]
0	0	0	0	0	1	0	0	1	0	OMUX_E0
0	0	0	0	0	1	0	1	1	1	SINGLE_W_BUF[1]
0	0	0	0	1	0	1	0	1	1	SINGLE_W_BUF[3]
0	0	0	0	1	1	0	0	1	1	SINGLE_W_BUF[2]
0	0	0	1	0	0	0	0	0	1	HEX_H5_BUF[0]
0	0	0	1	0	0	0	0	1	0	OUT_TBUF_E[2]
0	0	0	1	0	0	0	1	1	1	SINGLE_W_BUF[9]
0	0	0	1	1	0	0	0	1	1	SINGLE_W_BUF[4]
0	0	1	0	0	0	0	0	0	1	HEX_H4_BUF[0]
0	0	1	0	0	0	0	0	1	0	OUT_TBUF_E[3]
0	0	1	0	0	0	0	1	1	1	SINGLE_W_BUF[8]
0	0	1	0	1	0	0	0	1	1	SINGLE_W_BUF[5]
0	1	0	0	0	0	0	0	1	0	OUT_TBUF_E[0]
0	1	0	0	0	0	0	1	1	1	SINGLE_W_BUF[6]
0	1	0	0	1	0	0	0	1	1	SINGLE_W_BUF[10]
1	0	0	0	0	0	0	0	1	0	OUT_TBUF_E[1]
1	0	0	0	0	0	0	1	1	1	SINGLE_W_BUF[7]
1	0	0	0	1	0	0	0	1	1	SINGLE_W_BUF[11]

virtex IO_E switchbox INT muxes IMUX_IO_O[1]
Bits										Destination
MAIN[43][14]	MAIN[42][14]	MAIN[43][12]	MAIN[41][12]	MAIN[41][14]	MAIN[39][13]	MAIN[38][13]	MAIN[40][14]	MAIN[40][13]	MAIN[39][14]	IMUX_IO_O[1]
										Source
0	0	0	0	0	0	0	0	1	1	PULLUP
0	0	0	0	0	0	1	0	0	1	HEX_H4_BUF[1]
0	0	0	0	0	0	1	0	1	0	OMUX_E1
0	0	0	0	0	0	1	1	1	1	SINGLE_W_BUF[0]
0	0	0	0	0	1	0	0	0	1	HEX_H3_BUF[1]
0	0	0	0	0	1	0	0	1	0	OMUX_E0
0	0	0	0	0	1	0	1	1	1	SINGLE_W_BUF[1]
0	0	0	0	1	0	1	0	1	1	SINGLE_W_BUF[3]
0	0	0	0	1	1	0	0	1	1	SINGLE_W_BUF[2]
0	0	0	1	0	0	0	0	0	1	HEX_H5_BUF[1]
0	0	0	1	0	0	0	0	1	0	OUT_TBUF_E[2]
0	0	0	1	0	0	0	1	1	1	SINGLE_W_BUF[9]
0	0	0	1	1	0	0	0	1	1	SINGLE_W_BUF[4]
0	0	1	0	0	0	0	0	0	1	HEX_H6_BUF[1]
0	0	1	0	0	0	0	0	1	0	OUT_TBUF_E[3]
0	0	1	0	0	0	0	1	1	1	SINGLE_W_BUF[8]
0	0	1	0	1	0	0	0	1	1	SINGLE_W_BUF[5]
0	1	0	0	0	0	0	0	1	0	OUT_TBUF_E[0]
0	1	0	0	0	0	0	1	1	1	SINGLE_W_BUF[6]
0	1	0	0	1	0	0	0	1	1	SINGLE_W_BUF[10]
1	0	0	0	0	0	0	0	1	0	OUT_TBUF_E[1]
1	0	0	0	0	0	0	1	1	1	SINGLE_W_BUF[7]
1	0	0	0	1	0	0	0	1	1	SINGLE_W_BUF[11]

virtex IO_E switchbox INT muxes IMUX_IO_O[2]
Bits										Destination
MAIN[8][13]	MAIN[9][13]	MAIN[4][12]	MAIN[6][12]	MAIN[7][14]	MAIN[5][14]	MAIN[4][14]	MAIN[6][14]	MAIN[7][13]	MAIN[8][14]	IMUX_IO_O[2]
										Source
0	0	0	0	0	0	0	0	1	1	PULLUP
0	0	0	0	0	0	1	0	1	0	OUT_TBUF_E[1]
0	0	0	0	0	0	1	1	1	1	SINGLE_W_BUF[12]
0	0	0	0	0	1	0	0	1	0	OUT_TBUF_E[0]
0	0	0	0	0	1	0	1	1	1	SINGLE_W_BUF[13]
0	0	0	0	1	0	1	0	1	1	SINGLE_W_BUF[16]
0	0	0	0	1	1	0	0	1	1	SINGLE_W_BUF[17]
0	0	0	1	0	0	0	0	0	1	HEX_H5_BUF[2]
0	0	0	1	0	0	0	0	1	0	OUT_TBUF_E[2]
0	0	0	1	0	0	0	1	1	1	SINGLE_W_BUF[19]
0	0	0	1	1	0	0	0	1	1	SINGLE_W_BUF[14]
0	0	1	0	0	0	0	0	0	1	HEX_H6_BUF[2]
0	0	1	0	0	0	0	0	1	0	OUT_TBUF_E[3]
0	0	1	0	0	0	0	1	1	1	SINGLE_W_BUF[18]
0	0	1	0	1	0	0	0	1	1	SINGLE_W_BUF[15]
0	1	0	0	0	0	0	0	0	1	HEX_H4_BUF[2]
0	1	0	0	0	0	0	0	1	0	OMUX_E1
0	1	0	0	0	0	0	1	1	1	SINGLE_W_BUF[20]
0	1	0	0	1	0	0	0	1	1	SINGLE_W_BUF[23]
1	0	0	0	0	0	0	0	0	1	HEX_H3_BUF[2]
1	0	0	0	0	0	0	0	1	0	OMUX_E0
1	0	0	0	0	0	0	1	1	1	SINGLE_W_BUF[21]
1	0	0	0	1	0	0	0	1	1	SINGLE_W_BUF[22]

virtex IO_E switchbox INT muxes IMUX_IO_O[3]
Bits										Destination
MAIN[3][13]	MAIN[4][13]	MAIN[0][13]	MAIN[1][13]	MAIN[3][14]	MAIN[5][13]	MAIN[6][13]	MAIN[2][14]	MAIN[2][13]	MAIN[1][14]	IMUX_IO_O[3]
										Source
0	0	0	0	0	0	0	0	1	1	PULLUP
0	0	0	0	0	0	1	0	1	0	OUT_TBUF_E[1]
0	0	0	0	0	0	1	1	1	1	SINGLE_W_BUF[12]
0	0	0	0	0	1	0	0	1	0	OUT_TBUF_E[0]
0	0	0	0	0	1	0	1	1	1	SINGLE_W_BUF[13]
0	0	0	0	1	0	1	0	1	1	SINGLE_W_BUF[16]
0	0	0	0	1	1	0	0	1	1	SINGLE_W_BUF[17]
0	0	0	1	0	0	0	0	0	1	HEX_H5_BUF[3]
0	0	0	1	0	0	0	0	1	0	OUT_TBUF_E[2]
0	0	0	1	0	0	0	1	1	1	SINGLE_W_BUF[19]
0	0	0	1	1	0	0	0	1	1	SINGLE_W_BUF[14]
0	0	1	0	0	0	0	0	0	1	HEX_H4_BUF[3]
0	0	1	0	0	0	0	0	1	0	OUT_TBUF_E[3]
0	0	1	0	0	0	0	1	1	1	SINGLE_W_BUF[18]
0	0	1	0	1	0	0	0	1	1	SINGLE_W_BUF[15]
0	1	0	0	0	0	0	0	0	1	HEX_H6_BUF[3]
0	1	0	0	0	0	0	0	1	0	OMUX_E1
0	1	0	0	0	0	0	1	1	1	SINGLE_W_BUF[20]
0	1	0	0	1	0	0	0	1	1	SINGLE_W_BUF[23]
1	0	0	0	0	0	0	0	0	1	HEX_H3_BUF[3]
1	0	0	0	0	0	0	0	1	0	OMUX_E0
1	0	0	0	0	0	0	1	1	1	SINGLE_W_BUF[21]
1	0	0	0	1	0	0	0	1	1	SINGLE_W_BUF[22]

virtex IO_E switchbox INT muxes IMUX_IO_T[0]
Bits						Destination
MAIN[39][10]	MAIN[40][10]	MAIN[41][10]	MAIN[40][9]	MAIN[41][11]	MAIN[42][11]	IMUX_IO_T[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[0]
0	0	0	0	1	0	SINGLE_W_BUF[1]
0	0	0	1	0	0	SINGLE_W_BUF[2]
0	0	1	0	0	0	SINGLE_W_BUF[3]
0	1	0	0	0	1	HEX_V1_BUF[0]
0	1	0	0	1	0	HEX_V4_BUF[0]
1	1	0	0	0	1	HEX_V2_BUF[0]
1	1	0	0	1	0	HEX_V3_BUF[0]
1	1	0	1	0	0	HEX_V5_BUF[0]
1	1	1	0	0	0	HEX_V6_BUF[0]

virtex IO_E switchbox INT muxes IMUX_IO_T[1]
Bits						Destination
MAIN[40][11]	MAIN[39][11]	MAIN[38][10]	MAIN[42][9]	MAIN[43][9]	MAIN[38][11]	IMUX_IO_T[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[0]
0	0	0	0	1	0	SINGLE_W_BUF[1]
0	0	0	1	0	0	SINGLE_W_BUF[2]
0	0	1	0	0	0	SINGLE_W_BUF[3]
0	1	0	0	0	1	HEX_V1_BUF[0]
0	1	0	0	1	0	HEX_V4_BUF[0]
1	1	0	0	0	1	HEX_V2_BUF[0]
1	1	0	0	1	0	HEX_V3_BUF[0]
1	1	0	1	0	0	HEX_V5_BUF[0]
1	1	1	0	0	0	HEX_V6_BUF[0]

virtex IO_E switchbox INT muxes IMUX_IO_T[2]
Bits						Destination
MAIN[45][11]	MAIN[46][11]	MAIN[47][10]	MAIN[46][9]	MAIN[47][9]	MAIN[47][11]	IMUX_IO_T[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[0]
0	0	0	0	1	0	SINGLE_W_BUF[1]
0	0	0	1	0	0	SINGLE_W_BUF[2]
0	0	1	0	0	0	SINGLE_W_BUF[3]
0	1	0	0	0	1	HEX_V1_BUF[0]
0	1	0	0	1	0	HEX_V4_BUF[0]
1	1	0	0	0	1	HEX_V2_BUF[0]
1	1	0	0	1	0	HEX_V3_BUF[0]
1	1	0	1	0	0	HEX_V5_BUF[0]
1	1	1	0	0	0	HEX_V6_BUF[0]

virtex IO_E switchbox INT muxes IMUX_IO_T[3]
Bits						Destination
MAIN[46][10]	MAIN[45][10]	MAIN[44][10]	MAIN[45][9]	MAIN[43][11]	MAIN[44][11]	IMUX_IO_T[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_W_BUF[0]
0	0	0	0	1	0	SINGLE_W_BUF[1]
0	0	0	1	0	0	SINGLE_W_BUF[2]
0	0	1	0	0	0	SINGLE_W_BUF[3]
0	1	0	0	0	1	HEX_V1_BUF[0]
0	1	0	0	1	0	HEX_V4_BUF[0]
1	1	0	0	0	1	HEX_V2_BUF[0]
1	1	0	0	1	0	HEX_V3_BUF[0]
1	1	0	1	0	0	HEX_V5_BUF[0]
1	1	1	0	0	0	HEX_V6_BUF[0]

virtex IO_E switchbox INT muxes OMUX[6]
Bits			Destination
MAIN[30][15]	MAIN[41][15]	MAIN[33][15]	OMUX[6]
			Source
0	0	0	off
0	0	1	OUT_IO_I[1]
0	1	0	OUT_IO_I[2]
1	0	0	OUT_IO_I[3]

virtex IO_E switchbox INT muxes OMUX[7]
Bits			Destination
MAIN[32][15]	MAIN[34][15]	MAIN[42][15]	OMUX[7]
			Source
0	0	0	off
0	0	1	OUT_IO_I[1]
0	1	0	OUT_IO_I[2]
1	0	0	OUT_IO_I[3]

Bels TBUF

virtex IO_E bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	IMUX_TBUF_I[0] invert by !MAIN[18][15]	IMUX_TBUF_I[1] invert by !MAIN[23][15]
T	in	IMUX_TBUF_T[0] invert by MAIN[25][15]	IMUX_TBUF_T[1] invert by MAIN[31][15]

virtex IO_E bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
OUT_A	!MAIN[47][15]	!MAIN[44][15]
OUT_B	!MAIN[46][15]	!MAIN[45][15]

Bels TBUS_WE

virtex IO_E bel TBUS_WE pins
Pin	Direction	TBUS_WE
BUS0	out	OUT_TBUF_E[2]
BUS1	out	OUT_TBUF_E[3]
BUS2	out	OUT_TBUF_E[0]
BUS3	out	OUT_TBUF_E[1]

virtex IO_E bel TBUS_WE attribute bits
Attribute	TBUS_WE

Bels IOI

virtex IO_E bel IOI pins
Pin	Direction	IOI[0]	IOI[1]	IOI[2]	IOI[3]
ICLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[34][14]	IMUX_IO_CLK[2] invert by MAIN[13][14]	IMUX_IO_CLK[3] invert by MAIN[10][14]
OCLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[33][14]	IMUX_IO_CLK[2] invert by MAIN[14][14]	IMUX_IO_CLK[3] invert by MAIN[11][14]
TCLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[32][14]	IMUX_IO_CLK[2] invert by MAIN[15][14]	IMUX_IO_CLK[3] invert by MAIN[12][14]
SR	in	IMUX_IO_SR[0]	IMUX_IO_SR[1] invert by MAIN[33][10]	IMUX_IO_SR[2] invert by MAIN[34][9]	IMUX_IO_SR[3] invert by MAIN[37][9]
ICE	in	IMUX_IO_ICE[0]	IMUX_IO_ICE[1] invert by !MAIN[5][10]	IMUX_IO_ICE[2] invert by !MAIN[4][10]	IMUX_IO_ICE[3] invert by !MAIN[3][9]
OCE	in	IMUX_IO_OCE[0]	IMUX_IO_OCE[1] invert by !MAIN[14][10]	IMUX_IO_OCE[2] invert by !MAIN[13][9]	IMUX_IO_OCE[3] invert by !MAIN[10][9]
TCE	in	IMUX_IO_TCE[0]	IMUX_IO_TCE[1] invert by !MAIN[25][10]	IMUX_IO_TCE[2] invert by !MAIN[23][9]	IMUX_IO_TCE[3] invert by !MAIN[22][10]
O	in	IMUX_IO_O[0]	IMUX_IO_O[1] invert by !MAIN[38][14]	IMUX_IO_O[2] invert by !MAIN[9][14]	IMUX_IO_O[3] invert by !MAIN[0][14]
T	in	IMUX_IO_T[0]	IMUX_IO_T[1] invert by !MAIN[42][10]	IMUX_IO_T[2] invert by !MAIN[43][10]	IMUX_IO_T[3] invert by !MAIN[44][9]
I	out	OUT_IO_I[0]	OUT_IO_I[1]	OUT_IO_I[2]	OUT_IO_I[3]
IQ	out	OUT_IO_IQ[0]	OUT_IO_IQ[1]	OUT_IO_IQ[2]	OUT_IO_IQ[3]

virtex IO_E bel IOI attribute bits
Attribute	IOI[0]	IOI[1]	IOI[2]	IOI[3]
SHORTEN_JTAG_CHAIN	-	!MAIN[10][17]	!MAIN[19][17]	!MAIN[40][17]
FFI_INIT bit 0	-	MAIN[1][16]	MAIN[28][16]	MAIN[31][16]
FFI_READBACK bit 0	-	MAIN[2][17]	MAIN[27][17]	MAIN[32][17]
FFI_LATCH	-	MAIN[3][16]	MAIN[26][16]	MAIN[33][16]
FFI_SR_ENABLE	-	MAIN[4][16]	MAIN[25][16]	MAIN[34][16]
FFI_SR_SYNC	-	MAIN[0][16]	MAIN[29][16]	MAIN[30][16]
FFI_DELAY_ENABLE	-	MAIN[9][17]	MAIN[20][17]	MAIN[39][17]
I_DELAY_ENABLE	-	MAIN[2][16]	MAIN[27][16]	MAIN[32][16]
FFO_INIT bit 0	-	!MAIN[8][16]	!MAIN[21][16]	!MAIN[38][16]
FFO_READBACK bit 0	-	MAIN[8][17]	MAIN[21][17]	MAIN[38][17]
FFO_LATCH	-	MAIN[6][16]	MAIN[23][16]	MAIN[36][16]
FFO_SR_ENABLE	-	MAIN[5][16]	MAIN[24][16]	MAIN[35][16]
FFO_SR_SYNC	-	MAIN[9][16]	MAIN[20][16]	MAIN[39][16]
FFT_INIT bit 0	-	!MAIN[11][16]	!MAIN[18][16]	!MAIN[41][16]
FFT_READBACK bit 0	-	MAIN[12][17]	MAIN[17][17]	MAIN[42][17]
FFT_LATCH	-	MAIN[13][16]	MAIN[16][16]	MAIN[43][16]
FFT_SR_ENABLE	-	MAIN[14][16]	MAIN[15][16]	MAIN[44][16]
FFT_SR_SYNC	-	MAIN[10][16]	MAIN[19][16]	MAIN[40][16]
MUX_O	-	[enum: IO_MUX_O]	[enum: IO_MUX_O]	[enum: IO_MUX_O]
MUX_T	-	[enum: IO_MUX_T]	[enum: IO_MUX_T]	[enum: IO_MUX_T]

virtex IO_E enum IO_MUX_O
IOI[1].MUX_O	MAIN[7][16]
IOI[2].MUX_O	MAIN[22][16]
IOI[3].MUX_O	MAIN[37][16]
O	0
FFO	1

virtex IO_E enum IO_MUX_T
IOI[1].MUX_T	MAIN[12][16]
IOI[2].MUX_T	MAIN[17][16]
IOI[3].MUX_T	MAIN[42][16]
T	0
FFT	1

Bel wires

virtex IO_E bel wires
Wire	Pins
IMUX_TBUF_T[0]	TBUF[0].T
IMUX_TBUF_T[1]	TBUF[1].T
IMUX_TBUF_I[0]	TBUF[0].I
IMUX_TBUF_I[1]	TBUF[1].I
IMUX_IO_CLK[0]	IOI[0].ICLK, IOI[0].OCLK, IOI[0].TCLK
IMUX_IO_CLK[1]	IOI[1].ICLK, IOI[1].OCLK, IOI[1].TCLK
IMUX_IO_CLK[2]	IOI[2].ICLK, IOI[2].OCLK, IOI[2].TCLK
IMUX_IO_CLK[3]	IOI[3].ICLK, IOI[3].OCLK, IOI[3].TCLK
IMUX_IO_SR[0]	IOI[0].SR
IMUX_IO_SR[1]	IOI[1].SR
IMUX_IO_SR[2]	IOI[2].SR
IMUX_IO_SR[3]	IOI[3].SR
IMUX_IO_ICE[0]	IOI[0].ICE
IMUX_IO_ICE[1]	IOI[1].ICE
IMUX_IO_ICE[2]	IOI[2].ICE
IMUX_IO_ICE[3]	IOI[3].ICE
IMUX_IO_OCE[0]	IOI[0].OCE
IMUX_IO_OCE[1]	IOI[1].OCE
IMUX_IO_OCE[2]	IOI[2].OCE
IMUX_IO_OCE[3]	IOI[3].OCE
IMUX_IO_TCE[0]	IOI[0].TCE
IMUX_IO_TCE[1]	IOI[1].TCE
IMUX_IO_TCE[2]	IOI[2].TCE
IMUX_IO_TCE[3]	IOI[3].TCE
IMUX_IO_O[0]	IOI[0].O
IMUX_IO_O[1]	IOI[1].O
IMUX_IO_O[2]	IOI[2].O
IMUX_IO_O[3]	IOI[3].O
IMUX_IO_T[0]	IOI[0].T
IMUX_IO_T[1]	IOI[1].T
IMUX_IO_T[2]	IOI[2].T
IMUX_IO_T[3]	IOI[3].T
OUT_TBUF_E[0]	TBUS_WE.BUS2
OUT_TBUF_E[1]	TBUS_WE.BUS3
OUT_TBUF_E[2]	TBUS_WE.BUS0
OUT_TBUF_E[3]	TBUS_WE.BUS1
OUT_IO_I[0]	IOI[0].I
OUT_IO_I[1]	IOI[1].I
OUT_IO_I[2]	IOI[2].I
OUT_IO_I[3]	IOI[3].I
OUT_IO_IQ[0]	IOI[0].IQ
OUT_IO_IQ[1]	IOI[1].IQ
OUT_IO_IQ[2]	IOI[2].IQ
OUT_IO_IQ[3]	IOI[3].IQ

Bitstream

virtex IO_E rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B17	-	-	IOI[1]: FFI_READBACK bit 0	-	-	-	-	-	IOI[1]: FFO_READBACK bit 0	IOI[1]: FFI_DELAY_ENABLE	IOI[1]: ! SHORTEN_JTAG_CHAIN	-	IOI[1]: FFT_READBACK bit 0	-	-	-	-	IOI[2]: FFT_READBACK bit 0	-	IOI[2]: ! SHORTEN_JTAG_CHAIN	IOI[2]: FFI_DELAY_ENABLE	IOI[2]: FFO_READBACK bit 0	-	-	-	-	-	IOI[2]: FFI_READBACK bit 0	-	-	-	-	IOI[3]: FFI_READBACK bit 0	-	-	-	-	-	IOI[3]: FFO_READBACK bit 0	IOI[3]: FFI_DELAY_ENABLE	IOI[3]: ! SHORTEN_JTAG_CHAIN	-	IOI[3]: FFT_READBACK bit 0	-	-	-	-	-	-	-	-	-	-	-
B16	IOI[1]: FFI_SR_SYNC	IOI[1]: FFI_INIT bit 0	IOI[1]: I_DELAY_ENABLE	IOI[1]: FFI_LATCH	IOI[1]: FFI_SR_ENABLE	IOI[1]: FFO_SR_ENABLE	IOI[1]: FFO_LATCH	IOI[1]: MUX_O bit 0	IOI[1]: ! FFO_INIT bit 0	IOI[1]: FFO_SR_SYNC	IOI[1]: FFT_SR_SYNC	IOI[1]: ! FFT_INIT bit 0	IOI[1]: MUX_T bit 0	IOI[1]: FFT_LATCH	IOI[1]: FFT_SR_ENABLE	IOI[2]: FFT_SR_ENABLE	IOI[2]: FFT_LATCH	IOI[2]: MUX_T bit 0	IOI[2]: ! FFT_INIT bit 0	IOI[2]: FFT_SR_SYNC	IOI[2]: FFO_SR_SYNC	IOI[2]: ! FFO_INIT bit 0	IOI[2]: MUX_O bit 0	IOI[2]: FFO_LATCH	IOI[2]: FFO_SR_ENABLE	IOI[2]: FFI_SR_ENABLE	IOI[2]: FFI_LATCH	IOI[2]: I_DELAY_ENABLE	IOI[2]: FFI_INIT bit 0	IOI[2]: FFI_SR_SYNC	IOI[3]: FFI_SR_SYNC	IOI[3]: FFI_INIT bit 0	IOI[3]: I_DELAY_ENABLE	IOI[3]: FFI_LATCH	IOI[3]: FFI_SR_ENABLE	IOI[3]: FFO_SR_ENABLE	IOI[3]: FFO_LATCH	IOI[3]: MUX_O bit 0	IOI[3]: ! FFO_INIT bit 0	IOI[3]: FFO_SR_SYNC	IOI[3]: FFT_SR_SYNC	IOI[3]: ! FFT_INIT bit 0	IOI[3]: MUX_T bit 0	IOI[3]: FFT_LATCH	IOI[3]: FFT_SR_ENABLE	-	-	-	-	-	-	-	-	-
B15	INT: mux LV_MUX[0] bit 0	INT: mux LV_MUX[0] bit 6	INT: buffer LV[0] ← LV_MUX[0]	INT: mux LV_MUX[0] bit 1	INT: mux LV_MUX[0] bit 8	INT: mux LV_MUX[6] bit 6	INT: mux LV_MUX[6] bit 5	INT: mux LV_MUX[0] bit 5	INT: mux LV_MUX[6] bit 8	INT: mux LV_MUX[6] bit 2	INT: buffer LV[6] ← LV_MUX[6]	INT: mux LV_MUX[0] bit 3	INT: mux LV_MUX[0] bit 2	INT: mux LV_MUX[6] bit 1	INT: mux LV_MUX[0] bit 4	INT: mux LV_MUX[6] bit 4	INT: mux IMUX_TBUF_I[0] bit 0	INT: mux IMUX_TBUF_I[0] bit 1	TBUF[0]: !invert I	INT: mux IMUX_TBUF_I[0] bit 4	INT: mux IMUX_TBUF_I[0] bit 3	INT: mux IMUX_TBUF_I[1] bit 3	INT: mux IMUX_TBUF_I[1] bit 4	TBUF[1]: !invert I	INT: mux IMUX_TBUF_I[1] bit 0	TBUF[0]: invert T	INT: mux IMUX_TBUF_T[0] bit 4	INT: mux IMUX_TBUF_T[0] bit 3	INT: mux IMUX_TBUF_T[1] bit 3	INT: mux IMUX_TBUF_T[1] bit 4	INT: mux OMUX[6] bit 2	TBUF[1]: invert T	INT: mux OMUX[7] bit 2	INT: mux OMUX[6] bit 0	INT: mux OMUX[7] bit 1	-	-	INT: mux IMUX_TBUF_I[0] bit 2	INT: mux IMUX_TBUF_I[1] bit 2	INT: mux IMUX_TBUF_I[1] bit 1	INT: mux IMUX_TBUF_T[0] bit 2	INT: mux OMUX[6] bit 1	INT: mux OMUX[7] bit 0	INT: mux IMUX_TBUF_T[1] bit 2	TBUF[1]: ! OUT_A	TBUF[1]: ! OUT_B	TBUF[0]: ! OUT_B	TBUF[0]: ! OUT_A	-	-	-	-	-	-
B14	IOI[3]: !invert O	INT: mux IMUX_IO_O[3] bit 0	INT: mux IMUX_IO_O[3] bit 2	INT: mux IMUX_IO_O[3] bit 5	INT: mux IMUX_IO_O[2] bit 3	INT: mux IMUX_IO_O[2] bit 4	INT: mux IMUX_IO_O[2] bit 2	INT: mux IMUX_IO_O[2] bit 5	INT: mux IMUX_IO_O[2] bit 0	IOI[2]: !invert O	IOI[3]: invert ICLK	IOI[3]: invert OCLK	IOI[3]: invert TCLK	IOI[2]: invert ICLK	IOI[2]: invert OCLK	IOI[2]: invert TCLK	INT: mux IMUX_IO_CLK[2] bit 9	INT: mux IMUX_IO_CLK[3] bit 9	INT: mux IMUX_IO_CLK[3] bit 8	INT: mux IMUX_IO_CLK[2] bit 10	INT: mux IMUX_IO_CLK[3] bit 0	INT: mux IMUX_IO_CLK[3] bit 6	INT: mux IMUX_IO_CLK[3] bit 3	INT: mux IMUX_IO_CLK[2] bit 5	INT: mux IMUX_IO_CLK[1] bit 5	INT: mux IMUX_IO_CLK[0] bit 3	INT: mux IMUX_IO_CLK[0] bit 6	INT: mux IMUX_IO_CLK[0] bit 0	INT: mux IMUX_IO_CLK[1] bit 10	INT: mux IMUX_IO_CLK[0] bit 8	INT: mux IMUX_IO_CLK[0] bit 9	INT: mux IMUX_IO_CLK[1] bit 9	IOI[1]: invert TCLK	IOI[1]: invert OCLK	IOI[1]: invert ICLK	-	-	-	IOI[1]: !invert O	INT: mux IMUX_IO_O[1] bit 0	INT: mux IMUX_IO_O[1] bit 2	INT: mux IMUX_IO_O[1] bit 5	INT: mux IMUX_IO_O[1] bit 8	INT: mux IMUX_IO_O[1] bit 9	INT: mux IMUX_IO_O[0] bit 2	INT: mux IMUX_IO_O[0] bit 5	INT: mux IMUX_IO_O[0] bit 0	-	-	-	-	-	-	-
B13	INT: mux IMUX_IO_O[3] bit 7	INT: mux IMUX_IO_O[3] bit 6	INT: mux IMUX_IO_O[3] bit 1	INT: mux IMUX_IO_O[3] bit 9	INT: mux IMUX_IO_O[3] bit 8	INT: mux IMUX_IO_O[3] bit 4	INT: mux IMUX_IO_O[3] bit 3	INT: mux IMUX_IO_O[2] bit 1	INT: mux IMUX_IO_O[2] bit 9	INT: mux IMUX_IO_O[2] bit 8	-	INT: mux IMUX_IO_CLK[3] bit 7	-	INT: mux IMUX_IO_CLK[2] bit 3	INT: mux IMUX_IO_CLK[2] bit 7	INT: mux IMUX_IO_CLK[2] bit 1	INT: mux IMUX_IO_CLK[2] bit 4	INT: mux IMUX_IO_CLK[3] bit 5	INT: mux IMUX_IO_CLK[2] bit 0	INT: mux IMUX_IO_CLK[2] bit 8	INT: mux IMUX_IO_CLK[3] bit 1	INT: mux IMUX_IO_CLK[2] bit 2	INT: mux IMUX_IO_CLK[3] bit 2	INT: mux IMUX_IO_CLK[3] bit 4	INT: mux IMUX_IO_CLK[0] bit 4	INT: mux IMUX_IO_CLK[0] bit 2	INT: mux IMUX_IO_CLK[1] bit 2	INT: mux IMUX_IO_CLK[0] bit 1	INT: mux IMUX_IO_CLK[1] bit 8	INT: mux IMUX_IO_CLK[1] bit 0	INT: mux IMUX_IO_CLK[0] bit 5	INT: mux IMUX_IO_CLK[1] bit 4	INT: mux IMUX_IO_CLK[1] bit 1	INT: mux IMUX_IO_CLK[1] bit 7	INT: mux IMUX_IO_CLK[1] bit 3	-	INT: mux IMUX_IO_CLK[0] bit 7	-	INT: mux IMUX_IO_O[1] bit 3	INT: mux IMUX_IO_O[1] bit 4	INT: mux IMUX_IO_O[1] bit 1	INT: mux IMUX_IO_O[0] bit 9	INT: mux IMUX_IO_O[0] bit 8	INT: mux IMUX_IO_O[0] bit 3	INT: mux IMUX_IO_O[0] bit 4	INT: mux IMUX_IO_O[0] bit 1	INT: mux IMUX_IO_O[0] bit 6	INT: mux IMUX_IO_O[0] bit 7	-	-	-	-	-	-
B12	INT: mux LH_MUX[6] bit 0	INT: mux LV_MUX[6] bit 0	INT: buffer LH[6] ← LH_MUX[6]	-	INT: mux IMUX_IO_O[2] bit 7	INT: buffer LH[5] ← LH_MUX[5]	INT: mux IMUX_IO_O[2] bit 6	INT: mux LH_MUX[5] bit 0	INT: mux LH_MUX[4] bit 0	INT: mux LV_MUX[0] bit 7	INT: buffer LH[4] ← LH_MUX[4]	-	INT: mux LV_MUX[6] bit 7	INT: buffer LH[3] ← LH_MUX[3]	INT: mux LV_MUX[6] bit 3	INT: mux LH_MUX[3] bit 0	INT: mux LH_MUX[2] bit 0	INT: mux IMUX_IO_CLK[3] bit 10	INT: buffer LH[2] ← LH_MUX[2]	-	-	INT: buffer LH[1] ← LH_MUX[1]	INT: mux IMUX_IO_CLK[2] bit 6	-	-	INT: mux IMUX_IO_CLK[1] bit 6	INT: buffer LH[0] ← LH_MUX[0]	INT: mux IMUX_TBUF_T[0] bit 0	INT: mux IMUX_TBUF_T[1] bit 0	INT: buffer LH[7] ← LH_MUX[7]	INT: mux IMUX_IO_CLK[0] bit 10	INT: mux LH_MUX[7] bit 0	INT: mux LH_MUX[8] bit 0	INT: mux IMUX_TBUF_T[1] bit 1	INT: buffer LH[8] ← LH_MUX[8]	INT: mux IMUX_TBUF_T[0] bit 1	-	INT: buffer LH[9] ← LH_MUX[9]	-	INT: mux LH_MUX[9] bit 0	INT: mux LH_MUX[10] bit 0	INT: mux IMUX_IO_O[1] bit 6	INT: buffer LH[10] ← LH_MUX[10]	INT: mux IMUX_IO_O[1] bit 7	-	INT: buffer LH[11] ← LH_MUX[11]	-	INT: mux LH_MUX[11] bit 0	-	-	-	-	-	-
B11	INT: mux IMUX_IO_ICE[2] bit 3	INT: mux IMUX_IO_ICE[2] bit 4	INT: mux IMUX_IO_ICE[2] bit 5	INT: mux IMUX_IO_ICE[3] bit 3	INT: mux IMUX_IO_ICE[3] bit 2	INT: mux IMUX_IO_ICE[0] bit 3	INT: mux IMUX_IO_ICE[0] bit 2	INT: mux IMUX_IO_ICE[1] bit 5	INT: mux IMUX_IO_ICE[1] bit 4	INT: mux IMUX_IO_ICE[1] bit 3	INT: mux IMUX_IO_OCE[2] bit 3	INT: mux IMUX_IO_OCE[2] bit 4	INT: mux IMUX_IO_OCE[2] bit 5	INT: mux IMUX_IO_OCE[3] bit 3	INT: mux IMUX_IO_OCE[0] bit 3	INT: mux IMUX_IO_OCE[0] bit 2	INT: mux IMUX_IO_TCE[3] bit 2	INT: mux IMUX_IO_OCE[1] bit 5	INT: mux IMUX_IO_OCE[1] bit 4	INT: mux IMUX_IO_OCE[1] bit 3	INT: mux IMUX_IO_TCE[2] bit 3	INT: mux IMUX_IO_TCE[2] bit 4	INT: mux IMUX_IO_TCE[2] bit 5	INT: mux IMUX_IO_TCE[3] bit 3	INT: mux IMUX_IO_TCE[1] bit 3	INT: mux IMUX_IO_TCE[0] bit 5	INT: mux IMUX_IO_TCE[0] bit 4	INT: mux IMUX_IO_TCE[0] bit 3	INT: mux IMUX_IO_SR[1] bit 0	INT: mux IMUX_IO_SR[1] bit 4	INT: mux IMUX_IO_SR[1] bit 5	INT: mux IMUX_IO_TCE[1] bit 2	INT: mux IMUX_IO_SR[0] bit 1	INT: mux IMUX_IO_SR[0] bit 0	INT: mux IMUX_IO_SR[3] bit 0	INT: mux IMUX_IO_SR[2] bit 5	INT: mux IMUX_IO_SR[2] bit 4	INT: mux IMUX_IO_SR[2] bit 0	INT: mux IMUX_IO_T[1] bit 0	INT: mux IMUX_IO_T[1] bit 4	INT: mux IMUX_IO_T[1] bit 5	INT: mux IMUX_IO_T[0] bit 1	INT: mux IMUX_IO_T[0] bit 0	INT: mux IMUX_IO_T[3] bit 1	INT: mux IMUX_IO_T[3] bit 0	INT: mux IMUX_IO_T[2] bit 5	INT: mux IMUX_IO_T[2] bit 4	INT: mux IMUX_IO_T[2] bit 0	-	-	-	-	-	-
B10	INT: mux IMUX_IO_ICE[2] bit 0	INT: mux IMUX_IO_ICE[3] bit 5	INT: mux IMUX_IO_ICE[3] bit 4	INT: mux IMUX_IO_ICE[3] bit 0	IOI[2]: !invert ICE	IOI[1]: !invert ICE	INT: mux IMUX_IO_ICE[0] bit 0	INT: mux IMUX_IO_ICE[0] bit 4	INT: mux IMUX_IO_ICE[0] bit 5	INT: mux IMUX_IO_ICE[1] bit 0	INT: mux IMUX_IO_OCE[2] bit 1	INT: mux IMUX_IO_OCE[3] bit 5	INT: mux IMUX_IO_OCE[3] bit 4	INT: mux IMUX_IO_OCE[3] bit 1	IOI[1]: !invert OCE	-	INT: mux IMUX_IO_OCE[0] bit 1	INT: mux IMUX_IO_OCE[0] bit 4	INT: mux IMUX_IO_OCE[0] bit 5	INT: mux IMUX_IO_TCE[2] bit 0	INT: mux IMUX_IO_TCE[3] bit 5	INT: mux IMUX_IO_TCE[3] bit 4	IOI[3]: !invert TCE	INT: mux IMUX_IO_TCE[3] bit 0	INT: mux IMUX_IO_TCE[1] bit 0	IOI[1]: !invert TCE	INT: mux IMUX_IO_TCE[1] bit 4	INT: mux IMUX_IO_TCE[1] bit 5	INT: mux IMUX_IO_TCE[0] bit 0	INT: mux IMUX_IO_SR[0] bit 5	INT: mux IMUX_IO_SR[0] bit 4	INT: mux IMUX_IO_SR[0] bit 3	-	IOI[1]: invert SR	INT: mux IMUX_IO_SR[3] bit 3	INT: mux IMUX_IO_SR[3] bit 4	INT: mux IMUX_IO_SR[3] bit 5	INT: mux IMUX_IO_SR[2] bit 3	INT: mux IMUX_IO_T[1] bit 3	INT: mux IMUX_IO_T[0] bit 5	INT: mux IMUX_IO_T[0] bit 4	INT: mux IMUX_IO_T[0] bit 3	IOI[1]: !invert T	IOI[2]: !invert T	INT: mux IMUX_IO_T[3] bit 3	INT: mux IMUX_IO_T[3] bit 4	INT: mux IMUX_IO_T[3] bit 5	INT: mux IMUX_IO_T[2] bit 3	-	-	-	-	-	-
B9	INT: mux IMUX_IO_ICE[2] bit 2	INT: mux IMUX_IO_ICE[2] bit 1	INT: mux IMUX_IO_ICE[3] bit 1	IOI[3]: !invert ICE	INT: mux IMUX_IO_ICE[1] bit 2	INT: mux IMUX_IO_ICE[1] bit 1	-	INT: mux IMUX_IO_ICE[0] bit 1	INT: mux IMUX_IO_OCE[3] bit 2	INT: mux IMUX_IO_OCE[2] bit 0	IOI[3]: !invert OCE	INT: mux IMUX_IO_OCE[2] bit 2	INT: mux IMUX_IO_OCE[3] bit 0	IOI[2]: !invert OCE	INT: mux IMUX_IO_OCE[0] bit 0	INT: mux IMUX_IO_OCE[1] bit 0	INT: mux IMUX_IO_OCE[1] bit 2	-	-	INT: mux IMUX_IO_OCE[1] bit 1	INT: mux IMUX_IO_TCE[3] bit 1	INT: mux IMUX_IO_TCE[2] bit 1	INT: mux IMUX_IO_TCE[2] bit 2	IOI[2]: !invert TCE	-	INT: mux IMUX_IO_TCE[0] bit 2	INT: mux IMUX_IO_TCE[0] bit 1	INT: mux IMUX_IO_TCE[1] bit 1	INT: mux IMUX_IO_SR[1] bit 3	-	-	INT: mux IMUX_IO_SR[1] bit 1	INT: mux IMUX_IO_SR[1] bit 2	INT: mux IMUX_IO_SR[0] bit 2	IOI[2]: invert SR	INT: mux IMUX_IO_SR[3] bit 2	INT: mux IMUX_IO_SR[2] bit 1	IOI[3]: invert SR	INT: mux IMUX_IO_SR[2] bit 2	INT: mux IMUX_IO_SR[3] bit 1	INT: mux IMUX_IO_T[0] bit 2	-	INT: mux IMUX_IO_T[1] bit 2	INT: mux IMUX_IO_T[1] bit 1	IOI[3]: !invert T	INT: mux IMUX_IO_T[3] bit 2	INT: mux IMUX_IO_T[2] bit 2	INT: mux IMUX_IO_T[2] bit 1	-	-	-	-	-	-
B8	INT: pass SINGLE_W[23] ← HEX_V0[3]	INT: pass SINGLE_W[22] ← HEX_V3[3]	INT: pass SINGLE_W[22] ← OUT_IO_IQ[1]	INT: pass SINGLE_W[21] ← HEX_V6[3]	INT: pass SINGLE_W[21] ← OUT_IO_IQ[2]	INT: pass SINGLE_W[21] ← OUT_TBUF_E[0]	INT: pass SINGLE_W[20] ← OUT_IO_IQ[3]	INT: pass SINGLE_W[20] ← HEX_V0[3]	-	INT: pass SINGLE_W[19] ← HEX_V3[3]	INT: pass SINGLE_W[18] ← OUT_IO_I[1]	INT: pass SINGLE_W[18] ← OUT_TBUF_E[0]	INT: pass SINGLE_W[17] ← HEX_V0[2]	INT: pass SINGLE_W[16] ← HEX_V3[2]	INT: pass SINGLE_W[16] ← OUT_IO_I[3]	INT: pass SINGLE_W[15] ← HEX_V6[2]	-	INT: pass SINGLE_W[15] ← OUT_TBUF_E[1]	INT: pass SINGLE_W[14] ← OUT_IO_IQ[1]	INT: pass SINGLE_W[14] ← HEX_V0[2]	INT: pass SINGLE_W[13] ← OUT_IO_IQ[2]	INT: pass SINGLE_W[13] ← HEX_V3[2]	INT: pass SINGLE_W[12] ← OUT_IO_IQ[3]	INT: pass SINGLE_W[12] ← OUT_TBUF_E[1]	INT: pass SINGLE_W[11] ← HEX_V0[1]	INT: pass SINGLE_W[10] ← HEX_V3[1]	INT: pass SINGLE_W[10] ← OUT_IO_I[1]	INT: pass SINGLE_W[9] ← HEX_V6[1]	INT: pass SINGLE_W[9] ← OUT_IO_I[2]	INT: pass SINGLE_W[9] ← OUT_TBUF_E[2]	INT: pass SINGLE_W[8] ← OUT_IO_I[3]	INT: pass SINGLE_W[8] ← HEX_V0[1]	-	INT: pass SINGLE_W[7] ← HEX_V3[1]	INT: pass SINGLE_W[6] ← OUT_IO_IQ[1]	INT: pass SINGLE_W[6] ← OUT_TBUF_E[2]	INT: pass SINGLE_W[5] ← HEX_V0[0]	INT: pass SINGLE_W[4] ← HEX_V3[0]	INT: pass SINGLE_W[4] ← OUT_IO_IQ[3]	INT: pass SINGLE_W[3] ← HEX_V6[0]	-	INT: pass SINGLE_W[3] ← OUT_TBUF_E[3]	INT: pass SINGLE_W[2] ← OUT_IO_I[1]	INT: pass SINGLE_W[2] ← HEX_V0[0]	INT: pass SINGLE_W[1] ← OUT_IO_I[2]	INT: pass SINGLE_W[1] ← HEX_V3[0]	INT: pass SINGLE_W[0] ← OUT_IO_I[3]	INT: pass SINGLE_W[0] ← OUT_TBUF_E[3]	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	INT: pass SINGLE_W[18] ← HEX_V6[3]	INT: pass SINGLE_W[17] ← OUT_IO_I[2]	-	-	-	-	-	-	-	-	-	-	INT: pass SINGLE_W[12] ← HEX_V6[2]	-	-	-	-	-	-	-	-	-	-	-	INT: pass SINGLE_W[6] ← HEX_V6[1]	INT: pass SINGLE_W[5] ← OUT_IO_IQ[2]	-	-	-	-	-	-	-	-	-	-	INT: pass SINGLE_W[0] ← HEX_V6[0]	-	-	-	-	-	-
B6	INT: buffer HEX_V0[3] ← HEX_V0_MUX[3]	INT: mux HEX_V6_MUX[3] bit 5	INT: mux HEX_V6_MUX[3] bit 3	INT: mux HEX_V0_MUX[3] bit 1	INT: mux HEX_V0_MUX[3] bit 5	INT: mux HEX_V0_MUX[3] bit 6	INT: mux HEX_V0_MUX[3] bit 4	INT: mux HEX_V0_MUX[3] bit 2	INT: mux HEX_V0_MUX[3] bit 3	INT: mux HEX_V6_MUX[3] bit 0	INT: mux HEX_V6_MUX[3] bit 6	INT: buffer HEX_V6[3] ← HEX_V6_MUX[3]	INT: buffer HEX_V0[2] ← HEX_V0_MUX[2]	INT: mux HEX_V6_MUX[2] bit 5	INT: mux HEX_V6_MUX[2] bit 3	INT: mux HEX_V0_MUX[2] bit 1	INT: mux HEX_V0_MUX[2] bit 5	INT: mux HEX_V0_MUX[2] bit 6	INT: mux HEX_V0_MUX[2] bit 4	INT: mux HEX_V0_MUX[2] bit 2	INT: mux HEX_V0_MUX[2] bit 3	INT: mux HEX_V6_MUX[2] bit 0	INT: mux HEX_V6_MUX[2] bit 6	INT: buffer HEX_V6[2] ← HEX_V6_MUX[2]	INT: buffer HEX_V0[1] ← HEX_V0_MUX[1]	INT: mux HEX_V6_MUX[1] bit 5	INT: mux HEX_V6_MUX[1] bit 3	INT: mux HEX_V0_MUX[1] bit 1	INT: mux HEX_V0_MUX[1] bit 5	INT: mux HEX_V0_MUX[1] bit 6	INT: mux HEX_V0_MUX[1] bit 4	INT: mux HEX_V0_MUX[1] bit 2	INT: mux HEX_V0_MUX[1] bit 3	INT: mux HEX_V6_MUX[1] bit 0	INT: mux HEX_V6_MUX[1] bit 6	INT: buffer HEX_V6[1] ← HEX_V6_MUX[1]	INT: buffer HEX_V0[0] ← HEX_V0_MUX[0]	INT: mux HEX_V6_MUX[0] bit 5	INT: mux HEX_V6_MUX[0] bit 3	INT: mux HEX_V0_MUX[0] bit 1	INT: mux HEX_V0_MUX[0] bit 5	INT: mux HEX_V0_MUX[0] bit 6	INT: mux HEX_V0_MUX[0] bit 4	INT: mux HEX_V0_MUX[0] bit 2	INT: mux HEX_V0_MUX[0] bit 3	INT: mux HEX_V6_MUX[0] bit 0	INT: mux HEX_V6_MUX[0] bit 6	INT: buffer HEX_V6[0] ← HEX_V6_MUX[0]	-	-	-	-	-	-
B5	INT: mux HEX_V6_MUX[3] bit 2	INT: mux HEX_V0_MUX[3] bit 0	-	-	-	-	-	-	-	-	INT: mux HEX_V6_MUX[3] bit 4	INT: mux HEX_V6_MUX[3] bit 1	INT: mux HEX_V6_MUX[2] bit 2	INT: mux HEX_V0_MUX[2] bit 0	-	-	-	-	-	-	-	-	INT: mux HEX_V6_MUX[2] bit 4	INT: mux HEX_V6_MUX[2] bit 1	INT: mux HEX_V6_MUX[1] bit 2	INT: mux HEX_V0_MUX[1] bit 0	-	-	-	-	-	-	-	-	INT: mux HEX_V6_MUX[1] bit 4	INT: mux HEX_V6_MUX[1] bit 1	INT: mux HEX_V6_MUX[0] bit 2	INT: mux HEX_V0_MUX[0] bit 0	-	-	-	-	-	-	-	-	INT: mux HEX_V6_MUX[0] bit 4	INT: mux HEX_V6_MUX[0] bit 1	-	-	-	-	-	-
B4	INT: buffer HEX_H6[3] ← HEX_H6_MUX[3]	INT: mux HEX_H5_MUX[3] bit 3	INT: mux HEX_H6_MUX[3] bit 1	INT: buffer HEX_H5[3] ← HEX_H5_MUX[3]	INT: buffer HEX_H4[3] ← HEX_H4_MUX[3]	-	-	INT: buffer HEX_H3[3] ← HEX_H3_MUX[3]	INT: buffer HEX_H2[3] ← HEX_H2_MUX[3]	-	-	INT: buffer HEX_H1[3] ← HEX_H1_MUX[3]	INT: buffer HEX_H1[2] ← HEX_H1_MUX[2]	-	-	INT: buffer HEX_H2[2] ← HEX_H2_MUX[2]	INT: buffer HEX_H3[2] ← HEX_H3_MUX[2]	-	-	INT: buffer HEX_H4[2] ← HEX_H4_MUX[2]	INT: buffer HEX_H5[2] ← HEX_H5_MUX[2]	INT: mux HEX_H6_MUX[2] bit 3	INT: mux HEX_H5_MUX[2] bit 2	INT: buffer HEX_H6[2] ← HEX_H6_MUX[2]	INT: buffer HEX_H6[1] ← HEX_H6_MUX[1]	INT: mux HEX_H5_MUX[1] bit 2	INT: mux HEX_H6_MUX[1] bit 3	INT: buffer HEX_H5[1] ← HEX_H5_MUX[1]	INT: buffer HEX_H4[1] ← HEX_H4_MUX[1]	-	-	INT: buffer HEX_H3[1] ← HEX_H3_MUX[1]	INT: buffer HEX_H2[1] ← HEX_H2_MUX[1]	-	-	INT: buffer HEX_H1[1] ← HEX_H1_MUX[1]	INT: buffer HEX_H1[0] ← HEX_H1_MUX[0]	-	-	INT: buffer HEX_H2[0] ← HEX_H2_MUX[0]	INT: buffer HEX_H3[0] ← HEX_H3_MUX[0]	-	-	INT: buffer HEX_H4[0] ← HEX_H4_MUX[0]	INT: buffer HEX_H5[0] ← HEX_H5_MUX[0]	INT: mux HEX_H6_MUX[0] bit 2	INT: mux HEX_H5_MUX[0] bit 1	INT: buffer HEX_H6[0] ← HEX_H6_MUX[0]	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	INT: mux HEX_H6_MUX[3] bit 0	INT: mux HEX_H6_MUX[3] bit 5	INT: mux HEX_H6_MUX[3] bit 4	INT: mux HEX_H5_MUX[3] bit 0	INT: mux HEX_H4_MUX[3] bit 2	INT: mux HEX_H3_MUX[3] bit 2	INT: mux HEX_H3_MUX[3] bit 1	INT: mux HEX_H3_MUX[3] bit 0	INT: mux HEX_H2_MUX[3] bit 2	INT: mux HEX_H1_MUX[3] bit 2	-	INT: mux HEX_H1_MUX[3] bit 0	INT: mux HEX_H1_MUX[2] bit 0	INT: mux HEX_H1_MUX[2] bit 1	-	-	INT: mux HEX_H3_MUX[2] bit 0	INT: mux HEX_H3_MUX[2] bit 1	INT: mux HEX_H3_MUX[2] bit 3	INT: mux HEX_H4_MUX[2] bit 3	INT: mux HEX_H5_MUX[2] bit 0	-	INT: mux HEX_H6_MUX[2] bit 4	INT: mux HEX_H6_MUX[2] bit 0	INT: mux HEX_H6_MUX[1] bit 0	INT: mux HEX_H6_MUX[1] bit 5	INT: mux HEX_H6_MUX[1] bit 4	INT: mux HEX_H5_MUX[1] bit 0	INT: mux HEX_H4_MUX[1] bit 1	INT: mux HEX_H3_MUX[1] bit 1	INT: mux HEX_H3_MUX[1] bit 2	INT: mux HEX_H3_MUX[1] bit 0	INT: mux HEX_H2_MUX[1] bit 2	INT: mux HEX_H1_MUX[1] bit 2	-	INT: mux HEX_H1_MUX[1] bit 0	INT: mux HEX_H1_MUX[0] bit 0	INT: mux HEX_H1_MUX[0] bit 1	-	-	INT: mux HEX_H3_MUX[0] bit 0	INT: mux HEX_H3_MUX[0] bit 1	INT: mux HEX_H3_MUX[0] bit 3	INT: mux HEX_H4_MUX[0] bit 3	INT: mux HEX_H5_MUX[0] bit 0	-	INT: mux HEX_H6_MUX[0] bit 4	INT: mux HEX_H6_MUX[0] bit 0	-	-	-	-	-	-
B1	INT: mux HEX_W0[3] bit 3	INT: mux HEX_W0[3] bit 0	INT: mux HEX_W1[3] bit 0	INT: mux HEX_W1[3] bit 1	INT: mux HEX_W0[3] bit 1	INT: mux HEX_W0[3] bit 2	INT: mux HEX_W1[3] bit 2	INT: mux HEX_W1[3] bit 5	INT: mux HEX_W0[3] bit 5	INT: mux HEX_W0[3] bit 4	INT: mux HEX_W1[3] bit 4	INT: mux HEX_W1[3] bit 3	INT: mux HEX_W0[1] bit 3	INT: mux HEX_W0[1] bit 1	INT: mux HEX_W1[1] bit 1	INT: mux HEX_W1[1] bit 2	INT: mux HEX_W0[1] bit 2	INT: mux HEX_W0[1] bit 0	INT: mux HEX_W1[1] bit 0	INT: mux HEX_W1[1] bit 5	INT: mux HEX_W0[1] bit 5	INT: mux HEX_W0[1] bit 4	INT: mux HEX_W1[1] bit 4	INT: mux HEX_W1[1] bit 3	INT: mux HEX_W0[2] bit 3	INT: mux HEX_W0[2] bit 2	INT: mux HEX_W1[2] bit 2	INT: mux HEX_W1[2] bit 0	INT: mux HEX_W0[2] bit 0	INT: mux HEX_W0[2] bit 1	INT: mux HEX_W1[2] bit 1	INT: mux HEX_W1[2] bit 5	INT: mux HEX_W0[2] bit 5	INT: mux HEX_W0[2] bit 4	INT: mux HEX_W1[2] bit 4	INT: mux HEX_W1[2] bit 3	INT: mux HEX_W0[0] bit 3	INT: mux HEX_W0[0] bit 0	INT: mux HEX_W1[0] bit 0	INT: mux HEX_W1[0] bit 1	INT: mux HEX_W0[0] bit 1	INT: mux HEX_W0[0] bit 2	INT: mux HEX_W1[0] bit 2	-	-	-	-	INT: mux HEX_W1[0] bit 3	-	-	-	-	-	-
B0	INT: mux HEX_H6_MUX[3] bit 3	INT: mux HEX_H6_MUX[3] bit 2	INT: mux HEX_H5_MUX[3] bit 2	INT: mux HEX_H5_MUX[3] bit 1	INT: mux HEX_H4_MUX[3] bit 0	-	-	INT: mux HEX_H4_MUX[3] bit 1	INT: mux HEX_H2_MUX[3] bit 0	INT: mux HEX_H1_MUX[3] bit 1	INT: mux HEX_H2_MUX[3] bit 1	-	INT: mux HEX_H2_MUX[2] bit 1	INT: mux HEX_H2_MUX[2] bit 2	INT: mux HEX_H1_MUX[2] bit 2	INT: mux HEX_H2_MUX[2] bit 0	INT: mux HEX_H4_MUX[2] bit 1	INT: mux HEX_H4_MUX[2] bit 2	INT: mux HEX_H3_MUX[2] bit 2	INT: mux HEX_H4_MUX[2] bit 0	INT: mux HEX_H5_MUX[2] bit 1	-	INT: mux HEX_H6_MUX[2] bit 1	INT: mux HEX_H6_MUX[2] bit 2	INT: mux HEX_H6_MUX[1] bit 2	INT: mux HEX_H6_MUX[1] bit 1	INT: mux HEX_H5_MUX[1] bit 1	-	INT: mux HEX_H4_MUX[1] bit 0	-	-	INT: mux HEX_H4_MUX[1] bit 2	INT: mux HEX_H2_MUX[1] bit 0	INT: mux HEX_H1_MUX[1] bit 1	INT: mux HEX_H2_MUX[1] bit 1	-	INT: mux HEX_H2_MUX[0] bit 1	INT: mux HEX_H2_MUX[0] bit 2	INT: mux HEX_H1_MUX[0] bit 2	INT: mux HEX_H2_MUX[0] bit 0	INT: mux HEX_H4_MUX[0] bit 1	INT: mux HEX_H4_MUX[0] bit 2	INT: mux HEX_H3_MUX[0] bit 2	INT: mux HEX_H4_MUX[0] bit 0	INT: mux HEX_H5_MUX[0] bit 2	-	INT: mux HEX_H6_MUX[0] bit 3	INT: mux HEX_H6_MUX[0] bit 1	-	-	-	-	-	-

Tile IO_S

Cells: 1

Switchbox INT

virtex IO_S switchbox INT permanent buffers
Destination	Source
GCLK_BUF[0]	GCLK_LEAF[0]
GCLK_BUF[1]	GCLK_LEAF[1]
GCLK_BUF[2]	GCLK_LEAF[2]
GCLK_BUF[3]	GCLK_LEAF[3]
SINGLE_N_BUF[0]	SINGLE_N[0]
SINGLE_N_BUF[1]	SINGLE_N[1]
SINGLE_N_BUF[2]	SINGLE_N[2]
SINGLE_N_BUF[3]	SINGLE_N[3]
SINGLE_N_BUF[4]	SINGLE_N[4]
SINGLE_N_BUF[5]	SINGLE_N[5]
SINGLE_N_BUF[6]	SINGLE_N[6]
SINGLE_N_BUF[7]	SINGLE_N[7]
SINGLE_N_BUF[8]	SINGLE_N[8]
SINGLE_N_BUF[9]	SINGLE_N[9]
SINGLE_N_BUF[10]	SINGLE_N[10]
SINGLE_N_BUF[11]	SINGLE_N[11]
SINGLE_N_BUF[12]	SINGLE_N[12]
SINGLE_N_BUF[13]	SINGLE_N[13]
SINGLE_N_BUF[14]	SINGLE_N[14]
SINGLE_N_BUF[15]	SINGLE_N[15]
SINGLE_N_BUF[16]	SINGLE_N[16]
SINGLE_N_BUF[17]	SINGLE_N[17]
SINGLE_N_BUF[18]	SINGLE_N[18]
SINGLE_N_BUF[19]	SINGLE_N[19]
SINGLE_N_BUF[20]	SINGLE_N[20]
SINGLE_N_BUF[21]	SINGLE_N[21]
SINGLE_N_BUF[22]	SINGLE_N[22]
SINGLE_N_BUF[23]	SINGLE_N[23]
HEX_H1_BUF[0]	HEX_H1[0]
HEX_H1_BUF[1]	HEX_H1[1]
HEX_H1_BUF[2]	HEX_H1[2]
HEX_H1_BUF[3]	HEX_H1[3]
HEX_H2_BUF[0]	HEX_H2[0]
HEX_H2_BUF[1]	HEX_H2[1]
HEX_H2_BUF[2]	HEX_H2[2]
HEX_H2_BUF[3]	HEX_H2[3]
HEX_H3_BUF[0]	HEX_H3[0]
HEX_H3_BUF[1]	HEX_H3[1]
HEX_H3_BUF[2]	HEX_H3[2]
HEX_H3_BUF[3]	HEX_H3[3]
HEX_H4_BUF[0]	HEX_H4[0]
HEX_H4_BUF[1]	HEX_H4[1]
HEX_H4_BUF[2]	HEX_H4[2]
HEX_H4_BUF[3]	HEX_H4[3]
HEX_H5_BUF[0]	HEX_H5[0]
HEX_H5_BUF[1]	HEX_H5[1]
HEX_H5_BUF[2]	HEX_H5[2]
HEX_H5_BUF[3]	HEX_H5[3]
HEX_H6_BUF[0]	HEX_H6[0]
HEX_H6_BUF[1]	HEX_H6[1]
HEX_H6_BUF[2]	HEX_H6[2]
HEX_H6_BUF[3]	HEX_H6[3]
HEX_V0_BUF[0]	HEX_V0[0]
HEX_V0_BUF[1]	HEX_V0[1]
HEX_V0_BUF[2]	HEX_V0[2]
HEX_V0_BUF[3]	HEX_V0[3]
HEX_V1_BUF[0]	HEX_V1[0]
HEX_V1_BUF[1]	HEX_V1[1]
HEX_V1_BUF[2]	HEX_V1[2]
HEX_V1_BUF[3]	HEX_V1[3]
HEX_V2_BUF[0]	HEX_V2[0]
HEX_V2_BUF[1]	HEX_V2[1]
HEX_V2_BUF[2]	HEX_V2[2]
HEX_V2_BUF[3]	HEX_V2[3]
HEX_V3_BUF[0]	HEX_V3[0]
HEX_V3_BUF[1]	HEX_V3[1]
HEX_V3_BUF[2]	HEX_V3[2]
HEX_V3_BUF[3]	HEX_V3[3]
HEX_V4_BUF[0]	HEX_V4[0]
HEX_V4_BUF[1]	HEX_V4[1]
HEX_V4_BUF[2]	HEX_V4[2]
HEX_V4_BUF[3]	HEX_V4[3]
HEX_V5_BUF[0]	HEX_V5[0]
HEX_V5_BUF[1]	HEX_V5[1]
HEX_V5_BUF[2]	HEX_V5[2]
HEX_V5_BUF[3]	HEX_V5[3]
HEX_N2[0]	HEX_S3[0]
HEX_N2[1]	HEX_S3[1]
HEX_N2[2]	HEX_S3[2]
HEX_N2[3]	HEX_S3[3]
HEX_N3[0]	HEX_S4[0]
HEX_N3[1]	HEX_S4[1]
HEX_N3[2]	HEX_S4[2]
HEX_N3[3]	HEX_S4[3]
HEX_N4[0]	HEX_S5[0]
HEX_N4[1]	HEX_S5[1]
HEX_N4[2]	HEX_S5[2]
HEX_N4[3]	HEX_S5[3]
HEX_N5[0]	HEX_S6[0]
HEX_N5[1]	HEX_S6[1]
HEX_N5[2]	HEX_S6[2]
HEX_N5[3]	HEX_S6[3]

virtex IO_S switchbox INT programmable buffers
Destination	Source	Bit
HEX_H0[0]	HEX_H0_MUX[0]	MAIN[36][6]
HEX_H0[1]	HEX_H0_MUX[1]	MAIN[24][6]
HEX_H0[2]	HEX_H0_MUX[2]	MAIN[12][6]
HEX_H0[3]	HEX_H0_MUX[3]	MAIN[0][6]
HEX_H0[4]	HEX_H0_MUX[4]	MAIN[45][15]
HEX_H0[5]	HEX_H0_MUX[5]	MAIN[19][15]
HEX_H6[0]	HEX_H6_MUX[0]	MAIN[47][6]
HEX_H6[1]	HEX_H6_MUX[1]	MAIN[35][6]
HEX_H6[2]	HEX_H6_MUX[2]	MAIN[23][6]
HEX_H6[3]	HEX_H6_MUX[3]	MAIN[11][6]
HEX_H6[4]	HEX_H6_MUX[4]	MAIN[28][15]
HEX_H6[5]	HEX_H6_MUX[5]	MAIN[37][15]
HEX_V0[0]	HEX_V0_MUX[0]	MAIN[47][4]
HEX_V0[1]	HEX_V0_MUX[1]	MAIN[24][4]
HEX_V0[2]	HEX_V0_MUX[2]	MAIN[23][4]
HEX_V0[3]	HEX_V0_MUX[3]	MAIN[0][4]
HEX_V1[0]	HEX_V1_MUX[0]	MAIN[44][4]
HEX_V1[1]	HEX_V1_MUX[1]	MAIN[27][4]
HEX_V1[2]	HEX_V1_MUX[2]	MAIN[20][4]
HEX_V1[3]	HEX_V1_MUX[3]	MAIN[3][4]
HEX_V2[0]	HEX_V2_MUX[0]	MAIN[43][4]
HEX_V2[1]	HEX_V2_MUX[1]	MAIN[28][4]
HEX_V2[2]	HEX_V2_MUX[2]	MAIN[19][4]
HEX_V2[3]	HEX_V2_MUX[3]	MAIN[4][4]
HEX_V3[0]	HEX_V3_MUX[0]	MAIN[40][4]
HEX_V3[1]	HEX_V3_MUX[1]	MAIN[31][4]
HEX_V3[2]	HEX_V3_MUX[2]	MAIN[16][4]
HEX_V3[3]	HEX_V3_MUX[3]	MAIN[7][4]
HEX_V4[0]	HEX_V4_MUX[0]	MAIN[39][4]
HEX_V4[1]	HEX_V4_MUX[1]	MAIN[32][4]
HEX_V4[2]	HEX_V4_MUX[2]	MAIN[15][4]
HEX_V4[3]	HEX_V4_MUX[3]	MAIN[8][4]
HEX_V5[0]	HEX_V5_MUX[0]	MAIN[36][4]
HEX_V5[1]	HEX_V5_MUX[1]	MAIN[35][4]
HEX_V5[2]	HEX_V5_MUX[2]	MAIN[12][4]
HEX_V5[3]	HEX_V5_MUX[3]	MAIN[11][4]
LH[0]	LH_MUX[0]	MAIN[10][15]
LH[6]	LH_MUX[6]	MAIN[3][15]
LV[0]	LV_MUX[0]	MAIN[26][12]
LV[1]	LV_MUX[1]	MAIN[29][12]
LV[2]	LV_MUX[2]	MAIN[34][12]
LV[3]	LV_MUX[3]	MAIN[37][12]
LV[4]	LV_MUX[4]	MAIN[42][12]
LV[5]	LV_MUX[5]	MAIN[45][12]
LV[6]	LV_MUX[6]	MAIN[21][12]
LV[7]	LV_MUX[7]	MAIN[18][12]
LV[8]	LV_MUX[8]	MAIN[13][12]
LV[9]	LV_MUX[9]	MAIN[10][12]
LV[10]	LV_MUX[10]	MAIN[5][12]
LV[11]	LV_MUX[11]	MAIN[2][12]

virtex IO_S switchbox INT pass gates
Destination	Source	Bit
SINGLE_N[0]	HEX_H6[0]	MAIN[47][8]
SINGLE_N[1]	HEX_H3[0]	MAIN[45][8]
SINGLE_N[1]	OUT_IO_I[2]	MAIN[44][8]
SINGLE_N[2]	HEX_H0[0]	MAIN[43][8]
SINGLE_N[2]	OUT_IO_I[1]	MAIN[42][8]
SINGLE_N[3]	HEX_H6[0]	MAIN[41][8]
SINGLE_N[4]	HEX_H3[0]	MAIN[38][8]
SINGLE_N[5]	HEX_H0[0]	MAIN[36][8]
SINGLE_N[5]	OUT_IO_IQ[2]	MAIN[37][8]
SINGLE_N[6]	HEX_H6[1]	MAIN[35][8]
SINGLE_N[6]	OUT_IO_IQ[1]	MAIN[34][8]
SINGLE_N[7]	HEX_H3[1]	MAIN[33][8]
SINGLE_N[8]	HEX_H0[1]	MAIN[31][8]
SINGLE_N[9]	HEX_H6[1]	MAIN[29][8]
SINGLE_N[9]	OUT_IO_I[2]	MAIN[28][8]
SINGLE_N[10]	HEX_H3[1]	MAIN[26][8]
SINGLE_N[10]	OUT_IO_I[1]	MAIN[27][8]
SINGLE_N[11]	HEX_H0[1]	MAIN[24][8]
SINGLE_N[12]	HEX_H6[2]	MAIN[23][8]
SINGLE_N[13]	HEX_H3[2]	MAIN[21][8]
SINGLE_N[13]	OUT_IO_IQ[2]	MAIN[20][8]
SINGLE_N[14]	HEX_H0[2]	MAIN[19][8]
SINGLE_N[14]	OUT_IO_IQ[1]	MAIN[18][8]
SINGLE_N[15]	HEX_H6[2]	MAIN[17][8]
SINGLE_N[16]	HEX_H3[2]	MAIN[14][8]
SINGLE_N[17]	HEX_H0[2]	MAIN[12][8]
SINGLE_N[17]	OUT_IO_I[2]	MAIN[13][8]
SINGLE_N[18]	HEX_H6[3]	MAIN[11][8]
SINGLE_N[18]	OUT_IO_I[1]	MAIN[10][8]
SINGLE_N[19]	HEX_H3[3]	MAIN[9][8]
SINGLE_N[20]	HEX_H0[3]	MAIN[7][8]
SINGLE_N[21]	HEX_H6[3]	MAIN[5][8]
SINGLE_N[21]	OUT_IO_IQ[2]	MAIN[4][8]
SINGLE_N[22]	HEX_H3[3]	MAIN[2][8]
SINGLE_N[22]	OUT_IO_IQ[1]	MAIN[3][8]
SINGLE_N[23]	HEX_H0[3]	MAIN[0][8]

virtex IO_S switchbox INT muxes HEX_H0_MUX[0]
Bits							Destination
MAIN[41][6]	MAIN[40][6]	MAIN[42][6]	MAIN[44][6]	MAIN[37][5]	MAIN[39][6]	MAIN[43][6]	HEX_H0_MUX[0]
							Source
0	0	0	0	0	0	1	HEX_H6[0]
0	0	0	0	0	1	0	HEX_V0[3]
0	0	0	0	1	0	0	HEX_V3[2]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H0_MUX[1]
Bits							Destination
MAIN[29][6]	MAIN[28][6]	MAIN[30][6]	MAIN[32][6]	MAIN[25][5]	MAIN[27][6]	MAIN[31][6]	HEX_H0_MUX[1]
							Source
0	0	0	0	0	0	1	HEX_H6[1]
0	0	0	0	0	1	0	HEX_V0[0]
0	0	0	0	1	0	0	HEX_V3[3]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H0_MUX[2]
Bits							Destination
MAIN[17][6]	MAIN[16][6]	MAIN[18][6]	MAIN[20][6]	MAIN[13][5]	MAIN[15][6]	MAIN[19][6]	HEX_H0_MUX[2]
							Source
0	0	0	0	0	0	1	HEX_H6[2]
0	0	0	0	0	1	0	HEX_V0[1]
0	0	0	0	1	0	0	HEX_V3[0]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H0_MUX[3]
Bits							Destination
MAIN[5][6]	MAIN[4][6]	MAIN[6][6]	MAIN[8][6]	MAIN[1][5]	MAIN[3][6]	MAIN[7][6]	HEX_H0_MUX[3]
							Source
0	0	0	0	0	0	1	HEX_H6[3]
0	0	0	0	0	1	0	HEX_V0[2]
0	0	0	0	1	0	0	HEX_V3[1]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H0_MUX[4]
Bits							Destination
MAIN[41][15]	MAIN[39][15]	MAIN[40][15]	MAIN[43][15]	MAIN[44][15]	MAIN[35][15]	MAIN[34][15]	HEX_H0_MUX[4]
							Source
0	0	0	0	0	0	1	SINGLE_N_BUF[0]
0	0	0	0	0	1	0	SINGLE_N_BUF[7]
0	0	0	0	1	0	0	HEX_H6[4]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	1	0	0	0	OUT_IO_I[1]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	1	0	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H0_MUX[5]
Bits							Destination
MAIN[23][15]	MAIN[25][15]	MAIN[22][15]	MAIN[20][15]	MAIN[18][15]	MAIN[27][15]	MAIN[29][15]	HEX_H0_MUX[5]
							Source
0	0	0	0	0	0	1	SINGLE_N_BUF[12]
0	0	0	0	0	1	0	SINGLE_N_BUF[19]
0	0	0	0	1	0	0	HEX_H6[5]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	1	0	0	0	OUT_IO_I[1]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	1	0	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H6_MUX[0]
Bits							Destination
MAIN[46][6]	MAIN[37][6]	MAIN[46][5]	MAIN[38][6]	MAIN[45][6]	MAIN[47][5]	MAIN[36][5]	HEX_H6_MUX[0]
							Source
0	0	0	0	0	0	1	HEX_H0[0]
0	0	0	0	0	1	0	HEX_V0[0]
0	0	0	0	1	0	0	HEX_V3[2]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H6_MUX[1]
Bits							Destination
MAIN[34][6]	MAIN[25][6]	MAIN[34][5]	MAIN[26][6]	MAIN[33][6]	MAIN[35][5]	MAIN[24][5]	HEX_H6_MUX[1]
							Source
0	0	0	0	0	0	1	HEX_H0[1]
0	0	0	0	0	1	0	HEX_V0[1]
0	0	0	0	1	0	0	HEX_V3[3]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H6_MUX[2]
Bits							Destination
MAIN[22][6]	MAIN[13][6]	MAIN[22][5]	MAIN[14][6]	MAIN[21][6]	MAIN[23][5]	MAIN[12][5]	HEX_H6_MUX[2]
							Source
0	0	0	0	0	0	1	HEX_H0[2]
0	0	0	0	0	1	0	HEX_V0[2]
0	0	0	0	1	0	0	HEX_V3[0]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H6_MUX[3]
Bits							Destination
MAIN[10][6]	MAIN[1][6]	MAIN[10][5]	MAIN[2][6]	MAIN[9][6]	MAIN[11][5]	MAIN[0][5]	HEX_H6_MUX[3]
							Source
0	0	0	0	0	0	1	HEX_H0[3]
0	0	0	0	0	1	0	HEX_V0[3]
0	0	0	0	1	0	0	HEX_V3[1]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[2]
0	1	1	0	1	0	0	OUT_IO_I[1]
1	0	1	0	0	1	0	OUT_IO_IQ[2]
1	0	1	0	1	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H6_MUX[4]
Bits							Destination
MAIN[24][15]	MAIN[31][15]	MAIN[16][15]	MAIN[21][15]	MAIN[17][15]	MAIN[26][15]	MAIN[30][15]	HEX_H6_MUX[4]
							Source
0	0	0	0	0	0	1	SINGLE_N_BUF[12]
0	0	0	0	0	1	0	SINGLE_N_BUF[19]
0	0	0	0	1	0	0	HEX_H0[4]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	1	0	0	0	OUT_IO_I[1]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	1	0	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_H6_MUX[5]
Bits							Destination
MAIN[36][15]	MAIN[32][15]	MAIN[47][15]	MAIN[42][15]	MAIN[46][15]	MAIN[38][15]	MAIN[33][15]	HEX_H6_MUX[5]
							Source
0	0	0	0	0	0	1	SINGLE_N_BUF[0]
0	0	0	0	0	1	0	SINGLE_N_BUF[7]
0	0	0	0	1	0	0	HEX_H0[5]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	1	0	0	0	OUT_IO_I[1]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	1	0	0	0	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V0_MUX[0]
Bits					Destination
MAIN[46][2]	MAIN[46][0]	MAIN[45][4]	MAIN[47][0]	MAIN[47][2]	HEX_V0_MUX[0]
					Source
0	0	1	1	1	HEX_H0[1]
0	1	0	1	1	HEX_H3[3]
0	1	1	0	1	HEX_H6[0]
0	1	1	1	0	LV[0]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_I[1]

virtex IO_S switchbox INT muxes HEX_V0_MUX[1]
Bits					Destination
MAIN[26][2]	MAIN[26][4]	MAIN[24][0]	MAIN[25][0]	MAIN[24][2]	HEX_V0_MUX[1]
					Source
0	0	1	1	1	HEX_H0[2]
0	1	0	1	1	HEX_H3[0]
0	1	1	0	1	HEX_H6[1]
0	1	1	1	0	LV[0]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_V0_MUX[2]
Bits					Destination
MAIN[22][2]	MAIN[21][4]	MAIN[23][0]	MAIN[22][0]	MAIN[23][2]	HEX_V0_MUX[2]
					Source
0	0	1	1	1	HEX_H0[3]
0	1	0	1	1	HEX_H3[1]
0	1	1	0	1	HEX_H6[2]
0	1	1	1	0	LV[6]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V0_MUX[3]
Bits					Destination
MAIN[2][2]	MAIN[0][0]	MAIN[1][0]	MAIN[2][4]	MAIN[0][2]	HEX_V0_MUX[3]
					Source
0	0	1	1	1	HEX_H0[0]
0	1	0	1	1	HEX_H3[2]
0	1	1	0	1	HEX_H6[3]
0	1	1	1	0	LV[6]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V1_MUX[0]
Bits			Destination
MAIN[44][0]	MAIN[46][4]	MAIN[44][2]	HEX_V1_MUX[0]
			Source
0	0	0	LV[11]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V1_MUX[1]
Bits		Destination
MAIN[26][0]	MAIN[27][2]	HEX_V1_MUX[1]
		Source
0	0	LV[11]
0	1	off
1	1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_V1_MUX[2]
Bits		Destination
MAIN[22][4]	MAIN[20][2]	HEX_V1_MUX[2]
		Source
0	0	LV[5]
0	1	off
1	1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V1_MUX[3]
Bits			Destination
MAIN[2][0]	MAIN[3][0]	MAIN[3][2]	HEX_V1_MUX[3]
			Source
0	0	0	LV[5]
0	0	1	off
0	1	1	OUT_IO_I[2]
1	0	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V2_MUX[0]
Bits			Destination
MAIN[41][0]	MAIN[40][0]	MAIN[43][0]	HEX_V2_MUX[0]
			Source
0	0	0	LV[10]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V2_MUX[1]
Bits		Destination
MAIN[28][2]	MAIN[28][0]	HEX_V2_MUX[1]
		Source
0	0	LV[10]
0	1	off
1	1	OUT_IO_I[1]

virtex IO_S switchbox INT muxes HEX_V2_MUX[2]
Bits			Destination
MAIN[17][0]	MAIN[16][0]	MAIN[19][0]	HEX_V2_MUX[2]
			Source
0	0	0	LV[4]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_V2_MUX[3]
Bits		Destination
MAIN[4][2]	MAIN[4][0]	HEX_V2_MUX[3]
		Source
0	0	LV[4]
0	1	off
1	1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V3_MUX[0]
Bits			Destination
MAIN[42][0]	MAIN[41][2]	MAIN[40][2]	HEX_V3_MUX[0]
			Source
0	0	0	LV[9]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V3_MUX[1]
Bits		Destination
MAIN[29][2]	MAIN[31][2]	HEX_V3_MUX[1]
		Source
0	0	LV[9]
0	1	off
1	1	OUT_IO_I[1]

virtex IO_S switchbox INT muxes HEX_V3_MUX[2]
Bits			Destination
MAIN[18][0]	MAIN[17][2]	MAIN[16][2]	HEX_V3_MUX[2]
			Source
0	0	0	LV[3]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_V3_MUX[3]
Bits		Destination
MAIN[5][2]	MAIN[7][2]	HEX_V3_MUX[3]
		Source
0	0	LV[3]
0	1	off
1	1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_V4_MUX[0]
Bits		Destination
MAIN[36][0]	MAIN[39][0]	HEX_V4_MUX[0]
		Source
0	0	LV[8]
0	1	off
1	1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_V4_MUX[1]
Bits			Destination
MAIN[32][2]	MAIN[34][0]	MAIN[32][0]	HEX_V4_MUX[1]
			Source
0	0	0	LV[8]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V4_MUX[2]
Bits		Destination
MAIN[12][0]	MAIN[15][0]	HEX_V4_MUX[2]
		Source
0	0	LV[2]
0	1	off
1	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V4_MUX[3]
Bits			Destination
MAIN[8][2]	MAIN[10][0]	MAIN[8][0]	HEX_V4_MUX[3]
			Source
0	0	0	LV[2]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_V5_MUX[0]
Bits		Destination
MAIN[37][2]	MAIN[36][2]	HEX_V5_MUX[0]
		Source
0	0	LV[7]
0	1	off
1	1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_V5_MUX[1]
Bits			Destination
MAIN[33][2]	MAIN[33][0]	MAIN[35][2]	HEX_V5_MUX[1]
			Source
0	0	0	LV[7]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V5_MUX[2]
Bits		Destination
MAIN[13][2]	MAIN[12][2]	HEX_V5_MUX[2]
		Source
0	0	LV[1]
0	1	off
1	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_V5_MUX[3]
Bits			Destination
MAIN[9][2]	MAIN[9][0]	MAIN[11][2]	HEX_V5_MUX[3]
			Source
0	0	0	LV[1]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes HEX_N0[0]
Bits				Destination
MAIN[41][1]	MAIN[40][1]	MAIN[37][1]	MAIN[36][1]	HEX_N0[0]
				Source
0	1	1	1	HEX_H0[2]
1	0	1	1	HEX_H3[1]
1	1	0	1	HEX_H6[0]
1	1	1	0	HEX_S1[0]
1	1	1	1	off

virtex IO_S switchbox INT muxes HEX_N0[1]
Bits						Destination
MAIN[20][1]	MAIN[21][1]	MAIN[16][1]	MAIN[13][1]	MAIN[17][1]	MAIN[12][1]	HEX_N0[1]
						Source
0	0	0	1	1	1	HEX_H0[1]
0	0	1	0	1	1	HEX_H3[0]
0	0	1	1	0	1	HEX_H6[3]
0	0	1	1	1	0	HEX_S1[1]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[1]
1	0	1	1	1	1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_N0[2]
Bits						Destination
MAIN[32][1]	MAIN[33][1]	MAIN[25][1]	MAIN[29][1]	MAIN[28][1]	MAIN[24][1]	HEX_N0[2]
						Source
0	0	0	1	1	1	HEX_H0[0]
0	0	1	0	1	1	HEX_H3[3]
0	0	1	1	0	1	HEX_H6[2]
0	0	1	1	1	0	HEX_S1[2]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_N0[3]
Bits				Destination
MAIN[5][1]	MAIN[4][1]	MAIN[1][1]	MAIN[0][1]	HEX_N0[3]
				Source
0	1	1	1	HEX_H0[3]
1	0	1	1	HEX_H3[2]
1	1	0	1	HEX_H6[1]
1	1	1	0	HEX_S1[3]
1	1	1	1	off

virtex IO_S switchbox INT muxes HEX_N1[0]
Bits				Destination
MAIN[42][1]	MAIN[39][1]	MAIN[38][1]	MAIN[47][1]	HEX_N1[0]
				Source
0	1	1	1	HEX_H0[2]
1	0	1	1	HEX_H3[1]
1	1	0	1	HEX_H6[0]
1	1	1	0	HEX_S2[0]
1	1	1	1	off

virtex IO_S switchbox INT muxes HEX_N1[1]
Bits						Destination
MAIN[19][1]	MAIN[22][1]	MAIN[15][1]	MAIN[14][1]	MAIN[18][1]	MAIN[23][1]	HEX_N1[1]
						Source
0	0	0	1	1	1	HEX_H0[1]
0	0	1	0	1	1	HEX_H3[0]
0	0	1	1	0	1	HEX_H6[3]
0	0	1	1	1	0	HEX_S2[1]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[1]
1	0	1	1	1	1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes HEX_N1[2]
Bits						Destination
MAIN[31][1]	MAIN[34][1]	MAIN[26][1]	MAIN[30][1]	MAIN[27][1]	MAIN[35][1]	HEX_N1[2]
						Source
0	0	0	1	1	1	HEX_H0[0]
0	0	1	0	1	1	HEX_H3[3]
0	0	1	1	0	1	HEX_H6[2]
0	0	1	1	1	0	HEX_S2[2]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes HEX_N1[3]
Bits				Destination
MAIN[6][1]	MAIN[3][1]	MAIN[2][1]	MAIN[11][1]	HEX_N1[3]
				Source
0	1	1	1	HEX_H0[3]
1	0	1	1	HEX_H3[2]
1	1	0	1	HEX_H6[1]
1	1	1	0	HEX_S2[3]
1	1	1	1	off

virtex IO_S switchbox INT muxes LH_MUX[0]
Bits									Destination
MAIN[9][15]	MAIN[12][12]	MAIN[4][15]	MAIN[6][15]	MAIN[15][15]	MAIN[14][12]	MAIN[8][15]	MAIN[13][15]	MAIN[1][12]	LH_MUX[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	1	SINGLE_N_BUF[5]
0	0	0	0	0	0	0	1	0	SINGLE_N_BUF[6]
0	0	0	0	0	0	1	0	0	SINGLE_N_BUF[10]
0	0	0	0	0	1	0	0	0	SINGLE_N_BUF[11]
0	0	0	0	1	0	0	0	0	SINGLE_N_BUF[17]
0	0	0	1	0	0	0	0	0	SINGLE_N_BUF[18]
0	0	1	0	0	0	0	0	0	SINGLE_N_BUF[22]
0	1	0	0	0	0	0	0	0	SINGLE_N_BUF[23]
1	0	0	0	0	0	0	1	0	OUT_IO_IQ[2]
1	0	0	0	0	0	1	0	0	OUT_IO_I[2]
1	0	0	0	1	0	0	0	0	OUT_IO_IQ[1]
1	0	1	0	0	0	0	0	0	OUT_IO_I[1]

virtex IO_S switchbox INT muxes LH_MUX[6]
Bits									Destination
MAIN[5][15]	MAIN[9][12]	MAIN[1][15]	MAIN[7][15]	MAIN[14][15]	MAIN[11][15]	MAIN[12][15]	MAIN[2][15]	MAIN[0][15]	LH_MUX[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	1	SINGLE_N_BUF[5]
0	0	0	0	0	0	0	1	0	SINGLE_N_BUF[6]
0	0	0	0	0	0	1	0	0	SINGLE_N_BUF[10]
0	0	0	0	0	1	0	0	0	SINGLE_N_BUF[11]
0	0	0	0	1	0	0	0	0	SINGLE_N_BUF[17]
0	0	0	1	0	0	0	0	0	SINGLE_N_BUF[18]
0	0	1	0	0	0	0	0	0	SINGLE_N_BUF[22]
0	1	0	0	0	0	0	0	0	SINGLE_N_BUF[23]
1	0	0	0	0	0	0	1	0	OUT_IO_IQ[2]
1	0	0	0	0	0	1	0	0	OUT_IO_I[2]
1	0	0	0	1	0	0	0	0	OUT_IO_IQ[1]
1	0	1	0	0	0	0	0	0	OUT_IO_I[1]

virtex IO_S switchbox INT muxes LV_MUX[0]
Bits	Destination
LV_MUX[0]
	Source
HEX_H6[5]

virtex IO_S switchbox INT muxes LV_MUX[1]
Bits	Destination
LV_MUX[1]
	Source
HEX_H5[5]

virtex IO_S switchbox INT muxes LV_MUX[2]
Bits	Destination
MAIN[32][12]	LV_MUX[2]
	Source
0	HEX_H4[5]
1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes LV_MUX[3]
Bits	Destination
MAIN[39][12]	LV_MUX[3]
	Source
0	HEX_H3[5]
1	OUT_IO_IQ[1]

virtex IO_S switchbox INT muxes LV_MUX[4]
Bits	Destination
MAIN[40][12]	LV_MUX[4]
	Source
0	HEX_H2[5]
1	OUT_IO_I[1]

virtex IO_S switchbox INT muxes LV_MUX[5]
Bits	Destination
MAIN[47][12]	LV_MUX[5]
	Source
0	HEX_H1[5]
1	OUT_IO_I[1]

virtex IO_S switchbox INT muxes LV_MUX[6]
Bits	Destination
MAIN[23][12]	LV_MUX[6]
	Source
0	HEX_H6[4]
1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes LV_MUX[7]
Bits	Destination
MAIN[16][12]	LV_MUX[7]
	Source
0	HEX_H5[4]
1	OUT_IO_IQ[2]

virtex IO_S switchbox INT muxes LV_MUX[8]
Bits	Destination
MAIN[15][12]	LV_MUX[8]
	Source
0	HEX_H4[4]
1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes LV_MUX[9]
Bits	Destination
MAIN[8][12]	LV_MUX[9]
	Source
0	HEX_H3[4]
1	OUT_IO_I[2]

virtex IO_S switchbox INT muxes LV_MUX[10]
Bits	Destination
LV_MUX[10]
	Source
HEX_H2[4]

virtex IO_S switchbox INT muxes LV_MUX[11]
Bits	Destination
LV_MUX[11]
	Source
HEX_H1[4]

virtex IO_S switchbox INT muxes IMUX_IO_CLK[0]
Bits												Destination
MAIN[30][12]	MAIN[30][14]	MAIN[29][14]	MAIN[36][13]	MAIN[26][14]	MAIN[30][13]	MAIN[24][13]	MAIN[25][14]	MAIN[25][13]	MAIN[27][13]	MAIN[27][14]	MAIN[35][13]	IMUX_IO_CLK[0]
												Source
0	0	0	0	0	0	1	1	1	1	1	1	GCLK_BUF[0]
0	0	0	0	0	1	0	1	1	1	1	1	GCLK_BUF[1]
0	0	0	0	0	1	1	0	1	1	1	1	GCLK_BUF[2]
0	0	0	0	0	1	1	1	0	1	1	1	GCLK_BUF[3]
0	0	0	0	0	1	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	0	1	1	HEX_V4_BUF[2]
0	0	0	1	0	1	1	1	1	1	0	1	HEX_H5_BUF[2]
0	0	0	1	0	1	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	1	SINGLE_N_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	1	HEX_H1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	1	HEX_H4_BUF[2]
0	0	1	0	0	1	1	1	1	1	1	0	HEX_V1_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[9]
0	1	0	0	0	1	1	1	1	0	1	1	HEX_V0_BUF[2]
0	1	0	0	0	1	1	1	1	1	0	1	HEX_H6_BUF[2]
0	1	0	0	0	1	1	1	1	1	1	0	HEX_V3_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	1	HEX_H2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	1	HEX_H3_BUF[2]
1	0	0	0	0	1	1	1	1	1	1	0	HEX_V2_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[15]

virtex IO_S switchbox INT muxes IMUX_IO_CLK[1]
Bits												Destination
MAIN[28][14]	MAIN[31][14]	MAIN[28][13]	MAIN[33][13]	MAIN[25][12]	MAIN[24][14]	MAIN[31][13]	MAIN[34][13]	MAIN[26][13]	MAIN[32][13]	MAIN[29][13]	MAIN[37][13]	IMUX_IO_CLK[1]
												Source
0	0	0	0	0	0	1	1	1	1	1	1	GCLK_BUF[0]
0	0	0	0	0	1	0	1	1	1	1	1	GCLK_BUF[1]
0	0	0	0	0	1	1	0	1	1	1	1	GCLK_BUF[2]
0	0	0	0	0	1	1	1	0	1	1	1	GCLK_BUF[3]
0	0	0	0	0	1	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	0	1	1	HEX_V4_BUF[2]
0	0	0	1	0	1	1	1	1	1	0	1	HEX_H5_BUF[2]
0	0	0	1	0	1	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	1	SINGLE_N_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	1	HEX_H1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	1	HEX_H4_BUF[2]
0	0	1	0	0	1	1	1	1	1	1	0	HEX_V1_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[9]
0	1	0	0	0	1	1	1	1	0	1	1	HEX_V0_BUF[2]
0	1	0	0	0	1	1	1	1	1	0	1	HEX_H6_BUF[2]
0	1	0	0	0	1	1	1	1	1	1	0	HEX_V3_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	1	HEX_H2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	1	HEX_H3_BUF[2]
1	0	0	0	0	1	1	1	1	1	1	0	HEX_V2_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[15]

virtex IO_S switchbox INT muxes IMUX_IO_CLK[2]
Bits												Destination
MAIN[19][14]	MAIN[16][14]	MAIN[19][13]	MAIN[14][13]	MAIN[22][12]	MAIN[23][14]	MAIN[16][13]	MAIN[13][13]	MAIN[21][13]	MAIN[15][13]	MAIN[18][13]	MAIN[10][13]	IMUX_IO_CLK[2]
												Source
0	0	0	0	0	0	1	1	1	1	1	1	GCLK_BUF[0]
0	0	0	0	0	1	0	1	1	1	1	1	GCLK_BUF[1]
0	0	0	0	0	1	1	0	1	1	1	1	GCLK_BUF[2]
0	0	0	0	0	1	1	1	0	1	1	1	GCLK_BUF[3]
0	0	0	0	0	1	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	0	1	1	HEX_V4_BUF[2]
0	0	0	1	0	1	1	1	1	1	0	1	HEX_H5_BUF[2]
0	0	0	1	0	1	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	1	SINGLE_N_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	1	HEX_H1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	1	HEX_H4_BUF[2]
0	0	1	0	0	1	1	1	1	1	1	0	HEX_V1_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[9]
0	1	0	0	0	1	1	1	1	0	1	1	HEX_V0_BUF[2]
0	1	0	0	0	1	1	1	1	1	0	1	HEX_H6_BUF[2]
0	1	0	0	0	1	1	1	1	1	1	0	HEX_V3_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	1	HEX_H2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	1	HEX_H3_BUF[2]
1	0	0	0	0	1	1	1	1	1	1	0	HEX_V2_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[15]

virtex IO_S switchbox INT muxes IMUX_IO_CLK[3]
Bits												Destination
MAIN[17][12]	MAIN[17][14]	MAIN[18][14]	MAIN[11][13]	MAIN[21][14]	MAIN[17][13]	MAIN[23][13]	MAIN[22][14]	MAIN[22][13]	MAIN[20][13]	MAIN[20][14]	MAIN[12][13]	IMUX_IO_CLK[3]
												Source
0	0	0	0	0	0	1	1	1	1	1	1	GCLK_BUF[0]
0	0	0	0	0	1	0	1	1	1	1	1	GCLK_BUF[1]
0	0	0	0	0	1	1	0	1	1	1	1	GCLK_BUF[2]
0	0	0	0	0	1	1	1	0	1	1	1	GCLK_BUF[3]
0	0	0	0	0	1	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	0	1	1	HEX_V4_BUF[2]
0	0	0	1	0	1	1	1	1	1	0	1	HEX_H5_BUF[2]
0	0	0	1	0	1	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	1	SINGLE_N_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	1	HEX_H1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	1	HEX_H4_BUF[2]
0	0	1	0	0	1	1	1	1	1	1	0	HEX_V1_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[9]
0	1	0	0	0	1	1	1	1	0	1	1	HEX_V0_BUF[2]
0	1	0	0	0	1	1	1	1	1	0	1	HEX_H6_BUF[2]
0	1	0	0	0	1	1	1	1	1	1	0	HEX_V3_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	1	HEX_H2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	1	HEX_H3_BUF[2]
1	0	0	0	0	1	1	1	1	1	1	0	HEX_V2_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	1	SINGLE_N_BUF[15]

virtex IO_S switchbox INT muxes IMUX_IO_SR[0]
Bits						Destination
MAIN[29][10]	MAIN[30][10]	MAIN[31][10]	MAIN[33][9]	MAIN[32][11]	MAIN[33][11]	IMUX_IO_SR[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[4]
0	0	0	0	1	0	SINGLE_N_BUF[5]
0	0	0	1	0	0	SINGLE_N_BUF[6]
0	0	1	0	0	0	SINGLE_N_BUF[7]
0	1	0	0	0	1	HEX_H1_BUF[1]
0	1	0	0	1	0	HEX_H4_BUF[1]
0	1	0	1	0	0	HEX_V5_BUF[1]
0	1	1	0	0	0	HEX_V4_BUF[1]
1	0	0	0	0	1	HEX_V2_BUF[1]
1	0	0	0	1	0	HEX_V3_BUF[1]
1	0	0	1	0	0	HEX_V1_BUF[1]
1	0	1	0	0	0	HEX_V0_BUF[1]
1	1	0	0	0	1	HEX_H2_BUF[1]
1	1	0	0	1	0	HEX_H3_BUF[1]
1	1	0	1	0	0	HEX_H5_BUF[1]
1	1	1	0	0	0	HEX_H6_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_SR[1]
Bits						Destination
MAIN[30][11]	MAIN[29][11]	MAIN[28][9]	MAIN[32][9]	MAIN[31][9]	MAIN[28][11]	IMUX_IO_SR[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[4]
0	0	0	0	1	0	SINGLE_N_BUF[5]
0	0	0	1	0	0	SINGLE_N_BUF[6]
0	0	1	0	0	0	SINGLE_N_BUF[7]
0	1	0	0	0	1	HEX_H1_BUF[1]
0	1	0	0	1	0	HEX_H4_BUF[1]
0	1	0	1	0	0	HEX_V5_BUF[1]
0	1	1	0	0	0	HEX_V4_BUF[1]
1	0	0	0	0	1	HEX_V2_BUF[1]
1	0	0	0	1	0	HEX_V3_BUF[1]
1	0	0	1	0	0	HEX_V1_BUF[1]
1	0	1	0	0	0	HEX_V0_BUF[1]
1	1	0	0	0	1	HEX_H2_BUF[1]
1	1	0	0	1	0	HEX_H3_BUF[1]
1	1	0	1	0	0	HEX_H5_BUF[1]
1	1	1	0	0	0	HEX_H6_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_SR[2]
Bits						Destination
MAIN[35][11]	MAIN[36][11]	MAIN[37][10]	MAIN[38][9]	MAIN[36][9]	MAIN[37][11]	IMUX_IO_SR[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[4]
0	0	0	0	1	0	SINGLE_N_BUF[5]
0	0	0	1	0	0	SINGLE_N_BUF[6]
0	0	1	0	0	0	SINGLE_N_BUF[7]
0	1	0	0	0	1	HEX_H1_BUF[1]
0	1	0	0	1	0	HEX_H4_BUF[1]
0	1	0	1	0	0	HEX_V5_BUF[1]
0	1	1	0	0	0	HEX_V4_BUF[1]
1	0	0	0	0	1	HEX_V2_BUF[1]
1	0	0	0	1	0	HEX_V3_BUF[1]
1	0	0	1	0	0	HEX_V1_BUF[1]
1	0	1	0	0	0	HEX_V0_BUF[1]
1	1	0	0	0	1	HEX_H2_BUF[1]
1	1	0	0	1	0	HEX_H3_BUF[1]
1	1	0	1	0	0	HEX_H5_BUF[1]
1	1	1	0	0	0	HEX_H6_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_SR[3]
Bits						Destination
MAIN[36][10]	MAIN[35][10]	MAIN[34][10]	MAIN[35][9]	MAIN[39][9]	MAIN[34][11]	IMUX_IO_SR[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[4]
0	0	0	0	1	0	SINGLE_N_BUF[5]
0	0	0	1	0	0	SINGLE_N_BUF[6]
0	0	1	0	0	0	SINGLE_N_BUF[7]
0	1	0	0	0	1	HEX_H1_BUF[1]
0	1	0	0	1	0	HEX_H4_BUF[1]
0	1	0	1	0	0	HEX_V5_BUF[1]
0	1	1	0	0	0	HEX_V4_BUF[1]
1	0	0	0	0	1	HEX_V2_BUF[1]
1	0	0	0	1	0	HEX_V3_BUF[1]
1	0	0	1	0	0	HEX_V1_BUF[1]
1	0	1	0	0	0	HEX_V0_BUF[1]
1	1	0	0	0	1	HEX_H2_BUF[1]
1	1	0	0	1	0	HEX_H3_BUF[1]
1	1	0	1	0	0	HEX_H5_BUF[1]
1	1	1	0	0	0	HEX_H6_BUF[1]

virtex IO_S switchbox INT muxes IMUX_IO_ICE[0]
Bits						Destination
MAIN[8][10]	MAIN[7][10]	MAIN[5][11]	MAIN[6][11]	MAIN[7][9]	MAIN[6][10]	IMUX_IO_ICE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[20]
0	0	0	0	1	0	SINGLE_N_BUF[21]
0	0	0	1	0	0	SINGLE_N_BUF[22]
0	0	1	0	0	0	SINGLE_N_BUF[23]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_ICE[1]
Bits						Destination
MAIN[7][11]	MAIN[8][11]	MAIN[9][11]	MAIN[4][9]	MAIN[5][9]	MAIN[9][10]	IMUX_IO_ICE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[20]
0	0	0	0	1	0	SINGLE_N_BUF[21]
0	0	0	1	0	0	SINGLE_N_BUF[22]
0	0	1	0	0	0	SINGLE_N_BUF[23]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_ICE[2]
Bits						Destination
MAIN[2][11]	MAIN[1][11]	MAIN[0][11]	MAIN[0][9]	MAIN[1][9]	MAIN[0][10]	IMUX_IO_ICE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[20]
0	0	0	0	1	0	SINGLE_N_BUF[21]
0	0	0	1	0	0	SINGLE_N_BUF[22]
0	0	1	0	0	0	SINGLE_N_BUF[23]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_ICE[3]
Bits						Destination
MAIN[1][10]	MAIN[2][10]	MAIN[3][11]	MAIN[4][11]	MAIN[2][9]	MAIN[3][10]	IMUX_IO_ICE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[20]
0	0	0	0	1	0	SINGLE_N_BUF[21]
0	0	0	1	0	0	SINGLE_N_BUF[22]
0	0	1	0	0	0	SINGLE_N_BUF[23]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_OCE[0]
Bits						Destination
MAIN[18][10]	MAIN[17][10]	MAIN[14][11]	MAIN[15][11]	MAIN[14][9]	MAIN[16][10]	IMUX_IO_OCE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[16]
0	0	0	0	1	0	SINGLE_N_BUF[17]
0	0	0	1	0	0	SINGLE_N_BUF[18]
0	0	1	0	0	0	SINGLE_N_BUF[19]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_OCE[1]
Bits						Destination
MAIN[17][11]	MAIN[18][11]	MAIN[19][11]	MAIN[16][9]	MAIN[15][9]	MAIN[19][9]	IMUX_IO_OCE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[16]
0	0	0	0	1	0	SINGLE_N_BUF[17]
0	0	0	1	0	0	SINGLE_N_BUF[18]
0	0	1	0	0	0	SINGLE_N_BUF[19]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_OCE[2]
Bits						Destination
MAIN[12][11]	MAIN[11][11]	MAIN[10][11]	MAIN[11][9]	MAIN[9][9]	MAIN[10][10]	IMUX_IO_OCE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[16]
0	0	0	0	1	0	SINGLE_N_BUF[17]
0	0	0	1	0	0	SINGLE_N_BUF[18]
0	0	1	0	0	0	SINGLE_N_BUF[19]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_OCE[3]
Bits						Destination
MAIN[11][10]	MAIN[12][10]	MAIN[13][11]	MAIN[8][9]	MAIN[12][9]	MAIN[13][10]	IMUX_IO_OCE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[16]
0	0	0	0	1	0	SINGLE_N_BUF[17]
0	0	0	1	0	0	SINGLE_N_BUF[18]
0	0	1	0	0	0	SINGLE_N_BUF[19]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_TCE[0]
Bits						Destination
MAIN[25][11]	MAIN[26][11]	MAIN[27][11]	MAIN[25][9]	MAIN[26][9]	MAIN[28][10]	IMUX_IO_TCE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[10]
0	0	0	0	1	0	SINGLE_N_BUF[11]
0	0	0	1	0	0	SINGLE_N_BUF[12]
0	0	1	0	0	0	SINGLE_N_BUF[13]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_TCE[1]
Bits						Destination
MAIN[27][10]	MAIN[26][10]	MAIN[24][11]	MAIN[31][11]	MAIN[27][9]	MAIN[24][10]	IMUX_IO_TCE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[10]
0	0	0	0	1	0	SINGLE_N_BUF[11]
0	0	0	1	0	0	SINGLE_N_BUF[12]
0	0	1	0	0	0	SINGLE_N_BUF[13]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_TCE[2]
Bits						Destination
MAIN[22][11]	MAIN[21][11]	MAIN[20][11]	MAIN[22][9]	MAIN[21][9]	MAIN[19][10]	IMUX_IO_TCE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[10]
0	0	0	0	1	0	SINGLE_N_BUF[11]
0	0	0	1	0	0	SINGLE_N_BUF[12]
0	0	1	0	0	0	SINGLE_N_BUF[13]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_TCE[3]
Bits						Destination
MAIN[20][10]	MAIN[21][10]	MAIN[23][11]	MAIN[16][11]	MAIN[20][9]	MAIN[23][10]	IMUX_IO_TCE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[10]
0	0	0	0	1	0	SINGLE_N_BUF[11]
0	0	0	1	0	0	SINGLE_N_BUF[12]
0	0	1	0	0	0	SINGLE_N_BUF[13]
0	1	0	0	0	1	HEX_V1_BUF[3]
0	1	0	0	1	0	HEX_V0_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V5_BUF[3]
1	0	0	0	1	0	HEX_V4_BUF[3]
1	0	0	1	0	0	HEX_V2_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_S switchbox INT muxes IMUX_IO_O[0]
Bits									Destination
MAIN[41][13]	MAIN[42][13]	MAIN[47][13]	MAIN[46][13]	MAIN[45][14]	MAIN[44][13]	MAIN[43][13]	MAIN[44][14]	MAIN[45][13]	IMUX_IO_O[0]
									Source
0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	1	0	0	HEX_V0_BUF[0]
0	0	0	0	0	0	1	1	1	SINGLE_N_BUF[0]
0	0	0	0	0	1	0	0	0	HEX_V3_BUF[0]
0	0	0	0	0	1	0	1	1	SINGLE_N_BUF[1]
0	0	0	0	1	0	1	0	1	SINGLE_N_BUF[3]
0	0	0	0	1	1	0	0	1	SINGLE_N_BUF[2]
0	0	0	1	0	0	0	0	0	HEX_V1_BUF[0]
0	0	0	1	0	0	0	1	1	SINGLE_N_BUF[9]
0	0	0	1	1	0	0	0	1	SINGLE_N_BUF[4]
0	0	1	0	0	0	0	0	0	HEX_V2_BUF[0]
0	0	1	0	0	0	0	1	1	SINGLE_N_BUF[8]
0	0	1	0	1	0	0	0	1	SINGLE_N_BUF[5]
0	1	0	0	0	0	0	1	1	SINGLE_N_BUF[6]
0	1	0	0	1	0	0	0	1	SINGLE_N_BUF[10]
1	0	0	0	0	0	0	1	1	SINGLE_N_BUF[7]
1	0	0	0	1	0	0	0	1	SINGLE_N_BUF[11]

virtex IO_S switchbox INT muxes IMUX_IO_O[1]
Bits									Destination
MAIN[43][14]	MAIN[42][14]	MAIN[43][12]	MAIN[41][12]	MAIN[41][14]	MAIN[39][13]	MAIN[38][13]	MAIN[40][14]	MAIN[40][13]	IMUX_IO_O[1]
									Source
0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	1	0	0	HEX_V2_BUF[1]
0	0	0	0	0	0	1	1	1	SINGLE_N_BUF[0]
0	0	0	0	0	1	0	0	0	HEX_V3_BUF[1]
0	0	0	0	0	1	0	1	1	SINGLE_N_BUF[1]
0	0	0	0	1	0	1	0	1	SINGLE_N_BUF[3]
0	0	0	0	1	1	0	0	1	SINGLE_N_BUF[2]
0	0	0	1	0	0	0	0	0	HEX_V1_BUF[1]
0	0	0	1	0	0	0	1	1	SINGLE_N_BUF[9]
0	0	0	1	1	0	0	0	1	SINGLE_N_BUF[4]
0	0	1	0	0	0	0	0	0	HEX_V0_BUF[1]
0	0	1	0	0	0	0	1	1	SINGLE_N_BUF[8]
0	0	1	0	1	0	0	0	1	SINGLE_N_BUF[5]
0	1	0	0	0	0	0	1	1	SINGLE_N_BUF[6]
0	1	0	0	1	0	0	0	1	SINGLE_N_BUF[10]
1	0	0	0	0	0	0	1	1	SINGLE_N_BUF[7]
1	0	0	0	1	0	0	0	1	SINGLE_N_BUF[11]

virtex IO_S switchbox INT muxes IMUX_IO_O[2]
Bits									Destination
MAIN[8][13]	MAIN[9][13]	MAIN[4][12]	MAIN[6][12]	MAIN[7][14]	MAIN[5][14]	MAIN[4][14]	MAIN[6][14]	MAIN[7][13]	IMUX_IO_O[2]
									Source
0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	1	1	1	SINGLE_N_BUF[12]
0	0	0	0	0	1	0	1	1	SINGLE_N_BUF[13]
0	0	0	0	1	0	1	0	1	SINGLE_N_BUF[16]
0	0	0	0	1	1	0	0	1	SINGLE_N_BUF[17]
0	0	0	1	0	0	0	0	0	HEX_V1_BUF[2]
0	0	0	1	0	0	0	1	1	SINGLE_N_BUF[19]
0	0	0	1	1	0	0	0	1	SINGLE_N_BUF[14]
0	0	1	0	0	0	0	0	0	HEX_V0_BUF[2]
0	0	1	0	0	0	0	1	1	SINGLE_N_BUF[18]
0	0	1	0	1	0	0	0	1	SINGLE_N_BUF[15]
0	1	0	0	0	0	0	0	0	HEX_V2_BUF[2]
0	1	0	0	0	0	0	1	1	SINGLE_N_BUF[20]
0	1	0	0	1	0	0	0	1	SINGLE_N_BUF[23]
1	0	0	0	0	0	0	0	0	HEX_V3_BUF[2]
1	0	0	0	0	0	0	1	1	SINGLE_N_BUF[21]
1	0	0	0	1	0	0	0	1	SINGLE_N_BUF[22]

virtex IO_S switchbox INT muxes IMUX_IO_O[3]
Bits									Destination
MAIN[3][13]	MAIN[4][13]	MAIN[0][13]	MAIN[1][13]	MAIN[3][14]	MAIN[5][13]	MAIN[6][13]	MAIN[2][14]	MAIN[2][13]	IMUX_IO_O[3]
									Source
0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	1	1	1	SINGLE_N_BUF[12]
0	0	0	0	0	1	0	1	1	SINGLE_N_BUF[13]
0	0	0	0	1	0	1	0	1	SINGLE_N_BUF[16]
0	0	0	0	1	1	0	0	1	SINGLE_N_BUF[17]
0	0	0	1	0	0	0	0	0	HEX_V1_BUF[3]
0	0	0	1	0	0	0	1	1	SINGLE_N_BUF[19]
0	0	0	1	1	0	0	0	1	SINGLE_N_BUF[14]
0	0	1	0	0	0	0	0	0	HEX_V2_BUF[3]
0	0	1	0	0	0	0	1	1	SINGLE_N_BUF[18]
0	0	1	0	1	0	0	0	1	SINGLE_N_BUF[15]
0	1	0	0	0	0	0	0	0	HEX_V0_BUF[3]
0	1	0	0	0	0	0	1	1	SINGLE_N_BUF[20]
0	1	0	0	1	0	0	0	1	SINGLE_N_BUF[23]
1	0	0	0	0	0	0	0	0	HEX_V3_BUF[3]
1	0	0	0	0	0	0	1	1	SINGLE_N_BUF[21]
1	0	0	0	1	0	0	0	1	SINGLE_N_BUF[22]

virtex IO_S switchbox INT muxes IMUX_IO_T[0]
Bits						Destination
MAIN[39][10]	MAIN[40][10]	MAIN[41][10]	MAIN[40][9]	MAIN[41][11]	MAIN[42][11]	IMUX_IO_T[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[0]
0	0	0	0	1	0	SINGLE_N_BUF[1]
0	0	0	1	0	0	SINGLE_N_BUF[2]
0	0	1	0	0	0	SINGLE_N_BUF[3]
0	1	0	0	0	1	HEX_H1_BUF[0]
0	1	0	0	1	0	HEX_H4_BUF[0]
0	1	0	1	0	0	HEX_V0_BUF[0]
0	1	1	0	0	0	HEX_V1_BUF[0]
1	0	0	0	0	1	HEX_V3_BUF[0]
1	0	0	0	1	0	HEX_V2_BUF[0]
1	0	0	1	0	0	HEX_V4_BUF[0]
1	0	1	0	0	0	HEX_V5_BUF[0]
1	1	0	0	0	1	HEX_H2_BUF[0]
1	1	0	0	1	0	HEX_H3_BUF[0]
1	1	0	1	0	0	HEX_H5_BUF[0]
1	1	1	0	0	0	HEX_H6_BUF[0]

virtex IO_S switchbox INT muxes IMUX_IO_T[1]
Bits						Destination
MAIN[40][11]	MAIN[39][11]	MAIN[38][10]	MAIN[42][9]	MAIN[43][9]	MAIN[38][11]	IMUX_IO_T[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[0]
0	0	0	0	1	0	SINGLE_N_BUF[1]
0	0	0	1	0	0	SINGLE_N_BUF[2]
0	0	1	0	0	0	SINGLE_N_BUF[3]
0	1	0	0	0	1	HEX_H1_BUF[0]
0	1	0	0	1	0	HEX_H4_BUF[0]
0	1	0	1	0	0	HEX_V0_BUF[0]
0	1	1	0	0	0	HEX_V1_BUF[0]
1	0	0	0	0	1	HEX_V3_BUF[0]
1	0	0	0	1	0	HEX_V2_BUF[0]
1	0	0	1	0	0	HEX_V4_BUF[0]
1	0	1	0	0	0	HEX_V5_BUF[0]
1	1	0	0	0	1	HEX_H2_BUF[0]
1	1	0	0	1	0	HEX_H3_BUF[0]
1	1	0	1	0	0	HEX_H5_BUF[0]
1	1	1	0	0	0	HEX_H6_BUF[0]

virtex IO_S switchbox INT muxes IMUX_IO_T[2]
Bits						Destination
MAIN[45][11]	MAIN[46][11]	MAIN[47][10]	MAIN[46][9]	MAIN[47][9]	MAIN[47][11]	IMUX_IO_T[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[0]
0	0	0	0	1	0	SINGLE_N_BUF[1]
0	0	0	1	0	0	SINGLE_N_BUF[2]
0	0	1	0	0	0	SINGLE_N_BUF[3]
0	1	0	0	0	1	HEX_H1_BUF[0]
0	1	0	0	1	0	HEX_H4_BUF[0]
0	1	0	1	0	0	HEX_V0_BUF[0]
0	1	1	0	0	0	HEX_V1_BUF[0]
1	0	0	0	0	1	HEX_V3_BUF[0]
1	0	0	0	1	0	HEX_V2_BUF[0]
1	0	0	1	0	0	HEX_V4_BUF[0]
1	0	1	0	0	0	HEX_V5_BUF[0]
1	1	0	0	0	1	HEX_H2_BUF[0]
1	1	0	0	1	0	HEX_H3_BUF[0]
1	1	0	1	0	0	HEX_H5_BUF[0]
1	1	1	0	0	0	HEX_H6_BUF[0]

virtex IO_S switchbox INT muxes IMUX_IO_T[3]
Bits						Destination
MAIN[46][10]	MAIN[45][10]	MAIN[44][10]	MAIN[45][9]	MAIN[43][11]	MAIN[44][11]	IMUX_IO_T[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_N_BUF[0]
0	0	0	0	1	0	SINGLE_N_BUF[1]
0	0	0	1	0	0	SINGLE_N_BUF[2]
0	0	1	0	0	0	SINGLE_N_BUF[3]
0	1	0	0	0	1	HEX_H1_BUF[0]
0	1	0	0	1	0	HEX_H4_BUF[0]
0	1	0	1	0	0	HEX_V0_BUF[0]
0	1	1	0	0	0	HEX_V1_BUF[0]
1	0	0	0	0	1	HEX_V3_BUF[0]
1	0	0	0	1	0	HEX_V2_BUF[0]
1	0	0	1	0	0	HEX_V4_BUF[0]
1	0	1	0	0	0	HEX_V5_BUF[0]
1	1	0	0	0	1	HEX_H2_BUF[0]
1	1	0	0	1	0	HEX_H3_BUF[0]
1	1	0	1	0	0	HEX_H5_BUF[0]
1	1	1	0	0	0	HEX_H6_BUF[0]

Bels IOI

virtex IO_S bel IOI pins
Pin	Direction	IOI[0]	IOI[1]	IOI[2]	IOI[3]
ICLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[34][14]	IMUX_IO_CLK[2] invert by MAIN[13][14]	IMUX_IO_CLK[3]
OCLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[33][14]	IMUX_IO_CLK[2] invert by MAIN[14][14]	IMUX_IO_CLK[3]
TCLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[32][14]	IMUX_IO_CLK[2] invert by MAIN[15][14]	IMUX_IO_CLK[3]
SR	in	IMUX_IO_SR[0]	IMUX_IO_SR[1] invert by MAIN[33][10]	IMUX_IO_SR[2] invert by MAIN[34][9]	IMUX_IO_SR[3]
ICE	in	IMUX_IO_ICE[0]	IMUX_IO_ICE[1] invert by !MAIN[5][10]	IMUX_IO_ICE[2] invert by !MAIN[4][10]	IMUX_IO_ICE[3]
OCE	in	IMUX_IO_OCE[0]	IMUX_IO_OCE[1] invert by !MAIN[14][10]	IMUX_IO_OCE[2] invert by !MAIN[13][9]	IMUX_IO_OCE[3]
TCE	in	IMUX_IO_TCE[0]	IMUX_IO_TCE[1] invert by !MAIN[25][10]	IMUX_IO_TCE[2] invert by !MAIN[23][9]	IMUX_IO_TCE[3]
O	in	IMUX_IO_O[0]	IMUX_IO_O[1] invert by !MAIN[38][14]	IMUX_IO_O[2] invert by !MAIN[9][14]	IMUX_IO_O[3]
T	in	IMUX_IO_T[0]	IMUX_IO_T[1] invert by !MAIN[42][10]	IMUX_IO_T[2] invert by !MAIN[43][10]	IMUX_IO_T[3]
I	out	OUT_IO_I[0]	OUT_IO_I[1]	OUT_IO_I[2]	OUT_IO_I[3]
IQ	out	OUT_IO_IQ[0]	OUT_IO_IQ[1]	OUT_IO_IQ[2]	OUT_IO_IQ[3]

virtex IO_S bel IOI attribute bits
Attribute	IOI[0]	IOI[1]	IOI[2]	IOI[3]
SHORTEN_JTAG_CHAIN	-	!MAIN[37][17]	!MAIN[28][17]	-
FFI_INIT bit 0	-	MAIN[46][16]	MAIN[19][16]	-
FFI_READBACK bit 0	-	MAIN[45][17]	MAIN[20][17]	-
FFI_LATCH	-	MAIN[44][16]	MAIN[21][16]	-
FFI_SR_ENABLE	-	MAIN[43][16]	MAIN[22][16]	-
FFI_SR_SYNC	-	MAIN[47][16]	MAIN[18][16]	-
FFI_DELAY_ENABLE	-	MAIN[38][17]	MAIN[27][17]	-
I_DELAY_ENABLE	-	MAIN[45][16]	MAIN[20][16]	-
FFO_INIT bit 0	-	!MAIN[39][16]	!MAIN[26][16]	-
FFO_READBACK bit 0	-	MAIN[39][17]	MAIN[26][17]	-
FFO_LATCH	-	MAIN[41][16]	MAIN[24][16]	-
FFO_SR_ENABLE	-	MAIN[42][16]	MAIN[23][16]	-
FFO_SR_SYNC	-	MAIN[38][16]	MAIN[27][16]	-
FFT_INIT bit 0	-	!MAIN[36][16]	!MAIN[29][16]	-
FFT_READBACK bit 0	-	MAIN[35][17]	MAIN[30][17]	-
FFT_LATCH	-	MAIN[34][16]	MAIN[31][16]	-
FFT_SR_ENABLE	-	MAIN[33][16]	MAIN[32][16]	-
FFT_SR_SYNC	-	MAIN[37][16]	MAIN[28][16]	-
MUX_O	-	[enum: IO_MUX_O]	[enum: IO_MUX_O]	-
MUX_T	-	[enum: IO_MUX_T]	[enum: IO_MUX_T]	-

virtex IO_S enum IO_MUX_O
IOI[1].MUX_O	MAIN[40][16]
IOI[2].MUX_O	MAIN[25][16]
O	0
FFO	1

virtex IO_S enum IO_MUX_T
IOI[1].MUX_T	MAIN[35][16]
IOI[2].MUX_T	MAIN[30][16]
T	0
FFT	1

Bel wires

virtex IO_S bel wires
Wire	Pins
IMUX_IO_CLK[0]	IOI[0].ICLK, IOI[0].OCLK, IOI[0].TCLK
IMUX_IO_CLK[1]	IOI[1].ICLK, IOI[1].OCLK, IOI[1].TCLK
IMUX_IO_CLK[2]	IOI[2].ICLK, IOI[2].OCLK, IOI[2].TCLK
IMUX_IO_CLK[3]	IOI[3].ICLK, IOI[3].OCLK, IOI[3].TCLK
IMUX_IO_SR[0]	IOI[0].SR
IMUX_IO_SR[1]	IOI[1].SR
IMUX_IO_SR[2]	IOI[2].SR
IMUX_IO_SR[3]	IOI[3].SR
IMUX_IO_ICE[0]	IOI[0].ICE
IMUX_IO_ICE[1]	IOI[1].ICE
IMUX_IO_ICE[2]	IOI[2].ICE
IMUX_IO_ICE[3]	IOI[3].ICE
IMUX_IO_OCE[0]	IOI[0].OCE
IMUX_IO_OCE[1]	IOI[1].OCE
IMUX_IO_OCE[2]	IOI[2].OCE
IMUX_IO_OCE[3]	IOI[3].OCE
IMUX_IO_TCE[0]	IOI[0].TCE
IMUX_IO_TCE[1]	IOI[1].TCE
IMUX_IO_TCE[2]	IOI[2].TCE
IMUX_IO_TCE[3]	IOI[3].TCE
IMUX_IO_O[0]	IOI[0].O
IMUX_IO_O[1]	IOI[1].O
IMUX_IO_O[2]	IOI[2].O
IMUX_IO_O[3]	IOI[3].O
IMUX_IO_T[0]	IOI[0].T
IMUX_IO_T[1]	IOI[1].T
IMUX_IO_T[2]	IOI[2].T
IMUX_IO_T[3]	IOI[3].T
OUT_IO_I[0]	IOI[0].I
OUT_IO_I[1]	IOI[1].I
OUT_IO_I[2]	IOI[2].I
OUT_IO_I[3]	IOI[3].I
OUT_IO_IQ[0]	IOI[0].IQ
OUT_IO_IQ[1]	IOI[1].IQ
OUT_IO_IQ[2]	IOI[2].IQ
OUT_IO_IQ[3]	IOI[3].IQ

Bitstream

virtex IO_S rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOI[2]: FFI_READBACK bit 0	-	-	-	-	-	IOI[2]: FFO_READBACK bit 0	IOI[2]: FFI_DELAY_ENABLE	IOI[2]: ! SHORTEN_JTAG_CHAIN	-	IOI[2]: FFT_READBACK bit 0	-	-	-	-	IOI[1]: FFT_READBACK bit 0	-	IOI[1]: ! SHORTEN_JTAG_CHAIN	IOI[1]: FFI_DELAY_ENABLE	IOI[1]: FFO_READBACK bit 0	-	-	-	-	-	IOI[1]: FFI_READBACK bit 0	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOI[2]: FFI_SR_SYNC	IOI[2]: FFI_INIT bit 0	IOI[2]: I_DELAY_ENABLE	IOI[2]: FFI_LATCH	IOI[2]: FFI_SR_ENABLE	IOI[2]: FFO_SR_ENABLE	IOI[2]: FFO_LATCH	IOI[2]: MUX_O bit 0	IOI[2]: ! FFO_INIT bit 0	IOI[2]: FFO_SR_SYNC	IOI[2]: FFT_SR_SYNC	IOI[2]: ! FFT_INIT bit 0	IOI[2]: MUX_T bit 0	IOI[2]: FFT_LATCH	IOI[2]: FFT_SR_ENABLE	IOI[1]: FFT_SR_ENABLE	IOI[1]: FFT_LATCH	IOI[1]: MUX_T bit 0	IOI[1]: ! FFT_INIT bit 0	IOI[1]: FFT_SR_SYNC	IOI[1]: FFO_SR_SYNC	IOI[1]: ! FFO_INIT bit 0	IOI[1]: MUX_O bit 0	IOI[1]: FFO_LATCH	IOI[1]: FFO_SR_ENABLE	IOI[1]: FFI_SR_ENABLE	IOI[1]: FFI_LATCH	IOI[1]: I_DELAY_ENABLE	IOI[1]: FFI_INIT bit 0	IOI[1]: FFI_SR_SYNC
B15	INT: mux LH_MUX[6] bit 0	INT: mux LH_MUX[6] bit 6	INT: mux LH_MUX[6] bit 1	INT: buffer LH[6] ← LH_MUX[6]	INT: mux LH_MUX[0] bit 6	INT: mux LH_MUX[6] bit 8	INT: mux LH_MUX[0] bit 5	INT: mux LH_MUX[6] bit 5	INT: mux LH_MUX[0] bit 2	INT: mux LH_MUX[0] bit 8	INT: buffer LH[0] ← LH_MUX[0]	INT: mux LH_MUX[6] bit 3	INT: mux LH_MUX[6] bit 2	INT: mux LH_MUX[0] bit 1	INT: mux LH_MUX[6] bit 4	INT: mux LH_MUX[0] bit 4	INT: mux HEX_H6_MUX[4] bit 4	INT: mux HEX_H6_MUX[4] bit 2	INT: mux HEX_H0_MUX[5] bit 2	INT: buffer HEX_H0[5] ← HEX_H0_MUX[5]	INT: mux HEX_H0_MUX[5] bit 3	INT: mux HEX_H6_MUX[4] bit 3	INT: mux HEX_H0_MUX[5] bit 4	INT: mux HEX_H0_MUX[5] bit 6	INT: mux HEX_H6_MUX[4] bit 6	INT: mux HEX_H0_MUX[5] bit 5	INT: mux HEX_H6_MUX[4] bit 1	INT: mux HEX_H0_MUX[5] bit 1	INT: buffer HEX_H6[4] ← HEX_H6_MUX[4]	INT: mux HEX_H0_MUX[5] bit 0	INT: mux HEX_H6_MUX[4] bit 0	INT: mux HEX_H6_MUX[4] bit 5	INT: mux HEX_H6_MUX[5] bit 5	INT: mux HEX_H6_MUX[5] bit 0	INT: mux HEX_H0_MUX[4] bit 0	INT: mux HEX_H0_MUX[4] bit 1	INT: mux HEX_H6_MUX[5] bit 6	INT: buffer HEX_H6[5] ← HEX_H6_MUX[5]	INT: mux HEX_H6_MUX[5] bit 1	INT: mux HEX_H0_MUX[4] bit 5	INT: mux HEX_H0_MUX[4] bit 4	INT: mux HEX_H0_MUX[4] bit 6	INT: mux HEX_H6_MUX[5] bit 3	INT: mux HEX_H0_MUX[4] bit 3	INT: mux HEX_H0_MUX[4] bit 2	INT: buffer HEX_H0[4] ← HEX_H0_MUX[4]	INT: mux HEX_H6_MUX[5] bit 2	INT: mux HEX_H6_MUX[5] bit 4
B14	-	-	INT: mux IMUX_IO_O[3] bit 1	INT: mux IMUX_IO_O[3] bit 4	INT: mux IMUX_IO_O[2] bit 2	INT: mux IMUX_IO_O[2] bit 3	INT: mux IMUX_IO_O[2] bit 1	INT: mux IMUX_IO_O[2] bit 4	-	IOI[2]: !invert O	-	-	-	IOI[2]: invert ICLK	IOI[2]: invert OCLK	IOI[2]: invert TCLK	INT: mux IMUX_IO_CLK[2] bit 10	INT: mux IMUX_IO_CLK[3] bit 10	INT: mux IMUX_IO_CLK[3] bit 9	INT: mux IMUX_IO_CLK[2] bit 11	INT: mux IMUX_IO_CLK[3] bit 1	INT: mux IMUX_IO_CLK[3] bit 7	INT: mux IMUX_IO_CLK[3] bit 4	INT: mux IMUX_IO_CLK[2] bit 6	INT: mux IMUX_IO_CLK[1] bit 6	INT: mux IMUX_IO_CLK[0] bit 4	INT: mux IMUX_IO_CLK[0] bit 7	INT: mux IMUX_IO_CLK[0] bit 1	INT: mux IMUX_IO_CLK[1] bit 11	INT: mux IMUX_IO_CLK[0] bit 9	INT: mux IMUX_IO_CLK[0] bit 10	INT: mux IMUX_IO_CLK[1] bit 10	IOI[1]: invert TCLK	IOI[1]: invert OCLK	IOI[1]: invert ICLK	-	-	-	IOI[1]: !invert O	-	INT: mux IMUX_IO_O[1] bit 1	INT: mux IMUX_IO_O[1] bit 4	INT: mux IMUX_IO_O[1] bit 7	INT: mux IMUX_IO_O[1] bit 8	INT: mux IMUX_IO_O[0] bit 1	INT: mux IMUX_IO_O[0] bit 4	-	-
B13	INT: mux IMUX_IO_O[3] bit 6	INT: mux IMUX_IO_O[3] bit 5	INT: mux IMUX_IO_O[3] bit 0	INT: mux IMUX_IO_O[3] bit 8	INT: mux IMUX_IO_O[3] bit 7	INT: mux IMUX_IO_O[3] bit 3	INT: mux IMUX_IO_O[3] bit 2	INT: mux IMUX_IO_O[2] bit 0	INT: mux IMUX_IO_O[2] bit 8	INT: mux IMUX_IO_O[2] bit 7	INT: mux IMUX_IO_CLK[2] bit 0	INT: mux IMUX_IO_CLK[3] bit 8	INT: mux IMUX_IO_CLK[3] bit 0	INT: mux IMUX_IO_CLK[2] bit 4	INT: mux IMUX_IO_CLK[2] bit 8	INT: mux IMUX_IO_CLK[2] bit 2	INT: mux IMUX_IO_CLK[2] bit 5	INT: mux IMUX_IO_CLK[3] bit 6	INT: mux IMUX_IO_CLK[2] bit 1	INT: mux IMUX_IO_CLK[2] bit 9	INT: mux IMUX_IO_CLK[3] bit 2	INT: mux IMUX_IO_CLK[2] bit 3	INT: mux IMUX_IO_CLK[3] bit 3	INT: mux IMUX_IO_CLK[3] bit 5	INT: mux IMUX_IO_CLK[0] bit 5	INT: mux IMUX_IO_CLK[0] bit 3	INT: mux IMUX_IO_CLK[1] bit 3	INT: mux IMUX_IO_CLK[0] bit 2	INT: mux IMUX_IO_CLK[1] bit 9	INT: mux IMUX_IO_CLK[1] bit 1	INT: mux IMUX_IO_CLK[0] bit 6	INT: mux IMUX_IO_CLK[1] bit 5	INT: mux IMUX_IO_CLK[1] bit 2	INT: mux IMUX_IO_CLK[1] bit 8	INT: mux IMUX_IO_CLK[1] bit 4	INT: mux IMUX_IO_CLK[0] bit 0	INT: mux IMUX_IO_CLK[0] bit 8	INT: mux IMUX_IO_CLK[1] bit 0	INT: mux IMUX_IO_O[1] bit 2	INT: mux IMUX_IO_O[1] bit 3	INT: mux IMUX_IO_O[1] bit 0	INT: mux IMUX_IO_O[0] bit 8	INT: mux IMUX_IO_O[0] bit 7	INT: mux IMUX_IO_O[0] bit 2	INT: mux IMUX_IO_O[0] bit 3	INT: mux IMUX_IO_O[0] bit 0	INT: mux IMUX_IO_O[0] bit 5	INT: mux IMUX_IO_O[0] bit 6
B12	-	INT: mux LH_MUX[0] bit 0	INT: buffer LV[11] ← LV_MUX[11]	-	INT: mux IMUX_IO_O[2] bit 6	INT: buffer LV[10] ← LV_MUX[10]	INT: mux IMUX_IO_O[2] bit 5	-	INT: mux LV_MUX[9] bit 0	INT: mux LH_MUX[6] bit 7	INT: buffer LV[9] ← LV_MUX[9]	-	INT: mux LH_MUX[0] bit 7	INT: buffer LV[8] ← LV_MUX[8]	INT: mux LH_MUX[0] bit 3	INT: mux LV_MUX[8] bit 0	INT: mux LV_MUX[7] bit 0	INT: mux IMUX_IO_CLK[3] bit 11	INT: buffer LV[7] ← LV_MUX[7]	-	-	INT: buffer LV[6] ← LV_MUX[6]	INT: mux IMUX_IO_CLK[2] bit 7	INT: mux LV_MUX[6] bit 0	-	INT: mux IMUX_IO_CLK[1] bit 7	INT: buffer LV[0] ← LV_MUX[0]	-	-	INT: buffer LV[1] ← LV_MUX[1]	INT: mux IMUX_IO_CLK[0] bit 11	-	INT: mux LV_MUX[2] bit 0	-	INT: buffer LV[2] ← LV_MUX[2]	-	-	INT: buffer LV[3] ← LV_MUX[3]	-	INT: mux LV_MUX[3] bit 0	INT: mux LV_MUX[4] bit 0	INT: mux IMUX_IO_O[1] bit 5	INT: buffer LV[4] ← LV_MUX[4]	INT: mux IMUX_IO_O[1] bit 6	-	INT: buffer LV[5] ← LV_MUX[5]	-	INT: mux LV_MUX[5] bit 0
B11	INT: mux IMUX_IO_ICE[2] bit 3	INT: mux IMUX_IO_ICE[2] bit 4	INT: mux IMUX_IO_ICE[2] bit 5	INT: mux IMUX_IO_ICE[3] bit 3	INT: mux IMUX_IO_ICE[3] bit 2	INT: mux IMUX_IO_ICE[0] bit 3	INT: mux IMUX_IO_ICE[0] bit 2	INT: mux IMUX_IO_ICE[1] bit 5	INT: mux IMUX_IO_ICE[1] bit 4	INT: mux IMUX_IO_ICE[1] bit 3	INT: mux IMUX_IO_OCE[2] bit 3	INT: mux IMUX_IO_OCE[2] bit 4	INT: mux IMUX_IO_OCE[2] bit 5	INT: mux IMUX_IO_OCE[3] bit 3	INT: mux IMUX_IO_OCE[0] bit 3	INT: mux IMUX_IO_OCE[0] bit 2	INT: mux IMUX_IO_TCE[3] bit 2	INT: mux IMUX_IO_OCE[1] bit 5	INT: mux IMUX_IO_OCE[1] bit 4	INT: mux IMUX_IO_OCE[1] bit 3	INT: mux IMUX_IO_TCE[2] bit 3	INT: mux IMUX_IO_TCE[2] bit 4	INT: mux IMUX_IO_TCE[2] bit 5	INT: mux IMUX_IO_TCE[3] bit 3	INT: mux IMUX_IO_TCE[1] bit 3	INT: mux IMUX_IO_TCE[0] bit 5	INT: mux IMUX_IO_TCE[0] bit 4	INT: mux IMUX_IO_TCE[0] bit 3	INT: mux IMUX_IO_SR[1] bit 0	INT: mux IMUX_IO_SR[1] bit 4	INT: mux IMUX_IO_SR[1] bit 5	INT: mux IMUX_IO_TCE[1] bit 2	INT: mux IMUX_IO_SR[0] bit 1	INT: mux IMUX_IO_SR[0] bit 0	INT: mux IMUX_IO_SR[3] bit 0	INT: mux IMUX_IO_SR[2] bit 5	INT: mux IMUX_IO_SR[2] bit 4	INT: mux IMUX_IO_SR[2] bit 0	INT: mux IMUX_IO_T[1] bit 0	INT: mux IMUX_IO_T[1] bit 4	INT: mux IMUX_IO_T[1] bit 5	INT: mux IMUX_IO_T[0] bit 1	INT: mux IMUX_IO_T[0] bit 0	INT: mux IMUX_IO_T[3] bit 1	INT: mux IMUX_IO_T[3] bit 0	INT: mux IMUX_IO_T[2] bit 5	INT: mux IMUX_IO_T[2] bit 4	INT: mux IMUX_IO_T[2] bit 0
B10	INT: mux IMUX_IO_ICE[2] bit 0	INT: mux IMUX_IO_ICE[3] bit 5	INT: mux IMUX_IO_ICE[3] bit 4	INT: mux IMUX_IO_ICE[3] bit 0	IOI[2]: !invert ICE	IOI[1]: !invert ICE	INT: mux IMUX_IO_ICE[0] bit 0	INT: mux IMUX_IO_ICE[0] bit 4	INT: mux IMUX_IO_ICE[0] bit 5	INT: mux IMUX_IO_ICE[1] bit 0	INT: mux IMUX_IO_OCE[2] bit 0	INT: mux IMUX_IO_OCE[3] bit 5	INT: mux IMUX_IO_OCE[3] bit 4	INT: mux IMUX_IO_OCE[3] bit 0	IOI[1]: !invert OCE	-	INT: mux IMUX_IO_OCE[0] bit 0	INT: mux IMUX_IO_OCE[0] bit 4	INT: mux IMUX_IO_OCE[0] bit 5	INT: mux IMUX_IO_TCE[2] bit 0	INT: mux IMUX_IO_TCE[3] bit 5	INT: mux IMUX_IO_TCE[3] bit 4	-	INT: mux IMUX_IO_TCE[3] bit 0	INT: mux IMUX_IO_TCE[1] bit 0	IOI[1]: !invert TCE	INT: mux IMUX_IO_TCE[1] bit 4	INT: mux IMUX_IO_TCE[1] bit 5	INT: mux IMUX_IO_TCE[0] bit 0	INT: mux IMUX_IO_SR[0] bit 5	INT: mux IMUX_IO_SR[0] bit 4	INT: mux IMUX_IO_SR[0] bit 3	-	IOI[1]: invert SR	INT: mux IMUX_IO_SR[3] bit 3	INT: mux IMUX_IO_SR[3] bit 4	INT: mux IMUX_IO_SR[3] bit 5	INT: mux IMUX_IO_SR[2] bit 3	INT: mux IMUX_IO_T[1] bit 3	INT: mux IMUX_IO_T[0] bit 5	INT: mux IMUX_IO_T[0] bit 4	INT: mux IMUX_IO_T[0] bit 3	IOI[1]: !invert T	IOI[2]: !invert T	INT: mux IMUX_IO_T[3] bit 3	INT: mux IMUX_IO_T[3] bit 4	INT: mux IMUX_IO_T[3] bit 5	INT: mux IMUX_IO_T[2] bit 3
B9	INT: mux IMUX_IO_ICE[2] bit 2	INT: mux IMUX_IO_ICE[2] bit 1	INT: mux IMUX_IO_ICE[3] bit 1	-	INT: mux IMUX_IO_ICE[1] bit 2	INT: mux IMUX_IO_ICE[1] bit 1	-	INT: mux IMUX_IO_ICE[0] bit 1	INT: mux IMUX_IO_OCE[3] bit 2	INT: mux IMUX_IO_OCE[2] bit 1	-	INT: mux IMUX_IO_OCE[2] bit 2	INT: mux IMUX_IO_OCE[3] bit 1	IOI[2]: !invert OCE	INT: mux IMUX_IO_OCE[0] bit 1	INT: mux IMUX_IO_OCE[1] bit 1	INT: mux IMUX_IO_OCE[1] bit 2	-	-	INT: mux IMUX_IO_OCE[1] bit 0	INT: mux IMUX_IO_TCE[3] bit 1	INT: mux IMUX_IO_TCE[2] bit 1	INT: mux IMUX_IO_TCE[2] bit 2	IOI[2]: !invert TCE	-	INT: mux IMUX_IO_TCE[0] bit 2	INT: mux IMUX_IO_TCE[0] bit 1	INT: mux IMUX_IO_TCE[1] bit 1	INT: mux IMUX_IO_SR[1] bit 3	-	-	INT: mux IMUX_IO_SR[1] bit 1	INT: mux IMUX_IO_SR[1] bit 2	INT: mux IMUX_IO_SR[0] bit 2	IOI[2]: invert SR	INT: mux IMUX_IO_SR[3] bit 2	INT: mux IMUX_IO_SR[2] bit 1	-	INT: mux IMUX_IO_SR[2] bit 2	INT: mux IMUX_IO_SR[3] bit 1	INT: mux IMUX_IO_T[0] bit 2	-	INT: mux IMUX_IO_T[1] bit 2	INT: mux IMUX_IO_T[1] bit 1	-	INT: mux IMUX_IO_T[3] bit 2	INT: mux IMUX_IO_T[2] bit 2	INT: mux IMUX_IO_T[2] bit 1
B8	INT: pass SINGLE_N[23] ← HEX_H0[3]	-	INT: pass SINGLE_N[22] ← HEX_H3[3]	INT: pass SINGLE_N[22] ← OUT_IO_IQ[1]	INT: pass SINGLE_N[21] ← OUT_IO_IQ[2]	INT: pass SINGLE_N[21] ← HEX_H6[3]	-	INT: pass SINGLE_N[20] ← HEX_H0[3]	-	INT: pass SINGLE_N[19] ← HEX_H3[3]	INT: pass SINGLE_N[18] ← OUT_IO_I[1]	INT: pass SINGLE_N[18] ← HEX_H6[3]	INT: pass SINGLE_N[17] ← HEX_H0[2]	INT: pass SINGLE_N[17] ← OUT_IO_I[2]	INT: pass SINGLE_N[16] ← HEX_H3[2]	-	-	INT: pass SINGLE_N[15] ← HEX_H6[2]	INT: pass SINGLE_N[14] ← OUT_IO_IQ[1]	INT: pass SINGLE_N[14] ← HEX_H0[2]	INT: pass SINGLE_N[13] ← OUT_IO_IQ[2]	INT: pass SINGLE_N[13] ← HEX_H3[2]	-	INT: pass SINGLE_N[12] ← HEX_H6[2]	INT: pass SINGLE_N[11] ← HEX_H0[1]	-	INT: pass SINGLE_N[10] ← HEX_H3[1]	INT: pass SINGLE_N[10] ← OUT_IO_I[1]	INT: pass SINGLE_N[9] ← OUT_IO_I[2]	INT: pass SINGLE_N[9] ← HEX_H6[1]	-	INT: pass SINGLE_N[8] ← HEX_H0[1]	-	INT: pass SINGLE_N[7] ← HEX_H3[1]	INT: pass SINGLE_N[6] ← OUT_IO_IQ[1]	INT: pass SINGLE_N[6] ← HEX_H6[1]	INT: pass SINGLE_N[5] ← HEX_H0[0]	INT: pass SINGLE_N[5] ← OUT_IO_IQ[2]	INT: pass SINGLE_N[4] ← HEX_H3[0]	-	-	INT: pass SINGLE_N[3] ← HEX_H6[0]	INT: pass SINGLE_N[2] ← OUT_IO_I[1]	INT: pass SINGLE_N[2] ← HEX_H0[0]	INT: pass SINGLE_N[1] ← OUT_IO_I[2]	INT: pass SINGLE_N[1] ← HEX_H3[0]	-	INT: pass SINGLE_N[0] ← HEX_H6[0]
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT: buffer HEX_H0[3] ← HEX_H0_MUX[3]	INT: mux HEX_H6_MUX[3] bit 5	INT: mux HEX_H6_MUX[3] bit 3	INT: mux HEX_H0_MUX[3] bit 1	INT: mux HEX_H0_MUX[3] bit 5	INT: mux HEX_H0_MUX[3] bit 6	INT: mux HEX_H0_MUX[3] bit 4	INT: mux HEX_H0_MUX[3] bit 0	INT: mux HEX_H0_MUX[3] bit 3	INT: mux HEX_H6_MUX[3] bit 2	INT: mux HEX_H6_MUX[3] bit 6	INT: buffer HEX_H6[3] ← HEX_H6_MUX[3]	INT: buffer HEX_H0[2] ← HEX_H0_MUX[2]	INT: mux HEX_H6_MUX[2] bit 5	INT: mux HEX_H6_MUX[2] bit 3	INT: mux HEX_H0_MUX[2] bit 1	INT: mux HEX_H0_MUX[2] bit 5	INT: mux HEX_H0_MUX[2] bit 6	INT: mux HEX_H0_MUX[2] bit 4	INT: mux HEX_H0_MUX[2] bit 0	INT: mux HEX_H0_MUX[2] bit 3	INT: mux HEX_H6_MUX[2] bit 2	INT: mux HEX_H6_MUX[2] bit 6	INT: buffer HEX_H6[2] ← HEX_H6_MUX[2]	INT: buffer HEX_H0[1] ← HEX_H0_MUX[1]	INT: mux HEX_H6_MUX[1] bit 5	INT: mux HEX_H6_MUX[1] bit 3	INT: mux HEX_H0_MUX[1] bit 1	INT: mux HEX_H0_MUX[1] bit 5	INT: mux HEX_H0_MUX[1] bit 6	INT: mux HEX_H0_MUX[1] bit 4	INT: mux HEX_H0_MUX[1] bit 0	INT: mux HEX_H0_MUX[1] bit 3	INT: mux HEX_H6_MUX[1] bit 2	INT: mux HEX_H6_MUX[1] bit 6	INT: buffer HEX_H6[1] ← HEX_H6_MUX[1]	INT: buffer HEX_H0[0] ← HEX_H0_MUX[0]	INT: mux HEX_H6_MUX[0] bit 5	INT: mux HEX_H6_MUX[0] bit 3	INT: mux HEX_H0_MUX[0] bit 1	INT: mux HEX_H0_MUX[0] bit 5	INT: mux HEX_H0_MUX[0] bit 6	INT: mux HEX_H0_MUX[0] bit 4	INT: mux HEX_H0_MUX[0] bit 0	INT: mux HEX_H0_MUX[0] bit 3	INT: mux HEX_H6_MUX[0] bit 2	INT: mux HEX_H6_MUX[0] bit 6	INT: buffer HEX_H6[0] ← HEX_H6_MUX[0]
B5	INT: mux HEX_H6_MUX[3] bit 0	INT: mux HEX_H0_MUX[3] bit 2	-	-	-	-	-	-	-	-	INT: mux HEX_H6_MUX[3] bit 4	INT: mux HEX_H6_MUX[3] bit 1	INT: mux HEX_H6_MUX[2] bit 0	INT: mux HEX_H0_MUX[2] bit 2	-	-	-	-	-	-	-	-	INT: mux HEX_H6_MUX[2] bit 4	INT: mux HEX_H6_MUX[2] bit 1	INT: mux HEX_H6_MUX[1] bit 0	INT: mux HEX_H0_MUX[1] bit 2	-	-	-	-	-	-	-	-	INT: mux HEX_H6_MUX[1] bit 4	INT: mux HEX_H6_MUX[1] bit 1	INT: mux HEX_H6_MUX[0] bit 0	INT: mux HEX_H0_MUX[0] bit 2	-	-	-	-	-	-	-	-	INT: mux HEX_H6_MUX[0] bit 4	INT: mux HEX_H6_MUX[0] bit 1
B4	INT: buffer HEX_V0[3] ← HEX_V0_MUX[3]	-	INT: mux HEX_V0_MUX[3] bit 1	INT: buffer HEX_V1[3] ← HEX_V1_MUX[3]	INT: buffer HEX_V2[3] ← HEX_V2_MUX[3]	-	-	INT: buffer HEX_V3[3] ← HEX_V3_MUX[3]	INT: buffer HEX_V4[3] ← HEX_V4_MUX[3]	-	-	INT: buffer HEX_V5[3] ← HEX_V5_MUX[3]	INT: buffer HEX_V5[2] ← HEX_V5_MUX[2]	-	-	INT: buffer HEX_V4[2] ← HEX_V4_MUX[2]	INT: buffer HEX_V3[2] ← HEX_V3_MUX[2]	-	-	INT: buffer HEX_V2[2] ← HEX_V2_MUX[2]	INT: buffer HEX_V1[2] ← HEX_V1_MUX[2]	INT: mux HEX_V0_MUX[2] bit 3	INT: mux HEX_V1_MUX[2] bit 1	INT: buffer HEX_V0[2] ← HEX_V0_MUX[2]	INT: buffer HEX_V0[1] ← HEX_V0_MUX[1]	-	INT: mux HEX_V0_MUX[1] bit 3	INT: buffer HEX_V1[1] ← HEX_V1_MUX[1]	INT: buffer HEX_V2[1] ← HEX_V2_MUX[1]	-	-	INT: buffer HEX_V3[1] ← HEX_V3_MUX[1]	INT: buffer HEX_V4[1] ← HEX_V4_MUX[1]	-	-	INT: buffer HEX_V5[1] ← HEX_V5_MUX[1]	INT: buffer HEX_V5[0] ← HEX_V5_MUX[0]	-	-	INT: buffer HEX_V4[0] ← HEX_V4_MUX[0]	INT: buffer HEX_V3[0] ← HEX_V3_MUX[0]	-	-	INT: buffer HEX_V2[0] ← HEX_V2_MUX[0]	INT: buffer HEX_V1[0] ← HEX_V1_MUX[0]	INT: mux HEX_V0_MUX[0] bit 2	INT: mux HEX_V1_MUX[0] bit 1	INT: buffer HEX_V0[0] ← HEX_V0_MUX[0]
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	INT: mux HEX_V0_MUX[3] bit 0	-	INT: mux HEX_V0_MUX[3] bit 4	INT: mux HEX_V1_MUX[3] bit 0	INT: mux HEX_V2_MUX[3] bit 1	INT: mux HEX_V3_MUX[3] bit 1	-	INT: mux HEX_V3_MUX[3] bit 0	INT: mux HEX_V4_MUX[3] bit 2	INT: mux HEX_V5_MUX[3] bit 2	-	INT: mux HEX_V5_MUX[3] bit 0	INT: mux HEX_V5_MUX[2] bit 0	INT: mux HEX_V5_MUX[2] bit 1	-	-	INT: mux HEX_V3_MUX[2] bit 0	INT: mux HEX_V3_MUX[2] bit 1	-	-	INT: mux HEX_V1_MUX[2] bit 0	-	INT: mux HEX_V0_MUX[2] bit 4	INT: mux HEX_V0_MUX[2] bit 0	INT: mux HEX_V0_MUX[1] bit 0	-	INT: mux HEX_V0_MUX[1] bit 4	INT: mux HEX_V1_MUX[1] bit 0	INT: mux HEX_V2_MUX[1] bit 1	INT: mux HEX_V3_MUX[1] bit 1	-	INT: mux HEX_V3_MUX[1] bit 0	INT: mux HEX_V4_MUX[1] bit 2	INT: mux HEX_V5_MUX[1] bit 2	-	INT: mux HEX_V5_MUX[1] bit 0	INT: mux HEX_V5_MUX[0] bit 0	INT: mux HEX_V5_MUX[0] bit 1	-	-	INT: mux HEX_V3_MUX[0] bit 0	INT: mux HEX_V3_MUX[0] bit 1	-	-	INT: mux HEX_V1_MUX[0] bit 0	-	INT: mux HEX_V0_MUX[0] bit 4	INT: mux HEX_V0_MUX[0] bit 0
B1	INT: mux HEX_N0[3] bit 0	INT: mux HEX_N0[3] bit 1	INT: mux HEX_N1[3] bit 1	INT: mux HEX_N1[3] bit 2	INT: mux HEX_N0[3] bit 2	INT: mux HEX_N0[3] bit 3	INT: mux HEX_N1[3] bit 3	-	-	-	-	INT: mux HEX_N1[3] bit 0	INT: mux HEX_N0[1] bit 0	INT: mux HEX_N0[1] bit 2	INT: mux HEX_N1[1] bit 2	INT: mux HEX_N1[1] bit 3	INT: mux HEX_N0[1] bit 3	INT: mux HEX_N0[1] bit 1	INT: mux HEX_N1[1] bit 1	INT: mux HEX_N1[1] bit 5	INT: mux HEX_N0[1] bit 5	INT: mux HEX_N0[1] bit 4	INT: mux HEX_N1[1] bit 4	INT: mux HEX_N1[1] bit 0	INT: mux HEX_N0[2] bit 0	INT: mux HEX_N0[2] bit 3	INT: mux HEX_N1[2] bit 3	INT: mux HEX_N1[2] bit 1	INT: mux HEX_N0[2] bit 1	INT: mux HEX_N0[2] bit 2	INT: mux HEX_N1[2] bit 2	INT: mux HEX_N1[2] bit 5	INT: mux HEX_N0[2] bit 5	INT: mux HEX_N0[2] bit 4	INT: mux HEX_N1[2] bit 4	INT: mux HEX_N1[2] bit 0	INT: mux HEX_N0[0] bit 0	INT: mux HEX_N0[0] bit 1	INT: mux HEX_N1[0] bit 1	INT: mux HEX_N1[0] bit 2	INT: mux HEX_N0[0] bit 2	INT: mux HEX_N0[0] bit 3	INT: mux HEX_N1[0] bit 3	-	-	-	-	INT: mux HEX_N1[0] bit 0
B0	INT: mux HEX_V0_MUX[3] bit 3	INT: mux HEX_V0_MUX[3] bit 2	INT: mux HEX_V1_MUX[3] bit 2	INT: mux HEX_V1_MUX[3] bit 1	INT: mux HEX_V2_MUX[3] bit 0	-	-	-	INT: mux HEX_V4_MUX[3] bit 0	INT: mux HEX_V5_MUX[3] bit 1	INT: mux HEX_V4_MUX[3] bit 1	-	INT: mux HEX_V4_MUX[2] bit 1	-	-	INT: mux HEX_V4_MUX[2] bit 0	INT: mux HEX_V2_MUX[2] bit 1	INT: mux HEX_V2_MUX[2] bit 2	INT: mux HEX_V3_MUX[2] bit 2	INT: mux HEX_V2_MUX[2] bit 0	-	-	INT: mux HEX_V0_MUX[2] bit 1	INT: mux HEX_V0_MUX[2] bit 2	INT: mux HEX_V0_MUX[1] bit 2	INT: mux HEX_V0_MUX[1] bit 1	INT: mux HEX_V1_MUX[1] bit 1	-	INT: mux HEX_V2_MUX[1] bit 0	-	-	-	INT: mux HEX_V4_MUX[1] bit 0	INT: mux HEX_V5_MUX[1] bit 1	INT: mux HEX_V4_MUX[1] bit 1	-	INT: mux HEX_V4_MUX[0] bit 1	-	-	INT: mux HEX_V4_MUX[0] bit 0	INT: mux HEX_V2_MUX[0] bit 1	INT: mux HEX_V2_MUX[0] bit 2	INT: mux HEX_V3_MUX[0] bit 2	INT: mux HEX_V2_MUX[0] bit 0	INT: mux HEX_V1_MUX[0] bit 2	-	INT: mux HEX_V0_MUX[0] bit 3	INT: mux HEX_V0_MUX[0] bit 1

Tile IO_N

Cells: 1

Switchbox INT

virtex IO_N switchbox INT permanent buffers
Destination	Source
GCLK_BUF[0]	GCLK_LEAF[0]
GCLK_BUF[1]	GCLK_LEAF[1]
GCLK_BUF[2]	GCLK_LEAF[2]
GCLK_BUF[3]	GCLK_LEAF[3]
SINGLE_S_BUF[0]	SINGLE_S[0]
SINGLE_S_BUF[1]	SINGLE_S[1]
SINGLE_S_BUF[2]	SINGLE_S[2]
SINGLE_S_BUF[3]	SINGLE_S[3]
SINGLE_S_BUF[4]	SINGLE_S[4]
SINGLE_S_BUF[5]	SINGLE_S[5]
SINGLE_S_BUF[6]	SINGLE_S[6]
SINGLE_S_BUF[7]	SINGLE_S[7]
SINGLE_S_BUF[8]	SINGLE_S[8]
SINGLE_S_BUF[9]	SINGLE_S[9]
SINGLE_S_BUF[10]	SINGLE_S[10]
SINGLE_S_BUF[11]	SINGLE_S[11]
SINGLE_S_BUF[12]	SINGLE_S[12]
SINGLE_S_BUF[13]	SINGLE_S[13]
SINGLE_S_BUF[14]	SINGLE_S[14]
SINGLE_S_BUF[15]	SINGLE_S[15]
SINGLE_S_BUF[16]	SINGLE_S[16]
SINGLE_S_BUF[17]	SINGLE_S[17]
SINGLE_S_BUF[18]	SINGLE_S[18]
SINGLE_S_BUF[19]	SINGLE_S[19]
SINGLE_S_BUF[20]	SINGLE_S[20]
SINGLE_S_BUF[21]	SINGLE_S[21]
SINGLE_S_BUF[22]	SINGLE_S[22]
SINGLE_S_BUF[23]	SINGLE_S[23]
HEX_H1_BUF[0]	HEX_H1[0]
HEX_H1_BUF[1]	HEX_H1[1]
HEX_H1_BUF[2]	HEX_H1[2]
HEX_H1_BUF[3]	HEX_H1[3]
HEX_H2_BUF[0]	HEX_H2[0]
HEX_H2_BUF[1]	HEX_H2[1]
HEX_H2_BUF[2]	HEX_H2[2]
HEX_H2_BUF[3]	HEX_H2[3]
HEX_H3_BUF[0]	HEX_H3[0]
HEX_H3_BUF[1]	HEX_H3[1]
HEX_H3_BUF[2]	HEX_H3[2]
HEX_H3_BUF[3]	HEX_H3[3]
HEX_H4_BUF[0]	HEX_H4[0]
HEX_H4_BUF[1]	HEX_H4[1]
HEX_H4_BUF[2]	HEX_H4[2]
HEX_H4_BUF[3]	HEX_H4[3]
HEX_H5_BUF[0]	HEX_H5[0]
HEX_H5_BUF[1]	HEX_H5[1]
HEX_H5_BUF[2]	HEX_H5[2]
HEX_H5_BUF[3]	HEX_H5[3]
HEX_H6_BUF[0]	HEX_H6[0]
HEX_H6_BUF[1]	HEX_H6[1]
HEX_H6_BUF[2]	HEX_H6[2]
HEX_H6_BUF[3]	HEX_H6[3]
HEX_V1_BUF[0]	HEX_V1[0]
HEX_V1_BUF[1]	HEX_V1[1]
HEX_V1_BUF[2]	HEX_V1[2]
HEX_V1_BUF[3]	HEX_V1[3]
HEX_V2_BUF[0]	HEX_V2[0]
HEX_V2_BUF[1]	HEX_V2[1]
HEX_V2_BUF[2]	HEX_V2[2]
HEX_V2_BUF[3]	HEX_V2[3]
HEX_V3_BUF[0]	HEX_V3[0]
HEX_V3_BUF[1]	HEX_V3[1]
HEX_V3_BUF[2]	HEX_V3[2]
HEX_V3_BUF[3]	HEX_V3[3]
HEX_V4_BUF[0]	HEX_V4[0]
HEX_V4_BUF[1]	HEX_V4[1]
HEX_V4_BUF[2]	HEX_V4[2]
HEX_V4_BUF[3]	HEX_V4[3]
HEX_V5_BUF[0]	HEX_V5[0]
HEX_V5_BUF[1]	HEX_V5[1]
HEX_V5_BUF[2]	HEX_V5[2]
HEX_V5_BUF[3]	HEX_V5[3]
HEX_V6_BUF[0]	HEX_V6[0]
HEX_V6_BUF[1]	HEX_V6[1]
HEX_V6_BUF[2]	HEX_V6[2]
HEX_V6_BUF[3]	HEX_V6[3]
HEX_S2[0]	HEX_N3[0]
HEX_S2[1]	HEX_N3[1]
HEX_S2[2]	HEX_N3[2]
HEX_S2[3]	HEX_N3[3]
HEX_S3[0]	HEX_N4[0]
HEX_S3[1]	HEX_N4[1]
HEX_S3[2]	HEX_N4[2]
HEX_S3[3]	HEX_N4[3]
HEX_S4[0]	HEX_N5[0]
HEX_S4[1]	HEX_N5[1]
HEX_S4[2]	HEX_N5[2]
HEX_S4[3]	HEX_N5[3]
HEX_S5[0]	HEX_N6[0]
HEX_S5[1]	HEX_N6[1]
HEX_S5[2]	HEX_N6[2]
HEX_S5[3]	HEX_N6[3]

virtex IO_N switchbox INT programmable buffers
Destination	Source	Bit
HEX_H0[0]	HEX_H0_MUX[0]	MAIN[36][6]
HEX_H0[1]	HEX_H0_MUX[1]	MAIN[24][6]
HEX_H0[2]	HEX_H0_MUX[2]	MAIN[12][6]
HEX_H0[3]	HEX_H0_MUX[3]	MAIN[0][6]
HEX_H0[4]	HEX_H0_MUX[4]	MAIN[45][15]
HEX_H0[5]	HEX_H0_MUX[5]	MAIN[19][15]
HEX_H6[0]	HEX_H6_MUX[0]	MAIN[47][6]
HEX_H6[1]	HEX_H6_MUX[1]	MAIN[35][6]
HEX_H6[2]	HEX_H6_MUX[2]	MAIN[23][6]
HEX_H6[3]	HEX_H6_MUX[3]	MAIN[11][6]
HEX_H6[4]	HEX_H6_MUX[4]	MAIN[28][15]
HEX_H6[5]	HEX_H6_MUX[5]	MAIN[37][15]
HEX_V1[0]	HEX_V1_MUX[0]	MAIN[36][4]
HEX_V1[1]	HEX_V1_MUX[1]	MAIN[35][4]
HEX_V1[2]	HEX_V1_MUX[2]	MAIN[12][4]
HEX_V1[3]	HEX_V1_MUX[3]	MAIN[11][4]
HEX_V2[0]	HEX_V2_MUX[0]	MAIN[39][4]
HEX_V2[1]	HEX_V2_MUX[1]	MAIN[32][4]
HEX_V2[2]	HEX_V2_MUX[2]	MAIN[15][4]
HEX_V2[3]	HEX_V2_MUX[3]	MAIN[8][4]
HEX_V3[0]	HEX_V3_MUX[0]	MAIN[40][4]
HEX_V3[1]	HEX_V3_MUX[1]	MAIN[31][4]
HEX_V3[2]	HEX_V3_MUX[2]	MAIN[16][4]
HEX_V3[3]	HEX_V3_MUX[3]	MAIN[7][4]
HEX_V4[0]	HEX_V4_MUX[0]	MAIN[43][4]
HEX_V4[1]	HEX_V4_MUX[1]	MAIN[28][4]
HEX_V4[2]	HEX_V4_MUX[2]	MAIN[19][4]
HEX_V4[3]	HEX_V4_MUX[3]	MAIN[4][4]
HEX_V5[0]	HEX_V5_MUX[0]	MAIN[44][4]
HEX_V5[1]	HEX_V5_MUX[1]	MAIN[27][4]
HEX_V5[2]	HEX_V5_MUX[2]	MAIN[20][4]
HEX_V5[3]	HEX_V5_MUX[3]	MAIN[3][4]
HEX_V6[0]	HEX_V6_MUX[0]	MAIN[47][4]
HEX_V6[1]	HEX_V6_MUX[1]	MAIN[24][4]
HEX_V6[2]	HEX_V6_MUX[2]	MAIN[23][4]
HEX_V6[3]	HEX_V6_MUX[3]	MAIN[0][4]
LH[0]	LH_MUX[0]	MAIN[10][15]
LH[6]	LH_MUX[6]	MAIN[3][15]
LV[0]	LV_MUX[0]	MAIN[26][12]
LV[1]	LV_MUX[1]	MAIN[29][12]
LV[2]	LV_MUX[2]	MAIN[34][12]
LV[3]	LV_MUX[3]	MAIN[37][12]
LV[4]	LV_MUX[4]	MAIN[42][12]
LV[5]	LV_MUX[5]	MAIN[45][12]
LV[6]	LV_MUX[6]	MAIN[21][12]
LV[7]	LV_MUX[7]	MAIN[18][12]
LV[8]	LV_MUX[8]	MAIN[13][12]
LV[9]	LV_MUX[9]	MAIN[10][12]
LV[10]	LV_MUX[10]	MAIN[5][12]
LV[11]	LV_MUX[11]	MAIN[2][12]

virtex IO_N switchbox INT pass gates
Destination	Source	Bit
SINGLE_S[0]	HEX_H6[0]	MAIN[47][8]
SINGLE_S[1]	HEX_H3[0]	MAIN[45][8]
SINGLE_S[1]	OUT_IO_I[2]	MAIN[44][8]
SINGLE_S[2]	HEX_H0[0]	MAIN[43][8]
SINGLE_S[2]	OUT_IO_I[1]	MAIN[42][8]
SINGLE_S[3]	HEX_H6[0]	MAIN[41][8]
SINGLE_S[4]	HEX_H3[0]	MAIN[38][8]
SINGLE_S[5]	HEX_H0[0]	MAIN[36][8]
SINGLE_S[5]	OUT_IO_IQ[2]	MAIN[37][8]
SINGLE_S[6]	HEX_H6[1]	MAIN[35][8]
SINGLE_S[6]	OUT_IO_IQ[1]	MAIN[34][8]
SINGLE_S[7]	HEX_H3[1]	MAIN[33][8]
SINGLE_S[8]	HEX_H0[1]	MAIN[31][8]
SINGLE_S[9]	HEX_H6[1]	MAIN[29][8]
SINGLE_S[9]	OUT_IO_I[2]	MAIN[28][8]
SINGLE_S[10]	HEX_H3[1]	MAIN[26][8]
SINGLE_S[10]	OUT_IO_I[1]	MAIN[27][8]
SINGLE_S[11]	HEX_H0[1]	MAIN[24][8]
SINGLE_S[12]	HEX_H6[2]	MAIN[23][8]
SINGLE_S[13]	HEX_H3[2]	MAIN[21][8]
SINGLE_S[13]	OUT_IO_IQ[2]	MAIN[20][8]
SINGLE_S[14]	HEX_H0[2]	MAIN[19][8]
SINGLE_S[14]	OUT_IO_IQ[1]	MAIN[18][8]
SINGLE_S[15]	HEX_H6[2]	MAIN[17][8]
SINGLE_S[16]	HEX_H3[2]	MAIN[14][8]
SINGLE_S[17]	HEX_H0[2]	MAIN[12][8]
SINGLE_S[17]	OUT_IO_I[2]	MAIN[13][8]
SINGLE_S[18]	HEX_H6[3]	MAIN[11][8]
SINGLE_S[18]	OUT_IO_I[1]	MAIN[10][8]
SINGLE_S[19]	HEX_H3[3]	MAIN[9][8]
SINGLE_S[20]	HEX_H0[3]	MAIN[7][8]
SINGLE_S[21]	HEX_H6[3]	MAIN[5][8]
SINGLE_S[21]	OUT_IO_IQ[2]	MAIN[4][8]
SINGLE_S[22]	HEX_H3[3]	MAIN[2][8]
SINGLE_S[22]	OUT_IO_IQ[1]	MAIN[3][8]
SINGLE_S[23]	HEX_H0[3]	MAIN[0][8]

virtex IO_N switchbox INT muxes HEX_H0_MUX[0]
Bits							Destination
MAIN[41][6]	MAIN[40][6]	MAIN[42][6]	MAIN[44][6]	MAIN[39][6]	MAIN[37][5]	MAIN[43][6]	HEX_H0_MUX[0]
							Source
0	0	0	0	0	0	1	HEX_H6[0]
0	0	0	0	0	1	0	HEX_V3[2]
0	0	0	0	1	0	0	HEX_V6[3]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_H0_MUX[1]
Bits							Destination
MAIN[29][6]	MAIN[28][6]	MAIN[30][6]	MAIN[32][6]	MAIN[27][6]	MAIN[25][5]	MAIN[31][6]	HEX_H0_MUX[1]
							Source
0	0	0	0	0	0	1	HEX_H6[1]
0	0	0	0	0	1	0	HEX_V3[3]
0	0	0	0	1	0	0	HEX_V6[0]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_H0_MUX[2]
Bits							Destination
MAIN[17][6]	MAIN[16][6]	MAIN[18][6]	MAIN[20][6]	MAIN[15][6]	MAIN[13][5]	MAIN[19][6]	HEX_H0_MUX[2]
							Source
0	0	0	0	0	0	1	HEX_H6[2]
0	0	0	0	0	1	0	HEX_V3[0]
0	0	0	0	1	0	0	HEX_V6[1]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_H0_MUX[3]
Bits							Destination
MAIN[5][6]	MAIN[4][6]	MAIN[6][6]	MAIN[8][6]	MAIN[3][6]	MAIN[1][5]	MAIN[7][6]	HEX_H0_MUX[3]
							Source
0	0	0	0	0	0	1	HEX_H6[3]
0	0	0	0	0	1	0	HEX_V3[1]
0	0	0	0	1	0	0	HEX_V6[2]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_H0_MUX[4]
Bits							Destination
MAIN[41][15]	MAIN[39][15]	MAIN[40][15]	MAIN[43][15]	MAIN[44][15]	MAIN[35][15]	MAIN[34][15]	HEX_H0_MUX[4]
							Source
0	0	0	0	0	0	1	SINGLE_S_BUF[0]
0	0	0	0	0	1	0	SINGLE_S_BUF[7]
0	0	0	0	1	0	0	HEX_H6[4]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	1	0	0	0	OUT_IO_I[1]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	1	0	0	0	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_H0_MUX[5]
Bits							Destination
MAIN[23][15]	MAIN[25][15]	MAIN[22][15]	MAIN[20][15]	MAIN[18][15]	MAIN[27][15]	MAIN[29][15]	HEX_H0_MUX[5]
							Source
0	0	0	0	0	0	1	SINGLE_S_BUF[12]
0	0	0	0	0	1	0	SINGLE_S_BUF[19]
0	0	0	0	1	0	0	HEX_H6[5]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	1	0	0	0	OUT_IO_I[1]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	1	0	0	0	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_H6_MUX[0]
Bits							Destination
MAIN[46][6]	MAIN[37][6]	MAIN[46][5]	MAIN[38][6]	MAIN[47][5]	MAIN[45][6]	MAIN[36][5]	HEX_H6_MUX[0]
							Source
0	0	0	0	0	0	1	HEX_H0[0]
0	0	0	0	0	1	0	HEX_V3[2]
0	0	0	0	1	0	0	HEX_V6[0]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_H6_MUX[1]
Bits							Destination
MAIN[34][6]	MAIN[25][6]	MAIN[34][5]	MAIN[26][6]	MAIN[35][5]	MAIN[33][6]	MAIN[24][5]	HEX_H6_MUX[1]
							Source
0	0	0	0	0	0	1	HEX_H0[1]
0	0	0	0	0	1	0	HEX_V3[3]
0	0	0	0	1	0	0	HEX_V6[1]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_H6_MUX[2]
Bits							Destination
MAIN[22][6]	MAIN[13][6]	MAIN[22][5]	MAIN[14][6]	MAIN[23][5]	MAIN[21][6]	MAIN[12][5]	HEX_H6_MUX[2]
							Source
0	0	0	0	0	0	1	HEX_H0[2]
0	0	0	0	0	1	0	HEX_V3[0]
0	0	0	0	1	0	0	HEX_V6[2]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_H6_MUX[3]
Bits							Destination
MAIN[10][6]	MAIN[1][6]	MAIN[10][5]	MAIN[2][6]	MAIN[11][5]	MAIN[9][6]	MAIN[0][5]	HEX_H6_MUX[3]
							Source
0	0	0	0	0	0	1	HEX_H0[3]
0	0	0	0	0	1	0	HEX_V3[1]
0	0	0	0	1	0	0	HEX_V6[3]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	1	0	OUT_IO_I[1]
0	1	1	0	1	0	0	OUT_IO_I[2]
1	0	1	0	0	1	0	OUT_IO_IQ[1]
1	0	1	0	1	0	0	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_H6_MUX[4]
Bits							Destination
MAIN[24][15]	MAIN[31][15]	MAIN[16][15]	MAIN[21][15]	MAIN[17][15]	MAIN[26][15]	MAIN[30][15]	HEX_H6_MUX[4]
							Source
0	0	0	0	0	0	1	SINGLE_S_BUF[12]
0	0	0	0	0	1	0	SINGLE_S_BUF[19]
0	0	0	0	1	0	0	HEX_H0[4]
0	0	0	1	0	0	0	LH[0]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	1	0	0	0	OUT_IO_I[1]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	1	0	0	0	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_H6_MUX[5]
Bits							Destination
MAIN[36][15]	MAIN[32][15]	MAIN[47][15]	MAIN[42][15]	MAIN[46][15]	MAIN[38][15]	MAIN[33][15]	HEX_H6_MUX[5]
							Source
0	0	0	0	0	0	1	SINGLE_S_BUF[0]
0	0	0	0	0	1	0	SINGLE_S_BUF[7]
0	0	0	0	1	0	0	HEX_H0[5]
0	0	0	1	0	0	0	LH[6]
0	0	1	0	0	0	0	off
0	1	1	0	0	0	1	OUT_IO_I[2]
0	1	1	1	0	0	0	OUT_IO_I[1]
1	0	1	0	0	0	1	OUT_IO_IQ[2]
1	0	1	1	0	0	0	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V1_MUX[0]
Bits		Destination
MAIN[37][2]	MAIN[36][2]	HEX_V1_MUX[0]
		Source
0	0	LV[5]
0	1	off
1	1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V1_MUX[1]
Bits			Destination
MAIN[33][2]	MAIN[33][0]	MAIN[35][2]	HEX_V1_MUX[1]
			Source
0	0	0	LV[5]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V1_MUX[2]
Bits		Destination
MAIN[13][2]	MAIN[12][2]	HEX_V1_MUX[2]
		Source
0	0	LV[11]
0	1	off
1	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V1_MUX[3]
Bits			Destination
MAIN[9][2]	MAIN[9][0]	MAIN[11][2]	HEX_V1_MUX[3]
			Source
0	0	0	LV[11]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V2_MUX[0]
Bits		Destination
MAIN[36][0]	MAIN[39][0]	HEX_V2_MUX[0]
		Source
0	0	LV[4]
0	1	off
1	1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V2_MUX[1]
Bits			Destination
MAIN[32][2]	MAIN[34][0]	MAIN[32][0]	HEX_V2_MUX[1]
			Source
0	0	0	LV[4]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V2_MUX[2]
Bits		Destination
MAIN[12][0]	MAIN[15][0]	HEX_V2_MUX[2]
		Source
0	0	LV[10]
0	1	off
1	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V2_MUX[3]
Bits			Destination
MAIN[8][2]	MAIN[10][0]	MAIN[8][0]	HEX_V2_MUX[3]
			Source
0	0	0	LV[10]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V3_MUX[0]
Bits			Destination
MAIN[42][0]	MAIN[41][2]	MAIN[40][2]	HEX_V3_MUX[0]
			Source
0	0	0	LV[3]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V3_MUX[1]
Bits		Destination
MAIN[29][2]	MAIN[31][2]	HEX_V3_MUX[1]
		Source
0	0	LV[3]
0	1	off
1	1	OUT_IO_I[1]

virtex IO_N switchbox INT muxes HEX_V3_MUX[2]
Bits			Destination
MAIN[18][0]	MAIN[17][2]	MAIN[16][2]	HEX_V3_MUX[2]
			Source
0	0	0	LV[9]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V3_MUX[3]
Bits		Destination
MAIN[5][2]	MAIN[7][2]	HEX_V3_MUX[3]
		Source
0	0	LV[9]
0	1	off
1	1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V4_MUX[0]
Bits			Destination
MAIN[41][0]	MAIN[40][0]	MAIN[43][0]	HEX_V4_MUX[0]
			Source
0	0	0	LV[2]
0	0	1	off
0	1	1	OUT_IO_IQ[1]
1	0	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V4_MUX[1]
Bits		Destination
MAIN[28][2]	MAIN[28][0]	HEX_V4_MUX[1]
		Source
0	0	LV[2]
0	1	off
1	1	OUT_IO_I[1]

virtex IO_N switchbox INT muxes HEX_V4_MUX[2]
Bits			Destination
MAIN[17][0]	MAIN[16][0]	MAIN[19][0]	HEX_V4_MUX[2]
			Source
0	0	0	LV[8]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V4_MUX[3]
Bits		Destination
MAIN[4][2]	MAIN[4][0]	HEX_V4_MUX[3]
		Source
0	0	LV[8]
0	1	off
1	1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V5_MUX[0]
Bits			Destination
MAIN[44][0]	MAIN[46][4]	MAIN[44][2]	HEX_V5_MUX[0]
			Source
0	0	0	LV[1]
0	0	1	off
0	1	1	OUT_IO_I[1]
1	0	1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V5_MUX[1]
Bits		Destination
MAIN[26][0]	MAIN[27][2]	HEX_V5_MUX[1]
		Source
0	0	LV[1]
0	1	off
1	1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V5_MUX[2]
Bits		Destination
MAIN[22][4]	MAIN[20][2]	HEX_V5_MUX[2]
		Source
0	0	LV[7]
0	1	off
1	1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V5_MUX[3]
Bits			Destination
MAIN[2][0]	MAIN[3][0]	MAIN[3][2]	HEX_V5_MUX[3]
			Source
0	0	0	LV[7]
0	0	1	off
0	1	1	OUT_IO_I[2]
1	0	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_V6_MUX[0]
Bits					Destination
MAIN[46][2]	MAIN[46][0]	MAIN[45][4]	MAIN[47][0]	MAIN[47][2]	HEX_V6_MUX[0]
					Source
0	0	1	1	1	HEX_H0[1]
0	1	0	1	1	HEX_H3[3]
0	1	1	0	1	HEX_H6[0]
0	1	1	1	0	LV[0]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_I[1]

virtex IO_N switchbox INT muxes HEX_V6_MUX[1]
Bits					Destination
MAIN[26][2]	MAIN[26][4]	MAIN[24][0]	MAIN[25][0]	MAIN[24][2]	HEX_V6_MUX[1]
					Source
0	0	1	1	1	HEX_H0[2]
0	1	0	1	1	HEX_H3[0]
0	1	1	0	1	HEX_H6[1]
0	1	1	1	0	LV[0]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes HEX_V6_MUX[2]
Bits					Destination
MAIN[22][2]	MAIN[21][4]	MAIN[23][0]	MAIN[22][0]	MAIN[23][2]	HEX_V6_MUX[2]
					Source
0	0	1	1	1	HEX_H0[3]
0	1	0	1	1	HEX_H3[1]
0	1	1	0	1	HEX_H6[2]
0	1	1	1	0	LV[6]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_V6_MUX[3]
Bits					Destination
MAIN[2][2]	MAIN[0][0]	MAIN[1][0]	MAIN[2][4]	MAIN[0][2]	HEX_V6_MUX[3]
					Source
0	0	1	1	1	HEX_H0[0]
0	1	0	1	1	HEX_H3[2]
0	1	1	0	1	HEX_H6[3]
0	1	1	1	0	LV[6]
0	1	1	1	1	off
1	1	1	1	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_S0[0]
Bits				Destination
MAIN[42][1]	MAIN[39][1]	MAIN[38][1]	MAIN[47][1]	HEX_S0[0]
				Source
0	1	1	1	HEX_H0[2]
1	0	1	1	HEX_H3[1]
1	1	0	1	HEX_H6[0]
1	1	1	0	HEX_N1[0]
1	1	1	1	off

virtex IO_N switchbox INT muxes HEX_S0[1]
Bits						Destination
MAIN[19][1]	MAIN[22][1]	MAIN[15][1]	MAIN[14][1]	MAIN[18][1]	MAIN[23][1]	HEX_S0[1]
						Source
0	0	0	1	1	1	HEX_H0[1]
0	0	1	0	1	1	HEX_H3[0]
0	0	1	1	0	1	HEX_H6[3]
0	0	1	1	1	0	HEX_N1[1]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[1]
1	0	1	1	1	1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_S0[2]
Bits						Destination
MAIN[31][1]	MAIN[34][1]	MAIN[26][1]	MAIN[30][1]	MAIN[27][1]	MAIN[35][1]	HEX_S0[2]
						Source
0	0	0	1	1	1	HEX_H0[0]
0	0	1	0	1	1	HEX_H3[3]
0	0	1	1	0	1	HEX_H6[2]
0	0	1	1	1	0	HEX_N1[2]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_S0[3]
Bits				Destination
MAIN[6][1]	MAIN[3][1]	MAIN[2][1]	MAIN[11][1]	HEX_S0[3]
				Source
0	1	1	1	HEX_H0[3]
1	0	1	1	HEX_H3[2]
1	1	0	1	HEX_H6[1]
1	1	1	0	HEX_N1[3]
1	1	1	1	off

virtex IO_N switchbox INT muxes HEX_S1[0]
Bits				Destination
MAIN[41][1]	MAIN[40][1]	MAIN[37][1]	MAIN[36][1]	HEX_S1[0]
				Source
0	1	1	1	HEX_H0[2]
1	0	1	1	HEX_H3[1]
1	1	0	1	HEX_H6[0]
1	1	1	0	HEX_N2[0]
1	1	1	1	off

virtex IO_N switchbox INT muxes HEX_S1[1]
Bits						Destination
MAIN[20][1]	MAIN[21][1]	MAIN[16][1]	MAIN[13][1]	MAIN[17][1]	MAIN[12][1]	HEX_S1[1]
						Source
0	0	0	1	1	1	HEX_H0[1]
0	0	1	0	1	1	HEX_H3[0]
0	0	1	1	0	1	HEX_H6[3]
0	0	1	1	1	0	HEX_N2[1]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[1]
1	0	1	1	1	1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes HEX_S1[2]
Bits						Destination
MAIN[32][1]	MAIN[33][1]	MAIN[25][1]	MAIN[29][1]	MAIN[28][1]	MAIN[24][1]	HEX_S1[2]
						Source
0	0	0	1	1	1	HEX_H0[0]
0	0	1	0	1	1	HEX_H3[3]
0	0	1	1	0	1	HEX_H6[2]
0	0	1	1	1	0	HEX_N2[2]
0	0	1	1	1	1	off
0	1	1	1	1	1	OUT_IO_I[2]
1	0	1	1	1	1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes HEX_S1[3]
Bits				Destination
MAIN[5][1]	MAIN[4][1]	MAIN[1][1]	MAIN[0][1]	HEX_S1[3]
				Source
0	1	1	1	HEX_H0[3]
1	0	1	1	HEX_H3[2]
1	1	0	1	HEX_H6[1]
1	1	1	0	HEX_N2[3]
1	1	1	1	off

virtex IO_N switchbox INT muxes LH_MUX[0]
Bits									Destination
MAIN[9][15]	MAIN[12][12]	MAIN[4][15]	MAIN[6][15]	MAIN[15][15]	MAIN[14][12]	MAIN[8][15]	MAIN[13][15]	MAIN[1][12]	LH_MUX[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	1	SINGLE_S_BUF[5]
0	0	0	0	0	0	0	1	0	SINGLE_S_BUF[6]
0	0	0	0	0	0	1	0	0	SINGLE_S_BUF[10]
0	0	0	0	0	1	0	0	0	SINGLE_S_BUF[11]
0	0	0	0	1	0	0	0	0	SINGLE_S_BUF[17]
0	0	0	1	0	0	0	0	0	SINGLE_S_BUF[18]
0	0	1	0	0	0	0	0	0	SINGLE_S_BUF[22]
0	1	0	0	0	0	0	0	0	SINGLE_S_BUF[23]
1	0	0	0	0	0	0	1	0	OUT_IO_IQ[2]
1	0	0	0	0	0	1	0	0	OUT_IO_I[2]
1	0	0	0	1	0	0	0	0	OUT_IO_IQ[1]
1	0	1	0	0	0	0	0	0	OUT_IO_I[1]

virtex IO_N switchbox INT muxes LH_MUX[6]
Bits									Destination
MAIN[5][15]	MAIN[9][12]	MAIN[1][15]	MAIN[7][15]	MAIN[14][15]	MAIN[11][15]	MAIN[12][15]	MAIN[2][15]	MAIN[0][15]	LH_MUX[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	1	SINGLE_S_BUF[5]
0	0	0	0	0	0	0	1	0	SINGLE_S_BUF[6]
0	0	0	0	0	0	1	0	0	SINGLE_S_BUF[10]
0	0	0	0	0	1	0	0	0	SINGLE_S_BUF[11]
0	0	0	0	1	0	0	0	0	SINGLE_S_BUF[17]
0	0	0	1	0	0	0	0	0	SINGLE_S_BUF[18]
0	0	1	0	0	0	0	0	0	SINGLE_S_BUF[22]
0	1	0	0	0	0	0	0	0	SINGLE_S_BUF[23]
1	0	0	0	0	0	0	1	0	OUT_IO_IQ[2]
1	0	0	0	0	0	1	0	0	OUT_IO_I[2]
1	0	0	0	1	0	0	0	0	OUT_IO_IQ[1]
1	0	1	0	0	0	0	0	0	OUT_IO_I[1]

virtex IO_N switchbox INT muxes LV_MUX[0]
Bits	Destination
LV_MUX[0]
	Source
HEX_H6[5]

virtex IO_N switchbox INT muxes LV_MUX[1]
Bits	Destination
LV_MUX[1]
	Source
HEX_H5[5]

virtex IO_N switchbox INT muxes LV_MUX[2]
Bits	Destination
MAIN[32][12]	LV_MUX[2]
	Source
0	HEX_H4[5]
1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes LV_MUX[3]
Bits	Destination
MAIN[39][12]	LV_MUX[3]
	Source
0	HEX_H3[5]
1	OUT_IO_IQ[1]

virtex IO_N switchbox INT muxes LV_MUX[4]
Bits	Destination
MAIN[40][12]	LV_MUX[4]
	Source
0	HEX_H2[5]
1	OUT_IO_I[1]

virtex IO_N switchbox INT muxes LV_MUX[5]
Bits	Destination
MAIN[47][12]	LV_MUX[5]
	Source
0	HEX_H1[5]
1	OUT_IO_I[1]

virtex IO_N switchbox INT muxes LV_MUX[6]
Bits	Destination
MAIN[23][12]	LV_MUX[6]
	Source
0	HEX_H6[4]
1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes LV_MUX[7]
Bits	Destination
MAIN[16][12]	LV_MUX[7]
	Source
0	HEX_H5[4]
1	OUT_IO_IQ[2]

virtex IO_N switchbox INT muxes LV_MUX[8]
Bits	Destination
MAIN[15][12]	LV_MUX[8]
	Source
0	HEX_H4[4]
1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes LV_MUX[9]
Bits	Destination
MAIN[8][12]	LV_MUX[9]
	Source
0	HEX_H3[4]
1	OUT_IO_I[2]

virtex IO_N switchbox INT muxes LV_MUX[10]
Bits	Destination
LV_MUX[10]
	Source
HEX_H2[4]

virtex IO_N switchbox INT muxes LV_MUX[11]
Bits	Destination
LV_MUX[11]
	Source
HEX_H1[4]

virtex IO_N switchbox INT muxes IMUX_IO_CLK[0]
Bits												Destination
MAIN[30][12]	MAIN[30][14]	MAIN[29][14]	MAIN[36][13]	MAIN[26][14]	MAIN[30][13]	MAIN[24][13]	MAIN[25][14]	MAIN[25][13]	MAIN[27][13]	MAIN[27][14]	MAIN[35][13]	IMUX_IO_CLK[0]
												Source
0	0	0	0	0	0	1	1	1	1	1	1	GCLK_BUF[0]
0	0	0	0	0	1	0	1	1	1	1	1	GCLK_BUF[1]
0	0	0	0	0	1	1	0	1	1	1	1	GCLK_BUF[2]
0	0	0	0	0	1	1	1	0	1	1	1	GCLK_BUF[3]
0	0	0	0	0	1	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	0	1	1	HEX_V2_BUF[2]
0	0	0	1	0	1	1	1	1	1	0	1	HEX_H5_BUF[2]
0	0	0	1	0	1	1	1	1	1	1	0	HEX_V1_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	1	SINGLE_S_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	1	HEX_H1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	1	HEX_H4_BUF[2]
0	0	1	0	0	1	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[9]
0	1	0	0	0	1	1	1	1	0	1	1	HEX_V6_BUF[2]
0	1	0	0	0	1	1	1	1	1	0	1	HEX_H6_BUF[2]
0	1	0	0	0	1	1	1	1	1	1	0	HEX_V3_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	1	HEX_H2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	1	HEX_H3_BUF[2]
1	0	0	0	0	1	1	1	1	1	1	0	HEX_V4_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[15]

virtex IO_N switchbox INT muxes IMUX_IO_CLK[1]
Bits												Destination
MAIN[28][14]	MAIN[31][14]	MAIN[28][13]	MAIN[33][13]	MAIN[25][12]	MAIN[24][14]	MAIN[31][13]	MAIN[34][13]	MAIN[26][13]	MAIN[32][13]	MAIN[29][13]	MAIN[37][13]	IMUX_IO_CLK[1]
												Source
0	0	0	0	0	0	1	1	1	1	1	1	GCLK_BUF[0]
0	0	0	0	0	1	0	1	1	1	1	1	GCLK_BUF[1]
0	0	0	0	0	1	1	0	1	1	1	1	GCLK_BUF[2]
0	0	0	0	0	1	1	1	0	1	1	1	GCLK_BUF[3]
0	0	0	0	0	1	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	0	1	1	HEX_V2_BUF[2]
0	0	0	1	0	1	1	1	1	1	0	1	HEX_H5_BUF[2]
0	0	0	1	0	1	1	1	1	1	1	0	HEX_V1_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	1	SINGLE_S_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	1	HEX_H1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	1	HEX_H4_BUF[2]
0	0	1	0	0	1	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[9]
0	1	0	0	0	1	1	1	1	0	1	1	HEX_V6_BUF[2]
0	1	0	0	0	1	1	1	1	1	0	1	HEX_H6_BUF[2]
0	1	0	0	0	1	1	1	1	1	1	0	HEX_V3_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	1	HEX_H2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	1	HEX_H3_BUF[2]
1	0	0	0	0	1	1	1	1	1	1	0	HEX_V4_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[15]

virtex IO_N switchbox INT muxes IMUX_IO_CLK[2]
Bits												Destination
MAIN[19][14]	MAIN[16][14]	MAIN[19][13]	MAIN[14][13]	MAIN[22][12]	MAIN[23][14]	MAIN[16][13]	MAIN[13][13]	MAIN[21][13]	MAIN[15][13]	MAIN[18][13]	MAIN[10][13]	IMUX_IO_CLK[2]
												Source
0	0	0	0	0	0	1	1	1	1	1	1	GCLK_BUF[0]
0	0	0	0	0	1	0	1	1	1	1	1	GCLK_BUF[1]
0	0	0	0	0	1	1	0	1	1	1	1	GCLK_BUF[2]
0	0	0	0	0	1	1	1	0	1	1	1	GCLK_BUF[3]
0	0	0	0	0	1	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	0	1	1	HEX_V2_BUF[2]
0	0	0	1	0	1	1	1	1	1	0	1	HEX_H5_BUF[2]
0	0	0	1	0	1	1	1	1	1	1	0	HEX_V1_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	1	SINGLE_S_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	1	HEX_H1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	1	HEX_H4_BUF[2]
0	0	1	0	0	1	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[9]
0	1	0	0	0	1	1	1	1	0	1	1	HEX_V6_BUF[2]
0	1	0	0	0	1	1	1	1	1	0	1	HEX_H6_BUF[2]
0	1	0	0	0	1	1	1	1	1	1	0	HEX_V3_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	1	HEX_H2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	1	HEX_H3_BUF[2]
1	0	0	0	0	1	1	1	1	1	1	0	HEX_V4_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[15]

virtex IO_N switchbox INT muxes IMUX_IO_CLK[3]
Bits												Destination
MAIN[17][12]	MAIN[17][14]	MAIN[18][14]	MAIN[11][13]	MAIN[21][14]	MAIN[17][13]	MAIN[23][13]	MAIN[22][14]	MAIN[22][13]	MAIN[20][13]	MAIN[20][14]	MAIN[12][13]	IMUX_IO_CLK[3]
												Source
0	0	0	0	0	0	1	1	1	1	1	1	GCLK_BUF[0]
0	0	0	0	0	1	0	1	1	1	1	1	GCLK_BUF[1]
0	0	0	0	0	1	1	0	1	1	1	1	GCLK_BUF[2]
0	0	0	0	0	1	1	1	0	1	1	1	GCLK_BUF[3]
0	0	0	0	0	1	1	1	1	1	1	1	PULLUP
0	0	0	1	0	1	1	1	1	0	1	1	HEX_V2_BUF[2]
0	0	0	1	0	1	1	1	1	1	0	1	HEX_H5_BUF[2]
0	0	0	1	0	1	1	1	1	1	1	0	HEX_V1_BUF[2]
0	0	0	1	1	1	1	1	1	1	1	1	SINGLE_S_BUF[8]
0	0	1	0	0	1	1	1	1	0	1	1	HEX_H1_BUF[2]
0	0	1	0	0	1	1	1	1	1	0	1	HEX_H4_BUF[2]
0	0	1	0	0	1	1	1	1	1	1	0	HEX_V5_BUF[2]
0	0	1	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[9]
0	1	0	0	0	1	1	1	1	0	1	1	HEX_V6_BUF[2]
0	1	0	0	0	1	1	1	1	1	0	1	HEX_H6_BUF[2]
0	1	0	0	0	1	1	1	1	1	1	0	HEX_V3_BUF[2]
0	1	0	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[14]
1	0	0	0	0	1	1	1	1	0	1	1	HEX_H2_BUF[2]
1	0	0	0	0	1	1	1	1	1	0	1	HEX_H3_BUF[2]
1	0	0	0	0	1	1	1	1	1	1	0	HEX_V4_BUF[2]
1	0	0	0	1	1	1	1	1	1	1	1	SINGLE_S_BUF[15]

virtex IO_N switchbox INT muxes IMUX_IO_SR[0]
Bits						Destination
MAIN[29][10]	MAIN[30][10]	MAIN[31][10]	MAIN[33][9]	MAIN[32][11]	MAIN[33][11]	IMUX_IO_SR[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[4]
0	0	0	0	1	0	SINGLE_S_BUF[5]
0	0	0	1	0	0	SINGLE_S_BUF[6]
0	0	1	0	0	0	SINGLE_S_BUF[7]
0	1	0	0	0	1	HEX_H1_BUF[1]
0	1	0	0	1	0	HEX_H4_BUF[1]
0	1	0	1	0	0	HEX_V1_BUF[1]
0	1	1	0	0	0	HEX_V2_BUF[1]
1	0	0	0	0	1	HEX_V4_BUF[1]
1	0	0	0	1	0	HEX_V3_BUF[1]
1	0	0	1	0	0	HEX_V5_BUF[1]
1	0	1	0	0	0	HEX_V6_BUF[1]
1	1	0	0	0	1	HEX_H2_BUF[1]
1	1	0	0	1	0	HEX_H3_BUF[1]
1	1	0	1	0	0	HEX_H5_BUF[1]
1	1	1	0	0	0	HEX_H6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_SR[1]
Bits						Destination
MAIN[30][11]	MAIN[29][11]	MAIN[28][9]	MAIN[32][9]	MAIN[31][9]	MAIN[28][11]	IMUX_IO_SR[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[4]
0	0	0	0	1	0	SINGLE_S_BUF[5]
0	0	0	1	0	0	SINGLE_S_BUF[6]
0	0	1	0	0	0	SINGLE_S_BUF[7]
0	1	0	0	0	1	HEX_H1_BUF[1]
0	1	0	0	1	0	HEX_H4_BUF[1]
0	1	0	1	0	0	HEX_V1_BUF[1]
0	1	1	0	0	0	HEX_V2_BUF[1]
1	0	0	0	0	1	HEX_V4_BUF[1]
1	0	0	0	1	0	HEX_V3_BUF[1]
1	0	0	1	0	0	HEX_V5_BUF[1]
1	0	1	0	0	0	HEX_V6_BUF[1]
1	1	0	0	0	1	HEX_H2_BUF[1]
1	1	0	0	1	0	HEX_H3_BUF[1]
1	1	0	1	0	0	HEX_H5_BUF[1]
1	1	1	0	0	0	HEX_H6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_SR[2]
Bits						Destination
MAIN[35][11]	MAIN[36][11]	MAIN[37][10]	MAIN[38][9]	MAIN[36][9]	MAIN[37][11]	IMUX_IO_SR[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[4]
0	0	0	0	1	0	SINGLE_S_BUF[5]
0	0	0	1	0	0	SINGLE_S_BUF[6]
0	0	1	0	0	0	SINGLE_S_BUF[7]
0	1	0	0	0	1	HEX_H1_BUF[1]
0	1	0	0	1	0	HEX_H4_BUF[1]
0	1	0	1	0	0	HEX_V1_BUF[1]
0	1	1	0	0	0	HEX_V2_BUF[1]
1	0	0	0	0	1	HEX_V4_BUF[1]
1	0	0	0	1	0	HEX_V3_BUF[1]
1	0	0	1	0	0	HEX_V5_BUF[1]
1	0	1	0	0	0	HEX_V6_BUF[1]
1	1	0	0	0	1	HEX_H2_BUF[1]
1	1	0	0	1	0	HEX_H3_BUF[1]
1	1	0	1	0	0	HEX_H5_BUF[1]
1	1	1	0	0	0	HEX_H6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_SR[3]
Bits						Destination
MAIN[36][10]	MAIN[35][10]	MAIN[34][10]	MAIN[35][9]	MAIN[39][9]	MAIN[34][11]	IMUX_IO_SR[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[4]
0	0	0	0	1	0	SINGLE_S_BUF[5]
0	0	0	1	0	0	SINGLE_S_BUF[6]
0	0	1	0	0	0	SINGLE_S_BUF[7]
0	1	0	0	0	1	HEX_H1_BUF[1]
0	1	0	0	1	0	HEX_H4_BUF[1]
0	1	0	1	0	0	HEX_V1_BUF[1]
0	1	1	0	0	0	HEX_V2_BUF[1]
1	0	0	0	0	1	HEX_V4_BUF[1]
1	0	0	0	1	0	HEX_V3_BUF[1]
1	0	0	1	0	0	HEX_V5_BUF[1]
1	0	1	0	0	0	HEX_V6_BUF[1]
1	1	0	0	0	1	HEX_H2_BUF[1]
1	1	0	0	1	0	HEX_H3_BUF[1]
1	1	0	1	0	0	HEX_H5_BUF[1]
1	1	1	0	0	0	HEX_H6_BUF[1]

virtex IO_N switchbox INT muxes IMUX_IO_ICE[0]
Bits						Destination
MAIN[8][10]	MAIN[7][10]	MAIN[5][11]	MAIN[6][11]	MAIN[7][9]	MAIN[6][10]	IMUX_IO_ICE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[20]
0	0	0	0	1	0	SINGLE_S_BUF[21]
0	0	0	1	0	0	SINGLE_S_BUF[22]
0	0	1	0	0	0	SINGLE_S_BUF[23]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_ICE[1]
Bits						Destination
MAIN[7][11]	MAIN[8][11]	MAIN[9][11]	MAIN[4][9]	MAIN[5][9]	MAIN[9][10]	IMUX_IO_ICE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[20]
0	0	0	0	1	0	SINGLE_S_BUF[21]
0	0	0	1	0	0	SINGLE_S_BUF[22]
0	0	1	0	0	0	SINGLE_S_BUF[23]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_ICE[2]
Bits						Destination
MAIN[2][11]	MAIN[1][11]	MAIN[0][11]	MAIN[0][9]	MAIN[1][9]	MAIN[0][10]	IMUX_IO_ICE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[20]
0	0	0	0	1	0	SINGLE_S_BUF[21]
0	0	0	1	0	0	SINGLE_S_BUF[22]
0	0	1	0	0	0	SINGLE_S_BUF[23]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_ICE[3]
Bits						Destination
MAIN[1][10]	MAIN[2][10]	MAIN[3][11]	MAIN[4][11]	MAIN[2][9]	MAIN[3][10]	IMUX_IO_ICE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[20]
0	0	0	0	1	0	SINGLE_S_BUF[21]
0	0	0	1	0	0	SINGLE_S_BUF[22]
0	0	1	0	0	0	SINGLE_S_BUF[23]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_OCE[0]
Bits						Destination
MAIN[18][10]	MAIN[17][10]	MAIN[14][11]	MAIN[15][11]	MAIN[14][9]	MAIN[16][10]	IMUX_IO_OCE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[16]
0	0	0	0	1	0	SINGLE_S_BUF[17]
0	0	0	1	0	0	SINGLE_S_BUF[18]
0	0	1	0	0	0	SINGLE_S_BUF[19]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_OCE[1]
Bits						Destination
MAIN[17][11]	MAIN[18][11]	MAIN[19][11]	MAIN[16][9]	MAIN[15][9]	MAIN[19][9]	IMUX_IO_OCE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[16]
0	0	0	0	1	0	SINGLE_S_BUF[17]
0	0	0	1	0	0	SINGLE_S_BUF[18]
0	0	1	0	0	0	SINGLE_S_BUF[19]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_OCE[2]
Bits						Destination
MAIN[12][11]	MAIN[11][11]	MAIN[10][11]	MAIN[11][9]	MAIN[9][9]	MAIN[10][10]	IMUX_IO_OCE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[16]
0	0	0	0	1	0	SINGLE_S_BUF[17]
0	0	0	1	0	0	SINGLE_S_BUF[18]
0	0	1	0	0	0	SINGLE_S_BUF[19]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_OCE[3]
Bits						Destination
MAIN[11][10]	MAIN[12][10]	MAIN[13][11]	MAIN[8][9]	MAIN[12][9]	MAIN[13][10]	IMUX_IO_OCE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[16]
0	0	0	0	1	0	SINGLE_S_BUF[17]
0	0	0	1	0	0	SINGLE_S_BUF[18]
0	0	1	0	0	0	SINGLE_S_BUF[19]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_TCE[0]
Bits						Destination
MAIN[25][11]	MAIN[26][11]	MAIN[27][11]	MAIN[25][9]	MAIN[26][9]	MAIN[28][10]	IMUX_IO_TCE[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[10]
0	0	0	0	1	0	SINGLE_S_BUF[11]
0	0	0	1	0	0	SINGLE_S_BUF[12]
0	0	1	0	0	0	SINGLE_S_BUF[13]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_TCE[1]
Bits						Destination
MAIN[27][10]	MAIN[26][10]	MAIN[24][11]	MAIN[31][11]	MAIN[27][9]	MAIN[24][10]	IMUX_IO_TCE[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[10]
0	0	0	0	1	0	SINGLE_S_BUF[11]
0	0	0	1	0	0	SINGLE_S_BUF[12]
0	0	1	0	0	0	SINGLE_S_BUF[13]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_TCE[2]
Bits						Destination
MAIN[22][11]	MAIN[21][11]	MAIN[20][11]	MAIN[22][9]	MAIN[21][9]	MAIN[19][10]	IMUX_IO_TCE[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[10]
0	0	0	0	1	0	SINGLE_S_BUF[11]
0	0	0	1	0	0	SINGLE_S_BUF[12]
0	0	1	0	0	0	SINGLE_S_BUF[13]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_TCE[3]
Bits						Destination
MAIN[20][10]	MAIN[21][10]	MAIN[23][11]	MAIN[16][11]	MAIN[20][9]	MAIN[23][10]	IMUX_IO_TCE[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[10]
0	0	0	0	1	0	SINGLE_S_BUF[11]
0	0	0	1	0	0	SINGLE_S_BUF[12]
0	0	1	0	0	0	SINGLE_S_BUF[13]
0	1	0	0	0	1	HEX_V5_BUF[3]
0	1	0	0	1	0	HEX_V6_BUF[3]
0	1	0	1	0	0	HEX_H4_BUF[3]
0	1	1	0	0	0	HEX_H1_BUF[3]
1	0	0	0	0	1	HEX_V1_BUF[3]
1	0	0	0	1	0	HEX_V2_BUF[3]
1	0	0	1	0	0	HEX_V4_BUF[3]
1	0	1	0	0	0	HEX_V3_BUF[3]
1	1	0	0	0	1	HEX_H6_BUF[3]
1	1	0	0	1	0	HEX_H5_BUF[3]
1	1	0	1	0	0	HEX_H3_BUF[3]
1	1	1	0	0	0	HEX_H2_BUF[3]

virtex IO_N switchbox INT muxes IMUX_IO_O[0]
Bits									Destination
MAIN[41][13]	MAIN[42][13]	MAIN[47][13]	MAIN[46][13]	MAIN[45][14]	MAIN[44][13]	MAIN[43][13]	MAIN[44][14]	MAIN[45][13]	IMUX_IO_O[0]
									Source
0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	1	0	0	HEX_V6_BUF[0]
0	0	0	0	0	0	1	1	1	SINGLE_S_BUF[0]
0	0	0	0	0	1	0	0	0	HEX_V3_BUF[0]
0	0	0	0	0	1	0	1	1	SINGLE_S_BUF[1]
0	0	0	0	1	0	1	0	1	SINGLE_S_BUF[3]
0	0	0	0	1	1	0	0	1	SINGLE_S_BUF[2]
0	0	0	1	0	0	0	0	0	HEX_V5_BUF[0]
0	0	0	1	0	0	0	1	1	SINGLE_S_BUF[9]
0	0	0	1	1	0	0	0	1	SINGLE_S_BUF[4]
0	0	1	0	0	0	0	0	0	HEX_V4_BUF[0]
0	0	1	0	0	0	0	1	1	SINGLE_S_BUF[8]
0	0	1	0	1	0	0	0	1	SINGLE_S_BUF[5]
0	1	0	0	0	0	0	1	1	SINGLE_S_BUF[6]
0	1	0	0	1	0	0	0	1	SINGLE_S_BUF[10]
1	0	0	0	0	0	0	1	1	SINGLE_S_BUF[7]
1	0	0	0	1	0	0	0	1	SINGLE_S_BUF[11]

virtex IO_N switchbox INT muxes IMUX_IO_O[1]
Bits									Destination
MAIN[43][14]	MAIN[42][14]	MAIN[43][12]	MAIN[41][12]	MAIN[41][14]	MAIN[39][13]	MAIN[38][13]	MAIN[40][14]	MAIN[40][13]	IMUX_IO_O[1]
									Source
0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	1	0	0	HEX_V4_BUF[1]
0	0	0	0	0	0	1	1	1	SINGLE_S_BUF[0]
0	0	0	0	0	1	0	0	0	HEX_V3_BUF[1]
0	0	0	0	0	1	0	1	1	SINGLE_S_BUF[1]
0	0	0	0	1	0	1	0	1	SINGLE_S_BUF[3]
0	0	0	0	1	1	0	0	1	SINGLE_S_BUF[2]
0	0	0	1	0	0	0	0	0	HEX_V5_BUF[1]
0	0	0	1	0	0	0	1	1	SINGLE_S_BUF[9]
0	0	0	1	1	0	0	0	1	SINGLE_S_BUF[4]
0	0	1	0	0	0	0	0	0	HEX_V6_BUF[1]
0	0	1	0	0	0	0	1	1	SINGLE_S_BUF[8]
0	0	1	0	1	0	0	0	1	SINGLE_S_BUF[5]
0	1	0	0	0	0	0	1	1	SINGLE_S_BUF[6]
0	1	0	0	1	0	0	0	1	SINGLE_S_BUF[10]
1	0	0	0	0	0	0	1	1	SINGLE_S_BUF[7]
1	0	0	0	1	0	0	0	1	SINGLE_S_BUF[11]

virtex IO_N switchbox INT muxes IMUX_IO_O[2]
Bits									Destination
MAIN[8][13]	MAIN[9][13]	MAIN[4][12]	MAIN[6][12]	MAIN[7][14]	MAIN[5][14]	MAIN[4][14]	MAIN[6][14]	MAIN[7][13]	IMUX_IO_O[2]
									Source
0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	1	1	1	SINGLE_S_BUF[12]
0	0	0	0	0	1	0	1	1	SINGLE_S_BUF[13]
0	0	0	0	1	0	1	0	1	SINGLE_S_BUF[16]
0	0	0	0	1	1	0	0	1	SINGLE_S_BUF[17]
0	0	0	1	0	0	0	0	0	HEX_V5_BUF[2]
0	0	0	1	0	0	0	1	1	SINGLE_S_BUF[19]
0	0	0	1	1	0	0	0	1	SINGLE_S_BUF[14]
0	0	1	0	0	0	0	0	0	HEX_V6_BUF[2]
0	0	1	0	0	0	0	1	1	SINGLE_S_BUF[18]
0	0	1	0	1	0	0	0	1	SINGLE_S_BUF[15]
0	1	0	0	0	0	0	0	0	HEX_V4_BUF[2]
0	1	0	0	0	0	0	1	1	SINGLE_S_BUF[20]
0	1	0	0	1	0	0	0	1	SINGLE_S_BUF[23]
1	0	0	0	0	0	0	0	0	HEX_V3_BUF[2]
1	0	0	0	0	0	0	1	1	SINGLE_S_BUF[21]
1	0	0	0	1	0	0	0	1	SINGLE_S_BUF[22]

virtex IO_N switchbox INT muxes IMUX_IO_O[3]
Bits									Destination
MAIN[3][13]	MAIN[4][13]	MAIN[0][13]	MAIN[1][13]	MAIN[3][14]	MAIN[5][13]	MAIN[6][13]	MAIN[2][14]	MAIN[2][13]	IMUX_IO_O[3]
									Source
0	0	0	0	0	0	0	0	1	PULLUP
0	0	0	0	0	0	1	1	1	SINGLE_S_BUF[12]
0	0	0	0	0	1	0	1	1	SINGLE_S_BUF[13]
0	0	0	0	1	0	1	0	1	SINGLE_S_BUF[16]
0	0	0	0	1	1	0	0	1	SINGLE_S_BUF[17]
0	0	0	1	0	0	0	0	0	HEX_V5_BUF[3]
0	0	0	1	0	0	0	1	1	SINGLE_S_BUF[19]
0	0	0	1	1	0	0	0	1	SINGLE_S_BUF[14]
0	0	1	0	0	0	0	0	0	HEX_V4_BUF[3]
0	0	1	0	0	0	0	1	1	SINGLE_S_BUF[18]
0	0	1	0	1	0	0	0	1	SINGLE_S_BUF[15]
0	1	0	0	0	0	0	0	0	HEX_V6_BUF[3]
0	1	0	0	0	0	0	1	1	SINGLE_S_BUF[20]
0	1	0	0	1	0	0	0	1	SINGLE_S_BUF[23]
1	0	0	0	0	0	0	0	0	HEX_V3_BUF[3]
1	0	0	0	0	0	0	1	1	SINGLE_S_BUF[21]
1	0	0	0	1	0	0	0	1	SINGLE_S_BUF[22]

virtex IO_N switchbox INT muxes IMUX_IO_T[0]
Bits						Destination
MAIN[39][10]	MAIN[40][10]	MAIN[41][10]	MAIN[40][9]	MAIN[41][11]	MAIN[42][11]	IMUX_IO_T[0]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[0]
0	0	0	0	1	0	SINGLE_S_BUF[1]
0	0	0	1	0	0	SINGLE_S_BUF[2]
0	0	1	0	0	0	SINGLE_S_BUF[3]
0	1	0	0	0	1	HEX_H1_BUF[0]
0	1	0	0	1	0	HEX_H4_BUF[0]
0	1	0	1	0	0	HEX_V6_BUF[0]
0	1	1	0	0	0	HEX_V5_BUF[0]
1	0	0	0	0	1	HEX_V3_BUF[0]
1	0	0	0	1	0	HEX_V4_BUF[0]
1	0	0	1	0	0	HEX_V2_BUF[0]
1	0	1	0	0	0	HEX_V1_BUF[0]
1	1	0	0	0	1	HEX_H2_BUF[0]
1	1	0	0	1	0	HEX_H3_BUF[0]
1	1	0	1	0	0	HEX_H5_BUF[0]
1	1	1	0	0	0	HEX_H6_BUF[0]

virtex IO_N switchbox INT muxes IMUX_IO_T[1]
Bits						Destination
MAIN[40][11]	MAIN[39][11]	MAIN[38][10]	MAIN[42][9]	MAIN[43][9]	MAIN[38][11]	IMUX_IO_T[1]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[0]
0	0	0	0	1	0	SINGLE_S_BUF[1]
0	0	0	1	0	0	SINGLE_S_BUF[2]
0	0	1	0	0	0	SINGLE_S_BUF[3]
0	1	0	0	0	1	HEX_H1_BUF[0]
0	1	0	0	1	0	HEX_H4_BUF[0]
0	1	0	1	0	0	HEX_V6_BUF[0]
0	1	1	0	0	0	HEX_V5_BUF[0]
1	0	0	0	0	1	HEX_V3_BUF[0]
1	0	0	0	1	0	HEX_V4_BUF[0]
1	0	0	1	0	0	HEX_V2_BUF[0]
1	0	1	0	0	0	HEX_V1_BUF[0]
1	1	0	0	0	1	HEX_H2_BUF[0]
1	1	0	0	1	0	HEX_H3_BUF[0]
1	1	0	1	0	0	HEX_H5_BUF[0]
1	1	1	0	0	0	HEX_H6_BUF[0]

virtex IO_N switchbox INT muxes IMUX_IO_T[2]
Bits						Destination
MAIN[45][11]	MAIN[46][11]	MAIN[47][10]	MAIN[46][9]	MAIN[47][9]	MAIN[47][11]	IMUX_IO_T[2]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[0]
0	0	0	0	1	0	SINGLE_S_BUF[1]
0	0	0	1	0	0	SINGLE_S_BUF[2]
0	0	1	0	0	0	SINGLE_S_BUF[3]
0	1	0	0	0	1	HEX_H1_BUF[0]
0	1	0	0	1	0	HEX_H4_BUF[0]
0	1	0	1	0	0	HEX_V6_BUF[0]
0	1	1	0	0	0	HEX_V5_BUF[0]
1	0	0	0	0	1	HEX_V3_BUF[0]
1	0	0	0	1	0	HEX_V4_BUF[0]
1	0	0	1	0	0	HEX_V2_BUF[0]
1	0	1	0	0	0	HEX_V1_BUF[0]
1	1	0	0	0	1	HEX_H2_BUF[0]
1	1	0	0	1	0	HEX_H3_BUF[0]
1	1	0	1	0	0	HEX_H5_BUF[0]
1	1	1	0	0	0	HEX_H6_BUF[0]

virtex IO_N switchbox INT muxes IMUX_IO_T[3]
Bits						Destination
MAIN[46][10]	MAIN[45][10]	MAIN[44][10]	MAIN[45][9]	MAIN[43][11]	MAIN[44][11]	IMUX_IO_T[3]
						Source
0	0	0	0	0	0	PULLUP
0	0	0	0	0	1	SINGLE_S_BUF[0]
0	0	0	0	1	0	SINGLE_S_BUF[1]
0	0	0	1	0	0	SINGLE_S_BUF[2]
0	0	1	0	0	0	SINGLE_S_BUF[3]
0	1	0	0	0	1	HEX_H1_BUF[0]
0	1	0	0	1	0	HEX_H4_BUF[0]
0	1	0	1	0	0	HEX_V6_BUF[0]
0	1	1	0	0	0	HEX_V5_BUF[0]
1	0	0	0	0	1	HEX_V3_BUF[0]
1	0	0	0	1	0	HEX_V4_BUF[0]
1	0	0	1	0	0	HEX_V2_BUF[0]
1	0	1	0	0	0	HEX_V1_BUF[0]
1	1	0	0	0	1	HEX_H2_BUF[0]
1	1	0	0	1	0	HEX_H3_BUF[0]
1	1	0	1	0	0	HEX_H5_BUF[0]
1	1	1	0	0	0	HEX_H6_BUF[0]

Bels IOI

virtex IO_N bel IOI pins
Pin	Direction	IOI[0]	IOI[1]	IOI[2]	IOI[3]
ICLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[34][14]	IMUX_IO_CLK[2] invert by MAIN[13][14]	IMUX_IO_CLK[3]
OCLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[33][14]	IMUX_IO_CLK[2] invert by MAIN[14][14]	IMUX_IO_CLK[3]
TCLK	in	IMUX_IO_CLK[0]	IMUX_IO_CLK[1] invert by MAIN[32][14]	IMUX_IO_CLK[2] invert by MAIN[15][14]	IMUX_IO_CLK[3]
SR	in	IMUX_IO_SR[0]	IMUX_IO_SR[1] invert by MAIN[33][10]	IMUX_IO_SR[2] invert by MAIN[34][9]	IMUX_IO_SR[3]
ICE	in	IMUX_IO_ICE[0]	IMUX_IO_ICE[1] invert by !MAIN[5][10]	IMUX_IO_ICE[2] invert by !MAIN[4][10]	IMUX_IO_ICE[3]
OCE	in	IMUX_IO_OCE[0]	IMUX_IO_OCE[1] invert by !MAIN[14][10]	IMUX_IO_OCE[2] invert by !MAIN[13][9]	IMUX_IO_OCE[3]
TCE	in	IMUX_IO_TCE[0]	IMUX_IO_TCE[1] invert by !MAIN[25][10]	IMUX_IO_TCE[2] invert by !MAIN[23][9]	IMUX_IO_TCE[3]
O	in	IMUX_IO_O[0]	IMUX_IO_O[1] invert by !MAIN[38][14]	IMUX_IO_O[2] invert by !MAIN[9][14]	IMUX_IO_O[3]
T	in	IMUX_IO_T[0]	IMUX_IO_T[1] invert by !MAIN[42][10]	IMUX_IO_T[2] invert by !MAIN[43][10]	IMUX_IO_T[3]
I	out	OUT_IO_I[0]	OUT_IO_I[1]	OUT_IO_I[2]	OUT_IO_I[3]
IQ	out	OUT_IO_IQ[0]	OUT_IO_IQ[1]	OUT_IO_IQ[2]	OUT_IO_IQ[3]

virtex IO_N bel IOI attribute bits
Attribute	IOI[0]	IOI[1]	IOI[2]	IOI[3]
SHORTEN_JTAG_CHAIN	-	!MAIN[37][17]	!MAIN[28][17]	-
FFI_INIT bit 0	-	MAIN[46][16]	MAIN[19][16]	-
FFI_READBACK bit 0	-	MAIN[45][17]	MAIN[20][17]	-
FFI_LATCH	-	MAIN[44][16]	MAIN[21][16]	-
FFI_SR_ENABLE	-	MAIN[43][16]	MAIN[22][16]	-
FFI_SR_SYNC	-	MAIN[47][16]	MAIN[18][16]	-
FFI_DELAY_ENABLE	-	MAIN[38][17]	MAIN[27][17]	-
I_DELAY_ENABLE	-	MAIN[45][16]	MAIN[20][16]	-
FFO_INIT bit 0	-	!MAIN[39][16]	!MAIN[26][16]	-
FFO_READBACK bit 0	-	MAIN[39][17]	MAIN[26][17]	-
FFO_LATCH	-	MAIN[41][16]	MAIN[24][16]	-
FFO_SR_ENABLE	-	MAIN[42][16]	MAIN[23][16]	-
FFO_SR_SYNC	-	MAIN[38][16]	MAIN[27][16]	-
FFT_INIT bit 0	-	!MAIN[36][16]	!MAIN[29][16]	-
FFT_READBACK bit 0	-	MAIN[35][17]	MAIN[30][17]	-
FFT_LATCH	-	MAIN[34][16]	MAIN[31][16]	-
FFT_SR_ENABLE	-	MAIN[33][16]	MAIN[32][16]	-
FFT_SR_SYNC	-	MAIN[37][16]	MAIN[28][16]	-
MUX_O	-	[enum: IO_MUX_O]	[enum: IO_MUX_O]	-
MUX_T	-	[enum: IO_MUX_T]	[enum: IO_MUX_T]	-

virtex IO_N enum IO_MUX_O
IOI[1].MUX_O	MAIN[40][16]
IOI[2].MUX_O	MAIN[25][16]
O	0
FFO	1

virtex IO_N enum IO_MUX_T
IOI[1].MUX_T	MAIN[35][16]
IOI[2].MUX_T	MAIN[30][16]
T	0
FFT	1

Bel wires

virtex IO_N bel wires
Wire	Pins
IMUX_IO_CLK[0]	IOI[0].ICLK, IOI[0].OCLK, IOI[0].TCLK
IMUX_IO_CLK[1]	IOI[1].ICLK, IOI[1].OCLK, IOI[1].TCLK
IMUX_IO_CLK[2]	IOI[2].ICLK, IOI[2].OCLK, IOI[2].TCLK
IMUX_IO_CLK[3]	IOI[3].ICLK, IOI[3].OCLK, IOI[3].TCLK
IMUX_IO_SR[0]	IOI[0].SR
IMUX_IO_SR[1]	IOI[1].SR
IMUX_IO_SR[2]	IOI[2].SR
IMUX_IO_SR[3]	IOI[3].SR
IMUX_IO_ICE[0]	IOI[0].ICE
IMUX_IO_ICE[1]	IOI[1].ICE
IMUX_IO_ICE[2]	IOI[2].ICE
IMUX_IO_ICE[3]	IOI[3].ICE
IMUX_IO_OCE[0]	IOI[0].OCE
IMUX_IO_OCE[1]	IOI[1].OCE
IMUX_IO_OCE[2]	IOI[2].OCE
IMUX_IO_OCE[3]	IOI[3].OCE
IMUX_IO_TCE[0]	IOI[0].TCE
IMUX_IO_TCE[1]	IOI[1].TCE
IMUX_IO_TCE[2]	IOI[2].TCE
IMUX_IO_TCE[3]	IOI[3].TCE
IMUX_IO_O[0]	IOI[0].O
IMUX_IO_O[1]	IOI[1].O
IMUX_IO_O[2]	IOI[2].O
IMUX_IO_O[3]	IOI[3].O
IMUX_IO_T[0]	IOI[0].T
IMUX_IO_T[1]	IOI[1].T
IMUX_IO_T[2]	IOI[2].T
IMUX_IO_T[3]	IOI[3].T
OUT_IO_I[0]	IOI[0].I
OUT_IO_I[1]	IOI[1].I
OUT_IO_I[2]	IOI[2].I
OUT_IO_I[3]	IOI[3].I
OUT_IO_IQ[0]	IOI[0].IQ
OUT_IO_IQ[1]	IOI[1].IQ
OUT_IO_IQ[2]	IOI[2].IQ
OUT_IO_IQ[3]	IOI[3].IQ

Bitstream

virtex IO_N rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOI[2]: FFI_READBACK bit 0	-	-	-	-	-	IOI[2]: FFO_READBACK bit 0	IOI[2]: FFI_DELAY_ENABLE	IOI[2]: ! SHORTEN_JTAG_CHAIN	-	IOI[2]: FFT_READBACK bit 0	-	-	-	-	IOI[1]: FFT_READBACK bit 0	-	IOI[1]: ! SHORTEN_JTAG_CHAIN	IOI[1]: FFI_DELAY_ENABLE	IOI[1]: FFO_READBACK bit 0	-	-	-	-	-	IOI[1]: FFI_READBACK bit 0	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOI[2]: FFI_SR_SYNC	IOI[2]: FFI_INIT bit 0	IOI[2]: I_DELAY_ENABLE	IOI[2]: FFI_LATCH	IOI[2]: FFI_SR_ENABLE	IOI[2]: FFO_SR_ENABLE	IOI[2]: FFO_LATCH	IOI[2]: MUX_O bit 0	IOI[2]: ! FFO_INIT bit 0	IOI[2]: FFO_SR_SYNC	IOI[2]: FFT_SR_SYNC	IOI[2]: ! FFT_INIT bit 0	IOI[2]: MUX_T bit 0	IOI[2]: FFT_LATCH	IOI[2]: FFT_SR_ENABLE	IOI[1]: FFT_SR_ENABLE	IOI[1]: FFT_LATCH	IOI[1]: MUX_T bit 0	IOI[1]: ! FFT_INIT bit 0	IOI[1]: FFT_SR_SYNC	IOI[1]: FFO_SR_SYNC	IOI[1]: ! FFO_INIT bit 0	IOI[1]: MUX_O bit 0	IOI[1]: FFO_LATCH	IOI[1]: FFO_SR_ENABLE	IOI[1]: FFI_SR_ENABLE	IOI[1]: FFI_LATCH	IOI[1]: I_DELAY_ENABLE	IOI[1]: FFI_INIT bit 0	IOI[1]: FFI_SR_SYNC
B15	INT: mux LH_MUX[6] bit 0	INT: mux LH_MUX[6] bit 6	INT: mux LH_MUX[6] bit 1	INT: buffer LH[6] ← LH_MUX[6]	INT: mux LH_MUX[0] bit 6	INT: mux LH_MUX[6] bit 8	INT: mux LH_MUX[0] bit 5	INT: mux LH_MUX[6] bit 5	INT: mux LH_MUX[0] bit 2	INT: mux LH_MUX[0] bit 8	INT: buffer LH[0] ← LH_MUX[0]	INT: mux LH_MUX[6] bit 3	INT: mux LH_MUX[6] bit 2	INT: mux LH_MUX[0] bit 1	INT: mux LH_MUX[6] bit 4	INT: mux LH_MUX[0] bit 4	INT: mux HEX_H6_MUX[4] bit 4	INT: mux HEX_H6_MUX[4] bit 2	INT: mux HEX_H0_MUX[5] bit 2	INT: buffer HEX_H0[5] ← HEX_H0_MUX[5]	INT: mux HEX_H0_MUX[5] bit 3	INT: mux HEX_H6_MUX[4] bit 3	INT: mux HEX_H0_MUX[5] bit 4	INT: mux HEX_H0_MUX[5] bit 6	INT: mux HEX_H6_MUX[4] bit 6	INT: mux HEX_H0_MUX[5] bit 5	INT: mux HEX_H6_MUX[4] bit 1	INT: mux HEX_H0_MUX[5] bit 1	INT: buffer HEX_H6[4] ← HEX_H6_MUX[4]	INT: mux HEX_H0_MUX[5] bit 0	INT: mux HEX_H6_MUX[4] bit 0	INT: mux HEX_H6_MUX[4] bit 5	INT: mux HEX_H6_MUX[5] bit 5	INT: mux HEX_H6_MUX[5] bit 0	INT: mux HEX_H0_MUX[4] bit 0	INT: mux HEX_H0_MUX[4] bit 1	INT: mux HEX_H6_MUX[5] bit 6	INT: buffer HEX_H6[5] ← HEX_H6_MUX[5]	INT: mux HEX_H6_MUX[5] bit 1	INT: mux HEX_H0_MUX[4] bit 5	INT: mux HEX_H0_MUX[4] bit 4	INT: mux HEX_H0_MUX[4] bit 6	INT: mux HEX_H6_MUX[5] bit 3	INT: mux HEX_H0_MUX[4] bit 3	INT: mux HEX_H0_MUX[4] bit 2	INT: buffer HEX_H0[4] ← HEX_H0_MUX[4]	INT: mux HEX_H6_MUX[5] bit 2	INT: mux HEX_H6_MUX[5] bit 4
B14	-	-	INT: mux IMUX_IO_O[3] bit 1	INT: mux IMUX_IO_O[3] bit 4	INT: mux IMUX_IO_O[2] bit 2	INT: mux IMUX_IO_O[2] bit 3	INT: mux IMUX_IO_O[2] bit 1	INT: mux IMUX_IO_O[2] bit 4	-	IOI[2]: !invert O	-	-	-	IOI[2]: invert ICLK	IOI[2]: invert OCLK	IOI[2]: invert TCLK	INT: mux IMUX_IO_CLK[2] bit 10	INT: mux IMUX_IO_CLK[3] bit 10	INT: mux IMUX_IO_CLK[3] bit 9	INT: mux IMUX_IO_CLK[2] bit 11	INT: mux IMUX_IO_CLK[3] bit 1	INT: mux IMUX_IO_CLK[3] bit 7	INT: mux IMUX_IO_CLK[3] bit 4	INT: mux IMUX_IO_CLK[2] bit 6	INT: mux IMUX_IO_CLK[1] bit 6	INT: mux IMUX_IO_CLK[0] bit 4	INT: mux IMUX_IO_CLK[0] bit 7	INT: mux IMUX_IO_CLK[0] bit 1	INT: mux IMUX_IO_CLK[1] bit 11	INT: mux IMUX_IO_CLK[0] bit 9	INT: mux IMUX_IO_CLK[0] bit 10	INT: mux IMUX_IO_CLK[1] bit 10	IOI[1]: invert TCLK	IOI[1]: invert OCLK	IOI[1]: invert ICLK	-	-	-	IOI[1]: !invert O	-	INT: mux IMUX_IO_O[1] bit 1	INT: mux IMUX_IO_O[1] bit 4	INT: mux IMUX_IO_O[1] bit 7	INT: mux IMUX_IO_O[1] bit 8	INT: mux IMUX_IO_O[0] bit 1	INT: mux IMUX_IO_O[0] bit 4	-	-
B13	INT: mux IMUX_IO_O[3] bit 6	INT: mux IMUX_IO_O[3] bit 5	INT: mux IMUX_IO_O[3] bit 0	INT: mux IMUX_IO_O[3] bit 8	INT: mux IMUX_IO_O[3] bit 7	INT: mux IMUX_IO_O[3] bit 3	INT: mux IMUX_IO_O[3] bit 2	INT: mux IMUX_IO_O[2] bit 0	INT: mux IMUX_IO_O[2] bit 8	INT: mux IMUX_IO_O[2] bit 7	INT: mux IMUX_IO_CLK[2] bit 0	INT: mux IMUX_IO_CLK[3] bit 8	INT: mux IMUX_IO_CLK[3] bit 0	INT: mux IMUX_IO_CLK[2] bit 4	INT: mux IMUX_IO_CLK[2] bit 8	INT: mux IMUX_IO_CLK[2] bit 2	INT: mux IMUX_IO_CLK[2] bit 5	INT: mux IMUX_IO_CLK[3] bit 6	INT: mux IMUX_IO_CLK[2] bit 1	INT: mux IMUX_IO_CLK[2] bit 9	INT: mux IMUX_IO_CLK[3] bit 2	INT: mux IMUX_IO_CLK[2] bit 3	INT: mux IMUX_IO_CLK[3] bit 3	INT: mux IMUX_IO_CLK[3] bit 5	INT: mux IMUX_IO_CLK[0] bit 5	INT: mux IMUX_IO_CLK[0] bit 3	INT: mux IMUX_IO_CLK[1] bit 3	INT: mux IMUX_IO_CLK[0] bit 2	INT: mux IMUX_IO_CLK[1] bit 9	INT: mux IMUX_IO_CLK[1] bit 1	INT: mux IMUX_IO_CLK[0] bit 6	INT: mux IMUX_IO_CLK[1] bit 5	INT: mux IMUX_IO_CLK[1] bit 2	INT: mux IMUX_IO_CLK[1] bit 8	INT: mux IMUX_IO_CLK[1] bit 4	INT: mux IMUX_IO_CLK[0] bit 0	INT: mux IMUX_IO_CLK[0] bit 8	INT: mux IMUX_IO_CLK[1] bit 0	INT: mux IMUX_IO_O[1] bit 2	INT: mux IMUX_IO_O[1] bit 3	INT: mux IMUX_IO_O[1] bit 0	INT: mux IMUX_IO_O[0] bit 8	INT: mux IMUX_IO_O[0] bit 7	INT: mux IMUX_IO_O[0] bit 2	INT: mux IMUX_IO_O[0] bit 3	INT: mux IMUX_IO_O[0] bit 0	INT: mux IMUX_IO_O[0] bit 5	INT: mux IMUX_IO_O[0] bit 6
B12	-	INT: mux LH_MUX[0] bit 0	INT: buffer LV[11] ← LV_MUX[11]	-	INT: mux IMUX_IO_O[2] bit 6	INT: buffer LV[10] ← LV_MUX[10]	INT: mux IMUX_IO_O[2] bit 5	-	INT: mux LV_MUX[9] bit 0	INT: mux LH_MUX[6] bit 7	INT: buffer LV[9] ← LV_MUX[9]	-	INT: mux LH_MUX[0] bit 7	INT: buffer LV[8] ← LV_MUX[8]	INT: mux LH_MUX[0] bit 3	INT: mux LV_MUX[8] bit 0	INT: mux LV_MUX[7] bit 0	INT: mux IMUX_IO_CLK[3] bit 11	INT: buffer LV[7] ← LV_MUX[7]	-	-	INT: buffer LV[6] ← LV_MUX[6]	INT: mux IMUX_IO_CLK[2] bit 7	INT: mux LV_MUX[6] bit 0	-	INT: mux IMUX_IO_CLK[1] bit 7	INT: buffer LV[0] ← LV_MUX[0]	-	-	INT: buffer LV[1] ← LV_MUX[1]	INT: mux IMUX_IO_CLK[0] bit 11	-	INT: mux LV_MUX[2] bit 0	-	INT: buffer LV[2] ← LV_MUX[2]	-	-	INT: buffer LV[3] ← LV_MUX[3]	-	INT: mux LV_MUX[3] bit 0	INT: mux LV_MUX[4] bit 0	INT: mux IMUX_IO_O[1] bit 5	INT: buffer LV[4] ← LV_MUX[4]	INT: mux IMUX_IO_O[1] bit 6	-	INT: buffer LV[5] ← LV_MUX[5]	-	INT: mux LV_MUX[5] bit 0
B11	INT: mux IMUX_IO_ICE[2] bit 3	INT: mux IMUX_IO_ICE[2] bit 4	INT: mux IMUX_IO_ICE[2] bit 5	INT: mux IMUX_IO_ICE[3] bit 3	INT: mux IMUX_IO_ICE[3] bit 2	INT: mux IMUX_IO_ICE[0] bit 3	INT: mux IMUX_IO_ICE[0] bit 2	INT: mux IMUX_IO_ICE[1] bit 5	INT: mux IMUX_IO_ICE[1] bit 4	INT: mux IMUX_IO_ICE[1] bit 3	INT: mux IMUX_IO_OCE[2] bit 3	INT: mux IMUX_IO_OCE[2] bit 4	INT: mux IMUX_IO_OCE[2] bit 5	INT: mux IMUX_IO_OCE[3] bit 3	INT: mux IMUX_IO_OCE[0] bit 3	INT: mux IMUX_IO_OCE[0] bit 2	INT: mux IMUX_IO_TCE[3] bit 2	INT: mux IMUX_IO_OCE[1] bit 5	INT: mux IMUX_IO_OCE[1] bit 4	INT: mux IMUX_IO_OCE[1] bit 3	INT: mux IMUX_IO_TCE[2] bit 3	INT: mux IMUX_IO_TCE[2] bit 4	INT: mux IMUX_IO_TCE[2] bit 5	INT: mux IMUX_IO_TCE[3] bit 3	INT: mux IMUX_IO_TCE[1] bit 3	INT: mux IMUX_IO_TCE[0] bit 5	INT: mux IMUX_IO_TCE[0] bit 4	INT: mux IMUX_IO_TCE[0] bit 3	INT: mux IMUX_IO_SR[1] bit 0	INT: mux IMUX_IO_SR[1] bit 4	INT: mux IMUX_IO_SR[1] bit 5	INT: mux IMUX_IO_TCE[1] bit 2	INT: mux IMUX_IO_SR[0] bit 1	INT: mux IMUX_IO_SR[0] bit 0	INT: mux IMUX_IO_SR[3] bit 0	INT: mux IMUX_IO_SR[2] bit 5	INT: mux IMUX_IO_SR[2] bit 4	INT: mux IMUX_IO_SR[2] bit 0	INT: mux IMUX_IO_T[1] bit 0	INT: mux IMUX_IO_T[1] bit 4	INT: mux IMUX_IO_T[1] bit 5	INT: mux IMUX_IO_T[0] bit 1	INT: mux IMUX_IO_T[0] bit 0	INT: mux IMUX_IO_T[3] bit 1	INT: mux IMUX_IO_T[3] bit 0	INT: mux IMUX_IO_T[2] bit 5	INT: mux IMUX_IO_T[2] bit 4	INT: mux IMUX_IO_T[2] bit 0
B10	INT: mux IMUX_IO_ICE[2] bit 0	INT: mux IMUX_IO_ICE[3] bit 5	INT: mux IMUX_IO_ICE[3] bit 4	INT: mux IMUX_IO_ICE[3] bit 0	IOI[2]: !invert ICE	IOI[1]: !invert ICE	INT: mux IMUX_IO_ICE[0] bit 0	INT: mux IMUX_IO_ICE[0] bit 4	INT: mux IMUX_IO_ICE[0] bit 5	INT: mux IMUX_IO_ICE[1] bit 0	INT: mux IMUX_IO_OCE[2] bit 0	INT: mux IMUX_IO_OCE[3] bit 5	INT: mux IMUX_IO_OCE[3] bit 4	INT: mux IMUX_IO_OCE[3] bit 0	IOI[1]: !invert OCE	-	INT: mux IMUX_IO_OCE[0] bit 0	INT: mux IMUX_IO_OCE[0] bit 4	INT: mux IMUX_IO_OCE[0] bit 5	INT: mux IMUX_IO_TCE[2] bit 0	INT: mux IMUX_IO_TCE[3] bit 5	INT: mux IMUX_IO_TCE[3] bit 4	-	INT: mux IMUX_IO_TCE[3] bit 0	INT: mux IMUX_IO_TCE[1] bit 0	IOI[1]: !invert TCE	INT: mux IMUX_IO_TCE[1] bit 4	INT: mux IMUX_IO_TCE[1] bit 5	INT: mux IMUX_IO_TCE[0] bit 0	INT: mux IMUX_IO_SR[0] bit 5	INT: mux IMUX_IO_SR[0] bit 4	INT: mux IMUX_IO_SR[0] bit 3	-	IOI[1]: invert SR	INT: mux IMUX_IO_SR[3] bit 3	INT: mux IMUX_IO_SR[3] bit 4	INT: mux IMUX_IO_SR[3] bit 5	INT: mux IMUX_IO_SR[2] bit 3	INT: mux IMUX_IO_T[1] bit 3	INT: mux IMUX_IO_T[0] bit 5	INT: mux IMUX_IO_T[0] bit 4	INT: mux IMUX_IO_T[0] bit 3	IOI[1]: !invert T	IOI[2]: !invert T	INT: mux IMUX_IO_T[3] bit 3	INT: mux IMUX_IO_T[3] bit 4	INT: mux IMUX_IO_T[3] bit 5	INT: mux IMUX_IO_T[2] bit 3
B9	INT: mux IMUX_IO_ICE[2] bit 2	INT: mux IMUX_IO_ICE[2] bit 1	INT: mux IMUX_IO_ICE[3] bit 1	-	INT: mux IMUX_IO_ICE[1] bit 2	INT: mux IMUX_IO_ICE[1] bit 1	-	INT: mux IMUX_IO_ICE[0] bit 1	INT: mux IMUX_IO_OCE[3] bit 2	INT: mux IMUX_IO_OCE[2] bit 1	-	INT: mux IMUX_IO_OCE[2] bit 2	INT: mux IMUX_IO_OCE[3] bit 1	IOI[2]: !invert OCE	INT: mux IMUX_IO_OCE[0] bit 1	INT: mux IMUX_IO_OCE[1] bit 1	INT: mux IMUX_IO_OCE[1] bit 2	-	-	INT: mux IMUX_IO_OCE[1] bit 0	INT: mux IMUX_IO_TCE[3] bit 1	INT: mux IMUX_IO_TCE[2] bit 1	INT: mux IMUX_IO_TCE[2] bit 2	IOI[2]: !invert TCE	-	INT: mux IMUX_IO_TCE[0] bit 2	INT: mux IMUX_IO_TCE[0] bit 1	INT: mux IMUX_IO_TCE[1] bit 1	INT: mux IMUX_IO_SR[1] bit 3	-	-	INT: mux IMUX_IO_SR[1] bit 1	INT: mux IMUX_IO_SR[1] bit 2	INT: mux IMUX_IO_SR[0] bit 2	IOI[2]: invert SR	INT: mux IMUX_IO_SR[3] bit 2	INT: mux IMUX_IO_SR[2] bit 1	-	INT: mux IMUX_IO_SR[2] bit 2	INT: mux IMUX_IO_SR[3] bit 1	INT: mux IMUX_IO_T[0] bit 2	-	INT: mux IMUX_IO_T[1] bit 2	INT: mux IMUX_IO_T[1] bit 1	-	INT: mux IMUX_IO_T[3] bit 2	INT: mux IMUX_IO_T[2] bit 2	INT: mux IMUX_IO_T[2] bit 1
B8	INT: pass SINGLE_S[23] ← HEX_H0[3]	-	INT: pass SINGLE_S[22] ← HEX_H3[3]	INT: pass SINGLE_S[22] ← OUT_IO_IQ[1]	INT: pass SINGLE_S[21] ← OUT_IO_IQ[2]	INT: pass SINGLE_S[21] ← HEX_H6[3]	-	INT: pass SINGLE_S[20] ← HEX_H0[3]	-	INT: pass SINGLE_S[19] ← HEX_H3[3]	INT: pass SINGLE_S[18] ← OUT_IO_I[1]	INT: pass SINGLE_S[18] ← HEX_H6[3]	INT: pass SINGLE_S[17] ← HEX_H0[2]	INT: pass SINGLE_S[17] ← OUT_IO_I[2]	INT: pass SINGLE_S[16] ← HEX_H3[2]	-	-	INT: pass SINGLE_S[15] ← HEX_H6[2]	INT: pass SINGLE_S[14] ← OUT_IO_IQ[1]	INT: pass SINGLE_S[14] ← HEX_H0[2]	INT: pass SINGLE_S[13] ← OUT_IO_IQ[2]	INT: pass SINGLE_S[13] ← HEX_H3[2]	-	INT: pass SINGLE_S[12] ← HEX_H6[2]	INT: pass SINGLE_S[11] ← HEX_H0[1]	-	INT: pass SINGLE_S[10] ← HEX_H3[1]	INT: pass SINGLE_S[10] ← OUT_IO_I[1]	INT: pass SINGLE_S[9] ← OUT_IO_I[2]	INT: pass SINGLE_S[9] ← HEX_H6[1]	-	INT: pass SINGLE_S[8] ← HEX_H0[1]	-	INT: pass SINGLE_S[7] ← HEX_H3[1]	INT: pass SINGLE_S[6] ← OUT_IO_IQ[1]	INT: pass SINGLE_S[6] ← HEX_H6[1]	INT: pass SINGLE_S[5] ← HEX_H0[0]	INT: pass SINGLE_S[5] ← OUT_IO_IQ[2]	INT: pass SINGLE_S[4] ← HEX_H3[0]	-	-	INT: pass SINGLE_S[3] ← HEX_H6[0]	INT: pass SINGLE_S[2] ← OUT_IO_I[1]	INT: pass SINGLE_S[2] ← HEX_H0[0]	INT: pass SINGLE_S[1] ← OUT_IO_I[2]	INT: pass SINGLE_S[1] ← HEX_H3[0]	-	INT: pass SINGLE_S[0] ← HEX_H6[0]
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT: buffer HEX_H0[3] ← HEX_H0_MUX[3]	INT: mux HEX_H6_MUX[3] bit 5	INT: mux HEX_H6_MUX[3] bit 3	INT: mux HEX_H0_MUX[3] bit 2	INT: mux HEX_H0_MUX[3] bit 5	INT: mux HEX_H0_MUX[3] bit 6	INT: mux HEX_H0_MUX[3] bit 4	INT: mux HEX_H0_MUX[3] bit 0	INT: mux HEX_H0_MUX[3] bit 3	INT: mux HEX_H6_MUX[3] bit 1	INT: mux HEX_H6_MUX[3] bit 6	INT: buffer HEX_H6[3] ← HEX_H6_MUX[3]	INT: buffer HEX_H0[2] ← HEX_H0_MUX[2]	INT: mux HEX_H6_MUX[2] bit 5	INT: mux HEX_H6_MUX[2] bit 3	INT: mux HEX_H0_MUX[2] bit 2	INT: mux HEX_H0_MUX[2] bit 5	INT: mux HEX_H0_MUX[2] bit 6	INT: mux HEX_H0_MUX[2] bit 4	INT: mux HEX_H0_MUX[2] bit 0	INT: mux HEX_H0_MUX[2] bit 3	INT: mux HEX_H6_MUX[2] bit 1	INT: mux HEX_H6_MUX[2] bit 6	INT: buffer HEX_H6[2] ← HEX_H6_MUX[2]	INT: buffer HEX_H0[1] ← HEX_H0_MUX[1]	INT: mux HEX_H6_MUX[1] bit 5	INT: mux HEX_H6_MUX[1] bit 3	INT: mux HEX_H0_MUX[1] bit 2	INT: mux HEX_H0_MUX[1] bit 5	INT: mux HEX_H0_MUX[1] bit 6	INT: mux HEX_H0_MUX[1] bit 4	INT: mux HEX_H0_MUX[1] bit 0	INT: mux HEX_H0_MUX[1] bit 3	INT: mux HEX_H6_MUX[1] bit 1	INT: mux HEX_H6_MUX[1] bit 6	INT: buffer HEX_H6[1] ← HEX_H6_MUX[1]	INT: buffer HEX_H0[0] ← HEX_H0_MUX[0]	INT: mux HEX_H6_MUX[0] bit 5	INT: mux HEX_H6_MUX[0] bit 3	INT: mux HEX_H0_MUX[0] bit 2	INT: mux HEX_H0_MUX[0] bit 5	INT: mux HEX_H0_MUX[0] bit 6	INT: mux HEX_H0_MUX[0] bit 4	INT: mux HEX_H0_MUX[0] bit 0	INT: mux HEX_H0_MUX[0] bit 3	INT: mux HEX_H6_MUX[0] bit 1	INT: mux HEX_H6_MUX[0] bit 6	INT: buffer HEX_H6[0] ← HEX_H6_MUX[0]
B5	INT: mux HEX_H6_MUX[3] bit 0	INT: mux HEX_H0_MUX[3] bit 1	-	-	-	-	-	-	-	-	INT: mux HEX_H6_MUX[3] bit 4	INT: mux HEX_H6_MUX[3] bit 2	INT: mux HEX_H6_MUX[2] bit 0	INT: mux HEX_H0_MUX[2] bit 1	-	-	-	-	-	-	-	-	INT: mux HEX_H6_MUX[2] bit 4	INT: mux HEX_H6_MUX[2] bit 2	INT: mux HEX_H6_MUX[1] bit 0	INT: mux HEX_H0_MUX[1] bit 1	-	-	-	-	-	-	-	-	INT: mux HEX_H6_MUX[1] bit 4	INT: mux HEX_H6_MUX[1] bit 2	INT: mux HEX_H6_MUX[0] bit 0	INT: mux HEX_H0_MUX[0] bit 1	-	-	-	-	-	-	-	-	INT: mux HEX_H6_MUX[0] bit 4	INT: mux HEX_H6_MUX[0] bit 2
B4	INT: buffer HEX_V6[3] ← HEX_V6_MUX[3]	-	INT: mux HEX_V6_MUX[3] bit 1	INT: buffer HEX_V5[3] ← HEX_V5_MUX[3]	INT: buffer HEX_V4[3] ← HEX_V4_MUX[3]	-	-	INT: buffer HEX_V3[3] ← HEX_V3_MUX[3]	INT: buffer HEX_V2[3] ← HEX_V2_MUX[3]	-	-	INT: buffer HEX_V1[3] ← HEX_V1_MUX[3]	INT: buffer HEX_V1[2] ← HEX_V1_MUX[2]	-	-	INT: buffer HEX_V2[2] ← HEX_V2_MUX[2]	INT: buffer HEX_V3[2] ← HEX_V3_MUX[2]	-	-	INT: buffer HEX_V4[2] ← HEX_V4_MUX[2]	INT: buffer HEX_V5[2] ← HEX_V5_MUX[2]	INT: mux HEX_V6_MUX[2] bit 3	INT: mux HEX_V5_MUX[2] bit 1	INT: buffer HEX_V6[2] ← HEX_V6_MUX[2]	INT: buffer HEX_V6[1] ← HEX_V6_MUX[1]	-	INT: mux HEX_V6_MUX[1] bit 3	INT: buffer HEX_V5[1] ← HEX_V5_MUX[1]	INT: buffer HEX_V4[1] ← HEX_V4_MUX[1]	-	-	INT: buffer HEX_V3[1] ← HEX_V3_MUX[1]	INT: buffer HEX_V2[1] ← HEX_V2_MUX[1]	-	-	INT: buffer HEX_V1[1] ← HEX_V1_MUX[1]	INT: buffer HEX_V1[0] ← HEX_V1_MUX[0]	-	-	INT: buffer HEX_V2[0] ← HEX_V2_MUX[0]	INT: buffer HEX_V3[0] ← HEX_V3_MUX[0]	-	-	INT: buffer HEX_V4[0] ← HEX_V4_MUX[0]	INT: buffer HEX_V5[0] ← HEX_V5_MUX[0]	INT: mux HEX_V6_MUX[0] bit 2	INT: mux HEX_V5_MUX[0] bit 1	INT: buffer HEX_V6[0] ← HEX_V6_MUX[0]
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	INT: mux HEX_V6_MUX[3] bit 0	-	INT: mux HEX_V6_MUX[3] bit 4	INT: mux HEX_V5_MUX[3] bit 0	INT: mux HEX_V4_MUX[3] bit 1	INT: mux HEX_V3_MUX[3] bit 1	-	INT: mux HEX_V3_MUX[3] bit 0	INT: mux HEX_V2_MUX[3] bit 2	INT: mux HEX_V1_MUX[3] bit 2	-	INT: mux HEX_V1_MUX[3] bit 0	INT: mux HEX_V1_MUX[2] bit 0	INT: mux HEX_V1_MUX[2] bit 1	-	-	INT: mux HEX_V3_MUX[2] bit 0	INT: mux HEX_V3_MUX[2] bit 1	-	-	INT: mux HEX_V5_MUX[2] bit 0	-	INT: mux HEX_V6_MUX[2] bit 4	INT: mux HEX_V6_MUX[2] bit 0	INT: mux HEX_V6_MUX[1] bit 0	-	INT: mux HEX_V6_MUX[1] bit 4	INT: mux HEX_V5_MUX[1] bit 0	INT: mux HEX_V4_MUX[1] bit 1	INT: mux HEX_V3_MUX[1] bit 1	-	INT: mux HEX_V3_MUX[1] bit 0	INT: mux HEX_V2_MUX[1] bit 2	INT: mux HEX_V1_MUX[1] bit 2	-	INT: mux HEX_V1_MUX[1] bit 0	INT: mux HEX_V1_MUX[0] bit 0	INT: mux HEX_V1_MUX[0] bit 1	-	-	INT: mux HEX_V3_MUX[0] bit 0	INT: mux HEX_V3_MUX[0] bit 1	-	-	INT: mux HEX_V5_MUX[0] bit 0	-	INT: mux HEX_V6_MUX[0] bit 4	INT: mux HEX_V6_MUX[0] bit 0
B1	INT: mux HEX_S1[3] bit 0	INT: mux HEX_S1[3] bit 1	INT: mux HEX_S0[3] bit 1	INT: mux HEX_S0[3] bit 2	INT: mux HEX_S1[3] bit 2	INT: mux HEX_S1[3] bit 3	INT: mux HEX_S0[3] bit 3	-	-	-	-	INT: mux HEX_S0[3] bit 0	INT: mux HEX_S1[1] bit 0	INT: mux HEX_S1[1] bit 2	INT: mux HEX_S0[1] bit 2	INT: mux HEX_S0[1] bit 3	INT: mux HEX_S1[1] bit 3	INT: mux HEX_S1[1] bit 1	INT: mux HEX_S0[1] bit 1	INT: mux HEX_S0[1] bit 5	INT: mux HEX_S1[1] bit 5	INT: mux HEX_S1[1] bit 4	INT: mux HEX_S0[1] bit 4	INT: mux HEX_S0[1] bit 0	INT: mux HEX_S1[2] bit 0	INT: mux HEX_S1[2] bit 3	INT: mux HEX_S0[2] bit 3	INT: mux HEX_S0[2] bit 1	INT: mux HEX_S1[2] bit 1	INT: mux HEX_S1[2] bit 2	INT: mux HEX_S0[2] bit 2	INT: mux HEX_S0[2] bit 5	INT: mux HEX_S1[2] bit 5	INT: mux HEX_S1[2] bit 4	INT: mux HEX_S0[2] bit 4	INT: mux HEX_S0[2] bit 0	INT: mux HEX_S1[0] bit 0	INT: mux HEX_S1[0] bit 1	INT: mux HEX_S0[0] bit 1	INT: mux HEX_S0[0] bit 2	INT: mux HEX_S1[0] bit 2	INT: mux HEX_S1[0] bit 3	INT: mux HEX_S0[0] bit 3	-	-	-	-	INT: mux HEX_S0[0] bit 0
B0	INT: mux HEX_V6_MUX[3] bit 3	INT: mux HEX_V6_MUX[3] bit 2	INT: mux HEX_V5_MUX[3] bit 2	INT: mux HEX_V5_MUX[3] bit 1	INT: mux HEX_V4_MUX[3] bit 0	-	-	-	INT: mux HEX_V2_MUX[3] bit 0	INT: mux HEX_V1_MUX[3] bit 1	INT: mux HEX_V2_MUX[3] bit 1	-	INT: mux HEX_V2_MUX[2] bit 1	-	-	INT: mux HEX_V2_MUX[2] bit 0	INT: mux HEX_V4_MUX[2] bit 1	INT: mux HEX_V4_MUX[2] bit 2	INT: mux HEX_V3_MUX[2] bit 2	INT: mux HEX_V4_MUX[2] bit 0	-	-	INT: mux HEX_V6_MUX[2] bit 1	INT: mux HEX_V6_MUX[2] bit 2	INT: mux HEX_V6_MUX[1] bit 2	INT: mux HEX_V6_MUX[1] bit 1	INT: mux HEX_V5_MUX[1] bit 1	-	INT: mux HEX_V4_MUX[1] bit 0	-	-	-	INT: mux HEX_V2_MUX[1] bit 0	INT: mux HEX_V1_MUX[1] bit 1	INT: mux HEX_V2_MUX[1] bit 1	-	INT: mux HEX_V2_MUX[0] bit 1	-	-	INT: mux HEX_V2_MUX[0] bit 0	INT: mux HEX_V4_MUX[0] bit 1	INT: mux HEX_V4_MUX[0] bit 2	INT: mux HEX_V3_MUX[0] bit 2	INT: mux HEX_V4_MUX[0] bit 0	INT: mux HEX_V5_MUX[0] bit 2	-	INT: mux HEX_V6_MUX[0] bit 3	INT: mux HEX_V6_MUX[0] bit 1

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