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I/O Interface

TODO: document

Tile IOI

Cells: 1

Bels IOI

virtex2 IOI bel IOI pins
PinDirectionIOI[0]IOI[1]IOI[2]IOI[3]
ICLK1inIMUX_IOI_ICLK[1] invert by !MAIN[3][8]IMUX_IOI_ICLK[1] invert by !MAIN[3][28]IMUX_IOI_ICLK[3] invert by !MAIN[3][48]IMUX_IOI_ICLK[3] invert by !MAIN[3][68]
ICLK2inIMUX_IOI_ICLK[0] invert by !MAIN[3][0]IMUX_IOI_ICLK[0] invert by !MAIN[3][20]IMUX_IOI_ICLK[2] invert by !MAIN[3][40]IMUX_IOI_ICLK[2] invert by !MAIN[3][60]
ICEinIMUX_IOI_ICE[0] invert by !MAIN[3][6]IMUX_IOI_ICE[1] invert by !MAIN[3][26]IMUX_IOI_ICE[2] invert by !MAIN[3][46]IMUX_IOI_ICE[3] invert by !MAIN[3][66]
O1inIMUX_G0_DATA[7] invert by MAIN[3][11]IMUX_G1_DATA[7] invert by MAIN[3][31]IMUX_G2_DATA[7] invert by MAIN[3][51]IMUX_G3_DATA[7] invert by MAIN[3][71]
O2inIMUX_G0_DATA[6] invert by MAIN[3][13]IMUX_G1_DATA[6] invert by MAIN[3][33]IMUX_G2_DATA[6] invert by MAIN[3][53]IMUX_G3_DATA[6] invert by MAIN[3][73]
T1inIMUX_IOI_TS1[0] invert by MAIN[3][15]IMUX_IOI_TS1[1] invert by MAIN[3][35]IMUX_IOI_TS1[2] invert by MAIN[3][55]IMUX_IOI_TS1[3] invert by MAIN[3][75]
T2inIMUX_IOI_TS2[0] invert by MAIN[3][17]IMUX_IOI_TS2[1] invert by MAIN[3][37]IMUX_IOI_TS2[2] invert by MAIN[3][57]IMUX_IOI_TS2[3] invert by MAIN[3][77]
OTCLK1inIMUX_CLK_OPTINV[1] invert by !MAIN[3][19]IMUX_CLK_OPTINV[1] invert by !MAIN[3][39]IMUX_CLK_OPTINV[3] invert by !MAIN[3][59]IMUX_CLK_OPTINV[3] invert by !MAIN[3][79]
OTCLK2inIMUX_CLK_OPTINV[0] invert by !MAIN[3][9]IMUX_CLK_OPTINV[0] invert by !MAIN[3][29]IMUX_CLK_OPTINV[2] invert by !MAIN[3][49]IMUX_CLK_OPTINV[2] invert by !MAIN[3][69]
OCEinIMUX_CE_OPTINV[1]IMUX_CE_OPTINV[0]IMUX_CE_OPTINV[3]IMUX_CE_OPTINV[2]
TCEinIMUX_IOI_TCE[0] invert by !MAIN[3][4]IMUX_IOI_TCE[1] invert by !MAIN[3][24]IMUX_IOI_TCE[2] invert by !MAIN[3][44]IMUX_IOI_TCE[3] invert by !MAIN[3][64]
SRinIMUX_SR_OPTINV[2]IMUX_SR_OPTINV[0]IMUX_SR_OPTINV[1]IMUX_SR_OPTINV[3]
REVinIMUX_G0_DATA[5] invert by !MAIN[3][2]IMUX_G1_DATA[5] invert by !MAIN[3][22]IMUX_G2_DATA[5] invert by !MAIN[3][42]IMUX_G3_DATA[5] invert by !MAIN[3][62]
IoutOUT_FAN[0]OUT_FAN[1]OUT_FAN[2]OUT_FAN[3]
IQ1outOUT_SEC[20]OUT_SEC[21]OUT_SEC[22]OUT_SEC[23]
IQ2outOUT_SEC[15]OUT_SEC[9]OUT_SEC[18]OUT_SEC[10]
CLKPADoutOUT_CLKPAD[0]OUT_CLKPAD[1]OUT_CLKPAD[2]OUT_CLKPAD[3]
ToutOUT_SEC[17]OUT_SEC[12]OUT_SEC[13]OUT_SEC[14]
virtex2 IOI bel IOI attribute bits
AttributeIOI[0]IOI[1]IOI[2]IOI[3]
FFI1_INIT bit 0!MAIN[1][9]!MAIN[1][29]!MAIN[1][49]!MAIN[1][69]
FFI2_INIT bit 0!MAIN[1][13]!MAIN[1][33]!MAIN[1][53]!MAIN[1][73]
FFI1_SRVAL bit 0!MAIN[0][2]!MAIN[0][21]!MAIN[0][40]!MAIN[0][59]
FFI2_SRVAL bit 0!MAIN[0][20]!MAIN[0][39]!MAIN[0][58]!MAIN[0][77]
FFI_LATCHMAIN[0][16]MAIN[0][35]MAIN[0][54]MAIN[0][73]
FFI_SR_SYNCMAIN[0][13]MAIN[0][32]MAIN[0][52]MAIN[0][70]
FFI_SR_ENABLEMAIN[1][2]MAIN[1][21]MAIN[1][40]MAIN[1][59]
FFI_REV_ENABLEMAIN[1][3]MAIN[1][22]MAIN[1][41]MAIN[1][60]
I_DELAY_ENABLEMAIN[0][4]MAIN[0][24]MAIN[0][44]MAIN[0][64]
I_TSBYPASS_ENABLEMAIN[0][6]MAIN[0][26]MAIN[0][46]MAIN[0][66]
IQ_DELAY_ENABLEMAIN[0][11]MAIN[0][31]MAIN[0][51]MAIN[0][71]
IQ_TSBYPASS_ENABLEMAIN[0][9]MAIN[0][29]MAIN[0][49]MAIN[0][69]
READBACK_I bit 0MAIN[2][13]MAIN[2][33]MAIN[2][53]MAIN[2][73]
MUX_TSBYPASS[enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS]
FFO_INIT bit 0!MAIN[2][17]!MAIN[2][37]!MAIN[2][55]!MAIN[2][75]
FFO1_SRVAL bit 0!MAIN[3][1]!MAIN[3][21]!MAIN[3][41]!MAIN[3][61]
FFO2_SRVAL bit 0!MAIN[3][18]!MAIN[3][38]!MAIN[3][58]!MAIN[3][78]
FFO1_LATCHMAIN[3][7]MAIN[3][27]MAIN[3][47]MAIN[3][67]
FFO2_LATCHMAIN[3][14]MAIN[3][34]MAIN[3][54]MAIN[3][74]
FFO_SR_SYNCMAIN[0][10]MAIN[0][28]MAIN[0][48]MAIN[0][67]
FFO_SR_ENABLEMAIN[2][5]MAIN[2][24]MAIN[2][43]MAIN[2][62]
FFO_REV_ENABLEMAIN[2][4]MAIN[2][23]MAIN[2][42]MAIN[2][61]
MUX_O[enum: IOI_MUX_O][enum: IOI_MUX_O][enum: IOI_MUX_O][enum: IOI_MUX_O]
FFT_INIT bit 0!MAIN[1][17]!MAIN[1][37]!MAIN[1][55]!MAIN[1][75]
FFT1_SRVAL bit 0!MAIN[0][5]!MAIN[0][22]!MAIN[0][42]!MAIN[0][60]
FFT2_SRVAL bit 0!MAIN[0][19]!MAIN[0][38]!MAIN[0][57]!MAIN[0][76]
FFT1_LATCHMAIN[0][34]MAIN[0][18]MAIN[0][41]MAIN[0][62]
FFT2_LATCHMAIN[0][17]MAIN[0][37]MAIN[0][56]MAIN[0][75]
FFT_SR_SYNCMAIN[0][12]MAIN[0][30]MAIN[0][50]MAIN[0][68]
FFT_SR_ENABLEMAIN[1][5]MAIN[1][24]MAIN[1][43]MAIN[1][62]
FFT_REV_ENABLEMAIN[1][4]MAIN[1][23]MAIN[1][42]MAIN[1][61]
MUX_T[enum: IOI_MUX_T][enum: IOI_MUX_T][enum: IOI_MUX_T][enum: IOI_MUX_T]
virtex2 IOI enum IOI_MUX_TSBYPASS
IOI[0].MUX_TSBYPASSMAIN[0][3]
IOI[1].MUX_TSBYPASSMAIN[0][23]
IOI[2].MUX_TSBYPASSMAIN[0][43]
IOI[3].MUX_TSBYPASSMAIN[0][63]
GND1
T0
virtex2 IOI enum IOI_MUX_O
IOI[0].MUX_OMAIN[3][12]MAIN[3][3]MAIN[3][10]MAIN[3][5]
IOI[1].MUX_OMAIN[3][32]MAIN[3][23]MAIN[3][30]MAIN[3][25]
IOI[2].MUX_OMAIN[3][52]MAIN[3][43]MAIN[3][50]MAIN[3][45]
IOI[3].MUX_OMAIN[3][72]MAIN[3][63]MAIN[3][70]MAIN[3][65]
NONE0000
O10001
O20010
FFO10100
FFO21000
FFODDR1100
virtex2 IOI enum IOI_MUX_T
IOI[0].MUX_TMAIN[0][14]MAIN[0][8]MAIN[0][15]MAIN[0][7]
IOI[1].MUX_TMAIN[0][33]MAIN[0][27]MAIN[0][36]MAIN[0][25]
IOI[2].MUX_TMAIN[0][53]MAIN[0][47]MAIN[0][55]MAIN[0][45]
IOI[3].MUX_TMAIN[0][72]MAIN[0][65]MAIN[0][74]MAIN[0][61]
NONE0000
T10001
T20010
FFT10100
FFT21000
FFTDDR1100

Bel wires

virtex2 IOI bel wires
WirePins
OUT_CLKPAD[0]IOI[0].CLKPAD
OUT_CLKPAD[1]IOI[1].CLKPAD
OUT_CLKPAD[2]IOI[2].CLKPAD
OUT_CLKPAD[3]IOI[3].CLKPAD
IMUX_CLK_OPTINV[0]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_CLK_OPTINV[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_CLK_OPTINV[2]IOI[2].OTCLK2, IOI[3].OTCLK2
IMUX_CLK_OPTINV[3]IOI[2].OTCLK1, IOI[3].OTCLK1
IMUX_SR_OPTINV[0]IOI[1].SR
IMUX_SR_OPTINV[1]IOI[2].SR
IMUX_SR_OPTINV[2]IOI[0].SR
IMUX_SR_OPTINV[3]IOI[3].SR
IMUX_CE_OPTINV[0]IOI[1].OCE
IMUX_CE_OPTINV[1]IOI[0].OCE
IMUX_CE_OPTINV[2]IOI[3].OCE
IMUX_CE_OPTINV[3]IOI[2].OCE
IMUX_G0_DATA[5]IOI[0].REV
IMUX_G0_DATA[6]IOI[0].O2
IMUX_G0_DATA[7]IOI[0].O1
IMUX_G1_DATA[5]IOI[1].REV
IMUX_G1_DATA[6]IOI[1].O2
IMUX_G1_DATA[7]IOI[1].O1
IMUX_G2_DATA[5]IOI[2].REV
IMUX_G2_DATA[6]IOI[2].O2
IMUX_G2_DATA[7]IOI[2].O1
IMUX_G3_DATA[5]IOI[3].REV
IMUX_G3_DATA[6]IOI[3].O2
IMUX_G3_DATA[7]IOI[3].O1
IMUX_IOI_ICLK[0]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOI_ICLK[1]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOI_ICLK[2]IOI[2].ICLK2, IOI[3].ICLK2
IMUX_IOI_ICLK[3]IOI[2].ICLK1, IOI[3].ICLK1
IMUX_IOI_TS1[0]IOI[0].T1
IMUX_IOI_TS1[1]IOI[1].T1
IMUX_IOI_TS1[2]IOI[2].T1
IMUX_IOI_TS1[3]IOI[3].T1
IMUX_IOI_TS2[0]IOI[0].T2
IMUX_IOI_TS2[1]IOI[1].T2
IMUX_IOI_TS2[2]IOI[2].T2
IMUX_IOI_TS2[3]IOI[3].T2
IMUX_IOI_ICE[0]IOI[0].ICE
IMUX_IOI_ICE[1]IOI[1].ICE
IMUX_IOI_ICE[2]IOI[2].ICE
IMUX_IOI_ICE[3]IOI[3].ICE
IMUX_IOI_TCE[0]IOI[0].TCE
IMUX_IOI_TCE[1]IOI[1].TCE
IMUX_IOI_TCE[2]IOI[2].TCE
IMUX_IOI_TCE[3]IOI[3].TCE
OUT_FAN[0]IOI[0].I
OUT_FAN[1]IOI[1].I
OUT_FAN[2]IOI[2].I
OUT_FAN[3]IOI[3].I
OUT_SEC[9]IOI[1].IQ2
OUT_SEC[10]IOI[3].IQ2
OUT_SEC[12]IOI[1].T
OUT_SEC[13]IOI[2].T
OUT_SEC[14]IOI[3].T
OUT_SEC[15]IOI[0].IQ2
OUT_SEC[17]IOI[0].T
OUT_SEC[18]IOI[2].IQ2
OUT_SEC[20]IOI[0].IQ1
OUT_SEC[21]IOI[1].IQ1
OUT_SEC[22]IOI[2].IQ1
OUT_SEC[23]IOI[3].IQ1

Bitstream

virtex2 IOI rect MAIN
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B79 - - - - - - - - - - - - - - - - - - IOI[3]: !invert OTCLK1 - - -
B78 - - - - - - - - - - - - - - - - - - IOI[3]: ! FFO2_SRVAL bit 0 - - -
B77 - - - - - - - - - - - - - - - - - - IOI[3]: invert T2 - - IOI[3]: ! FFI2_SRVAL bit 0
B76 - - - - - - - - - - - - - - - - - - - - - IOI[3]: ! FFT2_SRVAL bit 0
B75 - - - - - - - - - - - - - - - - - - IOI[3]: invert T1 IOI[3]: ! FFO_INIT bit 0 IOI[3]: ! FFT_INIT bit 0 IOI[3]: FFT2_LATCH
B74 - - - - - - - - - - - - - - - - - - IOI[3]: FFO2_LATCH - - IOI[3]: MUX_T bit 1
B73 - - - - - - - - - - - - - - - - - - IOI[3]: invert O2 IOI[3]: READBACK_I bit 0 IOI[3]: ! FFI2_INIT bit 0 IOI[3]: FFI_LATCH
B72 - - - - - - - - - - - - - - - - - - IOI[3]: MUX_O bit 3 - - IOI[3]: MUX_T bit 3
B71 - - - - - - - - - - - - - - - - - - IOI[3]: invert O1 - - IOI[3]: IQ_DELAY_ENABLE
B70 - - - - - - - - - - - - - - - - - - IOI[3]: MUX_O bit 1 - - IOI[3]: FFI_SR_SYNC
B69 - - - - - - - - - - - - - - - - - - IOI[3]: !invert OTCLK2 - IOI[3]: ! FFI1_INIT bit 0 IOI[3]: IQ_TSBYPASS_ENABLE
B68 - - - - - - - - - - - - - - - - - - IOI[3]: !invert ICLK1 - - IOI[3]: FFT_SR_SYNC
B67 - - - - - - - - - - - - - - - - - - IOI[3]: FFO1_LATCH - - IOI[3]: FFO_SR_SYNC
B66 - - - - - - - - - - - - - - - - - - IOI[3]: !invert ICE - - IOI[3]: I_TSBYPASS_ENABLE
B65 - - - - - - - - - - - - - - - - - - IOI[3]: MUX_O bit 0 - - IOI[3]: MUX_T bit 2
B64 - - - - - - - - - - - - - - - - - - IOI[3]: !invert TCE - - IOI[3]: I_DELAY_ENABLE
B63 - - - - - - - - - - - - - - - - - - IOI[3]: MUX_O bit 2 - - IOI[3]: MUX_TSBYPASS bit 0
B62 - - - - - - - - - - - - - - - - - - IOI[3]: !invert REV IOI[3]: FFO_SR_ENABLE IOI[3]: FFT_SR_ENABLE IOI[3]: FFT1_LATCH
B61 - - - - - - - - - - - - - - - - - - IOI[3]: ! FFO1_SRVAL bit 0 IOI[3]: FFO_REV_ENABLE IOI[3]: FFT_REV_ENABLE IOI[3]: MUX_T bit 0
B60 - - - - - - - - - - - - - - - - - - IOI[3]: !invert ICLK2 - IOI[3]: FFI_REV_ENABLE IOI[3]: ! FFT1_SRVAL bit 0
B59 - - - - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK1 - IOI[3]: FFI_SR_ENABLE IOI[3]: ! FFI1_SRVAL bit 0
B58 - - - - - - - - - - - - - - - - - - IOI[2]: ! FFO2_SRVAL bit 0 - - IOI[2]: ! FFI2_SRVAL bit 0
B57 - - - - - - - - - - - - - - - - - - IOI[2]: invert T2 - - IOI[2]: ! FFT2_SRVAL bit 0
B56 - - - - - - - - - - - - - - - - - - - - - IOI[2]: FFT2_LATCH
B55 - - - - - - - - - - - - - - - - - - IOI[2]: invert T1 IOI[2]: ! FFO_INIT bit 0 IOI[2]: ! FFT_INIT bit 0 IOI[2]: MUX_T bit 1
B54 - - - - - - - - - - - - - - - - - - IOI[2]: FFO2_LATCH - - IOI[2]: FFI_LATCH
B53 - - - - - - - - - - - - - - - - - - IOI[2]: invert O2 IOI[2]: READBACK_I bit 0 IOI[2]: ! FFI2_INIT bit 0 IOI[2]: MUX_T bit 3
B52 - - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 3 - - IOI[2]: FFI_SR_SYNC
B51 - - - - - - - - - - - - - - - - - - IOI[2]: invert O1 - - IOI[2]: IQ_DELAY_ENABLE
B50 - - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 1 - - IOI[2]: FFT_SR_SYNC
B49 - - - - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK2 - IOI[2]: ! FFI1_INIT bit 0 IOI[2]: IQ_TSBYPASS_ENABLE
B48 - - - - - - - - - - - - - - - - - - IOI[2]: !invert ICLK1 - - IOI[2]: FFO_SR_SYNC
B47 - - - - - - - - - - - - - - - - - - IOI[2]: FFO1_LATCH - - IOI[2]: MUX_T bit 2
B46 - - - - - - - - - - - - - - - - - - IOI[2]: !invert ICE - - IOI[2]: I_TSBYPASS_ENABLE
B45 - - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 0 - - IOI[2]: MUX_T bit 0
B44 - - - - - - - - - - - - - - - - - - IOI[2]: !invert TCE - - IOI[2]: I_DELAY_ENABLE
B43 - - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 2 IOI[2]: FFO_SR_ENABLE IOI[2]: FFT_SR_ENABLE IOI[2]: MUX_TSBYPASS bit 0
B42 - - - - - - - - - - - - - - - - - - IOI[2]: !invert REV IOI[2]: FFO_REV_ENABLE IOI[2]: FFT_REV_ENABLE IOI[2]: ! FFT1_SRVAL bit 0
B41 - - - - - - - - - - - - - - - - - - IOI[2]: ! FFO1_SRVAL bit 0 - IOI[2]: FFI_REV_ENABLE IOI[2]: FFT1_LATCH
B40 - - - - - - - - - - - - - - - - - - IOI[2]: !invert ICLK2 - IOI[2]: FFI_SR_ENABLE IOI[2]: ! FFI1_SRVAL bit 0
B39 - - - - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK1 - - IOI[1]: ! FFI2_SRVAL bit 0
B38 - - - - - - - - - - - - - - - - - - IOI[1]: ! FFO2_SRVAL bit 0 - - IOI[1]: ! FFT2_SRVAL bit 0
B37 - - - - - - - - - - - - - - - - - - IOI[1]: invert T2 IOI[1]: ! FFO_INIT bit 0 IOI[1]: ! FFT_INIT bit 0 IOI[1]: FFT2_LATCH
B36 - - - - - - - - - - - - - - - - - - - - - IOI[1]: MUX_T bit 1
B35 - - - - - - - - - - - - - - - - - - IOI[1]: invert T1 - - IOI[1]: FFI_LATCH
B34 - - - - - - - - - - - - - - - - - - IOI[1]: FFO2_LATCH - - IOI[0]: FFT1_LATCH
B33 - - - - - - - - - - - - - - - - - - IOI[1]: invert O2 IOI[1]: READBACK_I bit 0 IOI[1]: ! FFI2_INIT bit 0 IOI[1]: MUX_T bit 3
B32 - - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 3 - - IOI[1]: FFI_SR_SYNC
B31 - - - - - - - - - - - - - - - - - - IOI[1]: invert O1 - - IOI[1]: IQ_DELAY_ENABLE
B30 - - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 1 - - IOI[1]: FFT_SR_SYNC
B29 - - - - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK2 - IOI[1]: ! FFI1_INIT bit 0 IOI[1]: IQ_TSBYPASS_ENABLE
B28 - - - - - - - - - - - - - - - - - - IOI[1]: !invert ICLK1 - - IOI[1]: FFO_SR_SYNC
B27 - - - - - - - - - - - - - - - - - - IOI[1]: FFO1_LATCH - - IOI[1]: MUX_T bit 2
B26 - - - - - - - - - - - - - - - - - - IOI[1]: !invert ICE - - IOI[1]: I_TSBYPASS_ENABLE
B25 - - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 0 - - IOI[1]: MUX_T bit 0
B24 - - - - - - - - - - - - - - - - - - IOI[1]: !invert TCE IOI[1]: FFO_SR_ENABLE IOI[1]: FFT_SR_ENABLE IOI[1]: I_DELAY_ENABLE
B23 - - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 2 IOI[1]: FFO_REV_ENABLE IOI[1]: FFT_REV_ENABLE IOI[1]: MUX_TSBYPASS bit 0
B22 - - - - - - - - - - - - - - - - - - IOI[1]: !invert REV - IOI[1]: FFI_REV_ENABLE IOI[1]: ! FFT1_SRVAL bit 0
B21 - - - - - - - - - - - - - - - - - - IOI[1]: ! FFO1_SRVAL bit 0 - IOI[1]: FFI_SR_ENABLE IOI[1]: ! FFI1_SRVAL bit 0
B20 - - - - - - - - - - - - - - - - - - IOI[1]: !invert ICLK2 - - IOI[0]: ! FFI2_SRVAL bit 0
B19 - - - - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK1 - - IOI[0]: ! FFT2_SRVAL bit 0
B18 - - - - - - - - - - - - - - - - - - IOI[0]: ! FFO2_SRVAL bit 0 - - IOI[1]: FFT1_LATCH
B17 - - - - - - - - - - - - - - - - - - IOI[0]: invert T2 IOI[0]: ! FFO_INIT bit 0 IOI[0]: ! FFT_INIT bit 0 IOI[0]: FFT2_LATCH
B16 - - - - - - - - - - - - - - - - - - - - - IOI[0]: FFI_LATCH
B15 - - - - - - - - - - - - - - - - - - IOI[0]: invert T1 - - IOI[0]: MUX_T bit 1
B14 - - - - - - - - - - - - - - - - - - IOI[0]: FFO2_LATCH - - IOI[0]: MUX_T bit 3
B13 - - - - - - - - - - - - - - - - - - IOI[0]: invert O2 IOI[0]: READBACK_I bit 0 IOI[0]: ! FFI2_INIT bit 0 IOI[0]: FFI_SR_SYNC
B12 - - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 3 - - IOI[0]: FFT_SR_SYNC
B11 - - - - - - - - - - - - - - - - - - IOI[0]: invert O1 - - IOI[0]: IQ_DELAY_ENABLE
B10 - - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 1 - - IOI[0]: FFO_SR_SYNC
B9 - - - - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK2 - IOI[0]: ! FFI1_INIT bit 0 IOI[0]: IQ_TSBYPASS_ENABLE
B8 - - - - - - - - - - - - - - - - - - IOI[0]: !invert ICLK1 - - IOI[0]: MUX_T bit 2
B7 - - - - - - - - - - - - - - - - - - IOI[0]: FFO1_LATCH - - IOI[0]: MUX_T bit 0
B6 - - - - - - - - - - - - - - - - - - IOI[0]: !invert ICE - - IOI[0]: I_TSBYPASS_ENABLE
B5 - - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 0 IOI[0]: FFO_SR_ENABLE IOI[0]: FFT_SR_ENABLE IOI[0]: ! FFT1_SRVAL bit 0
B4 - - - - - - - - - - - - - - - - - - IOI[0]: !invert TCE IOI[0]: FFO_REV_ENABLE IOI[0]: FFT_REV_ENABLE IOI[0]: I_DELAY_ENABLE
B3 - - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 2 - IOI[0]: FFI_REV_ENABLE IOI[0]: MUX_TSBYPASS bit 0
B2 - - - - - - - - - - - - - - - - - - IOI[0]: !invert REV - IOI[0]: FFI_SR_ENABLE IOI[0]: ! FFI1_SRVAL bit 0
B1 - - - - - - - - - - - - - - - - - - IOI[0]: ! FFO1_SRVAL bit 0 - - -
B0 - - - - - - - - - - - - - - - - - - IOI[0]: !invert ICLK2 - - -

Tile IOI_CLK_S

Cells: 1

Bels IOI

virtex2 IOI_CLK_S bel IOI pins
PinDirectionIOI[0]IOI[1]IOI[2]IOI[3]
ICLK1inIMUX_IOI_ICLK[1] invert by !MAIN[3][8]IMUX_IOI_ICLK[1] invert by !MAIN[3][28]--
ICLK2inIMUX_IOI_ICLK[0] invert by !MAIN[3][0]IMUX_IOI_ICLK[0] invert by !MAIN[3][20]--
ICEinIMUX_IOI_ICE[0] invert by !MAIN[3][6]IMUX_IOI_ICE[1] invert by !MAIN[3][26]--
O1inIMUX_G0_DATA[7] invert by MAIN[3][11]IMUX_G1_DATA[7] invert by MAIN[3][31]--
O2inIMUX_G0_DATA[6] invert by MAIN[3][13]IMUX_G1_DATA[6] invert by MAIN[3][33]--
T1inIMUX_IOI_TS1[0] invert by MAIN[3][15]IMUX_IOI_TS1[1] invert by MAIN[3][35]--
T2inIMUX_IOI_TS2[0] invert by MAIN[3][17]IMUX_IOI_TS2[1] invert by MAIN[3][37]--
OTCLK1inIMUX_CLK_OPTINV[1] invert by !MAIN[3][19]IMUX_CLK_OPTINV[1] invert by !MAIN[3][39]--
OTCLK2inIMUX_CLK_OPTINV[0] invert by !MAIN[3][9]IMUX_CLK_OPTINV[0] invert by !MAIN[3][29]--
OCEinIMUX_CE_OPTINV[1]IMUX_CE_OPTINV[0]--
TCEinIMUX_IOI_TCE[0] invert by !MAIN[3][4]IMUX_IOI_TCE[1] invert by !MAIN[3][24]--
SRinIMUX_SR_OPTINV[2]IMUX_SR_OPTINV[0]--
REVinIMUX_G0_DATA[5] invert by !MAIN[3][2]IMUX_G1_DATA[5] invert by !MAIN[3][22]--
IoutOUT_FAN[0]OUT_FAN[1]OUT_FAN[2]-
IQ1outOUT_SEC[20]OUT_SEC[21]--
IQ2outOUT_SEC[15]OUT_SEC[9]--
CLKPADoutOUT_CLKPAD[0]OUT_CLKPAD[1]--
ToutOUT_SEC[17]OUT_SEC[12]--
virtex2 IOI_CLK_S bel IOI attribute bits
AttributeIOI[0]IOI[1]IOI[2]IOI[3]
FFI1_INIT bit 0!MAIN[1][9]!MAIN[1][29]--
FFI2_INIT bit 0!MAIN[1][13]!MAIN[1][33]--
FFI1_SRVAL bit 0!MAIN[0][2]!MAIN[0][21]--
FFI2_SRVAL bit 0!MAIN[0][20]!MAIN[0][39]--
FFI_LATCHMAIN[0][16]MAIN[0][35]--
FFI_SR_SYNCMAIN[0][13]MAIN[0][32]--
FFI_SR_ENABLEMAIN[1][2]MAIN[1][21]--
FFI_REV_ENABLEMAIN[1][3]MAIN[1][22]--
I_DELAY_ENABLEMAIN[0][4]MAIN[0][24]--
I_TSBYPASS_ENABLEMAIN[0][6]MAIN[0][26]--
IQ_DELAY_ENABLEMAIN[0][11]MAIN[0][31]--
IQ_TSBYPASS_ENABLEMAIN[0][9]MAIN[0][29]--
READBACK_I bit 0MAIN[2][13]MAIN[2][33]--
MUX_TSBYPASS[enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS]--
FFO_INIT bit 0!MAIN[2][17]!MAIN[2][37]--
FFO1_SRVAL bit 0!MAIN[3][1]!MAIN[3][21]--
FFO2_SRVAL bit 0!MAIN[3][18]!MAIN[3][38]--
FFO1_LATCHMAIN[3][7]MAIN[3][27]--
FFO2_LATCHMAIN[3][14]MAIN[3][34]--
FFO_SR_SYNCMAIN[0][10]MAIN[0][28]--
FFO_SR_ENABLEMAIN[2][5]MAIN[2][24]--
FFO_REV_ENABLEMAIN[2][4]MAIN[2][23]--
MUX_O[enum: IOI_MUX_O][enum: IOI_MUX_O]--
FFT_INIT bit 0!MAIN[1][17]!MAIN[1][37]--
FFT1_SRVAL bit 0!MAIN[0][5]!MAIN[0][22]--
FFT2_SRVAL bit 0!MAIN[0][19]!MAIN[0][38]--
FFT1_LATCHMAIN[0][34]MAIN[0][18]--
FFT2_LATCHMAIN[0][17]MAIN[0][37]--
FFT_SR_SYNCMAIN[0][12]MAIN[0][30]--
FFT_SR_ENABLEMAIN[1][5]MAIN[1][24]--
FFT_REV_ENABLEMAIN[1][4]MAIN[1][23]--
MUX_T[enum: IOI_MUX_T][enum: IOI_MUX_T]--
virtex2 IOI_CLK_S enum IOI_MUX_TSBYPASS
IOI[0].MUX_TSBYPASSMAIN[0][3]
IOI[1].MUX_TSBYPASSMAIN[0][23]
GND1
T0
virtex2 IOI_CLK_S enum IOI_MUX_O
IOI[0].MUX_OMAIN[3][12]MAIN[3][3]MAIN[3][10]MAIN[3][5]
IOI[1].MUX_OMAIN[3][32]MAIN[3][23]MAIN[3][30]MAIN[3][25]
NONE0000
O10001
O20010
FFO10100
FFO21000
FFODDR1100
virtex2 IOI_CLK_S enum IOI_MUX_T
IOI[0].MUX_TMAIN[0][14]MAIN[0][8]MAIN[0][15]MAIN[0][7]
IOI[1].MUX_TMAIN[0][33]MAIN[0][27]MAIN[0][36]MAIN[0][25]
NONE0000
T10001
T20010
FFT10100
FFT21000
FFTDDR1100

Bel wires

virtex2 IOI_CLK_S bel wires
WirePins
OUT_CLKPAD[0]IOI[0].CLKPAD
OUT_CLKPAD[1]IOI[1].CLKPAD
IMUX_CLK_OPTINV[0]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_CLK_OPTINV[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_SR_OPTINV[0]IOI[1].SR
IMUX_SR_OPTINV[2]IOI[0].SR
IMUX_CE_OPTINV[0]IOI[1].OCE
IMUX_CE_OPTINV[1]IOI[0].OCE
IMUX_G0_DATA[5]IOI[0].REV
IMUX_G0_DATA[6]IOI[0].O2
IMUX_G0_DATA[7]IOI[0].O1
IMUX_G1_DATA[5]IOI[1].REV
IMUX_G1_DATA[6]IOI[1].O2
IMUX_G1_DATA[7]IOI[1].O1
IMUX_IOI_ICLK[0]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOI_ICLK[1]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOI_TS1[0]IOI[0].T1
IMUX_IOI_TS1[1]IOI[1].T1
IMUX_IOI_TS2[0]IOI[0].T2
IMUX_IOI_TS2[1]IOI[1].T2
IMUX_IOI_ICE[0]IOI[0].ICE
IMUX_IOI_ICE[1]IOI[1].ICE
IMUX_IOI_TCE[0]IOI[0].TCE
IMUX_IOI_TCE[1]IOI[1].TCE
OUT_FAN[0]IOI[0].I
OUT_FAN[1]IOI[1].I
OUT_FAN[2]IOI[2].I
OUT_SEC[9]IOI[1].IQ2
OUT_SEC[12]IOI[1].T
OUT_SEC[15]IOI[0].IQ2
OUT_SEC[17]IOI[0].T
OUT_SEC[20]IOI[0].IQ1
OUT_SEC[21]IOI[1].IQ1

Bitstream

virtex2 IOI_CLK_S rect MAIN
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B79 - - - - - - - - - - - - - - - - - - - - - -
B78 - - - - - - - - - - - - - - - - - - - - - -
B77 - - - - - - - - - - - - - - - - - - - - - -
B76 - - - - - - - - - - - - - - - - - - - - - -
B75 - - - - - - - - - - - - - - - - - - - - - -
B74 - - - - - - - - - - - - - - - - - - - - - -
B73 - - - - - - - - - - - - - - - - - - - - - -
B72 - - - - - - - - - - - - - - - - - - - - - -
B71 - - - - - - - - - - - - - - - - - - - - - -
B70 - - - - - - - - - - - - - - - - - - - - - -
B69 - - - - - - - - - - - - - - - - - - - - - -
B68 - - - - - - - - - - - - - - - - - - - - - -
B67 - - - - - - - - - - - - - - - - - - - - - -
B66 - - - - - - - - - - - - - - - - - - - - - -
B65 - - - - - - - - - - - - - - - - - - - - - -
B64 - - - - - - - - - - - - - - - - - - - - - -
B63 - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK1 - - IOI[1]: ! FFI2_SRVAL bit 0
B38 - - - - - - - - - - - - - - - - - - IOI[1]: ! FFO2_SRVAL bit 0 - - IOI[1]: ! FFT2_SRVAL bit 0
B37 - - - - - - - - - - - - - - - - - - IOI[1]: invert T2 IOI[1]: ! FFO_INIT bit 0 IOI[1]: ! FFT_INIT bit 0 IOI[1]: FFT2_LATCH
B36 - - - - - - - - - - - - - - - - - - - - - IOI[1]: MUX_T bit 1
B35 - - - - - - - - - - - - - - - - - - IOI[1]: invert T1 - - IOI[1]: FFI_LATCH
B34 - - - - - - - - - - - - - - - - - - IOI[1]: FFO2_LATCH - - IOI[0]: FFT1_LATCH
B33 - - - - - - - - - - - - - - - - - - IOI[1]: invert O2 IOI[1]: READBACK_I bit 0 IOI[1]: ! FFI2_INIT bit 0 IOI[1]: MUX_T bit 3
B32 - - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 3 - - IOI[1]: FFI_SR_SYNC
B31 - - - - - - - - - - - - - - - - - - IOI[1]: invert O1 - - IOI[1]: IQ_DELAY_ENABLE
B30 - - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 1 - - IOI[1]: FFT_SR_SYNC
B29 - - - - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK2 - IOI[1]: ! FFI1_INIT bit 0 IOI[1]: IQ_TSBYPASS_ENABLE
B28 - - - - - - - - - - - - - - - - - - IOI[1]: !invert ICLK1 - - IOI[1]: FFO_SR_SYNC
B27 - - - - - - - - - - - - - - - - - - IOI[1]: FFO1_LATCH - - IOI[1]: MUX_T bit 2
B26 - - - - - - - - - - - - - - - - - - IOI[1]: !invert ICE - - IOI[1]: I_TSBYPASS_ENABLE
B25 - - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 0 - - IOI[1]: MUX_T bit 0
B24 - - - - - - - - - - - - - - - - - - IOI[1]: !invert TCE IOI[1]: FFO_SR_ENABLE IOI[1]: FFT_SR_ENABLE IOI[1]: I_DELAY_ENABLE
B23 - - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 2 IOI[1]: FFO_REV_ENABLE IOI[1]: FFT_REV_ENABLE IOI[1]: MUX_TSBYPASS bit 0
B22 - - - - - - - - - - - - - - - - - - IOI[1]: !invert REV - IOI[1]: FFI_REV_ENABLE IOI[1]: ! FFT1_SRVAL bit 0
B21 - - - - - - - - - - - - - - - - - - IOI[1]: ! FFO1_SRVAL bit 0 - IOI[1]: FFI_SR_ENABLE IOI[1]: ! FFI1_SRVAL bit 0
B20 - - - - - - - - - - - - - - - - - - IOI[1]: !invert ICLK2 - - IOI[0]: ! FFI2_SRVAL bit 0
B19 - - - - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK1 - - IOI[0]: ! FFT2_SRVAL bit 0
B18 - - - - - - - - - - - - - - - - - - IOI[0]: ! FFO2_SRVAL bit 0 - - IOI[1]: FFT1_LATCH
B17 - - - - - - - - - - - - - - - - - - IOI[0]: invert T2 IOI[0]: ! FFO_INIT bit 0 IOI[0]: ! FFT_INIT bit 0 IOI[0]: FFT2_LATCH
B16 - - - - - - - - - - - - - - - - - - - - - IOI[0]: FFI_LATCH
B15 - - - - - - - - - - - - - - - - - - IOI[0]: invert T1 - - IOI[0]: MUX_T bit 1
B14 - - - - - - - - - - - - - - - - - - IOI[0]: FFO2_LATCH - - IOI[0]: MUX_T bit 3
B13 - - - - - - - - - - - - - - - - - - IOI[0]: invert O2 IOI[0]: READBACK_I bit 0 IOI[0]: ! FFI2_INIT bit 0 IOI[0]: FFI_SR_SYNC
B12 - - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 3 - - IOI[0]: FFT_SR_SYNC
B11 - - - - - - - - - - - - - - - - - - IOI[0]: invert O1 - - IOI[0]: IQ_DELAY_ENABLE
B10 - - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 1 - - IOI[0]: FFO_SR_SYNC
B9 - - - - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK2 - IOI[0]: ! FFI1_INIT bit 0 IOI[0]: IQ_TSBYPASS_ENABLE
B8 - - - - - - - - - - - - - - - - - - IOI[0]: !invert ICLK1 - - IOI[0]: MUX_T bit 2
B7 - - - - - - - - - - - - - - - - - - IOI[0]: FFO1_LATCH - - IOI[0]: MUX_T bit 0
B6 - - - - - - - - - - - - - - - - - - IOI[0]: !invert ICE - - IOI[0]: I_TSBYPASS_ENABLE
B5 - - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 0 IOI[0]: FFO_SR_ENABLE IOI[0]: FFT_SR_ENABLE IOI[0]: ! FFT1_SRVAL bit 0
B4 - - - - - - - - - - - - - - - - - - IOI[0]: !invert TCE IOI[0]: FFO_REV_ENABLE IOI[0]: FFT_REV_ENABLE IOI[0]: I_DELAY_ENABLE
B3 - - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 2 - IOI[0]: FFI_REV_ENABLE IOI[0]: MUX_TSBYPASS bit 0
B2 - - - - - - - - - - - - - - - - - - IOI[0]: !invert REV - IOI[0]: FFI_SR_ENABLE IOI[0]: ! FFI1_SRVAL bit 0
B1 - - - - - - - - - - - - - - - - - - IOI[0]: ! FFO1_SRVAL bit 0 - - -
B0 - - - - - - - - - - - - - - - - - - IOI[0]: !invert ICLK2 - - -

Tile IOI_CLK_N

Cells: 1

Bels IOI

virtex2 IOI_CLK_N bel IOI pins
PinDirectionIOI[0]IOI[1]IOI[2]IOI[3]
ICLK1in--IMUX_IOI_ICLK[3] invert by !MAIN[3][48]IMUX_IOI_ICLK[3] invert by !MAIN[3][68]
ICLK2in--IMUX_IOI_ICLK[2] invert by !MAIN[3][40]IMUX_IOI_ICLK[2] invert by !MAIN[3][60]
ICEin--IMUX_IOI_ICE[2] invert by !MAIN[3][46]IMUX_IOI_ICE[3] invert by !MAIN[3][66]
O1in--IMUX_G2_DATA[7] invert by MAIN[3][51]IMUX_G3_DATA[7] invert by MAIN[3][71]
O2in--IMUX_G2_DATA[6] invert by MAIN[3][53]IMUX_G3_DATA[6] invert by MAIN[3][73]
T1in--IMUX_IOI_TS1[2] invert by MAIN[3][55]IMUX_IOI_TS1[3] invert by MAIN[3][75]
T2in--IMUX_IOI_TS2[2] invert by MAIN[3][57]IMUX_IOI_TS2[3] invert by MAIN[3][77]
OTCLK1in--IMUX_CLK_OPTINV[3] invert by !MAIN[3][59]IMUX_CLK_OPTINV[3] invert by !MAIN[3][79]
OTCLK2in--IMUX_CLK_OPTINV[2] invert by !MAIN[3][49]IMUX_CLK_OPTINV[2] invert by !MAIN[3][69]
OCEin--IMUX_CE_OPTINV[3]IMUX_CE_OPTINV[2]
TCEin--IMUX_IOI_TCE[2] invert by !MAIN[3][44]IMUX_IOI_TCE[3] invert by !MAIN[3][64]
SRin--IMUX_SR_OPTINV[1]IMUX_SR_OPTINV[3]
REVin--IMUX_G2_DATA[5] invert by !MAIN[3][42]IMUX_G3_DATA[5] invert by !MAIN[3][62]
IoutOUT_FAN[0]-OUT_FAN[2]OUT_FAN[3]
IQ1out--OUT_SEC[22]OUT_SEC[23]
IQ2out--OUT_SEC[18]OUT_SEC[10]
CLKPADout--OUT_CLKPAD[2]OUT_CLKPAD[3]
Tout--OUT_SEC[13]OUT_SEC[14]
virtex2 IOI_CLK_N bel IOI attribute bits
AttributeIOI[0]IOI[1]IOI[2]IOI[3]
FFI1_INIT bit 0--!MAIN[1][49]!MAIN[1][69]
FFI2_INIT bit 0--!MAIN[1][53]!MAIN[1][73]
FFI1_SRVAL bit 0--!MAIN[0][40]!MAIN[0][59]
FFI2_SRVAL bit 0--!MAIN[0][58]!MAIN[0][77]
FFI_LATCH--MAIN[0][54]MAIN[0][73]
FFI_SR_SYNC--MAIN[0][52]MAIN[0][70]
FFI_SR_ENABLE--MAIN[1][40]MAIN[1][59]
FFI_REV_ENABLE--MAIN[1][41]MAIN[1][60]
I_DELAY_ENABLE--MAIN[0][44]MAIN[0][64]
I_TSBYPASS_ENABLE--MAIN[0][46]MAIN[0][66]
IQ_DELAY_ENABLE--MAIN[0][51]MAIN[0][71]
IQ_TSBYPASS_ENABLE--MAIN[0][49]MAIN[0][69]
READBACK_I bit 0--MAIN[2][53]MAIN[2][73]
MUX_TSBYPASS--[enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS]
FFO_INIT bit 0--!MAIN[2][55]!MAIN[2][75]
FFO1_SRVAL bit 0--!MAIN[3][41]!MAIN[3][61]
FFO2_SRVAL bit 0--!MAIN[3][58]!MAIN[3][78]
FFO1_LATCH--MAIN[3][47]MAIN[3][67]
FFO2_LATCH--MAIN[3][54]MAIN[3][74]
FFO_SR_SYNC--MAIN[0][48]MAIN[0][67]
FFO_SR_ENABLE--MAIN[2][43]MAIN[2][62]
FFO_REV_ENABLE--MAIN[2][42]MAIN[2][61]
MUX_O--[enum: IOI_MUX_O][enum: IOI_MUX_O]
FFT_INIT bit 0--!MAIN[1][55]!MAIN[1][75]
FFT1_SRVAL bit 0--!MAIN[0][42]!MAIN[0][60]
FFT2_SRVAL bit 0--!MAIN[0][57]!MAIN[0][76]
FFT1_LATCH--MAIN[0][41]MAIN[0][62]
FFT2_LATCH--MAIN[0][56]MAIN[0][75]
FFT_SR_SYNC--MAIN[0][50]MAIN[0][68]
FFT_SR_ENABLE--MAIN[1][43]MAIN[1][62]
FFT_REV_ENABLE--MAIN[1][42]MAIN[1][61]
MUX_T--[enum: IOI_MUX_T][enum: IOI_MUX_T]
virtex2 IOI_CLK_N enum IOI_MUX_TSBYPASS
IOI[2].MUX_TSBYPASSMAIN[0][43]
IOI[3].MUX_TSBYPASSMAIN[0][63]
GND1
T0
virtex2 IOI_CLK_N enum IOI_MUX_O
IOI[2].MUX_OMAIN[3][52]MAIN[3][43]MAIN[3][50]MAIN[3][45]
IOI[3].MUX_OMAIN[3][72]MAIN[3][63]MAIN[3][70]MAIN[3][65]
NONE0000
O10001
O20010
FFO10100
FFO21000
FFODDR1100
virtex2 IOI_CLK_N enum IOI_MUX_T
IOI[2].MUX_TMAIN[0][53]MAIN[0][47]MAIN[0][55]MAIN[0][45]
IOI[3].MUX_TMAIN[0][72]MAIN[0][65]MAIN[0][74]MAIN[0][61]
NONE0000
T10001
T20010
FFT10100
FFT21000
FFTDDR1100

Bel wires

virtex2 IOI_CLK_N bel wires
WirePins
OUT_CLKPAD[2]IOI[2].CLKPAD
OUT_CLKPAD[3]IOI[3].CLKPAD
IMUX_CLK_OPTINV[2]IOI[2].OTCLK2, IOI[3].OTCLK2
IMUX_CLK_OPTINV[3]IOI[2].OTCLK1, IOI[3].OTCLK1
IMUX_SR_OPTINV[1]IOI[2].SR
IMUX_SR_OPTINV[3]IOI[3].SR
IMUX_CE_OPTINV[2]IOI[3].OCE
IMUX_CE_OPTINV[3]IOI[2].OCE
IMUX_G2_DATA[5]IOI[2].REV
IMUX_G2_DATA[6]IOI[2].O2
IMUX_G2_DATA[7]IOI[2].O1
IMUX_G3_DATA[5]IOI[3].REV
IMUX_G3_DATA[6]IOI[3].O2
IMUX_G3_DATA[7]IOI[3].O1
IMUX_IOI_ICLK[2]IOI[2].ICLK2, IOI[3].ICLK2
IMUX_IOI_ICLK[3]IOI[2].ICLK1, IOI[3].ICLK1
IMUX_IOI_TS1[2]IOI[2].T1
IMUX_IOI_TS1[3]IOI[3].T1
IMUX_IOI_TS2[2]IOI[2].T2
IMUX_IOI_TS2[3]IOI[3].T2
IMUX_IOI_ICE[2]IOI[2].ICE
IMUX_IOI_ICE[3]IOI[3].ICE
IMUX_IOI_TCE[2]IOI[2].TCE
IMUX_IOI_TCE[3]IOI[3].TCE
OUT_FAN[0]IOI[0].I
OUT_FAN[2]IOI[2].I
OUT_FAN[3]IOI[3].I
OUT_SEC[10]IOI[3].IQ2
OUT_SEC[13]IOI[2].T
OUT_SEC[14]IOI[3].T
OUT_SEC[18]IOI[2].IQ2
OUT_SEC[22]IOI[2].IQ1
OUT_SEC[23]IOI[3].IQ1

Bitstream

virtex2 IOI_CLK_N rect MAIN
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B79 - - - - - - - - - - - - - - - - - - IOI[3]: !invert OTCLK1 - - -
B78 - - - - - - - - - - - - - - - - - - IOI[3]: ! FFO2_SRVAL bit 0 - - -
B77 - - - - - - - - - - - - - - - - - - IOI[3]: invert T2 - - IOI[3]: ! FFI2_SRVAL bit 0
B76 - - - - - - - - - - - - - - - - - - - - - IOI[3]: ! FFT2_SRVAL bit 0
B75 - - - - - - - - - - - - - - - - - - IOI[3]: invert T1 IOI[3]: ! FFO_INIT bit 0 IOI[3]: ! FFT_INIT bit 0 IOI[3]: FFT2_LATCH
B74 - - - - - - - - - - - - - - - - - - IOI[3]: FFO2_LATCH - - IOI[3]: MUX_T bit 1
B73 - - - - - - - - - - - - - - - - - - IOI[3]: invert O2 IOI[3]: READBACK_I bit 0 IOI[3]: ! FFI2_INIT bit 0 IOI[3]: FFI_LATCH
B72 - - - - - - - - - - - - - - - - - - IOI[3]: MUX_O bit 3 - - IOI[3]: MUX_T bit 3
B71 - - - - - - - - - - - - - - - - - - IOI[3]: invert O1 - - IOI[3]: IQ_DELAY_ENABLE
B70 - - - - - - - - - - - - - - - - - - IOI[3]: MUX_O bit 1 - - IOI[3]: FFI_SR_SYNC
B69 - - - - - - - - - - - - - - - - - - IOI[3]: !invert OTCLK2 - IOI[3]: ! FFI1_INIT bit 0 IOI[3]: IQ_TSBYPASS_ENABLE
B68 - - - - - - - - - - - - - - - - - - IOI[3]: !invert ICLK1 - - IOI[3]: FFT_SR_SYNC
B67 - - - - - - - - - - - - - - - - - - IOI[3]: FFO1_LATCH - - IOI[3]: FFO_SR_SYNC
B66 - - - - - - - - - - - - - - - - - - IOI[3]: !invert ICE - - IOI[3]: I_TSBYPASS_ENABLE
B65 - - - - - - - - - - - - - - - - - - IOI[3]: MUX_O bit 0 - - IOI[3]: MUX_T bit 2
B64 - - - - - - - - - - - - - - - - - - IOI[3]: !invert TCE - - IOI[3]: I_DELAY_ENABLE
B63 - - - - - - - - - - - - - - - - - - IOI[3]: MUX_O bit 2 - - IOI[3]: MUX_TSBYPASS bit 0
B62 - - - - - - - - - - - - - - - - - - IOI[3]: !invert REV IOI[3]: FFO_SR_ENABLE IOI[3]: FFT_SR_ENABLE IOI[3]: FFT1_LATCH
B61 - - - - - - - - - - - - - - - - - - IOI[3]: ! FFO1_SRVAL bit 0 IOI[3]: FFO_REV_ENABLE IOI[3]: FFT_REV_ENABLE IOI[3]: MUX_T bit 0
B60 - - - - - - - - - - - - - - - - - - IOI[3]: !invert ICLK2 - IOI[3]: FFI_REV_ENABLE IOI[3]: ! FFT1_SRVAL bit 0
B59 - - - - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK1 - IOI[3]: FFI_SR_ENABLE IOI[3]: ! FFI1_SRVAL bit 0
B58 - - - - - - - - - - - - - - - - - - IOI[2]: ! FFO2_SRVAL bit 0 - - IOI[2]: ! FFI2_SRVAL bit 0
B57 - - - - - - - - - - - - - - - - - - IOI[2]: invert T2 - - IOI[2]: ! FFT2_SRVAL bit 0
B56 - - - - - - - - - - - - - - - - - - - - - IOI[2]: FFT2_LATCH
B55 - - - - - - - - - - - - - - - - - - IOI[2]: invert T1 IOI[2]: ! FFO_INIT bit 0 IOI[2]: ! FFT_INIT bit 0 IOI[2]: MUX_T bit 1
B54 - - - - - - - - - - - - - - - - - - IOI[2]: FFO2_LATCH - - IOI[2]: FFI_LATCH
B53 - - - - - - - - - - - - - - - - - - IOI[2]: invert O2 IOI[2]: READBACK_I bit 0 IOI[2]: ! FFI2_INIT bit 0 IOI[2]: MUX_T bit 3
B52 - - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 3 - - IOI[2]: FFI_SR_SYNC
B51 - - - - - - - - - - - - - - - - - - IOI[2]: invert O1 - - IOI[2]: IQ_DELAY_ENABLE
B50 - - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 1 - - IOI[2]: FFT_SR_SYNC
B49 - - - - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK2 - IOI[2]: ! FFI1_INIT bit 0 IOI[2]: IQ_TSBYPASS_ENABLE
B48 - - - - - - - - - - - - - - - - - - IOI[2]: !invert ICLK1 - - IOI[2]: FFO_SR_SYNC
B47 - - - - - - - - - - - - - - - - - - IOI[2]: FFO1_LATCH - - IOI[2]: MUX_T bit 2
B46 - - - - - - - - - - - - - - - - - - IOI[2]: !invert ICE - - IOI[2]: I_TSBYPASS_ENABLE
B45 - - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 0 - - IOI[2]: MUX_T bit 0
B44 - - - - - - - - - - - - - - - - - - IOI[2]: !invert TCE - - IOI[2]: I_DELAY_ENABLE
B43 - - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 2 IOI[2]: FFO_SR_ENABLE IOI[2]: FFT_SR_ENABLE IOI[2]: MUX_TSBYPASS bit 0
B42 - - - - - - - - - - - - - - - - - - IOI[2]: !invert REV IOI[2]: FFO_REV_ENABLE IOI[2]: FFT_REV_ENABLE IOI[2]: ! FFT1_SRVAL bit 0
B41 - - - - - - - - - - - - - - - - - - IOI[2]: ! FFO1_SRVAL bit 0 - IOI[2]: FFI_REV_ENABLE IOI[2]: FFT1_LATCH
B40 - - - - - - - - - - - - - - - - - - IOI[2]: !invert ICLK2 - IOI[2]: FFI_SR_ENABLE IOI[2]: ! FFI1_SRVAL bit 0
B39 - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -