I/O Interface

TODO: document

IOI

virtex2 IOI bittile 0
BitFrame
0 1 2 3
79 - - - ~IO3:INV.OTCLK1
78 - - - ~IO3:OFF2_SRVAL
77 ~IO3:IFF2_SRVAL - - IO3:INV.T2
76 ~IO3:TFF2_SRVAL - - -
75 IO3:TFF2_LATCH ~IO3:TFF_INIT ~IO3:OFF_INIT IO3:INV.T1
74 IO3:TMUX[1] - - IO3:OFF2_LATCH
73 IO3:IFF_LATCH ~IO3:IFF2_INIT IO3:READBACK_I IO3:INV.O2
72 IO3:TMUX[3] - - IO3:OMUX[3]
71 IO3:IFF_DELAY_ENABLE - - IO3:INV.O1
70 IO3:IFF_SR_SYNC - - IO3:OMUX[1]
69 IO3:IFF_TSBYPASS_ENABLE ~IO3:IFF1_INIT - ~IO3:INV.OTCLK2
68 IO3:TFF_SR_SYNC - - ~IO3:INV.ICLK1
67 IO3:OFF_SR_SYNC - - IO3:OFF1_LATCH
66 IO3:I_TSBYPASS_ENABLE - - ~IO3:INV.ICE
65 IO3:TMUX[2] - - IO3:OMUX[0]
64 IO3:I_DELAY_ENABLE - - ~IO3:INV.TCE
63 IO3:TSBYPASS_MUX[0] - - IO3:OMUX[2]
62 IO3:TFF1_LATCH IO3:TFF_SR_ENABLE IO3:OFF_SR_ENABLE ~IO3:INV.REV
61 IO3:TMUX[0] IO3:TFF_REV_ENABLE IO3:OFF_REV_ENABLE ~IO3:OFF1_SRVAL
60 ~IO3:TFF1_SRVAL IO3:IFF_REV_ENABLE - ~IO3:INV.ICLK2
59 ~IO3:IFF1_SRVAL IO3:IFF_SR_ENABLE - ~IO2:INV.OTCLK1
58 ~IO2:IFF2_SRVAL - - ~IO2:OFF2_SRVAL
57 ~IO2:TFF2_SRVAL - - IO2:INV.T2
56 IO2:TFF2_LATCH - - -
55 IO2:TMUX[1] ~IO2:TFF_INIT ~IO2:OFF_INIT IO2:INV.T1
54 IO2:IFF_LATCH - - IO2:OFF2_LATCH
53 IO2:TMUX[3] ~IO2:IFF2_INIT IO2:READBACK_I IO2:INV.O2
52 IO2:IFF_SR_SYNC - - IO2:OMUX[3]
51 IO2:IFF_DELAY_ENABLE - - IO2:INV.O1
50 IO2:TFF_SR_SYNC - - IO2:OMUX[1]
49 IO2:IFF_TSBYPASS_ENABLE ~IO2:IFF1_INIT - ~IO2:INV.OTCLK2
48 IO2:OFF_SR_SYNC - - ~IO2:INV.ICLK1
47 IO2:TMUX[2] - - IO2:OFF1_LATCH
46 IO2:I_TSBYPASS_ENABLE - - ~IO2:INV.ICE
45 IO2:TMUX[0] - - IO2:OMUX[0]
44 IO2:I_DELAY_ENABLE - - ~IO2:INV.TCE
43 IO2:TSBYPASS_MUX[0] IO2:TFF_SR_ENABLE IO2:OFF_SR_ENABLE IO2:OMUX[2]
42 ~IO2:TFF1_SRVAL IO2:TFF_REV_ENABLE IO2:OFF_REV_ENABLE ~IO2:INV.REV
41 IO2:TFF1_LATCH IO2:IFF_REV_ENABLE - ~IO2:OFF1_SRVAL
40 ~IO2:IFF1_SRVAL IO2:IFF_SR_ENABLE - ~IO2:INV.ICLK2
39 ~IO1:IFF2_SRVAL - - ~IO1:INV.OTCLK1
38 ~IO1:TFF2_SRVAL - - ~IO1:OFF2_SRVAL
37 IO1:TFF2_LATCH ~IO1:TFF_INIT ~IO1:OFF_INIT IO1:INV.T2
36 IO1:TMUX[1] - - -
35 IO1:IFF_LATCH - - IO1:INV.T1
34 IO0:TFF1_LATCH - - IO1:OFF2_LATCH
33 IO1:TMUX[3] ~IO1:IFF2_INIT IO1:READBACK_I IO1:INV.O2
32 IO1:IFF_SR_SYNC - - IO1:OMUX[3]
31 IO1:IFF_DELAY_ENABLE - - IO1:INV.O1
30 IO1:TFF_SR_SYNC - - IO1:OMUX[1]
29 IO1:IFF_TSBYPASS_ENABLE ~IO1:IFF1_INIT - ~IO1:INV.OTCLK2
28 IO1:OFF_SR_SYNC - - ~IO1:INV.ICLK1
27 IO1:TMUX[2] - - IO1:OFF1_LATCH
26 IO1:I_TSBYPASS_ENABLE - - ~IO1:INV.ICE
25 IO1:TMUX[0] - - IO1:OMUX[0]
24 IO1:I_DELAY_ENABLE IO1:TFF_SR_ENABLE IO1:OFF_SR_ENABLE ~IO1:INV.TCE
23 IO1:TSBYPASS_MUX[0] IO1:TFF_REV_ENABLE IO1:OFF_REV_ENABLE IO1:OMUX[2]
22 ~IO1:TFF1_SRVAL IO1:IFF_REV_ENABLE - ~IO1:INV.REV
21 ~IO1:IFF1_SRVAL IO1:IFF_SR_ENABLE - ~IO1:OFF1_SRVAL
20 ~IO0:IFF2_SRVAL - - ~IO1:INV.ICLK2
19 ~IO0:TFF2_SRVAL - - ~IO0:INV.OTCLK1
18 IO1:TFF1_LATCH - - ~IO0:OFF2_SRVAL
17 IO0:TFF2_LATCH ~IO0:TFF_INIT ~IO0:OFF_INIT IO0:INV.T2
16 IO0:IFF_LATCH - - -
15 IO0:TMUX[1] - - IO0:INV.T1
14 IO0:TMUX[3] - - IO0:OFF2_LATCH
13 IO0:IFF_SR_SYNC ~IO0:IFF2_INIT IO0:READBACK_I IO0:INV.O2
12 IO0:TFF_SR_SYNC - - IO0:OMUX[3]
11 IO0:IFF_DELAY_ENABLE - - IO0:INV.O1
10 IO0:OFF_SR_SYNC - - IO0:OMUX[1]
9 IO0:IFF_TSBYPASS_ENABLE ~IO0:IFF1_INIT - ~IO0:INV.OTCLK2
8 IO0:TMUX[2] - - ~IO0:INV.ICLK1
7 IO0:TMUX[0] - - IO0:OFF1_LATCH
6 IO0:I_TSBYPASS_ENABLE - - ~IO0:INV.ICE
5 ~IO0:TFF1_SRVAL IO0:TFF_SR_ENABLE IO0:OFF_SR_ENABLE IO0:OMUX[0]
4 IO0:I_DELAY_ENABLE IO0:TFF_REV_ENABLE IO0:OFF_REV_ENABLE ~IO0:INV.TCE
3 IO0:TSBYPASS_MUX[0] IO0:IFF_REV_ENABLE - IO0:OMUX[2]
2 ~IO0:IFF1_SRVAL IO0:IFF_SR_ENABLE - ~IO0:INV.REV
1 - - - ~IO0:OFF1_SRVAL
0 - - - ~IO0:INV.ICLK2
IO0:IFF1_INIT 0.1.9
IO0:IFF1_SRVAL 0.0.2
IO0:IFF2_INIT 0.1.13
IO0:IFF2_SRVAL 0.0.20
IO0:INV.ICE 0.3.6
IO0:INV.ICLK1 0.3.8
IO0:INV.ICLK2 0.3.0
IO0:INV.OTCLK1 0.3.19
IO0:INV.OTCLK2 0.3.9
IO0:INV.REV 0.3.2
IO0:INV.TCE 0.3.4
IO0:OFF1_SRVAL 0.3.1
IO0:OFF2_SRVAL 0.3.18
IO0:OFF_INIT 0.2.17
IO0:TFF1_SRVAL 0.0.5
IO0:TFF2_SRVAL 0.0.19
IO0:TFF_INIT 0.1.17
IO1:IFF1_INIT 0.1.29
IO1:IFF1_SRVAL 0.0.21
IO1:IFF2_INIT 0.1.33
IO1:IFF2_SRVAL 0.0.39
IO1:INV.ICE 0.3.26
IO1:INV.ICLK1 0.3.28
IO1:INV.ICLK2 0.3.20
IO1:INV.OTCLK1 0.3.39
IO1:INV.OTCLK2 0.3.29
IO1:INV.REV 0.3.22
IO1:INV.TCE 0.3.24
IO1:OFF1_SRVAL 0.3.21
IO1:OFF2_SRVAL 0.3.38
IO1:OFF_INIT 0.2.37
IO1:TFF1_SRVAL 0.0.22
IO1:TFF2_SRVAL 0.0.38
IO1:TFF_INIT 0.1.37
IO2:IFF1_INIT 0.1.49
IO2:IFF1_SRVAL 0.0.40
IO2:IFF2_INIT 0.1.53
IO2:IFF2_SRVAL 0.0.58
IO2:INV.ICE 0.3.46
IO2:INV.ICLK1 0.3.48
IO2:INV.ICLK2 0.3.40
IO2:INV.OTCLK1 0.3.59
IO2:INV.OTCLK2 0.3.49
IO2:INV.REV 0.3.42
IO2:INV.TCE 0.3.44
IO2:OFF1_SRVAL 0.3.41
IO2:OFF2_SRVAL 0.3.58
IO2:OFF_INIT 0.2.55
IO2:TFF1_SRVAL 0.0.42
IO2:TFF2_SRVAL 0.0.57
IO2:TFF_INIT 0.1.55
IO3:IFF1_INIT 0.1.69
IO3:IFF1_SRVAL 0.0.59
IO3:IFF2_INIT 0.1.73
IO3:IFF2_SRVAL 0.0.77
IO3:INV.ICE 0.3.66
IO3:INV.ICLK1 0.3.68
IO3:INV.ICLK2 0.3.60
IO3:INV.OTCLK1 0.3.79
IO3:INV.OTCLK2 0.3.69
IO3:INV.REV 0.3.62
IO3:INV.TCE 0.3.64
IO3:OFF1_SRVAL 0.3.61
IO3:OFF2_SRVAL 0.3.78
IO3:OFF_INIT 0.2.75
IO3:TFF1_SRVAL 0.0.60
IO3:TFF2_SRVAL 0.0.76
IO3:TFF_INIT 0.1.75
inverted ~[0]
IO0:IFF_DELAY_ENABLE 0.0.11
IO0:IFF_LATCH 0.0.16
IO0:IFF_REV_ENABLE 0.1.3
IO0:IFF_SR_ENABLE 0.1.2
IO0:IFF_SR_SYNC 0.0.13
IO0:IFF_TSBYPASS_ENABLE 0.0.9
IO0:INV.O1 0.3.11
IO0:INV.O2 0.3.13
IO0:INV.T1 0.3.15
IO0:INV.T2 0.3.17
IO0:I_DELAY_ENABLE 0.0.4
IO0:I_TSBYPASS_ENABLE 0.0.6
IO0:OFF1_LATCH 0.3.7
IO0:OFF2_LATCH 0.3.14
IO0:OFF_REV_ENABLE 0.2.4
IO0:OFF_SR_ENABLE 0.2.5
IO0:OFF_SR_SYNC 0.0.10
IO0:READBACK_I 0.2.13
IO0:TFF1_LATCH 0.0.34
IO0:TFF2_LATCH 0.0.17
IO0:TFF_REV_ENABLE 0.1.4
IO0:TFF_SR_ENABLE 0.1.5
IO0:TFF_SR_SYNC 0.0.12
IO1:IFF_DELAY_ENABLE 0.0.31
IO1:IFF_LATCH 0.0.35
IO1:IFF_REV_ENABLE 0.1.22
IO1:IFF_SR_ENABLE 0.1.21
IO1:IFF_SR_SYNC 0.0.32
IO1:IFF_TSBYPASS_ENABLE 0.0.29
IO1:INV.O1 0.3.31
IO1:INV.O2 0.3.33
IO1:INV.T1 0.3.35
IO1:INV.T2 0.3.37
IO1:I_DELAY_ENABLE 0.0.24
IO1:I_TSBYPASS_ENABLE 0.0.26
IO1:OFF1_LATCH 0.3.27
IO1:OFF2_LATCH 0.3.34
IO1:OFF_REV_ENABLE 0.2.23
IO1:OFF_SR_ENABLE 0.2.24
IO1:OFF_SR_SYNC 0.0.28
IO1:READBACK_I 0.2.33
IO1:TFF1_LATCH 0.0.18
IO1:TFF2_LATCH 0.0.37
IO1:TFF_REV_ENABLE 0.1.23
IO1:TFF_SR_ENABLE 0.1.24
IO1:TFF_SR_SYNC 0.0.30
IO2:IFF_DELAY_ENABLE 0.0.51
IO2:IFF_LATCH 0.0.54
IO2:IFF_REV_ENABLE 0.1.41
IO2:IFF_SR_ENABLE 0.1.40
IO2:IFF_SR_SYNC 0.0.52
IO2:IFF_TSBYPASS_ENABLE 0.0.49
IO2:INV.O1 0.3.51
IO2:INV.O2 0.3.53
IO2:INV.T1 0.3.55
IO2:INV.T2 0.3.57
IO2:I_DELAY_ENABLE 0.0.44
IO2:I_TSBYPASS_ENABLE 0.0.46
IO2:OFF1_LATCH 0.3.47
IO2:OFF2_LATCH 0.3.54
IO2:OFF_REV_ENABLE 0.2.42
IO2:OFF_SR_ENABLE 0.2.43
IO2:OFF_SR_SYNC 0.0.48
IO2:READBACK_I 0.2.53
IO2:TFF1_LATCH 0.0.41
IO2:TFF2_LATCH 0.0.56
IO2:TFF_REV_ENABLE 0.1.42
IO2:TFF_SR_ENABLE 0.1.43
IO2:TFF_SR_SYNC 0.0.50
IO3:IFF_DELAY_ENABLE 0.0.71
IO3:IFF_LATCH 0.0.73
IO3:IFF_REV_ENABLE 0.1.60
IO3:IFF_SR_ENABLE 0.1.59
IO3:IFF_SR_SYNC 0.0.70
IO3:IFF_TSBYPASS_ENABLE 0.0.69
IO3:INV.O1 0.3.71
IO3:INV.O2 0.3.73
IO3:INV.T1 0.3.75
IO3:INV.T2 0.3.77
IO3:I_DELAY_ENABLE 0.0.64
IO3:I_TSBYPASS_ENABLE 0.0.66
IO3:OFF1_LATCH 0.3.67
IO3:OFF2_LATCH 0.3.74
IO3:OFF_REV_ENABLE 0.2.61
IO3:OFF_SR_ENABLE 0.2.62
IO3:OFF_SR_SYNC 0.0.67
IO3:READBACK_I 0.2.73
IO3:TFF1_LATCH 0.0.62
IO3:TFF2_LATCH 0.0.75
IO3:TFF_REV_ENABLE 0.1.61
IO3:TFF_SR_ENABLE 0.1.62
IO3:TFF_SR_SYNC 0.0.68
non-inverted [0]
IO0:OMUX 0.3.12 0.3.3 0.3.10 0.3.5
IO1:OMUX 0.3.32 0.3.23 0.3.30 0.3.25
IO2:OMUX 0.3.52 0.3.43 0.3.50 0.3.45
IO3:OMUX 0.3.72 0.3.63 0.3.70 0.3.65
NONE 0 0 0 0
O1 0 0 0 1
O2 0 0 1 0
OFF1 0 1 0 0
OFF2 1 0 0 0
OFFDDR 1 1 0 0
IO0:TMUX 0.0.14 0.0.8 0.0.15 0.0.7
IO1:TMUX 0.0.33 0.0.27 0.0.36 0.0.25
IO2:TMUX 0.0.53 0.0.47 0.0.55 0.0.45
IO3:TMUX 0.0.72 0.0.65 0.0.74 0.0.61
NONE 0 0 0 0
T1 0 0 0 1
T2 0 0 1 0
TFF1 0 1 0 0
TFF2 1 0 0 0
TFFDDR 1 1 0 0
IO0:TSBYPASS_MUX 0.0.3
IO1:TSBYPASS_MUX 0.0.23
IO2:TSBYPASS_MUX 0.0.43
IO3:TSBYPASS_MUX 0.0.63
TMUX 0
GND 1

IOI.CLK_B

virtex2 IOI.CLK_B bittile 0
BitFrame
0 1 2 3
39 ~IO1:IFF2_SRVAL - - ~IO1:INV.OTCLK1
38 ~IO1:TFF2_SRVAL - - ~IO1:OFF2_SRVAL
37 IO1:TFF2_LATCH ~IO1:TFF_INIT ~IO1:OFF_INIT IO1:INV.T2
36 IO1:TMUX[1] - - -
35 IO1:IFF_LATCH - - IO1:INV.T1
34 IO0:TFF1_LATCH - - IO1:OFF2_LATCH
33 IO1:TMUX[3] ~IO1:IFF2_INIT IO1:READBACK_I IO1:INV.O2
32 IO1:IFF_SR_SYNC - - IO1:OMUX[3]
31 IO1:IFF_DELAY_ENABLE - - IO1:INV.O1
30 IO1:TFF_SR_SYNC - - IO1:OMUX[1]
29 IO1:IFF_TSBYPASS_ENABLE ~IO1:IFF1_INIT - ~IO1:INV.OTCLK2
28 IO1:OFF_SR_SYNC - - ~IO1:INV.ICLK1
27 IO1:TMUX[2] - - IO1:OFF1_LATCH
26 IO1:I_TSBYPASS_ENABLE - - ~IO1:INV.ICE
25 IO1:TMUX[0] - - IO1:OMUX[0]
24 IO1:I_DELAY_ENABLE IO1:TFF_SR_ENABLE IO1:OFF_SR_ENABLE ~IO1:INV.TCE
23 IO1:TSBYPASS_MUX[0] IO1:TFF_REV_ENABLE IO1:OFF_REV_ENABLE IO1:OMUX[2]
22 ~IO1:TFF1_SRVAL IO1:IFF_REV_ENABLE - ~IO1:INV.REV
21 ~IO1:IFF1_SRVAL IO1:IFF_SR_ENABLE - ~IO1:OFF1_SRVAL
20 ~IO0:IFF2_SRVAL - - ~IO1:INV.ICLK2
19 ~IO0:TFF2_SRVAL - - ~IO0:INV.OTCLK1
18 IO1:TFF1_LATCH - - ~IO0:OFF2_SRVAL
17 IO0:TFF2_LATCH ~IO0:TFF_INIT ~IO0:OFF_INIT IO0:INV.T2
16 IO0:IFF_LATCH - - -
15 IO0:TMUX[1] - - IO0:INV.T1
14 IO0:TMUX[3] - - IO0:OFF2_LATCH
13 IO0:IFF_SR_SYNC ~IO0:IFF2_INIT IO0:READBACK_I IO0:INV.O2
12 IO0:TFF_SR_SYNC - - IO0:OMUX[3]
11 IO0:IFF_DELAY_ENABLE - - IO0:INV.O1
10 IO0:OFF_SR_SYNC - - IO0:OMUX[1]
9 IO0:IFF_TSBYPASS_ENABLE ~IO0:IFF1_INIT - ~IO0:INV.OTCLK2
8 IO0:TMUX[2] - - ~IO0:INV.ICLK1
7 IO0:TMUX[0] - - IO0:OFF1_LATCH
6 IO0:I_TSBYPASS_ENABLE - - ~IO0:INV.ICE
5 ~IO0:TFF1_SRVAL IO0:TFF_SR_ENABLE IO0:OFF_SR_ENABLE IO0:OMUX[0]
4 IO0:I_DELAY_ENABLE IO0:TFF_REV_ENABLE IO0:OFF_REV_ENABLE ~IO0:INV.TCE
3 IO0:TSBYPASS_MUX[0] IO0:IFF_REV_ENABLE - IO0:OMUX[2]
2 ~IO0:IFF1_SRVAL IO0:IFF_SR_ENABLE - ~IO0:INV.REV
1 - - - ~IO0:OFF1_SRVAL
0 - - - ~IO0:INV.ICLK2
IO0:IFF1_INIT 0.1.9
IO0:IFF1_SRVAL 0.0.2
IO0:IFF2_INIT 0.1.13
IO0:IFF2_SRVAL 0.0.20
IO0:INV.ICE 0.3.6
IO0:INV.ICLK1 0.3.8
IO0:INV.ICLK2 0.3.0
IO0:INV.OTCLK1 0.3.19
IO0:INV.OTCLK2 0.3.9
IO0:INV.REV 0.3.2
IO0:INV.TCE 0.3.4
IO0:OFF1_SRVAL 0.3.1
IO0:OFF2_SRVAL 0.3.18
IO0:OFF_INIT 0.2.17
IO0:TFF1_SRVAL 0.0.5
IO0:TFF2_SRVAL 0.0.19
IO0:TFF_INIT 0.1.17
IO1:IFF1_INIT 0.1.29
IO1:IFF1_SRVAL 0.0.21
IO1:IFF2_INIT 0.1.33
IO1:IFF2_SRVAL 0.0.39
IO1:INV.ICE 0.3.26
IO1:INV.ICLK1 0.3.28
IO1:INV.ICLK2 0.3.20
IO1:INV.OTCLK1 0.3.39
IO1:INV.OTCLK2 0.3.29
IO1:INV.REV 0.3.22
IO1:INV.TCE 0.3.24
IO1:OFF1_SRVAL 0.3.21
IO1:OFF2_SRVAL 0.3.38
IO1:OFF_INIT 0.2.37
IO1:TFF1_SRVAL 0.0.22
IO1:TFF2_SRVAL 0.0.38
IO1:TFF_INIT 0.1.37
inverted ~[0]
IO0:IFF_DELAY_ENABLE 0.0.11
IO0:IFF_LATCH 0.0.16
IO0:IFF_REV_ENABLE 0.1.3
IO0:IFF_SR_ENABLE 0.1.2
IO0:IFF_SR_SYNC 0.0.13
IO0:IFF_TSBYPASS_ENABLE 0.0.9
IO0:INV.O1 0.3.11
IO0:INV.O2 0.3.13
IO0:INV.T1 0.3.15
IO0:INV.T2 0.3.17
IO0:I_DELAY_ENABLE 0.0.4
IO0:I_TSBYPASS_ENABLE 0.0.6
IO0:OFF1_LATCH 0.3.7
IO0:OFF2_LATCH 0.3.14
IO0:OFF_REV_ENABLE 0.2.4
IO0:OFF_SR_ENABLE 0.2.5
IO0:OFF_SR_SYNC 0.0.10
IO0:READBACK_I 0.2.13
IO0:TFF1_LATCH 0.0.34
IO0:TFF2_LATCH 0.0.17
IO0:TFF_REV_ENABLE 0.1.4
IO0:TFF_SR_ENABLE 0.1.5
IO0:TFF_SR_SYNC 0.0.12
IO1:IFF_DELAY_ENABLE 0.0.31
IO1:IFF_LATCH 0.0.35
IO1:IFF_REV_ENABLE 0.1.22
IO1:IFF_SR_ENABLE 0.1.21
IO1:IFF_SR_SYNC 0.0.32
IO1:IFF_TSBYPASS_ENABLE 0.0.29
IO1:INV.O1 0.3.31
IO1:INV.O2 0.3.33
IO1:INV.T1 0.3.35
IO1:INV.T2 0.3.37
IO1:I_DELAY_ENABLE 0.0.24
IO1:I_TSBYPASS_ENABLE 0.0.26
IO1:OFF1_LATCH 0.3.27
IO1:OFF2_LATCH 0.3.34
IO1:OFF_REV_ENABLE 0.2.23
IO1:OFF_SR_ENABLE 0.2.24
IO1:OFF_SR_SYNC 0.0.28
IO1:READBACK_I 0.2.33
IO1:TFF1_LATCH 0.0.18
IO1:TFF2_LATCH 0.0.37
IO1:TFF_REV_ENABLE 0.1.23
IO1:TFF_SR_ENABLE 0.1.24
IO1:TFF_SR_SYNC 0.0.30
non-inverted [0]
IO0:OMUX 0.3.12 0.3.3 0.3.10 0.3.5
IO1:OMUX 0.3.32 0.3.23 0.3.30 0.3.25
NONE 0 0 0 0
O1 0 0 0 1
O2 0 0 1 0
OFF1 0 1 0 0
OFF2 1 0 0 0
OFFDDR 1 1 0 0
IO0:TMUX 0.0.14 0.0.8 0.0.15 0.0.7
IO1:TMUX 0.0.33 0.0.27 0.0.36 0.0.25
NONE 0 0 0 0
T1 0 0 0 1
T2 0 0 1 0
TFF1 0 1 0 0
TFF2 1 0 0 0
TFFDDR 1 1 0 0
IO0:TSBYPASS_MUX 0.0.3
IO1:TSBYPASS_MUX 0.0.23
TMUX 0
GND 1

IOI.CLK_T

virtex2 IOI.CLK_T bittile 0
BitFrame
0 1 2 3
79 - - - ~IO3:INV.OTCLK1
78 - - - ~IO3:OFF2_SRVAL
77 ~IO3:IFF2_SRVAL - - IO3:INV.T2
76 ~IO3:TFF2_SRVAL - - -
75 IO3:TFF2_LATCH ~IO3:TFF_INIT ~IO3:OFF_INIT IO3:INV.T1
74 IO3:TMUX[1] - - IO3:OFF2_LATCH
73 IO3:IFF_LATCH ~IO3:IFF2_INIT IO3:READBACK_I IO3:INV.O2
72 IO3:TMUX[3] - - IO3:OMUX[3]
71 IO3:IFF_DELAY_ENABLE - - IO3:INV.O1
70 IO3:IFF_SR_SYNC - - IO3:OMUX[1]
69 IO3:IFF_TSBYPASS_ENABLE ~IO3:IFF1_INIT - ~IO3:INV.OTCLK2
68 IO3:TFF_SR_SYNC - - ~IO3:INV.ICLK1
67 IO3:OFF_SR_SYNC - - IO3:OFF1_LATCH
66 IO3:I_TSBYPASS_ENABLE - - ~IO3:INV.ICE
65 IO3:TMUX[2] - - IO3:OMUX[0]
64 IO3:I_DELAY_ENABLE - - ~IO3:INV.TCE
63 IO3:TSBYPASS_MUX[0] - - IO3:OMUX[2]
62 IO3:TFF1_LATCH IO3:TFF_SR_ENABLE IO3:OFF_SR_ENABLE ~IO3:INV.REV
61 IO3:TMUX[0] IO3:TFF_REV_ENABLE IO3:OFF_REV_ENABLE ~IO3:OFF1_SRVAL
60 ~IO3:TFF1_SRVAL IO3:IFF_REV_ENABLE - ~IO3:INV.ICLK2
59 ~IO3:IFF1_SRVAL IO3:IFF_SR_ENABLE - ~IO2:INV.OTCLK1
58 ~IO2:IFF2_SRVAL - - ~IO2:OFF2_SRVAL
57 ~IO2:TFF2_SRVAL - - IO2:INV.T2
56 IO2:TFF2_LATCH - - -
55 IO2:TMUX[1] ~IO2:TFF_INIT ~IO2:OFF_INIT IO2:INV.T1
54 IO2:IFF_LATCH - - IO2:OFF2_LATCH
53 IO2:TMUX[3] ~IO2:IFF2_INIT IO2:READBACK_I IO2:INV.O2
52 IO2:IFF_SR_SYNC - - IO2:OMUX[3]
51 IO2:IFF_DELAY_ENABLE - - IO2:INV.O1
50 IO2:TFF_SR_SYNC - - IO2:OMUX[1]
49 IO2:IFF_TSBYPASS_ENABLE ~IO2:IFF1_INIT - ~IO2:INV.OTCLK2
48 IO2:OFF_SR_SYNC - - ~IO2:INV.ICLK1
47 IO2:TMUX[2] - - IO2:OFF1_LATCH
46 IO2:I_TSBYPASS_ENABLE - - ~IO2:INV.ICE
45 IO2:TMUX[0] - - IO2:OMUX[0]
44 IO2:I_DELAY_ENABLE - - ~IO2:INV.TCE
43 IO2:TSBYPASS_MUX[0] IO2:TFF_SR_ENABLE IO2:OFF_SR_ENABLE IO2:OMUX[2]
42 ~IO2:TFF1_SRVAL IO2:TFF_REV_ENABLE IO2:OFF_REV_ENABLE ~IO2:INV.REV
41 IO2:TFF1_LATCH IO2:IFF_REV_ENABLE - ~IO2:OFF1_SRVAL
40 ~IO2:IFF1_SRVAL IO2:IFF_SR_ENABLE - ~IO2:INV.ICLK2
39 - - - -
38 - - - -
37 - - - -
36 - - - -
35 - - - -
34 - - - -
33 - - - -
32 - - - -
31 - - - -
30 - - - -
29 - - - -
28 - - - -
27 - - - -
26 - - - -
25 - - - -
24 - - - -
23 - - - -
22 - - - -
21 - - - -
20 - - - -
19 - - - -
18 - - - -
17 - - - -
16 - - - -
15 - - - -
14 - - - -
13 - - - -
12 - - - -
11 - - - -
10 - - - -
9 - - - -
8 - - - -
7 - - - -
6 - - - -
5 - - - -
4 - - - -
3 - - - -
2 - - - -
1 - - - -
0 - - - -
IO2:IFF1_INIT 0.1.49
IO2:IFF1_SRVAL 0.0.40
IO2:IFF2_INIT 0.1.53
IO2:IFF2_SRVAL 0.0.58
IO2:INV.ICE 0.3.46
IO2:INV.ICLK1 0.3.48
IO2:INV.ICLK2 0.3.40
IO2:INV.OTCLK1 0.3.59
IO2:INV.OTCLK2 0.3.49
IO2:INV.REV 0.3.42
IO2:INV.TCE 0.3.44
IO2:OFF1_SRVAL 0.3.41
IO2:OFF2_SRVAL 0.3.58
IO2:OFF_INIT 0.2.55
IO2:TFF1_SRVAL 0.0.42
IO2:TFF2_SRVAL 0.0.57
IO2:TFF_INIT 0.1.55
IO3:IFF1_INIT 0.1.69
IO3:IFF1_SRVAL 0.0.59
IO3:IFF2_INIT 0.1.73
IO3:IFF2_SRVAL 0.0.77
IO3:INV.ICE 0.3.66
IO3:INV.ICLK1 0.3.68
IO3:INV.ICLK2 0.3.60
IO3:INV.OTCLK1 0.3.79
IO3:INV.OTCLK2 0.3.69
IO3:INV.REV 0.3.62
IO3:INV.TCE 0.3.64
IO3:OFF1_SRVAL 0.3.61
IO3:OFF2_SRVAL 0.3.78
IO3:OFF_INIT 0.2.75
IO3:TFF1_SRVAL 0.0.60
IO3:TFF2_SRVAL 0.0.76
IO3:TFF_INIT 0.1.75
inverted ~[0]
IO2:IFF_DELAY_ENABLE 0.0.51
IO2:IFF_LATCH 0.0.54
IO2:IFF_REV_ENABLE 0.1.41
IO2:IFF_SR_ENABLE 0.1.40
IO2:IFF_SR_SYNC 0.0.52
IO2:IFF_TSBYPASS_ENABLE 0.0.49
IO2:INV.O1 0.3.51
IO2:INV.O2 0.3.53
IO2:INV.T1 0.3.55
IO2:INV.T2 0.3.57
IO2:I_DELAY_ENABLE 0.0.44
IO2:I_TSBYPASS_ENABLE 0.0.46
IO2:OFF1_LATCH 0.3.47
IO2:OFF2_LATCH 0.3.54
IO2:OFF_REV_ENABLE 0.2.42
IO2:OFF_SR_ENABLE 0.2.43
IO2:OFF_SR_SYNC 0.0.48
IO2:READBACK_I 0.2.53
IO2:TFF1_LATCH 0.0.41
IO2:TFF2_LATCH 0.0.56
IO2:TFF_REV_ENABLE 0.1.42
IO2:TFF_SR_ENABLE 0.1.43
IO2:TFF_SR_SYNC 0.0.50
IO3:IFF_DELAY_ENABLE 0.0.71
IO3:IFF_LATCH 0.0.73
IO3:IFF_REV_ENABLE 0.1.60
IO3:IFF_SR_ENABLE 0.1.59
IO3:IFF_SR_SYNC 0.0.70
IO3:IFF_TSBYPASS_ENABLE 0.0.69
IO3:INV.O1 0.3.71
IO3:INV.O2 0.3.73
IO3:INV.T1 0.3.75
IO3:INV.T2 0.3.77
IO3:I_DELAY_ENABLE 0.0.64
IO3:I_TSBYPASS_ENABLE 0.0.66
IO3:OFF1_LATCH 0.3.67
IO3:OFF2_LATCH 0.3.74
IO3:OFF_REV_ENABLE 0.2.61
IO3:OFF_SR_ENABLE 0.2.62
IO3:OFF_SR_SYNC 0.0.67
IO3:READBACK_I 0.2.73
IO3:TFF1_LATCH 0.0.62
IO3:TFF2_LATCH 0.0.75
IO3:TFF_REV_ENABLE 0.1.61
IO3:TFF_SR_ENABLE 0.1.62
IO3:TFF_SR_SYNC 0.0.68
non-inverted [0]
IO2:OMUX 0.3.52 0.3.43 0.3.50 0.3.45
IO3:OMUX 0.3.72 0.3.63 0.3.70 0.3.65
NONE 0 0 0 0
O1 0 0 0 1
O2 0 0 1 0
OFF1 0 1 0 0
OFF2 1 0 0 0
OFFDDR 1 1 0 0
IO2:TMUX 0.0.53 0.0.47 0.0.55 0.0.45
IO3:TMUX 0.0.72 0.0.65 0.0.74 0.0.61
NONE 0 0 0 0
T1 0 0 0 1
T2 0 0 1 0
TFF1 0 1 0 0
TFF2 1 0 0 0
TFFDDR 1 1 0 0
IO2:TSBYPASS_MUX 0.0.43
IO3:TSBYPASS_MUX 0.0.63
TMUX 0
GND 1