Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Clock I/O and CMT buffers

Tile HCLK_IOI

Cells: 4

Bel IOCLK

virtex5 HCLK_IOI bel IOCLK
PinDirectionWires

Bel RCLK

virtex5 HCLK_IOI bel RCLK
PinDirectionWires
CKINT0inputCELL0.IMUX.IMUX6
CKINT1inputCELL3.IMUX.IMUX0

Bel BUFR0

virtex5 HCLK_IOI bel BUFR0
PinDirectionWires
CEinputCELL1.IMUX.IMUX6
CLRinputCELL1.IMUX.IMUX0

Bel BUFR1

virtex5 HCLK_IOI bel BUFR1
PinDirectionWires
CEinputCELL2.IMUX.IMUX6
CLRinputCELL2.IMUX.IMUX0

Bel BUFIO0

virtex5 HCLK_IOI bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex5 HCLK_IOI bel BUFIO1
PinDirectionWires

Bel BUFIO2

virtex5 HCLK_IOI bel BUFIO2
PinDirectionWires

Bel BUFIO3

virtex5 HCLK_IOI bel BUFIO3
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL1.OUT18.TMIN
OUTN1outputCELL1.OUT23.TMIN
OUTN65outputCELL1.OUT16.TMIN
RDYoutputCELL1.OUT22.TMIN
RSTinputCELL0.IMUX.IMUX0
UPPULSEOUToutputCELL1.OUT17.TMIN

Bel DCI

virtex5 HCLK_IOI bel DCI
PinDirectionWires
DCIADDRESS0outputCELL1.OUT8.TMIN
DCIADDRESS1outputCELL1.OUT20.TMIN
DCIADDRESS2outputCELL1.OUT22.TMIN
DCIDATAoutputCELL0.OUT22.TMIN
DCIDONEoutputCELL0.OUT20.TMIN
DCIIOUPDATEoutputCELL0.OUT8.TMIN
DCIREFIOUPDATEoutputCELL0.OUT15.TMIN
DCISCLKoutputCELL0.OUT20.TMIN
TSTCLKinputCELL1.IMUX.BYP2.SITE
TSTHLNinputCELL1.IMUX.BYP6.SITE
TSTHLPinputCELL1.IMUX.BYP3.SITE
TSTRSTinputCELL1.IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI bel wires
WirePins
CELL0.IMUX.IMUX0IDELAYCTRL.RST
CELL0.IMUX.IMUX6RCLK.CKINT0
CELL0.OUT8.TMINDCI.DCIIOUPDATE
CELL0.OUT15.TMINDCI.DCIREFIOUPDATE
CELL0.OUT20.TMINDCI.DCIDONE, DCI.DCISCLK
CELL0.OUT22.TMINDCI.DCIDATA
CELL1.IMUX.BYP0.SITEDCI.TSTRST
CELL1.IMUX.BYP2.SITEDCI.TSTCLK
CELL1.IMUX.BYP3.SITEDCI.TSTHLP
CELL1.IMUX.BYP6.SITEDCI.TSTHLN
CELL1.IMUX.IMUX0BUFR0.CLR
CELL1.IMUX.IMUX6BUFR0.CE
CELL1.OUT8.TMINDCI.DCIADDRESS0
CELL1.OUT16.TMINIDELAYCTRL.OUTN65
CELL1.OUT17.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT18.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT20.TMINDCI.DCIADDRESS1
CELL1.OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2
CELL1.OUT23.TMINIDELAYCTRL.OUTN1
CELL2.IMUX.IMUX0BUFR1.CLR
CELL2.IMUX.IMUX6BUFR1.CE
CELL3.IMUX.IMUX0RCLK.CKINT1

Bitstream

virtex5 HCLK_IOI rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B15 - - - - - - - - BUFR1:BUFR_DIVIDE[1] IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] RCLK:MUX.RCLK2[3] RCLK:MUX.RCLK2[1] BUFR1:BUFR_DIVIDE[0] IOCLK:IOCLK_ENABLE[1] BUFR0:BUFR_DIVIDE[3] RCLK:MUX.RCLK1[3] RCLK:MUX.RCLK0[0] - - - - - - - BUFR1:BUFR_DIVIDE[2] - RCLK:MUX.RCLK0[2] RCLK:MUX.RCLK0[1] BUFR0:MUX.I[5] BUFR0:MUX.I[6] BUFR0:MUX.I[8] BUFR0:MUX.I[7] LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
B14 - - - - - - - - - - RCLK:MUX.RCLK1[2] RCLK:MUX.RCLK1[1] IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] RCLK:MUX.RCLK1[0] IOCLK:IOCLK_ENABLE[0] BUFR0:BUFR_DIVIDE[2] BUFR0:BUFR_DIVIDE[1] BUFR0:BUFR_DIVIDE[0] - - - - - - - IDELAYCTRL:MUX.REFCLK[4] BUFR1:BUFR_DIVIDE[3] IOCLK:BUF.HCLK9 RCLK:MUX.RCLK0[3] BUFR0:MUX.I[4] BUFR0:MUX.I[3] BUFR0:MUX.I[0] BUFR0:MUX.I[1] LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
B13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 BUFR1:MUX.I[5] RCLK:MUX.RCLK3[3] RCLK:MUX.RCLK2[0] RCLK:MUX.RCLK3[0] RCLK:MUX.RCLK3[1] BUFIO2:ENABLE BUFIO1:ENABLE BUFR1:MUX.I[0] BUFR1:MUX.I[4] BUFR1:MUX.I[3] BUFR1:MUX.I[2] - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 BUFR0:MUX.I[9] BUFR0:MUX.I[2] LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
B12 - - - - - - - - - BUFR1:ENABLE IDELAYCTRL:MUX.REFCLK[0] BUFR1:MUX.I[8] IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] BUFIO3:ENABLE IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 BUFR1:MUX.I[6] BUFIO0:ENABLE RCLK:MUX.RCLK3[2] BUFR1:MUX.I[7] BUFR1:MUX.I[10] BUFR1:MUX.I[9] BUFR1:MUX.I[1] - RCLK:MUX.RCLK2[2] IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 BUFR0:MUX.I[10] BUFR0:ENABLE LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:ENABLE 0.F19.B12
BUFIO1:ENABLE 0.F19.B13
BUFIO2:ENABLE 0.F18.B13
BUFIO3:ENABLE 0.F14.B12
BUFR0:ENABLE 0.F31.B12
BUFR1:ENABLE 0.F9.B12
DCI:CASCADE_FROM_ABOVE 0.F47.B14
DCI:CASCADE_FROM_BELOW 0.F47.B13
DCI:ENABLE 0.F46.B14
DCI:QUIET 0.F48.B14
IOCLK:BUF.HCLK0 0.F16.B12
IOCLK:BUF.HCLK1 0.F15.B12
IOCLK:BUF.HCLK2 0.F17.B12
IOCLK:BUF.HCLK3 0.F11.B13
IOCLK:BUF.HCLK4 0.F12.B13
IOCLK:BUF.HCLK5 0.F28.B12
IOCLK:BUF.HCLK6 0.F29.B12
IOCLK:BUF.HCLK7 0.F29.B13
IOCLK:BUF.HCLK8 0.F28.B13
IOCLK:BUF.HCLK9 0.F28.B14
IOCLK:BUF.RCLK0 0.F9.B13
IOCLK:BUF.RCLK1 0.F12.B12
IOCLK:BUF.RCLK2 0.F27.B12
IOCLK:BUF.RCLK3 0.F9.B15
non-inverted [0]
BUFR0:BUFR_DIVIDE 0.F16.B15 0.F16.B14 0.F17.B14 0.F18.B14
BUFR1:BUFR_DIVIDE 0.F27.B14 0.F26.B15 0.F8.B15 0.F14.B15
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:MUX.I 0.F30.B12 0.F30.B13 0.F32.B15 0.F33.B15 0.F31.B15 0.F30.B15 0.F30.B14 0.F31.B14 0.F31.B13 0.F33.B14 0.F32.B14
BUFR1:MUX.I 0.F22.B12 0.F23.B12 0.F11.B12 0.F21.B12 0.F18.B12 0.F13.B13 0.F21.B13 0.F22.B13 0.F23.B13 0.F24.B12 0.F20.B13
NONE 0 0 0 0 0 0 0 0 0 0 0
CKINT0 0 0 0 0 0 0 0 0 0 0 1
CKINT1 0 0 0 0 0 0 0 0 0 1 0
BUFIO0 0 0 0 0 0 0 0 0 1 0 0
BUFIO1 0 0 0 0 0 0 0 1 0 0 0
BUFIO2 0 0 0 0 0 0 1 0 0 0 0
BUFIO3 0 0 0 0 0 1 0 0 0 0 0
MGT0 0 0 0 0 1 0 0 0 0 0 0
MGT1 0 0 0 1 0 0 0 0 0 0 0
MGT2 0 0 1 0 0 0 0 0 0 0 0
MGT3 0 1 0 0 0 0 0 0 0 0 0
MGT4 1 0 0 0 0 0 0 0 0 0 0
DCI:LVDIV2 0.F53.B15 0.F53.B12 0.F52.B12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.F51.B15 0.F48.B12 0.F49.B12 0.F49.B13 0.F48.B13
DCI:PMASK_TERM_SPLIT 0.F49.B15 0.F48.B15 0.F47.B12 0.F46.B12 0.F46.B13
DCI:PMASK_TERM_VCC 0.F50.B13 0.F51.B13 0.F51.B14 0.F50.B14 0.F50.B15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.F52.B13 0.F52.B14
DCI:TEST_ENABLE 0.F53.B13 0.F49.B14
IOCLK:IOCLK_ENABLE 0.F15.B15 0.F15.B14
non-inverted [1] [0]
DCI:PREF 0.F52.B15 0.F53.B14 0.F50.B12 0.F51.B12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.F36.B14 0.F37.B14 0.F36.B13 0.F36.B12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.F10.B15 0.F11.B15 0.F12.B14 0.F13.B14 0.F13.B12 0.F26.B14 0.F10.B13 0.F26.B13 0.F27.B13 0.F10.B12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.F39.B15 0.F38.B15 0.F38.B13 0.F38.B12 0.F39.B12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.F32.B12 0.F33.B12 0.F33.B13 0.F32.B13 0.F35.B12 0.F34.B12 0.F34.B13 0.F35.B13 0.F35.B14 0.F34.B14 0.F34.B15 0.F35.B15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
RCLK:MUX.RCLK0 0.F29.B14 0.F28.B15 0.F29.B15 0.F18.B15
RCLK:MUX.RCLK1 0.F17.B15 0.F10.B14 0.F11.B14 0.F14.B14
RCLK:MUX.RCLK2 0.F12.B15 0.F26.B12 0.F13.B15 0.F15.B13
RCLK:MUX.RCLK3 0.F14.B13 0.F20.B12 0.F17.B13 0.F16.B13
NONE 0 0 0 0
VRCLK_N0 0 0 0 1
VRCLK0 0 0 1 1
VRCLK_N1 0 1 0 1
VRCLK1 0 1 1 1
VRCLK_S0 1 0 0 1
VRCLK_S1 1 1 0 1

Tile HCLK_IOI_CENTER

Cells: 2

Bel IOCLK

virtex5 HCLK_IOI_CENTER bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex5 HCLK_IOI_CENTER bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex5 HCLK_IOI_CENTER bel BUFIO1
PinDirectionWires

Bel BUFIO2

virtex5 HCLK_IOI_CENTER bel BUFIO2
PinDirectionWires

Bel BUFIO3

virtex5 HCLK_IOI_CENTER bel BUFIO3
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI_CENTER bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL1.OUT18.TMIN
OUTN1outputCELL1.OUT23.TMIN
OUTN65outputCELL1.OUT16.TMIN
RDYoutputCELL1.OUT22.TMIN
RSTinputCELL0.IMUX.IMUX0
UPPULSEOUToutputCELL1.OUT17.TMIN

Bel DCI

virtex5 HCLK_IOI_CENTER bel DCI
PinDirectionWires
DCIADDRESS0outputCELL1.OUT8.TMIN
DCIADDRESS1outputCELL1.OUT20.TMIN
DCIADDRESS2outputCELL1.OUT22.TMIN
DCIDATAoutputCELL0.OUT22.TMIN
DCIDONEoutputCELL0.OUT20.TMIN
DCIIOUPDATEoutputCELL0.OUT8.TMIN
DCIREFIOUPDATEoutputCELL0.OUT15.TMIN
DCISCLKoutputCELL0.OUT20.TMIN
TSTCLKinputCELL1.IMUX.BYP2.SITE
TSTHLNinputCELL1.IMUX.BYP6.SITE
TSTHLPinputCELL1.IMUX.BYP3.SITE
TSTRSTinputCELL1.IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI_CENTER bel wires
WirePins
CELL0.IMUX.IMUX0IDELAYCTRL.RST
CELL0.OUT8.TMINDCI.DCIIOUPDATE
CELL0.OUT15.TMINDCI.DCIREFIOUPDATE
CELL0.OUT20.TMINDCI.DCIDONE, DCI.DCISCLK
CELL0.OUT22.TMINDCI.DCIDATA
CELL1.IMUX.BYP0.SITEDCI.TSTRST
CELL1.IMUX.BYP2.SITEDCI.TSTCLK
CELL1.IMUX.BYP3.SITEDCI.TSTHLP
CELL1.IMUX.BYP6.SITEDCI.TSTHLN
CELL1.OUT8.TMINDCI.DCIADDRESS0
CELL1.OUT16.TMINIDELAYCTRL.OUTN65
CELL1.OUT17.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT18.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT20.TMINDCI.DCIADDRESS1
CELL1.OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2
CELL1.OUT23.TMINIDELAYCTRL.OUTN1

Bitstream

virtex5 HCLK_IOI_CENTER rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
B14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
B13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - BUFIO2:ENABLE BUFIO1:ENABLE - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
B12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] BUFIO3:ENABLE IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - BUFIO0:ENABLE - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:ENABLE 0.F19.B12
BUFIO1:ENABLE 0.F19.B13
BUFIO2:ENABLE 0.F18.B13
BUFIO3:ENABLE 0.F14.B12
DCI:CASCADE_FROM_ABOVE 0.F47.B14
DCI:CASCADE_FROM_BELOW 0.F47.B13
DCI:ENABLE 0.F46.B14
DCI:QUIET 0.F48.B14
IOCLK:BUF.HCLK0 0.F16.B12
IOCLK:BUF.HCLK1 0.F15.B12
IOCLK:BUF.HCLK2 0.F17.B12
IOCLK:BUF.HCLK3 0.F11.B13
IOCLK:BUF.HCLK4 0.F12.B13
IOCLK:BUF.HCLK5 0.F28.B12
IOCLK:BUF.HCLK6 0.F29.B12
IOCLK:BUF.HCLK7 0.F29.B13
IOCLK:BUF.HCLK8 0.F28.B13
IOCLK:BUF.HCLK9 0.F28.B14
IOCLK:BUF.RCLK0 0.F9.B13
IOCLK:BUF.RCLK1 0.F12.B12
IOCLK:BUF.RCLK2 0.F27.B12
IOCLK:BUF.RCLK3 0.F9.B15
IOCLK:ENABLE.RCLK0 0.F18.B15
IOCLK:ENABLE.RCLK1 0.F14.B14
IOCLK:ENABLE.RCLK2 0.F15.B13
IOCLK:ENABLE.RCLK3 0.F16.B13
non-inverted [0]
DCI:LVDIV2 0.F53.B15 0.F53.B12 0.F52.B12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.F51.B15 0.F48.B12 0.F49.B12 0.F49.B13 0.F48.B13
DCI:PMASK_TERM_SPLIT 0.F49.B15 0.F48.B15 0.F47.B12 0.F46.B12 0.F46.B13
DCI:PMASK_TERM_VCC 0.F50.B13 0.F51.B13 0.F51.B14 0.F50.B14 0.F50.B15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.F52.B13 0.F52.B14
DCI:TEST_ENABLE 0.F53.B13 0.F49.B14
IOCLK:IOCLK_ENABLE 0.F15.B15 0.F15.B14
non-inverted [1] [0]
DCI:PREF 0.F52.B15 0.F53.B14 0.F50.B12 0.F51.B12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.F36.B14 0.F37.B14 0.F36.B13 0.F36.B12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.F10.B15 0.F11.B15 0.F12.B14 0.F13.B14 0.F13.B12 0.F26.B14 0.F10.B13 0.F26.B13 0.F27.B13 0.F10.B12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.F39.B15 0.F38.B15 0.F38.B13 0.F38.B12 0.F39.B12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.F32.B12 0.F33.B12 0.F33.B13 0.F32.B13 0.F35.B12 0.F34.B12 0.F34.B13 0.F35.B13 0.F35.B14 0.F34.B14 0.F34.B15 0.F35.B15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_IOI_BOTCEN

Cells: 2

Bel IOCLK

virtex5 HCLK_IOI_BOTCEN bel IOCLK
PinDirectionWires

Bel BUFIO2

virtex5 HCLK_IOI_BOTCEN bel BUFIO2
PinDirectionWires

Bel BUFIO3

virtex5 HCLK_IOI_BOTCEN bel BUFIO3
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI_BOTCEN bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL1.OUT18.TMIN
OUTN1outputCELL1.OUT23.TMIN
OUTN65outputCELL1.OUT16.TMIN
RDYoutputCELL1.OUT22.TMIN
RSTinputCELL0.IMUX.IMUX0
UPPULSEOUToutputCELL1.OUT17.TMIN

Bel DCI

virtex5 HCLK_IOI_BOTCEN bel DCI
PinDirectionWires
DCIADDRESS0outputCELL1.OUT8.TMIN
DCIADDRESS1outputCELL1.OUT20.TMIN
DCIADDRESS2outputCELL1.OUT22.TMIN
DCIDATAoutputCELL0.OUT22.TMIN
DCIDONEoutputCELL0.OUT20.TMIN
DCIIOUPDATEoutputCELL0.OUT8.TMIN
DCIREFIOUPDATEoutputCELL0.OUT15.TMIN
DCISCLKoutputCELL0.OUT20.TMIN
TSTCLKinputCELL1.IMUX.BYP2.SITE
TSTHLNinputCELL1.IMUX.BYP6.SITE
TSTHLPinputCELL1.IMUX.BYP3.SITE
TSTRSTinputCELL1.IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI_BOTCEN bel wires
WirePins
CELL0.IMUX.IMUX0IDELAYCTRL.RST
CELL0.OUT8.TMINDCI.DCIIOUPDATE
CELL0.OUT15.TMINDCI.DCIREFIOUPDATE
CELL0.OUT20.TMINDCI.DCIDONE, DCI.DCISCLK
CELL0.OUT22.TMINDCI.DCIDATA
CELL1.IMUX.BYP0.SITEDCI.TSTRST
CELL1.IMUX.BYP2.SITEDCI.TSTCLK
CELL1.IMUX.BYP3.SITEDCI.TSTHLP
CELL1.IMUX.BYP6.SITEDCI.TSTHLN
CELL1.OUT8.TMINDCI.DCIADDRESS0
CELL1.OUT16.TMINIDELAYCTRL.OUTN65
CELL1.OUT17.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT18.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT20.TMINDCI.DCIADDRESS1
CELL1.OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2
CELL1.OUT23.TMINIDELAYCTRL.OUTN1

Bitstream

virtex5 HCLK_IOI_BOTCEN rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
B14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
B13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - BUFIO2:ENABLE - - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
B12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] BUFIO3:ENABLE IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - - - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO2:ENABLE 0.F18.B13
BUFIO3:ENABLE 0.F14.B12
DCI:CASCADE_FROM_ABOVE 0.F47.B14
DCI:CASCADE_FROM_BELOW 0.F47.B13
DCI:ENABLE 0.F46.B14
DCI:QUIET 0.F48.B14
IOCLK:BUF.HCLK0 0.F16.B12
IOCLK:BUF.HCLK1 0.F15.B12
IOCLK:BUF.HCLK2 0.F17.B12
IOCLK:BUF.HCLK3 0.F11.B13
IOCLK:BUF.HCLK4 0.F12.B13
IOCLK:BUF.HCLK5 0.F28.B12
IOCLK:BUF.HCLK6 0.F29.B12
IOCLK:BUF.HCLK7 0.F29.B13
IOCLK:BUF.HCLK8 0.F28.B13
IOCLK:BUF.HCLK9 0.F28.B14
IOCLK:BUF.RCLK0 0.F9.B13
IOCLK:BUF.RCLK1 0.F12.B12
IOCLK:BUF.RCLK2 0.F27.B12
IOCLK:BUF.RCLK3 0.F9.B15
IOCLK:ENABLE.RCLK0 0.F18.B15
IOCLK:ENABLE.RCLK1 0.F14.B14
IOCLK:ENABLE.RCLK2 0.F15.B13
IOCLK:ENABLE.RCLK3 0.F16.B13
non-inverted [0]
DCI:LVDIV2 0.F53.B15 0.F53.B12 0.F52.B12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.F51.B15 0.F48.B12 0.F49.B12 0.F49.B13 0.F48.B13
DCI:PMASK_TERM_SPLIT 0.F49.B15 0.F48.B15 0.F47.B12 0.F46.B12 0.F46.B13
DCI:PMASK_TERM_VCC 0.F50.B13 0.F51.B13 0.F51.B14 0.F50.B14 0.F50.B15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.F52.B13 0.F52.B14
DCI:TEST_ENABLE 0.F53.B13 0.F49.B14
IOCLK:IOCLK_ENABLE 0.F15.B15 0.F15.B14
non-inverted [1] [0]
DCI:PREF 0.F52.B15 0.F53.B14 0.F50.B12 0.F51.B12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.F36.B14 0.F37.B14 0.F36.B13 0.F36.B12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.F10.B15 0.F11.B15 0.F12.B14 0.F13.B14 0.F13.B12 0.F26.B14 0.F10.B13 0.F26.B13 0.F27.B13 0.F10.B12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.F39.B15 0.F38.B15 0.F38.B13 0.F38.B12 0.F39.B12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.F32.B12 0.F33.B12 0.F33.B13 0.F32.B13 0.F35.B12 0.F34.B12 0.F34.B13 0.F35.B13 0.F35.B14 0.F34.B14 0.F34.B15 0.F35.B15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_IOI_TOPCEN

Cells: 2

Bel IOCLK

virtex5 HCLK_IOI_TOPCEN bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex5 HCLK_IOI_TOPCEN bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex5 HCLK_IOI_TOPCEN bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI_TOPCEN bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL0.OUT23.TMIN
OUTN1outputCELL0.OUT20.TMIN
OUTN65outputCELL0.OUT8.TMIN
RDYoutputCELL0.OUT22.TMIN
RSTinputCELL1.IMUX.IMUX6
UPPULSEOUToutputCELL0.OUT15.TMIN

Bel DCI

virtex5 HCLK_IOI_TOPCEN bel DCI
PinDirectionWires
DCIADDRESS0outputCELL0.OUT8.TMIN
DCIADDRESS1outputCELL0.OUT20.TMIN
DCIADDRESS2outputCELL0.OUT22.TMIN
DCIDATAoutputCELL0.OUT22.TMIN
DCIDONEoutputCELL0.OUT20.TMIN
DCIIOUPDATEoutputCELL0.OUT8.TMIN
DCIREFIOUPDATEoutputCELL0.OUT15.TMIN
DCISCLKoutputCELL0.OUT20.TMIN
TSTCLKinputCELL0.IMUX.BYP2.SITE
TSTHLNinputCELL0.IMUX.BYP6.SITE
TSTHLPinputCELL0.IMUX.BYP3.SITE
TSTRSTinputCELL0.IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI_TOPCEN bel wires
WirePins
CELL0.IMUX.BYP0.SITEDCI.TSTRST
CELL0.IMUX.BYP2.SITEDCI.TSTCLK
CELL0.IMUX.BYP3.SITEDCI.TSTHLP
CELL0.IMUX.BYP6.SITEDCI.TSTHLN
CELL0.OUT8.TMINIDELAYCTRL.OUTN65, DCI.DCIADDRESS0, DCI.DCIIOUPDATE
CELL0.OUT15.TMINIDELAYCTRL.UPPULSEOUT, DCI.DCIREFIOUPDATE
CELL0.OUT20.TMINIDELAYCTRL.OUTN1, DCI.DCIADDRESS1, DCI.DCIDONE, DCI.DCISCLK
CELL0.OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2, DCI.DCIDATA
CELL0.OUT23.TMINIDELAYCTRL.DNPULSEOUT
CELL1.IMUX.IMUX6IDELAYCTRL.RST

Bitstream

virtex5 HCLK_IOI_TOPCEN rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - SYSMON:ENABLE - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
B14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
B13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - - BUFIO1:ENABLE - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
B12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - BUFIO0:ENABLE - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:ENABLE 0.F19.B12
BUFIO1:ENABLE 0.F19.B13
DCI:CASCADE_FROM_ABOVE 0.F47.B14
DCI:CASCADE_FROM_BELOW 0.F47.B13
DCI:ENABLE 0.F46.B14
DCI:QUIET 0.F48.B14
IOCLK:BUF.HCLK0 0.F16.B12
IOCLK:BUF.HCLK1 0.F15.B12
IOCLK:BUF.HCLK2 0.F17.B12
IOCLK:BUF.HCLK3 0.F11.B13
IOCLK:BUF.HCLK4 0.F12.B13
IOCLK:BUF.HCLK5 0.F28.B12
IOCLK:BUF.HCLK6 0.F29.B12
IOCLK:BUF.HCLK7 0.F29.B13
IOCLK:BUF.HCLK8 0.F28.B13
IOCLK:BUF.HCLK9 0.F28.B14
IOCLK:BUF.RCLK0 0.F9.B13
IOCLK:BUF.RCLK1 0.F12.B12
IOCLK:BUF.RCLK2 0.F27.B12
IOCLK:BUF.RCLK3 0.F9.B15
IOCLK:ENABLE.RCLK0 0.F18.B15
IOCLK:ENABLE.RCLK1 0.F14.B14
IOCLK:ENABLE.RCLK2 0.F15.B13
IOCLK:ENABLE.RCLK3 0.F16.B13
SYSMON:ENABLE 0.F27.B15
non-inverted [0]
DCI:LVDIV2 0.F53.B15 0.F53.B12 0.F52.B12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.F51.B15 0.F48.B12 0.F49.B12 0.F49.B13 0.F48.B13
DCI:PMASK_TERM_SPLIT 0.F49.B15 0.F48.B15 0.F47.B12 0.F46.B12 0.F46.B13
DCI:PMASK_TERM_VCC 0.F50.B13 0.F51.B13 0.F51.B14 0.F50.B14 0.F50.B15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.F52.B13 0.F52.B14
DCI:TEST_ENABLE 0.F53.B13 0.F49.B14
IOCLK:IOCLK_ENABLE 0.F15.B15 0.F15.B14
non-inverted [1] [0]
DCI:PREF 0.F52.B15 0.F53.B14 0.F50.B12 0.F51.B12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.F36.B14 0.F37.B14 0.F36.B13 0.F36.B12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.F10.B15 0.F11.B15 0.F12.B14 0.F13.B14 0.F13.B12 0.F26.B14 0.F10.B13 0.F26.B13 0.F27.B13 0.F10.B12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.F39.B15 0.F38.B15 0.F38.B13 0.F38.B12 0.F39.B12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.F32.B12 0.F33.B12 0.F33.B13 0.F32.B13 0.F35.B12 0.F34.B12 0.F34.B13 0.F35.B13 0.F35.B14 0.F34.B14 0.F34.B15 0.F35.B15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_IOI_CMT

Cells: 2

Bel IOCLK

virtex5 HCLK_IOI_CMT bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex5 HCLK_IOI_CMT bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex5 HCLK_IOI_CMT bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI_CMT bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL0.OUT23.TMIN
OUTN1outputCELL0.OUT20.TMIN
OUTN65outputCELL0.OUT8.TMIN
RDYoutputCELL0.OUT22.TMIN
RSTinputCELL1.IMUX.IMUX6
UPPULSEOUToutputCELL0.OUT15.TMIN

Bel DCI

virtex5 HCLK_IOI_CMT bel DCI
PinDirectionWires
DCIADDRESS0outputCELL0.OUT8.TMIN
DCIADDRESS1outputCELL0.OUT20.TMIN
DCIADDRESS2outputCELL0.OUT22.TMIN
DCIDATAoutputCELL0.OUT22.TMIN
DCIDONEoutputCELL0.OUT20.TMIN
DCIIOUPDATEoutputCELL0.OUT8.TMIN
DCIREFIOUPDATEoutputCELL0.OUT15.TMIN
DCISCLKoutputCELL0.OUT20.TMIN
TSTCLKinputCELL0.IMUX.BYP2.SITE
TSTHLNinputCELL0.IMUX.BYP6.SITE
TSTHLPinputCELL0.IMUX.BYP3.SITE
TSTRSTinputCELL0.IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI_CMT bel wires
WirePins
CELL0.IMUX.BYP0.SITEDCI.TSTRST
CELL0.IMUX.BYP2.SITEDCI.TSTCLK
CELL0.IMUX.BYP3.SITEDCI.TSTHLP
CELL0.IMUX.BYP6.SITEDCI.TSTHLN
CELL0.OUT8.TMINIDELAYCTRL.OUTN65, DCI.DCIADDRESS0, DCI.DCIIOUPDATE
CELL0.OUT15.TMINIDELAYCTRL.UPPULSEOUT, DCI.DCIREFIOUPDATE
CELL0.OUT20.TMINIDELAYCTRL.OUTN1, DCI.DCIADDRESS1, DCI.DCIDONE, DCI.DCISCLK
CELL0.OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2, DCI.DCIDATA
CELL0.OUT23.TMINIDELAYCTRL.DNPULSEOUT
CELL1.IMUX.IMUX6IDELAYCTRL.RST

Bitstream

virtex5 HCLK_IOI_CMT rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
B14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
B13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - - BUFIO1:ENABLE - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
B12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - BUFIO0:ENABLE - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:ENABLE 0.F19.B12
BUFIO1:ENABLE 0.F19.B13
DCI:CASCADE_FROM_ABOVE 0.F47.B14
DCI:CASCADE_FROM_BELOW 0.F47.B13
DCI:ENABLE 0.F46.B14
DCI:QUIET 0.F48.B14
IOCLK:BUF.HCLK0 0.F16.B12
IOCLK:BUF.HCLK1 0.F15.B12
IOCLK:BUF.HCLK2 0.F17.B12
IOCLK:BUF.HCLK3 0.F11.B13
IOCLK:BUF.HCLK4 0.F12.B13
IOCLK:BUF.HCLK5 0.F28.B12
IOCLK:BUF.HCLK6 0.F29.B12
IOCLK:BUF.HCLK7 0.F29.B13
IOCLK:BUF.HCLK8 0.F28.B13
IOCLK:BUF.HCLK9 0.F28.B14
IOCLK:BUF.RCLK0 0.F9.B13
IOCLK:BUF.RCLK1 0.F12.B12
IOCLK:BUF.RCLK2 0.F27.B12
IOCLK:BUF.RCLK3 0.F9.B15
IOCLK:ENABLE.RCLK0 0.F18.B15
IOCLK:ENABLE.RCLK1 0.F14.B14
IOCLK:ENABLE.RCLK2 0.F15.B13
IOCLK:ENABLE.RCLK3 0.F16.B13
non-inverted [0]
DCI:LVDIV2 0.F53.B15 0.F53.B12 0.F52.B12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.F51.B15 0.F48.B12 0.F49.B12 0.F49.B13 0.F48.B13
DCI:PMASK_TERM_SPLIT 0.F49.B15 0.F48.B15 0.F47.B12 0.F46.B12 0.F46.B13
DCI:PMASK_TERM_VCC 0.F50.B13 0.F51.B13 0.F51.B14 0.F50.B14 0.F50.B15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.F52.B13 0.F52.B14
DCI:TEST_ENABLE 0.F53.B13 0.F49.B14
IOCLK:IOCLK_ENABLE 0.F15.B15 0.F15.B14
non-inverted [1] [0]
DCI:PREF 0.F52.B15 0.F53.B14 0.F50.B12 0.F51.B12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.F36.B14 0.F37.B14 0.F36.B13 0.F36.B12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.F10.B15 0.F11.B15 0.F12.B14 0.F13.B14 0.F13.B12 0.F26.B14 0.F10.B13 0.F26.B13 0.F27.B13 0.F10.B12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.F39.B15 0.F38.B15 0.F38.B13 0.F38.B12 0.F39.B12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.F32.B12 0.F33.B12 0.F33.B13 0.F32.B13 0.F35.B12 0.F34.B12 0.F34.B13 0.F35.B13 0.F35.B14 0.F34.B14 0.F34.B15 0.F35.B15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_CMT_IOI

Cells: 2

Bel IOCLK

virtex5 HCLK_CMT_IOI bel IOCLK
PinDirectionWires

Bel BUFIO2

virtex5 HCLK_CMT_IOI bel BUFIO2
PinDirectionWires

Bel BUFIO3

virtex5 HCLK_CMT_IOI bel BUFIO3
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_CMT_IOI bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL1.OUT18.TMIN
OUTN1outputCELL1.OUT23.TMIN
OUTN65outputCELL1.OUT16.TMIN
RDYoutputCELL1.OUT22.TMIN
RSTinputCELL0.IMUX.IMUX0
UPPULSEOUToutputCELL1.OUT17.TMIN

Bel DCI

virtex5 HCLK_CMT_IOI bel DCI
PinDirectionWires
DCIADDRESS0outputCELL1.OUT8.TMIN
DCIADDRESS1outputCELL1.OUT20.TMIN
DCIADDRESS2outputCELL1.OUT22.TMIN
DCIDATAoutputCELL0.OUT22.TMIN
DCIDONEoutputCELL0.OUT20.TMIN
DCIIOUPDATEoutputCELL0.OUT8.TMIN
DCIREFIOUPDATEoutputCELL0.OUT15.TMIN
DCISCLKoutputCELL0.OUT20.TMIN
TSTCLKinputCELL1.IMUX.BYP2.SITE
TSTHLNinputCELL1.IMUX.BYP6.SITE
TSTHLPinputCELL1.IMUX.BYP3.SITE
TSTRSTinputCELL1.IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_CMT_IOI bel wires
WirePins
CELL0.IMUX.IMUX0IDELAYCTRL.RST
CELL0.OUT8.TMINDCI.DCIIOUPDATE
CELL0.OUT15.TMINDCI.DCIREFIOUPDATE
CELL0.OUT20.TMINDCI.DCIDONE, DCI.DCISCLK
CELL0.OUT22.TMINDCI.DCIDATA
CELL1.IMUX.BYP0.SITEDCI.TSTRST
CELL1.IMUX.BYP2.SITEDCI.TSTCLK
CELL1.IMUX.BYP3.SITEDCI.TSTHLP
CELL1.IMUX.BYP6.SITEDCI.TSTHLN
CELL1.OUT8.TMINDCI.DCIADDRESS0
CELL1.OUT16.TMINIDELAYCTRL.OUTN65
CELL1.OUT17.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT18.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT20.TMINDCI.DCIADDRESS1
CELL1.OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2
CELL1.OUT23.TMINIDELAYCTRL.OUTN1

Bitstream

virtex5 HCLK_CMT_IOI rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
B14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
B13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - BUFIO2:ENABLE - - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
B12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] BUFIO3:ENABLE IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - - - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO2:ENABLE 0.F18.B13
BUFIO3:ENABLE 0.F14.B12
DCI:CASCADE_FROM_ABOVE 0.F47.B14
DCI:CASCADE_FROM_BELOW 0.F47.B13
DCI:ENABLE 0.F46.B14
DCI:QUIET 0.F48.B14
IOCLK:BUF.HCLK0 0.F16.B12
IOCLK:BUF.HCLK1 0.F15.B12
IOCLK:BUF.HCLK2 0.F17.B12
IOCLK:BUF.HCLK3 0.F11.B13
IOCLK:BUF.HCLK4 0.F12.B13
IOCLK:BUF.HCLK5 0.F28.B12
IOCLK:BUF.HCLK6 0.F29.B12
IOCLK:BUF.HCLK7 0.F29.B13
IOCLK:BUF.HCLK8 0.F28.B13
IOCLK:BUF.HCLK9 0.F28.B14
IOCLK:BUF.RCLK0 0.F9.B13
IOCLK:BUF.RCLK1 0.F12.B12
IOCLK:BUF.RCLK2 0.F27.B12
IOCLK:BUF.RCLK3 0.F9.B15
IOCLK:ENABLE.RCLK0 0.F18.B15
IOCLK:ENABLE.RCLK1 0.F14.B14
IOCLK:ENABLE.RCLK2 0.F15.B13
IOCLK:ENABLE.RCLK3 0.F16.B13
non-inverted [0]
DCI:LVDIV2 0.F53.B15 0.F53.B12 0.F52.B12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.F51.B15 0.F48.B12 0.F49.B12 0.F49.B13 0.F48.B13
DCI:PMASK_TERM_SPLIT 0.F49.B15 0.F48.B15 0.F47.B12 0.F46.B12 0.F46.B13
DCI:PMASK_TERM_VCC 0.F50.B13 0.F51.B13 0.F51.B14 0.F50.B14 0.F50.B15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.F52.B13 0.F52.B14
DCI:TEST_ENABLE 0.F53.B13 0.F49.B14
IOCLK:IOCLK_ENABLE 0.F15.B15 0.F15.B14
non-inverted [1] [0]
DCI:PREF 0.F52.B15 0.F53.B14 0.F50.B12 0.F51.B12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.F36.B14 0.F37.B14 0.F36.B13 0.F36.B12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.F10.B15 0.F11.B15 0.F12.B14 0.F13.B14 0.F13.B12 0.F26.B14 0.F10.B13 0.F26.B13 0.F27.B13 0.F10.B12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.F39.B15 0.F38.B15 0.F38.B13 0.F38.B12 0.F39.B12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.F32.B12 0.F33.B12 0.F33.B13 0.F32.B13 0.F35.B12 0.F34.B12 0.F34.B13 0.F35.B13 0.F35.B14 0.F34.B14 0.F34.B15 0.F35.B15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_CMT

Cells: 0

Bel HCLK_CMT_HCLK

virtex5 HCLK_CMT bel HCLK_CMT_HCLK
PinDirectionWires

Bel HCLK_CMT_GIOB

virtex5 HCLK_CMT bel HCLK_CMT_GIOB
PinDirectionWires

Bitstream

virtex5 HCLK_CMT rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_CMT:DRP_MASK - - - - - - - - - - - - HCLK_CMT:BUF.HCLK9 HCLK_CMT:BUF.HCLK5 HCLK_CMT:BUF.HCLK1 HCLK_CMT:BUF.GIOB7 HCLK_CMT:BUF.GIOB3
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_CMT:BUF.HCLK8 HCLK_CMT:BUF.HCLK4 HCLK_CMT:BUF.HCLK0 HCLK_CMT:BUF.GIOB6 HCLK_CMT:BUF.GIOB2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_CMT:BUF.HCLK7 HCLK_CMT:BUF.HCLK3 HCLK_CMT:BUF.GIOB9 HCLK_CMT:BUF.GIOB5 HCLK_CMT:BUF.GIOB1
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_CMT:BUF.HCLK6 HCLK_CMT:BUF.HCLK2 HCLK_CMT:BUF.GIOB8 HCLK_CMT:BUF.GIOB4 HCLK_CMT:BUF.GIOB0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HCLK_CMT:BUF.GIOB0 0.F44.B12
HCLK_CMT:BUF.GIOB1 0.F44.B13
HCLK_CMT:BUF.GIOB2 0.F44.B14
HCLK_CMT:BUF.GIOB3 0.F44.B15
HCLK_CMT:BUF.GIOB4 0.F43.B12
HCLK_CMT:BUF.GIOB5 0.F43.B13
HCLK_CMT:BUF.GIOB6 0.F43.B14
HCLK_CMT:BUF.GIOB7 0.F43.B15
HCLK_CMT:BUF.GIOB8 0.F42.B12
HCLK_CMT:BUF.GIOB9 0.F42.B13
HCLK_CMT:BUF.HCLK0 0.F42.B14
HCLK_CMT:BUF.HCLK1 0.F42.B15
HCLK_CMT:BUF.HCLK2 0.F41.B12
HCLK_CMT:BUF.HCLK3 0.F41.B13
HCLK_CMT:BUF.HCLK4 0.F41.B14
HCLK_CMT:BUF.HCLK5 0.F41.B15
HCLK_CMT:BUF.HCLK6 0.F40.B12
HCLK_CMT:BUF.HCLK7 0.F40.B13
HCLK_CMT:BUF.HCLK8 0.F40.B14
HCLK_CMT:BUF.HCLK9 0.F40.B15
HCLK_CMT:DRP_MASK 0.F27.B15
non-inverted [0]