Clock I/O and CMT buffers

Tile HCLK_IO

Cells: 4

Switchbox HCLK_IO_INT

virtex5 HCLK_IO switchbox HCLK_IO_INT programmable buffers
Destination	Source	Bit
CELL[2].HCLK_IO[0]	CELL[2].HCLK_ROW[0]	MAIN[16][12]
CELL[2].HCLK_IO[1]	CELL[2].HCLK_ROW[1]	MAIN[15][12]
CELL[2].HCLK_IO[2]	CELL[2].HCLK_ROW[2]	MAIN[17][12]
CELL[2].HCLK_IO[3]	CELL[2].HCLK_ROW[3]	MAIN[11][13]
CELL[2].HCLK_IO[4]	CELL[2].HCLK_ROW[4]	MAIN[12][13]
CELL[2].HCLK_IO[5]	CELL[2].HCLK_ROW[5]	MAIN[28][12]
CELL[2].HCLK_IO[6]	CELL[2].HCLK_ROW[6]	MAIN[29][12]
CELL[2].HCLK_IO[7]	CELL[2].HCLK_ROW[7]	MAIN[29][13]
CELL[2].HCLK_IO[8]	CELL[2].HCLK_ROW[8]	MAIN[28][13]
CELL[2].HCLK_IO[9]	CELL[2].HCLK_ROW[9]	MAIN[28][14]
CELL[2].RCLK_IO[0]	CELL[2].RCLK_ROW[0]	MAIN[9][13]
CELL[2].RCLK_IO[1]	CELL[2].RCLK_ROW[1]	MAIN[12][12]
CELL[2].RCLK_IO[2]	CELL[2].RCLK_ROW[2]	MAIN[27][12]
CELL[2].RCLK_IO[3]	CELL[2].RCLK_ROW[3]	MAIN[9][15]

virtex5 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[0]
Bits				Destination
MAIN[29][14]	MAIN[28][15]	MAIN[29][15]	MAIN[18][15]	CELL[2].RCLK_ROW[0]
				Source
0	0	0	0	off
0	0	0	1	CELL[2].VRCLK_N[0]
0	0	1	1	CELL[2].VRCLK[0]
0	1	0	1	CELL[2].VRCLK_N[1]
0	1	1	1	CELL[2].VRCLK[1]
1	0	0	1	CELL[2].VRCLK_S[0]
1	1	0	1	CELL[2].VRCLK_S[1]

virtex5 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[1]
Bits				Destination
MAIN[17][15]	MAIN[10][14]	MAIN[11][14]	MAIN[14][14]	CELL[2].RCLK_ROW[1]
				Source
0	0	0	0	off
0	0	0	1	CELL[2].VRCLK_N[0]
0	0	1	1	CELL[2].VRCLK[0]
0	1	0	1	CELL[2].VRCLK_N[1]
0	1	1	1	CELL[2].VRCLK[1]
1	0	0	1	CELL[2].VRCLK_S[0]
1	1	0	1	CELL[2].VRCLK_S[1]

virtex5 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[2]
Bits				Destination
MAIN[12][15]	MAIN[26][12]	MAIN[13][15]	MAIN[15][13]	CELL[2].RCLK_ROW[2]
				Source
0	0	0	0	off
0	0	0	1	CELL[2].VRCLK_N[0]
0	0	1	1	CELL[2].VRCLK[0]
0	1	0	1	CELL[2].VRCLK_N[1]
0	1	1	1	CELL[2].VRCLK[1]
1	0	0	1	CELL[2].VRCLK_S[0]
1	1	0	1	CELL[2].VRCLK_S[1]

virtex5 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[3]
Bits				Destination
MAIN[14][13]	MAIN[20][12]	MAIN[17][13]	MAIN[16][13]	CELL[2].RCLK_ROW[3]
				Source
0	0	0	0	off
0	0	0	1	CELL[2].VRCLK_N[0]
0	0	1	1	CELL[2].VRCLK[0]
0	1	0	1	CELL[2].VRCLK_N[1]
0	1	1	1	CELL[2].VRCLK[1]
1	0	0	1	CELL[2].VRCLK_S[0]
1	1	0	1	CELL[2].VRCLK_S[1]

virtex5 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
Bits										Destination
MAIN[10][15]	MAIN[11][15]	MAIN[12][14]	MAIN[13][14]	MAIN[13][12]	MAIN[26][14]	MAIN[10][13]	MAIN[26][13]	MAIN[27][13]	MAIN[10][12]	CELL[2].IMUX_IDELAYCTRL_REFCLK
										Source
0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	1	CELL[2].HCLK_IO[0]
0	0	0	0	0	0	0	0	1	0	CELL[2].HCLK_IO[1]
0	0	0	0	0	0	0	1	0	0	CELL[2].HCLK_IO[2]
0	0	0	0	0	0	1	0	0	0	CELL[2].HCLK_IO[3]
0	0	0	0	0	1	0	0	0	0	CELL[2].HCLK_IO[4]
0	0	0	0	1	0	0	0	0	0	CELL[2].HCLK_IO[5]
0	0	0	1	0	0	0	0	0	0	CELL[2].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	CELL[2].HCLK_IO[7]
0	1	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[8]
1	0	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[9]

virtex5 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_BUFR[0]
Bits											Destination
MAIN[31][14]	MAIN[33][14]	MAIN[31][13]	MAIN[30][12]	MAIN[30][13]	MAIN[32][15]	MAIN[33][15]	MAIN[31][15]	MAIN[30][15]	MAIN[30][14]	MAIN[32][14]	CELL[2].IMUX_BUFR[0]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_IMUX[6]
0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CLKPAD
0	0	0	0	0	0	0	0	1	0	0	CELL[1].OUT_CLKPAD
0	0	0	0	0	0	0	1	0	0	0	CELL[2].MGT_ROW_I[0]
0	0	0	0	0	0	1	0	0	0	0	CELL[2].MGT_ROW_I[1]
0	0	0	0	0	1	0	0	0	0	0	CELL[2].MGT_ROW_I[2]
0	0	0	0	1	0	0	0	0	0	0	CELL[2].MGT_ROW_I[3]
0	0	0	1	0	0	0	0	0	0	0	CELL[2].MGT_ROW_I[4]
0	0	1	0	0	0	0	0	0	0	0	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	0	0	CELL[3].IMUX_IMUX[0]
1	0	0	0	0	0	0	0	0	0	0	CELL[3].OUT_CLKPAD

virtex5 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_BUFR[1]
Bits											Destination
MAIN[22][13]	MAIN[24][12]	MAIN[23][13]	MAIN[22][12]	MAIN[23][12]	MAIN[11][12]	MAIN[21][12]	MAIN[18][12]	MAIN[13][13]	MAIN[21][13]	MAIN[20][13]	CELL[2].IMUX_BUFR[1]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_IMUX[6]
0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CLKPAD
0	0	0	0	0	0	0	0	1	0	0	CELL[1].OUT_CLKPAD
0	0	0	0	0	0	0	1	0	0	0	CELL[2].MGT_ROW_I[0]
0	0	0	0	0	0	1	0	0	0	0	CELL[2].MGT_ROW_I[1]
0	0	0	0	0	1	0	0	0	0	0	CELL[2].MGT_ROW_I[2]
0	0	0	0	1	0	0	0	0	0	0	CELL[2].MGT_ROW_I[3]
0	0	0	1	0	0	0	0	0	0	0	CELL[2].MGT_ROW_I[4]
0	0	1	0	0	0	0	0	0	0	0	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	0	0	CELL[3].IMUX_IMUX[0]
1	0	0	0	0	0	0	0	0	0	0	CELL[3].OUT_CLKPAD

virtex5 HCLK_IO wire support CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]
Bit
MAIN[15][14]
MAIN[15][15]

Bels BUFR

virtex5 HCLK_IO bel BUFR pins
Pin	Direction	BUFR[0]	BUFR[1]
I	in	CELL[2].IMUX_BUFR[0]	CELL[2].IMUX_BUFR[1]
CE	in	CELL[1].IMUX_IMUX[6]	CELL[2].IMUX_IMUX[6]
CLR	in	CELL[1].IMUX_IMUX[0]	CELL[2].IMUX_IMUX[0]
O	out	CELL[2].VRCLK[0]	CELL[2].VRCLK[1]

virtex5 HCLK_IO bel BUFR attribute bits
Attribute	BUFR[0]	BUFR[1]
ENABLE	MAIN[31][12]	MAIN[9][12]
DIVIDE	[enum: BUFR_DIVIDE]	[enum: BUFR_DIVIDE]

virtex5 HCLK_IO enum BUFR_DIVIDE
BUFR[0].DIVIDE	MAIN[16][15]	MAIN[16][14]	MAIN[17][14]	MAIN[18][14]
BUFR[1].DIVIDE	MAIN[27][14]	MAIN[26][15]	MAIN[8][15]	MAIN[14][15]
BYPASS	0	0	0	0
_1	0	0	0	1
_2	0	0	1	1
_3	0	1	0	1
_4	0	1	1	1
_5	1	0	0	1
_6	1	0	1	1
_7	1	1	0	1
_8	1	1	1	1

Bels BUFIO

virtex5 HCLK_IO bel BUFIO pins
Pin	Direction	BUFIO[0]	BUFIO[1]	BUFIO[2]	BUFIO[3]
I	in	CELL[2].OUT_CLKPAD	CELL[3].OUT_CLKPAD	CELL[0].OUT_CLKPAD	CELL[1].OUT_CLKPAD
O	out	CELL[2].IOCLK[0]	CELL[2].IOCLK[1]	CELL[2].IOCLK[2]	CELL[2].IOCLK[3]

virtex5 HCLK_IO bel BUFIO attribute bits
Attribute	BUFIO[0]	BUFIO[1]	BUFIO[2]	BUFIO[3]
ENABLE	MAIN[19][12]	MAIN[19][13]	MAIN[18][13]	MAIN[14][12]

Bels IDELAYCTRL

virtex5 HCLK_IO bel IDELAYCTRL pins
Pin	Direction	IDELAYCTRL
REFCLK	in	CELL[2].IMUX_IDELAYCTRL_REFCLK
RST	in	CELL[0].IMUX_IMUX[0]
RDY	out	CELL[1].OUT_BEL[22]
DNPULSEOUT	out	CELL[1].OUT_BEL[18]
UPPULSEOUT	out	CELL[1].OUT_BEL[17]
OUTN1	out	CELL[1].OUT_BEL[23]
OUTN65	out	CELL[1].OUT_BEL[16]

virtex5 HCLK_IO bel IDELAYCTRL attribute bits
Attribute	IDELAYCTRL
DLL_ENABLE	MAIN[37][14]
DELAY_ENABLE	MAIN[36][12]
VCTL_SEL bit 0	MAIN[36][13]
VCTL_SEL bit 1	MAIN[36][14]

Bels DCI

virtex5 HCLK_IO bel DCI pins
Pin	Direction	DCI
TSTCLK	in	CELL[1].IMUX_BYP_SITE[2]
TSTRST	in	CELL[1].IMUX_BYP_SITE[0]
TSTHLP	in	CELL[1].IMUX_BYP_SITE[3]
TSTHLN	in	CELL[1].IMUX_BYP_SITE[6]
DCISCLK	out	CELL[0].OUT_BEL[20]
DCIADDRESS[0]	out	CELL[1].OUT_BEL[8]
DCIADDRESS[1]	out	CELL[1].OUT_BEL[20]
DCIADDRESS[2]	out	CELL[1].OUT_BEL[22]
DCIDATA	out	CELL[0].OUT_BEL[22]
DCIIOUPDATE	out	CELL[0].OUT_BEL[8]
DCIREFIOUPDATE	out	CELL[0].OUT_BEL[15]
DCIDONE	out	CELL[0].OUT_BEL[20]

virtex5 HCLK_IO bel DCI attribute bits
Attribute	DCI
ENABLE	MAIN[46][14]
QUIET	MAIN[48][14]
V5_LVDIV2 bit 0	MAIN[52][12]
V5_LVDIV2 bit 1	MAIN[53][12]
V5_LVDIV2 bit 2	MAIN[53][15]
V4_PMASK_TERM_VCC bit 0	MAIN[50][15]
V4_PMASK_TERM_VCC bit 1	MAIN[50][14]
V4_PMASK_TERM_VCC bit 2	MAIN[51][14]
V4_PMASK_TERM_VCC bit 3	MAIN[51][13]
V4_PMASK_TERM_VCC bit 4	MAIN[50][13]
V4_PMASK_TERM_SPLIT bit 0	MAIN[46][13]
V4_PMASK_TERM_SPLIT bit 1	MAIN[46][12]
V4_PMASK_TERM_SPLIT bit 2	MAIN[47][12]
V4_PMASK_TERM_SPLIT bit 3	MAIN[48][15]
V4_PMASK_TERM_SPLIT bit 4	MAIN[49][15]
V4_NMASK_TERM_SPLIT bit 0	MAIN[48][13]
V4_NMASK_TERM_SPLIT bit 1	MAIN[49][13]
V4_NMASK_TERM_SPLIT bit 2	MAIN[49][12]
V4_NMASK_TERM_SPLIT bit 3	MAIN[48][12]
V4_NMASK_TERM_SPLIT bit 4	MAIN[51][15]
NREF bit 0	MAIN[52][14]
NREF bit 1	MAIN[52][13]
PREF bit 0	MAIN[51][12]
PREF bit 1	MAIN[50][12]
PREF bit 2	MAIN[53][14]
PREF bit 3	MAIN[52][15]
TEST_ENABLE bit 0	MAIN[49][14]
TEST_ENABLE bit 1	MAIN[53][13]
CASCADE_FROM_ABOVE	MAIN[47][14]
CASCADE_FROM_BELOW	MAIN[47][13]

Bels BANK

virtex5 HCLK_IO bel BANK pins
Pin	Direction	BANK

virtex5 HCLK_IO bel BANK attribute bits
Attribute	BANK
V5_LVDSBIAS bit 0	MAIN[35][15]
V5_LVDSBIAS bit 1	MAIN[34][15]
V5_LVDSBIAS bit 2	MAIN[34][14]
V5_LVDSBIAS bit 3	MAIN[35][14]
V5_LVDSBIAS bit 4	MAIN[35][13]
V5_LVDSBIAS bit 5	MAIN[34][13]
V5_LVDSBIAS bit 6	MAIN[34][12]
V5_LVDSBIAS bit 7	MAIN[35][12]
V5_LVDSBIAS bit 8	MAIN[32][13]
V5_LVDSBIAS bit 9	MAIN[33][13]
V5_LVDSBIAS bit 10	MAIN[33][12]
V5_LVDSBIAS bit 11	MAIN[32][12]
INTERNAL_VREF	[enum: INTERNAL_VREF]

virtex5 HCLK_IO enum INTERNAL_VREF
BANK.INTERNAL_VREF	MAIN[39][15]	MAIN[38][15]	MAIN[38][13]	MAIN[38][12]	MAIN[39][12]
OFF	0	0	0	0	0
_750	0	0	0	1	1
_900	0	0	1	0	1
_1080	0	1	0	0	1
_1250	1	0	0	0	1

Bel wires

virtex5 HCLK_IO bel wires
Wire	Pins
CELL[0].IMUX_IMUX[0]	IDELAYCTRL.RST
CELL[0].OUT_BEL[8]	DCI.DCIIOUPDATE
CELL[0].OUT_BEL[15]	DCI.DCIREFIOUPDATE
CELL[0].OUT_BEL[20]	DCI.DCISCLK, DCI.DCIDONE
CELL[0].OUT_BEL[22]	DCI.DCIDATA
CELL[0].OUT_CLKPAD	BUFIO[2].I
CELL[1].IMUX_BYP_SITE[0]	DCI.TSTRST
CELL[1].IMUX_BYP_SITE[2]	DCI.TSTCLK
CELL[1].IMUX_BYP_SITE[3]	DCI.TSTHLP
CELL[1].IMUX_BYP_SITE[6]	DCI.TSTHLN
CELL[1].IMUX_IMUX[0]	BUFR[0].CLR
CELL[1].IMUX_IMUX[6]	BUFR[0].CE
CELL[1].OUT_BEL[8]	DCI.DCIADDRESS[0]
CELL[1].OUT_BEL[16]	IDELAYCTRL.OUTN65
CELL[1].OUT_BEL[17]	IDELAYCTRL.UPPULSEOUT
CELL[1].OUT_BEL[18]	IDELAYCTRL.DNPULSEOUT
CELL[1].OUT_BEL[20]	DCI.DCIADDRESS[1]
CELL[1].OUT_BEL[22]	IDELAYCTRL.RDY, DCI.DCIADDRESS[2]
CELL[1].OUT_BEL[23]	IDELAYCTRL.OUTN1
CELL[1].OUT_CLKPAD	BUFIO[3].I
CELL[2].IMUX_IMUX[0]	BUFR[1].CLR
CELL[2].IMUX_IMUX[6]	BUFR[1].CE
CELL[2].OUT_CLKPAD	BUFIO[0].I
CELL[2].IMUX_IDELAYCTRL_REFCLK	IDELAYCTRL.REFCLK
CELL[2].IMUX_BUFR[0]	BUFR[0].I
CELL[2].IMUX_BUFR[1]	BUFR[1].I
CELL[2].IOCLK[0]	BUFIO[0].O
CELL[2].IOCLK[1]	BUFIO[1].O
CELL[2].IOCLK[2]	BUFIO[2].O
CELL[2].IOCLK[3]	BUFIO[3].O
CELL[2].VRCLK[0]	BUFR[0].O
CELL[2].VRCLK[1]	BUFR[1].O
CELL[3].OUT_CLKPAD	BUFIO[1].I

Bitstream

virtex5 HCLK_IO rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	BUFR[1]: DIVIDE bit 1	HCLK_IO_INT: buffer CELL[2].RCLK_IO[3] ← CELL[2].RCLK_ROW[3]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 9	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 8	HCLK_IO_INT: mux CELL[2].RCLK_ROW[2] bit 3	HCLK_IO_INT: mux CELL[2].RCLK_ROW[2] bit 1	BUFR[1]: DIVIDE bit 0	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 1	BUFR[0]: DIVIDE bit 3	HCLK_IO_INT: mux CELL[2].RCLK_ROW[1] bit 3	HCLK_IO_INT: mux CELL[2].RCLK_ROW[0] bit 0	-	-	-	-	-	-	-	BUFR[1]: DIVIDE bit 2	-	HCLK_IO_INT: mux CELL[2].RCLK_ROW[0] bit 2	HCLK_IO_INT: mux CELL[2].RCLK_ROW[0] bit 1	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 2	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 3	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 5	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 4	BANK: V5_LVDSBIAS bit 1	BANK: V5_LVDSBIAS bit 0	-	-	BANK: INTERNAL_VREF bit 3	BANK: INTERNAL_VREF bit 4	-	-	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 3	DCI: V4_PMASK_TERM_SPLIT bit 4	DCI: V4_PMASK_TERM_VCC bit 0	DCI: V4_NMASK_TERM_SPLIT bit 4	DCI: PREF bit 3	DCI: V5_LVDIV2 bit 2
B14	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].RCLK_ROW[1] bit 2	HCLK_IO_INT: mux CELL[2].RCLK_ROW[1] bit 1	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 7	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 6	HCLK_IO_INT: mux CELL[2].RCLK_ROW[1] bit 0	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 0	BUFR[0]: DIVIDE bit 2	BUFR[0]: DIVIDE bit 1	BUFR[0]: DIVIDE bit 0	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 4	BUFR[1]: DIVIDE bit 3	HCLK_IO_INT: buffer CELL[2].HCLK_IO[9] ← CELL[2].HCLK_ROW[9]	HCLK_IO_INT: mux CELL[2].RCLK_ROW[0] bit 3	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 1	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 10	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 0	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 9	BANK: V5_LVDSBIAS bit 2	BANK: V5_LVDSBIAS bit 3	IDELAYCTRL: VCTL_SEL bit 1	IDELAYCTRL: DLL_ENABLE	-	-	-	-	-	-	-	-	DCI: ENABLE	DCI: CASCADE_FROM_ABOVE	DCI: QUIET	DCI: TEST_ENABLE bit 0	DCI: V4_PMASK_TERM_VCC bit 1	DCI: V4_PMASK_TERM_VCC bit 2	DCI: NREF bit 0	DCI: PREF bit 2
B13	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[0] ← CELL[2].RCLK_ROW[0]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 3	HCLK_IO_INT: buffer CELL[2].HCLK_IO[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[4] ← CELL[2].HCLK_ROW[4]	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 2	HCLK_IO_INT: mux CELL[2].RCLK_ROW[3] bit 3	HCLK_IO_INT: mux CELL[2].RCLK_ROW[2] bit 0	HCLK_IO_INT: mux CELL[2].RCLK_ROW[3] bit 0	HCLK_IO_INT: mux CELL[2].RCLK_ROW[3] bit 1	BUFIO[2]: ENABLE	BUFIO[1]: ENABLE	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 0	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 1	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 10	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 8	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 2	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 1	HCLK_IO_INT: buffer CELL[2].HCLK_IO[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[7] ← CELL[2].HCLK_ROW[7]	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 6	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 8	BANK: V5_LVDSBIAS bit 8	BANK: V5_LVDSBIAS bit 9	BANK: V5_LVDSBIAS bit 5	BANK: V5_LVDSBIAS bit 4	IDELAYCTRL: VCTL_SEL bit 0	-	BANK: INTERNAL_VREF bit 2	-	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 0	DCI: CASCADE_FROM_BELOW	DCI: V4_NMASK_TERM_SPLIT bit 0	DCI: V4_NMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_VCC bit 4	DCI: V4_PMASK_TERM_VCC bit 3	DCI: NREF bit 1	DCI: TEST_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	BUFR[1]: ENABLE	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 0	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 5	HCLK_IO_INT: buffer CELL[2].RCLK_IO[1] ← CELL[2].RCLK_ROW[1]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 5	BUFIO[3]: ENABLE	HCLK_IO_INT: buffer CELL[2].HCLK_IO[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[2] ← CELL[2].HCLK_ROW[2]	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 3	BUFIO[0]: ENABLE	HCLK_IO_INT: mux CELL[2].RCLK_ROW[3] bit 2	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 4	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 7	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 6	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[1] bit 9	-	HCLK_IO_INT: mux CELL[2].RCLK_ROW[2] bit 2	HCLK_IO_INT: buffer CELL[2].RCLK_IO[2] ← CELL[2].RCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[6] ← CELL[2].HCLK_ROW[6]	HCLK_IO_INT: mux CELL[2].IMUX_BUFR[0] bit 7	BUFR[0]: ENABLE	BANK: V5_LVDSBIAS bit 11	BANK: V5_LVDSBIAS bit 10	BANK: V5_LVDSBIAS bit 6	BANK: V5_LVDSBIAS bit 7	IDELAYCTRL: DELAY_ENABLE	-	BANK: INTERNAL_VREF bit 1	BANK: INTERNAL_VREF bit 0	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_SPLIT bit 2	DCI: V4_NMASK_TERM_SPLIT bit 3	DCI: V4_NMASK_TERM_SPLIT bit 2	DCI: PREF bit 1	DCI: PREF bit 0	DCI: V5_LVDIV2 bit 0	DCI: V5_LVDIV2 bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile HCLK_IO_CENTER

Cells: 4

Switchbox HCLK_IO_INT

virtex5 HCLK_IO_CENTER switchbox HCLK_IO_INT programmable buffers
Destination	Source	Bit
CELL[2].HCLK_IO[0]	CELL[2].HCLK_ROW[0]	MAIN[16][12]
CELL[2].HCLK_IO[1]	CELL[2].HCLK_ROW[1]	MAIN[15][12]
CELL[2].HCLK_IO[2]	CELL[2].HCLK_ROW[2]	MAIN[17][12]
CELL[2].HCLK_IO[3]	CELL[2].HCLK_ROW[3]	MAIN[11][13]
CELL[2].HCLK_IO[4]	CELL[2].HCLK_ROW[4]	MAIN[12][13]
CELL[2].HCLK_IO[5]	CELL[2].HCLK_ROW[5]	MAIN[28][12]
CELL[2].HCLK_IO[6]	CELL[2].HCLK_ROW[6]	MAIN[29][12]
CELL[2].HCLK_IO[7]	CELL[2].HCLK_ROW[7]	MAIN[29][13]
CELL[2].HCLK_IO[8]	CELL[2].HCLK_ROW[8]	MAIN[28][13]
CELL[2].HCLK_IO[9]	CELL[2].HCLK_ROW[9]	MAIN[28][14]
CELL[2].RCLK_IO[0]	CELL[2].RCLK_ROW[0]	MAIN[9][13]
CELL[2].RCLK_IO[1]	CELL[2].RCLK_ROW[1]	MAIN[12][12]
CELL[2].RCLK_IO[2]	CELL[2].RCLK_ROW[2]	MAIN[27][12]
CELL[2].RCLK_IO[3]	CELL[2].RCLK_ROW[3]	MAIN[9][15]

virtex5 HCLK_IO_CENTER switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
Bits										Destination
MAIN[10][15]	MAIN[11][15]	MAIN[12][14]	MAIN[13][14]	MAIN[13][12]	MAIN[26][14]	MAIN[10][13]	MAIN[26][13]	MAIN[27][13]	MAIN[10][12]	CELL[2].IMUX_IDELAYCTRL_REFCLK
										Source
0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	1	CELL[2].HCLK_IO[0]
0	0	0	0	0	0	0	0	1	0	CELL[2].HCLK_IO[1]
0	0	0	0	0	0	0	1	0	0	CELL[2].HCLK_IO[2]
0	0	0	0	0	0	1	0	0	0	CELL[2].HCLK_IO[3]
0	0	0	0	0	1	0	0	0	0	CELL[2].HCLK_IO[4]
0	0	0	0	1	0	0	0	0	0	CELL[2].HCLK_IO[5]
0	0	0	1	0	0	0	0	0	0	CELL[2].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	CELL[2].HCLK_IO[7]
0	1	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[8]
1	0	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[9]

virtex5 HCLK_IO_CENTER wire support CELL[2].RCLK_ROW[0]
Bit
MAIN[18][15]

virtex5 HCLK_IO_CENTER wire support CELL[2].RCLK_ROW[1]
Bit
MAIN[14][14]

virtex5 HCLK_IO_CENTER wire support CELL[2].RCLK_ROW[2]
Bit
MAIN[15][13]

virtex5 HCLK_IO_CENTER wire support CELL[2].RCLK_ROW[3]
Bit
MAIN[16][13]

virtex5 HCLK_IO_CENTER wire support CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]
Bit
MAIN[15][14]
MAIN[15][15]

Bels BUFIO

virtex5 HCLK_IO_CENTER bel BUFIO pins
Pin	Direction	BUFIO[0]	BUFIO[1]	BUFIO[2]	BUFIO[3]
I	in	CELL[2].OUT_CLKPAD	CELL[3].OUT_CLKPAD	CELL[0].OUT_CLKPAD	CELL[1].OUT_CLKPAD
O	out	CELL[2].IOCLK[0]	CELL[2].IOCLK[1]	CELL[2].IOCLK[2]	CELL[2].IOCLK[3]

virtex5 HCLK_IO_CENTER bel BUFIO attribute bits
Attribute	BUFIO[0]	BUFIO[1]	BUFIO[2]	BUFIO[3]
ENABLE	MAIN[19][12]	MAIN[19][13]	MAIN[18][13]	MAIN[14][12]

Bels IDELAYCTRL

virtex5 HCLK_IO_CENTER bel IDELAYCTRL pins
Pin	Direction	IDELAYCTRL
REFCLK	in	CELL[2].IMUX_IDELAYCTRL_REFCLK
RST	in	CELL[0].IMUX_IMUX[0]
RDY	out	CELL[1].OUT_BEL[22]
DNPULSEOUT	out	CELL[1].OUT_BEL[18]
UPPULSEOUT	out	CELL[1].OUT_BEL[17]
OUTN1	out	CELL[1].OUT_BEL[23]
OUTN65	out	CELL[1].OUT_BEL[16]

virtex5 HCLK_IO_CENTER bel IDELAYCTRL attribute bits
Attribute	IDELAYCTRL
DLL_ENABLE	MAIN[37][14]
DELAY_ENABLE	MAIN[36][12]
VCTL_SEL bit 0	MAIN[36][13]
VCTL_SEL bit 1	MAIN[36][14]

Bels DCI

virtex5 HCLK_IO_CENTER bel DCI pins
Pin	Direction	DCI
TSTCLK	in	CELL[1].IMUX_BYP_SITE[2]
TSTRST	in	CELL[1].IMUX_BYP_SITE[0]
TSTHLP	in	CELL[1].IMUX_BYP_SITE[3]
TSTHLN	in	CELL[1].IMUX_BYP_SITE[6]
DCISCLK	out	CELL[0].OUT_BEL[20]
DCIADDRESS[0]	out	CELL[1].OUT_BEL[8]
DCIADDRESS[1]	out	CELL[1].OUT_BEL[20]
DCIADDRESS[2]	out	CELL[1].OUT_BEL[22]
DCIDATA	out	CELL[0].OUT_BEL[22]
DCIIOUPDATE	out	CELL[0].OUT_BEL[8]
DCIREFIOUPDATE	out	CELL[0].OUT_BEL[15]
DCIDONE	out	CELL[0].OUT_BEL[20]

virtex5 HCLK_IO_CENTER bel DCI attribute bits
Attribute	DCI
ENABLE	MAIN[46][14]
QUIET	MAIN[48][14]
V5_LVDIV2 bit 0	MAIN[52][12]
V5_LVDIV2 bit 1	MAIN[53][12]
V5_LVDIV2 bit 2	MAIN[53][15]
V4_PMASK_TERM_VCC bit 0	MAIN[50][15]
V4_PMASK_TERM_VCC bit 1	MAIN[50][14]
V4_PMASK_TERM_VCC bit 2	MAIN[51][14]
V4_PMASK_TERM_VCC bit 3	MAIN[51][13]
V4_PMASK_TERM_VCC bit 4	MAIN[50][13]
V4_PMASK_TERM_SPLIT bit 0	MAIN[46][13]
V4_PMASK_TERM_SPLIT bit 1	MAIN[46][12]
V4_PMASK_TERM_SPLIT bit 2	MAIN[47][12]
V4_PMASK_TERM_SPLIT bit 3	MAIN[48][15]
V4_PMASK_TERM_SPLIT bit 4	MAIN[49][15]
V4_NMASK_TERM_SPLIT bit 0	MAIN[48][13]
V4_NMASK_TERM_SPLIT bit 1	MAIN[49][13]
V4_NMASK_TERM_SPLIT bit 2	MAIN[49][12]
V4_NMASK_TERM_SPLIT bit 3	MAIN[48][12]
V4_NMASK_TERM_SPLIT bit 4	MAIN[51][15]
NREF bit 0	MAIN[52][14]
NREF bit 1	MAIN[52][13]
PREF bit 0	MAIN[51][12]
PREF bit 1	MAIN[50][12]
PREF bit 2	MAIN[53][14]
PREF bit 3	MAIN[52][15]
TEST_ENABLE bit 0	MAIN[49][14]
TEST_ENABLE bit 1	MAIN[53][13]
CASCADE_FROM_ABOVE	MAIN[47][14]
CASCADE_FROM_BELOW	MAIN[47][13]

Bels BANK

virtex5 HCLK_IO_CENTER bel BANK pins
Pin	Direction	BANK

virtex5 HCLK_IO_CENTER bel BANK attribute bits
Attribute	BANK
V5_LVDSBIAS bit 0	MAIN[35][15]
V5_LVDSBIAS bit 1	MAIN[34][15]
V5_LVDSBIAS bit 2	MAIN[34][14]
V5_LVDSBIAS bit 3	MAIN[35][14]
V5_LVDSBIAS bit 4	MAIN[35][13]
V5_LVDSBIAS bit 5	MAIN[34][13]
V5_LVDSBIAS bit 6	MAIN[34][12]
V5_LVDSBIAS bit 7	MAIN[35][12]
V5_LVDSBIAS bit 8	MAIN[32][13]
V5_LVDSBIAS bit 9	MAIN[33][13]
V5_LVDSBIAS bit 10	MAIN[33][12]
V5_LVDSBIAS bit 11	MAIN[32][12]
INTERNAL_VREF	[enum: INTERNAL_VREF]

virtex5 HCLK_IO_CENTER enum INTERNAL_VREF
BANK.INTERNAL_VREF	MAIN[39][15]	MAIN[38][15]	MAIN[38][13]	MAIN[38][12]	MAIN[39][12]
OFF	0	0	0	0	0
_750	0	0	0	1	1
_900	0	0	1	0	1
_1080	0	1	0	0	1
_1250	1	0	0	0	1

Bel wires

virtex5 HCLK_IO_CENTER bel wires
Wire	Pins
CELL[0].IMUX_IMUX[0]	IDELAYCTRL.RST
CELL[0].OUT_BEL[8]	DCI.DCIIOUPDATE
CELL[0].OUT_BEL[15]	DCI.DCIREFIOUPDATE
CELL[0].OUT_BEL[20]	DCI.DCISCLK, DCI.DCIDONE
CELL[0].OUT_BEL[22]	DCI.DCIDATA
CELL[0].OUT_CLKPAD	BUFIO[2].I
CELL[1].IMUX_BYP_SITE[0]	DCI.TSTRST
CELL[1].IMUX_BYP_SITE[2]	DCI.TSTCLK
CELL[1].IMUX_BYP_SITE[3]	DCI.TSTHLP
CELL[1].IMUX_BYP_SITE[6]	DCI.TSTHLN
CELL[1].OUT_BEL[8]	DCI.DCIADDRESS[0]
CELL[1].OUT_BEL[16]	IDELAYCTRL.OUTN65
CELL[1].OUT_BEL[17]	IDELAYCTRL.UPPULSEOUT
CELL[1].OUT_BEL[18]	IDELAYCTRL.DNPULSEOUT
CELL[1].OUT_BEL[20]	DCI.DCIADDRESS[1]
CELL[1].OUT_BEL[22]	IDELAYCTRL.RDY, DCI.DCIADDRESS[2]
CELL[1].OUT_BEL[23]	IDELAYCTRL.OUTN1
CELL[1].OUT_CLKPAD	BUFIO[3].I
CELL[2].OUT_CLKPAD	BUFIO[0].I
CELL[2].IMUX_IDELAYCTRL_REFCLK	IDELAYCTRL.REFCLK
CELL[2].IOCLK[0]	BUFIO[0].O
CELL[2].IOCLK[1]	BUFIO[1].O
CELL[2].IOCLK[2]	BUFIO[2].O
CELL[2].IOCLK[3]	BUFIO[3].O
CELL[3].OUT_CLKPAD	BUFIO[1].I

Bitstream

virtex5 HCLK_IO_CENTER rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[3] ← CELL[2].RCLK_ROW[3]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 9	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 8	-	-	-	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 1	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[0]) bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BANK: V5_LVDSBIAS bit 1	BANK: V5_LVDSBIAS bit 0	-	-	BANK: INTERNAL_VREF bit 3	BANK: INTERNAL_VREF bit 4	-	-	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 3	DCI: V4_PMASK_TERM_SPLIT bit 4	DCI: V4_PMASK_TERM_VCC bit 0	DCI: V4_NMASK_TERM_SPLIT bit 4	DCI: PREF bit 3	DCI: V5_LVDIV2 bit 2
B14	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 7	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 6	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[1]) bit 0	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 0	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 4	-	HCLK_IO_INT: buffer CELL[2].HCLK_IO[9] ← CELL[2].HCLK_ROW[9]	-	-	-	-	-	BANK: V5_LVDSBIAS bit 2	BANK: V5_LVDSBIAS bit 3	IDELAYCTRL: VCTL_SEL bit 1	IDELAYCTRL: DLL_ENABLE	-	-	-	-	-	-	-	-	DCI: ENABLE	DCI: CASCADE_FROM_ABOVE	DCI: QUIET	DCI: TEST_ENABLE bit 0	DCI: V4_PMASK_TERM_VCC bit 1	DCI: V4_PMASK_TERM_VCC bit 2	DCI: NREF bit 0	DCI: PREF bit 2
B13	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[0] ← CELL[2].RCLK_ROW[0]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 3	HCLK_IO_INT: buffer CELL[2].HCLK_IO[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[4] ← CELL[2].HCLK_ROW[4]	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[2]) bit 0	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[3]) bit 0	-	BUFIO[2]: ENABLE	BUFIO[1]: ENABLE	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 2	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 1	HCLK_IO_INT: buffer CELL[2].HCLK_IO[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[7] ← CELL[2].HCLK_ROW[7]	-	-	BANK: V5_LVDSBIAS bit 8	BANK: V5_LVDSBIAS bit 9	BANK: V5_LVDSBIAS bit 5	BANK: V5_LVDSBIAS bit 4	IDELAYCTRL: VCTL_SEL bit 0	-	BANK: INTERNAL_VREF bit 2	-	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 0	DCI: CASCADE_FROM_BELOW	DCI: V4_NMASK_TERM_SPLIT bit 0	DCI: V4_NMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_VCC bit 4	DCI: V4_PMASK_TERM_VCC bit 3	DCI: NREF bit 1	DCI: TEST_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 0	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[1] ← CELL[2].RCLK_ROW[1]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 5	BUFIO[3]: ENABLE	HCLK_IO_INT: buffer CELL[2].HCLK_IO[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[2] ← CELL[2].HCLK_ROW[2]	-	BUFIO[0]: ENABLE	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[2] ← CELL[2].RCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[6] ← CELL[2].HCLK_ROW[6]	-	-	BANK: V5_LVDSBIAS bit 11	BANK: V5_LVDSBIAS bit 10	BANK: V5_LVDSBIAS bit 6	BANK: V5_LVDSBIAS bit 7	IDELAYCTRL: DELAY_ENABLE	-	BANK: INTERNAL_VREF bit 1	BANK: INTERNAL_VREF bit 0	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_SPLIT bit 2	DCI: V4_NMASK_TERM_SPLIT bit 3	DCI: V4_NMASK_TERM_SPLIT bit 2	DCI: PREF bit 1	DCI: PREF bit 0	DCI: V5_LVDIV2 bit 0	DCI: V5_LVDIV2 bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile HCLK_IO_CFG_S

Cells: 4

Switchbox HCLK_IO_INT

virtex5 HCLK_IO_CFG_S switchbox HCLK_IO_INT programmable buffers
Destination	Source	Bit
CELL[2].HCLK_IO[0]	CELL[2].HCLK_ROW[0]	MAIN[16][12]
CELL[2].HCLK_IO[1]	CELL[2].HCLK_ROW[1]	MAIN[15][12]
CELL[2].HCLK_IO[2]	CELL[2].HCLK_ROW[2]	MAIN[17][12]
CELL[2].HCLK_IO[3]	CELL[2].HCLK_ROW[3]	MAIN[11][13]
CELL[2].HCLK_IO[4]	CELL[2].HCLK_ROW[4]	MAIN[12][13]
CELL[2].HCLK_IO[5]	CELL[2].HCLK_ROW[5]	MAIN[28][12]
CELL[2].HCLK_IO[6]	CELL[2].HCLK_ROW[6]	MAIN[29][12]
CELL[2].HCLK_IO[7]	CELL[2].HCLK_ROW[7]	MAIN[29][13]
CELL[2].HCLK_IO[8]	CELL[2].HCLK_ROW[8]	MAIN[28][13]
CELL[2].HCLK_IO[9]	CELL[2].HCLK_ROW[9]	MAIN[28][14]
CELL[2].RCLK_IO[0]	CELL[2].RCLK_ROW[0]	MAIN[9][13]
CELL[2].RCLK_IO[1]	CELL[2].RCLK_ROW[1]	MAIN[12][12]
CELL[2].RCLK_IO[2]	CELL[2].RCLK_ROW[2]	MAIN[27][12]
CELL[2].RCLK_IO[3]	CELL[2].RCLK_ROW[3]	MAIN[9][15]

virtex5 HCLK_IO_CFG_S switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
Bits										Destination
MAIN[10][15]	MAIN[11][15]	MAIN[12][14]	MAIN[13][14]	MAIN[13][12]	MAIN[26][14]	MAIN[10][13]	MAIN[26][13]	MAIN[27][13]	MAIN[10][12]	CELL[2].IMUX_IDELAYCTRL_REFCLK
										Source
0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	1	CELL[2].HCLK_IO[0]
0	0	0	0	0	0	0	0	1	0	CELL[2].HCLK_IO[1]
0	0	0	0	0	0	0	1	0	0	CELL[2].HCLK_IO[2]
0	0	0	0	0	0	1	0	0	0	CELL[2].HCLK_IO[3]
0	0	0	0	0	1	0	0	0	0	CELL[2].HCLK_IO[4]
0	0	0	0	1	0	0	0	0	0	CELL[2].HCLK_IO[5]
0	0	0	1	0	0	0	0	0	0	CELL[2].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	CELL[2].HCLK_IO[7]
0	1	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[8]
1	0	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[9]

virtex5 HCLK_IO_CFG_S wire support CELL[2].RCLK_ROW[0]
Bit
MAIN[18][15]

virtex5 HCLK_IO_CFG_S wire support CELL[2].RCLK_ROW[1]
Bit
MAIN[14][14]

virtex5 HCLK_IO_CFG_S wire support CELL[2].RCLK_ROW[2]
Bit
MAIN[15][13]

virtex5 HCLK_IO_CFG_S wire support CELL[2].RCLK_ROW[3]
Bit
MAIN[16][13]

virtex5 HCLK_IO_CFG_S wire support CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]
Bit
MAIN[15][14]
MAIN[15][15]

Bels BUFIO

virtex5 HCLK_IO_CFG_S bel BUFIO pins
Pin	Direction	BUFIO[2]	BUFIO[3]
I	in	CELL[0].OUT_CLKPAD	CELL[1].OUT_CLKPAD
O	out	CELL[2].IOCLK[2]	CELL[2].IOCLK[3]

virtex5 HCLK_IO_CFG_S bel BUFIO attribute bits
Attribute	BUFIO[2]	BUFIO[3]
ENABLE	MAIN[18][13]	MAIN[14][12]

Bels IDELAYCTRL

virtex5 HCLK_IO_CFG_S bel IDELAYCTRL pins
Pin	Direction	IDELAYCTRL
REFCLK	in	CELL[2].IMUX_IDELAYCTRL_REFCLK
RST	in	CELL[0].IMUX_IMUX[0]
RDY	out	CELL[1].OUT_BEL[22]
DNPULSEOUT	out	CELL[1].OUT_BEL[18]
UPPULSEOUT	out	CELL[1].OUT_BEL[17]
OUTN1	out	CELL[1].OUT_BEL[23]
OUTN65	out	CELL[1].OUT_BEL[16]

virtex5 HCLK_IO_CFG_S bel IDELAYCTRL attribute bits
Attribute	IDELAYCTRL
DLL_ENABLE	MAIN[37][14]
DELAY_ENABLE	MAIN[36][12]
VCTL_SEL bit 0	MAIN[36][13]
VCTL_SEL bit 1	MAIN[36][14]

Bels DCI

virtex5 HCLK_IO_CFG_S bel DCI pins
Pin	Direction	DCI
TSTCLK	in	CELL[1].IMUX_BYP_SITE[2]
TSTRST	in	CELL[1].IMUX_BYP_SITE[0]
TSTHLP	in	CELL[1].IMUX_BYP_SITE[3]
TSTHLN	in	CELL[1].IMUX_BYP_SITE[6]
DCISCLK	out	CELL[0].OUT_BEL[20]
DCIADDRESS[0]	out	CELL[1].OUT_BEL[8]
DCIADDRESS[1]	out	CELL[1].OUT_BEL[20]
DCIADDRESS[2]	out	CELL[1].OUT_BEL[22]
DCIDATA	out	CELL[0].OUT_BEL[22]
DCIIOUPDATE	out	CELL[0].OUT_BEL[8]
DCIREFIOUPDATE	out	CELL[0].OUT_BEL[15]
DCIDONE	out	CELL[0].OUT_BEL[20]

virtex5 HCLK_IO_CFG_S bel DCI attribute bits
Attribute	DCI
ENABLE	MAIN[46][14]
QUIET	MAIN[48][14]
V5_LVDIV2 bit 0	MAIN[52][12]
V5_LVDIV2 bit 1	MAIN[53][12]
V5_LVDIV2 bit 2	MAIN[53][15]
V4_PMASK_TERM_VCC bit 0	MAIN[50][15]
V4_PMASK_TERM_VCC bit 1	MAIN[50][14]
V4_PMASK_TERM_VCC bit 2	MAIN[51][14]
V4_PMASK_TERM_VCC bit 3	MAIN[51][13]
V4_PMASK_TERM_VCC bit 4	MAIN[50][13]
V4_PMASK_TERM_SPLIT bit 0	MAIN[46][13]
V4_PMASK_TERM_SPLIT bit 1	MAIN[46][12]
V4_PMASK_TERM_SPLIT bit 2	MAIN[47][12]
V4_PMASK_TERM_SPLIT bit 3	MAIN[48][15]
V4_PMASK_TERM_SPLIT bit 4	MAIN[49][15]
V4_NMASK_TERM_SPLIT bit 0	MAIN[48][13]
V4_NMASK_TERM_SPLIT bit 1	MAIN[49][13]
V4_NMASK_TERM_SPLIT bit 2	MAIN[49][12]
V4_NMASK_TERM_SPLIT bit 3	MAIN[48][12]
V4_NMASK_TERM_SPLIT bit 4	MAIN[51][15]
NREF bit 0	MAIN[52][14]
NREF bit 1	MAIN[52][13]
PREF bit 0	MAIN[51][12]
PREF bit 1	MAIN[50][12]
PREF bit 2	MAIN[53][14]
PREF bit 3	MAIN[52][15]
TEST_ENABLE bit 0	MAIN[49][14]
TEST_ENABLE bit 1	MAIN[53][13]
CASCADE_FROM_ABOVE	MAIN[47][14]
CASCADE_FROM_BELOW	MAIN[47][13]

Bels BANK

virtex5 HCLK_IO_CFG_S bel BANK pins
Pin	Direction	BANK

virtex5 HCLK_IO_CFG_S bel BANK attribute bits
Attribute	BANK
V5_LVDSBIAS bit 0	MAIN[35][15]
V5_LVDSBIAS bit 1	MAIN[34][15]
V5_LVDSBIAS bit 2	MAIN[34][14]
V5_LVDSBIAS bit 3	MAIN[35][14]
V5_LVDSBIAS bit 4	MAIN[35][13]
V5_LVDSBIAS bit 5	MAIN[34][13]
V5_LVDSBIAS bit 6	MAIN[34][12]
V5_LVDSBIAS bit 7	MAIN[35][12]
V5_LVDSBIAS bit 8	MAIN[32][13]
V5_LVDSBIAS bit 9	MAIN[33][13]
V5_LVDSBIAS bit 10	MAIN[33][12]
V5_LVDSBIAS bit 11	MAIN[32][12]
INTERNAL_VREF	[enum: INTERNAL_VREF]

virtex5 HCLK_IO_CFG_S enum INTERNAL_VREF
BANK.INTERNAL_VREF	MAIN[39][15]	MAIN[38][15]	MAIN[38][13]	MAIN[38][12]	MAIN[39][12]
OFF	0	0	0	0	0
_750	0	0	0	1	1
_900	0	0	1	0	1
_1080	0	1	0	0	1
_1250	1	0	0	0	1

Bel wires

virtex5 HCLK_IO_CFG_S bel wires
Wire	Pins
CELL[0].IMUX_IMUX[0]	IDELAYCTRL.RST
CELL[0].OUT_BEL[8]	DCI.DCIIOUPDATE
CELL[0].OUT_BEL[15]	DCI.DCIREFIOUPDATE
CELL[0].OUT_BEL[20]	DCI.DCISCLK, DCI.DCIDONE
CELL[0].OUT_BEL[22]	DCI.DCIDATA
CELL[0].OUT_CLKPAD	BUFIO[2].I
CELL[1].IMUX_BYP_SITE[0]	DCI.TSTRST
CELL[1].IMUX_BYP_SITE[2]	DCI.TSTCLK
CELL[1].IMUX_BYP_SITE[3]	DCI.TSTHLP
CELL[1].IMUX_BYP_SITE[6]	DCI.TSTHLN
CELL[1].OUT_BEL[8]	DCI.DCIADDRESS[0]
CELL[1].OUT_BEL[16]	IDELAYCTRL.OUTN65
CELL[1].OUT_BEL[17]	IDELAYCTRL.UPPULSEOUT
CELL[1].OUT_BEL[18]	IDELAYCTRL.DNPULSEOUT
CELL[1].OUT_BEL[20]	DCI.DCIADDRESS[1]
CELL[1].OUT_BEL[22]	IDELAYCTRL.RDY, DCI.DCIADDRESS[2]
CELL[1].OUT_BEL[23]	IDELAYCTRL.OUTN1
CELL[1].OUT_CLKPAD	BUFIO[3].I
CELL[2].IMUX_IDELAYCTRL_REFCLK	IDELAYCTRL.REFCLK
CELL[2].IOCLK[2]	BUFIO[2].O
CELL[2].IOCLK[3]	BUFIO[3].O

Bitstream

virtex5 HCLK_IO_CFG_S rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[3] ← CELL[2].RCLK_ROW[3]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 9	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 8	-	-	-	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 1	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[0]) bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BANK: V5_LVDSBIAS bit 1	BANK: V5_LVDSBIAS bit 0	-	-	BANK: INTERNAL_VREF bit 3	BANK: INTERNAL_VREF bit 4	-	-	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 3	DCI: V4_PMASK_TERM_SPLIT bit 4	DCI: V4_PMASK_TERM_VCC bit 0	DCI: V4_NMASK_TERM_SPLIT bit 4	DCI: PREF bit 3	DCI: V5_LVDIV2 bit 2
B14	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 7	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 6	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[1]) bit 0	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 0	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 4	-	HCLK_IO_INT: buffer CELL[2].HCLK_IO[9] ← CELL[2].HCLK_ROW[9]	-	-	-	-	-	BANK: V5_LVDSBIAS bit 2	BANK: V5_LVDSBIAS bit 3	IDELAYCTRL: VCTL_SEL bit 1	IDELAYCTRL: DLL_ENABLE	-	-	-	-	-	-	-	-	DCI: ENABLE	DCI: CASCADE_FROM_ABOVE	DCI: QUIET	DCI: TEST_ENABLE bit 0	DCI: V4_PMASK_TERM_VCC bit 1	DCI: V4_PMASK_TERM_VCC bit 2	DCI: NREF bit 0	DCI: PREF bit 2
B13	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[0] ← CELL[2].RCLK_ROW[0]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 3	HCLK_IO_INT: buffer CELL[2].HCLK_IO[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[4] ← CELL[2].HCLK_ROW[4]	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[2]) bit 0	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[3]) bit 0	-	BUFIO[2]: ENABLE	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 2	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 1	HCLK_IO_INT: buffer CELL[2].HCLK_IO[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[7] ← CELL[2].HCLK_ROW[7]	-	-	BANK: V5_LVDSBIAS bit 8	BANK: V5_LVDSBIAS bit 9	BANK: V5_LVDSBIAS bit 5	BANK: V5_LVDSBIAS bit 4	IDELAYCTRL: VCTL_SEL bit 0	-	BANK: INTERNAL_VREF bit 2	-	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 0	DCI: CASCADE_FROM_BELOW	DCI: V4_NMASK_TERM_SPLIT bit 0	DCI: V4_NMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_VCC bit 4	DCI: V4_PMASK_TERM_VCC bit 3	DCI: NREF bit 1	DCI: TEST_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 0	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[1] ← CELL[2].RCLK_ROW[1]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 5	BUFIO[3]: ENABLE	HCLK_IO_INT: buffer CELL[2].HCLK_IO[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[2] ← CELL[2].HCLK_ROW[2]	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[2] ← CELL[2].RCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[6] ← CELL[2].HCLK_ROW[6]	-	-	BANK: V5_LVDSBIAS bit 11	BANK: V5_LVDSBIAS bit 10	BANK: V5_LVDSBIAS bit 6	BANK: V5_LVDSBIAS bit 7	IDELAYCTRL: DELAY_ENABLE	-	BANK: INTERNAL_VREF bit 1	BANK: INTERNAL_VREF bit 0	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_SPLIT bit 2	DCI: V4_NMASK_TERM_SPLIT bit 3	DCI: V4_NMASK_TERM_SPLIT bit 2	DCI: PREF bit 1	DCI: PREF bit 0	DCI: V5_LVDIV2 bit 0	DCI: V5_LVDIV2 bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile HCLK_IO_CFG_N

Cells: 4

Switchbox HCLK_IO_INT

virtex5 HCLK_IO_CFG_N switchbox HCLK_IO_INT programmable buffers
Destination	Source	Bit
CELL[2].HCLK_IO[0]	CELL[2].HCLK_ROW[0]	MAIN[16][12]
CELL[2].HCLK_IO[1]	CELL[2].HCLK_ROW[1]	MAIN[15][12]
CELL[2].HCLK_IO[2]	CELL[2].HCLK_ROW[2]	MAIN[17][12]
CELL[2].HCLK_IO[3]	CELL[2].HCLK_ROW[3]	MAIN[11][13]
CELL[2].HCLK_IO[4]	CELL[2].HCLK_ROW[4]	MAIN[12][13]
CELL[2].HCLK_IO[5]	CELL[2].HCLK_ROW[5]	MAIN[28][12]
CELL[2].HCLK_IO[6]	CELL[2].HCLK_ROW[6]	MAIN[29][12]
CELL[2].HCLK_IO[7]	CELL[2].HCLK_ROW[7]	MAIN[29][13]
CELL[2].HCLK_IO[8]	CELL[2].HCLK_ROW[8]	MAIN[28][13]
CELL[2].HCLK_IO[9]	CELL[2].HCLK_ROW[9]	MAIN[28][14]
CELL[2].RCLK_IO[0]	CELL[2].RCLK_ROW[0]	MAIN[9][13]
CELL[2].RCLK_IO[1]	CELL[2].RCLK_ROW[1]	MAIN[12][12]
CELL[2].RCLK_IO[2]	CELL[2].RCLK_ROW[2]	MAIN[27][12]
CELL[2].RCLK_IO[3]	CELL[2].RCLK_ROW[3]	MAIN[9][15]

virtex5 HCLK_IO_CFG_N switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
Bits										Destination
MAIN[10][15]	MAIN[11][15]	MAIN[12][14]	MAIN[13][14]	MAIN[13][12]	MAIN[26][14]	MAIN[10][13]	MAIN[26][13]	MAIN[27][13]	MAIN[10][12]	CELL[2].IMUX_IDELAYCTRL_REFCLK
										Source
0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	1	CELL[2].HCLK_IO[0]
0	0	0	0	0	0	0	0	1	0	CELL[2].HCLK_IO[1]
0	0	0	0	0	0	0	1	0	0	CELL[2].HCLK_IO[2]
0	0	0	0	0	0	1	0	0	0	CELL[2].HCLK_IO[3]
0	0	0	0	0	1	0	0	0	0	CELL[2].HCLK_IO[4]
0	0	0	0	1	0	0	0	0	0	CELL[2].HCLK_IO[5]
0	0	0	1	0	0	0	0	0	0	CELL[2].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	CELL[2].HCLK_IO[7]
0	1	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[8]
1	0	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[9]

virtex5 HCLK_IO_CFG_N wire support CELL[2].RCLK_ROW[0]
Bit
MAIN[18][15]

virtex5 HCLK_IO_CFG_N wire support CELL[2].RCLK_ROW[1]
Bit
MAIN[14][14]

virtex5 HCLK_IO_CFG_N wire support CELL[2].RCLK_ROW[2]
Bit
MAIN[15][13]

virtex5 HCLK_IO_CFG_N wire support CELL[2].RCLK_ROW[3]
Bit
MAIN[16][13]

virtex5 HCLK_IO_CFG_N wire support CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]
Bit
MAIN[15][14]
MAIN[15][15]

Bels HCLK_CMT_DRP

virtex5 HCLK_IO_CFG_N bel HCLK_CMT_DRP pins
Pin	Direction	HCLK_CMT_DRP

virtex5 HCLK_IO_CFG_N bel HCLK_CMT_DRP attribute bits
Attribute	HCLK_CMT_DRP
DRP_MASK	MAIN[27][15]

Bels BUFIO

virtex5 HCLK_IO_CFG_N bel BUFIO pins
Pin	Direction	BUFIO[0]	BUFIO[1]
I	in	CELL[2].OUT_CLKPAD	CELL[3].OUT_CLKPAD
O	out	CELL[2].IOCLK[0]	CELL[2].IOCLK[1]

virtex5 HCLK_IO_CFG_N bel BUFIO attribute bits
Attribute	BUFIO[0]	BUFIO[1]
ENABLE	MAIN[19][12]	MAIN[19][13]

Bels IDELAYCTRL

virtex5 HCLK_IO_CFG_N bel IDELAYCTRL pins
Pin	Direction	IDELAYCTRL
REFCLK	in	CELL[2].IMUX_IDELAYCTRL_REFCLK
RST	in	CELL[3].IMUX_IMUX[6]
RDY	out	CELL[2].OUT_BEL[22]
DNPULSEOUT	out	CELL[2].OUT_BEL[23]
UPPULSEOUT	out	CELL[2].OUT_BEL[15]
OUTN1	out	CELL[2].OUT_BEL[20]
OUTN65	out	CELL[2].OUT_BEL[8]

virtex5 HCLK_IO_CFG_N bel IDELAYCTRL attribute bits
Attribute	IDELAYCTRL
DLL_ENABLE	MAIN[37][14]
DELAY_ENABLE	MAIN[36][12]
VCTL_SEL bit 0	MAIN[36][13]
VCTL_SEL bit 1	MAIN[36][14]

Bels DCI

virtex5 HCLK_IO_CFG_N bel DCI pins
Pin	Direction	DCI
TSTCLK	in	CELL[2].IMUX_BYP_SITE[2]
TSTRST	in	CELL[2].IMUX_BYP_SITE[0]
TSTHLP	in	CELL[2].IMUX_BYP_SITE[3]
TSTHLN	in	CELL[2].IMUX_BYP_SITE[6]
DCISCLK	out	CELL[2].OUT_BEL[20]
DCIADDRESS[0]	out	CELL[2].OUT_BEL[8]
DCIADDRESS[1]	out	CELL[2].OUT_BEL[20]
DCIADDRESS[2]	out	CELL[2].OUT_BEL[22]
DCIDATA	out	CELL[2].OUT_BEL[22]
DCIIOUPDATE	out	CELL[2].OUT_BEL[8]
DCIREFIOUPDATE	out	CELL[2].OUT_BEL[15]
DCIDONE	out	CELL[2].OUT_BEL[20]

virtex5 HCLK_IO_CFG_N bel DCI attribute bits
Attribute	DCI
ENABLE	MAIN[46][14]
QUIET	MAIN[48][14]
V5_LVDIV2 bit 0	MAIN[52][12]
V5_LVDIV2 bit 1	MAIN[53][12]
V5_LVDIV2 bit 2	MAIN[53][15]
V4_PMASK_TERM_VCC bit 0	MAIN[50][15]
V4_PMASK_TERM_VCC bit 1	MAIN[50][14]
V4_PMASK_TERM_VCC bit 2	MAIN[51][14]
V4_PMASK_TERM_VCC bit 3	MAIN[51][13]
V4_PMASK_TERM_VCC bit 4	MAIN[50][13]
V4_PMASK_TERM_SPLIT bit 0	MAIN[46][13]
V4_PMASK_TERM_SPLIT bit 1	MAIN[46][12]
V4_PMASK_TERM_SPLIT bit 2	MAIN[47][12]
V4_PMASK_TERM_SPLIT bit 3	MAIN[48][15]
V4_PMASK_TERM_SPLIT bit 4	MAIN[49][15]
V4_NMASK_TERM_SPLIT bit 0	MAIN[48][13]
V4_NMASK_TERM_SPLIT bit 1	MAIN[49][13]
V4_NMASK_TERM_SPLIT bit 2	MAIN[49][12]
V4_NMASK_TERM_SPLIT bit 3	MAIN[48][12]
V4_NMASK_TERM_SPLIT bit 4	MAIN[51][15]
NREF bit 0	MAIN[52][14]
NREF bit 1	MAIN[52][13]
PREF bit 0	MAIN[51][12]
PREF bit 1	MAIN[50][12]
PREF bit 2	MAIN[53][14]
PREF bit 3	MAIN[52][15]
TEST_ENABLE bit 0	MAIN[49][14]
TEST_ENABLE bit 1	MAIN[53][13]
CASCADE_FROM_ABOVE	MAIN[47][14]
CASCADE_FROM_BELOW	MAIN[47][13]

Bels BANK

virtex5 HCLK_IO_CFG_N bel BANK pins
Pin	Direction	BANK

virtex5 HCLK_IO_CFG_N bel BANK attribute bits
Attribute	BANK
V5_LVDSBIAS bit 0	MAIN[35][15]
V5_LVDSBIAS bit 1	MAIN[34][15]
V5_LVDSBIAS bit 2	MAIN[34][14]
V5_LVDSBIAS bit 3	MAIN[35][14]
V5_LVDSBIAS bit 4	MAIN[35][13]
V5_LVDSBIAS bit 5	MAIN[34][13]
V5_LVDSBIAS bit 6	MAIN[34][12]
V5_LVDSBIAS bit 7	MAIN[35][12]
V5_LVDSBIAS bit 8	MAIN[32][13]
V5_LVDSBIAS bit 9	MAIN[33][13]
V5_LVDSBIAS bit 10	MAIN[33][12]
V5_LVDSBIAS bit 11	MAIN[32][12]
INTERNAL_VREF	[enum: INTERNAL_VREF]

virtex5 HCLK_IO_CFG_N enum INTERNAL_VREF
BANK.INTERNAL_VREF	MAIN[39][15]	MAIN[38][15]	MAIN[38][13]	MAIN[38][12]	MAIN[39][12]
OFF	0	0	0	0	0
_750	0	0	0	1	1
_900	0	0	1	0	1
_1080	0	1	0	0	1
_1250	1	0	0	0	1

Bel wires

virtex5 HCLK_IO_CFG_N bel wires
Wire	Pins
CELL[2].IMUX_BYP_SITE[0]	DCI.TSTRST
CELL[2].IMUX_BYP_SITE[2]	DCI.TSTCLK
CELL[2].IMUX_BYP_SITE[3]	DCI.TSTHLP
CELL[2].IMUX_BYP_SITE[6]	DCI.TSTHLN
CELL[2].OUT_BEL[8]	IDELAYCTRL.OUTN65, DCI.DCIADDRESS[0], DCI.DCIIOUPDATE
CELL[2].OUT_BEL[15]	IDELAYCTRL.UPPULSEOUT, DCI.DCIREFIOUPDATE
CELL[2].OUT_BEL[20]	IDELAYCTRL.OUTN1, DCI.DCISCLK, DCI.DCIADDRESS[1], DCI.DCIDONE
CELL[2].OUT_BEL[22]	IDELAYCTRL.RDY, DCI.DCIADDRESS[2], DCI.DCIDATA
CELL[2].OUT_BEL[23]	IDELAYCTRL.DNPULSEOUT
CELL[2].OUT_CLKPAD	BUFIO[0].I
CELL[2].IMUX_IDELAYCTRL_REFCLK	IDELAYCTRL.REFCLK
CELL[2].IOCLK[0]	BUFIO[0].O
CELL[2].IOCLK[1]	BUFIO[1].O
CELL[3].IMUX_IMUX[6]	IDELAYCTRL.RST
CELL[3].OUT_CLKPAD	BUFIO[1].I

Bitstream

virtex5 HCLK_IO_CFG_N rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[3] ← CELL[2].RCLK_ROW[3]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 9	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 8	-	-	-	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 1	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[0]) bit 0	-	-	-	-	-	-	-	-	HCLK_CMT_DRP: DRP_MASK	-	-	-	-	-	-	BANK: V5_LVDSBIAS bit 1	BANK: V5_LVDSBIAS bit 0	-	-	BANK: INTERNAL_VREF bit 3	BANK: INTERNAL_VREF bit 4	-	-	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 3	DCI: V4_PMASK_TERM_SPLIT bit 4	DCI: V4_PMASK_TERM_VCC bit 0	DCI: V4_NMASK_TERM_SPLIT bit 4	DCI: PREF bit 3	DCI: V5_LVDIV2 bit 2
B14	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 7	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 6	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[1]) bit 0	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 0	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 4	-	HCLK_IO_INT: buffer CELL[2].HCLK_IO[9] ← CELL[2].HCLK_ROW[9]	-	-	-	-	-	BANK: V5_LVDSBIAS bit 2	BANK: V5_LVDSBIAS bit 3	IDELAYCTRL: VCTL_SEL bit 1	IDELAYCTRL: DLL_ENABLE	-	-	-	-	-	-	-	-	DCI: ENABLE	DCI: CASCADE_FROM_ABOVE	DCI: QUIET	DCI: TEST_ENABLE bit 0	DCI: V4_PMASK_TERM_VCC bit 1	DCI: V4_PMASK_TERM_VCC bit 2	DCI: NREF bit 0	DCI: PREF bit 2
B13	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[0] ← CELL[2].RCLK_ROW[0]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 3	HCLK_IO_INT: buffer CELL[2].HCLK_IO[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[4] ← CELL[2].HCLK_ROW[4]	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[2]) bit 0	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[3]) bit 0	-	-	BUFIO[1]: ENABLE	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 2	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 1	HCLK_IO_INT: buffer CELL[2].HCLK_IO[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[7] ← CELL[2].HCLK_ROW[7]	-	-	BANK: V5_LVDSBIAS bit 8	BANK: V5_LVDSBIAS bit 9	BANK: V5_LVDSBIAS bit 5	BANK: V5_LVDSBIAS bit 4	IDELAYCTRL: VCTL_SEL bit 0	-	BANK: INTERNAL_VREF bit 2	-	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 0	DCI: CASCADE_FROM_BELOW	DCI: V4_NMASK_TERM_SPLIT bit 0	DCI: V4_NMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_VCC bit 4	DCI: V4_PMASK_TERM_VCC bit 3	DCI: NREF bit 1	DCI: TEST_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 0	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[1] ← CELL[2].RCLK_ROW[1]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 5	-	HCLK_IO_INT: buffer CELL[2].HCLK_IO[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[2] ← CELL[2].HCLK_ROW[2]	-	BUFIO[0]: ENABLE	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[2] ← CELL[2].RCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[6] ← CELL[2].HCLK_ROW[6]	-	-	BANK: V5_LVDSBIAS bit 11	BANK: V5_LVDSBIAS bit 10	BANK: V5_LVDSBIAS bit 6	BANK: V5_LVDSBIAS bit 7	IDELAYCTRL: DELAY_ENABLE	-	BANK: INTERNAL_VREF bit 1	BANK: INTERNAL_VREF bit 0	-	-	-	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_SPLIT bit 2	DCI: V4_NMASK_TERM_SPLIT bit 3	DCI: V4_NMASK_TERM_SPLIT bit 2	DCI: PREF bit 1	DCI: PREF bit 0	DCI: V5_LVDIV2 bit 0	DCI: V5_LVDIV2 bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile HCLK_IO_CMT_S

Cells: 4

Switchbox HCLK_IO_INT

virtex5 HCLK_IO_CMT_S switchbox HCLK_IO_INT programmable buffers
Destination	Source	Bit
CELL[2].HCLK_IO[0]	CELL[2].HCLK_ROW[0]	MAIN[16][12]
CELL[2].HCLK_IO[1]	CELL[2].HCLK_ROW[1]	MAIN[15][12]
CELL[2].HCLK_IO[2]	CELL[2].HCLK_ROW[2]	MAIN[17][12]
CELL[2].HCLK_IO[3]	CELL[2].HCLK_ROW[3]	MAIN[11][13]
CELL[2].HCLK_IO[4]	CELL[2].HCLK_ROW[4]	MAIN[12][13]
CELL[2].HCLK_IO[5]	CELL[2].HCLK_ROW[5]	MAIN[28][12]
CELL[2].HCLK_IO[6]	CELL[2].HCLK_ROW[6]	MAIN[29][12]
CELL[2].HCLK_IO[7]	CELL[2].HCLK_ROW[7]	MAIN[29][13]
CELL[2].HCLK_IO[8]	CELL[2].HCLK_ROW[8]	MAIN[28][13]
CELL[2].HCLK_IO[9]	CELL[2].HCLK_ROW[9]	MAIN[28][14]
CELL[2].RCLK_IO[0]	CELL[2].RCLK_ROW[0]	MAIN[9][13]
CELL[2].RCLK_IO[1]	CELL[2].RCLK_ROW[1]	MAIN[12][12]
CELL[2].RCLK_IO[2]	CELL[2].RCLK_ROW[2]	MAIN[27][12]
CELL[2].RCLK_IO[3]	CELL[2].RCLK_ROW[3]	MAIN[9][15]
CELL[2].HCLK_CMT[0]	CELL[2].HCLK_ROW[0]	MAIN[42][14]
CELL[2].HCLK_CMT[1]	CELL[2].HCLK_ROW[1]	MAIN[42][15]
CELL[2].HCLK_CMT[2]	CELL[2].HCLK_ROW[2]	MAIN[41][12]
CELL[2].HCLK_CMT[3]	CELL[2].HCLK_ROW[3]	MAIN[41][13]
CELL[2].HCLK_CMT[4]	CELL[2].HCLK_ROW[4]	MAIN[41][14]
CELL[2].HCLK_CMT[5]	CELL[2].HCLK_ROW[5]	MAIN[41][15]
CELL[2].HCLK_CMT[6]	CELL[2].HCLK_ROW[6]	MAIN[40][12]
CELL[2].HCLK_CMT[7]	CELL[2].HCLK_ROW[7]	MAIN[40][13]
CELL[2].HCLK_CMT[8]	CELL[2].HCLK_ROW[8]	MAIN[40][14]
CELL[2].HCLK_CMT[9]	CELL[2].HCLK_ROW[9]	MAIN[40][15]
CELL[2].GIOB_CMT[0]	CELL[2].GIOB[0]	MAIN[44][12]
CELL[2].GIOB_CMT[1]	CELL[2].GIOB[1]	MAIN[44][13]
CELL[2].GIOB_CMT[2]	CELL[2].GIOB[2]	MAIN[44][14]
CELL[2].GIOB_CMT[3]	CELL[2].GIOB[3]	MAIN[44][15]
CELL[2].GIOB_CMT[4]	CELL[2].GIOB[4]	MAIN[43][12]
CELL[2].GIOB_CMT[5]	CELL[2].GIOB[5]	MAIN[43][13]
CELL[2].GIOB_CMT[6]	CELL[2].GIOB[6]	MAIN[43][14]
CELL[2].GIOB_CMT[7]	CELL[2].GIOB[7]	MAIN[43][15]
CELL[2].GIOB_CMT[8]	CELL[2].GIOB[8]	MAIN[42][12]
CELL[2].GIOB_CMT[9]	CELL[2].GIOB[9]	MAIN[42][13]

virtex5 HCLK_IO_CMT_S switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
Bits										Destination
MAIN[10][15]	MAIN[11][15]	MAIN[12][14]	MAIN[13][14]	MAIN[13][12]	MAIN[26][14]	MAIN[10][13]	MAIN[26][13]	MAIN[27][13]	MAIN[10][12]	CELL[2].IMUX_IDELAYCTRL_REFCLK
										Source
0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	1	CELL[2].HCLK_IO[0]
0	0	0	0	0	0	0	0	1	0	CELL[2].HCLK_IO[1]
0	0	0	0	0	0	0	1	0	0	CELL[2].HCLK_IO[2]
0	0	0	0	0	0	1	0	0	0	CELL[2].HCLK_IO[3]
0	0	0	0	0	1	0	0	0	0	CELL[2].HCLK_IO[4]
0	0	0	0	1	0	0	0	0	0	CELL[2].HCLK_IO[5]
0	0	0	1	0	0	0	0	0	0	CELL[2].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	CELL[2].HCLK_IO[7]
0	1	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[8]
1	0	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[9]

virtex5 HCLK_IO_CMT_S wire support CELL[2].RCLK_ROW[0]
Bit
MAIN[18][15]

virtex5 HCLK_IO_CMT_S wire support CELL[2].RCLK_ROW[1]
Bit
MAIN[14][14]

virtex5 HCLK_IO_CMT_S wire support CELL[2].RCLK_ROW[2]
Bit
MAIN[15][13]

virtex5 HCLK_IO_CMT_S wire support CELL[2].RCLK_ROW[3]
Bit
MAIN[16][13]

virtex5 HCLK_IO_CMT_S wire support CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]
Bit
MAIN[15][14]
MAIN[15][15]

Bels HCLK_CMT_DRP

virtex5 HCLK_IO_CMT_S bel HCLK_CMT_DRP pins
Pin	Direction	HCLK_CMT_DRP

virtex5 HCLK_IO_CMT_S bel HCLK_CMT_DRP attribute bits
Attribute	HCLK_CMT_DRP
DRP_MASK	MAIN[27][15]

Bels BUFIO

virtex5 HCLK_IO_CMT_S bel BUFIO pins
Pin	Direction	BUFIO[2]	BUFIO[3]
I	in	CELL[0].OUT_CLKPAD	CELL[1].OUT_CLKPAD
O	out	CELL[2].IOCLK[2]	CELL[2].IOCLK[3]

virtex5 HCLK_IO_CMT_S bel BUFIO attribute bits
Attribute	BUFIO[2]	BUFIO[3]
ENABLE	MAIN[18][13]	MAIN[14][12]

Bels IDELAYCTRL

virtex5 HCLK_IO_CMT_S bel IDELAYCTRL pins
Pin	Direction	IDELAYCTRL
REFCLK	in	CELL[2].IMUX_IDELAYCTRL_REFCLK
RST	in	CELL[0].IMUX_IMUX[0]
RDY	out	CELL[1].OUT_BEL[22]
DNPULSEOUT	out	CELL[1].OUT_BEL[18]
UPPULSEOUT	out	CELL[1].OUT_BEL[17]
OUTN1	out	CELL[1].OUT_BEL[23]
OUTN65	out	CELL[1].OUT_BEL[16]

virtex5 HCLK_IO_CMT_S bel IDELAYCTRL attribute bits
Attribute	IDELAYCTRL
DLL_ENABLE	MAIN[37][14]
DELAY_ENABLE	MAIN[36][12]
VCTL_SEL bit 0	MAIN[36][13]
VCTL_SEL bit 1	MAIN[36][14]

Bels DCI

virtex5 HCLK_IO_CMT_S bel DCI pins
Pin	Direction	DCI
TSTCLK	in	CELL[1].IMUX_BYP_SITE[2]
TSTRST	in	CELL[1].IMUX_BYP_SITE[0]
TSTHLP	in	CELL[1].IMUX_BYP_SITE[3]
TSTHLN	in	CELL[1].IMUX_BYP_SITE[6]
DCISCLK	out	CELL[0].OUT_BEL[20]
DCIADDRESS[0]	out	CELL[1].OUT_BEL[8]
DCIADDRESS[1]	out	CELL[1].OUT_BEL[20]
DCIADDRESS[2]	out	CELL[1].OUT_BEL[22]
DCIDATA	out	CELL[0].OUT_BEL[22]
DCIIOUPDATE	out	CELL[0].OUT_BEL[8]
DCIREFIOUPDATE	out	CELL[0].OUT_BEL[15]
DCIDONE	out	CELL[0].OUT_BEL[20]

virtex5 HCLK_IO_CMT_S bel DCI attribute bits
Attribute	DCI
ENABLE	MAIN[46][14]
QUIET	MAIN[48][14]
V5_LVDIV2 bit 0	MAIN[52][12]
V5_LVDIV2 bit 1	MAIN[53][12]
V5_LVDIV2 bit 2	MAIN[53][15]
V4_PMASK_TERM_VCC bit 0	MAIN[50][15]
V4_PMASK_TERM_VCC bit 1	MAIN[50][14]
V4_PMASK_TERM_VCC bit 2	MAIN[51][14]
V4_PMASK_TERM_VCC bit 3	MAIN[51][13]
V4_PMASK_TERM_VCC bit 4	MAIN[50][13]
V4_PMASK_TERM_SPLIT bit 0	MAIN[46][13]
V4_PMASK_TERM_SPLIT bit 1	MAIN[46][12]
V4_PMASK_TERM_SPLIT bit 2	MAIN[47][12]
V4_PMASK_TERM_SPLIT bit 3	MAIN[48][15]
V4_PMASK_TERM_SPLIT bit 4	MAIN[49][15]
V4_NMASK_TERM_SPLIT bit 0	MAIN[48][13]
V4_NMASK_TERM_SPLIT bit 1	MAIN[49][13]
V4_NMASK_TERM_SPLIT bit 2	MAIN[49][12]
V4_NMASK_TERM_SPLIT bit 3	MAIN[48][12]
V4_NMASK_TERM_SPLIT bit 4	MAIN[51][15]
NREF bit 0	MAIN[52][14]
NREF bit 1	MAIN[52][13]
PREF bit 0	MAIN[51][12]
PREF bit 1	MAIN[50][12]
PREF bit 2	MAIN[53][14]
PREF bit 3	MAIN[52][15]
TEST_ENABLE bit 0	MAIN[49][14]
TEST_ENABLE bit 1	MAIN[53][13]
CASCADE_FROM_ABOVE	MAIN[47][14]
CASCADE_FROM_BELOW	MAIN[47][13]

Bels BANK

virtex5 HCLK_IO_CMT_S bel BANK pins
Pin	Direction	BANK

virtex5 HCLK_IO_CMT_S bel BANK attribute bits
Attribute	BANK
V5_LVDSBIAS bit 0	MAIN[35][15]
V5_LVDSBIAS bit 1	MAIN[34][15]
V5_LVDSBIAS bit 2	MAIN[34][14]
V5_LVDSBIAS bit 3	MAIN[35][14]
V5_LVDSBIAS bit 4	MAIN[35][13]
V5_LVDSBIAS bit 5	MAIN[34][13]
V5_LVDSBIAS bit 6	MAIN[34][12]
V5_LVDSBIAS bit 7	MAIN[35][12]
V5_LVDSBIAS bit 8	MAIN[32][13]
V5_LVDSBIAS bit 9	MAIN[33][13]
V5_LVDSBIAS bit 10	MAIN[33][12]
V5_LVDSBIAS bit 11	MAIN[32][12]
INTERNAL_VREF	[enum: INTERNAL_VREF]

virtex5 HCLK_IO_CMT_S enum INTERNAL_VREF
BANK.INTERNAL_VREF	MAIN[39][15]	MAIN[38][15]	MAIN[38][13]	MAIN[38][12]	MAIN[39][12]
OFF	0	0	0	0	0
_750	0	0	0	1	1
_900	0	0	1	0	1
_1080	0	1	0	0	1
_1250	1	0	0	0	1

Bel wires

virtex5 HCLK_IO_CMT_S bel wires
Wire	Pins
CELL[0].IMUX_IMUX[0]	IDELAYCTRL.RST
CELL[0].OUT_BEL[8]	DCI.DCIIOUPDATE
CELL[0].OUT_BEL[15]	DCI.DCIREFIOUPDATE
CELL[0].OUT_BEL[20]	DCI.DCISCLK, DCI.DCIDONE
CELL[0].OUT_BEL[22]	DCI.DCIDATA
CELL[0].OUT_CLKPAD	BUFIO[2].I
CELL[1].IMUX_BYP_SITE[0]	DCI.TSTRST
CELL[1].IMUX_BYP_SITE[2]	DCI.TSTCLK
CELL[1].IMUX_BYP_SITE[3]	DCI.TSTHLP
CELL[1].IMUX_BYP_SITE[6]	DCI.TSTHLN
CELL[1].OUT_BEL[8]	DCI.DCIADDRESS[0]
CELL[1].OUT_BEL[16]	IDELAYCTRL.OUTN65
CELL[1].OUT_BEL[17]	IDELAYCTRL.UPPULSEOUT
CELL[1].OUT_BEL[18]	IDELAYCTRL.DNPULSEOUT
CELL[1].OUT_BEL[20]	DCI.DCIADDRESS[1]
CELL[1].OUT_BEL[22]	IDELAYCTRL.RDY, DCI.DCIADDRESS[2]
CELL[1].OUT_BEL[23]	IDELAYCTRL.OUTN1
CELL[1].OUT_CLKPAD	BUFIO[3].I
CELL[2].IMUX_IDELAYCTRL_REFCLK	IDELAYCTRL.REFCLK
CELL[2].IOCLK[2]	BUFIO[2].O
CELL[2].IOCLK[3]	BUFIO[3].O

Bitstream

virtex5 HCLK_IO_CMT_S rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[3] ← CELL[2].RCLK_ROW[3]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 9	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 8	-	-	-	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 1	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[0]) bit 0	-	-	-	-	-	-	-	-	HCLK_CMT_DRP: DRP_MASK	-	-	-	-	-	-	BANK: V5_LVDSBIAS bit 1	BANK: V5_LVDSBIAS bit 0	-	-	BANK: INTERNAL_VREF bit 3	BANK: INTERNAL_VREF bit 4	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[9] ← CELL[2].HCLK_ROW[9]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[7] ← CELL[2].GIOB[7]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[3] ← CELL[2].GIOB[3]	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 3	DCI: V4_PMASK_TERM_SPLIT bit 4	DCI: V4_PMASK_TERM_VCC bit 0	DCI: V4_NMASK_TERM_SPLIT bit 4	DCI: PREF bit 3	DCI: V5_LVDIV2 bit 2
B14	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 7	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 6	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[1]) bit 0	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 0	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 4	-	HCLK_IO_INT: buffer CELL[2].HCLK_IO[9] ← CELL[2].HCLK_ROW[9]	-	-	-	-	-	BANK: V5_LVDSBIAS bit 2	BANK: V5_LVDSBIAS bit 3	IDELAYCTRL: VCTL_SEL bit 1	IDELAYCTRL: DLL_ENABLE	-	-	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[4] ← CELL[2].HCLK_ROW[4]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[6] ← CELL[2].GIOB[6]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[2] ← CELL[2].GIOB[2]	-	DCI: ENABLE	DCI: CASCADE_FROM_ABOVE	DCI: QUIET	DCI: TEST_ENABLE bit 0	DCI: V4_PMASK_TERM_VCC bit 1	DCI: V4_PMASK_TERM_VCC bit 2	DCI: NREF bit 0	DCI: PREF bit 2
B13	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[0] ← CELL[2].RCLK_ROW[0]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 3	HCLK_IO_INT: buffer CELL[2].HCLK_IO[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[4] ← CELL[2].HCLK_ROW[4]	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[2]) bit 0	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[3]) bit 0	-	BUFIO[2]: ENABLE	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 2	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 1	HCLK_IO_INT: buffer CELL[2].HCLK_IO[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[7] ← CELL[2].HCLK_ROW[7]	-	-	BANK: V5_LVDSBIAS bit 8	BANK: V5_LVDSBIAS bit 9	BANK: V5_LVDSBIAS bit 5	BANK: V5_LVDSBIAS bit 4	IDELAYCTRL: VCTL_SEL bit 0	-	BANK: INTERNAL_VREF bit 2	-	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[7] ← CELL[2].HCLK_ROW[7]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[9] ← CELL[2].GIOB[9]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[5] ← CELL[2].GIOB[5]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[1] ← CELL[2].GIOB[1]	-	DCI: V4_PMASK_TERM_SPLIT bit 0	DCI: CASCADE_FROM_BELOW	DCI: V4_NMASK_TERM_SPLIT bit 0	DCI: V4_NMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_VCC bit 4	DCI: V4_PMASK_TERM_VCC bit 3	DCI: NREF bit 1	DCI: TEST_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 0	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[1] ← CELL[2].RCLK_ROW[1]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 5	BUFIO[3]: ENABLE	HCLK_IO_INT: buffer CELL[2].HCLK_IO[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[2] ← CELL[2].HCLK_ROW[2]	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[2] ← CELL[2].RCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[6] ← CELL[2].HCLK_ROW[6]	-	-	BANK: V5_LVDSBIAS bit 11	BANK: V5_LVDSBIAS bit 10	BANK: V5_LVDSBIAS bit 6	BANK: V5_LVDSBIAS bit 7	IDELAYCTRL: DELAY_ENABLE	-	BANK: INTERNAL_VREF bit 1	BANK: INTERNAL_VREF bit 0	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[6] ← CELL[2].HCLK_ROW[6]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[2] ← CELL[2].HCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[8] ← CELL[2].GIOB[8]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[4] ← CELL[2].GIOB[4]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[0] ← CELL[2].GIOB[0]	-	DCI: V4_PMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_SPLIT bit 2	DCI: V4_NMASK_TERM_SPLIT bit 3	DCI: V4_NMASK_TERM_SPLIT bit 2	DCI: PREF bit 1	DCI: PREF bit 0	DCI: V5_LVDIV2 bit 0	DCI: V5_LVDIV2 bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile HCLK_IO_CMT_N

Cells: 4

Switchbox HCLK_IO_INT

virtex5 HCLK_IO_CMT_N switchbox HCLK_IO_INT programmable buffers
Destination	Source	Bit
CELL[2].HCLK_IO[0]	CELL[2].HCLK_ROW[0]	MAIN[16][12]
CELL[2].HCLK_IO[1]	CELL[2].HCLK_ROW[1]	MAIN[15][12]
CELL[2].HCLK_IO[2]	CELL[2].HCLK_ROW[2]	MAIN[17][12]
CELL[2].HCLK_IO[3]	CELL[2].HCLK_ROW[3]	MAIN[11][13]
CELL[2].HCLK_IO[4]	CELL[2].HCLK_ROW[4]	MAIN[12][13]
CELL[2].HCLK_IO[5]	CELL[2].HCLK_ROW[5]	MAIN[28][12]
CELL[2].HCLK_IO[6]	CELL[2].HCLK_ROW[6]	MAIN[29][12]
CELL[2].HCLK_IO[7]	CELL[2].HCLK_ROW[7]	MAIN[29][13]
CELL[2].HCLK_IO[8]	CELL[2].HCLK_ROW[8]	MAIN[28][13]
CELL[2].HCLK_IO[9]	CELL[2].HCLK_ROW[9]	MAIN[28][14]
CELL[2].RCLK_IO[0]	CELL[2].RCLK_ROW[0]	MAIN[9][13]
CELL[2].RCLK_IO[1]	CELL[2].RCLK_ROW[1]	MAIN[12][12]
CELL[2].RCLK_IO[2]	CELL[2].RCLK_ROW[2]	MAIN[27][12]
CELL[2].RCLK_IO[3]	CELL[2].RCLK_ROW[3]	MAIN[9][15]
CELL[2].HCLK_CMT[0]	CELL[2].HCLK_ROW[0]	MAIN[42][14]
CELL[2].HCLK_CMT[1]	CELL[2].HCLK_ROW[1]	MAIN[42][15]
CELL[2].HCLK_CMT[2]	CELL[2].HCLK_ROW[2]	MAIN[41][12]
CELL[2].HCLK_CMT[3]	CELL[2].HCLK_ROW[3]	MAIN[41][13]
CELL[2].HCLK_CMT[4]	CELL[2].HCLK_ROW[4]	MAIN[41][14]
CELL[2].HCLK_CMT[5]	CELL[2].HCLK_ROW[5]	MAIN[41][15]
CELL[2].HCLK_CMT[6]	CELL[2].HCLK_ROW[6]	MAIN[40][12]
CELL[2].HCLK_CMT[7]	CELL[2].HCLK_ROW[7]	MAIN[40][13]
CELL[2].HCLK_CMT[8]	CELL[2].HCLK_ROW[8]	MAIN[40][14]
CELL[2].HCLK_CMT[9]	CELL[2].HCLK_ROW[9]	MAIN[40][15]
CELL[2].GIOB_CMT[0]	CELL[2].GIOB[0]	MAIN[44][12]
CELL[2].GIOB_CMT[1]	CELL[2].GIOB[1]	MAIN[44][13]
CELL[2].GIOB_CMT[2]	CELL[2].GIOB[2]	MAIN[44][14]
CELL[2].GIOB_CMT[3]	CELL[2].GIOB[3]	MAIN[44][15]
CELL[2].GIOB_CMT[4]	CELL[2].GIOB[4]	MAIN[43][12]
CELL[2].GIOB_CMT[5]	CELL[2].GIOB[5]	MAIN[43][13]
CELL[2].GIOB_CMT[6]	CELL[2].GIOB[6]	MAIN[43][14]
CELL[2].GIOB_CMT[7]	CELL[2].GIOB[7]	MAIN[43][15]
CELL[2].GIOB_CMT[8]	CELL[2].GIOB[8]	MAIN[42][12]
CELL[2].GIOB_CMT[9]	CELL[2].GIOB[9]	MAIN[42][13]

virtex5 HCLK_IO_CMT_N switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
Bits										Destination
MAIN[10][15]	MAIN[11][15]	MAIN[12][14]	MAIN[13][14]	MAIN[13][12]	MAIN[26][14]	MAIN[10][13]	MAIN[26][13]	MAIN[27][13]	MAIN[10][12]	CELL[2].IMUX_IDELAYCTRL_REFCLK
										Source
0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	1	CELL[2].HCLK_IO[0]
0	0	0	0	0	0	0	0	1	0	CELL[2].HCLK_IO[1]
0	0	0	0	0	0	0	1	0	0	CELL[2].HCLK_IO[2]
0	0	0	0	0	0	1	0	0	0	CELL[2].HCLK_IO[3]
0	0	0	0	0	1	0	0	0	0	CELL[2].HCLK_IO[4]
0	0	0	0	1	0	0	0	0	0	CELL[2].HCLK_IO[5]
0	0	0	1	0	0	0	0	0	0	CELL[2].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	CELL[2].HCLK_IO[7]
0	1	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[8]
1	0	0	0	0	0	0	0	0	0	CELL[2].HCLK_IO[9]

virtex5 HCLK_IO_CMT_N wire support CELL[2].RCLK_ROW[0]
Bit
MAIN[18][15]

virtex5 HCLK_IO_CMT_N wire support CELL[2].RCLK_ROW[1]
Bit
MAIN[14][14]

virtex5 HCLK_IO_CMT_N wire support CELL[2].RCLK_ROW[2]
Bit
MAIN[15][13]

virtex5 HCLK_IO_CMT_N wire support CELL[2].RCLK_ROW[3]
Bit
MAIN[16][13]

virtex5 HCLK_IO_CMT_N wire support CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]
Bit
MAIN[15][14]
MAIN[15][15]

Bels HCLK_CMT_DRP

virtex5 HCLK_IO_CMT_N bel HCLK_CMT_DRP pins
Pin	Direction	HCLK_CMT_DRP

virtex5 HCLK_IO_CMT_N bel HCLK_CMT_DRP attribute bits
Attribute	HCLK_CMT_DRP
DRP_MASK	MAIN[27][15]

Bels BUFIO

virtex5 HCLK_IO_CMT_N bel BUFIO pins
Pin	Direction	BUFIO[0]	BUFIO[1]
I	in	CELL[2].OUT_CLKPAD	CELL[3].OUT_CLKPAD
O	out	CELL[2].IOCLK[0]	CELL[2].IOCLK[1]

virtex5 HCLK_IO_CMT_N bel BUFIO attribute bits
Attribute	BUFIO[0]	BUFIO[1]
ENABLE	MAIN[19][12]	MAIN[19][13]

Bels IDELAYCTRL

virtex5 HCLK_IO_CMT_N bel IDELAYCTRL pins
Pin	Direction	IDELAYCTRL
REFCLK	in	CELL[2].IMUX_IDELAYCTRL_REFCLK
RST	in	CELL[3].IMUX_IMUX[6]
RDY	out	CELL[2].OUT_BEL[22]
DNPULSEOUT	out	CELL[2].OUT_BEL[23]
UPPULSEOUT	out	CELL[2].OUT_BEL[15]
OUTN1	out	CELL[2].OUT_BEL[20]
OUTN65	out	CELL[2].OUT_BEL[8]

virtex5 HCLK_IO_CMT_N bel IDELAYCTRL attribute bits
Attribute	IDELAYCTRL
DLL_ENABLE	MAIN[37][14]
DELAY_ENABLE	MAIN[36][12]
VCTL_SEL bit 0	MAIN[36][13]
VCTL_SEL bit 1	MAIN[36][14]

Bels DCI

virtex5 HCLK_IO_CMT_N bel DCI pins
Pin	Direction	DCI
TSTCLK	in	CELL[2].IMUX_BYP_SITE[2]
TSTRST	in	CELL[2].IMUX_BYP_SITE[0]
TSTHLP	in	CELL[2].IMUX_BYP_SITE[3]
TSTHLN	in	CELL[2].IMUX_BYP_SITE[6]
DCISCLK	out	CELL[2].OUT_BEL[20]
DCIADDRESS[0]	out	CELL[2].OUT_BEL[8]
DCIADDRESS[1]	out	CELL[2].OUT_BEL[20]
DCIADDRESS[2]	out	CELL[2].OUT_BEL[22]
DCIDATA	out	CELL[2].OUT_BEL[22]
DCIIOUPDATE	out	CELL[2].OUT_BEL[8]
DCIREFIOUPDATE	out	CELL[2].OUT_BEL[15]
DCIDONE	out	CELL[2].OUT_BEL[20]

virtex5 HCLK_IO_CMT_N bel DCI attribute bits
Attribute	DCI
ENABLE	MAIN[46][14]
QUIET	MAIN[48][14]
V5_LVDIV2 bit 0	MAIN[52][12]
V5_LVDIV2 bit 1	MAIN[53][12]
V5_LVDIV2 bit 2	MAIN[53][15]
V4_PMASK_TERM_VCC bit 0	MAIN[50][15]
V4_PMASK_TERM_VCC bit 1	MAIN[50][14]
V4_PMASK_TERM_VCC bit 2	MAIN[51][14]
V4_PMASK_TERM_VCC bit 3	MAIN[51][13]
V4_PMASK_TERM_VCC bit 4	MAIN[50][13]
V4_PMASK_TERM_SPLIT bit 0	MAIN[46][13]
V4_PMASK_TERM_SPLIT bit 1	MAIN[46][12]
V4_PMASK_TERM_SPLIT bit 2	MAIN[47][12]
V4_PMASK_TERM_SPLIT bit 3	MAIN[48][15]
V4_PMASK_TERM_SPLIT bit 4	MAIN[49][15]
V4_NMASK_TERM_SPLIT bit 0	MAIN[48][13]
V4_NMASK_TERM_SPLIT bit 1	MAIN[49][13]
V4_NMASK_TERM_SPLIT bit 2	MAIN[49][12]
V4_NMASK_TERM_SPLIT bit 3	MAIN[48][12]
V4_NMASK_TERM_SPLIT bit 4	MAIN[51][15]
NREF bit 0	MAIN[52][14]
NREF bit 1	MAIN[52][13]
PREF bit 0	MAIN[51][12]
PREF bit 1	MAIN[50][12]
PREF bit 2	MAIN[53][14]
PREF bit 3	MAIN[52][15]
TEST_ENABLE bit 0	MAIN[49][14]
TEST_ENABLE bit 1	MAIN[53][13]
CASCADE_FROM_ABOVE	MAIN[47][14]
CASCADE_FROM_BELOW	MAIN[47][13]

Bels BANK

virtex5 HCLK_IO_CMT_N bel BANK pins
Pin	Direction	BANK

virtex5 HCLK_IO_CMT_N bel BANK attribute bits
Attribute	BANK
V5_LVDSBIAS bit 0	MAIN[35][15]
V5_LVDSBIAS bit 1	MAIN[34][15]
V5_LVDSBIAS bit 2	MAIN[34][14]
V5_LVDSBIAS bit 3	MAIN[35][14]
V5_LVDSBIAS bit 4	MAIN[35][13]
V5_LVDSBIAS bit 5	MAIN[34][13]
V5_LVDSBIAS bit 6	MAIN[34][12]
V5_LVDSBIAS bit 7	MAIN[35][12]
V5_LVDSBIAS bit 8	MAIN[32][13]
V5_LVDSBIAS bit 9	MAIN[33][13]
V5_LVDSBIAS bit 10	MAIN[33][12]
V5_LVDSBIAS bit 11	MAIN[32][12]
INTERNAL_VREF	[enum: INTERNAL_VREF]

virtex5 HCLK_IO_CMT_N enum INTERNAL_VREF
BANK.INTERNAL_VREF	MAIN[39][15]	MAIN[38][15]	MAIN[38][13]	MAIN[38][12]	MAIN[39][12]
OFF	0	0	0	0	0
_750	0	0	0	1	1
_900	0	0	1	0	1
_1080	0	1	0	0	1
_1250	1	0	0	0	1

Bel wires

virtex5 HCLK_IO_CMT_N bel wires
Wire	Pins
CELL[2].IMUX_BYP_SITE[0]	DCI.TSTRST
CELL[2].IMUX_BYP_SITE[2]	DCI.TSTCLK
CELL[2].IMUX_BYP_SITE[3]	DCI.TSTHLP
CELL[2].IMUX_BYP_SITE[6]	DCI.TSTHLN
CELL[2].OUT_BEL[8]	IDELAYCTRL.OUTN65, DCI.DCIADDRESS[0], DCI.DCIIOUPDATE
CELL[2].OUT_BEL[15]	IDELAYCTRL.UPPULSEOUT, DCI.DCIREFIOUPDATE
CELL[2].OUT_BEL[20]	IDELAYCTRL.OUTN1, DCI.DCISCLK, DCI.DCIADDRESS[1], DCI.DCIDONE
CELL[2].OUT_BEL[22]	IDELAYCTRL.RDY, DCI.DCIADDRESS[2], DCI.DCIDATA
CELL[2].OUT_BEL[23]	IDELAYCTRL.DNPULSEOUT
CELL[2].OUT_CLKPAD	BUFIO[0].I
CELL[2].IMUX_IDELAYCTRL_REFCLK	IDELAYCTRL.REFCLK
CELL[2].IOCLK[0]	BUFIO[0].O
CELL[2].IOCLK[1]	BUFIO[1].O
CELL[3].IMUX_IMUX[6]	IDELAYCTRL.RST
CELL[3].OUT_CLKPAD	BUFIO[1].I

Bitstream

virtex5 HCLK_IO_CMT_N rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[3] ← CELL[2].RCLK_ROW[3]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 9	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 8	-	-	-	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 1	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[0]) bit 0	-	-	-	-	-	-	-	-	HCLK_CMT_DRP: DRP_MASK	-	-	-	-	-	-	BANK: V5_LVDSBIAS bit 1	BANK: V5_LVDSBIAS bit 0	-	-	BANK: INTERNAL_VREF bit 3	BANK: INTERNAL_VREF bit 4	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[9] ← CELL[2].HCLK_ROW[9]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[7] ← CELL[2].GIOB[7]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[3] ← CELL[2].GIOB[3]	-	-	-	DCI: V4_PMASK_TERM_SPLIT bit 3	DCI: V4_PMASK_TERM_SPLIT bit 4	DCI: V4_PMASK_TERM_VCC bit 0	DCI: V4_NMASK_TERM_SPLIT bit 4	DCI: PREF bit 3	DCI: V5_LVDIV2 bit 2
B14	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 7	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 6	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[1]) bit 0	HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1], CELL[2].IOCLK[2], CELL[2].IOCLK[3]) bit 0	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 4	-	HCLK_IO_INT: buffer CELL[2].HCLK_IO[9] ← CELL[2].HCLK_ROW[9]	-	-	-	-	-	BANK: V5_LVDSBIAS bit 2	BANK: V5_LVDSBIAS bit 3	IDELAYCTRL: VCTL_SEL bit 1	IDELAYCTRL: DLL_ENABLE	-	-	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[4] ← CELL[2].HCLK_ROW[4]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[6] ← CELL[2].GIOB[6]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[2] ← CELL[2].GIOB[2]	-	DCI: ENABLE	DCI: CASCADE_FROM_ABOVE	DCI: QUIET	DCI: TEST_ENABLE bit 0	DCI: V4_PMASK_TERM_VCC bit 1	DCI: V4_PMASK_TERM_VCC bit 2	DCI: NREF bit 0	DCI: PREF bit 2
B13	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[0] ← CELL[2].RCLK_ROW[0]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 3	HCLK_IO_INT: buffer CELL[2].HCLK_IO[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[4] ← CELL[2].HCLK_ROW[4]	-	-	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[2]) bit 0	HCLK_IO_INT: wire support (CELL[2].RCLK_ROW[3]) bit 0	-	-	BUFIO[1]: ENABLE	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 2	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 1	HCLK_IO_INT: buffer CELL[2].HCLK_IO[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[7] ← CELL[2].HCLK_ROW[7]	-	-	BANK: V5_LVDSBIAS bit 8	BANK: V5_LVDSBIAS bit 9	BANK: V5_LVDSBIAS bit 5	BANK: V5_LVDSBIAS bit 4	IDELAYCTRL: VCTL_SEL bit 0	-	BANK: INTERNAL_VREF bit 2	-	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[7] ← CELL[2].HCLK_ROW[7]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[9] ← CELL[2].GIOB[9]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[5] ← CELL[2].GIOB[5]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[1] ← CELL[2].GIOB[1]	-	DCI: V4_PMASK_TERM_SPLIT bit 0	DCI: CASCADE_FROM_BELOW	DCI: V4_NMASK_TERM_SPLIT bit 0	DCI: V4_NMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_VCC bit 4	DCI: V4_PMASK_TERM_VCC bit 3	DCI: NREF bit 1	DCI: TEST_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 0	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[1] ← CELL[2].RCLK_ROW[1]	HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 5	-	HCLK_IO_INT: buffer CELL[2].HCLK_IO[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[2] ← CELL[2].HCLK_ROW[2]	-	BUFIO[0]: ENABLE	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].RCLK_IO[2] ← CELL[2].RCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_IO[6] ← CELL[2].HCLK_ROW[6]	-	-	BANK: V5_LVDSBIAS bit 11	BANK: V5_LVDSBIAS bit 10	BANK: V5_LVDSBIAS bit 6	BANK: V5_LVDSBIAS bit 7	IDELAYCTRL: DELAY_ENABLE	-	BANK: INTERNAL_VREF bit 1	BANK: INTERNAL_VREF bit 0	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[6] ← CELL[2].HCLK_ROW[6]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[2] ← CELL[2].HCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[8] ← CELL[2].GIOB[8]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[4] ← CELL[2].GIOB[4]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[0] ← CELL[2].GIOB[0]	-	DCI: V4_PMASK_TERM_SPLIT bit 1	DCI: V4_PMASK_TERM_SPLIT bit 2	DCI: V4_NMASK_TERM_SPLIT bit 3	DCI: V4_NMASK_TERM_SPLIT bit 2	DCI: PREF bit 1	DCI: PREF bit 0	DCI: V5_LVDIV2 bit 0	DCI: V5_LVDIV2 bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile HCLK_CMT

Cells: 4

Switchbox HCLK_IO_INT

virtex5 HCLK_CMT switchbox HCLK_IO_INT programmable buffers
Destination	Source	Bit
CELL[2].HCLK_CMT[0]	CELL[2].HCLK_ROW[0]	MAIN[42][14]
CELL[2].HCLK_CMT[1]	CELL[2].HCLK_ROW[1]	MAIN[42][15]
CELL[2].HCLK_CMT[2]	CELL[2].HCLK_ROW[2]	MAIN[41][12]
CELL[2].HCLK_CMT[3]	CELL[2].HCLK_ROW[3]	MAIN[41][13]
CELL[2].HCLK_CMT[4]	CELL[2].HCLK_ROW[4]	MAIN[41][14]
CELL[2].HCLK_CMT[5]	CELL[2].HCLK_ROW[5]	MAIN[41][15]
CELL[2].HCLK_CMT[6]	CELL[2].HCLK_ROW[6]	MAIN[40][12]
CELL[2].HCLK_CMT[7]	CELL[2].HCLK_ROW[7]	MAIN[40][13]
CELL[2].HCLK_CMT[8]	CELL[2].HCLK_ROW[8]	MAIN[40][14]
CELL[2].HCLK_CMT[9]	CELL[2].HCLK_ROW[9]	MAIN[40][15]
CELL[2].GIOB_CMT[0]	CELL[2].GIOB[0]	MAIN[44][12]
CELL[2].GIOB_CMT[1]	CELL[2].GIOB[1]	MAIN[44][13]
CELL[2].GIOB_CMT[2]	CELL[2].GIOB[2]	MAIN[44][14]
CELL[2].GIOB_CMT[3]	CELL[2].GIOB[3]	MAIN[44][15]
CELL[2].GIOB_CMT[4]	CELL[2].GIOB[4]	MAIN[43][12]
CELL[2].GIOB_CMT[5]	CELL[2].GIOB[5]	MAIN[43][13]
CELL[2].GIOB_CMT[6]	CELL[2].GIOB[6]	MAIN[43][14]
CELL[2].GIOB_CMT[7]	CELL[2].GIOB[7]	MAIN[43][15]
CELL[2].GIOB_CMT[8]	CELL[2].GIOB[8]	MAIN[42][12]
CELL[2].GIOB_CMT[9]	CELL[2].GIOB[9]	MAIN[42][13]

Bels HCLK_CMT_DRP

virtex5 HCLK_CMT bel HCLK_CMT_DRP pins
Pin	Direction	HCLK_CMT_DRP

virtex5 HCLK_CMT bel HCLK_CMT_DRP attribute bits
Attribute	HCLK_CMT_DRP
DRP_MASK	MAIN[27][15]

Bitstream

virtex5 HCLK_CMT rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_CMT_DRP: DRP_MASK	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[9] ← CELL[2].HCLK_ROW[9]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[5] ← CELL[2].HCLK_ROW[5]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[1] ← CELL[2].HCLK_ROW[1]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[7] ← CELL[2].GIOB[7]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[3] ← CELL[2].GIOB[3]	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[8] ← CELL[2].HCLK_ROW[8]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[4] ← CELL[2].HCLK_ROW[4]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[0] ← CELL[2].HCLK_ROW[0]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[6] ← CELL[2].GIOB[6]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[2] ← CELL[2].GIOB[2]	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[7] ← CELL[2].HCLK_ROW[7]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[3] ← CELL[2].HCLK_ROW[3]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[9] ← CELL[2].GIOB[9]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[5] ← CELL[2].GIOB[5]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[1] ← CELL[2].GIOB[1]	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[6] ← CELL[2].HCLK_ROW[6]	HCLK_IO_INT: buffer CELL[2].HCLK_CMT[2] ← CELL[2].HCLK_ROW[2]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[8] ← CELL[2].GIOB[8]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[4] ← CELL[2].GIOB[4]	HCLK_IO_INT: buffer CELL[2].GIOB_CMT[0] ← CELL[2].GIOB[0]	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

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