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Clock I/O and CMT buffers

Tile HCLK_IOI

Cells: 4

Bel IOCLK

virtex5 HCLK_IOI bel IOCLK
PinDirectionWires

Bel RCLK

virtex5 HCLK_IOI bel RCLK
PinDirectionWires
CKINT0inputTCELL0:IMUX.IMUX6
CKINT1inputTCELL3:IMUX.IMUX0

Bel BUFR0

virtex5 HCLK_IOI bel BUFR0
PinDirectionWires
CEinputTCELL1:IMUX.IMUX6
CLRinputTCELL1:IMUX.IMUX0

Bel BUFR1

virtex5 HCLK_IOI bel BUFR1
PinDirectionWires
CEinputTCELL2:IMUX.IMUX6
CLRinputTCELL2:IMUX.IMUX0

Bel BUFIO0

virtex5 HCLK_IOI bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex5 HCLK_IOI bel BUFIO1
PinDirectionWires

Bel BUFIO2

virtex5 HCLK_IOI bel BUFIO2
PinDirectionWires

Bel BUFIO3

virtex5 HCLK_IOI bel BUFIO3
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL1:OUT18.TMIN
OUTN1outputTCELL1:OUT23.TMIN
OUTN65outputTCELL1:OUT16.TMIN
RDYoutputTCELL1:OUT22.TMIN
RSTinputTCELL0:IMUX.IMUX0
UPPULSEOUToutputTCELL1:OUT17.TMIN

Bel DCI

virtex5 HCLK_IOI bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL1:OUT8.TMIN
DCIADDRESS1outputTCELL1:OUT20.TMIN
DCIADDRESS2outputTCELL1:OUT22.TMIN
DCIDATAoutputTCELL0:OUT22.TMIN
DCIDONEoutputTCELL0:OUT20.TMIN
DCIIOUPDATEoutputTCELL0:OUT8.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT15.TMIN
DCISCLKoutputTCELL0:OUT20.TMIN
TSTCLKinputTCELL1:IMUX.BYP2.SITE
TSTHLNinputTCELL1:IMUX.BYP6.SITE
TSTHLPinputTCELL1:IMUX.BYP3.SITE
TSTRSTinputTCELL1:IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI bel wires
WirePins
TCELL0:IMUX.IMUX0IDELAYCTRL.RST
TCELL0:IMUX.IMUX6RCLK.CKINT0
TCELL0:OUT8.TMINDCI.DCIIOUPDATE
TCELL0:OUT15.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT20.TMINDCI.DCIDONE, DCI.DCISCLK
TCELL0:OUT22.TMINDCI.DCIDATA
TCELL1:IMUX.BYP0.SITEDCI.TSTRST
TCELL1:IMUX.BYP2.SITEDCI.TSTCLK
TCELL1:IMUX.BYP3.SITEDCI.TSTHLP
TCELL1:IMUX.BYP6.SITEDCI.TSTHLN
TCELL1:IMUX.IMUX0BUFR0.CLR
TCELL1:IMUX.IMUX6BUFR0.CE
TCELL1:OUT8.TMINDCI.DCIADDRESS0
TCELL1:OUT16.TMINIDELAYCTRL.OUTN65
TCELL1:OUT17.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT18.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT20.TMINDCI.DCIADDRESS1
TCELL1:OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2
TCELL1:OUT23.TMINIDELAYCTRL.OUTN1
TCELL2:IMUX.IMUX0BUFR1.CLR
TCELL2:IMUX.IMUX6BUFR1.CE
TCELL3:IMUX.IMUX0RCLK.CKINT1

Bitstream

virtex5 HCLK_IOI bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
15 - - - - - - - - BUFR1:BUFR_DIVIDE[1] IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] RCLK:MUX.RCLK2[3] RCLK:MUX.RCLK2[1] BUFR1:BUFR_DIVIDE[0] IOCLK:IOCLK_ENABLE[1] BUFR0:BUFR_DIVIDE[3] RCLK:MUX.RCLK1[3] RCLK:MUX.RCLK0[0] - - - - - - - BUFR1:BUFR_DIVIDE[2] - RCLK:MUX.RCLK0[2] RCLK:MUX.RCLK0[1] BUFR0:MUX.I[5] BUFR0:MUX.I[6] BUFR0:MUX.I[8] BUFR0:MUX.I[7] LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
14 - - - - - - - - - - RCLK:MUX.RCLK1[2] RCLK:MUX.RCLK1[1] IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] RCLK:MUX.RCLK1[0] IOCLK:IOCLK_ENABLE[0] BUFR0:BUFR_DIVIDE[2] BUFR0:BUFR_DIVIDE[1] BUFR0:BUFR_DIVIDE[0] - - - - - - - IDELAYCTRL:MUX.REFCLK[4] BUFR1:BUFR_DIVIDE[3] IOCLK:BUF.HCLK9 RCLK:MUX.RCLK0[3] BUFR0:MUX.I[4] BUFR0:MUX.I[3] BUFR0:MUX.I[0] BUFR0:MUX.I[1] LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 BUFR1:MUX.I[5] RCLK:MUX.RCLK3[3] RCLK:MUX.RCLK2[0] RCLK:MUX.RCLK3[0] RCLK:MUX.RCLK3[1] BUFIO2:ENABLE BUFIO1:ENABLE BUFR1:MUX.I[0] BUFR1:MUX.I[4] BUFR1:MUX.I[3] BUFR1:MUX.I[2] - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 BUFR0:MUX.I[9] BUFR0:MUX.I[2] LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
12 - - - - - - - - - BUFR1:ENABLE IDELAYCTRL:MUX.REFCLK[0] BUFR1:MUX.I[8] IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] BUFIO3:ENABLE IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 BUFR1:MUX.I[6] BUFIO0:ENABLE RCLK:MUX.RCLK3[2] BUFR1:MUX.I[7] BUFR1:MUX.I[10] BUFR1:MUX.I[9] BUFR1:MUX.I[1] - RCLK:MUX.RCLK2[2] IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 BUFR0:MUX.I[10] BUFR0:ENABLE LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:ENABLE 0.19.12
BUFIO1:ENABLE 0.19.13
BUFIO2:ENABLE 0.18.13
BUFIO3:ENABLE 0.14.12
BUFR0:ENABLE 0.31.12
BUFR1:ENABLE 0.9.12
DCI:CASCADE_FROM_ABOVE 0.47.14
DCI:CASCADE_FROM_BELOW 0.47.13
DCI:ENABLE 0.46.14
DCI:QUIET 0.48.14
IOCLK:BUF.HCLK0 0.16.12
IOCLK:BUF.HCLK1 0.15.12
IOCLK:BUF.HCLK2 0.17.12
IOCLK:BUF.HCLK3 0.11.13
IOCLK:BUF.HCLK4 0.12.13
IOCLK:BUF.HCLK5 0.28.12
IOCLK:BUF.HCLK6 0.29.12
IOCLK:BUF.HCLK7 0.29.13
IOCLK:BUF.HCLK8 0.28.13
IOCLK:BUF.HCLK9 0.28.14
IOCLK:BUF.RCLK0 0.9.13
IOCLK:BUF.RCLK1 0.12.12
IOCLK:BUF.RCLK2 0.27.12
IOCLK:BUF.RCLK3 0.9.15
non-inverted [0]
BUFR0:BUFR_DIVIDE 0.16.15 0.16.14 0.17.14 0.18.14
BUFR1:BUFR_DIVIDE 0.27.14 0.26.15 0.8.15 0.14.15
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:MUX.I 0.30.12 0.30.13 0.32.15 0.33.15 0.31.15 0.30.15 0.30.14 0.31.14 0.31.13 0.33.14 0.32.14
BUFR1:MUX.I 0.22.12 0.23.12 0.11.12 0.21.12 0.18.12 0.13.13 0.21.13 0.22.13 0.23.13 0.24.12 0.20.13
NONE 0 0 0 0 0 0 0 0 0 0 0
CKINT0 0 0 0 0 0 0 0 0 0 0 1
CKINT1 0 0 0 0 0 0 0 0 0 1 0
BUFIO0 0 0 0 0 0 0 0 0 1 0 0
BUFIO1 0 0 0 0 0 0 0 1 0 0 0
BUFIO2 0 0 0 0 0 0 1 0 0 0 0
BUFIO3 0 0 0 0 0 1 0 0 0 0 0
MGT0 0 0 0 0 1 0 0 0 0 0 0
MGT1 0 0 0 1 0 0 0 0 0 0 0
MGT2 0 0 1 0 0 0 0 0 0 0 0
MGT3 0 1 0 0 0 0 0 0 0 0 0
MGT4 1 0 0 0 0 0 0 0 0 0 0
DCI:LVDIV2 0.53.15 0.53.12 0.52.12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.51.15 0.48.12 0.49.12 0.49.13 0.48.13
DCI:PMASK_TERM_SPLIT 0.49.15 0.48.15 0.47.12 0.46.12 0.46.13
DCI:PMASK_TERM_VCC 0.50.13 0.51.13 0.51.14 0.50.14 0.50.15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.52.13 0.52.14
DCI:TEST_ENABLE 0.53.13 0.49.14
IOCLK:IOCLK_ENABLE 0.15.15 0.15.14
non-inverted [1] [0]
DCI:PREF 0.52.15 0.53.14 0.50.12 0.51.12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.36.14 0.37.14 0.36.13 0.36.12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.10.15 0.11.15 0.12.14 0.13.14 0.13.12 0.26.14 0.10.13 0.26.13 0.27.13 0.10.12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.39.15 0.38.15 0.38.13 0.38.12 0.39.12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.32.12 0.33.12 0.33.13 0.32.13 0.35.12 0.34.12 0.34.13 0.35.13 0.35.14 0.34.14 0.34.15 0.35.15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
RCLK:MUX.RCLK0 0.29.14 0.28.15 0.29.15 0.18.15
RCLK:MUX.RCLK1 0.17.15 0.10.14 0.11.14 0.14.14
RCLK:MUX.RCLK2 0.12.15 0.26.12 0.13.15 0.15.13
RCLK:MUX.RCLK3 0.14.13 0.20.12 0.17.13 0.16.13
NONE 0 0 0 0
VRCLK_N0 0 0 0 1
VRCLK0 0 0 1 1
VRCLK_N1 0 1 0 1
VRCLK1 0 1 1 1
VRCLK_S0 1 0 0 1
VRCLK_S1 1 1 0 1

Tile HCLK_IOI_CENTER

Cells: 2

Bel IOCLK

virtex5 HCLK_IOI_CENTER bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex5 HCLK_IOI_CENTER bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex5 HCLK_IOI_CENTER bel BUFIO1
PinDirectionWires

Bel BUFIO2

virtex5 HCLK_IOI_CENTER bel BUFIO2
PinDirectionWires

Bel BUFIO3

virtex5 HCLK_IOI_CENTER bel BUFIO3
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI_CENTER bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL1:OUT18.TMIN
OUTN1outputTCELL1:OUT23.TMIN
OUTN65outputTCELL1:OUT16.TMIN
RDYoutputTCELL1:OUT22.TMIN
RSTinputTCELL0:IMUX.IMUX0
UPPULSEOUToutputTCELL1:OUT17.TMIN

Bel DCI

virtex5 HCLK_IOI_CENTER bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL1:OUT8.TMIN
DCIADDRESS1outputTCELL1:OUT20.TMIN
DCIADDRESS2outputTCELL1:OUT22.TMIN
DCIDATAoutputTCELL0:OUT22.TMIN
DCIDONEoutputTCELL0:OUT20.TMIN
DCIIOUPDATEoutputTCELL0:OUT8.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT15.TMIN
DCISCLKoutputTCELL0:OUT20.TMIN
TSTCLKinputTCELL1:IMUX.BYP2.SITE
TSTHLNinputTCELL1:IMUX.BYP6.SITE
TSTHLPinputTCELL1:IMUX.BYP3.SITE
TSTRSTinputTCELL1:IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI_CENTER bel wires
WirePins
TCELL0:IMUX.IMUX0IDELAYCTRL.RST
TCELL0:OUT8.TMINDCI.DCIIOUPDATE
TCELL0:OUT15.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT20.TMINDCI.DCIDONE, DCI.DCISCLK
TCELL0:OUT22.TMINDCI.DCIDATA
TCELL1:IMUX.BYP0.SITEDCI.TSTRST
TCELL1:IMUX.BYP2.SITEDCI.TSTCLK
TCELL1:IMUX.BYP3.SITEDCI.TSTHLP
TCELL1:IMUX.BYP6.SITEDCI.TSTHLN
TCELL1:OUT8.TMINDCI.DCIADDRESS0
TCELL1:OUT16.TMINIDELAYCTRL.OUTN65
TCELL1:OUT17.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT18.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT20.TMINDCI.DCIADDRESS1
TCELL1:OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2
TCELL1:OUT23.TMINIDELAYCTRL.OUTN1

Bitstream

virtex5 HCLK_IOI_CENTER bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - BUFIO2:ENABLE BUFIO1:ENABLE - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] BUFIO3:ENABLE IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - BUFIO0:ENABLE - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:ENABLE 0.19.12
BUFIO1:ENABLE 0.19.13
BUFIO2:ENABLE 0.18.13
BUFIO3:ENABLE 0.14.12
DCI:CASCADE_FROM_ABOVE 0.47.14
DCI:CASCADE_FROM_BELOW 0.47.13
DCI:ENABLE 0.46.14
DCI:QUIET 0.48.14
IOCLK:BUF.HCLK0 0.16.12
IOCLK:BUF.HCLK1 0.15.12
IOCLK:BUF.HCLK2 0.17.12
IOCLK:BUF.HCLK3 0.11.13
IOCLK:BUF.HCLK4 0.12.13
IOCLK:BUF.HCLK5 0.28.12
IOCLK:BUF.HCLK6 0.29.12
IOCLK:BUF.HCLK7 0.29.13
IOCLK:BUF.HCLK8 0.28.13
IOCLK:BUF.HCLK9 0.28.14
IOCLK:BUF.RCLK0 0.9.13
IOCLK:BUF.RCLK1 0.12.12
IOCLK:BUF.RCLK2 0.27.12
IOCLK:BUF.RCLK3 0.9.15
IOCLK:ENABLE.RCLK0 0.18.15
IOCLK:ENABLE.RCLK1 0.14.14
IOCLK:ENABLE.RCLK2 0.15.13
IOCLK:ENABLE.RCLK3 0.16.13
non-inverted [0]
DCI:LVDIV2 0.53.15 0.53.12 0.52.12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.51.15 0.48.12 0.49.12 0.49.13 0.48.13
DCI:PMASK_TERM_SPLIT 0.49.15 0.48.15 0.47.12 0.46.12 0.46.13
DCI:PMASK_TERM_VCC 0.50.13 0.51.13 0.51.14 0.50.14 0.50.15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.52.13 0.52.14
DCI:TEST_ENABLE 0.53.13 0.49.14
IOCLK:IOCLK_ENABLE 0.15.15 0.15.14
non-inverted [1] [0]
DCI:PREF 0.52.15 0.53.14 0.50.12 0.51.12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.36.14 0.37.14 0.36.13 0.36.12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.10.15 0.11.15 0.12.14 0.13.14 0.13.12 0.26.14 0.10.13 0.26.13 0.27.13 0.10.12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.39.15 0.38.15 0.38.13 0.38.12 0.39.12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.32.12 0.33.12 0.33.13 0.32.13 0.35.12 0.34.12 0.34.13 0.35.13 0.35.14 0.34.14 0.34.15 0.35.15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_IOI_BOTCEN

Cells: 2

Bel IOCLK

virtex5 HCLK_IOI_BOTCEN bel IOCLK
PinDirectionWires

Bel BUFIO2

virtex5 HCLK_IOI_BOTCEN bel BUFIO2
PinDirectionWires

Bel BUFIO3

virtex5 HCLK_IOI_BOTCEN bel BUFIO3
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI_BOTCEN bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL1:OUT18.TMIN
OUTN1outputTCELL1:OUT23.TMIN
OUTN65outputTCELL1:OUT16.TMIN
RDYoutputTCELL1:OUT22.TMIN
RSTinputTCELL0:IMUX.IMUX0
UPPULSEOUToutputTCELL1:OUT17.TMIN

Bel DCI

virtex5 HCLK_IOI_BOTCEN bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL1:OUT8.TMIN
DCIADDRESS1outputTCELL1:OUT20.TMIN
DCIADDRESS2outputTCELL1:OUT22.TMIN
DCIDATAoutputTCELL0:OUT22.TMIN
DCIDONEoutputTCELL0:OUT20.TMIN
DCIIOUPDATEoutputTCELL0:OUT8.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT15.TMIN
DCISCLKoutputTCELL0:OUT20.TMIN
TSTCLKinputTCELL1:IMUX.BYP2.SITE
TSTHLNinputTCELL1:IMUX.BYP6.SITE
TSTHLPinputTCELL1:IMUX.BYP3.SITE
TSTRSTinputTCELL1:IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI_BOTCEN bel wires
WirePins
TCELL0:IMUX.IMUX0IDELAYCTRL.RST
TCELL0:OUT8.TMINDCI.DCIIOUPDATE
TCELL0:OUT15.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT20.TMINDCI.DCIDONE, DCI.DCISCLK
TCELL0:OUT22.TMINDCI.DCIDATA
TCELL1:IMUX.BYP0.SITEDCI.TSTRST
TCELL1:IMUX.BYP2.SITEDCI.TSTCLK
TCELL1:IMUX.BYP3.SITEDCI.TSTHLP
TCELL1:IMUX.BYP6.SITEDCI.TSTHLN
TCELL1:OUT8.TMINDCI.DCIADDRESS0
TCELL1:OUT16.TMINIDELAYCTRL.OUTN65
TCELL1:OUT17.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT18.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT20.TMINDCI.DCIADDRESS1
TCELL1:OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2
TCELL1:OUT23.TMINIDELAYCTRL.OUTN1

Bitstream

virtex5 HCLK_IOI_BOTCEN bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - BUFIO2:ENABLE - - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] BUFIO3:ENABLE IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - - - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO2:ENABLE 0.18.13
BUFIO3:ENABLE 0.14.12
DCI:CASCADE_FROM_ABOVE 0.47.14
DCI:CASCADE_FROM_BELOW 0.47.13
DCI:ENABLE 0.46.14
DCI:QUIET 0.48.14
IOCLK:BUF.HCLK0 0.16.12
IOCLK:BUF.HCLK1 0.15.12
IOCLK:BUF.HCLK2 0.17.12
IOCLK:BUF.HCLK3 0.11.13
IOCLK:BUF.HCLK4 0.12.13
IOCLK:BUF.HCLK5 0.28.12
IOCLK:BUF.HCLK6 0.29.12
IOCLK:BUF.HCLK7 0.29.13
IOCLK:BUF.HCLK8 0.28.13
IOCLK:BUF.HCLK9 0.28.14
IOCLK:BUF.RCLK0 0.9.13
IOCLK:BUF.RCLK1 0.12.12
IOCLK:BUF.RCLK2 0.27.12
IOCLK:BUF.RCLK3 0.9.15
IOCLK:ENABLE.RCLK0 0.18.15
IOCLK:ENABLE.RCLK1 0.14.14
IOCLK:ENABLE.RCLK2 0.15.13
IOCLK:ENABLE.RCLK3 0.16.13
non-inverted [0]
DCI:LVDIV2 0.53.15 0.53.12 0.52.12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.51.15 0.48.12 0.49.12 0.49.13 0.48.13
DCI:PMASK_TERM_SPLIT 0.49.15 0.48.15 0.47.12 0.46.12 0.46.13
DCI:PMASK_TERM_VCC 0.50.13 0.51.13 0.51.14 0.50.14 0.50.15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.52.13 0.52.14
DCI:TEST_ENABLE 0.53.13 0.49.14
IOCLK:IOCLK_ENABLE 0.15.15 0.15.14
non-inverted [1] [0]
DCI:PREF 0.52.15 0.53.14 0.50.12 0.51.12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.36.14 0.37.14 0.36.13 0.36.12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.10.15 0.11.15 0.12.14 0.13.14 0.13.12 0.26.14 0.10.13 0.26.13 0.27.13 0.10.12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.39.15 0.38.15 0.38.13 0.38.12 0.39.12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.32.12 0.33.12 0.33.13 0.32.13 0.35.12 0.34.12 0.34.13 0.35.13 0.35.14 0.34.14 0.34.15 0.35.15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_IOI_TOPCEN

Cells: 2

Bel IOCLK

virtex5 HCLK_IOI_TOPCEN bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex5 HCLK_IOI_TOPCEN bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex5 HCLK_IOI_TOPCEN bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI_TOPCEN bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL0:OUT23.TMIN
OUTN1outputTCELL0:OUT20.TMIN
OUTN65outputTCELL0:OUT8.TMIN
RDYoutputTCELL0:OUT22.TMIN
RSTinputTCELL1:IMUX.IMUX6
UPPULSEOUToutputTCELL0:OUT15.TMIN

Bel DCI

virtex5 HCLK_IOI_TOPCEN bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL0:OUT8.TMIN
DCIADDRESS1outputTCELL0:OUT20.TMIN
DCIADDRESS2outputTCELL0:OUT22.TMIN
DCIDATAoutputTCELL0:OUT22.TMIN
DCIDONEoutputTCELL0:OUT20.TMIN
DCIIOUPDATEoutputTCELL0:OUT8.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT15.TMIN
DCISCLKoutputTCELL0:OUT20.TMIN
TSTCLKinputTCELL0:IMUX.BYP2.SITE
TSTHLNinputTCELL0:IMUX.BYP6.SITE
TSTHLPinputTCELL0:IMUX.BYP3.SITE
TSTRSTinputTCELL0:IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI_TOPCEN bel wires
WirePins
TCELL0:IMUX.BYP0.SITEDCI.TSTRST
TCELL0:IMUX.BYP2.SITEDCI.TSTCLK
TCELL0:IMUX.BYP3.SITEDCI.TSTHLP
TCELL0:IMUX.BYP6.SITEDCI.TSTHLN
TCELL0:OUT8.TMINIDELAYCTRL.OUTN65, DCI.DCIADDRESS0, DCI.DCIIOUPDATE
TCELL0:OUT15.TMINIDELAYCTRL.UPPULSEOUT, DCI.DCIREFIOUPDATE
TCELL0:OUT20.TMINIDELAYCTRL.OUTN1, DCI.DCIADDRESS1, DCI.DCIDONE, DCI.DCISCLK
TCELL0:OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2, DCI.DCIDATA
TCELL0:OUT23.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:IMUX.IMUX6IDELAYCTRL.RST

Bitstream

virtex5 HCLK_IOI_TOPCEN bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - SYSMON:ENABLE - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - - BUFIO1:ENABLE - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - BUFIO0:ENABLE - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:ENABLE 0.19.12
BUFIO1:ENABLE 0.19.13
DCI:CASCADE_FROM_ABOVE 0.47.14
DCI:CASCADE_FROM_BELOW 0.47.13
DCI:ENABLE 0.46.14
DCI:QUIET 0.48.14
IOCLK:BUF.HCLK0 0.16.12
IOCLK:BUF.HCLK1 0.15.12
IOCLK:BUF.HCLK2 0.17.12
IOCLK:BUF.HCLK3 0.11.13
IOCLK:BUF.HCLK4 0.12.13
IOCLK:BUF.HCLK5 0.28.12
IOCLK:BUF.HCLK6 0.29.12
IOCLK:BUF.HCLK7 0.29.13
IOCLK:BUF.HCLK8 0.28.13
IOCLK:BUF.HCLK9 0.28.14
IOCLK:BUF.RCLK0 0.9.13
IOCLK:BUF.RCLK1 0.12.12
IOCLK:BUF.RCLK2 0.27.12
IOCLK:BUF.RCLK3 0.9.15
IOCLK:ENABLE.RCLK0 0.18.15
IOCLK:ENABLE.RCLK1 0.14.14
IOCLK:ENABLE.RCLK2 0.15.13
IOCLK:ENABLE.RCLK3 0.16.13
SYSMON:ENABLE 0.27.15
non-inverted [0]
DCI:LVDIV2 0.53.15 0.53.12 0.52.12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.51.15 0.48.12 0.49.12 0.49.13 0.48.13
DCI:PMASK_TERM_SPLIT 0.49.15 0.48.15 0.47.12 0.46.12 0.46.13
DCI:PMASK_TERM_VCC 0.50.13 0.51.13 0.51.14 0.50.14 0.50.15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.52.13 0.52.14
DCI:TEST_ENABLE 0.53.13 0.49.14
IOCLK:IOCLK_ENABLE 0.15.15 0.15.14
non-inverted [1] [0]
DCI:PREF 0.52.15 0.53.14 0.50.12 0.51.12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.36.14 0.37.14 0.36.13 0.36.12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.10.15 0.11.15 0.12.14 0.13.14 0.13.12 0.26.14 0.10.13 0.26.13 0.27.13 0.10.12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.39.15 0.38.15 0.38.13 0.38.12 0.39.12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.32.12 0.33.12 0.33.13 0.32.13 0.35.12 0.34.12 0.34.13 0.35.13 0.35.14 0.34.14 0.34.15 0.35.15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_IOI_CMT

Cells: 2

Bel IOCLK

virtex5 HCLK_IOI_CMT bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex5 HCLK_IOI_CMT bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex5 HCLK_IOI_CMT bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_IOI_CMT bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL0:OUT23.TMIN
OUTN1outputTCELL0:OUT20.TMIN
OUTN65outputTCELL0:OUT8.TMIN
RDYoutputTCELL0:OUT22.TMIN
RSTinputTCELL1:IMUX.IMUX6
UPPULSEOUToutputTCELL0:OUT15.TMIN

Bel DCI

virtex5 HCLK_IOI_CMT bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL0:OUT8.TMIN
DCIADDRESS1outputTCELL0:OUT20.TMIN
DCIADDRESS2outputTCELL0:OUT22.TMIN
DCIDATAoutputTCELL0:OUT22.TMIN
DCIDONEoutputTCELL0:OUT20.TMIN
DCIIOUPDATEoutputTCELL0:OUT8.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT15.TMIN
DCISCLKoutputTCELL0:OUT20.TMIN
TSTCLKinputTCELL0:IMUX.BYP2.SITE
TSTHLNinputTCELL0:IMUX.BYP6.SITE
TSTHLPinputTCELL0:IMUX.BYP3.SITE
TSTRSTinputTCELL0:IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_IOI_CMT bel wires
WirePins
TCELL0:IMUX.BYP0.SITEDCI.TSTRST
TCELL0:IMUX.BYP2.SITEDCI.TSTCLK
TCELL0:IMUX.BYP3.SITEDCI.TSTHLP
TCELL0:IMUX.BYP6.SITEDCI.TSTHLN
TCELL0:OUT8.TMINIDELAYCTRL.OUTN65, DCI.DCIADDRESS0, DCI.DCIIOUPDATE
TCELL0:OUT15.TMINIDELAYCTRL.UPPULSEOUT, DCI.DCIREFIOUPDATE
TCELL0:OUT20.TMINIDELAYCTRL.OUTN1, DCI.DCIADDRESS1, DCI.DCIDONE, DCI.DCISCLK
TCELL0:OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2, DCI.DCIDATA
TCELL0:OUT23.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:IMUX.IMUX6IDELAYCTRL.RST

Bitstream

virtex5 HCLK_IOI_CMT bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - - BUFIO1:ENABLE - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - BUFIO0:ENABLE - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:ENABLE 0.19.12
BUFIO1:ENABLE 0.19.13
DCI:CASCADE_FROM_ABOVE 0.47.14
DCI:CASCADE_FROM_BELOW 0.47.13
DCI:ENABLE 0.46.14
DCI:QUIET 0.48.14
IOCLK:BUF.HCLK0 0.16.12
IOCLK:BUF.HCLK1 0.15.12
IOCLK:BUF.HCLK2 0.17.12
IOCLK:BUF.HCLK3 0.11.13
IOCLK:BUF.HCLK4 0.12.13
IOCLK:BUF.HCLK5 0.28.12
IOCLK:BUF.HCLK6 0.29.12
IOCLK:BUF.HCLK7 0.29.13
IOCLK:BUF.HCLK8 0.28.13
IOCLK:BUF.HCLK9 0.28.14
IOCLK:BUF.RCLK0 0.9.13
IOCLK:BUF.RCLK1 0.12.12
IOCLK:BUF.RCLK2 0.27.12
IOCLK:BUF.RCLK3 0.9.15
IOCLK:ENABLE.RCLK0 0.18.15
IOCLK:ENABLE.RCLK1 0.14.14
IOCLK:ENABLE.RCLK2 0.15.13
IOCLK:ENABLE.RCLK3 0.16.13
non-inverted [0]
DCI:LVDIV2 0.53.15 0.53.12 0.52.12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.51.15 0.48.12 0.49.12 0.49.13 0.48.13
DCI:PMASK_TERM_SPLIT 0.49.15 0.48.15 0.47.12 0.46.12 0.46.13
DCI:PMASK_TERM_VCC 0.50.13 0.51.13 0.51.14 0.50.14 0.50.15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.52.13 0.52.14
DCI:TEST_ENABLE 0.53.13 0.49.14
IOCLK:IOCLK_ENABLE 0.15.15 0.15.14
non-inverted [1] [0]
DCI:PREF 0.52.15 0.53.14 0.50.12 0.51.12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.36.14 0.37.14 0.36.13 0.36.12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.10.15 0.11.15 0.12.14 0.13.14 0.13.12 0.26.14 0.10.13 0.26.13 0.27.13 0.10.12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.39.15 0.38.15 0.38.13 0.38.12 0.39.12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.32.12 0.33.12 0.33.13 0.32.13 0.35.12 0.34.12 0.34.13 0.35.13 0.35.14 0.34.14 0.34.15 0.35.15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_CMT_IOI

Cells: 2

Bel IOCLK

virtex5 HCLK_CMT_IOI bel IOCLK
PinDirectionWires

Bel BUFIO2

virtex5 HCLK_CMT_IOI bel BUFIO2
PinDirectionWires

Bel BUFIO3

virtex5 HCLK_CMT_IOI bel BUFIO3
PinDirectionWires

Bel IDELAYCTRL

virtex5 HCLK_CMT_IOI bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL1:OUT18.TMIN
OUTN1outputTCELL1:OUT23.TMIN
OUTN65outputTCELL1:OUT16.TMIN
RDYoutputTCELL1:OUT22.TMIN
RSTinputTCELL0:IMUX.IMUX0
UPPULSEOUToutputTCELL1:OUT17.TMIN

Bel DCI

virtex5 HCLK_CMT_IOI bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL1:OUT8.TMIN
DCIADDRESS1outputTCELL1:OUT20.TMIN
DCIADDRESS2outputTCELL1:OUT22.TMIN
DCIDATAoutputTCELL0:OUT22.TMIN
DCIDONEoutputTCELL0:OUT20.TMIN
DCIIOUPDATEoutputTCELL0:OUT8.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT15.TMIN
DCISCLKoutputTCELL0:OUT20.TMIN
TSTCLKinputTCELL1:IMUX.BYP2.SITE
TSTHLNinputTCELL1:IMUX.BYP6.SITE
TSTHLPinputTCELL1:IMUX.BYP3.SITE
TSTRSTinputTCELL1:IMUX.BYP0.SITE

Bel wires

virtex5 HCLK_CMT_IOI bel wires
WirePins
TCELL0:IMUX.IMUX0IDELAYCTRL.RST
TCELL0:OUT8.TMINDCI.DCIIOUPDATE
TCELL0:OUT15.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT20.TMINDCI.DCIDONE, DCI.DCISCLK
TCELL0:OUT22.TMINDCI.DCIDATA
TCELL1:IMUX.BYP0.SITEDCI.TSTRST
TCELL1:IMUX.BYP2.SITEDCI.TSTCLK
TCELL1:IMUX.BYP3.SITEDCI.TSTHLP
TCELL1:IMUX.BYP6.SITEDCI.TSTHLN
TCELL1:OUT8.TMINDCI.DCIADDRESS0
TCELL1:OUT16.TMINIDELAYCTRL.OUTN65
TCELL1:OUT17.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT18.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT20.TMINDCI.DCIADDRESS1
TCELL1:OUT22.TMINIDELAYCTRL.RDY, DCI.DCIADDRESS2
TCELL1:OUT23.TMINIDELAYCTRL.OUTN1

Bitstream

virtex5 HCLK_CMT_IOI bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
15 - - - - - - - - - IOCLK:BUF.RCLK3 IDELAYCTRL:MUX.REFCLK[9] IDELAYCTRL:MUX.REFCLK[8] - - - IOCLK:IOCLK_ENABLE[1] - - IOCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - LVDS:LVDSBIAS[1] LVDS:LVDSBIAS[0] - - INTERNAL_VREF:VREF[3] INTERNAL_VREF:VREF[4] - - - - - - - - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:PMASK_TERM_VCC[0] DCI:NMASK_TERM_SPLIT[4] DCI:PREF[3] DCI:LVDIV2[2]
14 - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] IDELAYCTRL:MUX.REFCLK[6] IOCLK:ENABLE.RCLK1 IOCLK:IOCLK_ENABLE[0] - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] - IOCLK:BUF.HCLK9 - - - - - LVDS:LVDSBIAS[2] LVDS:LVDSBIAS[3] IDELAYCTRL:MODE[3] IDELAYCTRL:MODE[2] - - - - - - - - DCI:ENABLE DCI:CASCADE_FROM_ABOVE DCI:QUIET DCI:TEST_ENABLE[0] DCI:PMASK_TERM_VCC[1] DCI:PMASK_TERM_VCC[2] DCI:NREF[0] DCI:PREF[2]
13 - - - - - - - - - IOCLK:BUF.RCLK0 IDELAYCTRL:MUX.REFCLK[3] IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK4 - - IOCLK:ENABLE.RCLK2 IOCLK:ENABLE.RCLK3 - BUFIO2:ENABLE - - - - - - - IDELAYCTRL:MUX.REFCLK[2] IDELAYCTRL:MUX.REFCLK[1] IOCLK:BUF.HCLK8 IOCLK:BUF.HCLK7 - - LVDS:LVDSBIAS[8] LVDS:LVDSBIAS[9] LVDS:LVDSBIAS[5] LVDS:LVDSBIAS[4] IDELAYCTRL:MODE[1] - INTERNAL_VREF:VREF[2] - - - - - - - DCI:PMASK_TERM_SPLIT[0] DCI:CASCADE_FROM_BELOW DCI:NMASK_TERM_SPLIT[0] DCI:NMASK_TERM_SPLIT[1] DCI:PMASK_TERM_VCC[4] DCI:PMASK_TERM_VCC[3] DCI:NREF[1] DCI:TEST_ENABLE[1]
12 - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] - IOCLK:BUF.RCLK1 IDELAYCTRL:MUX.REFCLK[5] BUFIO3:ENABLE IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK2 - - - - - - - - - IOCLK:BUF.RCLK2 IOCLK:BUF.HCLK5 IOCLK:BUF.HCLK6 - - LVDS:LVDSBIAS[11] LVDS:LVDSBIAS[10] LVDS:LVDSBIAS[6] LVDS:LVDSBIAS[7] IDELAYCTRL:MODE[0] - INTERNAL_VREF:VREF[1] INTERNAL_VREF:VREF[0] - - - - - - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[3] DCI:NMASK_TERM_SPLIT[2] DCI:PREF[1] DCI:PREF[0] DCI:LVDIV2[0] DCI:LVDIV2[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO2:ENABLE 0.18.13
BUFIO3:ENABLE 0.14.12
DCI:CASCADE_FROM_ABOVE 0.47.14
DCI:CASCADE_FROM_BELOW 0.47.13
DCI:ENABLE 0.46.14
DCI:QUIET 0.48.14
IOCLK:BUF.HCLK0 0.16.12
IOCLK:BUF.HCLK1 0.15.12
IOCLK:BUF.HCLK2 0.17.12
IOCLK:BUF.HCLK3 0.11.13
IOCLK:BUF.HCLK4 0.12.13
IOCLK:BUF.HCLK5 0.28.12
IOCLK:BUF.HCLK6 0.29.12
IOCLK:BUF.HCLK7 0.29.13
IOCLK:BUF.HCLK8 0.28.13
IOCLK:BUF.HCLK9 0.28.14
IOCLK:BUF.RCLK0 0.9.13
IOCLK:BUF.RCLK1 0.12.12
IOCLK:BUF.RCLK2 0.27.12
IOCLK:BUF.RCLK3 0.9.15
IOCLK:ENABLE.RCLK0 0.18.15
IOCLK:ENABLE.RCLK1 0.14.14
IOCLK:ENABLE.RCLK2 0.15.13
IOCLK:ENABLE.RCLK3 0.16.13
non-inverted [0]
DCI:LVDIV2 0.53.15 0.53.12 0.52.12
non-inverted [2] [1] [0]
DCI:NMASK_TERM_SPLIT 0.51.15 0.48.12 0.49.12 0.49.13 0.48.13
DCI:PMASK_TERM_SPLIT 0.49.15 0.48.15 0.47.12 0.46.12 0.46.13
DCI:PMASK_TERM_VCC 0.50.13 0.51.13 0.51.14 0.50.14 0.50.15
non-inverted [4] [3] [2] [1] [0]
DCI:NREF 0.52.13 0.52.14
DCI:TEST_ENABLE 0.53.13 0.49.14
IOCLK:IOCLK_ENABLE 0.15.15 0.15.14
non-inverted [1] [0]
DCI:PREF 0.52.15 0.53.14 0.50.12 0.51.12
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MODE 0.36.14 0.37.14 0.36.13 0.36.12
NONE 0 0 0 0
FULL 0 1 1 1
DEFAULT_ONLY 1 0 1 1
IDELAYCTRL:MUX.REFCLK 0.10.15 0.11.15 0.12.14 0.13.14 0.13.12 0.26.14 0.10.13 0.26.13 0.27.13 0.10.12
NONE 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0
HCLK8 0 1 0 0 0 0 0 0 0 0
HCLK9 1 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.39.15 0.38.15 0.38.13 0.38.12 0.39.12
OFF 0 0 0 0 0
750 0 0 0 1 1
900 0 0 1 0 1
1080 0 1 0 0 1
1250 1 0 0 0 1
LVDS:LVDSBIAS 0.32.12 0.33.12 0.33.13 0.32.13 0.35.12 0.34.12 0.34.13 0.35.13 0.35.14 0.34.14 0.34.15 0.35.15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile HCLK_CMT

Cells: 0

Bel HCLK_CMT_HCLK

virtex5 HCLK_CMT bel HCLK_CMT_HCLK
PinDirectionWires

Bel HCLK_CMT_GIOB

virtex5 HCLK_CMT bel HCLK_CMT_GIOB
PinDirectionWires

Bitstream

virtex5 HCLK_CMT bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
15 - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_CMT:DRP_MASK - - - - - - - - - - - - HCLK_CMT:BUF.HCLK9 HCLK_CMT:BUF.HCLK5 HCLK_CMT:BUF.HCLK1 HCLK_CMT:BUF.GIOB7 HCLK_CMT:BUF.GIOB3
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_CMT:BUF.HCLK8 HCLK_CMT:BUF.HCLK4 HCLK_CMT:BUF.HCLK0 HCLK_CMT:BUF.GIOB6 HCLK_CMT:BUF.GIOB2
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_CMT:BUF.HCLK7 HCLK_CMT:BUF.HCLK3 HCLK_CMT:BUF.GIOB9 HCLK_CMT:BUF.GIOB5 HCLK_CMT:BUF.GIOB1
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_CMT:BUF.HCLK6 HCLK_CMT:BUF.HCLK2 HCLK_CMT:BUF.GIOB8 HCLK_CMT:BUF.GIOB4 HCLK_CMT:BUF.GIOB0
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HCLK_CMT:BUF.GIOB0 0.44.12
HCLK_CMT:BUF.GIOB1 0.44.13
HCLK_CMT:BUF.GIOB2 0.44.14
HCLK_CMT:BUF.GIOB3 0.44.15
HCLK_CMT:BUF.GIOB4 0.43.12
HCLK_CMT:BUF.GIOB5 0.43.13
HCLK_CMT:BUF.GIOB6 0.43.14
HCLK_CMT:BUF.GIOB7 0.43.15
HCLK_CMT:BUF.GIOB8 0.42.12
HCLK_CMT:BUF.GIOB9 0.42.13
HCLK_CMT:BUF.HCLK0 0.42.14
HCLK_CMT:BUF.HCLK1 0.42.15
HCLK_CMT:BUF.HCLK2 0.41.12
HCLK_CMT:BUF.HCLK3 0.41.13
HCLK_CMT:BUF.HCLK4 0.41.14
HCLK_CMT:BUF.HCLK5 0.41.15
HCLK_CMT:BUF.HCLK6 0.40.12
HCLK_CMT:BUF.HCLK7 0.40.13
HCLK_CMT:BUF.HCLK8 0.40.14
HCLK_CMT:BUF.HCLK9 0.40.15
HCLK_CMT:DRP_MASK 0.27.15
non-inverted [0]