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DSP

Tile DSP

Cells: 5

Bels DSP_V5

virtex5 DSP bel DSP_V5 pins
PinDirectionDSP[0]DSP[1]
CLKinCELL[1].IMUX_CLK[0] invert by !MAIN[1][26][20]CELL[3].IMUX_CLK[0] invert by !MAIN[3][26][52]
A[0]inCELL[0].IMUX_IMUX[0]CELL[0].IMUX_IMUX[24]
A[1]inCELL[0].IMUX_IMUX[6]CELL[0].IMUX_IMUX[30]
A[2]inCELL[0].IMUX_IMUX[12]CELL[0].IMUX_IMUX[36]
A[3]inCELL[0].IMUX_IMUX[18]CELL[0].IMUX_IMUX[42]
A[4]inCELL[1].IMUX_IMUX[0]CELL[1].IMUX_IMUX[24]
A[5]inCELL[1].IMUX_IMUX[6]CELL[1].IMUX_IMUX[30]
A[6]inCELL[1].IMUX_IMUX[12]CELL[1].IMUX_IMUX[36]
A[7]inCELL[1].IMUX_IMUX[18]CELL[1].IMUX_IMUX[42]
A[8]inCELL[2].IMUX_IMUX[0]CELL[2].IMUX_IMUX[24]
A[9]inCELL[2].IMUX_IMUX[6]CELL[2].IMUX_IMUX[30]
A[10]inCELL[2].IMUX_IMUX[12]CELL[2].IMUX_IMUX[36]
A[11]inCELL[2].IMUX_IMUX[18]CELL[2].IMUX_IMUX[42]
A[12]inCELL[3].IMUX_IMUX[0]CELL[3].IMUX_IMUX[24]
A[13]inCELL[3].IMUX_IMUX[6]CELL[3].IMUX_IMUX[30]
A[14]inCELL[3].IMUX_IMUX[12]CELL[3].IMUX_IMUX[36]
A[15]inCELL[3].IMUX_IMUX[18]CELL[3].IMUX_IMUX[42]
A[16]inCELL[4].IMUX_IMUX[0]CELL[4].IMUX_IMUX[24]
A[17]inCELL[4].IMUX_IMUX[6]CELL[4].IMUX_IMUX[30]
A[18]inCELL[4].IMUX_IMUX[12]CELL[4].IMUX_IMUX[36]
A[19]inCELL[4].IMUX_IMUX[18]CELL[4].IMUX_IMUX[42]
A[20]inCELL[4].IMUX_IMUX[4]CELL[4].IMUX_IMUX[5]
A[21]inCELL[4].IMUX_IMUX[10]CELL[4].IMUX_IMUX[11]
A[22]inCELL[4].IMUX_IMUX[16]CELL[4].IMUX_IMUX[17]
A[23]inCELL[4].IMUX_IMUX[22]CELL[4].IMUX_IMUX[23]
A[24]inCELL[4].IMUX_IMUX[28]CELL[4].IMUX_IMUX[29]
A[25]inCELL[4].IMUX_IMUX[34]CELL[4].IMUX_IMUX[35]
A[26]inCELL[4].IMUX_IMUX[40]CELL[4].IMUX_IMUX[41]
A[27]inCELL[4].IMUX_IMUX[46]CELL[4].IMUX_IMUX[47]
A[28]inCELL[4].IMUX_IMUX[13]CELL[4].IMUX_IMUX[37]
A[29]inCELL[4].IMUX_IMUX[19]CELL[4].IMUX_IMUX[43]
RSTAinCELL[1].IMUX_CTRL_SITE[3]CELL[4].IMUX_CTRL_SITE[3]
CEA1inCELL[0].IMUX_IMUX[17]CELL[0].IMUX_IMUX[41]
CEA2inCELL[0].IMUX_IMUX[23]CELL[0].IMUX_IMUX[47]
B[0]inCELL[0].IMUX_IMUX[1]CELL[0].IMUX_IMUX[25]
B[1]inCELL[0].IMUX_IMUX[7]CELL[0].IMUX_IMUX[31]
B[2]inCELL[0].IMUX_IMUX[13]CELL[0].IMUX_IMUX[37]
B[3]inCELL[0].IMUX_IMUX[19]CELL[0].IMUX_IMUX[43]
B[4]inCELL[1].IMUX_IMUX[1]CELL[1].IMUX_IMUX[25]
B[5]inCELL[1].IMUX_IMUX[7]CELL[1].IMUX_IMUX[31]
B[6]inCELL[1].IMUX_IMUX[13]CELL[1].IMUX_IMUX[37]
B[7]inCELL[1].IMUX_IMUX[19]CELL[1].IMUX_IMUX[43]
B[8]inCELL[2].IMUX_IMUX[1]CELL[2].IMUX_IMUX[25]
B[9]inCELL[2].IMUX_IMUX[7]CELL[2].IMUX_IMUX[31]
B[10]inCELL[2].IMUX_IMUX[13]CELL[2].IMUX_IMUX[37]
B[11]inCELL[2].IMUX_IMUX[19]CELL[2].IMUX_IMUX[43]
B[12]inCELL[3].IMUX_IMUX[1]CELL[3].IMUX_IMUX[25]
B[13]inCELL[3].IMUX_IMUX[7]CELL[3].IMUX_IMUX[31]
B[14]inCELL[3].IMUX_IMUX[13]CELL[3].IMUX_IMUX[37]
B[15]inCELL[3].IMUX_IMUX[19]CELL[3].IMUX_IMUX[43]
B[16]inCELL[4].IMUX_IMUX[1]CELL[4].IMUX_IMUX[25]
B[17]inCELL[4].IMUX_IMUX[7]CELL[4].IMUX_IMUX[31]
RSTBinCELL[1].IMUX_CTRL_SITE[2]CELL[4].IMUX_CTRL_SITE[2]
CEB1inCELL[0].IMUX_IMUX[5]CELL[0].IMUX_IMUX[29]
CEB2inCELL[0].IMUX_IMUX[11]CELL[0].IMUX_IMUX[35]
C[0]inCELL[0].IMUX_IMUX[2]CELL[0].IMUX_IMUX[26]
C[1]inCELL[0].IMUX_IMUX[8]CELL[0].IMUX_IMUX[32]
C[2]inCELL[0].IMUX_IMUX[14]CELL[0].IMUX_IMUX[38]
C[3]inCELL[0].IMUX_IMUX[20]CELL[0].IMUX_IMUX[44]
C[4]inCELL[1].IMUX_IMUX[2]CELL[1].IMUX_IMUX[26]
C[5]inCELL[1].IMUX_IMUX[8]CELL[1].IMUX_IMUX[32]
C[6]inCELL[1].IMUX_IMUX[14]CELL[1].IMUX_IMUX[38]
C[7]inCELL[1].IMUX_IMUX[20]CELL[1].IMUX_IMUX[44]
C[8]inCELL[2].IMUX_IMUX[2]CELL[2].IMUX_IMUX[26]
C[9]inCELL[2].IMUX_IMUX[8]CELL[2].IMUX_IMUX[32]
C[10]inCELL[2].IMUX_IMUX[14]CELL[2].IMUX_IMUX[38]
C[11]inCELL[2].IMUX_IMUX[20]CELL[2].IMUX_IMUX[44]
C[12]inCELL[3].IMUX_IMUX[2]CELL[3].IMUX_IMUX[26]
C[13]inCELL[3].IMUX_IMUX[8]CELL[3].IMUX_IMUX[32]
C[14]inCELL[3].IMUX_IMUX[14]CELL[3].IMUX_IMUX[38]
C[15]inCELL[3].IMUX_IMUX[20]CELL[3].IMUX_IMUX[44]
C[16]inCELL[4].IMUX_IMUX[2]CELL[4].IMUX_IMUX[26]
C[17]inCELL[4].IMUX_IMUX[8]CELL[4].IMUX_IMUX[32]
C[18]inCELL[4].IMUX_IMUX[14]CELL[4].IMUX_IMUX[38]
C[19]inCELL[4].IMUX_IMUX[20]CELL[4].IMUX_IMUX[44]
C[20]inCELL[0].IMUX_IMUX[3]CELL[0].IMUX_IMUX[27]
C[21]inCELL[0].IMUX_IMUX[9]CELL[0].IMUX_IMUX[33]
C[22]inCELL[0].IMUX_IMUX[15]CELL[0].IMUX_IMUX[39]
C[23]inCELL[0].IMUX_IMUX[21]CELL[0].IMUX_IMUX[45]
C[24]inCELL[1].IMUX_IMUX[3]CELL[1].IMUX_IMUX[27]
C[25]inCELL[1].IMUX_IMUX[9]CELL[1].IMUX_IMUX[33]
C[26]inCELL[1].IMUX_IMUX[15]CELL[1].IMUX_IMUX[39]
C[27]inCELL[1].IMUX_IMUX[21]CELL[1].IMUX_IMUX[45]
C[28]inCELL[2].IMUX_IMUX[3]CELL[2].IMUX_IMUX[27]
C[29]inCELL[2].IMUX_IMUX[9]CELL[2].IMUX_IMUX[33]
C[30]inCELL[2].IMUX_IMUX[15]CELL[2].IMUX_IMUX[39]
C[31]inCELL[2].IMUX_IMUX[21]CELL[2].IMUX_IMUX[45]
C[32]inCELL[3].IMUX_IMUX[3]CELL[3].IMUX_IMUX[27]
C[33]inCELL[3].IMUX_IMUX[9]CELL[3].IMUX_IMUX[33]
C[34]inCELL[3].IMUX_IMUX[15]CELL[3].IMUX_IMUX[39]
C[35]inCELL[3].IMUX_IMUX[21]CELL[3].IMUX_IMUX[45]
C[36]inCELL[4].IMUX_IMUX[3]CELL[4].IMUX_IMUX[27]
C[37]inCELL[4].IMUX_IMUX[9]CELL[4].IMUX_IMUX[33]
C[38]inCELL[4].IMUX_IMUX[15]CELL[4].IMUX_IMUX[39]
C[39]inCELL[4].IMUX_IMUX[21]CELL[4].IMUX_IMUX[45]
C[40]inCELL[0].IMUX_IMUX[4]CELL[0].IMUX_IMUX[28]
C[41]inCELL[0].IMUX_IMUX[10]CELL[0].IMUX_IMUX[34]
C[42]inCELL[0].IMUX_IMUX[16]CELL[0].IMUX_IMUX[40]
C[43]inCELL[0].IMUX_IMUX[22]CELL[0].IMUX_IMUX[46]
C[44]inCELL[1].IMUX_IMUX[4]CELL[1].IMUX_IMUX[28]
C[45]inCELL[1].IMUX_IMUX[10]CELL[1].IMUX_IMUX[34]
C[46]inCELL[1].IMUX_IMUX[16]CELL[1].IMUX_IMUX[40]
C[47]inCELL[1].IMUX_IMUX[22]CELL[1].IMUX_IMUX[46]
RSTCinCELL[0].IMUX_CTRL_SITE[3]CELL[3].IMUX_CTRL_SITE[3]
CECinCELL[2].IMUX_IMUX[23]CELL[2].IMUX_IMUX[47]
RSTMinCELL[1].IMUX_CTRL_SITE[1]CELL[4].IMUX_CTRL_SITE[1]
CEMinCELL[2].IMUX_CTRL_SITE[2]CELL[2].IMUX_CTRL_SITE[3]
OPMODE[0]inCELL[3].IMUX_IMUX[4] invert by !MAIN[1][27][60]CELL[3].IMUX_IMUX[28] invert by !MAIN[4][27][40]
OPMODE[1]inCELL[3].IMUX_IMUX[10] invert by !MAIN[1][27][61]CELL[3].IMUX_IMUX[34] invert by !MAIN[4][27][39]
OPMODE[2]inCELL[3].IMUX_IMUX[16] invert by !MAIN[1][26][58]CELL[3].IMUX_IMUX[40] invert by !MAIN[4][26][34]
OPMODE[3]inCELL[3].IMUX_IMUX[22] invert by !MAIN[1][26][60]CELL[3].IMUX_IMUX[46] invert by !MAIN[4][26][36]
OPMODE[4]inCELL[3].IMUX_IMUX[5] invert by !MAIN[0][26][30]CELL[3].IMUX_IMUX[29] invert by !MAIN[2][27][62]
OPMODE[5]inCELL[3].IMUX_IMUX[11] invert by !MAIN[0][26][31]CELL[3].IMUX_IMUX[35] invert by !MAIN[2][27][63]
OPMODE[6]inCELL[3].IMUX_IMUX[17] invert by !MAIN[0][27][31]CELL[3].IMUX_IMUX[41] invert by !MAIN[3][27][0]
CARRYINSEL[0]inCELL[2].IMUX_IMUX[5]CELL[2].IMUX_IMUX[29]
CARRYINSEL[1]inCELL[2].IMUX_IMUX[11]CELL[2].IMUX_IMUX[35]
CARRYINSEL[2]inCELL[2].IMUX_IMUX[17]CELL[2].IMUX_IMUX[41]
RSTCTRLinCELL[0].IMUX_CTRL_SITE[2]CELL[3].IMUX_CTRL_SITE[2]
CECTRLinCELL[1].IMUX_IMUX[11]CELL[1].IMUX_IMUX[35]
CARRYINinCELL[3].IMUX_IMUX[23] invert by !MAIN[0][26][12]CELL[3].IMUX_IMUX[47] invert by !MAIN[2][26][42]
RSTALLCARRYINinCELL[0].IMUX_CTRL_SITE[0]CELL[3].IMUX_CTRL_SITE[0]
CECARRYINinCELL[1].IMUX_IMUX[17]CELL[1].IMUX_IMUX[41]
CEMULTCARRYINinCELL[1].IMUX_IMUX[23]CELL[1].IMUX_IMUX[47]
RSTALUMODEinCELL[0].IMUX_CTRL_SITE[1]CELL[3].IMUX_CTRL_SITE[1]
CEALUMODEinCELL[1].IMUX_IMUX[5]CELL[1].IMUX_IMUX[29]
ALUMODE[0]inCELL[2].IMUX_IMUX[4] invert by !MAIN[2][26][29]CELL[2].IMUX_IMUX[28] invert by !MAIN[4][26][52]
ALUMODE[1]inCELL[2].IMUX_IMUX[10] invert by !MAIN[2][27][7]CELL[2].IMUX_IMUX[34] invert by !MAIN[4][27][51]
ALUMODE[2]inCELL[2].IMUX_IMUX[16] invert by !MAIN[2][26][7]CELL[2].IMUX_IMUX[40] invert by !MAIN[4][27][47]
ALUMODE[3]inCELL[2].IMUX_IMUX[22] invert by !MAIN[2][26][1]CELL[2].IMUX_IMUX[46] invert by !MAIN[4][27][46]
RSTPinCELL[1].IMUX_CTRL_SITE[0]CELL[4].IMUX_CTRL_SITE[0]
CEPinCELL[2].IMUX_CTRL_SITE[0]CELL[2].IMUX_CTRL_SITE[1]
LFSRENinCELL[2].IMUX_BYP_SITE[0]CELL[2].IMUX_BYP_SITE[1]
TESTMinCELL[1].IMUX_BYP_SITE[0]CELL[3].IMUX_BYP_SITE[0]
TESTPinCELL[1].IMUX_BYP_SITE[1]CELL[3].IMUX_BYP_SITE[1]
SCANINMinCELL[1].IMUX_BYP_SITE[2]CELL[3].IMUX_BYP_SITE[2]
SCANINPinCELL[1].IMUX_BYP_SITE[3]CELL[3].IMUX_BYP_SITE[3]
P[0]outCELL[0].OUT_BEL[0]CELL[0].OUT_BEL[3]
P[1]outCELL[0].OUT_BEL[6]CELL[0].OUT_BEL[9]
P[2]outCELL[0].OUT_BEL[20]CELL[0].OUT_BEL[15]
P[3]outCELL[0].OUT_BEL[23]CELL[0].OUT_BEL[21]
P[4]outCELL[1].OUT_BEL[0]CELL[1].OUT_BEL[3]
P[5]outCELL[1].OUT_BEL[6]CELL[1].OUT_BEL[9]
P[6]outCELL[1].OUT_BEL[12]CELL[1].OUT_BEL[15]
P[7]outCELL[1].OUT_BEL[18]CELL[1].OUT_BEL[21]
P[8]outCELL[2].OUT_BEL[0]CELL[2].OUT_BEL[3]
P[9]outCELL[2].OUT_BEL[6]CELL[2].OUT_BEL[9]
P[10]outCELL[2].OUT_BEL[12]CELL[2].OUT_BEL[15]
P[11]outCELL[2].OUT_BEL[18]CELL[2].OUT_BEL[21]
P[12]outCELL[3].OUT_BEL[0]CELL[3].OUT_BEL[3]
P[13]outCELL[3].OUT_BEL[6]CELL[3].OUT_BEL[9]
P[14]outCELL[3].OUT_BEL[12]CELL[3].OUT_BEL[15]
P[15]outCELL[3].OUT_BEL[18]CELL[3].OUT_BEL[21]
P[16]outCELL[4].OUT_BEL[0]CELL[4].OUT_BEL[3]
P[17]outCELL[4].OUT_BEL[6]CELL[4].OUT_BEL[9]
P[18]outCELL[4].OUT_BEL[12]CELL[4].OUT_BEL[2]
P[19]outCELL[4].OUT_BEL[18]CELL[4].OUT_BEL[21]
P[20]outCELL[0].OUT_BEL[1]CELL[0].OUT_BEL[4]
P[21]outCELL[0].OUT_BEL[7]CELL[0].OUT_BEL[10]
P[22]outCELL[0].OUT_BEL[13]CELL[0].OUT_BEL[16]
P[23]outCELL[0].OUT_BEL[19]CELL[0].OUT_BEL[22]
P[24]outCELL[1].OUT_BEL[1]CELL[1].OUT_BEL[4]
P[25]outCELL[1].OUT_BEL[7]CELL[1].OUT_BEL[10]
P[26]outCELL[1].OUT_BEL[13]CELL[1].OUT_BEL[16]
P[27]outCELL[1].OUT_BEL[19]CELL[1].OUT_BEL[22]
P[28]outCELL[2].OUT_BEL[1]CELL[2].OUT_BEL[4]
P[29]outCELL[2].OUT_BEL[7]CELL[2].OUT_BEL[10]
P[30]outCELL[2].OUT_BEL[13]CELL[2].OUT_BEL[16]
P[31]outCELL[2].OUT_BEL[19]CELL[2].OUT_BEL[22]
P[32]outCELL[3].OUT_BEL[1]CELL[3].OUT_BEL[4]
P[33]outCELL[3].OUT_BEL[7]CELL[3].OUT_BEL[10]
P[34]outCELL[3].OUT_BEL[13]CELL[3].OUT_BEL[16]
P[35]outCELL[3].OUT_BEL[19]CELL[3].OUT_BEL[22]
P[36]outCELL[4].OUT_BEL[1]CELL[4].OUT_BEL[4]
P[37]outCELL[4].OUT_BEL[7]CELL[4].OUT_BEL[10]
P[38]outCELL[4].OUT_BEL[13]CELL[4].OUT_BEL[16]
P[39]outCELL[4].OUT_BEL[19]CELL[4].OUT_BEL[22]
P[40]outCELL[0].OUT_BEL[2]CELL[0].OUT_BEL[5]
P[41]outCELL[0].OUT_BEL[8]CELL[0].OUT_BEL[11]
P[42]outCELL[0].OUT_BEL[14]CELL[0].OUT_BEL[17]
P[43]outCELL[2].OUT_BEL[2]CELL[2].OUT_BEL[5]
P[44]outCELL[1].OUT_BEL[2]CELL[1].OUT_BEL[5]
P[45]outCELL[1].OUT_BEL[8]CELL[1].OUT_BEL[11]
P[46]outCELL[1].OUT_BEL[14]CELL[1].OUT_BEL[17]
P[47]outCELL[1].OUT_BEL[20]CELL[1].OUT_BEL[23]
CARRYOUT[0]outCELL[3].OUT_BEL[5]CELL[3].OUT_BEL[2]
CARRYOUT[1]outCELL[3].OUT_BEL[11]CELL[3].OUT_BEL[8]
CARRYOUT[2]outCELL[3].OUT_BEL[17]CELL[3].OUT_BEL[14]
CARRYOUT[3]outCELL[3].OUT_BEL[23]CELL[3].OUT_BEL[20]
PATTERNDETECToutCELL[2].OUT_BEL[14]CELL[4].OUT_BEL[14]
PATTERNBDETECToutCELL[2].OUT_BEL[20]CELL[4].OUT_BEL[20]
OVERFLOWoutCELL[2].OUT_BEL[11]CELL[4].OUT_BEL[11]
UNDERFLOWoutCELL[2].OUT_BEL[8]CELL[4].OUT_BEL[8]
SCANOUTMoutCELL[2].OUT_BEL[17]CELL[4].OUT_BEL[17]
SCANOUTPoutCELL[2].OUT_BEL[23]CELL[4].OUT_BEL[23]
virtex5 DSP bel DSP_V5 attribute bits
AttributeDSP[0]DSP[1]
AREG[enum: DSP_REG2_CASC][enum: DSP_REG2_CASC]
A_INPUT[enum: DSP_AB_INPUT][enum: DSP_AB_INPUT]
BREG[enum: DSP_REG2_CASC][enum: DSP_REG2_CASC]
B_INPUT[enum: DSP_AB_INPUT][enum: DSP_AB_INPUT]
CREG!MAIN[2][26][2]!MAIN[4][26][46]
MREG!MAIN[0][27][6]!MAIN[2][27][32]
CLOCK_INVERT_MMAIN[1][26][15]MAIN[3][26][46]
USE_MULT[enum: DSP_USE_MULT][enum: DSP_USE_MULT]
OPMODEREG!MAIN[1][26][62]!MAIN[4][27][41]
CARRYINSELREG!MAIN[0][26][32]!MAIN[3][27][1]
CARRYINREG!MAIN[0][27][12]!MAIN[2][27][42]
MULTCARRYINREG!MAIN[0][26][15]!MAIN[2][27][45]
ALUMODEREG!MAIN[2][26][8]!MAIN[4][26][51]
USE_SIMD[enum: DSP_USE_SIMD][enum: DSP_USE_SIMD]
PREG!MAIN[1][26][6]!MAIN[3][26][38]
CLOCK_INVERT_PMAIN[1][27][14]MAIN[3][26][45]
USE_PATTERN_DETECTMAIN[1][27][22]MAIN[3][27][23]
PATTERN bit 0MAIN[0][27][2]MAIN[2][26][34]
PATTERN bit 1MAIN[0][26][3]MAIN[2][26][36]
PATTERN bit 2MAIN[0][26][5]MAIN[2][26][37]
PATTERN bit 3MAIN[0][27][9]MAIN[2][26][41]
PATTERN bit 4MAIN[0][27][11]MAIN[2][27][43]
PATTERN bit 5MAIN[0][27][14]MAIN[2][26][46]
PATTERN bit 6MAIN[0][26][18]MAIN[2][27][50]
PATTERN bit 7MAIN[0][27][20]MAIN[2][27][53]
PATTERN bit 8MAIN[0][27][23]MAIN[2][27][55]
PATTERN bit 9MAIN[0][26][26]MAIN[2][27][57]
PATTERN bit 10MAIN[0][27][26]MAIN[2][26][57]
PATTERN bit 11MAIN[0][26][29]MAIN[2][26][61]
PATTERN bit 12MAIN[0][27][41]MAIN[3][27][8]
PATTERN bit 13MAIN[0][26][43]MAIN[3][26][12]
PATTERN bit 14MAIN[0][27][45]MAIN[3][27][13]
PATTERN bit 15MAIN[0][26][49]MAIN[3][26][17]
PATTERN bit 16MAIN[0][27][51]MAIN[3][27][18]
PATTERN bit 17MAIN[0][26][54]MAIN[3][26][22]
PATTERN bit 18MAIN[0][26][57]MAIN[3][27][24]
PATTERN bit 19MAIN[0][27][60]MAIN[3][27][26]
PATTERN bit 20MAIN[0][27][61]MAIN[3][26][28]
PATTERN bit 21MAIN[1][27][0]MAIN[3][26][32]
PATTERN bit 22MAIN[1][27][1]MAIN[3][26][33]
PATTERN bit 23MAIN[1][26][5]MAIN[3][27][37]
PATTERN bit 24MAIN[1][27][24]MAIN[3][27][56]
PATTERN bit 25MAIN[1][27][27]MAIN[3][26][60]
PATTERN bit 26MAIN[1][26][29]MAIN[3][26][61]
PATTERN bit 27MAIN[1][27][32]MAIN[4][27][1]
PATTERN bit 28MAIN[1][27][34]MAIN[4][27][2]
PATTERN bit 29MAIN[1][27][36]MAIN[4][26][5]
PATTERN bit 30MAIN[1][26][42]MAIN[4][27][9]
PATTERN bit 31MAIN[1][26][45]MAIN[4][27][13]
PATTERN bit 32MAIN[1][27][46]MAIN[4][27][14]
PATTERN bit 33MAIN[1][27][50]MAIN[4][26][18]
PATTERN bit 34MAIN[1][26][51]MAIN[4][27][18]
PATTERN bit 35MAIN[1][27][53]MAIN[4][26][21]
PATTERN bit 36MAIN[2][27][0]MAIN[4][27][32]
PATTERN bit 37MAIN[2][27][3]MAIN[4][26][35]
PATTERN bit 38MAIN[2][26][5]MAIN[4][27][36]
PATTERN bit 39MAIN[2][27][6]MAIN[4][26][38]
PATTERN bit 40MAIN[2][27][9]MAIN[4][26][41]
PATTERN bit 41MAIN[2][26][11]MAIN[4][26][43]
PATTERN bit 42MAIN[2][26][16]MAIN[4][26][47]
PATTERN bit 43MAIN[2][26][18]MAIN[4][27][50]
PATTERN bit 44MAIN[2][27][20]MAIN[4][27][52]
PATTERN bit 45MAIN[2][27][23]MAIN[4][27][55]
PATTERN bit 46MAIN[2][26][25]MAIN[4][27][57]
PATTERN bit 47MAIN[2][26][27]MAIN[4][26][60]
SEL_PATTERN[enum: DSP_SEL_PATTERN][enum: DSP_SEL_PATTERN]
MASK bit 0MAIN[0][26][2]MAIN[2][27][34]
MASK bit 1MAIN[0][27][3]MAIN[2][26][35]
MASK bit 2MAIN[0][26][6]MAIN[2][26][38]
MASK bit 3MAIN[0][27][8]MAIN[2][27][41]
MASK bit 4MAIN[0][26][11]MAIN[2][26][43]
MASK bit 5MAIN[0][27][13]MAIN[2][26][45]
MASK bit 6MAIN[0][27][18]MAIN[2][27][51]
MASK bit 7MAIN[0][26][20]MAIN[2][27][52]
MASK bit 8MAIN[0][27][24]MAIN[2][26][56]
MASK bit 9MAIN[0][26][25]MAIN[2][27][56]
MASK bit 10MAIN[0][27][27]MAIN[2][26][58]
MASK bit 11MAIN[0][27][29]MAIN[2][27][61]
MASK bit 12MAIN[0][26][41]MAIN[3][27][9]
MASK bit 13MAIN[0][27][43]MAIN[3][26][11]
MASK bit 14MAIN[0][26][45]MAIN[3][27][14]
MASK bit 15MAIN[0][26][48]MAIN[3][27][17]
MASK bit 16MAIN[0][26][51]MAIN[3][26][20]
MASK bit 17MAIN[0][27][53]MAIN[3][26][21]
MASK bit 18MAIN[0][26][58]MAIN[3][26][25]
MASK bit 19MAIN[0][26][60]MAIN[3][26][26]
MASK bit 20MAIN[0][26][61]MAIN[3][27][29]
MASK bit 21MAIN[0][27][63]MAIN[3][26][31]
MASK bit 22MAIN[1][26][2]MAIN[3][26][34]
MASK bit 23MAIN[1][26][3]MAIN[3][27][36]
MASK bit 24MAIN[1][26][25]MAIN[3][27][57]
MASK bit 25MAIN[1][27][26]MAIN[3][26][58]
MASK bit 26MAIN[1][26][30]MAIN[3][26][62]
MASK bit 27MAIN[1][26][32]MAIN[4][27][0]
MASK bit 28MAIN[1][26][35]MAIN[4][27][3]
MASK bit 29MAIN[1][26][36]MAIN[4][26][3]
MASK bit 30MAIN[1][27][42]MAIN[4][27][10]
MASK bit 31MAIN[1][27][45]MAIN[4][27][12]
MASK bit 32MAIN[1][27][47]MAIN[4][26][15]
MASK bit 33MAIN[1][26][49]MAIN[4][26][17]
MASK bit 34MAIN[1][26][52]MAIN[4][26][20]
MASK bit 35MAIN[1][27][52]MAIN[4][27][20]
MASK bit 36MAIN[2][27][1]MAIN[4][27][33]
MASK bit 37MAIN[2][27][2]MAIN[4][27][34]
MASK bit 38MAIN[2][26][3]MAIN[4][27][37]
MASK bit 39MAIN[2][26][6]MAIN[4][26][37]
MASK bit 40MAIN[2][27][10]MAIN[4][26][42]
MASK bit 41MAIN[2][27][11]MAIN[4][27][43]
MASK bit 42MAIN[2][27][16]MAIN[4][26][48]
MASK bit 43MAIN[2][26][17]MAIN[4][26][49]
MASK bit 44MAIN[2][27][21]MAIN[4][27][53]
MASK bit 45MAIN[2][27][22]MAIN[4][26][54]
MASK bit 46MAIN[2][26][26]MAIN[4][26][57]
MASK bit 47MAIN[2][27][27]MAIN[4][26][58]
SEL_MASK[enum: DSP_SEL_MASK][enum: DSP_SEL_MASK]
SEL_ROUNDING_MASK[enum: DSP_SEL_ROUNDING_MASK][enum: DSP_SEL_ROUNDING_MASK]
ROUNDING_LSB_MASK bit 0MAIN[0][26][1]MAIN[2][26][33]
AUTORESET_OVER_UNDER_FLOWMAIN[1][27][16]MAIN[3][26][48]
AUTORESET_PATTERN_DETECTMAIN[1][26][16]MAIN[3][27][47]
AUTORESET_PATTERN_DETECT_OPTINVMAIN[1][26][18]MAIN[3][27][50]
LFSR_EN_SET!MAIN[1][27][63]!MAIN[4][27][56]
LFSR_EN_SETVAL bit 0MAIN[1][27][62]MAIN[4][26][56]
TEST_SET_M!MAIN[0][27][7]!MAIN[2][27][36]
TEST_SET_P!MAIN[1][26][17]!MAIN[3][26][49]
TEST_SETVAL_M bit 0MAIN[0][26][7]MAIN[2][27][37]
TEST_SETVAL_P bit 0MAIN[1][27][17]MAIN[3][26][47]
SCAN_IN_SET_M!MAIN[0][27][10]!MAIN[2][27][39]
SCAN_IN_SET_P!MAIN[0][27][1]!MAIN[2][27][33]
SCAN_IN_SETVAL_M bit 0MAIN[0][26][8]MAIN[2][27][40]
SCAN_IN_SETVAL_P bit 0MAIN[0][27][0]MAIN[2][26][32]
virtex5 DSP enum DSP_REG2_CASC
DSP[0].AREGMAIN[0][27][55]MAIN[0][26][56]MAIN[0][27][56]
DSP[1].AREGMAIN[3][27][12]MAIN[3][26][7]MAIN[3][26][15]
DSP[0].BREGMAIN[1][26][1]MAIN[1][27][3]MAIN[0][27][57]
DSP[1].BREGMAIN[3][27][34]MAIN[3][26][36]MAIN[3][26][16]
NONE000
_0011
_1001
_2101
DIRECT_2_CASC_1100
virtex5 DSP enum DSP_AB_INPUT
DSP[0].A_INPUTMAIN[1][27][2]
DSP[1].A_INPUTMAIN[3][26][35]
DSP[0].B_INPUTMAIN[0][27][62]
DSP[1].B_INPUTMAIN[3][26][18]
DIRECT0
CASCADE1
virtex5 DSP enum DSP_USE_MULT
DSP[0].USE_MULTMAIN[0][26][62]MAIN[1][26][22]
DSP[1].USE_MULTMAIN[3][27][16]MAIN[3][27][22]
NONE11
MULT00
MULT_S01
virtex5 DSP enum DSP_USE_SIMD
DSP[0].USE_SIMDMAIN[1][26][56]MAIN[0][27][39]MAIN[1][27][13]
DSP[1].USE_SIMDMAIN[4][27][23]MAIN[3][27][6]MAIN[3][27][45]
ONE48000
TWO24001
FOUR12111
virtex5 DSP enum DSP_SEL_PATTERN
DSP[0].SEL_PATTERNMAIN[2][26][31]
DSP[1].SEL_PATTERNMAIN[4][27][61]
PATTERN0
C1
virtex5 DSP enum DSP_SEL_MASK
DSP[0].SEL_MASKMAIN[2][26][30]
DSP[1].SEL_MASKMAIN[4][26][62]
MASK0
C1
virtex5 DSP enum DSP_SEL_ROUNDING_MASK
DSP[0].SEL_ROUNDING_MASKMAIN[2][27][31]MAIN[2][27][29]
DSP[1].SEL_ROUNDING_MASKMAIN[4][27][62]MAIN[4][26][61]
SEL_MASK00
MODE101
MODE211

Bel wires

virtex5 DSP bel wires
WirePins
CELL[0].IMUX_CTRL_SITE[0]DSP[0].RSTALLCARRYIN
CELL[0].IMUX_CTRL_SITE[1]DSP[0].RSTALUMODE
CELL[0].IMUX_CTRL_SITE[2]DSP[0].RSTCTRL
CELL[0].IMUX_CTRL_SITE[3]DSP[0].RSTC
CELL[0].IMUX_IMUX[0]DSP[0].A[0]
CELL[0].IMUX_IMUX[1]DSP[0].B[0]
CELL[0].IMUX_IMUX[2]DSP[0].C[0]
CELL[0].IMUX_IMUX[3]DSP[0].C[20]
CELL[0].IMUX_IMUX[4]DSP[0].C[40]
CELL[0].IMUX_IMUX[5]DSP[0].CEB1
CELL[0].IMUX_IMUX[6]DSP[0].A[1]
CELL[0].IMUX_IMUX[7]DSP[0].B[1]
CELL[0].IMUX_IMUX[8]DSP[0].C[1]
CELL[0].IMUX_IMUX[9]DSP[0].C[21]
CELL[0].IMUX_IMUX[10]DSP[0].C[41]
CELL[0].IMUX_IMUX[11]DSP[0].CEB2
CELL[0].IMUX_IMUX[12]DSP[0].A[2]
CELL[0].IMUX_IMUX[13]DSP[0].B[2]
CELL[0].IMUX_IMUX[14]DSP[0].C[2]
CELL[0].IMUX_IMUX[15]DSP[0].C[22]
CELL[0].IMUX_IMUX[16]DSP[0].C[42]
CELL[0].IMUX_IMUX[17]DSP[0].CEA1
CELL[0].IMUX_IMUX[18]DSP[0].A[3]
CELL[0].IMUX_IMUX[19]DSP[0].B[3]
CELL[0].IMUX_IMUX[20]DSP[0].C[3]
CELL[0].IMUX_IMUX[21]DSP[0].C[23]
CELL[0].IMUX_IMUX[22]DSP[0].C[43]
CELL[0].IMUX_IMUX[23]DSP[0].CEA2
CELL[0].IMUX_IMUX[24]DSP[1].A[0]
CELL[0].IMUX_IMUX[25]DSP[1].B[0]
CELL[0].IMUX_IMUX[26]DSP[1].C[0]
CELL[0].IMUX_IMUX[27]DSP[1].C[20]
CELL[0].IMUX_IMUX[28]DSP[1].C[40]
CELL[0].IMUX_IMUX[29]DSP[1].CEB1
CELL[0].IMUX_IMUX[30]DSP[1].A[1]
CELL[0].IMUX_IMUX[31]DSP[1].B[1]
CELL[0].IMUX_IMUX[32]DSP[1].C[1]
CELL[0].IMUX_IMUX[33]DSP[1].C[21]
CELL[0].IMUX_IMUX[34]DSP[1].C[41]
CELL[0].IMUX_IMUX[35]DSP[1].CEB2
CELL[0].IMUX_IMUX[36]DSP[1].A[2]
CELL[0].IMUX_IMUX[37]DSP[1].B[2]
CELL[0].IMUX_IMUX[38]DSP[1].C[2]
CELL[0].IMUX_IMUX[39]DSP[1].C[22]
CELL[0].IMUX_IMUX[40]DSP[1].C[42]
CELL[0].IMUX_IMUX[41]DSP[1].CEA1
CELL[0].IMUX_IMUX[42]DSP[1].A[3]
CELL[0].IMUX_IMUX[43]DSP[1].B[3]
CELL[0].IMUX_IMUX[44]DSP[1].C[3]
CELL[0].IMUX_IMUX[45]DSP[1].C[23]
CELL[0].IMUX_IMUX[46]DSP[1].C[43]
CELL[0].IMUX_IMUX[47]DSP[1].CEA2
CELL[0].OUT_BEL[0]DSP[0].P[0]
CELL[0].OUT_BEL[1]DSP[0].P[20]
CELL[0].OUT_BEL[2]DSP[0].P[40]
CELL[0].OUT_BEL[3]DSP[1].P[0]
CELL[0].OUT_BEL[4]DSP[1].P[20]
CELL[0].OUT_BEL[5]DSP[1].P[40]
CELL[0].OUT_BEL[6]DSP[0].P[1]
CELL[0].OUT_BEL[7]DSP[0].P[21]
CELL[0].OUT_BEL[8]DSP[0].P[41]
CELL[0].OUT_BEL[9]DSP[1].P[1]
CELL[0].OUT_BEL[10]DSP[1].P[21]
CELL[0].OUT_BEL[11]DSP[1].P[41]
CELL[0].OUT_BEL[13]DSP[0].P[22]
CELL[0].OUT_BEL[14]DSP[0].P[42]
CELL[0].OUT_BEL[15]DSP[1].P[2]
CELL[0].OUT_BEL[16]DSP[1].P[22]
CELL[0].OUT_BEL[17]DSP[1].P[42]
CELL[0].OUT_BEL[19]DSP[0].P[23]
CELL[0].OUT_BEL[20]DSP[0].P[2]
CELL[0].OUT_BEL[21]DSP[1].P[3]
CELL[0].OUT_BEL[22]DSP[1].P[23]
CELL[0].OUT_BEL[23]DSP[0].P[3]
CELL[1].IMUX_CLK[0]DSP[0].CLK
CELL[1].IMUX_CTRL_SITE[0]DSP[0].RSTP
CELL[1].IMUX_CTRL_SITE[1]DSP[0].RSTM
CELL[1].IMUX_CTRL_SITE[2]DSP[0].RSTB
CELL[1].IMUX_CTRL_SITE[3]DSP[0].RSTA
CELL[1].IMUX_BYP_SITE[0]DSP[0].TESTM
CELL[1].IMUX_BYP_SITE[1]DSP[0].TESTP
CELL[1].IMUX_BYP_SITE[2]DSP[0].SCANINM
CELL[1].IMUX_BYP_SITE[3]DSP[0].SCANINP
CELL[1].IMUX_IMUX[0]DSP[0].A[4]
CELL[1].IMUX_IMUX[1]DSP[0].B[4]
CELL[1].IMUX_IMUX[2]DSP[0].C[4]
CELL[1].IMUX_IMUX[3]DSP[0].C[24]
CELL[1].IMUX_IMUX[4]DSP[0].C[44]
CELL[1].IMUX_IMUX[5]DSP[0].CEALUMODE
CELL[1].IMUX_IMUX[6]DSP[0].A[5]
CELL[1].IMUX_IMUX[7]DSP[0].B[5]
CELL[1].IMUX_IMUX[8]DSP[0].C[5]
CELL[1].IMUX_IMUX[9]DSP[0].C[25]
CELL[1].IMUX_IMUX[10]DSP[0].C[45]
CELL[1].IMUX_IMUX[11]DSP[0].CECTRL
CELL[1].IMUX_IMUX[12]DSP[0].A[6]
CELL[1].IMUX_IMUX[13]DSP[0].B[6]
CELL[1].IMUX_IMUX[14]DSP[0].C[6]
CELL[1].IMUX_IMUX[15]DSP[0].C[26]
CELL[1].IMUX_IMUX[16]DSP[0].C[46]
CELL[1].IMUX_IMUX[17]DSP[0].CECARRYIN
CELL[1].IMUX_IMUX[18]DSP[0].A[7]
CELL[1].IMUX_IMUX[19]DSP[0].B[7]
CELL[1].IMUX_IMUX[20]DSP[0].C[7]
CELL[1].IMUX_IMUX[21]DSP[0].C[27]
CELL[1].IMUX_IMUX[22]DSP[0].C[47]
CELL[1].IMUX_IMUX[23]DSP[0].CEMULTCARRYIN
CELL[1].IMUX_IMUX[24]DSP[1].A[4]
CELL[1].IMUX_IMUX[25]DSP[1].B[4]
CELL[1].IMUX_IMUX[26]DSP[1].C[4]
CELL[1].IMUX_IMUX[27]DSP[1].C[24]
CELL[1].IMUX_IMUX[28]DSP[1].C[44]
CELL[1].IMUX_IMUX[29]DSP[1].CEALUMODE
CELL[1].IMUX_IMUX[30]DSP[1].A[5]
CELL[1].IMUX_IMUX[31]DSP[1].B[5]
CELL[1].IMUX_IMUX[32]DSP[1].C[5]
CELL[1].IMUX_IMUX[33]DSP[1].C[25]
CELL[1].IMUX_IMUX[34]DSP[1].C[45]
CELL[1].IMUX_IMUX[35]DSP[1].CECTRL
CELL[1].IMUX_IMUX[36]DSP[1].A[6]
CELL[1].IMUX_IMUX[37]DSP[1].B[6]
CELL[1].IMUX_IMUX[38]DSP[1].C[6]
CELL[1].IMUX_IMUX[39]DSP[1].C[26]
CELL[1].IMUX_IMUX[40]DSP[1].C[46]
CELL[1].IMUX_IMUX[41]DSP[1].CECARRYIN
CELL[1].IMUX_IMUX[42]DSP[1].A[7]
CELL[1].IMUX_IMUX[43]DSP[1].B[7]
CELL[1].IMUX_IMUX[44]DSP[1].C[7]
CELL[1].IMUX_IMUX[45]DSP[1].C[27]
CELL[1].IMUX_IMUX[46]DSP[1].C[47]
CELL[1].IMUX_IMUX[47]DSP[1].CEMULTCARRYIN
CELL[1].OUT_BEL[0]DSP[0].P[4]
CELL[1].OUT_BEL[1]DSP[0].P[24]
CELL[1].OUT_BEL[2]DSP[0].P[44]
CELL[1].OUT_BEL[3]DSP[1].P[4]
CELL[1].OUT_BEL[4]DSP[1].P[24]
CELL[1].OUT_BEL[5]DSP[1].P[44]
CELL[1].OUT_BEL[6]DSP[0].P[5]
CELL[1].OUT_BEL[7]DSP[0].P[25]
CELL[1].OUT_BEL[8]DSP[0].P[45]
CELL[1].OUT_BEL[9]DSP[1].P[5]
CELL[1].OUT_BEL[10]DSP[1].P[25]
CELL[1].OUT_BEL[11]DSP[1].P[45]
CELL[1].OUT_BEL[12]DSP[0].P[6]
CELL[1].OUT_BEL[13]DSP[0].P[26]
CELL[1].OUT_BEL[14]DSP[0].P[46]
CELL[1].OUT_BEL[15]DSP[1].P[6]
CELL[1].OUT_BEL[16]DSP[1].P[26]
CELL[1].OUT_BEL[17]DSP[1].P[46]
CELL[1].OUT_BEL[18]DSP[0].P[7]
CELL[1].OUT_BEL[19]DSP[0].P[27]
CELL[1].OUT_BEL[20]DSP[0].P[47]
CELL[1].OUT_BEL[21]DSP[1].P[7]
CELL[1].OUT_BEL[22]DSP[1].P[27]
CELL[1].OUT_BEL[23]DSP[1].P[47]
CELL[2].IMUX_CTRL_SITE[0]DSP[0].CEP
CELL[2].IMUX_CTRL_SITE[1]DSP[1].CEP
CELL[2].IMUX_CTRL_SITE[2]DSP[0].CEM
CELL[2].IMUX_CTRL_SITE[3]DSP[1].CEM
CELL[2].IMUX_BYP_SITE[0]DSP[0].LFSREN
CELL[2].IMUX_BYP_SITE[1]DSP[1].LFSREN
CELL[2].IMUX_IMUX[0]DSP[0].A[8]
CELL[2].IMUX_IMUX[1]DSP[0].B[8]
CELL[2].IMUX_IMUX[2]DSP[0].C[8]
CELL[2].IMUX_IMUX[3]DSP[0].C[28]
CELL[2].IMUX_IMUX[4]DSP[0].ALUMODE[0]
CELL[2].IMUX_IMUX[5]DSP[0].CARRYINSEL[0]
CELL[2].IMUX_IMUX[6]DSP[0].A[9]
CELL[2].IMUX_IMUX[7]DSP[0].B[9]
CELL[2].IMUX_IMUX[8]DSP[0].C[9]
CELL[2].IMUX_IMUX[9]DSP[0].C[29]
CELL[2].IMUX_IMUX[10]DSP[0].ALUMODE[1]
CELL[2].IMUX_IMUX[11]DSP[0].CARRYINSEL[1]
CELL[2].IMUX_IMUX[12]DSP[0].A[10]
CELL[2].IMUX_IMUX[13]DSP[0].B[10]
CELL[2].IMUX_IMUX[14]DSP[0].C[10]
CELL[2].IMUX_IMUX[15]DSP[0].C[30]
CELL[2].IMUX_IMUX[16]DSP[0].ALUMODE[2]
CELL[2].IMUX_IMUX[17]DSP[0].CARRYINSEL[2]
CELL[2].IMUX_IMUX[18]DSP[0].A[11]
CELL[2].IMUX_IMUX[19]DSP[0].B[11]
CELL[2].IMUX_IMUX[20]DSP[0].C[11]
CELL[2].IMUX_IMUX[21]DSP[0].C[31]
CELL[2].IMUX_IMUX[22]DSP[0].ALUMODE[3]
CELL[2].IMUX_IMUX[23]DSP[0].CEC
CELL[2].IMUX_IMUX[24]DSP[1].A[8]
CELL[2].IMUX_IMUX[25]DSP[1].B[8]
CELL[2].IMUX_IMUX[26]DSP[1].C[8]
CELL[2].IMUX_IMUX[27]DSP[1].C[28]
CELL[2].IMUX_IMUX[28]DSP[1].ALUMODE[0]
CELL[2].IMUX_IMUX[29]DSP[1].CARRYINSEL[0]
CELL[2].IMUX_IMUX[30]DSP[1].A[9]
CELL[2].IMUX_IMUX[31]DSP[1].B[9]
CELL[2].IMUX_IMUX[32]DSP[1].C[9]
CELL[2].IMUX_IMUX[33]DSP[1].C[29]
CELL[2].IMUX_IMUX[34]DSP[1].ALUMODE[1]
CELL[2].IMUX_IMUX[35]DSP[1].CARRYINSEL[1]
CELL[2].IMUX_IMUX[36]DSP[1].A[10]
CELL[2].IMUX_IMUX[37]DSP[1].B[10]
CELL[2].IMUX_IMUX[38]DSP[1].C[10]
CELL[2].IMUX_IMUX[39]DSP[1].C[30]
CELL[2].IMUX_IMUX[40]DSP[1].ALUMODE[2]
CELL[2].IMUX_IMUX[41]DSP[1].CARRYINSEL[2]
CELL[2].IMUX_IMUX[42]DSP[1].A[11]
CELL[2].IMUX_IMUX[43]DSP[1].B[11]
CELL[2].IMUX_IMUX[44]DSP[1].C[11]
CELL[2].IMUX_IMUX[45]DSP[1].C[31]
CELL[2].IMUX_IMUX[46]DSP[1].ALUMODE[3]
CELL[2].IMUX_IMUX[47]DSP[1].CEC
CELL[2].OUT_BEL[0]DSP[0].P[8]
CELL[2].OUT_BEL[1]DSP[0].P[28]
CELL[2].OUT_BEL[2]DSP[0].P[43]
CELL[2].OUT_BEL[3]DSP[1].P[8]
CELL[2].OUT_BEL[4]DSP[1].P[28]
CELL[2].OUT_BEL[5]DSP[1].P[43]
CELL[2].OUT_BEL[6]DSP[0].P[9]
CELL[2].OUT_BEL[7]DSP[0].P[29]
CELL[2].OUT_BEL[8]DSP[0].UNDERFLOW
CELL[2].OUT_BEL[9]DSP[1].P[9]
CELL[2].OUT_BEL[10]DSP[1].P[29]
CELL[2].OUT_BEL[11]DSP[0].OVERFLOW
CELL[2].OUT_BEL[12]DSP[0].P[10]
CELL[2].OUT_BEL[13]DSP[0].P[30]
CELL[2].OUT_BEL[14]DSP[0].PATTERNDETECT
CELL[2].OUT_BEL[15]DSP[1].P[10]
CELL[2].OUT_BEL[16]DSP[1].P[30]
CELL[2].OUT_BEL[17]DSP[0].SCANOUTM
CELL[2].OUT_BEL[18]DSP[0].P[11]
CELL[2].OUT_BEL[19]DSP[0].P[31]
CELL[2].OUT_BEL[20]DSP[0].PATTERNBDETECT
CELL[2].OUT_BEL[21]DSP[1].P[11]
CELL[2].OUT_BEL[22]DSP[1].P[31]
CELL[2].OUT_BEL[23]DSP[0].SCANOUTP
CELL[3].IMUX_CLK[0]DSP[1].CLK
CELL[3].IMUX_CTRL_SITE[0]DSP[1].RSTALLCARRYIN
CELL[3].IMUX_CTRL_SITE[1]DSP[1].RSTALUMODE
CELL[3].IMUX_CTRL_SITE[2]DSP[1].RSTCTRL
CELL[3].IMUX_CTRL_SITE[3]DSP[1].RSTC
CELL[3].IMUX_BYP_SITE[0]DSP[1].TESTM
CELL[3].IMUX_BYP_SITE[1]DSP[1].TESTP
CELL[3].IMUX_BYP_SITE[2]DSP[1].SCANINM
CELL[3].IMUX_BYP_SITE[3]DSP[1].SCANINP
CELL[3].IMUX_IMUX[0]DSP[0].A[12]
CELL[3].IMUX_IMUX[1]DSP[0].B[12]
CELL[3].IMUX_IMUX[2]DSP[0].C[12]
CELL[3].IMUX_IMUX[3]DSP[0].C[32]
CELL[3].IMUX_IMUX[4]DSP[0].OPMODE[0]
CELL[3].IMUX_IMUX[5]DSP[0].OPMODE[4]
CELL[3].IMUX_IMUX[6]DSP[0].A[13]
CELL[3].IMUX_IMUX[7]DSP[0].B[13]
CELL[3].IMUX_IMUX[8]DSP[0].C[13]
CELL[3].IMUX_IMUX[9]DSP[0].C[33]
CELL[3].IMUX_IMUX[10]DSP[0].OPMODE[1]
CELL[3].IMUX_IMUX[11]DSP[0].OPMODE[5]
CELL[3].IMUX_IMUX[12]DSP[0].A[14]
CELL[3].IMUX_IMUX[13]DSP[0].B[14]
CELL[3].IMUX_IMUX[14]DSP[0].C[14]
CELL[3].IMUX_IMUX[15]DSP[0].C[34]
CELL[3].IMUX_IMUX[16]DSP[0].OPMODE[2]
CELL[3].IMUX_IMUX[17]DSP[0].OPMODE[6]
CELL[3].IMUX_IMUX[18]DSP[0].A[15]
CELL[3].IMUX_IMUX[19]DSP[0].B[15]
CELL[3].IMUX_IMUX[20]DSP[0].C[15]
CELL[3].IMUX_IMUX[21]DSP[0].C[35]
CELL[3].IMUX_IMUX[22]DSP[0].OPMODE[3]
CELL[3].IMUX_IMUX[23]DSP[0].CARRYIN
CELL[3].IMUX_IMUX[24]DSP[1].A[12]
CELL[3].IMUX_IMUX[25]DSP[1].B[12]
CELL[3].IMUX_IMUX[26]DSP[1].C[12]
CELL[3].IMUX_IMUX[27]DSP[1].C[32]
CELL[3].IMUX_IMUX[28]DSP[1].OPMODE[0]
CELL[3].IMUX_IMUX[29]DSP[1].OPMODE[4]
CELL[3].IMUX_IMUX[30]DSP[1].A[13]
CELL[3].IMUX_IMUX[31]DSP[1].B[13]
CELL[3].IMUX_IMUX[32]DSP[1].C[13]
CELL[3].IMUX_IMUX[33]DSP[1].C[33]
CELL[3].IMUX_IMUX[34]DSP[1].OPMODE[1]
CELL[3].IMUX_IMUX[35]DSP[1].OPMODE[5]
CELL[3].IMUX_IMUX[36]DSP[1].A[14]
CELL[3].IMUX_IMUX[37]DSP[1].B[14]
CELL[3].IMUX_IMUX[38]DSP[1].C[14]
CELL[3].IMUX_IMUX[39]DSP[1].C[34]
CELL[3].IMUX_IMUX[40]DSP[1].OPMODE[2]
CELL[3].IMUX_IMUX[41]DSP[1].OPMODE[6]
CELL[3].IMUX_IMUX[42]DSP[1].A[15]
CELL[3].IMUX_IMUX[43]DSP[1].B[15]
CELL[3].IMUX_IMUX[44]DSP[1].C[15]
CELL[3].IMUX_IMUX[45]DSP[1].C[35]
CELL[3].IMUX_IMUX[46]DSP[1].OPMODE[3]
CELL[3].IMUX_IMUX[47]DSP[1].CARRYIN
CELL[3].OUT_BEL[0]DSP[0].P[12]
CELL[3].OUT_BEL[1]DSP[0].P[32]
CELL[3].OUT_BEL[2]DSP[1].CARRYOUT[0]
CELL[3].OUT_BEL[3]DSP[1].P[12]
CELL[3].OUT_BEL[4]DSP[1].P[32]
CELL[3].OUT_BEL[5]DSP[0].CARRYOUT[0]
CELL[3].OUT_BEL[6]DSP[0].P[13]
CELL[3].OUT_BEL[7]DSP[0].P[33]
CELL[3].OUT_BEL[8]DSP[1].CARRYOUT[1]
CELL[3].OUT_BEL[9]DSP[1].P[13]
CELL[3].OUT_BEL[10]DSP[1].P[33]
CELL[3].OUT_BEL[11]DSP[0].CARRYOUT[1]
CELL[3].OUT_BEL[12]DSP[0].P[14]
CELL[3].OUT_BEL[13]DSP[0].P[34]
CELL[3].OUT_BEL[14]DSP[1].CARRYOUT[2]
CELL[3].OUT_BEL[15]DSP[1].P[14]
CELL[3].OUT_BEL[16]DSP[1].P[34]
CELL[3].OUT_BEL[17]DSP[0].CARRYOUT[2]
CELL[3].OUT_BEL[18]DSP[0].P[15]
CELL[3].OUT_BEL[19]DSP[0].P[35]
CELL[3].OUT_BEL[20]DSP[1].CARRYOUT[3]
CELL[3].OUT_BEL[21]DSP[1].P[15]
CELL[3].OUT_BEL[22]DSP[1].P[35]
CELL[3].OUT_BEL[23]DSP[0].CARRYOUT[3]
CELL[4].IMUX_CTRL_SITE[0]DSP[1].RSTP
CELL[4].IMUX_CTRL_SITE[1]DSP[1].RSTM
CELL[4].IMUX_CTRL_SITE[2]DSP[1].RSTB
CELL[4].IMUX_CTRL_SITE[3]DSP[1].RSTA
CELL[4].IMUX_IMUX[0]DSP[0].A[16]
CELL[4].IMUX_IMUX[1]DSP[0].B[16]
CELL[4].IMUX_IMUX[2]DSP[0].C[16]
CELL[4].IMUX_IMUX[3]DSP[0].C[36]
CELL[4].IMUX_IMUX[4]DSP[0].A[20]
CELL[4].IMUX_IMUX[5]DSP[1].A[20]
CELL[4].IMUX_IMUX[6]DSP[0].A[17]
CELL[4].IMUX_IMUX[7]DSP[0].B[17]
CELL[4].IMUX_IMUX[8]DSP[0].C[17]
CELL[4].IMUX_IMUX[9]DSP[0].C[37]
CELL[4].IMUX_IMUX[10]DSP[0].A[21]
CELL[4].IMUX_IMUX[11]DSP[1].A[21]
CELL[4].IMUX_IMUX[12]DSP[0].A[18]
CELL[4].IMUX_IMUX[13]DSP[0].A[28]
CELL[4].IMUX_IMUX[14]DSP[0].C[18]
CELL[4].IMUX_IMUX[15]DSP[0].C[38]
CELL[4].IMUX_IMUX[16]DSP[0].A[22]
CELL[4].IMUX_IMUX[17]DSP[1].A[22]
CELL[4].IMUX_IMUX[18]DSP[0].A[19]
CELL[4].IMUX_IMUX[19]DSP[0].A[29]
CELL[4].IMUX_IMUX[20]DSP[0].C[19]
CELL[4].IMUX_IMUX[21]DSP[0].C[39]
CELL[4].IMUX_IMUX[22]DSP[0].A[23]
CELL[4].IMUX_IMUX[23]DSP[1].A[23]
CELL[4].IMUX_IMUX[24]DSP[1].A[16]
CELL[4].IMUX_IMUX[25]DSP[1].B[16]
CELL[4].IMUX_IMUX[26]DSP[1].C[16]
CELL[4].IMUX_IMUX[27]DSP[1].C[36]
CELL[4].IMUX_IMUX[28]DSP[0].A[24]
CELL[4].IMUX_IMUX[29]DSP[1].A[24]
CELL[4].IMUX_IMUX[30]DSP[1].A[17]
CELL[4].IMUX_IMUX[31]DSP[1].B[17]
CELL[4].IMUX_IMUX[32]DSP[1].C[17]
CELL[4].IMUX_IMUX[33]DSP[1].C[37]
CELL[4].IMUX_IMUX[34]DSP[0].A[25]
CELL[4].IMUX_IMUX[35]DSP[1].A[25]
CELL[4].IMUX_IMUX[36]DSP[1].A[18]
CELL[4].IMUX_IMUX[37]DSP[1].A[28]
CELL[4].IMUX_IMUX[38]DSP[1].C[18]
CELL[4].IMUX_IMUX[39]DSP[1].C[38]
CELL[4].IMUX_IMUX[40]DSP[0].A[26]
CELL[4].IMUX_IMUX[41]DSP[1].A[26]
CELL[4].IMUX_IMUX[42]DSP[1].A[19]
CELL[4].IMUX_IMUX[43]DSP[1].A[29]
CELL[4].IMUX_IMUX[44]DSP[1].C[19]
CELL[4].IMUX_IMUX[45]DSP[1].C[39]
CELL[4].IMUX_IMUX[46]DSP[0].A[27]
CELL[4].IMUX_IMUX[47]DSP[1].A[27]
CELL[4].OUT_BEL[0]DSP[0].P[16]
CELL[4].OUT_BEL[1]DSP[0].P[36]
CELL[4].OUT_BEL[2]DSP[1].P[18]
CELL[4].OUT_BEL[3]DSP[1].P[16]
CELL[4].OUT_BEL[4]DSP[1].P[36]
CELL[4].OUT_BEL[6]DSP[0].P[17]
CELL[4].OUT_BEL[7]DSP[0].P[37]
CELL[4].OUT_BEL[8]DSP[1].UNDERFLOW
CELL[4].OUT_BEL[9]DSP[1].P[17]
CELL[4].OUT_BEL[10]DSP[1].P[37]
CELL[4].OUT_BEL[11]DSP[1].OVERFLOW
CELL[4].OUT_BEL[12]DSP[0].P[18]
CELL[4].OUT_BEL[13]DSP[0].P[38]
CELL[4].OUT_BEL[14]DSP[1].PATTERNDETECT
CELL[4].OUT_BEL[16]DSP[1].P[38]
CELL[4].OUT_BEL[17]DSP[1].SCANOUTM
CELL[4].OUT_BEL[18]DSP[0].P[19]
CELL[4].OUT_BEL[19]DSP[0].P[39]
CELL[4].OUT_BEL[20]DSP[1].PATTERNBDETECT
CELL[4].OUT_BEL[21]DSP[1].P[19]
CELL[4].OUT_BEL[22]DSP[1].P[39]
CELL[4].OUT_BEL[23]DSP[1].SCANOUTP

Bitstream

virtex5 DSP rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 21
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: USE_MULT bit 1 DSP[0]: B_INPUT bit 0
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 20 DSP[0]: PATTERN bit 20
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 19 DSP[0]: PATTERN bit 19
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 18 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 18 DSP[0]: BREG bit 0
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: AREG bit 1 DSP[0]: AREG bit 0
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: AREG bit 2
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 17 -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 17
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 16 DSP[0]: PATTERN bit 16
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 15 -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 15 -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 14 DSP[0]: PATTERN bit 14
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 13 DSP[0]: MASK bit 13
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 12 DSP[0]: PATTERN bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: USE_SIMD bit 1
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! CARRYINSELREG -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert OPMODE[5] DSP[0]: !invert OPMODE[6]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert OPMODE[4] -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 11 DSP[0]: MASK bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 10
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 9 DSP[0]: PATTERN bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 9 -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 8
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 8
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 7 DSP[0]: PATTERN bit 7
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 6 DSP[0]: MASK bit 6
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! MULTCARRYINREG -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 5
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 5
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert CARRYIN DSP[0]: ! CARRYINREG
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 4 DSP[0]: PATTERN bit 4
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! SCAN_IN_SET_M
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: SCAN_IN_SETVAL_M bit 0 DSP[0]: MASK bit 3
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: TEST_SETVAL_M bit 0 DSP[0]: ! TEST_SET_M
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 2 DSP[0]: ! MREG
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 2 -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 1 DSP[0]: MASK bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 0 DSP[0]: PATTERN bit 0
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ROUNDING_LSB_MASK bit 0 DSP[0]: ! SCAN_IN_SET_P
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: SCAN_IN_SETVAL_P bit 0
virtex5 DSP rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! LFSR_EN_SET
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! OPMODEREG DSP[0]: LFSR_EN_SETVAL bit 0
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert OPMODE[1]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert OPMODE[3] DSP[0]: !invert OPMODE[0]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert OPMODE[2] -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: USE_SIMD bit 2 -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 35
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 34 DSP[0]: MASK bit 35
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 34 -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 33
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 33 -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 32
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 32
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 31 DSP[0]: MASK bit 31
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 30 DSP[0]: MASK bit 30
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 29 DSP[0]: PATTERN bit 29
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 28 -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 28
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 27 DSP[0]: PATTERN bit 27
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 26 -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 26 -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 25
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 25
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 24 -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 24
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: USE_MULT bit 0 DSP[0]: USE_PATTERN_DETECT
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert CLK -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: AUTORESET_PATTERN_DETECT_OPTINV -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! TEST_SET_P DSP[0]: TEST_SETVAL_P bit 0
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: AUTORESET_PATTERN_DETECT DSP[0]: AUTORESET_OVER_UNDER_FLOW
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: CLOCK_INVERT_M -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: CLOCK_INVERT_P
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: USE_SIMD bit 0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! PREG -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 23 -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 23 DSP[0]: BREG bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 22 DSP[0]: A_INPUT bit 0
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: BREG bit 2 DSP[0]: PATTERN bit 22
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 21
virtex5 DSP rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert OPMODE[5]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert OPMODE[4]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 11 DSP[1]: MASK bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 10 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 10 DSP[1]: PATTERN bit 9
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 8 DSP[1]: MASK bit 9
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 8
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 7
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 7
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 6
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 6
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 5 -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 5 DSP[1]: ! MULTCARRYINREG
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 4 DSP[1]: PATTERN bit 4
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert CARRYIN DSP[1]: ! CARRYINREG
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 3 DSP[1]: MASK bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: SCAN_IN_SETVAL_M bit 0
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: ! SCAN_IN_SET_M
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 2 -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 2 DSP[1]: TEST_SETVAL_M bit 0
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 1 DSP[1]: ! TEST_SET_M
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 1 -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 0 DSP[1]: MASK bit 0
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: ROUNDING_LSB_MASK bit 0 DSP[1]: ! SCAN_IN_SET_P
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: SCAN_IN_SETVAL_P bit 0 DSP[1]: ! MREG
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: SEL_PATTERN bit 0 DSP[0]: SEL_ROUNDING_MASK bit 1
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: SEL_MASK bit 0 -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert ALUMODE[0] DSP[0]: SEL_ROUNDING_MASK bit 0
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 47 DSP[0]: MASK bit 47
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 46 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 46 -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 45
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 45
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 44
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 44
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 43 -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 43 -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 42 DSP[0]: MASK bit 42
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 41 DSP[0]: MASK bit 41
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 40
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 40
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! ALUMODEREG -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert ALUMODE[2] DSP[0]: !invert ALUMODE[1]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 39 DSP[0]: PATTERN bit 39
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 38 -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: MASK bit 38 DSP[0]: PATTERN bit 37
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: ! CREG DSP[0]: MASK bit 37
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: !invert ALUMODE[3] DSP[0]: MASK bit 36
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[0]: PATTERN bit 36
virtex5 DSP rect MAIN[3]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 26 -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 26 -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 25 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 25 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 24
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 24
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert CLK -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: AUTORESET_PATTERN_DETECT_OPTINV
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: ! TEST_SET_P -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: AUTORESET_OVER_UNDER_FLOW -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: TEST_SETVAL_P bit 0 DSP[1]: AUTORESET_PATTERN_DETECT
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: CLOCK_INVERT_M -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: CLOCK_INVERT_P DSP[1]: USE_SIMD bit 0
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: ! PREG -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 23
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: BREG bit 1 DSP[1]: MASK bit 23
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: A_INPUT bit 0 -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 22 DSP[1]: BREG bit 2
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 22 -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 21 -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 21 -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 20
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 20 -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 19 DSP[1]: PATTERN bit 19
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 18 -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 18
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: USE_PATTERN_DETECT
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 17 DSP[1]: USE_MULT bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 17 -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 16 -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: B_INPUT bit 0 DSP[1]: PATTERN bit 16
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 15 DSP[1]: MASK bit 15
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: BREG bit 0 DSP[1]: USE_MULT bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: AREG bit 0 -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 14
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 14
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 13 DSP[1]: AREG bit 2
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 13 -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 12
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: AREG bit 1 -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: USE_SIMD bit 1
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: ! CARRYINSELREG
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert OPMODE[6]
virtex5 DSP rect MAIN[4]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: SEL_MASK bit 0 DSP[1]: SEL_ROUNDING_MASK bit 1
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: SEL_ROUNDING_MASK bit 0 DSP[1]: SEL_PATTERN bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 47 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 47 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 46 DSP[1]: PATTERN bit 46
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: LFSR_EN_SETVAL bit 0 DSP[1]: ! LFSR_EN_SET
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 45
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 45 -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 44
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert ALUMODE[0] DSP[1]: PATTERN bit 44
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: ! ALUMODEREG DSP[1]: !invert ALUMODE[1]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 43
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 43 -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 42 -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 42 DSP[1]: !invert ALUMODE[2]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: ! CREG DSP[1]: !invert ALUMODE[3]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 41 DSP[1]: MASK bit 41
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 40 -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 40 DSP[1]: ! OPMODEREG
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert OPMODE[0]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert OPMODE[1]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 39 -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 39 DSP[1]: MASK bit 38
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert OPMODE[3] DSP[1]: PATTERN bit 38
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 37 -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: !invert OPMODE[2] DSP[1]: MASK bit 37
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 36
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 36
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: USE_SIMD bit 2
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 35 -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 34 DSP[1]: MASK bit 35
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 33 DSP[1]: PATTERN bit 34
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 33 -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 32 -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 32
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 31
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 31
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 30
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 30
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 29 -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 29 DSP[1]: MASK bit 28
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 28
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: PATTERN bit 27
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP[1]: MASK bit 27