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Interconnect

TODO: document

Tile slots

virtex5 tile slots
SlotTilesBel slots
INTINTINT
INTFINTF, INTF_DELAYINTF_INT, INTF_TESTMUX
BELCLBLL, CLBLM, BRAM, DSP, IO, CMT, PPC, EMAC, PCIE, GTP, GTX, CLK_BUFGSPEC_INT, SLICE[0], SLICE[1], SLICE[2], SLICE[3], BRAM, BRAM_F, BRAM_H[0], BRAM_H[1], BRAM_ADDR, DSP[0], DSP[1], DSP_C, ILOGIC[0], ILOGIC[1], OLOGIC[0], OLOGIC[1], IODELAY[0], IODELAY[1], IDELAY[0], IDELAY[1], ODELAY[0], ODELAY[1], IOB[0], IOB[1], DCM[0], DCM[1], PLL[0], PLL[1], PPR_FRAME, PHASER_IN[0], PHASER_IN[1], PHASER_IN[2], PHASER_IN[3], PHASER_OUT[0], PHASER_OUT[1], PHASER_OUT[2], PHASER_OUT[3], PHASER_REF, PHY_CONTROL, BUFMRCE[0], BUFMRCE[1], CCM, PMCD[0], PMCD[1], DPM, BUFHCE_W[0], BUFHCE_W[1], BUFHCE_W[2], BUFHCE_W[3], BUFHCE_W[4], BUFHCE_W[5], BUFHCE_W[6], BUFHCE_W[7], BUFHCE_W[8], BUFHCE_W[9], BUFHCE_W[10], BUFHCE_W[11], BUFHCE_E[0], BUFHCE_E[1], BUFHCE_E[2], BUFHCE_E[3], BUFHCE_E[4], BUFHCE_E[5], BUFHCE_E[6], BUFHCE_E[7], BUFHCE_E[8], BUFHCE_E[9], BUFHCE_E[10], BUFHCE_E[11], PMV_CLK, PMVIOB_CLK, PMV2, PMV2_SVT, MTBF2, PPC, EMAC, PCIE, PCIE3, GT11[0], GT11[1], GT11CLK, GTP_DUAL, GTX_DUAL, HCLK_GTX, GTCLK[0], GTCLK[1], GTX[0], GTX[1], GTX[2], GTX[3], GTH_QUAD, HCLK_DRP_GTP_MID, GTP_COMMON, GTX_COMMON, GTP_CHANNEL, GTX_CHANNEL, CRC32[0], CRC32[1], CRC32[2], CRC32[3], BUFGCTRL[0], BUFGCTRL[1], BUFGCTRL[2], BUFGCTRL[3], BUFGCTRL[4], BUFGCTRL[5], BUFGCTRL[6], BUFGCTRL[7], BUFGCTRL[8], BUFGCTRL[9], BUFGCTRL[10], BUFGCTRL[11], BUFGCTRL[12], BUFGCTRL[13], BUFGCTRL[14], BUFGCTRL[15], BUFGCTRL[16], BUFGCTRL[17], BUFGCTRL[18], BUFGCTRL[19], BUFGCTRL[20], BUFGCTRL[21], BUFGCTRL[22], BUFGCTRL[23], BUFGCTRL[24], BUFGCTRL[25], BUFGCTRL[26], BUFGCTRL[27], BUFGCTRL[28], BUFGCTRL[29], BUFGCTRL[30], BUFGCTRL[31], PS
CMT_FIFOCMT_FIFO_INT, IN_FIFO, OUT_FIFO
CFGCFGSYSMON_INT, BSCAN[0], BSCAN[1], BSCAN[2], BSCAN[3], ICAP[0], ICAP[1], STARTUP, CAPTURE, JTAGPPC, PMV_CFG[0], PMV_CFG[1], DCIRESET, FRAME_ECC, USR_ACCESS, KEY_CLEAR, EFUSE_USR, DNA_PORT, CFG_IO_ACCESS, PMVIOB_CFG, MISC_CFG, SYSMON
CLKCLK_CMT_S, CLK_CMT_N, CLK_IOB_S, CLK_IOB_N, CLK_MGT_S, CLK_MGT_N, HCLK_MGT_BUFCLK_INT
HROWCLK_HROWHROW_INT
HCLKHCLKHCLK, GLOBALSIG, HCLK_DRP[0], HCLK_DRP[1]
HCLK_BELPMVBRAM, HCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_S, HCLK_IO_CMT_S, HCLK_IO_CFG_N, HCLK_IO_CMT_N, HCLK_CMTPMVBRAM, HCLK_IO_INT, HCLK_CMT_DRP, BUFR[0], BUFR[1], BUFR[2], BUFR[3], BUFIO[0], BUFIO[1], BUFIO[2], BUFIO[3], IDELAYCTRL, DCI, BANK, LVDS
GLOBALGLOBALGLOBAL

Bel slots

virtex5 bel slots
SlotClassTile slotTiles
INTroutingINTINT
INTF_INTroutingINTFINTF, INTF_DELAY
INTF_TESTMUXroutingINTFINTF, INTF_DELAY
SPEC_INTroutingBELIO, CMT, CLK_BUFG
SLICE[0]SLICE_V5BELCLBLL, CLBLM
SLICE[1]SLICE_V5BELCLBLL, CLBLM
SLICE[2]SLICE_V5BEL
SLICE[3]SLICE_V5BEL
BRAMBRAM_V5BELBRAM
BRAM_FlegacyBEL
BRAM_H[0]legacyBEL
BRAM_H[1]legacyBEL
BRAM_ADDRlegacyBEL
DSP[0]DSP_V5BELDSP
DSP[1]DSP_V5BELDSP
DSP_CDSP_CBEL
ILOGIC[0]ILOGICBELIO
ILOGIC[1]ILOGICBELIO
OLOGIC[0]OLOGICBELIO
OLOGIC[1]OLOGICBELIO
IODELAY[0]IODELAY_V5BELIO
IODELAY[1]IODELAY_V5BELIO
IDELAY[0]IDELAYBEL
IDELAY[1]IDELAYBEL
ODELAY[0]ODELAYBEL
ODELAY[1]ODELAYBEL
IOB[0]IOBBELIO
IOB[1]IOBBELIO
DCM[0]DCM_V5BELCMT
DCM[1]DCM_V5BELCMT
PLL[0]PLL_V5BELCMT
PLL[1]PLL_V5BEL
PPR_FRAMEPPR_FRAMEBEL
PHASER_IN[0]PHASER_INBEL
PHASER_IN[1]PHASER_INBEL
PHASER_IN[2]PHASER_INBEL
PHASER_IN[3]PHASER_INBEL
PHASER_OUT[0]PHASER_OUTBEL
PHASER_OUT[1]PHASER_OUTBEL
PHASER_OUT[2]PHASER_OUTBEL
PHASER_OUT[3]PHASER_OUTBEL
PHASER_REFPHASER_REFBEL
PHY_CONTROLPHY_CONTROLBEL
BUFMRCE[0]BUFHCEBEL
BUFMRCE[1]BUFHCEBEL
CCMCCMBEL
PMCD[0]PMCDBEL
PMCD[1]PMCDBEL
DPMDPMBEL
BUFHCE_W[0]BUFHCEBEL
BUFHCE_W[1]BUFHCEBEL
BUFHCE_W[2]BUFHCEBEL
BUFHCE_W[3]BUFHCEBEL
BUFHCE_W[4]BUFHCEBEL
BUFHCE_W[5]BUFHCEBEL
BUFHCE_W[6]BUFHCEBEL
BUFHCE_W[7]BUFHCEBEL
BUFHCE_W[8]BUFHCEBEL
BUFHCE_W[9]BUFHCEBEL
BUFHCE_W[10]BUFHCEBEL
BUFHCE_W[11]BUFHCEBEL
BUFHCE_E[0]BUFHCEBEL
BUFHCE_E[1]BUFHCEBEL
BUFHCE_E[2]BUFHCEBEL
BUFHCE_E[3]BUFHCEBEL
BUFHCE_E[4]BUFHCEBEL
BUFHCE_E[5]BUFHCEBEL
BUFHCE_E[6]BUFHCEBEL
BUFHCE_E[7]BUFHCEBEL
BUFHCE_E[8]BUFHCEBEL
BUFHCE_E[9]BUFHCEBEL
BUFHCE_E[10]BUFHCEBEL
BUFHCE_E[11]BUFHCEBEL
PMV_CLKPMVBEL
PMVIOB_CLKPMVIOBBEL
PMV2PMV2BEL
PMV2_SVTPMV2BEL
MTBF2MTBF2BEL
PPCPPC440BELPPC
EMACEMAC_V4BELEMAC
PCIEPCIE_V5BELPCIE
PCIE3PCIE3BEL
GT11[0]GT11BEL
GT11[1]GT11BEL
GT11CLKGT11CLKBEL
GTP_DUALGTP_DUALBELGTP
GTX_DUALGTX_DUALBELGTX
HCLK_GTXHCLK_GTXBEL
GTCLK[0]GTCLKBEL
GTCLK[1]GTCLKBEL
GTX[0]GTXBEL
GTX[1]GTXBEL
GTX[2]GTXBEL
GTX[3]GTXBEL
GTH_QUADGTH_QUADBEL
HCLK_DRP_GTP_MIDHCLK_DRPBEL
GTP_COMMONGTP_COMMONBEL
GTX_COMMONGTX_COMMONBEL
GTP_CHANNELGTP_CHANNELBEL
GTX_CHANNELGTX_CHANNELBEL
CRC32[0]CRC32BELGTP, GTX
CRC32[1]CRC32BELGTP, GTX
CRC32[2]CRC32BELGTP, GTX
CRC32[3]CRC32BELGTP, GTX
BUFGCTRL[0]BUFGCTRLBELCLK_BUFG
BUFGCTRL[1]BUFGCTRLBELCLK_BUFG
BUFGCTRL[2]BUFGCTRLBELCLK_BUFG
BUFGCTRL[3]BUFGCTRLBELCLK_BUFG
BUFGCTRL[4]BUFGCTRLBELCLK_BUFG
BUFGCTRL[5]BUFGCTRLBELCLK_BUFG
BUFGCTRL[6]BUFGCTRLBELCLK_BUFG
BUFGCTRL[7]BUFGCTRLBELCLK_BUFG
BUFGCTRL[8]BUFGCTRLBELCLK_BUFG
BUFGCTRL[9]BUFGCTRLBELCLK_BUFG
BUFGCTRL[10]BUFGCTRLBELCLK_BUFG
BUFGCTRL[11]BUFGCTRLBELCLK_BUFG
BUFGCTRL[12]BUFGCTRLBELCLK_BUFG
BUFGCTRL[13]BUFGCTRLBELCLK_BUFG
BUFGCTRL[14]BUFGCTRLBELCLK_BUFG
BUFGCTRL[15]BUFGCTRLBELCLK_BUFG
BUFGCTRL[16]BUFGCTRLBELCLK_BUFG
BUFGCTRL[17]BUFGCTRLBELCLK_BUFG
BUFGCTRL[18]BUFGCTRLBELCLK_BUFG
BUFGCTRL[19]BUFGCTRLBELCLK_BUFG
BUFGCTRL[20]BUFGCTRLBELCLK_BUFG
BUFGCTRL[21]BUFGCTRLBELCLK_BUFG
BUFGCTRL[22]BUFGCTRLBELCLK_BUFG
BUFGCTRL[23]BUFGCTRLBELCLK_BUFG
BUFGCTRL[24]BUFGCTRLBELCLK_BUFG
BUFGCTRL[25]BUFGCTRLBELCLK_BUFG
BUFGCTRL[26]BUFGCTRLBELCLK_BUFG
BUFGCTRL[27]BUFGCTRLBELCLK_BUFG
BUFGCTRL[28]BUFGCTRLBELCLK_BUFG
BUFGCTRL[29]BUFGCTRLBELCLK_BUFG
BUFGCTRL[30]BUFGCTRLBELCLK_BUFG
BUFGCTRL[31]BUFGCTRLBELCLK_BUFG
PSPSBEL
CMT_FIFO_INTroutingCMT_FIFO
IN_FIFOIN_FIFOCMT_FIFO
OUT_FIFOOUT_FIFOCMT_FIFO
SYSMON_INTroutingCFG
BSCAN[0]BSCANCFGCFG
BSCAN[1]BSCANCFGCFG
BSCAN[2]BSCANCFGCFG
BSCAN[3]BSCANCFGCFG
ICAP[0]ICAP_V4CFGCFG
ICAP[1]ICAP_V4CFGCFG
STARTUPSTARTUPCFGCFG
CAPTURECAPTURECFGCFG
JTAGPPCJTAGPPCCFGCFG
PMV_CFG[0]PMVCFGCFG
PMV_CFG[1]PMVCFG
DCIRESETDCIRESETCFGCFG
FRAME_ECCFRAME_ECC_V4CFGCFG
USR_ACCESSUSR_ACCESSCFGCFG
KEY_CLEARKEY_CLEARCFGCFG
EFUSE_USREFUSE_USRCFGCFG
DNA_PORTDNA_PORTCFG
CFG_IO_ACCESSCFG_IO_ACCESS_V6CFG
PMVIOB_CFGPMVIOBCFG
MISC_CFGMISC_CFGCFGCFG
SYSMONSYSMON_V5CFGCFG
CLK_INTroutingCLKCLK_CMT_S, CLK_CMT_N, CLK_IOB_S, CLK_IOB_N, CLK_MGT_S, CLK_MGT_N, HCLK_MGT_BUF
HROW_INTroutingHROWCLK_HROW
HCLKroutingHCLKHCLK
GLOBALSIGGLOBALSIGHCLKHCLK
HCLK_DRP[0]HCLK_DRPHCLK
HCLK_DRP[1]HCLK_DRPHCLK
PMVBRAMPMVBRAM_V5HCLK_BELPMVBRAM
HCLK_IO_INTroutingHCLK_BELHCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_S, HCLK_IO_CMT_S, HCLK_IO_CFG_N, HCLK_IO_CMT_N, HCLK_CMT
HCLK_CMT_DRPHCLK_CMT_DRPHCLK_BELHCLK_IO_CMT_S, HCLK_IO_CFG_N, HCLK_IO_CMT_N, HCLK_CMT
BUFR[0]BUFRHCLK_BELHCLK_IO
BUFR[1]BUFRHCLK_BELHCLK_IO
BUFR[2]BUFRHCLK_BEL
BUFR[3]BUFRHCLK_BEL
BUFIO[0]BUFIOHCLK_BELHCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_N, HCLK_IO_CMT_N
BUFIO[1]BUFIOHCLK_BELHCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_N, HCLK_IO_CMT_N
BUFIO[2]BUFIOHCLK_BELHCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_S, HCLK_IO_CMT_S
BUFIO[3]BUFIOHCLK_BELHCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_S, HCLK_IO_CMT_S
IDELAYCTRLIDELAYCTRLHCLK_BELHCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_S, HCLK_IO_CMT_S, HCLK_IO_CFG_N, HCLK_IO_CMT_N
DCIDCIHCLK_BELHCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_S, HCLK_IO_CMT_S, HCLK_IO_CFG_N, HCLK_IO_CMT_N
BANKBANKHCLK_BELHCLK_IO, HCLK_IO_CENTER, HCLK_IO_CFG_S, HCLK_IO_CMT_S, HCLK_IO_CFG_N, HCLK_IO_CMT_N
LVDSLVDS_V4HCLK_BEL
GLOBALGLOBALGLOBALGLOBAL

Connector slots

virtex5 connector slots
SlotOppositeConnectors
WEPASS_W, TERM_W, INT_BUFS_W, PPC_W
EWPASS_E, TERM_E, TERM_E_HOLE, INT_BUFS_E, PPC_E
SNPASS_S, TERM_S_HOLE, TERM_S_PPC
NSPASS_N, PASS_NHOLE_N, TERM_N_HOLE, TERM_N_PPC
IO_SIO_NIO_S
IO_NIO_SIO_N
CLK_PREVCLK_NEXTCLK_PREV
CLK_NEXTCLK_PREVCLK_NEXT
BEL_SBEL_N
BEL_NBEL_S
CMT_PREVCMT_NEXT
CMT_NEXTCMT_PREV
HCLK_ROW_PREVHCLK_ROW_NEXTHCLK_ROW_PREV, HCLK_ROW_PREV_PASS
HCLK_ROW_NEXTHCLK_ROW_PREVHCLK_ROW_NEXT

Region slots

virtex5 region slots
SlotWires
GLOBALGCLK[0], GCLK[1], GCLK[2], GCLK[3], GCLK[4], GCLK[5], GCLK[6], GCLK[7], GCLK[8], GCLK[9], GCLK[10], GCLK[11], GCLK[12], GCLK[13], GCLK[14], GCLK[15], GCLK[16], GCLK[17], GCLK[18], GCLK[19], GCLK[20], GCLK[21], GCLK[22], GCLK[23], GCLK[24], GCLK[25], GCLK[26], GCLK[27], GCLK[28], GCLK[29], GCLK[30], GCLK[31]
GIOBGIOB[0], GIOB[1], GIOB[2], GIOB[3], GIOB[4], GIOB[5], GIOB[6], GIOB[7], GIOB[8], GIOB[9]
HROWHCLK_ROW[0], HCLK_ROW[1], HCLK_ROW[2], HCLK_ROW[3], HCLK_ROW[4], HCLK_ROW[5], HCLK_ROW[6], HCLK_ROW[7], HCLK_ROW[8], HCLK_ROW[9], RCLK_ROW[0], RCLK_ROW[1], RCLK_ROW[2], RCLK_ROW[3]
LEAFHCLK[0], HCLK[1], HCLK[2], HCLK[3], HCLK[4], HCLK[5], HCLK[6], HCLK[7], HCLK[8], HCLK[9], RCLK[0], RCLK[1], RCLK[2], RCLK[3], HCLK_IO[0], HCLK_IO[1], HCLK_IO[2], HCLK_IO[3], HCLK_IO[4], HCLK_IO[5], HCLK_IO[6], HCLK_IO[7], HCLK_IO[8], HCLK_IO[9], RCLK_IO[0], RCLK_IO[1], RCLK_IO[2], RCLK_IO[3], IOCLK[0], IOCLK[1], IOCLK[2], IOCLK[3], HCLK_CMT[0], HCLK_CMT[1], HCLK_CMT[2], HCLK_CMT[3], HCLK_CMT[4], HCLK_CMT[5], HCLK_CMT[6], HCLK_CMT[7], HCLK_CMT[8], HCLK_CMT[9], GIOB_CMT[0], GIOB_CMT[1], GIOB_CMT[2], GIOB_CMT[3], GIOB_CMT[4], GIOB_CMT[5], GIOB_CMT[6], GIOB_CMT[7], GIOB_CMT[8], GIOB_CMT[9]

Wires

virtex5 wires
WireKind
PULLUPpullup
TIE_0tie 0
TIE_1tie 1
HCLK[0]regional LEAF
HCLK[1]regional LEAF
HCLK[2]regional LEAF
HCLK[3]regional LEAF
HCLK[4]regional LEAF
HCLK[5]regional LEAF
HCLK[6]regional LEAF
HCLK[7]regional LEAF
HCLK[8]regional LEAF
HCLK[9]regional LEAF
RCLK[0]regional LEAF
RCLK[1]regional LEAF
RCLK[2]regional LEAF
RCLK[3]regional LEAF
DBL_WW0_S0mux
DBL_WW0_N5mux
DBL_WW0[0]branch S
DBL_WW0[1]mux
DBL_WW0[2]mux
DBL_WW0[3]mux
DBL_WW0[4]mux
DBL_WW0[5]branch N
DBL_WW1[0]branch E
DBL_WW1[1]branch E
DBL_WW1[2]branch E
DBL_WW1[3]branch E
DBL_WW1[4]branch E
DBL_WW1[5]branch E
DBL_WW2[0]branch E
DBL_WW2[1]branch E
DBL_WW2[2]branch E
DBL_WW2[3]branch E
DBL_WW2[4]branch E
DBL_WW2[5]branch E
DBL_WS0[0]mux
DBL_WS0[1]mux
DBL_WS0[2]mux
DBL_WS1[0]branch E
DBL_WS1[1]branch E
DBL_WS1[2]branch E
DBL_WS2[0]branch N
DBL_WS2[1]branch N
DBL_WS2[2]branch N
DBL_WS1_BUF0mux
DBL_WS1_S0branch N
DBL_WN0[0]mux
DBL_WN0[1]mux
DBL_WN0[2]mux
DBL_WN1[0]branch E
DBL_WN1[1]branch E
DBL_WN1[2]branch E
DBL_WN2[0]branch S
DBL_WN2[1]branch S
DBL_WN2[2]branch S
DBL_WN2_S0branch N
DBL_EE0_S3mux
DBL_EE0[0]mux
DBL_EE0[1]mux
DBL_EE0[2]mux
DBL_EE0[3]branch S
DBL_EE0[4]mux
DBL_EE0[5]mux
DBL_EE1[0]branch W
DBL_EE1[1]branch W
DBL_EE1[2]branch W
DBL_EE1[3]branch W
DBL_EE1[4]branch W
DBL_EE1[5]branch W
DBL_EE2[0]branch W
DBL_EE2[1]branch W
DBL_EE2[2]branch W
DBL_EE2[3]branch W
DBL_EE2[4]branch W
DBL_EE2[5]branch W
DBL_ES0[0]mux
DBL_ES0[1]mux
DBL_ES0[2]mux
DBL_ES1[0]branch W
DBL_ES1[1]branch W
DBL_ES1[2]branch W
DBL_ES2[0]branch N
DBL_ES2[1]branch N
DBL_ES2[2]branch N
DBL_EN0[0]mux
DBL_EN0[1]mux
DBL_EN0[2]mux
DBL_EN1[0]branch W
DBL_EN1[1]branch W
DBL_EN1[2]branch W
DBL_EN2[0]branch S
DBL_EN2[1]branch S
DBL_EN2[2]branch S
DBL_NN0_S0mux
DBL_NN0_N5mux
DBL_NN0[0]branch S
DBL_NN0[1]mux
DBL_NN0[2]mux
DBL_NN0[3]mux
DBL_NN0[4]mux
DBL_NN0[5]branch N
DBL_NN1[0]branch S
DBL_NN1[1]branch S
DBL_NN1[2]branch S
DBL_NN1[3]branch S
DBL_NN1[4]branch S
DBL_NN1[5]branch S
DBL_NN2[0]branch S
DBL_NN2[1]branch S
DBL_NN2[2]branch S
DBL_NN2[3]branch S
DBL_NN2[4]branch S
DBL_NN2[5]branch S
DBL_NW0[0]mux
DBL_NW0[1]mux
DBL_NW0[2]mux
DBL_NW1[0]branch S
DBL_NW1[1]branch S
DBL_NW1[2]branch S
DBL_NW2[0]branch E
DBL_NW2[1]branch E
DBL_NW2[2]branch E
DBL_NW2_N2branch S
DBL_NE0[0]mux
DBL_NE0[1]mux
DBL_NE0[2]mux
DBL_NE1[0]branch S
DBL_NE1[1]branch S
DBL_NE1[2]branch S
DBL_NE2[0]branch W
DBL_NE2[1]branch W
DBL_NE2[2]branch W
DBL_NE1_BUF2mux
DBL_NE1_N2branch S
DBL_SS0_N2mux
DBL_SS0[0]mux
DBL_SS0[1]mux
DBL_SS0[2]branch N
DBL_SS0[3]mux
DBL_SS0[4]mux
DBL_SS0[5]mux
DBL_SS1[0]branch N
DBL_SS1[1]branch N
DBL_SS1[2]branch N
DBL_SS1[3]branch N
DBL_SS1[4]branch N
DBL_SS1[5]branch N
DBL_SS2[0]branch N
DBL_SS2[1]branch N
DBL_SS2[2]branch N
DBL_SS2[3]branch N
DBL_SS2[4]branch N
DBL_SS2[5]branch N
DBL_SW0[0]mux
DBL_SW0[1]mux
DBL_SW0[2]mux
DBL_SW1[0]branch N
DBL_SW1[1]branch N
DBL_SW1[2]branch N
DBL_SW2[0]branch E
DBL_SW2[1]branch E
DBL_SW2[2]branch E
DBL_SE0[0]mux
DBL_SE0[1]mux
DBL_SE0[2]mux
DBL_SE1[0]branch N
DBL_SE1[1]branch N
DBL_SE1[2]branch N
DBL_SE2[0]branch W
DBL_SE2[1]branch W
DBL_SE2[2]branch W
PENT_WW0_S0mux
PENT_WW0[0]branch S
PENT_WW0[1]mux
PENT_WW0[2]mux
PENT_WW0[3]mux
PENT_WW0[4]mux
PENT_WW0[5]mux
PENT_WW1[0]branch E
PENT_WW1[1]branch E
PENT_WW1[2]branch E
PENT_WW1[3]branch E
PENT_WW1[4]branch E
PENT_WW1[5]branch E
PENT_WW2[0]branch E
PENT_WW2[1]branch E
PENT_WW2[2]branch E
PENT_WW2[3]branch E
PENT_WW2[4]branch E
PENT_WW2[5]branch E
PENT_WW3[0]branch E
PENT_WW3[1]branch E
PENT_WW3[2]branch E
PENT_WW3[3]branch E
PENT_WW3[4]branch E
PENT_WW3[5]branch E
PENT_WW4[0]branch E
PENT_WW4[1]branch E
PENT_WW4[2]branch E
PENT_WW4[3]branch E
PENT_WW4[4]branch E
PENT_WW4[5]branch E
PENT_WW5[0]branch E
PENT_WW5[1]branch E
PENT_WW5[2]branch E
PENT_WW5[3]branch E
PENT_WW5[4]branch E
PENT_WW5[5]branch E
PENT_WS0[0]mux
PENT_WS0[1]mux
PENT_WS0[2]mux
PENT_WS1[0]branch E
PENT_WS1[1]branch E
PENT_WS1[2]branch E
PENT_WS2[0]branch E
PENT_WS2[1]branch E
PENT_WS2[2]branch E
PENT_WS3[0]branch E
PENT_WS3[1]branch E
PENT_WS3[2]branch E
PENT_WS4[0]branch N
PENT_WS4[1]branch N
PENT_WS4[2]branch N
PENT_WS5[0]branch N
PENT_WS5[1]branch N
PENT_WS5[2]branch N
PENT_WS3_BUF0mux
PENT_WS3_S0branch N
PENT_WN0[0]mux
PENT_WN0[1]mux
PENT_WN0[2]mux
PENT_WN1[0]branch E
PENT_WN1[1]branch E
PENT_WN1[2]branch E
PENT_WN2[0]branch E
PENT_WN2[1]branch E
PENT_WN2[2]branch E
PENT_WN3[0]branch E
PENT_WN3[1]branch E
PENT_WN3[2]branch E
PENT_WN4[0]branch S
PENT_WN4[1]branch S
PENT_WN4[2]branch S
PENT_WN5[0]branch S
PENT_WN5[1]branch S
PENT_WN5[2]branch S
PENT_WN5_S0branch N
PENT_EE0[0]mux
PENT_EE0[1]mux
PENT_EE0[2]mux
PENT_EE0[3]mux
PENT_EE0[4]mux
PENT_EE0[5]mux
PENT_EE1[0]branch W
PENT_EE1[1]branch W
PENT_EE1[2]branch W
PENT_EE1[3]branch W
PENT_EE1[4]branch W
PENT_EE1[5]branch W
PENT_EE2[0]branch W
PENT_EE2[1]branch W
PENT_EE2[2]branch W
PENT_EE2[3]branch W
PENT_EE2[4]branch W
PENT_EE2[5]branch W
PENT_EE3[0]branch W
PENT_EE3[1]branch W
PENT_EE3[2]branch W
PENT_EE3[3]branch W
PENT_EE3[4]branch W
PENT_EE3[5]branch W
PENT_EE4[0]branch W
PENT_EE4[1]branch W
PENT_EE4[2]branch W
PENT_EE4[3]branch W
PENT_EE4[4]branch W
PENT_EE4[5]branch W
PENT_EE5[0]branch W
PENT_EE5[1]branch W
PENT_EE5[2]branch W
PENT_EE5[3]branch W
PENT_EE5[4]branch W
PENT_EE5[5]branch W
PENT_ES0[0]mux
PENT_ES0[1]mux
PENT_ES0[2]mux
PENT_ES1[0]branch W
PENT_ES1[1]branch W
PENT_ES1[2]branch W
PENT_ES2[0]branch W
PENT_ES2[1]branch W
PENT_ES2[2]branch W
PENT_ES3[0]branch W
PENT_ES3[1]branch W
PENT_ES3[2]branch W
PENT_ES4[0]branch N
PENT_ES4[1]branch N
PENT_ES4[2]branch N
PENT_ES5[0]branch N
PENT_ES5[1]branch N
PENT_ES5[2]branch N
PENT_EN0[0]mux
PENT_EN0[1]mux
PENT_EN0[2]mux
PENT_EN1[0]branch W
PENT_EN1[1]branch W
PENT_EN1[2]branch W
PENT_EN2[0]branch W
PENT_EN2[1]branch W
PENT_EN2[2]branch W
PENT_EN3[0]branch W
PENT_EN3[1]branch W
PENT_EN3[2]branch W
PENT_EN4[0]branch S
PENT_EN4[1]branch S
PENT_EN4[2]branch S
PENT_EN5[0]branch S
PENT_EN5[1]branch S
PENT_EN5[2]branch S
PENT_SS0[0]mux
PENT_SS0[1]mux
PENT_SS0[2]mux
PENT_SS0[3]mux
PENT_SS0[4]mux
PENT_SS0[5]mux
PENT_SS1[0]branch N
PENT_SS1[1]branch N
PENT_SS1[2]branch N
PENT_SS1[3]branch N
PENT_SS1[4]branch N
PENT_SS1[5]branch N
PENT_SS2[0]branch N
PENT_SS2[1]branch N
PENT_SS2[2]branch N
PENT_SS2[3]branch N
PENT_SS2[4]branch N
PENT_SS2[5]branch N
PENT_SS3[0]branch N
PENT_SS3[1]branch N
PENT_SS3[2]branch N
PENT_SS3[3]branch N
PENT_SS3[4]branch N
PENT_SS3[5]branch N
PENT_SS4[0]branch N
PENT_SS4[1]branch N
PENT_SS4[2]branch N
PENT_SS4[3]branch N
PENT_SS4[4]branch N
PENT_SS4[5]branch N
PENT_SS5[0]branch N
PENT_SS5[1]branch N
PENT_SS5[2]branch N
PENT_SS5[3]branch N
PENT_SS5[4]branch N
PENT_SS5[5]branch N
PENT_SW0[0]mux
PENT_SW0[1]mux
PENT_SW0[2]mux
PENT_SW1[0]branch N
PENT_SW1[1]branch N
PENT_SW1[2]branch N
PENT_SW2[0]branch N
PENT_SW2[1]branch N
PENT_SW2[2]branch N
PENT_SW3[0]branch N
PENT_SW3[1]branch N
PENT_SW3[2]branch N
PENT_SW4[0]branch E
PENT_SW4[1]branch E
PENT_SW4[2]branch E
PENT_SW5[0]branch E
PENT_SW5[1]branch E
PENT_SW5[2]branch E
PENT_SE0[0]mux
PENT_SE0[1]mux
PENT_SE0[2]mux
PENT_SE1[0]branch N
PENT_SE1[1]branch N
PENT_SE1[2]branch N
PENT_SE2[0]branch N
PENT_SE2[1]branch N
PENT_SE2[2]branch N
PENT_SE3[0]branch N
PENT_SE3[1]branch N
PENT_SE3[2]branch N
PENT_SE4[0]branch W
PENT_SE4[1]branch W
PENT_SE4[2]branch W
PENT_SE5[0]branch W
PENT_SE5[1]branch W
PENT_SE5[2]branch W
PENT_NN0_N5mux
PENT_NN0[0]mux
PENT_NN0[1]mux
PENT_NN0[2]mux
PENT_NN0[3]mux
PENT_NN0[4]mux
PENT_NN0[5]branch N
PENT_NN1[0]branch S
PENT_NN1[1]branch S
PENT_NN1[2]branch S
PENT_NN1[3]branch S
PENT_NN1[4]branch S
PENT_NN1[5]branch S
PENT_NN2[0]branch S
PENT_NN2[1]branch S
PENT_NN2[2]branch S
PENT_NN2[3]branch S
PENT_NN2[4]branch S
PENT_NN2[5]branch S
PENT_NN3[0]branch S
PENT_NN3[1]branch S
PENT_NN3[2]branch S
PENT_NN3[3]branch S
PENT_NN3[4]branch S
PENT_NN3[5]branch S
PENT_NN4[0]branch S
PENT_NN4[1]branch S
PENT_NN4[2]branch S
PENT_NN4[3]branch S
PENT_NN4[4]branch S
PENT_NN4[5]branch S
PENT_NN5[0]branch S
PENT_NN5[1]branch S
PENT_NN5[2]branch S
PENT_NN5[3]branch S
PENT_NN5[4]branch S
PENT_NN5[5]branch S
PENT_NW0[0]mux
PENT_NW0[1]mux
PENT_NW0[2]mux
PENT_NW1[0]branch S
PENT_NW1[1]branch S
PENT_NW1[2]branch S
PENT_NW2[0]branch S
PENT_NW2[1]branch S
PENT_NW2[2]branch S
PENT_NW3[0]branch S
PENT_NW3[1]branch S
PENT_NW3[2]branch S
PENT_NW4[0]branch E
PENT_NW4[1]branch E
PENT_NW4[2]branch E
PENT_NW5[0]branch E
PENT_NW5[1]branch E
PENT_NW5[2]branch E
PENT_NW5_N2branch S
PENT_NE0[0]mux
PENT_NE0[1]mux
PENT_NE0[2]mux
PENT_NE1[0]branch S
PENT_NE1[1]branch S
PENT_NE1[2]branch S
PENT_NE2[0]branch S
PENT_NE2[1]branch S
PENT_NE2[2]branch S
PENT_NE3[0]branch S
PENT_NE3[1]branch S
PENT_NE3[2]branch S
PENT_NE4[0]branch W
PENT_NE4[1]branch W
PENT_NE4[2]branch W
PENT_NE5[0]branch W
PENT_NE5[1]branch W
PENT_NE5[2]branch W
PENT_NE3_BUF2mux
PENT_NE3_N2branch S
LH[0]multi_branch W
LH[1]multi_branch W
LH[2]multi_branch W
LH[3]multi_branch W
LH[4]multi_branch W
LH[5]multi_branch W
LH[6]multi_branch W
LH[7]multi_branch W
LH[8]multi_branch W
LH[9]multi_root
LH[10]multi_branch E
LH[11]multi_branch E
LH[12]multi_branch E
LH[13]multi_branch E
LH[14]multi_branch E
LH[15]multi_branch E
LH[16]multi_branch E
LH[17]multi_branch E
LH[18]multi_branch E
LV[0]multi_branch N
LV[1]multi_branch N
LV[2]multi_branch N
LV[3]multi_branch N
LV[4]multi_branch N
LV[5]multi_branch N
LV[6]multi_branch N
LV[7]multi_branch N
LV[8]multi_branch N
LV[9]multi_root
LV[10]multi_branch S
LV[11]multi_branch S
LV[12]multi_branch S
LV[13]multi_branch S
LV[14]multi_branch S
LV[15]multi_branch S
LV[16]multi_branch S
LV[17]multi_branch S
LV[18]multi_branch S
IMUX_GFAN[0]mux
IMUX_GFAN[1]mux
IMUX_CLK[0]mux
IMUX_CLK[1]mux
IMUX_CTRL[0]mux
IMUX_CTRL[1]mux
IMUX_CTRL[2]mux
IMUX_CTRL[3]mux
IMUX_CTRL_SITE[0]mux
IMUX_CTRL_SITE[1]mux
IMUX_CTRL_SITE[2]mux
IMUX_CTRL_SITE[3]mux
IMUX_CTRL_BOUNCE[0]mux
IMUX_CTRL_BOUNCE[1]mux
IMUX_CTRL_BOUNCE[2]mux
IMUX_CTRL_BOUNCE[3]mux
IMUX_CTRL_BOUNCE_S0branch N
IMUX_CTRL_BOUNCE_N3branch S
IMUX_BYP[0]mux
IMUX_BYP[1]mux
IMUX_BYP[2]mux
IMUX_BYP[3]mux
IMUX_BYP[4]mux
IMUX_BYP[5]mux
IMUX_BYP[6]mux
IMUX_BYP[7]mux
IMUX_BYP_SITE[0]mux
IMUX_BYP_SITE[1]mux
IMUX_BYP_SITE[2]mux
IMUX_BYP_SITE[3]mux
IMUX_BYP_SITE[4]mux
IMUX_BYP_SITE[5]mux
IMUX_BYP_SITE[6]mux
IMUX_BYP_SITE[7]mux
IMUX_BYP_BOUNCE[0]mux
IMUX_BYP_BOUNCE[1]mux
IMUX_BYP_BOUNCE[2]mux
IMUX_BYP_BOUNCE[3]mux
IMUX_BYP_BOUNCE[4]mux
IMUX_BYP_BOUNCE[5]mux
IMUX_BYP_BOUNCE[6]mux
IMUX_BYP_BOUNCE[7]mux
IMUX_BYP_BOUNCE_S0branch N
IMUX_BYP_BOUNCE_N3branch S
IMUX_BYP_BOUNCE_S4branch N
IMUX_BYP_BOUNCE_N7branch S
IMUX_FAN[0]mux
IMUX_FAN[1]mux
IMUX_FAN[2]mux
IMUX_FAN[3]mux
IMUX_FAN[4]mux
IMUX_FAN[5]mux
IMUX_FAN[6]mux
IMUX_FAN[7]mux
IMUX_FAN_SITE[0]mux
IMUX_FAN_SITE[1]mux
IMUX_FAN_SITE[2]mux
IMUX_FAN_SITE[3]mux
IMUX_FAN_SITE[4]mux
IMUX_FAN_SITE[5]mux
IMUX_FAN_SITE[6]mux
IMUX_FAN_SITE[7]mux
IMUX_FAN_BOUNCE[0]mux
IMUX_FAN_BOUNCE[1]mux
IMUX_FAN_BOUNCE[2]mux
IMUX_FAN_BOUNCE[3]mux
IMUX_FAN_BOUNCE[4]mux
IMUX_FAN_BOUNCE[5]mux
IMUX_FAN_BOUNCE[6]mux
IMUX_FAN_BOUNCE[7]mux
IMUX_FAN_BOUNCE_S0branch N
IMUX_FAN_BOUNCE_N7branch S
IMUX_IMUX[0]mux
IMUX_IMUX[1]mux
IMUX_IMUX[2]mux
IMUX_IMUX[3]mux
IMUX_IMUX[4]mux
IMUX_IMUX[5]mux
IMUX_IMUX[6]mux
IMUX_IMUX[7]mux
IMUX_IMUX[8]mux
IMUX_IMUX[9]mux
IMUX_IMUX[10]mux
IMUX_IMUX[11]mux
IMUX_IMUX[12]mux
IMUX_IMUX[13]mux
IMUX_IMUX[14]mux
IMUX_IMUX[15]mux
IMUX_IMUX[16]mux
IMUX_IMUX[17]mux
IMUX_IMUX[18]mux
IMUX_IMUX[19]mux
IMUX_IMUX[20]mux
IMUX_IMUX[21]mux
IMUX_IMUX[22]mux
IMUX_IMUX[23]mux
IMUX_IMUX[24]mux
IMUX_IMUX[25]mux
IMUX_IMUX[26]mux
IMUX_IMUX[27]mux
IMUX_IMUX[28]mux
IMUX_IMUX[29]mux
IMUX_IMUX[30]mux
IMUX_IMUX[31]mux
IMUX_IMUX[32]mux
IMUX_IMUX[33]mux
IMUX_IMUX[34]mux
IMUX_IMUX[35]mux
IMUX_IMUX[36]mux
IMUX_IMUX[37]mux
IMUX_IMUX[38]mux
IMUX_IMUX[39]mux
IMUX_IMUX[40]mux
IMUX_IMUX[41]mux
IMUX_IMUX[42]mux
IMUX_IMUX[43]mux
IMUX_IMUX[44]mux
IMUX_IMUX[45]mux
IMUX_IMUX[46]mux
IMUX_IMUX[47]mux
IMUX_IMUX_DELAY[0]mux
IMUX_IMUX_DELAY[1]mux
IMUX_IMUX_DELAY[2]mux
IMUX_IMUX_DELAY[3]mux
IMUX_IMUX_DELAY[4]mux
IMUX_IMUX_DELAY[5]mux
IMUX_IMUX_DELAY[6]mux
IMUX_IMUX_DELAY[7]mux
IMUX_IMUX_DELAY[8]mux
IMUX_IMUX_DELAY[9]mux
IMUX_IMUX_DELAY[10]mux
IMUX_IMUX_DELAY[11]mux
IMUX_IMUX_DELAY[12]mux
IMUX_IMUX_DELAY[13]mux
IMUX_IMUX_DELAY[14]mux
IMUX_IMUX_DELAY[15]mux
IMUX_IMUX_DELAY[16]mux
IMUX_IMUX_DELAY[17]mux
IMUX_IMUX_DELAY[18]mux
IMUX_IMUX_DELAY[19]mux
IMUX_IMUX_DELAY[20]mux
IMUX_IMUX_DELAY[21]mux
IMUX_IMUX_DELAY[22]mux
IMUX_IMUX_DELAY[23]mux
IMUX_IMUX_DELAY[24]mux
IMUX_IMUX_DELAY[25]mux
IMUX_IMUX_DELAY[26]mux
IMUX_IMUX_DELAY[27]mux
IMUX_IMUX_DELAY[28]mux
IMUX_IMUX_DELAY[29]mux
IMUX_IMUX_DELAY[30]mux
IMUX_IMUX_DELAY[31]mux
IMUX_IMUX_DELAY[32]mux
IMUX_IMUX_DELAY[33]mux
IMUX_IMUX_DELAY[34]mux
IMUX_IMUX_DELAY[35]mux
IMUX_IMUX_DELAY[36]mux
IMUX_IMUX_DELAY[37]mux
IMUX_IMUX_DELAY[38]mux
IMUX_IMUX_DELAY[39]mux
IMUX_IMUX_DELAY[40]mux
IMUX_IMUX_DELAY[41]mux
IMUX_IMUX_DELAY[42]mux
IMUX_IMUX_DELAY[43]mux
IMUX_IMUX_DELAY[44]mux
IMUX_IMUX_DELAY[45]mux
IMUX_IMUX_DELAY[46]mux
IMUX_IMUX_DELAY[47]mux
OUT[0]bel
OUT[1]bel
OUT[2]bel
OUT[3]bel
OUT[4]bel
OUT[5]bel
OUT[6]bel
OUT[7]bel
OUT[8]bel
OUT[9]bel
OUT[10]bel
OUT[11]bel
OUT[12]bel
OUT[13]bel
OUT[14]bel
OUT[15]bel
OUT[16]bel
OUT[17]bel
OUT[18]bel
OUT[19]bel
OUT[20]bel
OUT[21]bel
OUT[22]bel
OUT[23]bel
OUT_BEL[0]bel
OUT_BEL[1]bel
OUT_BEL[2]bel
OUT_BEL[3]bel
OUT_BEL[4]bel
OUT_BEL[5]bel
OUT_BEL[6]bel
OUT_BEL[7]bel
OUT_BEL[8]bel
OUT_BEL[9]bel
OUT_BEL[10]bel
OUT_BEL[11]bel
OUT_BEL[12]bel
OUT_BEL[13]bel
OUT_BEL[14]bel
OUT_BEL[15]bel
OUT_BEL[16]bel
OUT_BEL[17]bel
OUT_BEL[18]bel
OUT_BEL[19]bel
OUT_BEL[20]bel
OUT_BEL[21]bel
OUT_BEL[22]bel
OUT_BEL[23]bel
OUT_TEST[0]test
OUT_TEST[1]test
OUT_TEST[2]test
OUT_TEST[3]test
OUT_TEST[4]test
OUT_TEST[5]test
OUT_TEST[6]test
OUT_TEST[7]test
OUT_TEST[8]test
OUT_TEST[9]test
OUT_TEST[10]test
OUT_TEST[11]test
OUT_TEST[12]test
OUT_TEST[13]test
OUT_TEST[14]test
OUT_TEST[15]test
OUT_TEST[16]test
OUT_TEST[17]test
OUT_TEST[18]test
OUT_TEST[19]test
OUT_TEST[20]test
OUT_TEST[21]test
OUT_TEST[22]test
OUT_TEST[23]test
OUT_S12_DBLbranch N
OUT_N15_DBLbranch S
OUT_N17_DBLbranch S
OUT_S18_DBLbranch N
OUT_S12_PENTbranch N
OUT_N15_PENTbranch S
OUT_N17_PENTbranch S
OUT_S18_PENTbranch N
IMUX_SPEC[0]test
IMUX_SPEC[1]test
IMUX_SPEC[2]test
IMUX_SPEC[3]test
HCLK_ROW[0]regional HROW
HCLK_ROW[1]regional HROW
HCLK_ROW[2]regional HROW
HCLK_ROW[3]regional HROW
HCLK_ROW[4]regional HROW
HCLK_ROW[5]regional HROW
HCLK_ROW[6]regional HROW
HCLK_ROW[7]regional HROW
HCLK_ROW[8]regional HROW
HCLK_ROW[9]regional HROW
RCLK_ROW[0]regional HROW
RCLK_ROW[1]regional HROW
RCLK_ROW[2]regional HROW
RCLK_ROW[3]regional HROW
MGT_ROW_I[0]branch HCLK_ROW_PREV
MGT_ROW_I[1]branch HCLK_ROW_PREV
MGT_ROW_I[2]branch HCLK_ROW_PREV
MGT_ROW_I[3]branch HCLK_ROW_PREV
MGT_ROW_I[4]branch HCLK_ROW_PREV
MGT_ROW_O[0]mux
MGT_ROW_O[1]mux
MGT_ROW_O[2]mux
MGT_ROW_O[3]mux
MGT_ROW_O[4]mux
OUT_BUFG[0]bel
OUT_BUFG[1]bel
OUT_BUFG[2]bel
OUT_BUFG[3]bel
OUT_BUFG[4]bel
OUT_BUFG[5]bel
OUT_BUFG[6]bel
OUT_BUFG[7]bel
OUT_BUFG[8]bel
OUT_BUFG[9]bel
OUT_BUFG[10]bel
OUT_BUFG[11]bel
OUT_BUFG[12]bel
OUT_BUFG[13]bel
OUT_BUFG[14]bel
OUT_BUFG[15]bel
OUT_BUFG[16]bel
OUT_BUFG[17]bel
OUT_BUFG[18]bel
OUT_BUFG[19]bel
OUT_BUFG[20]bel
OUT_BUFG[21]bel
OUT_BUFG[22]bel
OUT_BUFG[23]bel
OUT_BUFG[24]bel
OUT_BUFG[25]bel
OUT_BUFG[26]bel
OUT_BUFG[27]bel
OUT_BUFG[28]bel
OUT_BUFG[29]bel
OUT_BUFG[30]bel
OUT_BUFG[31]bel
GCLK[0]regional GLOBAL
GCLK[1]regional GLOBAL
GCLK[2]regional GLOBAL
GCLK[3]regional GLOBAL
GCLK[4]regional GLOBAL
GCLK[5]regional GLOBAL
GCLK[6]regional GLOBAL
GCLK[7]regional GLOBAL
GCLK[8]regional GLOBAL
GCLK[9]regional GLOBAL
GCLK[10]regional GLOBAL
GCLK[11]regional GLOBAL
GCLK[12]regional GLOBAL
GCLK[13]regional GLOBAL
GCLK[14]regional GLOBAL
GCLK[15]regional GLOBAL
GCLK[16]regional GLOBAL
GCLK[17]regional GLOBAL
GCLK[18]regional GLOBAL
GCLK[19]regional GLOBAL
GCLK[20]regional GLOBAL
GCLK[21]regional GLOBAL
GCLK[22]regional GLOBAL
GCLK[23]regional GLOBAL
GCLK[24]regional GLOBAL
GCLK[25]regional GLOBAL
GCLK[26]regional GLOBAL
GCLK[27]regional GLOBAL
GCLK[28]regional GLOBAL
GCLK[29]regional GLOBAL
GCLK[30]regional GLOBAL
GCLK[31]regional GLOBAL
GCLK_BUF[0]mux
GCLK_BUF[1]mux
GCLK_BUF[2]mux
GCLK_BUF[3]mux
GCLK_BUF[4]mux
GCLK_BUF[5]mux
GCLK_BUF[6]mux
GCLK_BUF[7]mux
GCLK_BUF[8]mux
GCLK_BUF[9]mux
GCLK_BUF[10]mux
GCLK_BUF[11]mux
GCLK_BUF[12]mux
GCLK_BUF[13]mux
GCLK_BUF[14]mux
GCLK_BUF[15]mux
GCLK_BUF[16]mux
GCLK_BUF[17]mux
GCLK_BUF[18]mux
GCLK_BUF[19]mux
GCLK_BUF[20]mux
GCLK_BUF[21]mux
GCLK_BUF[22]mux
GCLK_BUF[23]mux
GCLK_BUF[24]mux
GCLK_BUF[25]mux
GCLK_BUF[26]mux
GCLK_BUF[27]mux
GCLK_BUF[28]mux
GCLK_BUF[29]mux
GCLK_BUF[30]mux
GCLK_BUF[31]mux
GIOB[0]regional GIOB
GIOB[1]regional GIOB
GIOB[2]regional GIOB
GIOB[3]regional GIOB
GIOB[4]regional GIOB
GIOB[5]regional GIOB
GIOB[6]regional GIOB
GIOB[7]regional GIOB
GIOB[8]regional GIOB
GIOB[9]regional GIOB
IMUX_BUFG_O[0]mux
IMUX_BUFG_O[1]mux
IMUX_BUFG_O[2]mux
IMUX_BUFG_O[3]mux
IMUX_BUFG_O[4]mux
IMUX_BUFG_O[5]mux
IMUX_BUFG_O[6]mux
IMUX_BUFG_O[7]mux
IMUX_BUFG_O[8]mux
IMUX_BUFG_O[9]mux
IMUX_BUFG_O[10]mux
IMUX_BUFG_O[11]mux
IMUX_BUFG_O[12]mux
IMUX_BUFG_O[13]mux
IMUX_BUFG_O[14]mux
IMUX_BUFG_O[15]mux
IMUX_BUFG_O[16]mux
IMUX_BUFG_O[17]mux
IMUX_BUFG_O[18]mux
IMUX_BUFG_O[19]mux
IMUX_BUFG_O[20]mux
IMUX_BUFG_O[21]mux
IMUX_BUFG_O[22]mux
IMUX_BUFG_O[23]mux
IMUX_BUFG_O[24]mux
IMUX_BUFG_O[25]mux
IMUX_BUFG_O[26]mux
IMUX_BUFG_O[27]mux
IMUX_BUFG_O[28]mux
IMUX_BUFG_O[29]mux
IMUX_BUFG_O[30]mux
IMUX_BUFG_O[31]mux
IMUX_BUFG_I[0]branch CLK_PREV
IMUX_BUFG_I[1]branch CLK_PREV
IMUX_BUFG_I[2]branch CLK_PREV
IMUX_BUFG_I[3]branch CLK_PREV
IMUX_BUFG_I[4]branch CLK_PREV
IMUX_BUFG_I[5]branch CLK_PREV
IMUX_BUFG_I[6]branch CLK_PREV
IMUX_BUFG_I[7]branch CLK_PREV
IMUX_BUFG_I[8]branch CLK_PREV
IMUX_BUFG_I[9]branch CLK_PREV
IMUX_BUFG_I[10]branch CLK_PREV
IMUX_BUFG_I[11]branch CLK_PREV
IMUX_BUFG_I[12]branch CLK_PREV
IMUX_BUFG_I[13]branch CLK_PREV
IMUX_BUFG_I[14]branch CLK_PREV
IMUX_BUFG_I[15]branch CLK_PREV
IMUX_BUFG_I[16]branch CLK_PREV
IMUX_BUFG_I[17]branch CLK_PREV
IMUX_BUFG_I[18]branch CLK_PREV
IMUX_BUFG_I[19]branch CLK_PREV
IMUX_BUFG_I[20]branch CLK_PREV
IMUX_BUFG_I[21]branch CLK_PREV
IMUX_BUFG_I[22]branch CLK_PREV
IMUX_BUFG_I[23]branch CLK_PREV
IMUX_BUFG_I[24]branch CLK_PREV
IMUX_BUFG_I[25]branch CLK_PREV
IMUX_BUFG_I[26]branch CLK_PREV
IMUX_BUFG_I[27]branch CLK_PREV
IMUX_BUFG_I[28]branch CLK_PREV
IMUX_BUFG_I[29]branch CLK_PREV
IMUX_BUFG_I[30]branch CLK_PREV
IMUX_BUFG_I[31]branch CLK_PREV
MGT_BUF[0]mux
MGT_BUF[1]mux
MGT_BUF[2]mux
MGT_BUF[3]mux
MGT_BUF[4]mux
MGT_BUF[5]mux
MGT_BUF[6]mux
MGT_BUF[7]mux
MGT_BUF[8]mux
MGT_BUF[9]mux
OUT_CLKPADbel
HCLK_IO[0]regional LEAF
HCLK_IO[1]regional LEAF
HCLK_IO[2]regional LEAF
HCLK_IO[3]regional LEAF
HCLK_IO[4]regional LEAF
HCLK_IO[5]regional LEAF
HCLK_IO[6]regional LEAF
HCLK_IO[7]regional LEAF
HCLK_IO[8]regional LEAF
HCLK_IO[9]regional LEAF
RCLK_IO[0]regional LEAF
RCLK_IO[1]regional LEAF
RCLK_IO[2]regional LEAF
RCLK_IO[3]regional LEAF
IMUX_IDELAYCTRL_REFCLKmux
IMUX_BUFR[0]mux
IMUX_BUFR[1]mux
IOCLK[0]regional LEAF
IOCLK[1]regional LEAF
IOCLK[2]regional LEAF
IOCLK[3]regional LEAF
VRCLK[0]mux
VRCLK[1]mux
VRCLK_S[0]branch IO_N
VRCLK_S[1]branch IO_N
VRCLK_N[0]branch IO_S
VRCLK_N[1]branch IO_S
IMUX_IO_ICLK[0]mux
IMUX_IO_ICLK[1]mux
IMUX_IO_ICLK_OPTINV[0]mux
IMUX_IO_ICLK_OPTINV[1]mux
IMUX_ILOGIC_CLK[0]mux
IMUX_ILOGIC_CLK[1]mux
IMUX_ILOGIC_CLKB[0]mux
IMUX_ILOGIC_CLKB[1]mux
HCLK_CMT[0]regional LEAF
HCLK_CMT[1]regional LEAF
HCLK_CMT[2]regional LEAF
HCLK_CMT[3]regional LEAF
HCLK_CMT[4]regional LEAF
HCLK_CMT[5]regional LEAF
HCLK_CMT[6]regional LEAF
HCLK_CMT[7]regional LEAF
HCLK_CMT[8]regional LEAF
HCLK_CMT[9]regional LEAF
GIOB_CMT[0]regional LEAF
GIOB_CMT[1]regional LEAF
GIOB_CMT[2]regional LEAF
GIOB_CMT[3]regional LEAF
GIOB_CMT[4]regional LEAF
GIOB_CMT[5]regional LEAF
GIOB_CMT[6]regional LEAF
GIOB_CMT[7]regional LEAF
GIOB_CMT[8]regional LEAF
GIOB_CMT[9]regional LEAF
OUT_CMT[0]bel
OUT_CMT[1]bel
OUT_CMT[2]bel
OUT_CMT[3]bel
OUT_CMT[4]bel
OUT_CMT[5]bel
OUT_CMT[6]bel
OUT_CMT[7]bel
OUT_CMT[8]bel
OUT_CMT[9]bel
OUT_CMT[10]bel
OUT_CMT[11]bel
OUT_CMT[12]bel
OUT_CMT[13]bel
OUT_CMT[14]bel
OUT_CMT[15]bel
OUT_CMT[16]bel
OUT_CMT[17]bel
OUT_CMT[18]bel
OUT_CMT[19]bel
OUT_CMT[20]bel
OUT_CMT[21]bel
OUT_CMT[22]bel
OUT_CMT[23]bel
OUT_CMT[24]bel
OUT_CMT[25]bel
OUT_CMT[26]bel
OUT_CMT[27]bel
IMUX_DCM_CLKIN[0]mux
IMUX_DCM_CLKIN[1]mux
IMUX_DCM_CLKFB[0]mux
IMUX_DCM_CLKFB[1]mux
OMUX_DCM_SKEWCLKIN1[0]mux
OMUX_DCM_SKEWCLKIN1[1]mux
OMUX_DCM_SKEWCLKIN2[0]mux
OMUX_DCM_SKEWCLKIN2[1]mux
IMUX_PLL_CLKIN1mux
IMUX_PLL_CLKIN2mux
IMUX_PLL_CLKFBmux
TEST_PLL_CLKINbel
OMUX_PLL_SKEWCLKIN1mux
OMUX_PLL_SKEWCLKIN2mux
OUT_PLL_CLKOUTDCM[0]bel
OUT_PLL_CLKOUTDCM[1]bel
OUT_PLL_CLKOUTDCM[2]bel
OUT_PLL_CLKOUTDCM[3]bel
OUT_PLL_CLKOUTDCM[4]bel
OUT_PLL_CLKOUTDCM[5]bel
OUT_PLL_CLKFBDCMbel

Connectors — W

virtex5 wires
Wire PASS_W TERM_W INT_BUFS_W PPC_W
DBL_EE1[0] → DBL_EE0[0] ← DBL_WW0[3] → DBL_EE0[0] ← DBL_WW0[3]
DBL_EE1[1] → DBL_EE0[1] ← DBL_WW0[4] → DBL_EE0[1] ← DBL_WW0[4]
DBL_EE1[2] → DBL_EE0[2] ← DBL_WW0[5] → DBL_EE0[2] ← DBL_WW0[5]
DBL_EE1[3] → DBL_EE0[3] ← DBL_WW0[0] → DBL_EE0[3] ← DBL_WW0[0]
DBL_EE1[4] → DBL_EE0[4] ← DBL_WW0[1] → DBL_EE0[4] ← DBL_WW0[1]
DBL_EE1[5] → DBL_EE0[5] ← DBL_WW0[2] → DBL_EE0[5] ← DBL_WW0[2]
DBL_EE2[0] → DBL_EE1[0] ← DBL_WW1[3] → DBL_EE1[0] ← DBL_WW1[3]
DBL_EE2[1] → DBL_EE1[1] ← DBL_WW1[4] → DBL_EE1[1] ← DBL_WW1[4]
DBL_EE2[2] → DBL_EE1[2] ← DBL_WW1[5] → DBL_EE1[2] ← DBL_WW1[5]
DBL_EE2[3] → DBL_EE1[3] ← DBL_WW1[0] → DBL_EE1[3] ← DBL_WW1[0]
DBL_EE2[4] → DBL_EE1[4] ← DBL_WW1[1] → DBL_EE1[4] ← DBL_WW1[1]
DBL_EE2[5] → DBL_EE1[5] ← DBL_WW1[2] → DBL_EE1[5] ← DBL_WW1[2]
DBL_ES1[0] → DBL_ES0[0] ← DBL_WS0[0] → DBL_ES0[0] ← DBL_WS0[0]
DBL_ES1[1] → DBL_ES0[1] ← DBL_WS0[1] → DBL_ES0[1] ← DBL_WS0[1]
DBL_ES1[2] → DBL_ES0[2] ← DBL_WS0[2] → DBL_ES0[2] ← DBL_WS0[2]
DBL_EN1[0] → DBL_EN0[0] ← DBL_WN0[0] → DBL_EN0[0] ← DBL_WN0[0]
DBL_EN1[1] → DBL_EN0[1] ← DBL_WN0[1] → DBL_EN0[1] ← DBL_WN0[1]
DBL_EN1[2] → DBL_EN0[2] ← DBL_WN0[2] → DBL_EN0[2] ← DBL_WN0[2]
DBL_NE2[0] → DBL_NE1[0] ← DBL_NW1[0] → DBL_NE1[0] ← DBL_NW1[0]
DBL_NE2[1] → DBL_NE1[1] ← DBL_NW1[1] → DBL_NE1[1] ← DBL_NW1[1]
DBL_NE2[2] → DBL_NE1[2] ← DBL_NW1[2] → DBL_NE1[2] ← DBL_NW1[2]
DBL_SE2[0] → DBL_SE1[0] ← DBL_SW1[0] → DBL_SE1[0] ← DBL_SW1[0]
DBL_SE2[1] → DBL_SE1[1] ← DBL_SW1[1] → DBL_SE1[1] ← DBL_SW1[1]
DBL_SE2[2] → DBL_SE1[2] ← DBL_SW1[2] → DBL_SE1[2] ← DBL_SW1[2]
PENT_EE1[0] → PENT_EE0[0] ← PENT_WW0[3] → PENT_EE0[0] → PENT_EE0[0]
PENT_EE1[1] → PENT_EE0[1] ← PENT_WW0[4] → PENT_EE0[1] → PENT_EE0[1]
PENT_EE1[2] → PENT_EE0[2] ← PENT_WW0[5] → PENT_EE0[2] → PENT_EE0[2]
PENT_EE1[3] → PENT_EE0[3] ← PENT_WW0[0] → PENT_EE0[3] → PENT_EE0[3]
PENT_EE1[4] → PENT_EE0[4] ← PENT_WW0[1] → PENT_EE0[4] → PENT_EE0[4]
PENT_EE1[5] → PENT_EE0[5] ← PENT_WW0[2] → PENT_EE0[5] → PENT_EE0[5]
PENT_EE2[0] → PENT_EE1[0] ← PENT_WW1[3] → PENT_EE1[0] → PENT_EE1[0]
PENT_EE2[1] → PENT_EE1[1] ← PENT_WW1[4] → PENT_EE1[1] → PENT_EE1[1]
PENT_EE2[2] → PENT_EE1[2] ← PENT_WW1[5] → PENT_EE1[2] → PENT_EE1[2]
PENT_EE2[3] → PENT_EE1[3] ← PENT_WW1[0] → PENT_EE1[3] → PENT_EE1[3]
PENT_EE2[4] → PENT_EE1[4] ← PENT_WW1[1] → PENT_EE1[4] → PENT_EE1[4]
PENT_EE2[5] → PENT_EE1[5] ← PENT_WW1[2] → PENT_EE1[5] → PENT_EE1[5]
PENT_EE3[0] → PENT_EE2[0] ← PENT_WW2[3] → PENT_EE2[0] → PENT_EE2[0]
PENT_EE3[1] → PENT_EE2[1] ← PENT_WW2[4] → PENT_EE2[1] → PENT_EE2[1]
PENT_EE3[2] → PENT_EE2[2] ← PENT_WW2[5] → PENT_EE2[2] → PENT_EE2[2]
PENT_EE3[3] → PENT_EE2[3] ← PENT_WW2[0] → PENT_EE2[3] → PENT_EE2[3]
PENT_EE3[4] → PENT_EE2[4] ← PENT_WW2[1] → PENT_EE2[4] → PENT_EE2[4]
PENT_EE3[5] → PENT_EE2[5] ← PENT_WW2[2] → PENT_EE2[5] → PENT_EE2[5]
PENT_EE4[0] → PENT_EE3[0] ← PENT_WW3[3] → PENT_EE3[0] → PENT_EE3[0]
PENT_EE4[1] → PENT_EE3[1] ← PENT_WW3[4] → PENT_EE3[1] → PENT_EE3[1]
PENT_EE4[2] → PENT_EE3[2] ← PENT_WW3[5] → PENT_EE3[2] → PENT_EE3[2]
PENT_EE4[3] → PENT_EE3[3] ← PENT_WW3[0] → PENT_EE3[3] → PENT_EE3[3]
PENT_EE4[4] → PENT_EE3[4] ← PENT_WW3[1] → PENT_EE3[4] → PENT_EE3[4]
PENT_EE4[5] → PENT_EE3[5] ← PENT_WW3[2] → PENT_EE3[5] → PENT_EE3[5]
PENT_EE5[0] → PENT_EE4[0] ← PENT_WW4[3] → PENT_EE4[0] → PENT_EE4[0]
PENT_EE5[1] → PENT_EE4[1] ← PENT_WW4[4] → PENT_EE4[1] → PENT_EE4[1]
PENT_EE5[2] → PENT_EE4[2] ← PENT_WW4[5] → PENT_EE4[2] → PENT_EE4[2]
PENT_EE5[3] → PENT_EE4[3] ← PENT_WW4[0] → PENT_EE4[3] → PENT_EE4[3]
PENT_EE5[4] → PENT_EE4[4] ← PENT_WW4[1] → PENT_EE4[4] → PENT_EE4[4]
PENT_EE5[5] → PENT_EE4[5] ← PENT_WW4[2] → PENT_EE4[5] → PENT_EE4[5]
PENT_ES1[0] → PENT_ES0[0] ← PENT_WS0[0] → PENT_ES0[0] → PENT_ES0[0]
PENT_ES1[1] → PENT_ES0[1] ← PENT_WS0[1] → PENT_ES0[1] → PENT_ES0[1]
PENT_ES1[2] → PENT_ES0[2] ← PENT_WS0[2] → PENT_ES0[2] → PENT_ES0[2]
PENT_ES2[0] → PENT_ES1[0] ← PENT_WS1[0] → PENT_ES1[0] → PENT_ES1[0]
PENT_ES2[1] → PENT_ES1[1] ← PENT_WS1[1] → PENT_ES1[1] → PENT_ES1[1]
PENT_ES2[2] → PENT_ES1[2] ← PENT_WS1[2] → PENT_ES1[2] → PENT_ES1[2]
PENT_ES3[0] → PENT_ES2[0] ← PENT_WS2[0] → PENT_ES2[0] → PENT_ES2[0]
PENT_ES3[1] → PENT_ES2[1] ← PENT_WS2[1] → PENT_ES2[1] → PENT_ES2[1]
PENT_ES3[2] → PENT_ES2[2] ← PENT_WS2[2] → PENT_ES2[2] → PENT_ES2[2]
PENT_EN1[0] → PENT_EN0[0] ← PENT_WN0[0] → PENT_EN0[0] → PENT_EN0[0]
PENT_EN1[1] → PENT_EN0[1] ← PENT_WN0[1] → PENT_EN0[1] → PENT_EN0[1]
PENT_EN1[2] → PENT_EN0[2] ← PENT_WN0[2] → PENT_EN0[2] → PENT_EN0[2]
PENT_EN2[0] → PENT_EN1[0] ← PENT_WN1[0] → PENT_EN1[0] → PENT_EN1[0]
PENT_EN2[1] → PENT_EN1[1] ← PENT_WN1[1] → PENT_EN1[1] → PENT_EN1[1]
PENT_EN2[2] → PENT_EN1[2] ← PENT_WN1[2] → PENT_EN1[2] → PENT_EN1[2]
PENT_EN3[0] → PENT_EN2[0] ← PENT_WN2[0] → PENT_EN2[0] → PENT_EN2[0]
PENT_EN3[1] → PENT_EN2[1] ← PENT_WN2[1] → PENT_EN2[1] → PENT_EN2[1]
PENT_EN3[2] → PENT_EN2[2] ← PENT_WN2[2] → PENT_EN2[2] → PENT_EN2[2]
PENT_SE4[0] → PENT_SE3[0] ← PENT_SW3[0] → PENT_SE3[0] → PENT_SE3[0]
PENT_SE4[1] → PENT_SE3[1] ← PENT_SW3[1] → PENT_SE3[1] → PENT_SE3[1]
PENT_SE4[2] → PENT_SE3[2] ← PENT_SW3[2] → PENT_SE3[2] → PENT_SE3[2]
PENT_SE5[0] → PENT_SE4[0] ← PENT_SW4[0] → PENT_SE4[0] → PENT_SE4[0]
PENT_SE5[1] → PENT_SE4[1] ← PENT_SW4[1] → PENT_SE4[1] → PENT_SE4[1]
PENT_SE5[2] → PENT_SE4[2] ← PENT_SW4[2] → PENT_SE4[2] → PENT_SE4[2]
PENT_NE4[0] → PENT_NE3[0] ← PENT_NW3[0] → PENT_NE3[0] → PENT_NE3[0]
PENT_NE4[1] → PENT_NE3[1] ← PENT_NW3[1] → PENT_NE3[1] → PENT_NE3[1]
PENT_NE4[2] → PENT_NE3[2] ← PENT_NW3[2] → PENT_NE3[2] → PENT_NE3[2]
PENT_NE5[0] → PENT_NE4[0] ← PENT_NW4[0] → PENT_NE4[0] → PENT_NE4[0]
PENT_NE5[1] → PENT_NE4[1] ← PENT_NW4[1] → PENT_NE4[1] → PENT_NE4[1]
PENT_NE5[2] → PENT_NE4[2] ← PENT_NW4[2] → PENT_NE4[2] → PENT_NE4[2]
LH[0] → LH[1] ← LH[17] → LH[1] → LH[1]
LH[1] → LH[2] ← LH[16] → LH[2] → LH[2]
LH[2] → LH[3] ← LH[15] → LH[3] → LH[3]
LH[3] → LH[4] ← LH[14] → LH[4] → LH[4]
LH[4] → LH[5] ← LH[13] → LH[5] → LH[5]
LH[5] → LH[6] ← LH[12] → LH[6] → LH[6]
LH[6] → LH[7] ← LH[11] → LH[7] → LH[7]
LH[7] → LH[8] ← LH[10] → LH[8] → LH[8]
LH[8] → LH[9] ← LH[9] → LH[9] → LH[9]

Connectors — E

virtex5 wires
Wire PASS_E TERM_E TERM_E_HOLE INT_BUFS_E PPC_E
DBL_WW1[0] → DBL_WW0[0] ← DBL_EE0[3] - → DBL_WW0[0] ← DBL_EE0[3]
DBL_WW1[1] → DBL_WW0[1] ← DBL_EE0[4] - → DBL_WW0[1] ← DBL_EE0[4]
DBL_WW1[2] → DBL_WW0[2] ← DBL_EE0[5] - → DBL_WW0[2] ← DBL_EE0[5]
DBL_WW1[3] → DBL_WW0[3] ← DBL_EE0[0] - → DBL_WW0[3] ← DBL_EE0[0]
DBL_WW1[4] → DBL_WW0[4] ← DBL_EE0[1] - → DBL_WW0[4] ← DBL_EE0[1]
DBL_WW1[5] → DBL_WW0[5] ← DBL_EE0[2] - → DBL_WW0[5] ← DBL_EE0[2]
DBL_WW2[0] → DBL_WW1[0] ← DBL_EE1[3] - → DBL_WW1[0] ← DBL_EE1[3]
DBL_WW2[1] → DBL_WW1[1] ← DBL_EE1[4] - → DBL_WW1[1] ← DBL_EE1[4]
DBL_WW2[2] → DBL_WW1[2] ← DBL_EE1[5] - → DBL_WW1[2] ← DBL_EE1[5]
DBL_WW2[3] → DBL_WW1[3] ← DBL_EE1[0] - → DBL_WW1[3] ← DBL_EE1[0]
DBL_WW2[4] → DBL_WW1[4] ← DBL_EE1[1] - → DBL_WW1[4] ← DBL_EE1[1]
DBL_WW2[5] → DBL_WW1[5] ← DBL_EE1[2] - → DBL_WW1[5] ← DBL_EE1[2]
DBL_WS1[0] → DBL_WS0[0] ← DBL_ES0[0] - → DBL_WS0[0] ← DBL_ES0[0]
DBL_WS1[1] → DBL_WS0[1] ← DBL_ES0[1] - → DBL_WS0[1] ← DBL_ES0[1]
DBL_WS1[2] → DBL_WS0[2] ← DBL_ES0[2] - → DBL_WS0[2] ← DBL_ES0[2]
DBL_WN1[0] → DBL_WN0[0] ← DBL_EN0[0] - → DBL_WN0[0] ← DBL_EN0[0]
DBL_WN1[1] → DBL_WN0[1] ← DBL_EN0[1] - → DBL_WN0[1] ← DBL_EN0[1]
DBL_WN1[2] → DBL_WN0[2] ← DBL_EN0[2] - → DBL_WN0[2] ← DBL_EN0[2]
DBL_NW2[0] → DBL_NW1[0] ← DBL_NE1[0] - → DBL_NW1[0] ← DBL_NE1[0]
DBL_NW2[1] → DBL_NW1[1] ← DBL_NE1[1] - → DBL_NW1[1] ← DBL_NE1[1]
DBL_NW2[2] → DBL_NW1[2] ← DBL_NE1[2] - → DBL_NW1[2] ← DBL_NE1[2]
DBL_SW2[0] → DBL_SW1[0] ← DBL_SE1[0] - → DBL_SW1[0] ← DBL_SE1[0]
DBL_SW2[1] → DBL_SW1[1] ← DBL_SE1[1] - → DBL_SW1[1] ← DBL_SE1[1]
DBL_SW2[2] → DBL_SW1[2] ← DBL_SE1[2] - → DBL_SW1[2] ← DBL_SE1[2]
PENT_WW1[0] → PENT_WW0[0] ← PENT_EE0[3] - → PENT_WW0[0] → PENT_WW0[0]
PENT_WW1[1] → PENT_WW0[1] ← PENT_EE0[4] - → PENT_WW0[1] → PENT_WW0[1]
PENT_WW1[2] → PENT_WW0[2] ← PENT_EE0[5] - → PENT_WW0[2] → PENT_WW0[2]
PENT_WW1[3] → PENT_WW0[3] ← PENT_EE0[0] - → PENT_WW0[3] → PENT_WW0[3]
PENT_WW1[4] → PENT_WW0[4] ← PENT_EE0[1] - → PENT_WW0[4] → PENT_WW0[4]
PENT_WW1[5] → PENT_WW0[5] ← PENT_EE0[2] - → PENT_WW0[5] → PENT_WW0[5]
PENT_WW2[0] → PENT_WW1[0] ← PENT_EE1[3] - → PENT_WW1[0] → PENT_WW1[0]
PENT_WW2[1] → PENT_WW1[1] ← PENT_EE1[4] - → PENT_WW1[1] → PENT_WW1[1]
PENT_WW2[2] → PENT_WW1[2] ← PENT_EE1[5] - → PENT_WW1[2] → PENT_WW1[2]
PENT_WW2[3] → PENT_WW1[3] ← PENT_EE1[0] - → PENT_WW1[3] → PENT_WW1[3]
PENT_WW2[4] → PENT_WW1[4] ← PENT_EE1[1] - → PENT_WW1[4] → PENT_WW1[4]
PENT_WW2[5] → PENT_WW1[5] ← PENT_EE1[2] - → PENT_WW1[5] → PENT_WW1[5]
PENT_WW3[0] → PENT_WW2[0] ← PENT_EE2[3] - → PENT_WW2[0] → PENT_WW2[0]
PENT_WW3[1] → PENT_WW2[1] ← PENT_EE2[4] - → PENT_WW2[1] → PENT_WW2[1]
PENT_WW3[2] → PENT_WW2[2] ← PENT_EE2[5] - → PENT_WW2[2] → PENT_WW2[2]
PENT_WW3[3] → PENT_WW2[3] ← PENT_EE2[0] - → PENT_WW2[3] → PENT_WW2[3]
PENT_WW3[4] → PENT_WW2[4] ← PENT_EE2[1] - → PENT_WW2[4] → PENT_WW2[4]
PENT_WW3[5] → PENT_WW2[5] ← PENT_EE2[2] - → PENT_WW2[5] → PENT_WW2[5]
PENT_WW4[0] → PENT_WW3[0] ← PENT_EE3[3] - → PENT_WW3[0] → PENT_WW3[0]
PENT_WW4[1] → PENT_WW3[1] ← PENT_EE3[4] - → PENT_WW3[1] → PENT_WW3[1]
PENT_WW4[2] → PENT_WW3[2] ← PENT_EE3[5] - → PENT_WW3[2] → PENT_WW3[2]
PENT_WW4[3] → PENT_WW3[3] ← PENT_EE3[0] - → PENT_WW3[3] → PENT_WW3[3]
PENT_WW4[4] → PENT_WW3[4] ← PENT_EE3[1] - → PENT_WW3[4] → PENT_WW3[4]
PENT_WW4[5] → PENT_WW3[5] ← PENT_EE3[2] - → PENT_WW3[5] → PENT_WW3[5]
PENT_WW5[0] → PENT_WW4[0] ← PENT_EE4[3] - → PENT_WW4[0] → PENT_WW4[0]
PENT_WW5[1] → PENT_WW4[1] ← PENT_EE4[4] - → PENT_WW4[1] → PENT_WW4[1]
PENT_WW5[2] → PENT_WW4[2] ← PENT_EE4[5] - → PENT_WW4[2] → PENT_WW4[2]
PENT_WW5[3] → PENT_WW4[3] ← PENT_EE4[0] - → PENT_WW4[3] → PENT_WW4[3]
PENT_WW5[4] → PENT_WW4[4] ← PENT_EE4[1] - → PENT_WW4[4] → PENT_WW4[4]
PENT_WW5[5] → PENT_WW4[5] ← PENT_EE4[2] - → PENT_WW4[5] → PENT_WW4[5]
PENT_WS1[0] → PENT_WS0[0] ← PENT_ES0[0] - → PENT_WS0[0] → PENT_WS0[0]
PENT_WS1[1] → PENT_WS0[1] ← PENT_ES0[1] - → PENT_WS0[1] → PENT_WS0[1]
PENT_WS1[2] → PENT_WS0[2] ← PENT_ES0[2] - → PENT_WS0[2] → PENT_WS0[2]
PENT_WS2[0] → PENT_WS1[0] ← PENT_ES1[0] - → PENT_WS1[0] → PENT_WS1[0]
PENT_WS2[1] → PENT_WS1[1] ← PENT_ES1[1] - → PENT_WS1[1] → PENT_WS1[1]
PENT_WS2[2] → PENT_WS1[2] ← PENT_ES1[2] - → PENT_WS1[2] → PENT_WS1[2]
PENT_WS3[0] → PENT_WS2[0] ← PENT_ES2[0] - → PENT_WS2[0] → PENT_WS2[0]
PENT_WS3[1] → PENT_WS2[1] ← PENT_ES2[1] - → PENT_WS2[1] → PENT_WS2[1]
PENT_WS3[2] → PENT_WS2[2] ← PENT_ES2[2] - → PENT_WS2[2] → PENT_WS2[2]
PENT_WN1[0] → PENT_WN0[0] ← PENT_EN0[0] - → PENT_WN0[0] → PENT_WN0[0]
PENT_WN1[1] → PENT_WN0[1] ← PENT_EN0[1] - → PENT_WN0[1] → PENT_WN0[1]
PENT_WN1[2] → PENT_WN0[2] ← PENT_EN0[2] - → PENT_WN0[2] → PENT_WN0[2]
PENT_WN2[0] → PENT_WN1[0] ← PENT_EN1[0] - → PENT_WN1[0] → PENT_WN1[0]
PENT_WN2[1] → PENT_WN1[1] ← PENT_EN1[1] - → PENT_WN1[1] → PENT_WN1[1]
PENT_WN2[2] → PENT_WN1[2] ← PENT_EN1[2] - → PENT_WN1[2] → PENT_WN1[2]
PENT_WN3[0] → PENT_WN2[0] ← PENT_EN2[0] - → PENT_WN2[0] → PENT_WN2[0]
PENT_WN3[1] → PENT_WN2[1] ← PENT_EN2[1] - → PENT_WN2[1] → PENT_WN2[1]
PENT_WN3[2] → PENT_WN2[2] ← PENT_EN2[2] - → PENT_WN2[2] → PENT_WN2[2]
PENT_SW4[0] → PENT_SW3[0] ← PENT_SE3[0] - → PENT_SW3[0] → PENT_SW3[0]
PENT_SW4[1] → PENT_SW3[1] ← PENT_SE3[1] - → PENT_SW3[1] → PENT_SW3[1]
PENT_SW4[2] → PENT_SW3[2] ← PENT_SE3[2] - → PENT_SW3[2] → PENT_SW3[2]
PENT_SW5[0] → PENT_SW4[0] ← PENT_SE4[0] - → PENT_SW4[0] → PENT_SW4[0]
PENT_SW5[1] → PENT_SW4[1] ← PENT_SE4[1] - → PENT_SW4[1] → PENT_SW4[1]
PENT_SW5[2] → PENT_SW4[2] ← PENT_SE4[2] - → PENT_SW4[2] → PENT_SW4[2]
PENT_NW4[0] → PENT_NW3[0] ← PENT_NE3[0] - → PENT_NW3[0] → PENT_NW3[0]
PENT_NW4[1] → PENT_NW3[1] ← PENT_NE3[1] - → PENT_NW3[1] → PENT_NW3[1]
PENT_NW4[2] → PENT_NW3[2] ← PENT_NE3[2] - → PENT_NW3[2] → PENT_NW3[2]
PENT_NW5[0] → PENT_NW4[0] ← PENT_NE4[0] - → PENT_NW4[0] → PENT_NW4[0]
PENT_NW5[1] → PENT_NW4[1] ← PENT_NE4[1] - → PENT_NW4[1] → PENT_NW4[1]
PENT_NW5[2] → PENT_NW4[2] ← PENT_NE4[2] - → PENT_NW4[2] → PENT_NW4[2]
LH[10] → LH[9] ← LH[9] [BLACKHOLE] → LH[9] → LH[9]
LH[11] → LH[10] ← LH[8] [BLACKHOLE] → LH[10] → LH[10]
LH[12] → LH[11] ← LH[7] [BLACKHOLE] → LH[11] → LH[11]
LH[13] → LH[12] ← LH[6] [BLACKHOLE] → LH[12] → LH[12]
LH[14] → LH[13] ← LH[5] [BLACKHOLE] → LH[13] → LH[13]
LH[15] → LH[14] ← LH[4] [BLACKHOLE] → LH[14] → LH[14]
LH[16] → LH[15] ← LH[3] [BLACKHOLE] → LH[15] → LH[15]
LH[17] → LH[16] ← LH[2] [BLACKHOLE] → LH[16] → LH[16]
LH[18] → LH[17] ← LH[1] [BLACKHOLE] → LH[17] → LH[17]

Connectors — S

virtex5 wires
Wire PASS_S TERM_S_HOLE TERM_S_PPC
DBL_WW0[0] → DBL_WW0_S0 - ← DBL_NN0_N5
DBL_WN2[0] → DBL_WN1[0] - ← DBL_WS1[2]
DBL_WN2[1] → DBL_WN1[1] - ← DBL_WS1[1]
DBL_WN2[2] → DBL_WN1[2] - ← DBL_WS1[0]
DBL_EE0[3] → DBL_EE0_S3 - ← DBL_WW0_N5
DBL_EN2[0] → DBL_EN1[0] - ← DBL_ES1[2]
DBL_EN2[1] → DBL_EN1[1] - ← DBL_ES1[1]
DBL_EN2[2] → DBL_EN1[2] - ← DBL_ES1[0]
DBL_NN0[0] → DBL_NN0_S0 - ← DBL_SS0_N2
DBL_NN1[0] → DBL_NN0[0] - ← DBL_SS0[5]
DBL_NN1[1] → DBL_NN0[1] - ← DBL_SS0[4]
DBL_NN1[2] → DBL_NN0[2] - ← DBL_SS0[3]
DBL_NN1[3] → DBL_NN0[3] - ← DBL_SS0[2]
DBL_NN1[4] → DBL_NN0[4] - ← DBL_SS0[1]
DBL_NN1[5] → DBL_NN0[5] - ← DBL_SS0[0]
DBL_NN2[0] → DBL_NN1[0] - ← DBL_SS1[5]
DBL_NN2[1] → DBL_NN1[1] - ← DBL_SS1[4]
DBL_NN2[2] → DBL_NN1[2] - ← DBL_SS1[3]
DBL_NN2[3] → DBL_NN1[3] - ← DBL_SS1[2]
DBL_NN2[4] → DBL_NN1[4] - ← DBL_SS1[1]
DBL_NN2[5] → DBL_NN1[5] - ← DBL_SS1[0]
DBL_NW1[0] → DBL_NW0[0] - ← DBL_SW0[2]
DBL_NW1[1] → DBL_NW0[1] - ← DBL_SW0[1]
DBL_NW1[2] → DBL_NW0[2] - ← DBL_SW0[0]
DBL_NW2_N2 → DBL_NW2[2] - ← DBL_WN2[0]
DBL_NE1[0] → DBL_NE0[0] - ← DBL_SE0[2]
DBL_NE1[1] → DBL_NE0[1] - ← DBL_SE0[1]
DBL_NE1[2] → DBL_NE0[2] - ← DBL_SE0[0]
DBL_NE1_N2 → DBL_NE1_BUF2 - ← DBL_WS1_BUF0
PENT_WW0[0] → PENT_WW0_S0 - ← PENT_NN0_N5
PENT_WN4[0] → PENT_WN3[0] - ← PENT_WS3[2]
PENT_WN4[1] → PENT_WN3[1] - ← PENT_WS3[1]
PENT_WN4[2] → PENT_WN3[2] - ← PENT_WS3[0]
PENT_WN5[0] → PENT_WN4[0] - ← PENT_WS4[2]
PENT_WN5[1] → PENT_WN4[1] - ← PENT_WS4[1]
PENT_WN5[2] → PENT_WN4[2] - ← PENT_WS4[0]
PENT_EN4[0] → PENT_EN3[0] - ← PENT_ES3[2]
PENT_EN4[1] → PENT_EN3[1] - ← PENT_ES3[1]
PENT_EN4[2] → PENT_EN3[2] - ← PENT_ES3[0]
PENT_EN5[0] → PENT_EN4[0] - ← PENT_ES4[2]
PENT_EN5[1] → PENT_EN4[1] - ← PENT_ES4[1]
PENT_EN5[2] → PENT_EN4[2] - ← PENT_ES4[0]
PENT_NN1[0] → PENT_NN0[0] - ← PENT_SS0[5]
PENT_NN1[1] → PENT_NN0[1] - ← PENT_SS0[4]
PENT_NN1[2] → PENT_NN0[2] - ← PENT_SS0[3]
PENT_NN1[3] → PENT_NN0[3] - ← PENT_SS0[2]
PENT_NN1[4] → PENT_NN0[4] - ← PENT_SS0[1]
PENT_NN1[5] → PENT_NN0[5] - ← PENT_SS0[0]
PENT_NN2[0] → PENT_NN1[0] - ← PENT_SS1[5]
PENT_NN2[1] → PENT_NN1[1] - ← PENT_SS1[4]
PENT_NN2[2] → PENT_NN1[2] - ← PENT_SS1[3]
PENT_NN2[3] → PENT_NN1[3] - ← PENT_SS1[2]
PENT_NN2[4] → PENT_NN1[4] - ← PENT_SS1[1]
PENT_NN2[5] → PENT_NN1[5] - ← PENT_SS1[0]
PENT_NN3[0] → PENT_NN2[0] - ← PENT_SS2[5]
PENT_NN3[1] → PENT_NN2[1] - ← PENT_SS2[4]
PENT_NN3[2] → PENT_NN2[2] - ← PENT_SS2[3]
PENT_NN3[3] → PENT_NN2[3] - ← PENT_SS2[2]
PENT_NN3[4] → PENT_NN2[4] - ← PENT_SS2[1]
PENT_NN3[5] → PENT_NN2[5] - ← PENT_SS2[0]
PENT_NN4[0] → PENT_NN3[0] - ← PENT_SS3[5]
PENT_NN4[1] → PENT_NN3[1] - ← PENT_SS3[4]
PENT_NN4[2] → PENT_NN3[2] - ← PENT_SS3[3]
PENT_NN4[3] → PENT_NN3[3] - ← PENT_SS3[2]
PENT_NN4[4] → PENT_NN3[4] - ← PENT_SS3[1]
PENT_NN4[5] → PENT_NN3[5] - ← PENT_SS3[0]
PENT_NN5[0] → PENT_NN4[0] - ← PENT_SS4[5]
PENT_NN5[1] → PENT_NN4[1] - ← PENT_SS4[4]
PENT_NN5[2] → PENT_NN4[2] - ← PENT_SS4[3]
PENT_NN5[3] → PENT_NN4[3] - ← PENT_SS4[2]
PENT_NN5[4] → PENT_NN4[4] - ← PENT_SS4[1]
PENT_NN5[5] → PENT_NN4[5] - ← PENT_SS4[0]
PENT_NW1[0] → PENT_NW0[0] - ← PENT_SW0[2]
PENT_NW1[1] → PENT_NW0[1] - ← PENT_SW0[1]
PENT_NW1[2] → PENT_NW0[2] - ← PENT_SW0[0]
PENT_NW2[0] → PENT_NW1[0] - ← PENT_SW1[2]
PENT_NW2[1] → PENT_NW1[1] - ← PENT_SW1[1]
PENT_NW2[2] → PENT_NW1[2] - ← PENT_SW1[0]
PENT_NW3[0] → PENT_NW2[0] - ← PENT_SW2[2]
PENT_NW3[1] → PENT_NW2[1] - ← PENT_SW2[1]
PENT_NW3[2] → PENT_NW2[2] - ← PENT_SW2[0]
PENT_NW5_N2 → PENT_NW5[2] - ← PENT_WN5[0]
PENT_NE1[0] → PENT_NE0[0] - ← PENT_SE0[2]
PENT_NE1[1] → PENT_NE0[1] - ← PENT_SE0[1]
PENT_NE1[2] → PENT_NE0[2] - ← PENT_SE0[0]
PENT_NE2[0] → PENT_NE1[0] - ← PENT_SE1[2]
PENT_NE2[1] → PENT_NE1[1] - ← PENT_SE1[1]
PENT_NE2[2] → PENT_NE1[2] - ← PENT_SE1[0]
PENT_NE3[0] → PENT_NE2[0] - ← PENT_SE2[2]
PENT_NE3[1] → PENT_NE2[1] - ← PENT_SE2[1]
PENT_NE3[2] → PENT_NE2[2] - ← PENT_SE2[0]
PENT_NE3_N2 → PENT_NE3_BUF2 - ← PENT_WS3_BUF0
LV[10] → LV[9] [BLACKHOLE] ← LV[9]
LV[11] → LV[10] [BLACKHOLE] ← LV[8]
LV[12] → LV[11] [BLACKHOLE] ← LV[7]
LV[13] → LV[12] [BLACKHOLE] ← LV[6]
LV[14] → LV[13] [BLACKHOLE] ← LV[5]
LV[15] → LV[14] [BLACKHOLE] ← LV[4]
LV[16] → LV[15] [BLACKHOLE] ← LV[3]
LV[17] → LV[16] [BLACKHOLE] ← LV[2]
LV[18] → LV[17] [BLACKHOLE] ← LV[1]
IMUX_CTRL_BOUNCE_N3 → IMUX_CTRL_BOUNCE[3] - ← IMUX_CTRL_BOUNCE[0]
IMUX_BYP_BOUNCE_N3 → IMUX_BYP_BOUNCE[3] - -
IMUX_BYP_BOUNCE_N7 → IMUX_BYP_BOUNCE[7] - ← IMUX_BYP_BOUNCE[0]
IMUX_FAN_BOUNCE_N7 → IMUX_FAN_BOUNCE[7] - ← IMUX_FAN_BOUNCE[0]
OUT_N15_DBL → OUT[15] - -
OUT_N17_DBL → OUT[17] - -
OUT_N15_PENT → OUT[15] - ← OUT[18]
OUT_N17_PENT → OUT[17] - -

Connectors — N

virtex5 wires
Wire PASS_N PASS_NHOLE_N TERM_N_HOLE TERM_N_PPC
DBL_WW0[5] → DBL_WW0_N5 → DBL_WW0_N5 - ← DBL_EE0_S3
DBL_WS2[0] → DBL_WS1[0] → DBL_WS1[0] - ← DBL_WN1[2]
DBL_WS2[1] → DBL_WS1[1] → DBL_WS1[1] - ← DBL_WN1[1]
DBL_WS2[2] → DBL_WS1[2] → DBL_WS1[2] - ← DBL_WN1[0]
DBL_WS1_S0 → DBL_WS1_BUF0 → DBL_WS1_BUF0 - ← DBL_NE1_BUF2
DBL_WN2_S0 → DBL_WN2[0] → DBL_WN2[0] - ← DBL_NW2[2]
DBL_ES2[0] → DBL_ES1[0] → DBL_ES1[0] - ← DBL_EN1[2]
DBL_ES2[1] → DBL_ES1[1] → DBL_ES1[1] - ← DBL_EN1[1]
DBL_ES2[2] → DBL_ES1[2] → DBL_ES1[2] - ← DBL_EN1[0]
DBL_NN0[5] → DBL_NN0_N5 → DBL_NN0_N5 - ← DBL_WW0_S0
DBL_SS0[2] → DBL_SS0_N2 → DBL_SS0_N2 - ← DBL_NN0_S0
DBL_SS1[0] → DBL_SS0[0] → DBL_SS0[0] - ← DBL_NN0[5]
DBL_SS1[1] → DBL_SS0[1] → DBL_SS0[1] - ← DBL_NN0[4]
DBL_SS1[2] → DBL_SS0[2] → DBL_SS0[2] - ← DBL_NN0[3]
DBL_SS1[3] → DBL_SS0[3] → DBL_SS0[3] - ← DBL_NN0[2]
DBL_SS1[4] → DBL_SS0[4] → DBL_SS0[4] - ← DBL_NN0[1]
DBL_SS1[5] → DBL_SS0[5] → DBL_SS0[5] - ← DBL_NN0[0]
DBL_SS2[0] → DBL_SS1[0] → DBL_SS1[0] - ← DBL_NN1[5]
DBL_SS2[1] → DBL_SS1[1] → DBL_SS1[1] - ← DBL_NN1[4]
DBL_SS2[2] → DBL_SS1[2] → DBL_SS1[2] - ← DBL_NN1[3]
DBL_SS2[3] → DBL_SS1[3] → DBL_SS1[3] - ← DBL_NN1[2]
DBL_SS2[4] → DBL_SS1[4] → DBL_SS1[4] - ← DBL_NN1[1]
DBL_SS2[5] → DBL_SS1[5] → DBL_SS1[5] - ← DBL_NN1[0]
DBL_SW1[0] → DBL_SW0[0] → DBL_SW0[0] - ← DBL_NW0[2]
DBL_SW1[1] → DBL_SW0[1] → DBL_SW0[1] - ← DBL_NW0[1]
DBL_SW1[2] → DBL_SW0[2] → DBL_SW0[2] - ← DBL_NW0[0]
DBL_SE1[0] → DBL_SE0[0] → DBL_SE0[0] - ← DBL_NE0[2]
DBL_SE1[1] → DBL_SE0[1] → DBL_SE0[1] - ← DBL_NE0[1]
DBL_SE1[2] → DBL_SE0[2] → DBL_SE0[2] - ← DBL_NE0[0]
PENT_WS4[0] → PENT_WS3[0] → PENT_WS3[0] - ← PENT_WN3[2]
PENT_WS4[1] → PENT_WS3[1] → PENT_WS3[1] - ← PENT_WN3[1]
PENT_WS4[2] → PENT_WS3[2] → PENT_WS3[2] - ← PENT_WN3[0]
PENT_WS5[0] → PENT_WS4[0] → PENT_WS4[0] - ← PENT_WN4[2]
PENT_WS5[1] → PENT_WS4[1] → PENT_WS4[1] - ← PENT_WN4[1]
PENT_WS5[2] → PENT_WS4[2] → PENT_WS4[2] - ← PENT_WN4[0]
PENT_WS3_S0 → PENT_WS3_BUF0 → PENT_WS3_BUF0 - ← PENT_NE3_BUF2
PENT_WN5_S0 → PENT_WN5[0] → PENT_WN5[0] - ← PENT_NW5[2]
PENT_ES4[0] → PENT_ES3[0] → PENT_ES3[0] - ← PENT_EN3[2]
PENT_ES4[1] → PENT_ES3[1] → PENT_ES3[1] - ← PENT_EN3[1]
PENT_ES4[2] → PENT_ES3[2] → PENT_ES3[2] - ← PENT_EN3[0]
PENT_ES5[0] → PENT_ES4[0] → PENT_ES4[0] - ← PENT_EN4[2]
PENT_ES5[1] → PENT_ES4[1] → PENT_ES4[1] - ← PENT_EN4[1]
PENT_ES5[2] → PENT_ES4[2] → PENT_ES4[2] - ← PENT_EN4[0]
PENT_SS1[0] → PENT_SS0[0] → PENT_SS0[0] - ← PENT_NN0[5]
PENT_SS1[1] → PENT_SS0[1] → PENT_SS0[1] - ← PENT_NN0[4]
PENT_SS1[2] → PENT_SS0[2] → PENT_SS0[2] - ← PENT_NN0[3]
PENT_SS1[3] → PENT_SS0[3] → PENT_SS0[3] - ← PENT_NN0[2]
PENT_SS1[4] → PENT_SS0[4] → PENT_SS0[4] - ← PENT_NN0[1]
PENT_SS1[5] → PENT_SS0[5] → PENT_SS0[5] - ← PENT_NN0[0]
PENT_SS2[0] → PENT_SS1[0] → PENT_SS1[0] - ← PENT_NN1[5]
PENT_SS2[1] → PENT_SS1[1] → PENT_SS1[1] - ← PENT_NN1[4]
PENT_SS2[2] → PENT_SS1[2] → PENT_SS1[2] - ← PENT_NN1[3]
PENT_SS2[3] → PENT_SS1[3] → PENT_SS1[3] - ← PENT_NN1[2]
PENT_SS2[4] → PENT_SS1[4] → PENT_SS1[4] - ← PENT_NN1[1]
PENT_SS2[5] → PENT_SS1[5] → PENT_SS1[5] - ← PENT_NN1[0]
PENT_SS3[0] → PENT_SS2[0] → PENT_SS2[0] - ← PENT_NN2[5]
PENT_SS3[1] → PENT_SS2[1] → PENT_SS2[1] - ← PENT_NN2[4]
PENT_SS3[2] → PENT_SS2[2] → PENT_SS2[2] - ← PENT_NN2[3]
PENT_SS3[3] → PENT_SS2[3] → PENT_SS2[3] - ← PENT_NN2[2]
PENT_SS3[4] → PENT_SS2[4] → PENT_SS2[4] - ← PENT_NN2[1]
PENT_SS3[5] → PENT_SS2[5] → PENT_SS2[5] - ← PENT_NN2[0]
PENT_SS4[0] → PENT_SS3[0] → PENT_SS3[0] - ← PENT_NN3[5]
PENT_SS4[1] → PENT_SS3[1] → PENT_SS3[1] - ← PENT_NN3[4]
PENT_SS4[2] → PENT_SS3[2] → PENT_SS3[2] - ← PENT_NN3[3]
PENT_SS4[3] → PENT_SS3[3] → PENT_SS3[3] - ← PENT_NN3[2]
PENT_SS4[4] → PENT_SS3[4] → PENT_SS3[4] - ← PENT_NN3[1]
PENT_SS4[5] → PENT_SS3[5] → PENT_SS3[5] - ← PENT_NN3[0]
PENT_SS5[0] → PENT_SS4[0] → PENT_SS4[0] - ← PENT_NN4[5]
PENT_SS5[1] → PENT_SS4[1] → PENT_SS4[1] - ← PENT_NN4[4]
PENT_SS5[2] → PENT_SS4[2] → PENT_SS4[2] - ← PENT_NN4[3]
PENT_SS5[3] → PENT_SS4[3] → PENT_SS4[3] - ← PENT_NN4[2]
PENT_SS5[4] → PENT_SS4[4] → PENT_SS4[4] - ← PENT_NN4[1]
PENT_SS5[5] → PENT_SS4[5] → PENT_SS4[5] - ← PENT_NN4[0]
PENT_SW1[0] → PENT_SW0[0] → PENT_SW0[0] - ← PENT_NW0[2]
PENT_SW1[1] → PENT_SW0[1] → PENT_SW0[1] - ← PENT_NW0[1]
PENT_SW1[2] → PENT_SW0[2] → PENT_SW0[2] - ← PENT_NW0[0]
PENT_SW2[0] → PENT_SW1[0] → PENT_SW1[0] - ← PENT_NW1[2]
PENT_SW2[1] → PENT_SW1[1] → PENT_SW1[1] - ← PENT_NW1[1]
PENT_SW2[2] → PENT_SW1[2] → PENT_SW1[2] - ← PENT_NW1[0]
PENT_SW3[0] → PENT_SW2[0] → PENT_SW2[0] - ← PENT_NW2[2]
PENT_SW3[1] → PENT_SW2[1] → PENT_SW2[1] - ← PENT_NW2[1]
PENT_SW3[2] → PENT_SW2[2] → PENT_SW2[2] - ← PENT_NW2[0]
PENT_SE1[0] → PENT_SE0[0] → PENT_SE0[0] - ← PENT_NE0[2]
PENT_SE1[1] → PENT_SE0[1] → PENT_SE0[1] - ← PENT_NE0[1]
PENT_SE1[2] → PENT_SE0[2] → PENT_SE0[2] - ← PENT_NE0[0]
PENT_SE2[0] → PENT_SE1[0] → PENT_SE1[0] - ← PENT_NE1[2]
PENT_SE2[1] → PENT_SE1[1] → PENT_SE1[1] - ← PENT_NE1[1]
PENT_SE2[2] → PENT_SE1[2] → PENT_SE1[2] - ← PENT_NE1[0]
PENT_SE3[0] → PENT_SE2[0] → PENT_SE2[0] - ← PENT_NE2[2]
PENT_SE3[1] → PENT_SE2[1] → PENT_SE2[1] - ← PENT_NE2[1]
PENT_SE3[2] → PENT_SE2[2] → PENT_SE2[2] - ← PENT_NE2[0]
PENT_NN0[5] → PENT_NN0_N5 → PENT_NN0_N5 - ← PENT_WW0_S0
LV[0] → LV[1] [BLACKHOLE] [BLACKHOLE] ← LV[17]
LV[1] → LV[2] [BLACKHOLE] [BLACKHOLE] ← LV[16]
LV[2] → LV[3] [BLACKHOLE] [BLACKHOLE] ← LV[15]
LV[3] → LV[4] [BLACKHOLE] [BLACKHOLE] ← LV[14]
LV[4] → LV[5] [BLACKHOLE] [BLACKHOLE] ← LV[13]
LV[5] → LV[6] [BLACKHOLE] [BLACKHOLE] ← LV[12]
LV[6] → LV[7] [BLACKHOLE] [BLACKHOLE] ← LV[11]
LV[7] → LV[8] [BLACKHOLE] [BLACKHOLE] ← LV[10]
LV[8] → LV[9] [BLACKHOLE] [BLACKHOLE] ← LV[9]
IMUX_CTRL_BOUNCE_S0 → IMUX_CTRL_BOUNCE[0] → IMUX_CTRL_BOUNCE[0] - ← IMUX_CTRL_BOUNCE[3]
IMUX_BYP_BOUNCE_S0 → IMUX_BYP_BOUNCE[0] → IMUX_BYP_BOUNCE[0] - -
IMUX_BYP_BOUNCE_S4 → IMUX_BYP_BOUNCE[4] → IMUX_BYP_BOUNCE[4] - -
IMUX_FAN_BOUNCE_S0 → IMUX_FAN_BOUNCE[0] → IMUX_FAN_BOUNCE[0] - ← IMUX_FAN_BOUNCE[7]
OUT_S12_DBL → OUT[12] → OUT[12] - -
OUT_S18_DBL → OUT[18] → OUT[18] - -
OUT_S12_PENT → OUT[12] → OUT[12] - ← OUT[17]
OUT_S18_PENT → OUT[18] → OUT[18] - -

Connectors — IO_S

virtex5 wires
Wire IO_S
VRCLK_N[0] → VRCLK[0]
VRCLK_N[1] → VRCLK[1]

Connectors — IO_N

virtex5 wires
Wire IO_N
VRCLK_S[0] → VRCLK[0]
VRCLK_S[1] → VRCLK[1]

Connectors — CLK_PREV

virtex5 wires
Wire CLK_PREV
IMUX_BUFG_I[0] → IMUX_BUFG_O[0]
IMUX_BUFG_I[1] → IMUX_BUFG_O[1]
IMUX_BUFG_I[2] → IMUX_BUFG_O[2]
IMUX_BUFG_I[3] → IMUX_BUFG_O[3]
IMUX_BUFG_I[4] → IMUX_BUFG_O[4]
IMUX_BUFG_I[5] → IMUX_BUFG_O[5]
IMUX_BUFG_I[6] → IMUX_BUFG_O[6]
IMUX_BUFG_I[7] → IMUX_BUFG_O[7]
IMUX_BUFG_I[8] → IMUX_BUFG_O[8]
IMUX_BUFG_I[9] → IMUX_BUFG_O[9]
IMUX_BUFG_I[10] → IMUX_BUFG_O[10]
IMUX_BUFG_I[11] → IMUX_BUFG_O[11]
IMUX_BUFG_I[12] → IMUX_BUFG_O[12]
IMUX_BUFG_I[13] → IMUX_BUFG_O[13]
IMUX_BUFG_I[14] → IMUX_BUFG_O[14]
IMUX_BUFG_I[15] → IMUX_BUFG_O[15]
IMUX_BUFG_I[16] → IMUX_BUFG_O[16]
IMUX_BUFG_I[17] → IMUX_BUFG_O[17]
IMUX_BUFG_I[18] → IMUX_BUFG_O[18]
IMUX_BUFG_I[19] → IMUX_BUFG_O[19]
IMUX_BUFG_I[20] → IMUX_BUFG_O[20]
IMUX_BUFG_I[21] → IMUX_BUFG_O[21]
IMUX_BUFG_I[22] → IMUX_BUFG_O[22]
IMUX_BUFG_I[23] → IMUX_BUFG_O[23]
IMUX_BUFG_I[24] → IMUX_BUFG_O[24]
IMUX_BUFG_I[25] → IMUX_BUFG_O[25]
IMUX_BUFG_I[26] → IMUX_BUFG_O[26]
IMUX_BUFG_I[27] → IMUX_BUFG_O[27]
IMUX_BUFG_I[28] → IMUX_BUFG_O[28]
IMUX_BUFG_I[29] → IMUX_BUFG_O[29]
IMUX_BUFG_I[30] → IMUX_BUFG_O[30]
IMUX_BUFG_I[31] → IMUX_BUFG_O[31]

Connectors — CLK_NEXT

virtex5 wires
Wire CLK_NEXT

Connectors — BEL_S

virtex5 wires
Wire

Connectors — BEL_N

virtex5 wires
Wire

Connectors — CMT_PREV

virtex5 wires
Wire

Connectors — CMT_NEXT

virtex5 wires
Wire

Connectors — HCLK_ROW_PREV

virtex5 wires
Wire HCLK_ROW_PREV HCLK_ROW_PREV_PASS
MGT_ROW_I[0] → MGT_ROW_O[0] → MGT_ROW_I[0]
MGT_ROW_I[1] → MGT_ROW_O[1] → MGT_ROW_I[1]
MGT_ROW_I[2] → MGT_ROW_O[2] → MGT_ROW_I[2]
MGT_ROW_I[3] → MGT_ROW_O[3] → MGT_ROW_I[3]
MGT_ROW_I[4] → MGT_ROW_O[4] → MGT_ROW_I[4]

Connectors — HCLK_ROW_NEXT

virtex5 wires
Wire HCLK_ROW_NEXT

Tile INT

Cells: 1

Switchbox INT

virtex5 INT switchbox INT permanent buffers
DestinationSource
DBL_WS1_BUF0DBL_WS1[0]
DBL_NE1_BUF2DBL_NE1[2]
PENT_WS3_BUF0PENT_WS3[0]
PENT_NE3_BUF2PENT_NE3[2]
IMUX_CTRL_SITE[0]IMUX_CTRL[0]
IMUX_CTRL_SITE[1]IMUX_CTRL[1]
IMUX_CTRL_SITE[2]IMUX_CTRL[2]
IMUX_CTRL_SITE[3]IMUX_CTRL[3]
IMUX_CTRL_BOUNCE[0]IMUX_CTRL[0]
IMUX_CTRL_BOUNCE[1]IMUX_CTRL[1]
IMUX_CTRL_BOUNCE[2]IMUX_CTRL[2]
IMUX_CTRL_BOUNCE[3]IMUX_CTRL[3]
IMUX_BYP_SITE[0]IMUX_BYP[0]
IMUX_BYP_SITE[1]IMUX_BYP[1]
IMUX_BYP_SITE[2]IMUX_BYP[2]
IMUX_BYP_SITE[3]IMUX_BYP[3]
IMUX_BYP_SITE[4]IMUX_BYP[4]
IMUX_BYP_SITE[5]IMUX_BYP[5]
IMUX_BYP_SITE[6]IMUX_BYP[6]
IMUX_BYP_SITE[7]IMUX_BYP[7]
IMUX_BYP_BOUNCE[0]IMUX_BYP[0]
IMUX_BYP_BOUNCE[1]IMUX_BYP[1]
IMUX_BYP_BOUNCE[2]IMUX_BYP[2]
IMUX_BYP_BOUNCE[3]IMUX_BYP[3]
IMUX_BYP_BOUNCE[4]IMUX_BYP[4]
IMUX_BYP_BOUNCE[5]IMUX_BYP[5]
IMUX_BYP_BOUNCE[6]IMUX_BYP[6]
IMUX_BYP_BOUNCE[7]IMUX_BYP[7]
IMUX_FAN_SITE[0]IMUX_FAN[0]
IMUX_FAN_SITE[1]IMUX_FAN[1]
IMUX_FAN_SITE[2]IMUX_FAN[2]
IMUX_FAN_SITE[3]IMUX_FAN[3]
IMUX_FAN_SITE[4]IMUX_FAN[4]
IMUX_FAN_SITE[5]IMUX_FAN[5]
IMUX_FAN_SITE[6]IMUX_FAN[6]
IMUX_FAN_SITE[7]IMUX_FAN[7]
IMUX_FAN_BOUNCE[0]IMUX_FAN[0]
IMUX_FAN_BOUNCE[1]IMUX_FAN[1]
IMUX_FAN_BOUNCE[2]IMUX_FAN[2]
IMUX_FAN_BOUNCE[3]IMUX_FAN[3]
IMUX_FAN_BOUNCE[4]IMUX_FAN[4]
IMUX_FAN_BOUNCE[5]IMUX_FAN[5]
IMUX_FAN_BOUNCE[6]IMUX_FAN[6]
IMUX_FAN_BOUNCE[7]IMUX_FAN[7]
virtex5 INT switchbox INT muxes DBL_WW0_S0
BitsDestination
MAIN[8][61]MAIN[7][61]MAIN[9][63]MAIN[8][63]MAIN[12][63]MAIN[12][62]MAIN[12][61]MAIN[7][63]MAIN[11][61]MAIN[11][63]DBL_WW0_S0
Source
0000000000off
0001000001DBL_WS1_S0
0001000010DBL_NE1[2]
0001000100PENT_WS3_S0
0001001000PENT_NE3[2]
0001010000OUT[21]
0001100000OUT[11]
0010000001DBL_WN2_S0
0010000010DBL_NW2[2]
0010000100PENT_WN5_S0
0010001000PENT_NW5[2]
0010010000OUT[3]
0010100000OUT[6]
0100000001DBL_NN1[2]
0100000010DBL_NN1[5]
0100000100PENT_NN3[2]
0100001000PENT_NN3[5]
0100010000OUT[17]
0100100000OUT[15]
1000000001DBL_NN2[2]
1000000010DBL_NN2[5]
1000000100PENT_NN5[2]
1000001000PENT_NN5[5]
1000010000OUT_S12_DBL
1000100000OUT_S18_DBL
virtex5 INT switchbox INT muxes DBL_WW0_N5
BitsDestination
MAIN[9][6]MAIN[6][6]MAIN[7][6]MAIN[8][6]MAIN[10][6]MAIN[13][6]MAIN[6][7]MAIN[6][5]MAIN[10][7]MAIN[11][6]DBL_WW0_N5
Source
0000000000off
0001000001DBL_WS2[0]
0001000010DBL_SW2[0]
0001000100PENT_WS5[0]
0001001000PENT_SW5[0]
0001010000OUT[18]
0001100000OUT[12]
0010000001DBL_WN1[0]
0010000010DBL_SE1[0]
0010000100PENT_WN3[0]
0010001000PENT_SE3[0]
0010010000OUT_N15_DBL
0010100000OUT_N17_DBL
0100000001DBL_SS1[0]
0100000010DBL_SS1[3]
0100000100PENT_SS3[0]
0100001000PENT_SS3[3]
0100010000OUT[0]
0100100000OUT[5]
1000000001DBL_SS2[0]
1000000010DBL_SS2[3]
1000000100PENT_SS5[0]
1000001000PENT_SS5[3]
1000010000OUT[22]
1000100000OUT[8]
virtex5 INT switchbox INT muxes DBL_WW0[1]
BitsDestination
MAIN[9][19]MAIN[6][19]MAIN[9][20]MAIN[6][20]MAIN[13][21]MAIN[13][18]MAIN[13][20]MAIN[6][18]MAIN[10][21]MAIN[10][18]DBL_WW0[1]
Source
0000000000off
0001000001DBL_WS1[1]
0001000010DBL_NE1[0]
0001000100PENT_WS3[1]
0001001000PENT_NE3[0]
0001010000OUT[0]
0001100000OUT[5]
0010000001DBL_WN2[1]
0010000010DBL_NW2[0]
0010000100PENT_WN5[1]
0010001000PENT_NW5[0]
0010010000OUT[22]
0010100000OUT[8]
0100000001DBL_NN1[0]
0100000010DBL_NN1[3]
0100000100PENT_NN3[0]
0100001000PENT_NN3[3]
0100010000OUT[4]
0100100000OUT[1]
1000000001DBL_NN2[0]
1000000010DBL_NN2[3]
1000000100PENT_NN5[0]
1000001000PENT_NN5[3]
1000010000OUT[9]
1000100000OUT[23]
virtex5 INT switchbox INT muxes DBL_WW0[2]
BitsDestination
MAIN[9][40]MAIN[8][40]MAIN[8][42]MAIN[9][42]MAIN[12][40]MAIN[12][42]MAIN[6][40]MAIN[7][42]MAIN[11][42]MAIN[11][40]DBL_WW0[2]
Source
0000000000off
0001000001DBL_WS1[2]
0001000010DBL_NE1[1]
0001000100PENT_WS3[2]
0001001000PENT_NE3[1]
0001010000OUT[16]
0001100000OUT[14]
0010000001DBL_WN2[2]
0010000010DBL_NW2[1]
0010000100PENT_WN5[2]
0010001000PENT_NW5[1]
0010010000OUT[13]
0010100000OUT[19]
0100000001DBL_NN1[1]
0100000010DBL_NN1[4]
0100000100PENT_NN3[1]
0100001000PENT_NN3[4]
0100010000OUT[20]
0100100000OUT[10]
1000000001DBL_NN2[1]
1000000010DBL_NN2[4]
1000000100PENT_NN5[1]
1000001000PENT_NN5[4]
1000010000OUT[2]
1000100000OUT[7]
virtex5 INT switchbox INT muxes DBL_WW0[3]
BitsDestination
MAIN[8][28]MAIN[7][28]MAIN[7][27]MAIN[8][27]MAIN[11][28]MAIN[11][27]MAIN[13][27]MAIN[9][29]MAIN[10][27]MAIN[10][28]DBL_WW0[3]
Source
0000000000off
0001000001DBL_WS2[1]
0001000010DBL_SW2[1]
0001000100PENT_WS5[1]
0001001000PENT_SW5[1]
0001010000OUT[23]
0001100000OUT[9]
0010000001DBL_WN1[1]
0010000010DBL_SE1[1]
0010000100PENT_WN3[1]
0010001000PENT_SE3[1]
0010010000OUT[1]
0010100000OUT[4]
0100000001DBL_SS1[1]
0100000010DBL_SS1[4]
0100000100PENT_SS3[1]
0100001000PENT_SS3[4]
0100010000OUT[14]
0100100000OUT[16]
1000000001DBL_SS2[1]
1000000010DBL_SS2[4]
1000000100PENT_SS5[1]
1000001000PENT_SS5[4]
1000010000OUT[19]
1000100000OUT[13]
virtex5 INT switchbox INT muxes DBL_WW0[4]
BitsDestination
MAIN[8][49]MAIN[7][49]MAIN[9][49]MAIN[6][49]MAIN[11][49]MAIN[12][49]MAIN[13][49]MAIN[7][48]MAIN[10][48]MAIN[10][49]DBL_WW0[4]
Source
0000000000off
0001000001DBL_WS2[2]
0001000010DBL_SW2[2]
0001000100PENT_WS5[2]
0001001000PENT_SW5[2]
0001010000OUT[2]
0001100000OUT[7]
0010000001DBL_WN1[2]
0010000010DBL_SE1[2]
0010000100PENT_WN3[2]
0010001000PENT_SE3[2]
0010010000OUT[20]
0010100000OUT[10]
0100000001DBL_SS1[2]
0100000010DBL_SS1[5]
0100000100PENT_SS3[2]
0100001000PENT_SS3[5]
0100010000OUT[11]
0100100000OUT[21]
1000000001DBL_SS2[2]
1000000010DBL_SS2[5]
1000000100PENT_SS5[2]
1000001000PENT_SS5[5]
1000010000OUT[6]
1000100000OUT[3]
virtex5 INT switchbox INT muxes DBL_WS0[0]
BitsDestination
MAIN[7][4]MAIN[8][4]MAIN[8][3]MAIN[7][3]MAIN[11][3]MAIN[11][4]MAIN[13][3]MAIN[9][5]MAIN[10][3]MAIN[10][4]DBL_WS0[0]
Source
0000000000off
0001000001DBL_WW1[0]
0001000010DBL_WW1[3]
0001000100PENT_WW3[0]
0001001000PENT_WW3[3]
0001010000OUT_N15_DBL
0001100000OUT_N17_DBL
0010000001DBL_WW2[0]
0010000010DBL_WW2[3]
0010000100PENT_WW5[0]
0010001000PENT_WW5[3]
0010010000OUT[18]
0010100000OUT[12]
0100000001DBL_WS2[0]
0100000010DBL_SW2[0]
0100000100PENT_WS5[0]
0100001000PENT_SW5[0]
0100010000OUT[22]
0100100000OUT[8]
1000000001DBL_WN1[0]
1000000010DBL_SE1[0]
1000000100PENT_WN3[0]
1000001000PENT_SE3[0]
1000010000OUT[0]
1000100000OUT[5]
virtex5 INT switchbox INT muxes DBL_WS0[1]
BitsDestination
MAIN[7][25]MAIN[8][25]MAIN[6][25]MAIN[9][25]MAIN[12][25]MAIN[11][25]MAIN[13][25]MAIN[7][24]MAIN[10][24]MAIN[10][25]DBL_WS0[1]
Source
0000000000off
0001000001DBL_WW1[1]
0001000010DBL_WW1[4]
0001000100PENT_WW3[1]
0001001000PENT_WW3[4]
0001010000OUT[1]
0001100000OUT[4]
0010000001DBL_WW2[1]
0010000010DBL_WW2[4]
0010000100PENT_WW5[1]
0010001000PENT_WW5[4]
0010010000OUT[23]
0010100000OUT[9]
0100000001DBL_WS2[1]
0100000010DBL_SW2[1]
0100000100PENT_WS5[1]
0100001000PENT_SW5[1]
0100010000OUT[19]
0100100000OUT[13]
1000000001DBL_WN1[1]
1000000010DBL_SE1[1]
1000000100PENT_WN3[1]
1000001000PENT_SE3[1]
1000010000OUT[14]
1000100000OUT[16]
virtex5 INT switchbox INT muxes DBL_WS0[2]
BitsDestination
MAIN[6][46]MAIN[9][46]MAIN[8][46]MAIN[7][46]MAIN[10][46]MAIN[13][46]MAIN[6][47]MAIN[6][45]MAIN[10][47]MAIN[11][46]DBL_WS0[2]
Source
0000000000off
0001000001DBL_WW1[2]
0001000010DBL_WW1[5]
0001000100PENT_WW3[2]
0001001000PENT_WW3[5]
0001010000OUT[20]
0001100000OUT[10]
0010000001DBL_WW2[2]
0010000010DBL_WW2[5]
0010000100PENT_WW5[2]
0010001000PENT_WW5[5]
0010010000OUT[2]
0010100000OUT[7]
0100000001DBL_WS2[2]
0100000010DBL_SW2[2]
0100000100PENT_WS5[2]
0100001000PENT_SW5[2]
0100010000OUT[6]
0100100000OUT[3]
1000000001DBL_WN1[2]
1000000010DBL_SE1[2]
1000000100PENT_WN3[2]
1000001000PENT_SE3[2]
1000010000OUT[11]
1000100000OUT[21]
virtex5 INT switchbox INT muxes DBL_WN0[0]
BitsDestination
MAIN[9][0]MAIN[8][0]MAIN[8][2]MAIN[9][2]MAIN[12][0]MAIN[12][2]MAIN[6][0]MAIN[7][2]MAIN[11][2]MAIN[11][0]DBL_WN0[0]
Source
0000000000off
0001000001DBL_WW1[0]
0001000010DBL_WW1[3]
0001000100PENT_WW3[0]
0001001000PENT_WW3[3]
0001010000OUT[0]
0001100000OUT[5]
0010000001DBL_WW2[0]
0010000010DBL_WW2[3]
0010000100PENT_WW5[0]
0010001000PENT_WW5[3]
0010010000OUT[22]
0010100000OUT[8]
0100000001DBL_WS1[0]
0100000010DBL_NE1_N2
0100000100PENT_WS3[0]
0100001000PENT_NE3_N2
0100010000OUT_N15_DBL
0100100000OUT_N17_DBL
1000000001DBL_WN2[0]
1000000010DBL_NW2_N2
1000000100PENT_WN5[0]
1000001000PENT_NW5_N2
1000010000OUT[18]
1000100000OUT[12]
virtex5 INT switchbox INT muxes DBL_WN0[1]
BitsDestination
MAIN[8][21]MAIN[7][21]MAIN[9][23]MAIN[8][23]MAIN[12][23]MAIN[12][22]MAIN[12][21]MAIN[7][23]MAIN[11][21]MAIN[11][23]DBL_WN0[1]
Source
0000000000off
0001000001DBL_WW1[1]
0001000010DBL_WW1[4]
0001000100PENT_WW3[1]
0001001000PENT_WW3[4]
0001010000OUT[14]
0001100000OUT[16]
0010000001DBL_WW2[1]
0010000010DBL_WW2[4]
0010000100PENT_WW5[1]
0010001000PENT_WW5[4]
0010010000OUT[19]
0010100000OUT[13]
0100000001DBL_WS1[1]
0100000010DBL_NE1[0]
0100000100PENT_WS3[1]
0100001000PENT_NE3[0]
0100010000OUT[1]
0100100000OUT[4]
1000000001DBL_WN2[1]
1000000010DBL_NW2[0]
1000000100PENT_WN5[1]
1000001000PENT_NW5[0]
1000010000OUT[23]
1000100000OUT[9]
virtex5 INT switchbox INT muxes DBL_WN0[2]
BitsDestination
MAIN[9][43]MAIN[6][43]MAIN[9][44]MAIN[6][44]MAIN[13][45]MAIN[13][42]MAIN[13][44]MAIN[6][42]MAIN[10][45]MAIN[10][42]DBL_WN0[2]
Source
0000000000off
0001000001DBL_WW1[2]
0001000010DBL_WW1[5]
0001000100PENT_WW3[2]
0001001000PENT_WW3[5]
0001010000OUT[11]
0001100000OUT[21]
0010000001DBL_WW2[2]
0010000010DBL_WW2[5]
0010000100PENT_WW5[2]
0010001000PENT_WW5[5]
0010010000OUT[6]
0010100000OUT[3]
0100000001DBL_WS1[2]
0100000010DBL_NE1[1]
0100000100PENT_WS3[2]
0100001000PENT_NE3[1]
0100010000OUT[20]
0100100000OUT[10]
1000000001DBL_WN2[2]
1000000010DBL_NW2[1]
1000000100PENT_WN5[2]
1000001000PENT_NW5[1]
1000010000OUT[2]
1000100000OUT[7]
virtex5 INT switchbox INT muxes DBL_EE0_S3
BitsDestination
MAIN[8][60]MAIN[7][60]MAIN[8][59]MAIN[7][59]MAIN[11][60]MAIN[11][59]MAIN[13][59]MAIN[9][61]MAIN[10][59]MAIN[10][60]DBL_EE0_S3
Source
0000000000off
0001000001DBL_ES1[2]
0001000010DBL_NW1[2]
0001000100PENT_ES3[2]
0001001000PENT_NW3[2]
0001010000OUT[17]
0001100000OUT[15]
0010000001DBL_EN2[2]
0010000010DBL_NE2[2]
0010000100PENT_EN5[2]
0010001000PENT_NE5[2]
0010010000OUT_S12_DBL
0010100000OUT_S18_DBL
0100000001DBL_NN1[2]
0100000010DBL_NN1[5]
0100000100PENT_NN3[2]
0100001000PENT_NN3[5]
0100010000OUT[21]
0100100000OUT[11]
1000000001DBL_NN2[2]
1000000010DBL_NN2[5]
1000000100PENT_NN5[2]
1000001000PENT_NN5[5]
1000010000OUT[3]
1000100000OUT[6]
virtex5 INT switchbox INT muxes DBL_EE0[0]
BitsDestination
MAIN[9][8]MAIN[8][8]MAIN[9][10]MAIN[8][10]MAIN[12][8]MAIN[12][10]MAIN[7][10]MAIN[6][8]MAIN[11][8]MAIN[11][10]DBL_EE0[0]
Source
0000000000off
0001000001DBL_ES2[0]
0001000010DBL_SE2[0]
0001000100PENT_ES5[0]
0001001000PENT_SE5[0]
0001010000OUT[22]
0001100000OUT[8]
0010000001DBL_EN1[0]
0010000010DBL_SW1[0]
0010000100PENT_EN3[0]
0010001000PENT_SW3[0]
0010010000OUT[0]
0010100000OUT[5]
0100000001DBL_SS1[3]
0100000010DBL_SS1[0]
0100000100PENT_SS3[3]
0100001000PENT_SS3[0]
0100010000OUT_N15_DBL
0100100000OUT_N17_DBL
1000000001DBL_SS2[3]
1000000010DBL_SS2[0]
1000000100PENT_SS5[3]
1000001000PENT_SS5[0]
1000010000OUT[18]
1000100000OUT[12]
virtex5 INT switchbox INT muxes DBL_EE0[1]
BitsDestination
MAIN[8][29]MAIN[7][29]MAIN[8][31]MAIN[9][31]MAIN[12][31]MAIN[12][30]MAIN[7][31]MAIN[12][29]MAIN[11][31]MAIN[11][29]DBL_EE0[1]
Source
0000000000off
0001000001DBL_ES2[1]
0001000010DBL_SE2[1]
0001000100PENT_ES5[1]
0001001000PENT_SE5[1]
0001010000OUT[19]
0001100000OUT[13]
0010000001DBL_EN1[1]
0010000010DBL_SW1[1]
0010000100PENT_EN3[1]
0010001000PENT_SW3[1]
0010010000OUT[14]
0010100000OUT[16]
0100000001DBL_SS1[4]
0100000010DBL_SS1[1]
0100000100PENT_SS3[4]
0100001000PENT_SS3[1]
0100010000OUT[1]
0100100000OUT[4]
1000000001DBL_SS2[4]
1000000010DBL_SS2[1]
1000000100PENT_SS5[4]
1000001000PENT_SS5[1]
1000010000OUT[23]
1000100000OUT[9]
virtex5 INT switchbox INT muxes DBL_EE0[2]
BitsDestination
MAIN[9][51]MAIN[6][51]MAIN[6][52]MAIN[9][52]MAIN[13][53]MAIN[13][50]MAIN[6][50]MAIN[13][52]MAIN[10][50]MAIN[10][53]DBL_EE0[2]
Source
0000000000off
0001000001DBL_ES2[2]
0001000010DBL_SE2[2]
0001000100PENT_ES5[2]
0001001000PENT_SE5[2]
0001010000OUT[6]
0001100000OUT[3]
0010000001DBL_EN1[2]
0010000010DBL_SW1[2]
0010000100PENT_EN3[2]
0010001000PENT_SW3[2]
0010010000OUT[11]
0010100000OUT[21]
0100000001DBL_SS1[5]
0100000010DBL_SS1[2]
0100000100PENT_SS3[5]
0100001000PENT_SS3[2]
0100010000OUT[20]
0100100000OUT[10]
1000000001DBL_SS2[5]
1000000010DBL_SS2[2]
1000000100PENT_SS5[5]
1000001000PENT_SS5[2]
1000010000OUT[2]
1000100000OUT[7]
virtex5 INT switchbox INT muxes DBL_EE0[4]
BitsDestination
MAIN[8][17]MAIN[7][17]MAIN[6][17]MAIN[9][17]MAIN[11][17]MAIN[12][17]MAIN[13][17]MAIN[7][16]MAIN[10][16]MAIN[10][17]DBL_EE0[4]
Source
0000000000off
0001000001DBL_ES1[0]
0001000010DBL_NW1[0]
0001000100PENT_ES3[0]
0001001000PENT_NW3[0]
0001010000OUT[4]
0001100000OUT[1]
0010000001DBL_EN2[0]
0010000010DBL_NE2[0]
0010000100PENT_EN5[0]
0010001000PENT_NE5[0]
0010010000OUT[9]
0010100000OUT[23]
0100000001DBL_NN1[0]
0100000010DBL_NN1[3]
0100000100PENT_NN3[0]
0100001000PENT_NN3[3]
0100010000OUT[0]
0100100000OUT[5]
1000000001DBL_NN2[0]
1000000010DBL_NN2[3]
1000000100PENT_NN5[0]
1000001000PENT_NN5[3]
1000010000OUT[22]
1000100000OUT[8]
virtex5 INT switchbox INT muxes DBL_EE0[5]
BitsDestination
MAIN[9][38]MAIN[6][38]MAIN[8][38]MAIN[7][38]MAIN[10][38]MAIN[13][38]MAIN[6][39]MAIN[6][37]MAIN[10][39]MAIN[11][38]DBL_EE0[5]
Source
0000000000off
0001000001DBL_ES1[1]
0001000010DBL_NW1[1]
0001000100PENT_ES3[1]
0001001000PENT_NW3[1]
0001010000OUT[20]
0001100000OUT[10]
0010000001DBL_EN2[1]
0010000010DBL_NE2[1]
0010000100PENT_EN5[1]
0010001000PENT_NE5[1]
0010010000OUT[2]
0010100000OUT[7]
0100000001DBL_NN1[1]
0100000010DBL_NN1[4]
0100000100PENT_NN3[1]
0100001000PENT_NN3[4]
0100010000OUT[16]
0100100000OUT[14]
1000000001DBL_NN2[1]
1000000010DBL_NN2[4]
1000000100PENT_NN5[1]
1000001000PENT_NN5[4]
1000010000OUT[13]
1000100000OUT[19]
virtex5 INT switchbox INT muxes DBL_ES0[0]
BitsDestination
MAIN[6][11]MAIN[9][11]MAIN[9][12]MAIN[6][12]MAIN[13][13]MAIN[13][10]MAIN[13][12]MAIN[6][10]MAIN[10][13]MAIN[10][10]DBL_ES0[0]
Source
0000000000off
0001000001DBL_EE1[0]
0001000010DBL_EE1[3]
0001000100PENT_EE3[0]
0001001000PENT_EE3[3]
0001010000OUT[0]
0001100000OUT[5]
0010000001DBL_EE2[0]
0010000010DBL_EE2[3]
0010000100PENT_EE5[0]
0010001000PENT_EE5[3]
0010010000OUT[22]
0010100000OUT[8]
0100000001DBL_SE2[0]
0100000010DBL_ES2[0]
0100000100PENT_SE5[0]
0100001000PENT_ES5[0]
0100010000OUT[9]
0100100000OUT[23]
1000000001DBL_SW1[0]
1000000010DBL_EN1[0]
1000000100PENT_SW3[0]
1000001000PENT_EN3[0]
1000010000OUT[4]
1000100000OUT[1]
virtex5 INT switchbox INT muxes DBL_ES0[1]
BitsDestination
MAIN[8][32]MAIN[9][32]MAIN[8][34]MAIN[9][34]MAIN[12][32]MAIN[12][34]MAIN[6][32]MAIN[7][34]MAIN[11][34]MAIN[11][32]DBL_ES0[1]
Source
0000000000off
0001000001DBL_EE1[1]
0001000010DBL_EE1[4]
0001000100PENT_EE3[1]
0001001000PENT_EE3[4]
0001010000OUT[16]
0001100000OUT[14]
0010000001DBL_EE2[1]
0010000010DBL_EE2[4]
0010000100PENT_EE5[1]
0010001000PENT_EE5[4]
0010010000OUT[13]
0010100000OUT[19]
0100000001DBL_SE2[1]
0100000010DBL_ES2[1]
0100000100PENT_SE5[1]
0100001000PENT_ES5[1]
0100010000OUT[2]
0100100000OUT[7]
1000000001DBL_SW1[1]
1000000010DBL_EN1[1]
1000000100PENT_SW3[1]
1000001000PENT_EN3[1]
1000010000OUT[20]
1000100000OUT[10]
virtex5 INT switchbox INT muxes DBL_ES0[2]
BitsDestination
MAIN[7][53]MAIN[8][53]MAIN[9][55]MAIN[8][55]MAIN[12][55]MAIN[12][54]MAIN[12][53]MAIN[7][55]MAIN[11][53]MAIN[11][55]DBL_ES0[2]
Source
0000000000off
0001000001DBL_EE1[2]
0001000010DBL_EE1[5]
0001000100PENT_EE3[2]
0001001000PENT_EE3[5]
0001010000OUT[21]
0001100000OUT[11]
0010000001DBL_EE2[2]
0010000010DBL_EE2[5]
0010000100PENT_EE5[2]
0010001000PENT_EE5[5]
0010010000OUT[3]
0010100000OUT[6]
0100000001DBL_SE2[2]
0100000010DBL_ES2[2]
0100000100PENT_SE5[2]
0100001000PENT_ES5[2]
0100010000OUT_S12_DBL
0100100000OUT_S18_DBL
1000000001DBL_SW1[2]
1000000010DBL_EN1[2]
1000000100PENT_SW3[2]
1000001000PENT_EN3[2]
1000010000OUT[17]
1000100000OUT[15]
virtex5 INT switchbox INT muxes DBL_EN0[0]
BitsDestination
MAIN[9][14]MAIN[6][14]MAIN[8][14]MAIN[7][14]MAIN[10][14]MAIN[13][14]MAIN[6][15]MAIN[6][13]MAIN[10][15]MAIN[11][14]DBL_EN0[0]
Source
0000000000off
0001000001DBL_EE1[0]
0001000010DBL_EE1[3]
0001000100PENT_EE3[0]
0001001000PENT_EE3[3]
0001010000OUT[4]
0001100000OUT[1]
0010000001DBL_EE2[0]
0010000010DBL_EE2[3]
0010000100PENT_EE5[0]
0010001000PENT_EE5[3]
0010010000OUT[9]
0010100000OUT[23]
0100000001DBL_ES1[0]
0100000010DBL_NW1[0]
0100000100PENT_ES3[0]
0100001000PENT_NW3[0]
0100010000OUT[0]
0100100000OUT[5]
1000000001DBL_EN2[0]
1000000010DBL_NE2[0]
1000000100PENT_EN5[0]
1000001000PENT_NE5[0]
1000010000OUT[22]
1000100000OUT[8]
virtex5 INT switchbox INT muxes DBL_EN0[1]
BitsDestination
MAIN[8][36]MAIN[7][36]MAIN[8][35]MAIN[7][35]MAIN[11][35]MAIN[11][36]MAIN[13][35]MAIN[9][37]MAIN[10][35]MAIN[10][36]DBL_EN0[1]
Source
0000000000off
0001000001DBL_EE1[1]
0001000010DBL_EE1[4]
0001000100PENT_EE3[1]
0001001000PENT_EE3[4]
0001010000OUT[20]
0001100000OUT[10]
0010000001DBL_EE2[1]
0010000010DBL_EE2[4]
0010000100PENT_EE5[1]
0010001000PENT_EE5[4]
0010010000OUT[2]
0010100000OUT[7]
0100000001DBL_ES1[1]
0100000010DBL_NW1[1]
0100000100PENT_ES3[1]
0100001000PENT_NW3[1]
0100010000OUT[16]
0100100000OUT[14]
1000000001DBL_EN2[1]
1000000010DBL_NE2[1]
1000000100PENT_EN5[1]
1000001000PENT_NE5[1]
1000010000OUT[13]
1000100000OUT[19]
virtex5 INT switchbox INT muxes DBL_EN0[2]
BitsDestination
MAIN[8][57]MAIN[7][57]MAIN[6][57]MAIN[9][57]MAIN[12][57]MAIN[11][57]MAIN[13][57]MAIN[7][56]MAIN[10][56]MAIN[10][57]DBL_EN0[2]
Source
0000000000off
0001000001DBL_EE1[2]
0001000010DBL_EE1[5]
0001000100PENT_EE3[2]
0001001000PENT_EE3[5]
0001010000OUT[17]
0001100000OUT[15]
0010000001DBL_EE2[2]
0010000010DBL_EE2[5]
0010000100PENT_EE5[2]
0010001000PENT_EE5[5]
0010010000OUT_S12_DBL
0010100000OUT_S18_DBL
0100000001DBL_ES1[2]
0100000010DBL_NW1[2]
0100000100PENT_ES3[2]
0100001000PENT_NW3[2]
0100010000OUT[21]
0100100000OUT[11]
1000000001DBL_EN2[2]
1000000010DBL_NE2[2]
1000000100PENT_EN5[2]
1000001000PENT_NE5[2]
1000010000OUT[3]
1000100000OUT[6]
virtex5 INT switchbox INT muxes DBL_NN0_S0
BitsDestination
MAIN[8][58]MAIN[9][58]MAIN[9][56]MAIN[8][56]MAIN[12][58]MAIN[12][56]MAIN[6][56]MAIN[7][58]MAIN[11][58]MAIN[11][56]DBL_NN0_S0
Source
0000000000off
0001000001DBL_EE1[2]
0001000010DBL_EE1[5]
0001000100PENT_EE3[2]
0001001000PENT_EE3[5]
0001010000OUT[17]
0001100000OUT[15]
0010000001DBL_EE2[2]
0010000010DBL_EE2[5]
0010000100PENT_EE5[2]
0010001000PENT_EE5[5]
0010010000OUT_S12_DBL
0010100000OUT_S18_DBL
0100000001DBL_ES1[2]
0100000010DBL_NW1[2]
0100000100PENT_ES3[2]
0100001000PENT_NW3[2]
0100010000OUT[21]
0100100000OUT[11]
1000000001DBL_EN2[2]
1000000010DBL_NE2[2]
1000000100PENT_EN5[2]
1000001000PENT_NE5[2]
1000010000OUT[3]
1000100000OUT[6]
virtex5 INT switchbox INT muxes DBL_NN0_N5
BitsDestination
MAIN[6][1]MAIN[9][1]MAIN[8][1]MAIN[7][1]MAIN[11][1]MAIN[12][1]MAIN[13][1]MAIN[7][0]MAIN[10][0]MAIN[10][1]DBL_NN0_N5
Source
0000000000off
0001000001DBL_WW1[0]
0001000010DBL_WW1[3]
0001000100PENT_WW3[0]
0001001000PENT_WW3[3]
0001010000OUT[0]
0001100000OUT[5]
0010000001DBL_WW2[0]
0010000010DBL_WW2[3]
0010000100PENT_WW5[0]
0010001000PENT_WW5[3]
0010010000OUT[22]
0010100000OUT[8]
0100000001DBL_WS1[0]
0100000010DBL_NE1_N2
0100000100PENT_WS3[0]
0100001000PENT_NE3_N2
0100010000OUT_N15_DBL
0100100000OUT_N17_DBL
1000000001DBL_WN2[0]
1000000010DBL_NW2_N2
1000000100PENT_WN5[0]
1000001000PENT_NW5_N2
1000010000OUT[18]
1000100000OUT[12]
virtex5 INT switchbox INT muxes DBL_NN0[1]
BitsDestination
MAIN[9][15]MAIN[8][15]MAIN[8][13]MAIN[7][13]MAIN[12][14]MAIN[12][15]MAIN[12][13]MAIN[7][15]MAIN[11][13]MAIN[11][15]DBL_NN0[1]
Source
0000000000off
0001000001DBL_EE1[0]
0001000010DBL_EE1[3]
0001000100PENT_EE3[0]
0001001000PENT_EE3[3]
0001010000OUT[4]
0001100000OUT[1]
0010000001DBL_EE2[0]
0010000010DBL_EE2[3]
0010000100PENT_EE5[0]
0010001000PENT_EE5[3]
0010010000OUT[9]
0010100000OUT[23]
0100000001DBL_ES1[0]
0100000010DBL_NW1[0]
0100000100PENT_ES3[0]
0100001000PENT_NW3[0]
0100010000OUT[0]
0100100000OUT[5]
1000000001DBL_EN2[0]
1000000010DBL_NE2[0]
1000000100PENT_EN5[0]
1000001000PENT_NE5[0]
1000010000OUT[22]
1000100000OUT[8]
virtex5 INT switchbox INT muxes DBL_NN0[2]
BitsDestination
MAIN[9][36]MAIN[6][36]MAIN[9][35]MAIN[6][35]MAIN[13][37]MAIN[13][34]MAIN[13][36]MAIN[6][34]MAIN[10][37]MAIN[10][34]DBL_NN0[2]
Source
0000000000off
0001000001DBL_EE1[1]
0001000010DBL_EE1[4]
0001000100PENT_EE3[1]
0001001000PENT_EE3[4]
0001010000OUT[20]
0001100000OUT[10]
0010000001DBL_EE2[1]
0010000010DBL_EE2[4]
0010000100PENT_EE5[1]
0010001000PENT_EE5[4]
0010010000OUT[2]
0010100000OUT[7]
0100000001DBL_ES1[1]
0100000010DBL_NW1[1]
0100000100PENT_ES3[1]
0100001000PENT_NW3[1]
0100010000OUT[16]
0100100000OUT[14]
1000000001DBL_EN2[1]
1000000010DBL_NE2[1]
1000000100PENT_EN5[1]
1000001000PENT_NE5[1]
1000010000OUT[13]
1000100000OUT[19]
virtex5 INT switchbox INT muxes DBL_NN0[3]
BitsDestination
MAIN[8][22]MAIN[7][22]MAIN[9][22]MAIN[6][22]MAIN[13][22]MAIN[10][22]MAIN[6][23]MAIN[6][21]MAIN[10][23]MAIN[11][22]DBL_NN0[3]
Source
0000000000off
0001000001DBL_WW1[1]
0001000010DBL_WW1[4]
0001000100PENT_WW3[1]
0001001000PENT_WW3[4]
0001010000OUT[14]
0001100000OUT[16]
0010000001DBL_WW2[1]
0010000010DBL_WW2[4]
0010000100PENT_WW5[1]
0010001000PENT_WW5[4]
0010010000OUT[19]
0010100000OUT[13]
0100000001DBL_WS1[1]
0100000010DBL_NE1[0]
0100000100PENT_WS3[1]
0100001000PENT_NE3[0]
0100010000OUT[1]
0100100000OUT[4]
1000000001DBL_WN2[1]
1000000010DBL_NW2[0]
1000000100PENT_WN5[1]
1000001000PENT_NW5[0]
1000010000OUT[23]
1000100000OUT[9]
virtex5 INT switchbox INT muxes DBL_NN0[4]
BitsDestination
MAIN[8][43]MAIN[7][43]MAIN[8][44]MAIN[7][44]MAIN[11][43]MAIN[11][44]MAIN[13][43]MAIN[9][45]MAIN[10][43]MAIN[10][44]DBL_NN0[4]
Source
0000000000off
0001000001DBL_WW1[2]
0001000010DBL_WW1[5]
0001000100PENT_WW3[2]
0001001000PENT_WW3[5]
0001010000OUT[11]
0001100000OUT[21]
0010000001DBL_WW2[2]
0010000010DBL_WW2[5]
0010000100PENT_WW5[2]
0010001000PENT_WW5[5]
0010010000OUT[6]
0010100000OUT[3]
0100000001DBL_WS1[2]
0100000010DBL_NE1[1]
0100000100PENT_WS3[2]
0100001000PENT_NE3[1]
0100010000OUT[20]
0100100000OUT[10]
1000000001DBL_WN2[2]
1000000010DBL_NW2[1]
1000000100PENT_WN5[2]
1000001000PENT_NW5[1]
1000010000OUT[2]
1000100000OUT[7]
virtex5 INT switchbox INT muxes DBL_NW0[0]
BitsDestination
MAIN[8][19]MAIN[7][19]MAIN[8][20]MAIN[7][20]MAIN[11][19]MAIN[11][20]MAIN[13][19]MAIN[9][21]MAIN[10][19]MAIN[10][20]DBL_NW0[0]
Source
0000000000off
0001000001DBL_WS1[1]
0001000010DBL_NE1[0]
0001000100PENT_WS3[1]
0001001000PENT_NE3[0]
0001010000OUT[0]
0001100000OUT[5]
0010000001DBL_WN2[1]
0010000010DBL_NW2[0]
0010000100PENT_WN5[1]
0010001000PENT_NW5[0]
0010010000OUT[22]
0010100000OUT[8]
0100000001DBL_NN1[0]
0100000010DBL_NN1[3]
0100000100PENT_NN3[0]
0100001000PENT_NN3[3]
0100010000OUT[4]
0100100000OUT[1]
1000000001DBL_NN2[0]
1000000010DBL_NN2[3]
1000000100PENT_NN5[0]
1000001000PENT_NN5[3]
1000010000OUT[9]
1000100000OUT[23]
virtex5 INT switchbox INT muxes DBL_NW0[1]
BitsDestination
MAIN[6][41]MAIN[9][41]MAIN[8][41]MAIN[7][41]MAIN[11][41]MAIN[12][41]MAIN[13][41]MAIN[7][40]MAIN[10][40]MAIN[10][41]DBL_NW0[1]
Source
0000000000off
0001000001DBL_WS1[2]
0001000010DBL_NE1[1]
0001000100PENT_WS3[2]
0001001000PENT_NE3[1]
0001010000OUT[16]
0001100000OUT[14]
0010000001DBL_WN2[2]
0010000010DBL_NW2[1]
0010000100PENT_WN5[2]
0010001000PENT_NW5[1]
0010010000OUT[13]
0010100000OUT[19]
0100000001DBL_NN1[1]
0100000010DBL_NN1[4]
0100000100PENT_NN3[1]
0100001000PENT_NN3[4]
0100010000OUT[20]
0100100000OUT[10]
1000000001DBL_NN2[1]
1000000010DBL_NN2[4]
1000000100PENT_NN5[1]
1000001000PENT_NN5[4]
1000010000OUT[2]
1000100000OUT[7]
virtex5 INT switchbox INT muxes DBL_NW0[2]
BitsDestination
MAIN[8][62]MAIN[7][62]MAIN[9][62]MAIN[6][62]MAIN[13][62]MAIN[10][62]MAIN[6][63]MAIN[6][61]MAIN[10][63]MAIN[11][62]DBL_NW0[2]
Source
0000000000off
0001000001DBL_WS1_S0
0001000010DBL_NE1[2]
0001000100PENT_WS3_S0
0001001000PENT_NE3[2]
0001010000OUT[21]
0001100000OUT[11]
0010000001DBL_WN2_S0
0010000010DBL_NW2[2]
0010000100PENT_WN5_S0
0010001000PENT_NW5[2]
0010010000OUT[3]
0010100000OUT[6]
0100000001DBL_NN1[2]
0100000010DBL_NN1[5]
0100000100PENT_NN3[2]
0100001000PENT_NN3[5]
0100010000OUT[17]
0100100000OUT[15]
1000000001DBL_NN2[2]
1000000010DBL_NN2[5]
1000000100PENT_NN5[2]
1000001000PENT_NN5[5]
1000010000OUT_S12_DBL
1000100000OUT_S18_DBL
virtex5 INT switchbox INT muxes DBL_NE0[0]
BitsDestination
MAIN[8][18]MAIN[9][18]MAIN[9][16]MAIN[8][16]MAIN[12][16]MAIN[12][18]MAIN[6][16]MAIN[7][18]MAIN[11][18]MAIN[11][16]DBL_NE0[0]
Source
0000000000off
0001000001DBL_ES1[0]
0001000010DBL_NW1[0]
0001000100PENT_ES3[0]
0001001000PENT_NW3[0]
0001010000OUT[4]
0001100000OUT[1]
0010000001DBL_EN2[0]
0010000010DBL_NE2[0]
0010000100PENT_EN5[0]
0010001000PENT_NE5[0]
0010010000OUT[9]
0010100000OUT[23]
0100000001DBL_NN1[0]
0100000010DBL_NN1[3]
0100000100PENT_NN3[0]
0100001000PENT_NN3[3]
0100010000OUT[0]
0100100000OUT[5]
1000000001DBL_NN2[0]
1000000010DBL_NN2[3]
1000000100PENT_NN5[0]
1000001000PENT_NN5[3]
1000010000OUT[22]
1000100000OUT[8]
virtex5 INT switchbox INT muxes DBL_NE0[1]
BitsDestination
MAIN[9][39]MAIN[8][39]MAIN[8][37]MAIN[7][37]MAIN[12][38]MAIN[12][39]MAIN[12][37]MAIN[7][39]MAIN[11][37]MAIN[11][39]DBL_NE0[1]
Source
0000000000off
0001000001DBL_ES1[1]
0001000010DBL_NW1[1]
0001000100PENT_ES3[1]
0001001000PENT_NW3[1]
0001010000OUT[20]
0001100000OUT[10]
0010000001DBL_EN2[1]
0010000010DBL_NE2[1]
0010000100PENT_EN5[1]
0010001000PENT_NE5[1]
0010010000OUT[2]
0010100000OUT[7]
0100000001DBL_NN1[1]
0100000010DBL_NN1[4]
0100000100PENT_NN3[1]
0100001000PENT_NN3[4]
0100010000OUT[16]
0100100000OUT[14]
1000000001DBL_NN2[1]
1000000010DBL_NN2[4]
1000000100PENT_NN5[1]
1000001000PENT_NN5[4]
1000010000OUT[13]
1000100000OUT[19]
virtex5 INT switchbox INT muxes DBL_NE0[2]
BitsDestination
MAIN[9][60]MAIN[6][60]MAIN[9][59]MAIN[6][59]MAIN[13][58]MAIN[13][61]MAIN[13][60]MAIN[6][58]MAIN[10][61]MAIN[10][58]DBL_NE0[2]
Source
0000000000off
0001000001DBL_ES1[2]
0001000010DBL_NW1[2]
0001000100PENT_ES3[2]
0001001000PENT_NW3[2]
0001010000OUT[17]
0001100000OUT[15]
0010000001DBL_EN2[2]
0010000010DBL_NE2[2]
0010000100PENT_EN5[2]
0010001000PENT_NE5[2]
0010010000OUT_S12_DBL
0010100000OUT_S18_DBL
0100000001DBL_NN1[2]
0100000010DBL_NN1[5]
0100000100PENT_NN3[2]
0100001000PENT_NN3[5]
0100010000OUT[21]
0100100000OUT[11]
1000000001DBL_NN2[2]
1000000010DBL_NN2[5]
1000000100PENT_NN5[2]
1000001000PENT_NN5[5]
1000010000OUT[3]
1000100000OUT[6]
virtex5 INT switchbox INT muxes DBL_SS0_N2
BitsDestination
MAIN[6][4]MAIN[9][4]MAIN[9][3]MAIN[6][3]MAIN[13][5]MAIN[13][2]MAIN[13][4]MAIN[6][2]MAIN[10][5]MAIN[10][2]DBL_SS0_N2
Source
0000000000off
0001000001DBL_WW1[0]
0001000010DBL_WW1[3]
0001000100PENT_WW3[0]
0001001000PENT_WW3[3]
0001010000OUT_N15_DBL
0001100000OUT_N17_DBL
0010000001DBL_WW2[0]
0010000010DBL_WW2[3]
0010000100PENT_WW5[0]
0010001000PENT_WW5[3]
0010010000OUT[18]
0010100000OUT[12]
0100000001DBL_WS2[0]
0100000010DBL_SW2[0]
0100000100PENT_WS5[0]
0100001000PENT_SW5[0]
0100010000OUT[22]
0100100000OUT[8]
1000000001DBL_WN1[0]
1000000010DBL_SE1[0]
1000000100PENT_WN3[0]
1000001000PENT_SE3[0]
1000010000OUT[0]
1000100000OUT[5]
virtex5 INT switchbox INT muxes DBL_SS0[0]
BitsDestination
MAIN[9][26]MAIN[8][26]MAIN[9][24]MAIN[8][24]MAIN[12][26]MAIN[12][24]MAIN[6][24]MAIN[7][26]MAIN[11][26]MAIN[11][24]DBL_SS0[0]
Source
0000000000off
0001000001DBL_WW1[1]
0001000010DBL_WW1[4]
0001000100PENT_WW3[1]
0001001000PENT_WW3[4]
0001010000OUT[1]
0001100000OUT[4]
0010000001DBL_WW2[1]
0010000010DBL_WW2[4]
0010000100PENT_WW5[1]
0010001000PENT_WW5[4]
0010010000OUT[23]
0010100000OUT[9]
0100000001DBL_WS2[1]
0100000010DBL_SW2[1]
0100000100PENT_WS5[1]
0100001000PENT_SW5[1]
0100010000OUT[19]
0100100000OUT[13]
1000000001DBL_WN1[1]
1000000010DBL_SE1[1]
1000000100PENT_WN3[1]
1000001000PENT_SE3[1]
1000010000OUT[14]
1000100000OUT[16]
virtex5 INT switchbox INT muxes DBL_SS0[1]
BitsDestination
MAIN[8][47]MAIN[9][47]MAIN[8][45]MAIN[7][45]MAIN[12][46]MAIN[12][47]MAIN[12][45]MAIN[7][47]MAIN[11][45]MAIN[11][47]DBL_SS0[1]
Source
0000000000off
0001000001DBL_WW1[2]
0001000010DBL_WW1[5]
0001000100PENT_WW3[2]
0001001000PENT_WW3[5]
0001010000OUT[20]
0001100000OUT[10]
0010000001DBL_WW2[2]
0010000010DBL_WW2[5]
0010000100PENT_WW5[2]
0010001000PENT_WW5[5]
0010010000OUT[2]
0010100000OUT[7]
0100000001DBL_WS2[2]
0100000010DBL_SW2[2]
0100000100PENT_WS5[2]
0100001000PENT_SW5[2]
0100010000OUT[6]
0100100000OUT[3]
1000000001DBL_WN1[2]
1000000010DBL_SE1[2]
1000000100PENT_WN3[2]
1000001000PENT_SE3[2]
1000010000OUT[11]
1000100000OUT[21]
virtex5 INT switchbox INT muxes DBL_SS0[3]
BitsDestination
MAIN[7][11]MAIN[8][11]MAIN[8][12]MAIN[7][12]MAIN[11][11]MAIN[11][12]MAIN[13][11]MAIN[9][13]MAIN[10][11]MAIN[10][12]DBL_SS0[3]
Source
0000000000off
0001000001DBL_EE1[0]
0001000010DBL_EE1[3]
0001000100PENT_EE3[0]
0001001000PENT_EE3[3]
0001010000OUT[0]
0001100000OUT[5]
0010000001DBL_EE2[0]
0010000010DBL_EE2[3]
0010000100PENT_EE5[0]
0010001000PENT_EE5[3]
0010010000OUT[22]
0010100000OUT[8]
0100000001DBL_SE2[0]
0100000010DBL_ES2[0]
0100000100PENT_SE5[0]
0100001000PENT_ES5[0]
0100010000OUT[9]
0100100000OUT[23]
1000000001DBL_SW1[0]
1000000010DBL_EN1[0]
1000000100PENT_SW3[0]
1000001000PENT_EN3[0]
1000010000OUT[4]
1000100000OUT[1]
virtex5 INT switchbox INT muxes DBL_SS0[4]
BitsDestination
MAIN[9][33]MAIN[6][33]MAIN[8][33]MAIN[7][33]MAIN[11][33]MAIN[12][33]MAIN[13][33]MAIN[7][32]MAIN[10][32]MAIN[10][33]DBL_SS0[4]
Source
0000000000off
0001000001DBL_EE1[1]
0001000010DBL_EE1[4]
0001000100PENT_EE3[1]
0001001000PENT_EE3[4]
0001010000OUT[16]
0001100000OUT[14]
0010000001DBL_EE2[1]
0010000010DBL_EE2[4]
0010000100PENT_EE5[1]
0010001000PENT_EE5[4]
0010010000OUT[13]
0010100000OUT[19]
0100000001DBL_SE2[1]
0100000010DBL_ES2[1]
0100000100PENT_SE5[1]
0100001000PENT_ES5[1]
0100010000OUT[2]
0100100000OUT[7]
1000000001DBL_SW1[1]
1000000010DBL_EN1[1]
1000000100PENT_SW3[1]
1000001000PENT_EN3[1]
1000010000OUT[20]
1000100000OUT[10]
virtex5 INT switchbox INT muxes DBL_SS0[5]
BitsDestination
MAIN[7][54]MAIN[8][54]MAIN[9][54]MAIN[6][54]MAIN[13][54]MAIN[10][54]MAIN[6][55]MAIN[6][53]MAIN[10][55]MAIN[11][54]DBL_SS0[5]
Source
0000000000off
0001000001DBL_EE1[2]
0001000010DBL_EE1[5]
0001000100PENT_EE3[2]
0001001000PENT_EE3[5]
0001010000OUT[21]
0001100000OUT[11]
0010000001DBL_EE2[2]
0010000010DBL_EE2[5]
0010000100PENT_EE5[2]
0010001000PENT_EE5[5]
0010010000OUT[3]
0010100000OUT[6]
0100000001DBL_SE2[2]
0100000010DBL_ES2[2]
0100000100PENT_SE5[2]
0100001000PENT_ES5[2]
0100010000OUT_S12_DBL
0100100000OUT_S18_DBL
1000000001DBL_SW1[2]
1000000010DBL_EN1[2]
1000000100PENT_SW3[2]
1000001000PENT_EN3[2]
1000010000OUT[17]
1000100000OUT[15]
virtex5 INT switchbox INT muxes DBL_SW0[0]
BitsDestination
MAIN[9][7]MAIN[8][7]MAIN[7][5]MAIN[8][5]MAIN[12][6]MAIN[12][7]MAIN[12][5]MAIN[7][7]MAIN[11][5]MAIN[11][7]DBL_SW0[0]
Source
0000000000off
0001000001DBL_WS2[0]
0001000010DBL_SW2[0]
0001000100PENT_WS5[0]
0001001000PENT_SW5[0]
0001010000OUT[18]
0001100000OUT[12]
0010000001DBL_WN1[0]
0010000010DBL_SE1[0]
0010000100PENT_WN3[0]
0010001000PENT_SE3[0]
0010010000OUT_N15_DBL
0010100000OUT_N17_DBL
0100000001DBL_SS1[0]
0100000010DBL_SS1[3]
0100000100PENT_SS3[0]
0100001000PENT_SS3[3]
0100010000OUT[0]
0100100000OUT[5]
1000000001DBL_SS2[0]
1000000010DBL_SS2[3]
1000000100PENT_SS5[0]
1000001000PENT_SS5[3]
1000010000OUT[22]
1000100000OUT[8]
virtex5 INT switchbox INT muxes DBL_SW0[1]
BitsDestination
MAIN[9][28]MAIN[6][28]MAIN[6][27]MAIN[9][27]MAIN[13][26]MAIN[13][29]MAIN[13][28]MAIN[6][26]MAIN[10][29]MAIN[10][26]DBL_SW0[1]
Source
0000000000off
0001000001DBL_WS2[1]
0001000010DBL_SW2[1]
0001000100PENT_WS5[1]
0001001000PENT_SW5[1]
0001010000OUT[23]
0001100000OUT[9]
0010000001DBL_WN1[1]
0010000010DBL_SE1[1]
0010000100PENT_WN3[1]
0010001000PENT_SE3[1]
0010010000OUT[1]
0010100000OUT[4]
0100000001DBL_SS1[1]
0100000010DBL_SS1[4]
0100000100PENT_SS3[1]
0100001000PENT_SS3[4]
0100010000OUT[14]
0100100000OUT[16]
1000000001DBL_SS2[1]
1000000010DBL_SS2[4]
1000000100PENT_SS5[1]
1000001000PENT_SS5[4]
1000010000OUT[19]
1000100000OUT[13]
virtex5 INT switchbox INT muxes DBL_SW0[2]
BitsDestination
MAIN[8][50]MAIN[9][50]MAIN[8][48]MAIN[9][48]MAIN[12][48]MAIN[12][50]MAIN[6][48]MAIN[7][50]MAIN[11][50]MAIN[11][48]DBL_SW0[2]
Source
0000000000off
0001000001DBL_WS2[2]
0001000010DBL_SW2[2]
0001000100PENT_WS5[2]
0001001000PENT_SW5[2]
0001010000OUT[2]
0001100000OUT[7]
0010000001DBL_WN1[2]
0010000010DBL_SE1[2]
0010000100PENT_WN3[2]
0010001000PENT_SE3[2]
0010010000OUT[20]
0010100000OUT[10]
0100000001DBL_SS1[2]
0100000010DBL_SS1[5]
0100000100PENT_SS3[2]
0100001000PENT_SS3[5]
0100010000OUT[11]
0100100000OUT[21]
1000000001DBL_SS2[2]
1000000010DBL_SS2[5]
1000000100PENT_SS5[2]
1000001000PENT_SS5[5]
1000010000OUT[6]
1000100000OUT[3]
virtex5 INT switchbox INT muxes DBL_SE0[0]
BitsDestination
MAIN[6][9]MAIN[9][9]MAIN[7][9]MAIN[8][9]MAIN[11][9]MAIN[12][9]MAIN[7][8]MAIN[13][9]MAIN[10][9]MAIN[10][8]DBL_SE0[0]
Source
0000000000off
0001000001DBL_ES2[0]
0001000010DBL_SE2[0]
0001000100PENT_ES5[0]
0001001000PENT_SE5[0]
0001010000OUT[22]
0001100000OUT[8]
0010000001DBL_EN1[0]
0010000010DBL_SW1[0]
0010000100PENT_EN3[0]
0010001000PENT_SW3[0]
0010010000OUT[0]
0010100000OUT[5]
0100000001DBL_SS1[3]
0100000010DBL_SS1[0]
0100000100PENT_SS3[3]
0100001000PENT_SS3[0]
0100010000OUT_N15_DBL
0100100000OUT_N17_DBL
1000000001DBL_SS2[3]
1000000010DBL_SS2[0]
1000000100PENT_SS5[3]
1000001000PENT_SS5[0]
1000010000OUT[18]
1000100000OUT[12]
virtex5 INT switchbox INT muxes DBL_SE0[1]
BitsDestination
MAIN[8][30]MAIN[7][30]MAIN[6][30]MAIN[9][30]MAIN[13][30]MAIN[10][30]MAIN[6][29]MAIN[6][31]MAIN[11][30]MAIN[10][31]DBL_SE0[1]
Source
0000000000off
0001000001DBL_ES2[1]
0001000010DBL_SE2[1]
0001000100PENT_ES5[1]
0001001000PENT_SE5[1]
0001010000OUT[19]
0001100000OUT[13]
0010000001DBL_EN1[1]
0010000010DBL_SW1[1]
0010000100PENT_EN3[1]
0010001000PENT_SW3[1]
0010010000OUT[14]
0010100000OUT[16]
0100000001DBL_SS1[4]
0100000010DBL_SS1[1]
0100000100PENT_SS3[4]
0100001000PENT_SS3[1]
0100010000OUT[1]
0100100000OUT[4]
1000000001DBL_SS2[4]
1000000010DBL_SS2[1]
1000000100PENT_SS5[4]
1000001000PENT_SS5[1]
1000010000OUT[23]
1000100000OUT[9]
virtex5 INT switchbox INT muxes DBL_SE0[2]
BitsDestination
MAIN[8][51]MAIN[7][51]MAIN[7][52]MAIN[8][52]MAIN[11][51]MAIN[11][52]MAIN[9][53]MAIN[13][51]MAIN[10][52]MAIN[10][51]DBL_SE0[2]
Source
0000000000off
0001000001DBL_ES2[2]
0001000010DBL_SE2[2]
0001000100PENT_ES5[2]
0001001000PENT_SE5[2]
0001010000OUT[6]
0001100000OUT[3]
0010000001DBL_EN1[2]
0010000010DBL_SW1[2]
0010000100PENT_EN3[2]
0010001000PENT_SW3[2]
0010010000OUT[11]
0010100000OUT[21]
0100000001DBL_SS1[5]
0100000010DBL_SS1[2]
0100000100PENT_SS3[5]
0100001000PENT_SS3[2]
0100010000OUT[20]
0100100000OUT[10]
1000000001DBL_SS2[5]
1000000010DBL_SS2[2]
1000000100PENT_SS5[5]
1000001000PENT_SS5[2]
1000010000OUT[2]
1000100000OUT[7]
virtex5 INT switchbox INT muxes PENT_WW0_S0
BitsDestination
MAIN[5][61]MAIN[1][61]MAIN[4][63]MAIN[5][63]MAIN[2][63]MAIN[3][62]MAIN[0][63]MAIN[1][63]PENT_WW0_S0
Source
00000000off
00010001PENT_WS3_S0
00010010PENT_NE3[2]
00010100OUT[6]
00011000OUT[11]
00100001PENT_WN5_S0
00100010PENT_NW5[2]
00100100OUT_S12_PENT
00101000OUT[15]
01000001PENT_NN3[2]
01000010PENT_NN3[5]
01000100LH[0]
01001000OUT_S18_PENT
10000001PENT_NN5[2]
10000010PENT_NN5[5]
10000100OUT[3]
10001000OUT[21]
virtex5 INT switchbox INT muxes PENT_WW0[1]
BitsDestination
MAIN[4][19]MAIN[0][19]MAIN[4][20]MAIN[4][21]MAIN[3][21]MAIN[3][18]MAIN[0][18]MAIN[1][20]PENT_WW0[1]
Source
00000000off
00010001PENT_WS3[1]
00010010PENT_NE3[0]
00010100OUT[5]
00011000OUT[8]
00100001PENT_WN5[1]
00100010PENT_NW5[0]
00100100OUT[4]
00101000OUT[9]
01000001PENT_NN3[0]
01000010PENT_NN3[3]
01000100LV[12]
01001000LV[18]
10000001PENT_NN5[0]
10000010PENT_NN5[3]
10000100OUT[0]
10001000OUT[1]
virtex5 INT switchbox INT muxes PENT_WW0[2]
BitsDestination
MAIN[4][40]MAIN[5][40]MAIN[5][42]MAIN[4][42]MAIN[2][40]MAIN[3][41]MAIN[1][42]MAIN[1][40]PENT_WW0[2]
Source
00000000off
00010001PENT_WS3[2]
00010010PENT_NE3[1]
00010100OUT[13]
00011000OUT[14]
00100001PENT_WN5[2]
00100010PENT_NW5[1]
00100100OUT[10]
00101000OUT[7]
01000001PENT_NN3[1]
01000010PENT_NN3[4]
01000100LH[6]
01001000OUT[19]
10000001PENT_NN5[1]
10000010PENT_NN5[4]
10000100OUT[20]
10001000OUT[2]
virtex5 INT switchbox INT muxes PENT_WW0[3]
BitsDestination
MAIN[4][6]MAIN[0][6]MAIN[1][6]MAIN[5][6]MAIN[3][7]MAIN[2][5]MAIN[2][6]MAIN[0][5]PENT_WW0[3]
Source
00000000off
00010001PENT_WS5[0]
00010010PENT_SW5[0]
00010100OUT[0]
00011000OUT[22]
00100001PENT_WN3[0]
00100010PENT_SE3[0]
00100100LH[18]
00101000OUT_N17_PENT
01000001PENT_SS3[0]
01000010PENT_SS3[3]
01000100OUT[5]
01001000OUT[8]
10000001PENT_SS5[0]
10000010PENT_SS5[3]
10000100OUT[12]
10001000OUT_N15_PENT
virtex5 INT switchbox INT muxes PENT_WW0[4]
BitsDestination
MAIN[5][28]MAIN[2][28]MAIN[1][27]MAIN[5][27]MAIN[3][27]MAIN[3][28]MAIN[2][27]MAIN[0][28]PENT_WW0[4]
Source
00000000off
00010001PENT_WS5[1]
00010010PENT_SW5[1]
00010100OUT[23]
00011000OUT[1]
00100001PENT_WN3[1]
00100010PENT_SE3[1]
00100100LH[12]
00101000OUT[16]
01000001PENT_SS3[1]
01000010PENT_SS3[4]
01000100OUT[13]
01001000OUT[14]
10000001PENT_SS5[1]
10000010PENT_SS5[4]
10000100OUT[4]
10001000OUT[9]
virtex5 INT switchbox INT muxes PENT_WW0[5]
BitsDestination
MAIN[1][49]MAIN[5][49]MAIN[4][49]MAIN[0][49]MAIN[3][48]MAIN[2][50]MAIN[2][49]MAIN[0][48]PENT_WW0[5]
Source
00000000off
00010001PENT_WS5[2]
00010010PENT_SW5[2]
00010100OUT[3]
00011000OUT[2]
00100001PENT_WN3[2]
00100010PENT_SE3[2]
00100100LV[0]
00101000LV[6]
01000001PENT_SS3[2]
01000010PENT_SS3[5]
01000100OUT[6]
01001000OUT[11]
10000001PENT_SS5[2]
10000010PENT_SS5[5]
10000100OUT[10]
10001000OUT[7]
virtex5 INT switchbox INT muxes PENT_WS0[0]
BitsDestination
MAIN[3][3]MAIN[3][4]MAIN[2][3]MAIN[0][4]MAIN[2][4]MAIN[5][4]MAIN[5][3]MAIN[1][3]PENT_WS0[0]
Source
00000000off
00010001PENT_WW3[0]
00010010PENT_WW5[0]
00010100PENT_WS5[0]
00011000PENT_WN3[0]
00100001PENT_WW3[3]
00100010PENT_WW5[3]
00100100PENT_SW5[0]
00101000PENT_SE3[0]
01000001LH[18]
01000010OUT[0]
01000100OUT[12]
01001000OUT[5]
10000001OUT_N17_PENT
10000010OUT[22]
10000100OUT_N15_PENT
10001000OUT[8]
virtex5 INT switchbox INT muxes PENT_WS0[1]
BitsDestination
MAIN[3][24]MAIN[2][26]MAIN[2][25]MAIN[0][24]MAIN[5][25]MAIN[1][25]MAIN[0][25]MAIN[4][25]PENT_WS0[1]
Source
00000000off
00010001PENT_WW3[1]
00010010PENT_WW5[1]
00010100PENT_WS5[1]
00011000PENT_WN3[1]
00100001PENT_WW3[4]
00100010PENT_WW5[4]
00100100PENT_SW5[1]
00101000PENT_SE3[1]
01000001LH[12]
01000010OUT[23]
01000100OUT[4]
01001000OUT[13]
10000001OUT[16]
10000010OUT[1]
10000100OUT[9]
10001000OUT[14]
virtex5 INT switchbox INT muxes PENT_WS0[2]
BitsDestination
MAIN[3][47]MAIN[2][45]MAIN[2][46]MAIN[0][45]MAIN[0][46]MAIN[4][46]MAIN[5][46]MAIN[1][46]PENT_WS0[2]
Source
00000000off
00010001PENT_WW3[2]
00010010PENT_WW5[2]
00010100PENT_WS5[2]
00011000PENT_WN3[2]
00100001PENT_WW3[5]
00100010PENT_WW5[5]
00100100PENT_SW5[2]
00101000PENT_SE3[2]
01000001LV[0]
01000010OUT[3]
01000100OUT[10]
01001000OUT[6]
10000001LV[6]
10000010OUT[2]
10000100OUT[7]
10001000OUT[11]
virtex5 INT switchbox INT muxes PENT_WN0[0]
BitsDestination
MAIN[2][0]MAIN[3][1]MAIN[1][0]MAIN[1][2]MAIN[4][0]MAIN[5][0]MAIN[5][2]MAIN[4][2]PENT_WN0[0]
Source
00000000off
00010001PENT_WW3[0]
00010010PENT_WW5[0]
00010100PENT_NE3_N2
00011000PENT_NW5_N2
00100001PENT_WW3[3]
00100010PENT_WW5[3]
00100100PENT_WS3[0]
00101000PENT_WN5[0]
01000001OUT[5]
01000010OUT[12]
01000100LH[18]
01001000OUT[0]
10000001OUT[8]
10000010OUT_N15_PENT
10000100OUT_N17_PENT
10001000OUT[22]
virtex5 INT switchbox INT muxes PENT_WN0[1]
BitsDestination
MAIN[2][23]MAIN[3][22]MAIN[1][23]MAIN[0][23]MAIN[5][21]MAIN[1][21]MAIN[4][23]MAIN[5][23]PENT_WN0[1]
Source
00000000off
00010001PENT_WW3[1]
00010010PENT_WW5[1]
00010100PENT_NE3[0]
00011000PENT_NW5[0]
00100001PENT_WW3[4]
00100010PENT_WW5[4]
00100100PENT_WS3[1]
00101000PENT_WN5[1]
01000001OUT[13]
01000010OUT[4]
01000100LH[12]
01001000OUT[23]
10000001OUT[14]
10000010OUT[9]
10000100OUT[16]
10001000OUT[1]
virtex5 INT switchbox INT muxes PENT_WN0[2]
BitsDestination
MAIN[3][45]MAIN[3][42]MAIN[1][44]MAIN[0][42]MAIN[4][43]MAIN[0][43]MAIN[4][44]MAIN[4][45]PENT_WN0[2]
Source
00000000off
00010001PENT_WW3[2]
00010010PENT_WW5[2]
00010100PENT_NE3[1]
00011000PENT_NW5[1]
00100001PENT_WW3[5]
00100010PENT_WW5[5]
00100100PENT_WS3[2]
00101000PENT_WN5[2]
01000001OUT[6]
01000010OUT[10]
01000100LV[0]
01001000OUT[3]
10000001OUT[11]
10000010OUT[7]
10000100LV[6]
10001000OUT[2]
virtex5 INT switchbox INT muxes PENT_EE0[0]
BitsDestination
MAIN[4][8]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[2][8]MAIN[3][9]MAIN[1][10]MAIN[1][8]PENT_EE0[0]
Source
00000000off
00010001PENT_ES5[0]
00010010PENT_SE5[0]
00010100OUT[12]
00011000OUT_N15_PENT
00100001PENT_EN3[0]
00100010PENT_SW3[0]
00100100OUT[5]
00101000OUT[8]
01000001PENT_SS3[3]
01000010PENT_SS3[0]
01000100LH[18]
01001000OUT_N17_PENT
10000001PENT_SS5[3]
10000010PENT_SS5[0]
10000100OUT[0]
10001000OUT[22]
virtex5 INT switchbox INT muxes PENT_EE0[1]
BitsDestination
MAIN[5][29]MAIN[1][29]MAIN[5][31]MAIN[4][31]MAIN[2][31]MAIN[3][30]MAIN[0][31]MAIN[1][31]PENT_EE0[1]
Source
00000000off
00010001PENT_ES5[1]
00010010PENT_SE5[1]
00010100OUT[4]
00011000OUT[9]
00100001PENT_EN3[1]
00100010PENT_SW3[1]
00100100OUT[13]
00101000OUT[14]
01000001PENT_SS3[4]
01000010PENT_SS3[1]
01000100LH[12]
01001000OUT[16]
10000001PENT_SS5[4]
10000010PENT_SS5[1]
10000100OUT[23]
10001000OUT[1]
virtex5 INT switchbox INT muxes PENT_EE0[2]
BitsDestination
MAIN[4][51]MAIN[0][51]MAIN[4][53]MAIN[4][52]MAIN[3][53]MAIN[3][50]MAIN[0][50]MAIN[1][52]PENT_EE0[2]
Source
00000000off
00010001PENT_ES5[2]
00010010PENT_SE5[2]
00010100OUT[10]
00011000OUT[7]
00100001PENT_EN3[2]
00100010PENT_SW3[2]
00100100OUT[6]
00101000OUT[11]
01000001PENT_SS3[5]
01000010PENT_SS3[2]
01000100LV[0]
01001000LV[6]
10000001PENT_SS5[5]
10000010PENT_SS5[2]
10000100OUT[3]
10001000OUT[2]
virtex5 INT switchbox INT muxes PENT_EE0[3]
BitsDestination
MAIN[1][17]MAIN[5][17]MAIN[0][17]MAIN[4][17]MAIN[3][16]MAIN[2][18]MAIN[2][17]MAIN[0][16]PENT_EE0[3]
Source
00000000off
00010001PENT_ES3[0]
00010010PENT_NW3[0]
00010100LV[12]
00011000LV[18]
00100001PENT_EN5[0]
00100010PENT_NE5[0]
00100100OUT[0]
00101000OUT[1]
01000001PENT_NN3[3]
01000010PENT_NN3[0]
01000100OUT[5]
01001000OUT[8]
10000001PENT_NN5[3]
10000010PENT_NN5[0]
10000100OUT[4]
10001000OUT[9]
virtex5 INT switchbox INT muxes PENT_EE0[4]
BitsDestination
MAIN[4][38]MAIN[0][38]MAIN[5][38]MAIN[1][38]MAIN[3][39]MAIN[2][37]MAIN[2][38]MAIN[0][37]PENT_EE0[4]
Source
00000000off
00010001PENT_ES3[1]
00010010PENT_NW3[1]
00010100LH[6]
00011000OUT[19]
00100001PENT_EN5[1]
00100010PENT_NE5[1]
00100100OUT[20]
00101000OUT[2]
01000001PENT_NN3[4]
01000010PENT_NN3[1]
01000100OUT[13]
01001000OUT[14]
10000001PENT_NN5[4]
10000010PENT_NN5[1]
10000100OUT[10]
10001000OUT[7]
virtex5 INT switchbox INT muxes PENT_EE0[5]
BitsDestination
MAIN[5][60]MAIN[2][60]MAIN[5][59]MAIN[1][59]MAIN[3][59]MAIN[3][60]MAIN[2][59]MAIN[0][60]PENT_EE0[5]
Source
00000000off
00010001PENT_ES3[2]
00010010PENT_NW3[2]
00010100LH[0]
00011000OUT_S18_PENT
00100001PENT_EN5[2]
00100010PENT_NE5[2]
00100100OUT[3]
00101000OUT[21]
01000001PENT_NN3[5]
01000010PENT_NN3[2]
01000100OUT[6]
01001000OUT[11]
10000001PENT_NN5[5]
10000010PENT_NN5[2]
10000100OUT_S12_PENT
10001000OUT[15]
virtex5 INT switchbox INT muxes PENT_ES0[0]
BitsDestination
MAIN[3][13]MAIN[3][10]MAIN[1][12]MAIN[0][10]MAIN[0][11]MAIN[4][11]MAIN[4][12]MAIN[4][13]PENT_ES0[0]
Source
00000000off
00010001PENT_EE3[0]
00010010PENT_EE5[0]
00010100PENT_SE5[0]
00011000PENT_SW3[0]
00100001PENT_EE3[3]
00100010PENT_EE5[3]
00100100PENT_ES5[0]
00101000PENT_EN3[0]
01000001OUT[5]
01000010OUT[4]
01000100OUT[0]
01001000LV[12]
10000001OUT[8]
10000010OUT[9]
10000100OUT[1]
10001000LV[18]
virtex5 INT switchbox INT muxes PENT_ES0[1]
BitsDestination
MAIN[2][32]MAIN[3][33]MAIN[1][32]MAIN[1][34]MAIN[5][32]MAIN[4][32]MAIN[5][34]MAIN[4][34]PENT_ES0[1]
Source
00000000off
00010001PENT_EE3[1]
00010010PENT_EE5[1]
00010100PENT_SE5[1]
00011000PENT_SW3[1]
00100001PENT_EE3[4]
00100010PENT_EE5[4]
00100100PENT_ES5[1]
00101000PENT_EN3[1]
01000001OUT[13]
01000010OUT[10]
01000100OUT[20]
01001000LH[6]
10000001OUT[14]
10000010OUT[7]
10000100OUT[2]
10001000OUT[19]
virtex5 INT switchbox INT muxes PENT_ES0[2]
BitsDestination
MAIN[2][55]MAIN[3][54]MAIN[1][55]MAIN[0][55]MAIN[1][53]MAIN[5][53]MAIN[4][55]MAIN[5][55]PENT_ES0[2]
Source
00000000off
00010001PENT_EE3[2]
00010010PENT_EE5[2]
00010100PENT_SE5[2]
00011000PENT_SW3[2]
00100001PENT_EE3[5]
00100010PENT_EE5[5]
00100100PENT_ES5[2]
00101000PENT_EN3[2]
01000001OUT[6]
01000010OUT_S12_PENT
01000100OUT[3]
01001000LH[0]
10000001OUT[11]
10000010OUT[15]
10000100OUT[21]
10001000OUT_S18_PENT
virtex5 INT switchbox INT muxes PENT_EN0[0]
BitsDestination
MAIN[3][15]MAIN[2][13]MAIN[2][14]MAIN[0][13]MAIN[4][14]MAIN[0][14]MAIN[5][14]MAIN[1][14]PENT_EN0[0]
Source
00000000off
00010001PENT_EE3[0]
00010010PENT_EE5[0]
00010100PENT_ES3[0]
00011000PENT_EN5[0]
00100001PENT_EE3[3]
00100010PENT_EE5[3]
00100100PENT_NW3[0]
00101000PENT_NE5[0]
01000001LV[12]
01000010OUT[0]
01000100OUT[5]
01001000OUT[4]
10000001LV[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[9]
virtex5 INT switchbox INT muxes PENT_EN0[1]
BitsDestination
MAIN[3][35]MAIN[3][36]MAIN[2][35]MAIN[0][36]MAIN[5][36]MAIN[2][36]MAIN[5][35]MAIN[1][35]PENT_EN0[1]
Source
00000000off
00010001PENT_EE3[1]
00010010PENT_EE5[1]
00010100PENT_ES3[1]
00011000PENT_EN5[1]
00100001PENT_EE3[4]
00100010PENT_EE5[4]
00100100PENT_NW3[1]
00101000PENT_NE5[1]
01000001LH[6]
01000010OUT[20]
01000100OUT[13]
01001000OUT[10]
10000001OUT[19]
10000010OUT[2]
10000100OUT[14]
10001000OUT[7]
virtex5 INT switchbox INT muxes PENT_EN0[2]
BitsDestination
MAIN[3][56]MAIN[2][58]MAIN[2][57]MAIN[0][56]MAIN[1][57]MAIN[5][57]MAIN[0][57]MAIN[4][57]PENT_EN0[2]
Source
00000000off
00010001PENT_EE3[2]
00010010PENT_EE5[2]
00010100PENT_ES3[2]
00011000PENT_EN5[2]
00100001PENT_EE3[5]
00100010PENT_EE5[5]
00100100PENT_NW3[2]
00101000PENT_NE5[2]
01000001LH[0]
01000010OUT[3]
01000100OUT[6]
01001000OUT_S12_PENT
10000001OUT_S18_PENT
10000010OUT[21]
10000100OUT[11]
10001000OUT[15]
virtex5 INT switchbox INT muxes PENT_SS0[0]
BitsDestination
MAIN[3][5]MAIN[3][2]MAIN[1][4]MAIN[0][2]MAIN[4][5]MAIN[4][4]MAIN[4][3]MAIN[0][3]PENT_SS0[0]
Source
00000000off
00010001PENT_WW3[0]
00010010PENT_WW5[0]
00010100PENT_WS5[0]
00011000PENT_WN3[0]
00100001PENT_WW3[3]
00100010PENT_WW5[3]
00100100PENT_SW5[0]
00101000PENT_SE3[0]
01000001LH[18]
01000010OUT[0]
01000100OUT[12]
01001000OUT[5]
10000001OUT_N17_PENT
10000010OUT[22]
10000100OUT_N15_PENT
10001000OUT[8]
virtex5 INT switchbox INT muxes PENT_SS0[1]
BitsDestination
MAIN[2][24]MAIN[3][25]MAIN[1][24]MAIN[1][26]MAIN[4][26]MAIN[5][26]MAIN[4][24]MAIN[5][24]PENT_SS0[1]
Source
00000000off
00010001PENT_WW3[1]
00010010PENT_WW5[1]
00010100PENT_WS5[1]
00011000PENT_WN3[1]
00100001PENT_WW3[4]
00100010PENT_WW5[4]
00100100PENT_SW5[1]
00101000PENT_SE3[1]
01000001LH[12]
01000010OUT[23]
01000100OUT[4]
01001000OUT[13]
10000001OUT[16]
10000010OUT[1]
10000100OUT[9]
10001000OUT[14]
virtex5 INT switchbox INT muxes PENT_SS0[2]
BitsDestination
MAIN[2][47]MAIN[3][46]MAIN[1][47]MAIN[0][47]MAIN[5][47]MAIN[4][47]MAIN[5][45]MAIN[1][45]PENT_SS0[2]
Source
00000000off
00010001PENT_WW3[2]
00010010PENT_WW5[2]
00010100PENT_WS5[2]
00011000PENT_WN3[2]
00100001PENT_WW3[5]
00100010PENT_WW5[5]
00100100PENT_SW5[2]
00101000PENT_SE3[2]
01000001LV[0]
01000010OUT[3]
01000100OUT[10]
01001000OUT[6]
10000001LV[6]
10000010OUT[2]
10000100OUT[7]
10001000OUT[11]
virtex5 INT switchbox INT muxes PENT_SS0[3]
BitsDestination
MAIN[3][11]MAIN[3][12]MAIN[2][11]MAIN[0][12]MAIN[1][11]MAIN[5][11]MAIN[5][12]MAIN[2][12]PENT_SS0[3]
Source
00000000off
00010001PENT_EE3[0]
00010010PENT_EE5[0]
00010100PENT_SE5[0]
00011000PENT_SW3[0]
00100001PENT_EE3[3]
00100010PENT_EE5[3]
00100100PENT_ES5[0]
00101000PENT_EN3[0]
01000001OUT[5]
01000010OUT[4]
01000100OUT[0]
01001000LV[12]
10000001OUT[8]
10000010OUT[9]
10000100OUT[1]
10001000LV[18]
virtex5 INT switchbox INT muxes PENT_SS0[4]
BitsDestination
MAIN[3][32]MAIN[2][34]MAIN[2][33]MAIN[0][32]MAIN[4][33]MAIN[0][33]MAIN[1][33]MAIN[5][33]PENT_SS0[4]
Source
00000000off
00010001PENT_EE3[1]
00010010PENT_EE5[1]
00010100PENT_SE5[1]
00011000PENT_SW3[1]
00100001PENT_EE3[4]
00100010PENT_EE5[4]
00100100PENT_ES5[1]
00101000PENT_EN3[1]
01000001OUT[13]
01000010OUT[10]
01000100OUT[20]
01001000LH[6]
10000001OUT[14]
10000010OUT[7]
10000100OUT[2]
10001000OUT[19]
virtex5 INT switchbox INT muxes PENT_SS0[5]
BitsDestination
MAIN[3][55]MAIN[2][53]MAIN[2][54]MAIN[0][53]MAIN[1][54]MAIN[5][54]MAIN[4][54]MAIN[0][54]PENT_SS0[5]
Source
00000000off
00010001PENT_EE3[2]
00010010PENT_EE5[2]
00010100PENT_SE5[2]
00011000PENT_SW3[2]
00100001PENT_EE3[5]
00100010PENT_EE5[5]
00100100PENT_ES5[2]
00101000PENT_EN3[2]
01000001OUT[6]
01000010OUT_S12_PENT
01000100OUT[3]
01001000LH[0]
10000001OUT[11]
10000010OUT[15]
10000100OUT[21]
10001000OUT_S18_PENT
virtex5 INT switchbox INT muxes PENT_SW0[0]
BitsDestination
MAIN[4][7]MAIN[5][7]MAIN[1][5]MAIN[5][5]MAIN[2][7]MAIN[3][6]MAIN[1][7]MAIN[0][7]PENT_SW0[0]
Source
00000000off
00010001PENT_WS5[0]
00010010PENT_SW5[0]
00010100OUT[0]
00011000OUT[22]
00100001PENT_WN3[0]
00100010PENT_SE3[0]
00100100LH[18]
00101000OUT_N17_PENT
01000001PENT_SS3[0]
01000010PENT_SS3[3]
01000100OUT[5]
01001000OUT[8]
10000001PENT_SS5[0]
10000010PENT_SS5[3]
10000100OUT[12]
10001000OUT_N15_PENT
virtex5 INT switchbox INT muxes PENT_SW0[1]
BitsDestination
MAIN[4][28]MAIN[4][29]MAIN[0][27]MAIN[4][27]MAIN[3][29]MAIN[3][26]MAIN[1][28]MAIN[0][26]PENT_SW0[1]
Source
00000000off
00010001PENT_WS5[1]
00010010PENT_SW5[1]
00010100OUT[23]
00011000OUT[1]
00100001PENT_WN3[1]
00100010PENT_SE3[1]
00100100LH[12]
00101000OUT[16]
01000001PENT_SS3[1]
01000010PENT_SS3[4]
01000100OUT[13]
01001000OUT[14]
10000001PENT_SS5[1]
10000010PENT_SS5[4]
10000100OUT[4]
10001000OUT[9]
virtex5 INT switchbox INT muxes PENT_SW0[2]
BitsDestination
MAIN[5][50]MAIN[4][50]MAIN[5][48]MAIN[4][48]MAIN[2][48]MAIN[3][49]MAIN[1][48]MAIN[1][50]PENT_SW0[2]
Source
00000000off
00010001PENT_WS5[2]
00010010PENT_SW5[2]
00010100OUT[3]
00011000OUT[2]
00100001PENT_WN3[2]
00100010PENT_SE3[2]
00100100LV[0]
00101000LV[6]
01000001PENT_SS3[2]
01000010PENT_SS3[5]
01000100OUT[6]
01001000OUT[11]
10000001PENT_SS5[2]
10000010PENT_SS5[5]
10000100OUT[10]
10001000OUT[7]
virtex5 INT switchbox INT muxes PENT_SE0[0]
BitsDestination
MAIN[0][9]MAIN[4][9]MAIN[5][9]MAIN[1][9]MAIN[3][8]MAIN[2][10]MAIN[0][8]MAIN[2][9]PENT_SE0[0]
Source
00000000off
00010001PENT_ES5[0]
00010010PENT_SE5[0]
00010100OUT[12]
00011000OUT_N15_PENT
00100001PENT_EN3[0]
00100010PENT_SW3[0]
00100100OUT[5]
00101000OUT[8]
01000001PENT_SS3[3]
01000010PENT_SS3[0]
01000100LH[18]
01001000OUT_N17_PENT
10000001PENT_SS5[3]
10000010PENT_SS5[0]
10000100OUT[0]
10001000OUT[22]
virtex5 INT switchbox INT muxes PENT_SE0[1]
BitsDestination
MAIN[5][30]MAIN[1][30]MAIN[0][30]MAIN[4][30]MAIN[3][31]MAIN[2][29]MAIN[0][29]MAIN[2][30]PENT_SE0[1]
Source
00000000off
00010001PENT_ES5[1]
00010010PENT_SE5[1]
00010100OUT[4]
00011000OUT[9]
00100001PENT_EN3[1]
00100010PENT_SW3[1]
00100100OUT[13]
00101000OUT[14]
01000001PENT_SS3[4]
01000010PENT_SS3[1]
01000100LH[12]
01001000OUT[16]
10000001PENT_SS5[4]
10000010PENT_SS5[1]
10000100OUT[23]
10001000OUT[1]
virtex5 INT switchbox INT muxes PENT_SE0[2]
BitsDestination
MAIN[5][51]MAIN[1][51]MAIN[2][52]MAIN[5][52]MAIN[3][51]MAIN[3][52]MAIN[0][52]MAIN[2][51]PENT_SE0[2]
Source
00000000off
00010001PENT_ES5[2]
00010010PENT_SE5[2]
00010100OUT[10]
00011000OUT[7]
00100001PENT_EN3[2]
00100010PENT_SW3[2]
00100100OUT[6]
00101000OUT[11]
01000001PENT_SS3[5]
01000010PENT_SS3[2]
01000100LV[0]
01001000LV[6]
10000001PENT_SS5[5]
10000010PENT_SS5[2]
10000100OUT[3]
10001000OUT[2]
virtex5 INT switchbox INT muxes PENT_NN0_N5
BitsDestination
MAIN[3][0]MAIN[2][2]MAIN[2][1]MAIN[0][0]MAIN[0][1]MAIN[4][1]MAIN[1][1]MAIN[5][1]PENT_NN0_N5
Source
00000000off
00010001PENT_WW3[0]
00010010PENT_WW5[0]
00010100PENT_NE3_N2
00011000PENT_NW5_N2
00100001PENT_WW3[3]
00100010PENT_WW5[3]
00100100PENT_WS3[0]
00101000PENT_WN5[0]
01000001OUT[5]
01000010OUT[12]
01000100LH[18]
01001000OUT[0]
10000001OUT[8]
10000010OUT_N15_PENT
10000100OUT_N17_PENT
10001000OUT[22]
virtex5 INT switchbox INT muxes PENT_NN0[0]
BitsDestination
MAIN[2][15]MAIN[3][14]MAIN[1][15]MAIN[0][15]MAIN[4][15]MAIN[5][15]MAIN[5][13]MAIN[1][13]PENT_NN0[0]
Source
00000000off
00010001PENT_EE3[0]
00010010PENT_EE5[0]
00010100PENT_ES3[0]
00011000PENT_EN5[0]
00100001PENT_EE3[3]
00100010PENT_EE5[3]
00100100PENT_NW3[0]
00101000PENT_NE5[0]
01000001LV[12]
01000010OUT[0]
01000100OUT[5]
01001000OUT[4]
10000001LV[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[9]
virtex5 INT switchbox INT muxes PENT_NN0[1]
BitsDestination
MAIN[3][37]MAIN[3][34]MAIN[1][36]MAIN[0][34]MAIN[4][36]MAIN[4][37]MAIN[4][35]MAIN[0][35]PENT_NN0[1]
Source
00000000off
00010001PENT_EE3[1]
00010010PENT_EE5[1]
00010100PENT_ES3[1]
00011000PENT_EN5[1]
00100001PENT_EE3[4]
00100010PENT_EE5[4]
00100100PENT_NW3[1]
00101000PENT_NE5[1]
01000001LH[6]
01000010OUT[20]
01000100OUT[13]
01001000OUT[10]
10000001OUT[19]
10000010OUT[2]
10000100OUT[14]
10001000OUT[7]
virtex5 INT switchbox INT muxes PENT_NN0[2]
BitsDestination
MAIN[2][56]MAIN[3][57]MAIN[1][56]MAIN[1][58]MAIN[5][58]MAIN[4][58]MAIN[4][56]MAIN[5][56]PENT_NN0[2]
Source
00000000off
00010001PENT_EE3[2]
00010010PENT_EE5[2]
00010100PENT_ES3[2]
00011000PENT_EN5[2]
00100001PENT_EE3[5]
00100010PENT_EE5[5]
00100100PENT_NW3[2]
00101000PENT_NE5[2]
01000001LH[0]
01000010OUT[3]
01000100OUT[6]
01001000OUT_S12_PENT
10000001OUT_S18_PENT
10000010OUT[21]
10000100OUT[11]
10001000OUT[15]
virtex5 INT switchbox INT muxes PENT_NN0[3]
BitsDestination
MAIN[3][23]MAIN[2][21]MAIN[2][22]MAIN[0][21]MAIN[5][22]MAIN[1][22]MAIN[4][22]MAIN[0][22]PENT_NN0[3]
Source
00000000off
00010001PENT_WW3[1]
00010010PENT_WW5[1]
00010100PENT_NE3[0]
00011000PENT_NW5[0]
00100001PENT_WW3[4]
00100010PENT_WW5[4]
00100100PENT_WS3[1]
00101000PENT_WN5[1]
01000001OUT[13]
01000010OUT[4]
01000100LH[12]
01001000OUT[23]
10000001OUT[14]
10000010OUT[9]
10000100OUT[16]
10001000OUT[1]
virtex5 INT switchbox INT muxes PENT_NN0[4]
BitsDestination
MAIN[3][43]MAIN[3][44]MAIN[2][43]MAIN[0][44]MAIN[5][43]MAIN[1][43]MAIN[5][44]MAIN[2][44]PENT_NN0[4]
Source
00000000off
00010001PENT_WW3[2]
00010010PENT_WW5[2]
00010100PENT_NE3[1]
00011000PENT_NW5[1]
00100001PENT_WW3[5]
00100010PENT_WW5[5]
00100100PENT_WS3[2]
00101000PENT_WN5[2]
01000001OUT[6]
01000010OUT[10]
01000100LV[0]
01001000OUT[3]
10000001OUT[11]
10000010OUT[7]
10000100LV[6]
10001000OUT[2]
virtex5 INT switchbox INT muxes PENT_NW0[0]
BitsDestination
MAIN[5][19]MAIN[1][19]MAIN[5][20]MAIN[2][20]MAIN[3][19]MAIN[3][20]MAIN[0][20]MAIN[2][19]PENT_NW0[0]
Source
00000000off
00010001PENT_WS3[1]
00010010PENT_NE3[0]
00010100OUT[5]
00011000OUT[8]
00100001PENT_WN5[1]
00100010PENT_NW5[0]
00100100OUT[4]
00101000OUT[9]
01000001PENT_NN3[0]
01000010PENT_NN3[3]
01000100LV[12]
01001000LV[18]
10000001PENT_NN5[0]
10000010PENT_NN5[3]
10000100OUT[0]
10001000OUT[1]
virtex5 INT switchbox INT muxes PENT_NW0[1]
BitsDestination
MAIN[0][41]MAIN[4][41]MAIN[1][41]MAIN[5][41]MAIN[3][40]MAIN[2][42]MAIN[0][40]MAIN[2][41]PENT_NW0[1]
Source
00000000off
00010001PENT_WS3[2]
00010010PENT_NE3[1]
00010100OUT[13]
00011000OUT[14]
00100001PENT_WN5[2]
00100010PENT_NW5[1]
00100100OUT[10]
00101000OUT[7]
01000001PENT_NN3[1]
01000010PENT_NN3[4]
01000100LH[6]
01001000OUT[19]
10000001PENT_NN5[1]
10000010PENT_NN5[4]
10000100OUT[20]
10001000OUT[2]
virtex5 INT switchbox INT muxes PENT_NW0[2]
BitsDestination
MAIN[5][62]MAIN[1][62]MAIN[4][62]MAIN[0][62]MAIN[3][63]MAIN[2][61]MAIN[0][61]MAIN[2][62]PENT_NW0[2]
Source
00000000off
00010001PENT_WS3_S0
00010010PENT_NE3[2]
00010100OUT[6]
00011000OUT[11]
00100001PENT_WN5_S0
00100010PENT_NW5[2]
00100100OUT_S12_PENT
00101000OUT[15]
01000001PENT_NN3[2]
01000010PENT_NN3[5]
01000100LH[0]
01001000OUT_S18_PENT
10000001PENT_NN5[2]
10000010PENT_NN5[5]
10000100OUT[3]
10001000OUT[21]
virtex5 INT switchbox INT muxes PENT_NE0[0]
BitsDestination
MAIN[5][18]MAIN[4][18]MAIN[4][16]MAIN[5][16]MAIN[2][16]MAIN[3][17]MAIN[1][16]MAIN[1][18]PENT_NE0[0]
Source
00000000off
00010001PENT_ES3[0]
00010010PENT_NW3[0]
00010100LV[12]
00011000LV[18]
00100001PENT_EN5[0]
00100010PENT_NE5[0]
00100100OUT[0]
00101000OUT[1]
01000001PENT_NN3[3]
01000010PENT_NN3[0]
01000100OUT[5]
01001000OUT[8]
10000001PENT_NN5[3]
10000010PENT_NN5[0]
10000100OUT[4]
10001000OUT[9]
virtex5 INT switchbox INT muxes PENT_NE0[1]
BitsDestination
MAIN[4][39]MAIN[5][39]MAIN[5][37]MAIN[1][37]MAIN[2][39]MAIN[3][38]MAIN[1][39]MAIN[0][39]PENT_NE0[1]
Source
00000000off
00010001PENT_ES3[1]
00010010PENT_NW3[1]
00010100LH[6]
00011000OUT[19]
00100001PENT_EN5[1]
00100010PENT_NE5[1]
00100100OUT[20]
00101000OUT[2]
01000001PENT_NN3[4]
01000010PENT_NN3[1]
01000100OUT[13]
01001000OUT[14]
10000001PENT_NN5[4]
10000010PENT_NN5[1]
10000100OUT[10]
10001000OUT[7]
virtex5 INT switchbox INT muxes PENT_NE0[2]
BitsDestination
MAIN[4][60]MAIN[4][61]MAIN[4][59]MAIN[0][59]MAIN[3][61]MAIN[3][58]MAIN[1][60]MAIN[0][58]PENT_NE0[2]
Source
00000000off
00010001PENT_ES3[2]
00010010PENT_NW3[2]
00010100LH[0]
00011000OUT_S18_PENT
00100001PENT_EN5[2]
00100010PENT_NE5[2]
00100100OUT[3]
00101000OUT[21]
01000001PENT_NN3[5]
01000010PENT_NN3[2]
01000100OUT[6]
01001000OUT[11]
10000001PENT_NN5[5]
10000010PENT_NN5[2]
10000100OUT_S12_PENT
10001000OUT[15]
virtex5 INT switchbox INT muxes LH[0]
BitsDestination
MAIN[16][59]MAIN[17][58]MAIN[16][58]MAIN[16][63]MAIN[17][59]MAIN[17][61]MAIN[16][62]MAIN[14][60]MAIN[14][62]MAIN[16][60]LH[0]
Source
0000000000off
0001000011DBL_WS1_S0
0001000101DBL_WN2_S0
0001001001DBL_NN0[5]
0001010001DBL_NN2[5]
0001100001LV[0]
0010000011DBL_EN2[2]
0010000101DBL_ES1[2]
0010001001DBL_EE0_S3
0010010001DBL_EE2[5]
0010100001LV[18]
0100000011DBL_EE2[2]
0100000101DBL_EE0[2]
0100001001DBL_SW1[2]
0100010001DBL_SE2[2]
0100100001LH[18]
1000000011DBL_NN2[2]
1000000101DBL_NN0_S0
1000001001DBL_NW1[2]
1000010001DBL_NE2[2]
1000100001LV[6]
virtex5 INT switchbox INT muxes LH[18]
BitsDestination
MAIN[16][4]MAIN[16][0]MAIN[17][5]MAIN[16][5]MAIN[17][4]MAIN[17][2]MAIN[14][1]MAIN[14][3]MAIN[16][1]MAIN[16][3]LH[18]
Source
0000000000off
0001000011DBL_WW0_N5
0001000101DBL_WN1[0]
0001001001DBL_WS2[0]
0001010001DBL_WW2[3]
0001100001LV[0]
0010000011DBL_NW2_N2
0010000101DBL_WW0[0]
0010001001DBL_WW2[0]
0010010001DBL_NE1_N2
0010100001LH[0]
0100000011DBL_SS0[3]
0100000101DBL_EN1[0]
0100001001DBL_ES2[0]
0100010001DBL_SS2[3]
0100100001LV[18]
1000000011DBL_SW2[0]
1000000101DBL_SS0_N2
1000001001DBL_SS2[0]
1000010001DBL_SE1[0]
1000100001LV[12]
virtex5 INT switchbox INT muxes LV[0]
BitsDestination
MAIN[15][59]MAIN[14][58]MAIN[15][58]MAIN[15][63]MAIN[14][59]MAIN[17][60]MAIN[17][62]MAIN[14][61]MAIN[15][62]MAIN[15][60]LV[0]
Source
0000000000off
0001000011DBL_WS1_S0
0001000101DBL_WN2_S0
0001001001DBL_NN0[5]
0001010001DBL_NN2[5]
0001100001LH[0]
0010000011DBL_EN2[2]
0010000101DBL_ES1[2]
0010001001DBL_EE0_S3
0010010001DBL_EE2[5]
0010100001LV[18]
0100000011DBL_EE2[2]
0100000101DBL_EE0[2]
0100001001DBL_SW1[2]
0100010001DBL_SE2[2]
0100100001LH[18]
1000000011DBL_NN2[2]
1000000101DBL_NN0_S0
1000001001DBL_NW1[2]
1000010001DBL_NE2[2]
1000100001LH[12]
virtex5 INT switchbox INT muxes LV[18]
BitsDestination
MAIN[15][4]MAIN[15][0]MAIN[14][5]MAIN[15][5]MAIN[14][4]MAIN[17][3]MAIN[15][1]MAIN[14][2]MAIN[17][1]MAIN[15][3]LV[18]
Source
0000000000off
0001000011DBL_WW0_N5
0001000101DBL_WN1[0]
0001001001DBL_WS2[0]
0001010001DBL_WW2[3]
0001100001LV[0]
0010000011DBL_NW2_N2
0010000101DBL_WW0[0]
0010001001DBL_WW2[0]
0010010001DBL_NE1_N2
0010100001LH[0]
0100000011DBL_SS0[3]
0100000101DBL_EN1[0]
0100001001DBL_ES2[0]
0100010001DBL_SS2[3]
0100100001LH[18]
1000000011DBL_SW2[0]
1000000101DBL_SS0_N2
1000001001DBL_SS2[0]
1000010001DBL_SE1[0]
1000100001LH[6]
virtex5 INT switchbox INT muxes IMUX_GFAN[0]
BitsDestination
MAIN[14][29]MAIN[12][28]MAIN[12][27]MAIN[17][29]MAIN[14][30]MAIN[15][30]MAIN[15][31]MAIN[14][31]IMUX_GFAN[0]
Source
00000000off
00010001HCLK[0]
00010010IMUX_FAN_BOUNCE[4]
00010100IMUX_FAN_BOUNCE[1]
00011000HCLK[7]
00100001HCLK[1]
00100010HCLK[3]
00100100HCLK[5]
00101000HCLK[8]
01000001HCLK[2]
01000010HCLK[4]
01000100HCLK[6]
01001000HCLK[9]
10000001RCLK[0]
10000010RCLK[1]
10000100RCLK[2]
10001000RCLK[3]
virtex5 INT switchbox INT muxes IMUX_GFAN[1]
BitsDestination
MAIN[14][34]MAIN[12][35]MAIN[12][36]MAIN[17][34]MAIN[14][33]MAIN[15][33]MAIN[15][32]MAIN[14][32]IMUX_GFAN[1]
Source
00000000off
00010001HCLK[0]
00010010IMUX_FAN_BOUNCE[6]
00010100IMUX_FAN_BOUNCE[3]
00011000HCLK[7]
00100001HCLK[1]
00100010HCLK[3]
00100100HCLK[5]
00101000HCLK[8]
01000001HCLK[2]
01000010HCLK[4]
01000100HCLK[6]
01001000HCLK[9]
10000001RCLK[0]
10000010RCLK[1]
10000100RCLK[2]
10001000RCLK[3]
virtex5 INT switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[15][29]MAIN[15][28]MAIN[16][28]MAIN[16][29]MAIN[17][30]MAIN[16][30]MAIN[16][31]MAIN[17][31]IMUX_CLK[0]
Source
00000000off
00010001HCLK[0]
00010010IMUX_FAN_BOUNCE[4]
00010100IMUX_FAN_BOUNCE[1]
00011000HCLK[7]
00100001HCLK[1]
00100010HCLK[3]
00100100HCLK[5]
00101000HCLK[8]
01000001HCLK[2]
01000010HCLK[4]
01000100HCLK[6]
01001000HCLK[9]
10000001RCLK[0]
10000010RCLK[1]
10000100RCLK[2]
10001000RCLK[3]
virtex5 INT switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[15][34]MAIN[15][35]MAIN[16][35]MAIN[16][34]MAIN[17][33]MAIN[16][33]MAIN[16][32]MAIN[17][32]IMUX_CLK[1]
Source
00000000off
00010001HCLK[0]
00010010IMUX_FAN_BOUNCE[6]
00010100IMUX_FAN_BOUNCE[3]
00011000HCLK[7]
00100001HCLK[1]
00100010HCLK[3]
00100100HCLK[5]
00101000HCLK[8]
01000001HCLK[2]
01000010HCLK[4]
01000100HCLK[6]
01001000HCLK[9]
10000001RCLK[0]
10000010RCLK[1]
10000100RCLK[2]
10001000RCLK[3]
virtex5 INT switchbox INT muxes IMUX_CTRL[0]
BitsDestination
MAIN[15][27]MAIN[14][28]MAIN[14][27]MAIN[12][20]MAIN[16][25]MAIN[17][25]MAIN[15][26]MAIN[14][25]MAIN[15][25]MAIN[17][26]IMUX_CTRL[0]
Source
0000000000PULLUP
0001000001DBL_WW0[1]
0001000010DBL_WW0[3]
0001000100DBL_NE1[0]
0001001000DBL_WW1[4]
0001010000DBL_WW2[4]
0001100000IMUX_GFAN[1]
0010000001DBL_SS1[4]
0010000010DBL_EN1[1]
0010000100DBL_WW1[1]
0010001000DBL_ES2[1]
0010010000DBL_SS0[4]
0010100000IMUX_FAN_BOUNCE[4]
0100000001DBL_SS2[1]
0100000010DBL_SS2[4]
0100000100DBL_WW2[1]
0100001000DBL_SS0[0]
0100010000DBL_SS1[1]
0100100000IMUX_FAN_BOUNCE[1]
1000000001DBL_WS2[1]
1000000010DBL_SW2[1]
1000000100DBL_NW2[0]
1000001000DBL_SE1[1]
1000010000DBL_WN1[1]
1000100000IMUX_GFAN[0]
virtex5 INT switchbox INT muxes IMUX_CTRL[1]
BitsDestination
MAIN[17][28]MAIN[16][27]MAIN[17][27]MAIN[12][19]MAIN[16][24]MAIN[16][26]MAIN[12][12]MAIN[15][24]MAIN[14][26]MAIN[17][24]IMUX_CTRL[1]
Source
0000000000PULLUP
0001000001DBL_WW0[1]
0001000010DBL_WW0[3]
0001000100DBL_NE1[0]
0001001000DBL_WW1[4]
0001010000DBL_WW2[4]
0001100000IMUX_GFAN[1]
0010000001DBL_SS1[4]
0010000010DBL_EN1[1]
0010000100DBL_WW1[1]
0010001000DBL_ES2[1]
0010010000DBL_SS0[4]
0010100000IMUX_FAN_BOUNCE[4]
0100000001DBL_SS2[1]
0100000010DBL_SS2[4]
0100000100DBL_WW2[1]
0100001000DBL_SS0[0]
0100010000DBL_SS1[1]
0100100000IMUX_FAN_BOUNCE[1]
1000000001DBL_WS2[1]
1000000010DBL_SW2[1]
1000000100DBL_NW2[0]
1000001000DBL_SE1[1]
1000010000DBL_WN1[1]
1000100000IMUX_GFAN[0]
virtex5 INT switchbox INT muxes IMUX_CTRL[2]
BitsDestination
MAIN[15][36]MAIN[14][35]MAIN[12][43]MAIN[14][36]MAIN[16][38]MAIN[17][38]MAIN[14][38]MAIN[17][37]MAIN[15][38]MAIN[15][37]IMUX_CTRL[2]
Source
0000000000PULLUP
0001000001DBL_WS1[2]
0001000010DBL_WN2[2]
0001000100DBL_NN1[4]
0001001000DBL_EE1[1]
0001010000DBL_NN0[4]
0001100000IMUX_FAN_BOUNCE[6]
0010000001DBL_EE1[4]
0010000010DBL_EE0[5]
0010000100DBL_EE0[1]
0010001000DBL_SE2[1]
0010010000DBL_EE2[4]
0010100000IMUX_GFAN[1]
0100000001DBL_NN0[2]
0100000010DBL_NN2[4]
0100000100DBL_NN2[1]
0100001000DBL_EE2[1]
0100010000DBL_NN1[1]
0100100000IMUX_FAN_BOUNCE[3]
1000000001DBL_NE2[1]
1000000010DBL_NW1[1]
1000000100DBL_ES1[1]
1000001000DBL_SW1[1]
1000010000DBL_EN2[1]
1000100000IMUX_GFAN[0]
virtex5 INT switchbox INT muxes IMUX_CTRL[3]
BitsDestination
MAIN[17][35]MAIN[16][36]MAIN[12][44]MAIN[17][36]MAIN[16][39]MAIN[16][37]MAIN[15][39]MAIN[17][39]MAIN[14][37]MAIN[12][51]IMUX_CTRL[3]
Source
0000000000PULLUP
0001000001DBL_WS1[2]
0001000010DBL_WN2[2]
0001000100DBL_NN1[4]
0001001000DBL_EE1[1]
0001010000DBL_NN0[4]
0001100000IMUX_FAN_BOUNCE[6]
0010000001DBL_EE1[4]
0010000010DBL_EE0[5]
0010000100DBL_EE0[1]
0010001000DBL_SE2[1]
0010010000DBL_EE2[4]
0010100000IMUX_GFAN[1]
0100000001DBL_NN0[2]
0100000010DBL_NN2[4]
0100000100DBL_NN2[1]
0100001000DBL_EE2[1]
0100010000DBL_NN1[1]
0100100000IMUX_FAN_BOUNCE[3]
1000000001DBL_NE2[1]
1000000010DBL_NW1[1]
1000000100DBL_ES1[1]
1000001000DBL_SW1[1]
1000010000DBL_EN2[1]
1000100000IMUX_GFAN[0]
virtex5 INT switchbox INT muxes IMUX_BYP[0]
BitsDestination
MAIN[15][11]MAIN[14][12]MAIN[14][11]MAIN[14][7]MAIN[17][13]MAIN[16][2]MAIN[14][14]MAIN[16][12]MAIN[15][13]MAIN[14][13]IMUX_BYP[0]
Source
0000000000PULLUP
0001000001DBL_WS1[1]
0001000010DBL_WN2[1]
0001000100DBL_NN1[3]
0001001000DBL_EE1[0]
0001010000DBL_NN0[3]
0001100000OUT[0]
0010000001DBL_EE0[4]
0010000010DBL_EE1[3]
0010000100DBL_EE0[0]
0010001000DBL_SE2[0]
0010010000DBL_EE2[3]
0010100000IMUX_FAN_BOUNCE[2]
0100000001DBL_NN2[3]
0100000010DBL_NN0[1]
0100000100DBL_NN2[0]
0100001000DBL_EE2[0]
0100010000DBL_NN1[0]
0100100000OUT[5]
1000000001DBL_NW1[0]
1000000010DBL_NE2[0]
1000000100DBL_ES1[0]
1000001000DBL_SW1[0]
1000010000DBL_EN2[0]
1000100000IMUX_FAN_BOUNCE_N7
virtex5 INT switchbox INT muxes IMUX_BYP[1]
BitsDestination
MAIN[14][19]MAIN[15][18]MAIN[15][19]MAIN[14][18]MAIN[16][17]MAIN[17][16]MAIN[14][15]MAIN[17][17]MAIN[15][15]MAIN[15][17]IMUX_BYP[1]
Source
0000000000PULLUP
0001000001DBL_WS1[1]
0001000010DBL_WN2[1]
0001000100DBL_NN1[3]
0001001000DBL_EE1[0]
0001010000DBL_NN0[3]
0001100000OUT[4]
0010000001DBL_EE0[4]
0010000010DBL_EE1[3]
0010000100DBL_EE0[0]
0010001000DBL_SE2[0]
0010010000DBL_EE2[3]
0010100000IMUX_FAN_BOUNCE[2]
0100000001DBL_NN2[3]
0100000010DBL_NN0[1]
0100000100DBL_NN2[0]
0100001000DBL_EE2[0]
0100010000DBL_NN1[0]
0100100000OUT[1]
1000000001DBL_NW1[0]
1000000010DBL_NE2[0]
1000000100DBL_ES1[0]
1000001000DBL_SW1[0]
1000010000DBL_EN2[0]
1000100000IMUX_FAN_BOUNCE_N7
virtex5 INT switchbox INT muxes IMUX_BYP[2]
BitsDestination
MAIN[14][44]MAIN[15][45]MAIN[14][45]MAIN[15][44]MAIN[16][46]MAIN[17][47]MAIN[15][48]MAIN[14][48]MAIN[15][46]MAIN[17][46]IMUX_BYP[2]
Source
0000000000PULLUP
0001000001DBL_WW0[2]
0001000010DBL_WW0[4]
0001000100DBL_NW2[1]
0001001000DBL_WW1[5]
0001010000DBL_WW2[5]
0001100000IMUX_FAN_BOUNCE_S0
0010000001DBL_SS1[5]
0010000010DBL_EN1[2]
0010000100DBL_WW1[2]
0010001000DBL_ES2[2]
0010010000DBL_SS0[5]
0010100000OUT[2]
0100000001DBL_SS2[2]
0100000010DBL_SS2[5]
0100000100DBL_WW2[2]
0100001000DBL_SS0[1]
0100010000DBL_SS1[2]
0100100000OUT[7]
1000000001DBL_WS2[2]
1000000010DBL_SW2[2]
1000000100DBL_NE1[1]
1000001000DBL_SE1[2]
1000010000DBL_WN1[2]
1000100000IMUX_FAN_BOUNCE[5]
virtex5 INT switchbox INT muxes IMUX_BYP[3]
BitsDestination
MAIN[15][52]MAIN[14][51]MAIN[14][56]MAIN[14][52]MAIN[17][50]MAIN[16][61]MAIN[15][50]MAIN[14][49]MAIN[14][50]MAIN[16][51]IMUX_BYP[3]
Source
0000000000PULLUP
0001000001DBL_WW0[2]
0001000010DBL_WW0[4]
0001000100DBL_NW2[1]
0001001000DBL_WW1[5]
0001010000DBL_WW2[5]
0001100000IMUX_FAN_BOUNCE_S0
0010000001DBL_SS1[5]
0010000010DBL_EN1[2]
0010000100DBL_WW1[2]
0010001000DBL_ES2[2]
0010010000DBL_SS0[5]
0010100000OUT[6]
0100000001DBL_SS2[2]
0100000010DBL_SS2[5]
0100000100DBL_WW2[2]
0100001000DBL_SS0[1]
0100010000DBL_SS1[2]
0100100000OUT[3]
1000000001DBL_WS2[2]
1000000010DBL_SW2[2]
1000000100DBL_NE1[1]
1000001000DBL_SE1[2]
1000010000DBL_WN1[2]
1000100000IMUX_FAN_BOUNCE[5]
virtex5 INT switchbox INT muxes IMUX_BYP[4]
BitsDestination
MAIN[17][12]MAIN[16][11]MAIN[17][11]MAIN[17][7]MAIN[16][14]MAIN[16][13]MAIN[15][14]MAIN[17][14]MAIN[14][16]MAIN[15][12]IMUX_BYP[4]
Source
0000000000PULLUP
0001000001DBL_WS1[1]
0001000010DBL_WN2[1]
0001000100DBL_NN1[3]
0001001000DBL_EE1[0]
0001010000DBL_NN0[3]
0001100000OUT[0]
0010000001DBL_EE0[4]
0010000010DBL_EE1[3]
0010000100DBL_EE0[0]
0010001000DBL_SE2[0]
0010010000DBL_EE2[3]
0010100000IMUX_FAN_BOUNCE[2]
0100000001DBL_NN2[3]
0100000010DBL_NN0[1]
0100000100DBL_NN2[0]
0100001000DBL_EE2[0]
0100010000DBL_NN1[0]
0100100000OUT[5]
1000000001DBL_NW1[0]
1000000010DBL_NE2[0]
1000000100DBL_ES1[0]
1000001000DBL_SW1[0]
1000010000DBL_EN2[0]
1000100000IMUX_FAN_BOUNCE_N7
virtex5 INT switchbox INT muxes IMUX_BYP[5]
BitsDestination
MAIN[16][18]MAIN[17][19]MAIN[16][19]MAIN[17][18]MAIN[16][16]MAIN[16][15]MAIN[15][16]MAIN[17][15]MAIN[15][2]MAIN[14][17]IMUX_BYP[5]
Source
0000000000PULLUP
0001000001DBL_WS1[1]
0001000010DBL_WN2[1]
0001000100DBL_NN1[3]
0001001000DBL_EE1[0]
0001010000DBL_NN0[3]
0001100000OUT[4]
0010000001DBL_EE0[4]
0010000010DBL_EE1[3]
0010000100DBL_EE0[0]
0010001000DBL_SE2[0]
0010010000DBL_EE2[3]
0010100000IMUX_FAN_BOUNCE[2]
0100000001DBL_NN2[3]
0100000010DBL_NN0[1]
0100000100DBL_NN2[0]
0100001000DBL_EE2[0]
0100010000DBL_NN1[0]
0100100000OUT[1]
1000000001DBL_NW1[0]
1000000010DBL_NE2[0]
1000000100DBL_ES1[0]
1000001000DBL_SW1[0]
1000010000DBL_EN2[0]
1000100000IMUX_FAN_BOUNCE_N7
virtex5 INT switchbox INT muxes IMUX_BYP[6]
BitsDestination
MAIN[16][45]MAIN[17][44]MAIN[17][45]MAIN[16][44]MAIN[16][47]MAIN[16][48]MAIN[15][61]MAIN[15][47]MAIN[14][46]MAIN[17][48]IMUX_BYP[6]
Source
0000000000PULLUP
0001000001DBL_WW0[2]
0001000010DBL_WW0[4]
0001000100DBL_NW2[1]
0001001000DBL_WW1[5]
0001010000DBL_WW2[5]
0001100000IMUX_FAN_BOUNCE_S0
0010000001DBL_SS1[5]
0010000010DBL_EN1[2]
0010000100DBL_WW1[2]
0010001000DBL_ES2[2]
0010010000DBL_SS0[5]
0010100000OUT[2]
0100000001DBL_SS2[2]
0100000010DBL_SS2[5]
0100000100DBL_WW2[2]
0100001000DBL_SS0[1]
0100010000DBL_SS1[2]
0100100000OUT[7]
1000000001DBL_WS2[2]
1000000010DBL_SW2[2]
1000000100DBL_NE1[1]
1000001000DBL_SE1[2]
1000010000DBL_WN1[2]
1000100000IMUX_FAN_BOUNCE[5]
virtex5 INT switchbox INT muxes IMUX_BYP[7]
BitsDestination
MAIN[17][51]MAIN[16][52]MAIN[17][56]MAIN[17][52]MAIN[16][49]MAIN[16][50]MAIN[14][47]MAIN[15][49]MAIN[15][51]MAIN[17][49]IMUX_BYP[7]
Source
0000000000PULLUP
0001000001DBL_WW0[2]
0001000010DBL_WW0[4]
0001000100DBL_NW2[1]
0001001000DBL_WW1[5]
0001010000DBL_WW2[5]
0001100000IMUX_FAN_BOUNCE_S0
0010000001DBL_SS1[5]
0010000010DBL_EN1[2]
0010000100DBL_WW1[2]
0010001000DBL_ES2[2]
0010010000DBL_SS0[5]
0010100000OUT[6]
0100000001DBL_SS2[2]
0100000010DBL_SS2[5]
0100000100DBL_WW2[2]
0100001000DBL_SS0[1]
0100010000DBL_SS1[2]
0100100000OUT[3]
1000000001DBL_WS2[2]
1000000010DBL_SW2[2]
1000000100DBL_NE1[1]
1000001000DBL_SE1[2]
1000010000DBL_WN1[2]
1000100000IMUX_FAN_BOUNCE[5]
virtex5 INT switchbox INT muxes IMUX_FAN[0]
BitsDestination
MAIN[14][10]MAIN[15][10]MAIN[14][9]MAIN[15][9]MAIN[16][8]MAIN[14][8]MAIN[14][6]MAIN[15][7]MAIN[17][0]MAIN[16][7]IMUX_FAN[0]
Source
0000000000off
0001000001TIE_0
0001000010DBL_SS0[3]
0001000100DBL_EN1[0]
0001001000DBL_SS1[3]
0001010000DBL_ES2[0]
0001100000DBL_SS2[3]
0010000001TIE_1
0010000010DBL_SW2[0]
0010000100DBL_SS0_N2
0010001000DBL_SS1[0]
0010010000DBL_SS2[0]
0010100000DBL_SE1[0]
0100000001IMUX_GFAN[0]
0100000010DBL_WW0_N5
0100000100DBL_WN1[0]
0100001000DBL_WW1[3]
0100010000DBL_WS2[0]
0100100000DBL_WW2[3]
1000000001IMUX_GFAN[1]
1000000010DBL_NW2_N2
1000000100DBL_WW0[0]
1000001000DBL_WW1[0]
1000010000DBL_WW2[0]
1000100000DBL_NE1_N2
virtex5 INT switchbox INT muxes IMUX_FAN[1]
BitsDestination
MAIN[17][10]MAIN[17][9]MAIN[16][10]MAIN[16][9]MAIN[17][6]MAIN[14][0]MAIN[15][6]MAIN[15][8]MAIN[17][8]MAIN[16][6]IMUX_FAN[1]
Source
0000000000off
0001000001TIE_0
0001000010DBL_SS0[3]
0001000100DBL_EN1[0]
0001001000DBL_SS1[3]
0001010000DBL_ES2[0]
0001100000DBL_SS2[3]
0010000001TIE_1
0010000010DBL_SW2[0]
0010000100DBL_SS0_N2
0010001000DBL_SS1[0]
0010010000DBL_SS2[0]
0010100000DBL_SE1[0]
0100000001IMUX_GFAN[0]
0100000010DBL_WW0_N5
0100000100DBL_WN1[0]
0100001000DBL_WW1[3]
0100010000DBL_WS2[0]
0100100000DBL_WW2[3]
1000000001IMUX_GFAN[1]
1000000010DBL_NW2_N2
1000000100DBL_WW0[0]
1000001000DBL_WW1[0]
1000010000DBL_WW2[0]
1000100000DBL_NE1_N2
virtex5 INT switchbox INT muxes IMUX_FAN[2]
BitsDestination
MAIN[12][4]MAIN[14][20]MAIN[14][21]MAIN[15][20]MAIN[12][11]MAIN[14][22]MAIN[14][24]MAIN[15][22]MAIN[16][21]MAIN[16][22]IMUX_FAN[2]
Source
0000000000off
0001000001TIE_0
0001000010DBL_SS1[4]
0001000100DBL_EN1[1]
0001001000DBL_WW1[1]
0001010000DBL_ES2[1]
0001100000DBL_SS0[4]
0010000001TIE_1
0010000010DBL_SS2[1]
0010000100DBL_SS2[4]
0010001000DBL_WW2[1]
0010010000DBL_SS0[0]
0010100000DBL_SS1[1]
0100000001IMUX_GFAN[1]
0100000010DBL_WW0[1]
0100000100DBL_WW0[3]
0100001000DBL_NE1[0]
0100010000DBL_WW1[4]
0100100000DBL_WW2[4]
1000000001IMUX_GFAN[0]
1000000010DBL_WS2[1]
1000000100DBL_SW2[1]
1000001000DBL_NW2[0]
1000010000DBL_SE1[1]
1000100000DBL_WN1[1]
virtex5 INT switchbox INT muxes IMUX_FAN[3]
BitsDestination
MAIN[17][21]MAIN[17][20]MAIN[12][3]MAIN[16][20]MAIN[17][22]MAIN[14][23]MAIN[15][23]MAIN[15][21]MAIN[17][23]MAIN[16][23]IMUX_FAN[3]
Source
0000000000off
0001000001TIE_0
0001000010DBL_SS1[4]
0001000100DBL_EN1[1]
0001001000DBL_WW1[1]
0001010000DBL_ES2[1]
0001100000DBL_SS0[4]
0010000001TIE_1
0010000010DBL_SS2[1]
0010000100DBL_SS2[4]
0010001000DBL_WW2[1]
0010010000DBL_SS0[0]
0010100000DBL_SS1[1]
0100000001IMUX_GFAN[1]
0100000010DBL_WW0[1]
0100000100DBL_WW0[3]
0100001000DBL_NE1[0]
0100010000DBL_WW1[4]
0100100000DBL_WW2[4]
1000000001IMUX_GFAN[0]
1000000010DBL_WS2[1]
1000000100DBL_SW2[1]
1000001000DBL_NW2[0]
1000010000DBL_SE1[1]
1000100000DBL_WN1[1]
virtex5 INT switchbox INT muxes IMUX_FAN[4]
BitsDestination
MAIN[12][59]MAIN[14][43]MAIN[14][42]MAIN[15][43]MAIN[12][52]MAIN[14][39]MAIN[16][42]MAIN[15][41]MAIN[14][41]MAIN[16][41]IMUX_FAN[4]
Source
0000000000off
0001000001TIE_0
0001000010DBL_WS1[2]
0001000100DBL_WN2[2]
0001001000DBL_NN1[4]
0001010000DBL_EE1[1]
0001100000DBL_NN0[4]
0010000001TIE_1
0010000010DBL_NN0[2]
0010000100DBL_NN2[4]
0010001000DBL_NN2[1]
0010010000DBL_EE2[1]
0010100000DBL_NN1[1]
0100000001IMUX_GFAN[1]
0100000010DBL_EE1[4]
0100000100DBL_EE0[5]
0100001000DBL_EE0[1]
0100010000DBL_SE2[1]
0100100000DBL_EE2[4]
1000000001IMUX_GFAN[0]
1000000010DBL_NE2[1]
1000000100DBL_NW1[1]
1000001000DBL_ES1[1]
1000010000DBL_SW1[1]
1000100000DBL_EN2[1]
virtex5 INT switchbox INT muxes IMUX_FAN[5]
BitsDestination
MAIN[17][42]MAIN[17][43]MAIN[12][60]MAIN[16][43]MAIN[17][41]MAIN[15][40]MAIN[17][40]MAIN[15][42]MAIN[14][40]MAIN[16][40]IMUX_FAN[5]
Source
0000000000off
0001000001TIE_0
0001000010DBL_WS1[2]
0001000100DBL_WN2[2]
0001001000DBL_NN1[4]
0001010000DBL_EE1[1]
0001100000DBL_NN0[4]
0010000001TIE_1
0010000010DBL_NN0[2]
0010000100DBL_NN2[4]
0010001000DBL_NN2[1]
0010010000DBL_EE2[1]
0010100000DBL_NN1[1]
0100000001IMUX_GFAN[1]
0100000010DBL_EE1[4]
0100000100DBL_EE0[5]
0100001000DBL_EE0[1]
0100010000DBL_SE2[1]
0100100000DBL_EE2[4]
1000000001IMUX_GFAN[0]
1000000010DBL_NE2[1]
1000000100DBL_NW1[1]
1000001000DBL_ES1[1]
1000010000DBL_SW1[1]
1000100000DBL_EN2[1]
virtex5 INT switchbox INT muxes IMUX_FAN[6]
BitsDestination
MAIN[14][53]MAIN[15][53]MAIN[14][54]MAIN[15][54]MAIN[16][55]MAIN[14][57]MAIN[17][63]MAIN[15][56]MAIN[14][55]MAIN[16][56]IMUX_FAN[6]
Source
0000000000off
0001000001TIE_0
0001000010DBL_WS1_S0
0001000100DBL_WN2_S0
0001001000DBL_NN0[5]
0001010000DBL_EE1[5]
0001100000DBL_NN2[5]
0010000001TIE_1
0010000010DBL_NN2[2]
0010000100DBL_NN0_S0
0010001000DBL_NW1[2]
0010010000DBL_EE1[2]
0010100000DBL_NE2[2]
0100000001IMUX_GFAN[0]
0100000010DBL_EN2[2]
0100000100DBL_ES1[2]
0100001000DBL_EE0_S3
0100010000DBL_NN1[5]
0100100000DBL_EE2[5]
1000000001IMUX_GFAN[1]
1000000010DBL_EE2[2]
1000000100DBL_EE0[2]
1000001000DBL_SW1[2]
1000010000DBL_NN1[2]
1000100000DBL_SE2[2]
virtex5 INT switchbox INT muxes IMUX_FAN[7]
BitsDestination
MAIN[17][53]MAIN[17][54]MAIN[16][53]MAIN[16][54]MAIN[17][57]MAIN[15][57]MAIN[17][55]MAIN[15][55]MAIN[14][63]MAIN[16][57]IMUX_FAN[7]
Source
0000000000off
0001000001TIE_0
0001000010DBL_WS1_S0
0001000100DBL_WN2_S0
0001001000DBL_NN0[5]
0001010000DBL_EE1[5]
0001100000DBL_NN2[5]
0010000001TIE_1
0010000010DBL_NN2[2]
0010000100DBL_NN0_S0
0010001000DBL_NW1[2]
0010010000DBL_EE1[2]
0010100000DBL_NE2[2]
0100000001IMUX_GFAN[0]
0100000010DBL_EN2[2]
0100000100DBL_ES1[2]
0100001000DBL_EE0_S3
0100010000DBL_NN1[5]
0100100000DBL_EE2[5]
1000000001IMUX_GFAN[1]
1000000010DBL_EE2[2]
1000000100DBL_EE0[2]
1000001000DBL_SW1[2]
1000010000DBL_NN1[2]
1000100000DBL_SE2[2]
virtex5 INT switchbox INT muxes IMUX_IMUX[0]
BitsDestination
MAIN[24][1]MAIN[23][1]MAIN[25][1]MAIN[22][1]MAIN[20][2]MAIN[20][0]MAIN[25][2]MAIN[22][0]MAIN[19][2]MAIN[19][0]MAIN[19][1]IMUX_IMUX[0]
Source
00000000000PULLUP
00010000001DBL_WW0_N5
00010000010DBL_WW1[3]
00010000100DBL_WN1[0]
00010001000DBL_SS1[3]
00010010000DBL_SS0[3]
00010100000IMUX_CTRL_BOUNCE[2]
00011000000IMUX_BYP_BOUNCE_N3
00100000001DBL_WW2[3]
00100000010DBL_WW0[0]
00100000100DBL_WS2[0]
00100001000DBL_SS0_N2
00100010000DBL_SS2[3]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_BYP_BOUNCE[4]
01000000001DBL_WW1[0]
01000000010DBL_WW2[0]
01000000100DBL_NW2_N2
01000001000DBL_SS2[0]
01000010000DBL_SS1[0]
01000100000IMUX_FAN_BOUNCE_N7
01001000000OUT[12]
10000000001DBL_SW2[0]
10000000010DBL_SE1[0]
10000000100DBL_NE1_N2
10000001000DBL_ES2[0]
10000010000DBL_EN1[0]
10000100000IMUX_FAN_BOUNCE[2]
10001000000OUT[18]
virtex5 INT switchbox INT muxes IMUX_IMUX[1]
BitsDestination
MAIN[23][12]MAIN[24][11]MAIN[19][11]MAIN[24][12]MAIN[21][13]MAIN[21][10]MAIN[18][12]MAIN[19][12]MAIN[13][8]MAIN[25][14]MAIN[22][11]IMUX_IMUX[1]
Source
00000000000PULLUP
00010000001DBL_WS1[1]
00010000010DBL_WN2[1]
00010000100DBL_NE2[0]
00010001000DBL_NW1[0]
00010010000DBL_SE2[0]
00010100000IMUX_FAN_BOUNCE[2]
00011000000OUT[0]
00100000001DBL_NN0[1]
00100000010DBL_NN2[3]
00100000100DBL_EE0[0]
00100001000DBL_EE2[3]
00100010000DBL_ES1[0]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_FAN_BOUNCE[4]
01000000001DBL_NN1[3]
01000000010DBL_NN0[3]
01000000100DBL_EE1[3]
01000001000DBL_EE0[4]
01000010000DBL_EN2[0]
01000100000IMUX_CTRL_BOUNCE_N3
01001000000IMUX_BYP_BOUNCE_N7
10000000001DBL_NN2[0]
10000000010DBL_NN1[0]
10000000100DBL_EE2[0]
10000001000DBL_EE1[0]
10000010000DBL_SW1[0]
10000100000IMUX_FAN_BOUNCE_N7
10001000000OUT[5]
virtex5 INT switchbox INT muxes IMUX_IMUX[2]
BitsDestination
MAIN[22][22]MAIN[18][22]MAIN[19][22]MAIN[24][22]MAIN[20][21]MAIN[20][23]MAIN[25][21]MAIN[22][23]MAIN[18][21]MAIN[13][23]MAIN[19][23]IMUX_IMUX[2]
Source
00000000000PULLUP
00010000001DBL_WW0[1]
00010000010DBL_WW2[4]
00010000100DBL_WS2[1]
00010001000DBL_SS0[0]
00010010000DBL_SS2[4]
00010100000IMUX_BYP_BOUNCE[6]
00011000000IMUX_FAN_BOUNCE[4]
00100000001DBL_WW1[4]
00100000010DBL_WW0[3]
00100000100DBL_WN1[1]
00100001000DBL_SS1[4]
00100010000DBL_SS0[4]
00100100000IMUX_BYP_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE_N7
01000000001DBL_WW2[1]
01000000010DBL_WW1[1]
01000000100DBL_NW2[0]
01000001000DBL_SS2[1]
01000010000DBL_SS1[1]
01000100000IMUX_FAN_BOUNCE[6]
01001000000OUT[23]
10000000001DBL_SE1[1]
10000000010DBL_SW2[1]
10000000100DBL_NE1[0]
10000001000DBL_ES2[1]
10000010000DBL_EN1[1]
10000100000IMUX_FAN_BOUNCE[1]
10001000000OUT[9]
virtex5 INT switchbox INT muxes IMUX_IMUX[3]
BitsDestination
MAIN[23][33]MAIN[22][33]MAIN[25][33]MAIN[24][33]MAIN[20][34]MAIN[20][32]MAIN[19][34]MAIN[19][33]MAIN[19][32]MAIN[25][34]MAIN[22][32]IMUX_IMUX[3]
Source
00000000000PULLUP
00010000001DBL_WS1[2]
00010000010DBL_WN2[2]
00010000100DBL_NE2[1]
00010001000DBL_NW1[1]
00010010000DBL_SE2[1]
00010100000IMUX_FAN_BOUNCE[1]
00011000000OUT[16]
00100000001DBL_NN0[2]
00100000010DBL_NN2[4]
00100000100DBL_EE0[1]
00100001000DBL_EE2[4]
00100010000DBL_ES1[1]
00100100000IMUX_BYP_BOUNCE[6]
00101000000IMUX_FAN_BOUNCE[3]
01000000001DBL_NN1[4]
01000000010DBL_NN0[4]
01000000100DBL_EE1[4]
01000001000DBL_EE0[5]
01000010000DBL_EN2[1]
01000100000IMUX_BYP_BOUNCE[1]
01001000000IMUX_BYP_BOUNCE_S0
10000000001DBL_NN2[1]
10000000010DBL_NN1[1]
10000000100DBL_EE2[1]
10000001000DBL_EE1[1]
10000010000DBL_SW1[1]
10000100000IMUX_FAN_BOUNCE[6]
10001000000OUT[14]
virtex5 INT switchbox INT muxes IMUX_IMUX[4]
BitsDestination
MAIN[24][44]MAIN[23][44]MAIN[24][43]MAIN[19][43]MAIN[21][45]MAIN[21][42]MAIN[25][46]MAIN[22][43]MAIN[18][44]MAIN[19][44]MAIN[13][40]IMUX_IMUX[4]
Source
00000000000PULLUP
00010000001DBL_WW0[2]
00010000010DBL_WW2[5]
00010000100DBL_WS2[2]
00010001000DBL_SS0[1]
00010010000DBL_SS2[5]
00010100000IMUX_BYP_BOUNCE[5]
00011000000IMUX_FAN_BOUNCE[3]
00100000001DBL_WW1[5]
00100000010DBL_WW0[4]
00100000100DBL_WN1[2]
00100001000DBL_SS1[5]
00100010000DBL_SS0[5]
00100100000IMUX_CTRL_BOUNCE_S0
00101000000IMUX_BYP_BOUNCE_S0
01000000001DBL_WW2[2]
01000000010DBL_WW1[2]
01000000100DBL_NW2[1]
01000001000DBL_SS2[2]
01000010000DBL_SS1[2]
01000100000IMUX_FAN_BOUNCE[5]
01001000000OUT[7]
10000000001DBL_SE1[2]
10000000010DBL_SW2[2]
10000000100DBL_NE1[1]
10000001000DBL_ES2[2]
10000010000DBL_EN1[2]
10000100000IMUX_FAN_BOUNCE_S0
10001000000OUT[2]
virtex5 INT switchbox INT muxes IMUX_IMUX[5]
BitsDestination
MAIN[18][54]MAIN[24][54]MAIN[19][54]MAIN[22][54]MAIN[20][53]MAIN[20][55]MAIN[18][53]MAIN[19][55]MAIN[13][55]MAIN[25][53]MAIN[22][55]IMUX_IMUX[5]
Source
00000000000PULLUP
00010000001DBL_WS1_S0
00010000010DBL_WN2_S0
00010000100DBL_NW1[2]
00010001000DBL_NE2[2]
00010010000DBL_SE2[2]
00010100000IMUX_FAN_BOUNCE_S0
00011000000OUT[11]
00100000001DBL_NN1[5]
00100000010DBL_NN0[5]
00100000100DBL_EE0_S3
00100001000DBL_EE1[5]
00100010000DBL_EN2[2]
00100100000IMUX_CTRL_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE[3]
01000000001DBL_NN0_S0
01000000010DBL_NN2[5]
01000000100DBL_EE2[5]
01000001000DBL_EE0[2]
01000010000DBL_ES1[2]
01000100000IMUX_BYP_BOUNCE[5]
01001000000IMUX_BYP_BOUNCE_S4
10000000001DBL_NN2[2]
10000000010DBL_NN1[2]
10000000100DBL_EE1[2]
10000001000DBL_EE2[2]
10000010000DBL_SW1[2]
10000100000IMUX_FAN_BOUNCE[5]
10001000000OUT[21]
virtex5 INT switchbox INT muxes IMUX_IMUX[6]
BitsDestination
MAIN[22][2]MAIN[24][2]MAIN[25][0]MAIN[23][0]MAIN[21][0]MAIN[20][1]MAIN[24][0]MAIN[23][2]MAIN[21][1]MAIN[18][1]MAIN[18][0]IMUX_IMUX[6]
Source
00000000000PULLUP
00010000001DBL_WW0_N5
00010000010DBL_WW1[3]
00010000100DBL_WN1[0]
00010001000DBL_SS1[3]
00010010000DBL_SS0[3]
00010100000IMUX_CTRL_BOUNCE[2]
00011000000IMUX_BYP_BOUNCE_N3
00100000001DBL_WW2[3]
00100000010DBL_WW0[0]
00100000100DBL_WS2[0]
00100001000DBL_SS0_N2
00100010000DBL_SS2[3]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_BYP_BOUNCE[4]
01000000001DBL_WW1[0]
01000000010DBL_WW2[0]
01000000100DBL_NW2_N2
01000001000DBL_SS2[0]
01000010000DBL_SS1[0]
01000100000IMUX_FAN_BOUNCE_N7
01001000000OUT[12]
10000000001DBL_SW2[0]
10000000010DBL_SE1[0]
10000000100DBL_NE1_N2
10000001000DBL_ES2[0]
10000010000DBL_EN1[0]
10000100000IMUX_FAN_BOUNCE[2]
10001000000OUT[18]
virtex5 INT switchbox INT muxes IMUX_IMUX[7]
BitsDestination
MAIN[22][12]MAIN[18][10]MAIN[23][11]MAIN[25][12]MAIN[21][11]MAIN[21][12]MAIN[20][11]MAIN[18][11]MAIN[20][12]MAIN[25][11]MAIN[22][13]IMUX_IMUX[7]
Source
00000000000PULLUP
00010000001DBL_WS1[1]
00010000010DBL_WN2[1]
00010000100DBL_NE2[0]
00010001000DBL_NW1[0]
00010010000DBL_SE2[0]
00010100000IMUX_FAN_BOUNCE[2]
00011000000OUT[0]
00100000001DBL_NN0[1]
00100000010DBL_NN2[3]
00100000100DBL_EE0[0]
00100001000DBL_EE2[3]
00100010000DBL_ES1[0]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_FAN_BOUNCE[4]
01000000001DBL_NN1[3]
01000000010DBL_NN0[3]
01000000100DBL_EE1[3]
01000001000DBL_EE0[4]
01000010000DBL_EN2[0]
01000100000IMUX_CTRL_BOUNCE_N3
01001000000IMUX_BYP_BOUNCE_N7
10000000001DBL_NN2[0]
10000000010DBL_NN1[0]
10000000100DBL_EE2[0]
10000001000DBL_EE1[0]
10000010000DBL_SW1[0]
10000100000IMUX_FAN_BOUNCE_N7
10001000000OUT[5]
virtex5 INT switchbox INT muxes IMUX_IMUX[8]
BitsDestination
MAIN[24][23]MAIN[25][23]MAIN[23][21]MAIN[23][22]MAIN[21][23]MAIN[20][22]MAIN[23][23]MAIN[24][21]MAIN[21][22]MAIN[18][23]MAIN[19][21]IMUX_IMUX[8]
Source
00000000000PULLUP
00010000001DBL_WW0[1]
00010000010DBL_WW2[4]
00010000100DBL_WS2[1]
00010001000DBL_SS0[0]
00010010000DBL_SS2[4]
00010100000IMUX_BYP_BOUNCE[6]
00011000000IMUX_FAN_BOUNCE[4]
00100000001DBL_WW1[4]
00100000010DBL_WW0[3]
00100000100DBL_WN1[1]
00100001000DBL_SS1[4]
00100010000DBL_SS0[4]
00100100000IMUX_BYP_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE_N7
01000000001DBL_WW2[1]
01000000010DBL_WW1[1]
01000000100DBL_NW2[0]
01000001000DBL_SS2[1]
01000010000DBL_SS1[1]
01000100000IMUX_FAN_BOUNCE[6]
01001000000OUT[23]
10000000001DBL_SE1[1]
10000000010DBL_SW2[1]
10000000100DBL_NE1[0]
10000001000DBL_ES2[1]
10000010000DBL_EN1[1]
10000100000IMUX_FAN_BOUNCE[1]
10001000000OUT[9]
virtex5 INT switchbox INT muxes IMUX_IMUX[9]
BitsDestination
MAIN[24][34]MAIN[23][32]MAIN[25][32]MAIN[22][34]MAIN[21][32]MAIN[20][33]MAIN[21][33]MAIN[18][32]MAIN[18][33]MAIN[24][32]MAIN[23][34]IMUX_IMUX[9]
Source
00000000000PULLUP
00010000001DBL_WS1[2]
00010000010DBL_WN2[2]
00010000100DBL_NE2[1]
00010001000DBL_NW1[1]
00010010000DBL_SE2[1]
00010100000IMUX_FAN_BOUNCE[1]
00011000000OUT[16]
00100000001DBL_NN0[2]
00100000010DBL_NN2[4]
00100000100DBL_EE0[1]
00100001000DBL_EE2[4]
00100010000DBL_ES1[1]
00100100000IMUX_BYP_BOUNCE[6]
00101000000IMUX_FAN_BOUNCE[3]
01000000001DBL_NN1[4]
01000000010DBL_NN0[4]
01000000100DBL_EE1[4]
01000001000DBL_EE0[5]
01000010000DBL_EN2[1]
01000100000IMUX_BYP_BOUNCE[1]
01001000000IMUX_BYP_BOUNCE_S0
10000000001DBL_NN2[1]
10000000010DBL_NN1[1]
10000000100DBL_EE2[1]
10000001000DBL_EE1[1]
10000010000DBL_SW1[1]
10000100000IMUX_FAN_BOUNCE[6]
10001000000OUT[14]
virtex5 INT switchbox INT muxes IMUX_IMUX[10]
BitsDestination
MAIN[25][44]MAIN[22][44]MAIN[18][42]MAIN[23][43]MAIN[21][43]MAIN[21][44]MAIN[25][43]MAIN[22][45]MAIN[20][43]MAIN[18][43]MAIN[20][44]IMUX_IMUX[10]
Source
00000000000PULLUP
00010000001DBL_WW0[2]
00010000010DBL_WW2[5]
00010000100DBL_WS2[2]
00010001000DBL_SS0[1]
00010010000DBL_SS2[5]
00010100000IMUX_BYP_BOUNCE[5]
00011000000IMUX_FAN_BOUNCE[3]
00100000001DBL_WW1[5]
00100000010DBL_WW0[4]
00100000100DBL_WN1[2]
00100001000DBL_SS1[5]
00100010000DBL_SS0[5]
00100100000IMUX_CTRL_BOUNCE_S0
00101000000IMUX_BYP_BOUNCE_S0
01000000001DBL_WW2[2]
01000000010DBL_WW1[2]
01000000100DBL_NW2[1]
01000001000DBL_SS2[2]
01000010000DBL_SS1[2]
01000100000IMUX_FAN_BOUNCE[5]
01001000000OUT[7]
10000000001DBL_SE1[2]
10000000010DBL_SW2[2]
10000000100DBL_NE1[1]
10000001000DBL_ES2[2]
10000010000DBL_EN1[2]
10000100000IMUX_FAN_BOUNCE_S0
10001000000OUT[2]
virtex5 INT switchbox INT muxes IMUX_IMUX[11]
BitsDestination
MAIN[25][55]MAIN[23][54]MAIN[23][53]MAIN[24][55]MAIN[21][55]MAIN[20][54]MAIN[21][54]MAIN[19][53]MAIN[18][55]MAIN[23][55]MAIN[24][53]IMUX_IMUX[11]
Source
00000000000PULLUP
00010000001DBL_WS1_S0
00010000010DBL_WN2_S0
00010000100DBL_NW1[2]
00010001000DBL_NE2[2]
00010010000DBL_SE2[2]
00010100000IMUX_FAN_BOUNCE_S0
00011000000OUT[11]
00100000001DBL_NN1[5]
00100000010DBL_NN0[5]
00100000100DBL_EE0_S3
00100001000DBL_EE1[5]
00100010000DBL_EN2[2]
00100100000IMUX_CTRL_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE[3]
01000000001DBL_NN0_S0
01000000010DBL_NN2[5]
01000000100DBL_EE2[5]
01000001000DBL_EE0[2]
01000010000DBL_ES1[2]
01000100000IMUX_BYP_BOUNCE[5]
01001000000IMUX_BYP_BOUNCE_S4
10000000001DBL_NN2[2]
10000000010DBL_NN1[2]
10000000100DBL_EE1[2]
10000001000DBL_EE2[2]
10000010000DBL_SW1[2]
10000100000IMUX_FAN_BOUNCE[5]
10001000000OUT[21]
virtex5 INT switchbox INT muxes IMUX_IMUX[12]
BitsDestination
MAIN[24][4]MAIN[23][4]MAIN[19][3]MAIN[24][3]MAIN[21][5]MAIN[21][2]MAIN[25][6]MAIN[22][3]MAIN[18][4]MAIN[13][0]MAIN[19][4]IMUX_IMUX[12]
Source
00000000000PULLUP
00010000001DBL_WW0_N5
00010000010DBL_WW1[3]
00010000100DBL_WN1[0]
00010001000DBL_SS1[3]
00010010000DBL_SS0[3]
00010100000IMUX_CTRL_BOUNCE[2]
00011000000IMUX_BYP_BOUNCE_N3
00100000001DBL_WW2[3]
00100000010DBL_WW0[0]
00100000100DBL_WS2[0]
00100001000DBL_SS0_N2
00100010000DBL_SS2[3]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_BYP_BOUNCE[4]
01000000001DBL_WW1[0]
01000000010DBL_WW2[0]
01000000100DBL_NW2_N2
01000001000DBL_SS2[0]
01000010000DBL_SS1[0]
01000100000IMUX_FAN_BOUNCE_N7
01001000000OUT[12]
10000000001DBL_SW2[0]
10000000010DBL_SE1[0]
10000000100DBL_NE1_N2
10000001000DBL_ES2[0]
10000010000DBL_EN1[0]
10000100000IMUX_FAN_BOUNCE[2]
10001000000OUT[18]
virtex5 INT switchbox INT muxes IMUX_IMUX[13]
BitsDestination
MAIN[18][14]MAIN[19][14]MAIN[24][14]MAIN[22][14]MAIN[20][13]MAIN[20][15]MAIN[18][13]MAIN[13][15]MAIN[19][15]MAIN[25][13]MAIN[22][15]IMUX_IMUX[13]
Source
00000000000PULLUP
00010000001DBL_WS1[1]
00010000010DBL_WN2[1]
00010000100DBL_NE2[0]
00010001000DBL_NW1[0]
00010010000DBL_SE2[0]
00010100000IMUX_FAN_BOUNCE[2]
00011000000OUT[0]
00100000001DBL_NN0[1]
00100000010DBL_NN2[3]
00100000100DBL_EE0[0]
00100001000DBL_EE2[3]
00100010000DBL_ES1[0]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_FAN_BOUNCE[4]
01000000001DBL_NN1[3]
01000000010DBL_NN0[3]
01000000100DBL_EE1[3]
01000001000DBL_EE0[4]
01000010000DBL_EN2[0]
01000100000IMUX_CTRL_BOUNCE_N3
01001000000IMUX_BYP_BOUNCE_N7
10000000001DBL_NN2[0]
10000000010DBL_NN1[0]
10000000100DBL_EE2[0]
10000001000DBL_EE1[0]
10000010000DBL_SW1[0]
10000100000IMUX_FAN_BOUNCE_N7
10001000000OUT[5]
virtex5 INT switchbox INT muxes IMUX_IMUX[14]
BitsDestination
MAIN[24][25]MAIN[23][25]MAIN[22][25]MAIN[25][25]MAIN[20][26]MAIN[20][24]MAIN[25][26]MAIN[22][24]MAIN[19][26]MAIN[19][25]MAIN[19][24]IMUX_IMUX[14]
Source
00000000000PULLUP
00010000001DBL_WW0[1]
00010000010DBL_WW2[4]
00010000100DBL_WS2[1]
00010001000DBL_SS0[0]
00010010000DBL_SS2[4]
00010100000IMUX_BYP_BOUNCE[6]
00011000000IMUX_FAN_BOUNCE[4]
00100000001DBL_WW1[4]
00100000010DBL_WW0[3]
00100000100DBL_WN1[1]
00100001000DBL_SS1[4]
00100010000DBL_SS0[4]
00100100000IMUX_BYP_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE_N7
01000000001DBL_WW2[1]
01000000010DBL_WW1[1]
01000000100DBL_NW2[0]
01000001000DBL_SS2[1]
01000010000DBL_SS1[1]
01000100000IMUX_FAN_BOUNCE[6]
01001000000OUT[23]
10000000001DBL_SE1[1]
10000000010DBL_SW2[1]
10000000100DBL_NE1[0]
10000001000DBL_ES2[1]
10000010000DBL_EN1[1]
10000100000IMUX_FAN_BOUNCE[1]
10001000000OUT[9]
virtex5 INT switchbox INT muxes IMUX_IMUX[15]
BitsDestination
MAIN[23][36]MAIN[24][35]MAIN[19][35]MAIN[24][36]MAIN[21][37]MAIN[21][34]MAIN[18][36]MAIN[19][36]MAIN[13][32]MAIN[25][38]MAIN[22][35]IMUX_IMUX[15]
Source
00000000000PULLUP
00010000001DBL_WS1[2]
00010000010DBL_WN2[2]
00010000100DBL_NE2[1]
00010001000DBL_NW1[1]
00010010000DBL_SE2[1]
00010100000IMUX_FAN_BOUNCE[1]
00011000000OUT[16]
00100000001DBL_NN0[2]
00100000010DBL_NN2[4]
00100000100DBL_EE0[1]
00100001000DBL_EE2[4]
00100010000DBL_ES1[1]
00100100000IMUX_BYP_BOUNCE[6]
00101000000IMUX_FAN_BOUNCE[3]
01000000001DBL_NN1[4]
01000000010DBL_NN0[4]
01000000100DBL_EE1[4]
01000001000DBL_EE0[5]
01000010000DBL_EN2[1]
01000100000IMUX_BYP_BOUNCE[1]
01001000000IMUX_BYP_BOUNCE_S0
10000000001DBL_NN2[1]
10000000010DBL_NN1[1]
10000000100DBL_EE2[1]
10000001000DBL_EE1[1]
10000010000DBL_SW1[1]
10000100000IMUX_FAN_BOUNCE[6]
10001000000OUT[14]
virtex5 INT switchbox INT muxes IMUX_IMUX[16]
BitsDestination
MAIN[22][46]MAIN[18][46]MAIN[19][46]MAIN[24][46]MAIN[20][45]MAIN[20][47]MAIN[25][45]MAIN[22][47]MAIN[18][45]MAIN[13][47]MAIN[19][47]IMUX_IMUX[16]
Source
00000000000PULLUP
00010000001DBL_WW0[2]
00010000010DBL_WW2[5]
00010000100DBL_WS2[2]
00010001000DBL_SS0[1]
00010010000DBL_SS2[5]
00010100000IMUX_BYP_BOUNCE[5]
00011000000IMUX_FAN_BOUNCE[3]
00100000001DBL_WW1[5]
00100000010DBL_WW0[4]
00100000100DBL_WN1[2]
00100001000DBL_SS1[5]
00100010000DBL_SS0[5]
00100100000IMUX_CTRL_BOUNCE_S0
00101000000IMUX_BYP_BOUNCE_S0
01000000001DBL_WW2[2]
01000000010DBL_WW1[2]
01000000100DBL_NW2[1]
01000001000DBL_SS2[2]
01000010000DBL_SS1[2]
01000100000IMUX_FAN_BOUNCE[5]
01001000000OUT[7]
10000000001DBL_SE1[2]
10000000010DBL_SW2[2]
10000000100DBL_NE1[1]
10000001000DBL_ES2[2]
10000010000DBL_EN1[2]
10000100000IMUX_FAN_BOUNCE_S0
10001000000OUT[2]
virtex5 INT switchbox INT muxes IMUX_IMUX[17]
BitsDestination
MAIN[23][57]MAIN[25][57]MAIN[22][57]MAIN[24][57]MAIN[20][58]MAIN[20][56]MAIN[19][58]MAIN[19][56]MAIN[19][57]MAIN[25][58]MAIN[22][56]IMUX_IMUX[17]
Source
00000000000PULLUP
00010000001DBL_WS1_S0
00010000010DBL_WN2_S0
00010000100DBL_NW1[2]
00010001000DBL_NE2[2]
00010010000DBL_SE2[2]
00010100000IMUX_FAN_BOUNCE_S0
00011000000OUT[11]
00100000001DBL_NN1[5]
00100000010DBL_NN0[5]
00100000100DBL_EE0_S3
00100001000DBL_EE1[5]
00100010000DBL_EN2[2]
00100100000IMUX_CTRL_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE[3]
01000000001DBL_NN0_S0
01000000010DBL_NN2[5]
01000000100DBL_EE2[5]
01000001000DBL_EE0[2]
01000010000DBL_ES1[2]
01000100000IMUX_BYP_BOUNCE[5]
01001000000IMUX_BYP_BOUNCE_S4
10000000001DBL_NN2[2]
10000000010DBL_NN1[2]
10000000100DBL_EE1[2]
10000001000DBL_EE2[2]
10000010000DBL_SW1[2]
10000100000IMUX_FAN_BOUNCE[5]
10001000000OUT[21]
virtex5 INT switchbox INT muxes IMUX_IMUX[18]
BitsDestination
MAIN[25][4]MAIN[22][4]MAIN[23][3]MAIN[18][2]MAIN[21][3]MAIN[21][4]MAIN[25][3]MAIN[22][5]MAIN[20][3]MAIN[20][4]MAIN[18][3]IMUX_IMUX[18]
Source
00000000000PULLUP
00010000001DBL_WW0_N5
00010000010DBL_WW1[3]
00010000100DBL_WN1[0]
00010001000DBL_SS1[3]
00010010000DBL_SS0[3]
00010100000IMUX_CTRL_BOUNCE[2]
00011000000IMUX_BYP_BOUNCE_N3
00100000001DBL_WW2[3]
00100000010DBL_WW0[0]
00100000100DBL_WS2[0]
00100001000DBL_SS0_N2
00100010000DBL_SS2[3]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_BYP_BOUNCE[4]
01000000001DBL_WW1[0]
01000000010DBL_WW2[0]
01000000100DBL_NW2_N2
01000001000DBL_SS2[0]
01000010000DBL_SS1[0]
01000100000IMUX_FAN_BOUNCE_N7
01001000000OUT[12]
10000000001DBL_SW2[0]
10000000010DBL_SE1[0]
10000000100DBL_NE1_N2
10000001000DBL_ES2[0]
10000010000DBL_EN1[0]
10000100000IMUX_FAN_BOUNCE[2]
10001000000OUT[18]
virtex5 INT switchbox INT muxes IMUX_IMUX[19]
BitsDestination
MAIN[25][15]MAIN[23][13]MAIN[23][14]MAIN[24][15]MAIN[21][15]MAIN[20][14]MAIN[21][14]MAIN[18][15]MAIN[19][13]MAIN[23][15]MAIN[24][13]IMUX_IMUX[19]
Source
00000000000PULLUP
00010000001DBL_WS1[1]
00010000010DBL_WN2[1]
00010000100DBL_NE2[0]
00010001000DBL_NW1[0]
00010010000DBL_SE2[0]
00010100000IMUX_FAN_BOUNCE[2]
00011000000OUT[0]
00100000001DBL_NN0[1]
00100000010DBL_NN2[3]
00100000100DBL_EE0[0]
00100001000DBL_EE2[3]
00100010000DBL_ES1[0]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_FAN_BOUNCE[4]
01000000001DBL_NN1[3]
01000000010DBL_NN0[3]
01000000100DBL_EE1[3]
01000001000DBL_EE0[4]
01000010000DBL_EN2[0]
01000100000IMUX_CTRL_BOUNCE_N3
01001000000IMUX_BYP_BOUNCE_N7
10000000001DBL_NN2[0]
10000000010DBL_NN1[0]
10000000100DBL_EE2[0]
10000001000DBL_EE1[0]
10000010000DBL_SW1[0]
10000100000IMUX_FAN_BOUNCE_N7
10001000000OUT[5]
virtex5 INT switchbox INT muxes IMUX_IMUX[20]
BitsDestination
MAIN[22][26]MAIN[24][26]MAIN[23][24]MAIN[25][24]MAIN[21][24]MAIN[20][25]MAIN[24][24]MAIN[23][26]MAIN[21][25]MAIN[18][24]MAIN[18][25]IMUX_IMUX[20]
Source
00000000000PULLUP
00010000001DBL_WW0[1]
00010000010DBL_WW2[4]
00010000100DBL_WS2[1]
00010001000DBL_SS0[0]
00010010000DBL_SS2[4]
00010100000IMUX_BYP_BOUNCE[6]
00011000000IMUX_FAN_BOUNCE[4]
00100000001DBL_WW1[4]
00100000010DBL_WW0[3]
00100000100DBL_WN1[1]
00100001000DBL_SS1[4]
00100010000DBL_SS0[4]
00100100000IMUX_BYP_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE_N7
01000000001DBL_WW2[1]
01000000010DBL_WW1[1]
01000000100DBL_NW2[0]
01000001000DBL_SS2[1]
01000010000DBL_SS1[1]
01000100000IMUX_FAN_BOUNCE[6]
01001000000OUT[23]
10000000001DBL_SE1[1]
10000000010DBL_SW2[1]
10000000100DBL_NE1[0]
10000001000DBL_ES2[1]
10000010000DBL_EN1[1]
10000100000IMUX_FAN_BOUNCE[1]
10001000000OUT[9]
virtex5 INT switchbox INT muxes IMUX_IMUX[21]
BitsDestination
MAIN[22][36]MAIN[18][34]MAIN[23][35]MAIN[25][36]MAIN[21][35]MAIN[21][36]MAIN[20][35]MAIN[18][35]MAIN[20][36]MAIN[25][35]MAIN[22][37]IMUX_IMUX[21]
Source
00000000000PULLUP
00010000001DBL_WS1[2]
00010000010DBL_WN2[2]
00010000100DBL_NE2[1]
00010001000DBL_NW1[1]
00010010000DBL_SE2[1]
00010100000IMUX_FAN_BOUNCE[1]
00011000000OUT[16]
00100000001DBL_NN0[2]
00100000010DBL_NN2[4]
00100000100DBL_EE0[1]
00100001000DBL_EE2[4]
00100010000DBL_ES1[1]
00100100000IMUX_BYP_BOUNCE[6]
00101000000IMUX_FAN_BOUNCE[3]
01000000001DBL_NN1[4]
01000000010DBL_NN0[4]
01000000100DBL_EE1[4]
01000001000DBL_EE0[5]
01000010000DBL_EN2[1]
01000100000IMUX_BYP_BOUNCE[1]
01001000000IMUX_BYP_BOUNCE_S0
10000000001DBL_NN2[1]
10000000010DBL_NN1[1]
10000000100DBL_EE2[1]
10000001000DBL_EE1[1]
10000010000DBL_SW1[1]
10000100000IMUX_FAN_BOUNCE[6]
10001000000OUT[14]
virtex5 INT switchbox INT muxes IMUX_IMUX[22]
BitsDestination
MAIN[24][47]MAIN[25][47]MAIN[23][45]MAIN[23][46]MAIN[21][47]MAIN[20][46]MAIN[23][47]MAIN[24][45]MAIN[21][46]MAIN[18][47]MAIN[19][45]IMUX_IMUX[22]
Source
00000000000PULLUP
00010000001DBL_WW0[2]
00010000010DBL_WW2[5]
00010000100DBL_WS2[2]
00010001000DBL_SS0[1]
00010010000DBL_SS2[5]
00010100000IMUX_BYP_BOUNCE[5]
00011000000IMUX_FAN_BOUNCE[3]
00100000001DBL_WW1[5]
00100000010DBL_WW0[4]
00100000100DBL_WN1[2]
00100001000DBL_SS1[5]
00100010000DBL_SS0[5]
00100100000IMUX_CTRL_BOUNCE_S0
00101000000IMUX_BYP_BOUNCE_S0
01000000001DBL_WW2[2]
01000000010DBL_WW1[2]
01000000100DBL_NW2[1]
01000001000DBL_SS2[2]
01000010000DBL_SS1[2]
01000100000IMUX_FAN_BOUNCE[5]
01001000000OUT[7]
10000000001DBL_SE1[2]
10000000010DBL_SW2[2]
10000000100DBL_NE1[1]
10000001000DBL_ES2[2]
10000010000DBL_EN1[2]
10000100000IMUX_FAN_BOUNCE_S0
10001000000OUT[2]
virtex5 INT switchbox INT muxes IMUX_IMUX[23]
BitsDestination
MAIN[24][58]MAIN[25][56]MAIN[23][56]MAIN[22][58]MAIN[21][56]MAIN[20][57]MAIN[21][57]MAIN[18][57]MAIN[18][56]MAIN[24][56]MAIN[23][58]IMUX_IMUX[23]
Source
00000000000PULLUP
00010000001DBL_WS1_S0
00010000010DBL_WN2_S0
00010000100DBL_NW1[2]
00010001000DBL_NE2[2]
00010010000DBL_SE2[2]
00010100000IMUX_FAN_BOUNCE_S0
00011000000OUT[11]
00100000001DBL_NN1[5]
00100000010DBL_NN0[5]
00100000100DBL_EE0_S3
00100001000DBL_EE1[5]
00100010000DBL_EN2[2]
00100100000IMUX_CTRL_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE[3]
01000000001DBL_NN0_S0
01000000010DBL_NN2[5]
01000000100DBL_EE2[5]
01000001000DBL_EE0[2]
01000010000DBL_ES1[2]
01000100000IMUX_BYP_BOUNCE[5]
01001000000IMUX_BYP_BOUNCE_S4
10000000001DBL_NN2[2]
10000000010DBL_NN1[2]
10000000100DBL_EE1[2]
10000001000DBL_EE2[2]
10000010000DBL_SW1[2]
10000100000IMUX_FAN_BOUNCE[5]
10001000000OUT[21]
virtex5 INT switchbox INT muxes IMUX_IMUX[24]
BitsDestination
MAIN[22][6]MAIN[18][6]MAIN[24][6]MAIN[19][6]MAIN[20][5]MAIN[20][7]MAIN[25][5]MAIN[22][7]MAIN[18][5]MAIN[19][7]MAIN[13][7]IMUX_IMUX[24]
Source
00000000000PULLUP
00010000001DBL_WW0_N5
00010000010DBL_WW1[3]
00010000100DBL_WN1[0]
00010001000DBL_SS1[3]
00010010000DBL_SS0[3]
00010100000IMUX_CTRL_BOUNCE[2]
00011000000IMUX_BYP_BOUNCE_N3
00100000001DBL_WW2[3]
00100000010DBL_WW0[0]
00100000100DBL_WS2[0]
00100001000DBL_SS0_N2
00100010000DBL_SS2[3]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_BYP_BOUNCE[4]
01000000001DBL_WW1[0]
01000000010DBL_WW2[0]
01000000100DBL_NW2_N2
01000001000DBL_SS2[0]
01000010000DBL_SS1[0]
01000100000IMUX_FAN_BOUNCE_N7
01001000000OUT[8]
10000000001DBL_SW2[0]
10000000010DBL_SE1[0]
10000000100DBL_NE1_N2
10000001000DBL_ES2[0]
10000010000DBL_EN1[0]
10000100000IMUX_FAN_BOUNCE[2]
10001000000OUT[22]
virtex5 INT switchbox INT muxes IMUX_IMUX[25]
BitsDestination
MAIN[23][17]MAIN[22][17]MAIN[25][17]MAIN[24][17]MAIN[20][18]MAIN[20][16]MAIN[19][18]MAIN[19][17]MAIN[19][16]MAIN[25][18]MAIN[22][16]IMUX_IMUX[25]
Source
00000000000PULLUP
00010000001DBL_WS1[1]
00010000010DBL_WN2[1]
00010000100DBL_NE2[0]
00010001000DBL_NW1[0]
00010010000DBL_SE2[0]
00010100000IMUX_FAN_BOUNCE[2]
00011000000OUT[4]
00100000001DBL_NN0[1]
00100000010DBL_NN2[3]
00100000100DBL_EE0[0]
00100001000DBL_EE2[3]
00100010000DBL_ES1[0]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_FAN_BOUNCE[4]
01000000001DBL_NN1[3]
01000000010DBL_NN0[3]
01000000100DBL_EE1[3]
01000001000DBL_EE0[4]
01000010000DBL_EN2[0]
01000100000IMUX_CTRL_BOUNCE_N3
01001000000IMUX_BYP_BOUNCE_N7
10000000001DBL_NN2[0]
10000000010DBL_NN1[0]
10000000100DBL_EE2[0]
10000001000DBL_EE1[0]
10000010000DBL_SW1[0]
10000100000IMUX_FAN_BOUNCE_N7
10001000000OUT[1]
virtex5 INT switchbox INT muxes IMUX_IMUX[26]
BitsDestination
MAIN[24][28]MAIN[23][28]MAIN[24][27]MAIN[19][27]MAIN[21][29]MAIN[21][26]MAIN[25][30]MAIN[22][27]MAIN[18][28]MAIN[19][28]MAIN[13][24]IMUX_IMUX[26]
Source
00000000000PULLUP
00010000001DBL_WW0[1]
00010000010DBL_WW2[4]
00010000100DBL_WS2[1]
00010001000DBL_SS0[0]
00010010000DBL_SS2[4]
00010100000IMUX_BYP_BOUNCE[6]
00011000000IMUX_FAN_BOUNCE[4]
00100000001DBL_WW1[4]
00100000010DBL_WW0[3]
00100000100DBL_WN1[1]
00100001000DBL_SS1[4]
00100010000DBL_SS0[4]
00100100000IMUX_BYP_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE_N7
01000000001DBL_WW2[1]
01000000010DBL_WW1[1]
01000000100DBL_NW2[0]
01000001000DBL_SS2[1]
01000010000DBL_SS1[1]
01000100000IMUX_FAN_BOUNCE[6]
01001000000OUT[19]
10000000001DBL_SE1[1]
10000000010DBL_SW2[1]
10000000100DBL_NE1[0]
10000001000DBL_ES2[1]
10000010000DBL_EN1[1]
10000100000IMUX_FAN_BOUNCE[1]
10001000000OUT[13]
virtex5 INT switchbox INT muxes IMUX_IMUX[27]
BitsDestination
MAIN[18][38]MAIN[19][38]MAIN[24][38]MAIN[22][38]MAIN[20][37]MAIN[20][39]MAIN[18][37]MAIN[13][39]MAIN[19][39]MAIN[25][37]MAIN[22][39]IMUX_IMUX[27]
Source
00000000000PULLUP
00010000001DBL_WS1[2]
00010000010DBL_WN2[2]
00010000100DBL_NE2[1]
00010001000DBL_NW1[1]
00010010000DBL_SE2[1]
00010100000IMUX_FAN_BOUNCE[1]
00011000000OUT[20]
00100000001DBL_NN0[2]
00100000010DBL_NN2[4]
00100000100DBL_EE0[1]
00100001000DBL_EE2[4]
00100010000DBL_ES1[1]
00100100000IMUX_BYP_BOUNCE[6]
00101000000IMUX_FAN_BOUNCE[3]
01000000001DBL_NN1[4]
01000000010DBL_NN0[4]
01000000100DBL_EE1[4]
01000001000DBL_EE0[5]
01000010000DBL_EN2[1]
01000100000IMUX_BYP_BOUNCE[1]
01001000000IMUX_BYP_BOUNCE_S0
10000000001DBL_NN2[1]
10000000010DBL_NN1[1]
10000000100DBL_EE2[1]
10000001000DBL_EE1[1]
10000010000DBL_SW1[1]
10000100000IMUX_FAN_BOUNCE[6]
10001000000OUT[10]
virtex5 INT switchbox INT muxes IMUX_IMUX[28]
BitsDestination
MAIN[24][49]MAIN[23][49]MAIN[22][49]MAIN[25][49]MAIN[20][50]MAIN[20][48]MAIN[25][50]MAIN[22][48]MAIN[19][50]MAIN[19][49]MAIN[19][48]IMUX_IMUX[28]
Source
00000000000PULLUP
00010000001DBL_WW0[2]
00010000010DBL_WW2[5]
00010000100DBL_WS2[2]
00010001000DBL_SS0[1]
00010010000DBL_SS2[5]
00010100000IMUX_BYP_BOUNCE[5]
00011000000IMUX_FAN_BOUNCE[3]
00100000001DBL_WW1[5]
00100000010DBL_WW0[4]
00100000100DBL_WN1[2]
00100001000DBL_SS1[5]
00100010000DBL_SS0[5]
00100100000IMUX_CTRL_BOUNCE_S0
00101000000IMUX_BYP_BOUNCE_S0
01000000001DBL_WW2[2]
01000000010DBL_WW1[2]
01000000100DBL_NW2[1]
01000001000DBL_SS2[2]
01000010000DBL_SS1[2]
01000100000IMUX_FAN_BOUNCE[5]
01001000000OUT[3]
10000000001DBL_SE1[2]
10000000010DBL_SW2[2]
10000000100DBL_NE1[1]
10000001000DBL_ES2[2]
10000010000DBL_EN1[2]
10000100000IMUX_FAN_BOUNCE_S0
10001000000OUT[6]
virtex5 INT switchbox INT muxes IMUX_IMUX[29]
BitsDestination
MAIN[23][60]MAIN[19][59]MAIN[24][59]MAIN[24][60]MAIN[21][61]MAIN[21][58]MAIN[18][60]MAIN[13][56]MAIN[19][60]MAIN[25][62]MAIN[22][59]IMUX_IMUX[29]
Source
00000000000PULLUP
00010000001DBL_WS1_S0
00010000010DBL_WN2_S0
00010000100DBL_NW1[2]
00010001000DBL_NE2[2]
00010010000DBL_SE2[2]
00010100000IMUX_FAN_BOUNCE_S0
00011000000OUT[15]
00100000001DBL_NN1[5]
00100000010DBL_NN0[5]
00100000100DBL_EE0_S3
00100001000DBL_EE1[5]
00100010000DBL_EN2[2]
00100100000IMUX_CTRL_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE[3]
01000000001DBL_NN0_S0
01000000010DBL_NN2[5]
01000000100DBL_EE2[5]
01000001000DBL_EE0[2]
01000010000DBL_ES1[2]
01000100000IMUX_BYP_BOUNCE[5]
01001000000IMUX_BYP_BOUNCE_S4
10000000001DBL_NN2[2]
10000000010DBL_NN1[2]
10000000100DBL_EE1[2]
10000001000DBL_EE2[2]
10000010000DBL_SW1[2]
10000100000IMUX_FAN_BOUNCE[5]
10001000000OUT[17]
virtex5 INT switchbox INT muxes IMUX_IMUX[30]
BitsDestination
MAIN[24][7]MAIN[25][7]MAIN[23][6]MAIN[23][5]MAIN[21][7]MAIN[20][6]MAIN[23][7]MAIN[24][5]MAIN[21][6]MAIN[19][5]MAIN[18][7]IMUX_IMUX[30]
Source
00000000000PULLUP
00010000001DBL_WW0_N5
00010000010DBL_WW1[3]
00010000100DBL_WN1[0]
00010001000DBL_SS1[3]
00010010000DBL_SS0[3]
00010100000IMUX_CTRL_BOUNCE[2]
00011000000IMUX_BYP_BOUNCE_N3
00100000001DBL_WW2[3]
00100000010DBL_WW0[0]
00100000100DBL_WS2[0]
00100001000DBL_SS0_N2
00100010000DBL_SS2[3]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_BYP_BOUNCE[4]
01000000001DBL_WW1[0]
01000000010DBL_WW2[0]
01000000100DBL_NW2_N2
01000001000DBL_SS2[0]
01000010000DBL_SS1[0]
01000100000IMUX_FAN_BOUNCE_N7
01001000000OUT[8]
10000000001DBL_SW2[0]
10000000010DBL_SE1[0]
10000000100DBL_NE1_N2
10000001000DBL_ES2[0]
10000010000DBL_EN1[0]
10000100000IMUX_FAN_BOUNCE[2]
10001000000OUT[22]
virtex5 INT switchbox INT muxes IMUX_IMUX[31]
BitsDestination
MAIN[24][18]MAIN[23][16]MAIN[25][16]MAIN[22][18]MAIN[21][16]MAIN[20][17]MAIN[21][17]MAIN[18][16]MAIN[18][17]MAIN[24][16]MAIN[23][18]IMUX_IMUX[31]
Source
00000000000PULLUP
00010000001DBL_WS1[1]
00010000010DBL_WN2[1]
00010000100DBL_NE2[0]
00010001000DBL_NW1[0]
00010010000DBL_SE2[0]
00010100000IMUX_FAN_BOUNCE[2]
00011000000OUT[4]
00100000001DBL_NN0[1]
00100000010DBL_NN2[3]
00100000100DBL_EE0[0]
00100001000DBL_EE2[3]
00100010000DBL_ES1[0]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_FAN_BOUNCE[4]
01000000001DBL_NN1[3]
01000000010DBL_NN0[3]
01000000100DBL_EE1[3]
01000001000DBL_EE0[4]
01000010000DBL_EN2[0]
01000100000IMUX_CTRL_BOUNCE_N3
01001000000IMUX_BYP_BOUNCE_N7
10000000001DBL_NN2[0]
10000000010DBL_NN1[0]
10000000100DBL_EE2[0]
10000001000DBL_EE1[0]
10000010000DBL_SW1[0]
10000100000IMUX_FAN_BOUNCE_N7
10001000000OUT[1]
virtex5 INT switchbox INT muxes IMUX_IMUX[32]
BitsDestination
MAIN[25][28]MAIN[22][28]MAIN[18][26]MAIN[23][27]MAIN[21][27]MAIN[21][28]MAIN[25][27]MAIN[22][29]MAIN[20][27]MAIN[18][27]MAIN[20][28]IMUX_IMUX[32]
Source
00000000000PULLUP
00010000001DBL_WW0[1]
00010000010DBL_WW2[4]
00010000100DBL_WS2[1]
00010001000DBL_SS0[0]
00010010000DBL_SS2[4]
00010100000IMUX_BYP_BOUNCE[6]
00011000000IMUX_FAN_BOUNCE[4]
00100000001DBL_WW1[4]
00100000010DBL_WW0[3]
00100000100DBL_WN1[1]
00100001000DBL_SS1[4]
00100010000DBL_SS0[4]
00100100000IMUX_BYP_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE_N7
01000000001DBL_WW2[1]
01000000010DBL_WW1[1]
01000000100DBL_NW2[0]
01000001000DBL_SS2[1]
01000010000DBL_SS1[1]
01000100000IMUX_FAN_BOUNCE[6]
01001000000OUT[19]
10000000001DBL_SE1[1]
10000000010DBL_SW2[1]
10000000100DBL_NE1[0]
10000001000DBL_ES2[1]
10000010000DBL_EN1[1]
10000100000IMUX_FAN_BOUNCE[1]
10001000000OUT[13]
virtex5 INT switchbox INT muxes IMUX_IMUX[33]
BitsDestination
MAIN[25][39]MAIN[23][37]MAIN[23][38]MAIN[24][39]MAIN[21][39]MAIN[20][38]MAIN[21][38]MAIN[18][39]MAIN[19][37]MAIN[23][39]MAIN[24][37]IMUX_IMUX[33]
Source
00000000000PULLUP
00010000001DBL_WS1[2]
00010000010DBL_WN2[2]
00010000100DBL_NE2[1]
00010001000DBL_NW1[1]
00010010000DBL_SE2[1]
00010100000IMUX_FAN_BOUNCE[1]
00011000000OUT[20]
00100000001DBL_NN0[2]
00100000010DBL_NN2[4]
00100000100DBL_EE0[1]
00100001000DBL_EE2[4]
00100010000DBL_ES1[1]
00100100000IMUX_BYP_BOUNCE[6]
00101000000IMUX_FAN_BOUNCE[3]
01000000001DBL_NN1[4]
01000000010DBL_NN0[4]
01000000100DBL_EE1[4]
01000001000DBL_EE0[5]
01000010000DBL_EN2[1]
01000100000IMUX_BYP_BOUNCE[1]
01001000000IMUX_BYP_BOUNCE_S0
10000000001DBL_NN2[1]
10000000010DBL_NN1[1]
10000000100DBL_EE2[1]
10000001000DBL_EE1[1]
10000010000DBL_SW1[1]
10000100000IMUX_FAN_BOUNCE[6]
10001000000OUT[10]
virtex5 INT switchbox INT muxes IMUX_IMUX[34]
BitsDestination
MAIN[22][50]MAIN[24][50]MAIN[23][48]MAIN[25][48]MAIN[21][48]MAIN[20][49]MAIN[24][48]MAIN[23][50]MAIN[21][49]MAIN[18][48]MAIN[18][49]IMUX_IMUX[34]
Source
00000000000PULLUP
00010000001DBL_WW0[2]
00010000010DBL_WW2[5]
00010000100DBL_WS2[2]
00010001000DBL_SS0[1]
00010010000DBL_SS2[5]
00010100000IMUX_BYP_BOUNCE[5]
00011000000IMUX_FAN_BOUNCE[3]
00100000001DBL_WW1[5]
00100000010DBL_WW0[4]
00100000100DBL_WN1[2]
00100001000DBL_SS1[5]
00100010000DBL_SS0[5]
00100100000IMUX_CTRL_BOUNCE_S0
00101000000IMUX_BYP_BOUNCE_S0
01000000001DBL_WW2[2]
01000000010DBL_WW1[2]
01000000100DBL_NW2[1]
01000001000DBL_SS2[2]
01000010000DBL_SS1[2]
01000100000IMUX_FAN_BOUNCE[5]
01001000000OUT[3]
10000000001DBL_SE1[2]
10000000010DBL_SW2[2]
10000000100DBL_NE1[1]
10000001000DBL_ES2[2]
10000010000DBL_EN1[2]
10000100000IMUX_FAN_BOUNCE_S0
10001000000OUT[6]
virtex5 INT switchbox INT muxes IMUX_IMUX[35]
BitsDestination
MAIN[22][60]MAIN[23][59]MAIN[18][58]MAIN[25][60]MAIN[21][59]MAIN[21][60]MAIN[20][59]MAIN[20][60]MAIN[18][59]MAIN[25][59]MAIN[22][61]IMUX_IMUX[35]
Source
00000000000PULLUP
00010000001DBL_WS1_S0
00010000010DBL_WN2_S0
00010000100DBL_NW1[2]
00010001000DBL_NE2[2]
00010010000DBL_SE2[2]
00010100000IMUX_FAN_BOUNCE_S0
00011000000OUT[15]
00100000001DBL_NN1[5]
00100000010DBL_NN0[5]
00100000100DBL_EE0_S3
00100001000DBL_EE1[5]
00100010000DBL_EN2[2]
00100100000IMUX_CTRL_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE[3]
01000000001DBL_NN0_S0
01000000010DBL_NN2[5]
01000000100DBL_EE2[5]
01000001000DBL_EE0[2]
01000010000DBL_ES1[2]
01000100000IMUX_BYP_BOUNCE[5]
01001000000IMUX_BYP_BOUNCE_S4
10000000001DBL_NN2[2]
10000000010DBL_NN1[2]
10000000100DBL_EE1[2]
10000001000DBL_EE2[2]
10000010000DBL_SW1[2]
10000100000IMUX_FAN_BOUNCE[5]
10001000000OUT[17]
virtex5 INT switchbox INT muxes IMUX_IMUX[36]
BitsDestination
MAIN[24][9]MAIN[23][9]MAIN[25][9]MAIN[22][9]MAIN[20][10]MAIN[20][8]MAIN[25][10]MAIN[22][8]MAIN[19][10]MAIN[19][8]MAIN[19][9]IMUX_IMUX[36]
Source
00000000000PULLUP
00010000001DBL_WW0_N5
00010000010DBL_WW1[3]
00010000100DBL_WN1[0]
00010001000DBL_SS1[3]
00010010000DBL_SS0[3]
00010100000IMUX_CTRL_BOUNCE[2]
00011000000IMUX_BYP_BOUNCE_N3
00100000001DBL_WW2[3]
00100000010DBL_WW0[0]
00100000100DBL_WS2[0]
00100001000DBL_SS0_N2
00100010000DBL_SS2[3]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_BYP_BOUNCE[4]
01000000001DBL_WW1[0]
01000000010DBL_WW2[0]
01000000100DBL_NW2_N2
01000001000DBL_SS2[0]
01000010000DBL_SS1[0]
01000100000IMUX_FAN_BOUNCE_N7
01001000000OUT[8]
10000000001DBL_SW2[0]
10000000010DBL_SE1[0]
10000000100DBL_NE1_N2
10000001000DBL_ES2[0]
10000010000DBL_EN1[0]
10000100000IMUX_FAN_BOUNCE[2]
10001000000OUT[22]
virtex5 INT switchbox INT muxes IMUX_IMUX[37]
BitsDestination
MAIN[23][20]MAIN[24][19]MAIN[19][19]MAIN[24][20]MAIN[21][21]MAIN[21][18]MAIN[18][20]MAIN[19][20]MAIN[13][16]MAIN[25][22]MAIN[22][19]IMUX_IMUX[37]
Source
00000000000PULLUP
00010000001DBL_WS1[1]
00010000010DBL_WN2[1]
00010000100DBL_NE2[0]
00010001000DBL_NW1[0]
00010010000DBL_SE2[0]
00010100000IMUX_FAN_BOUNCE[2]
00011000000OUT[4]
00100000001DBL_NN0[1]
00100000010DBL_NN2[3]
00100000100DBL_EE0[0]
00100001000DBL_EE2[3]
00100010000DBL_ES1[0]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_FAN_BOUNCE[4]
01000000001DBL_NN1[3]
01000000010DBL_NN0[3]
01000000100DBL_EE1[3]
01000001000DBL_EE0[4]
01000010000DBL_EN2[0]
01000100000IMUX_CTRL_BOUNCE_N3
01001000000IMUX_BYP_BOUNCE_N7
10000000001DBL_NN2[0]
10000000010DBL_NN1[0]
10000000100DBL_EE2[0]
10000001000DBL_EE1[0]
10000010000DBL_SW1[0]
10000100000IMUX_FAN_BOUNCE_N7
10001000000OUT[1]
virtex5 INT switchbox INT muxes IMUX_IMUX[38]
BitsDestination
MAIN[22][30]MAIN[18][30]MAIN[19][30]MAIN[24][30]MAIN[20][29]MAIN[20][31]MAIN[25][29]MAIN[22][31]MAIN[18][29]MAIN[13][31]MAIN[19][31]IMUX_IMUX[38]
Source
00000000000PULLUP
00010000001DBL_WW0[1]
00010000010DBL_WW2[4]
00010000100DBL_WS2[1]
00010001000DBL_SS0[0]
00010010000DBL_SS2[4]
00010100000IMUX_BYP_BOUNCE[6]
00011000000IMUX_FAN_BOUNCE[4]
00100000001DBL_WW1[4]
00100000010DBL_WW0[3]
00100000100DBL_WN1[1]
00100001000DBL_SS1[4]
00100010000DBL_SS0[4]
00100100000IMUX_BYP_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE_N7
01000000001DBL_WW2[1]
01000000010DBL_WW1[1]
01000000100DBL_NW2[0]
01000001000DBL_SS2[1]
01000010000DBL_SS1[1]
01000100000IMUX_FAN_BOUNCE[6]
01001000000OUT[19]
10000000001DBL_SE1[1]
10000000010DBL_SW2[1]
10000000100DBL_NE1[0]
10000001000DBL_ES2[1]
10000010000DBL_EN1[1]
10000100000IMUX_FAN_BOUNCE[1]
10001000000OUT[13]
virtex5 INT switchbox INT muxes IMUX_IMUX[39]
BitsDestination
MAIN[23][41]MAIN[22][41]MAIN[25][41]MAIN[24][41]MAIN[20][42]MAIN[20][40]MAIN[19][42]MAIN[19][41]MAIN[19][40]MAIN[25][42]MAIN[22][40]IMUX_IMUX[39]
Source
00000000000PULLUP
00010000001DBL_WS1[2]
00010000010DBL_WN2[2]
00010000100DBL_NE2[1]
00010001000DBL_NW1[1]
00010010000DBL_SE2[1]
00010100000IMUX_FAN_BOUNCE[1]
00011000000OUT[20]
00100000001DBL_NN0[2]
00100000010DBL_NN2[4]
00100000100DBL_EE0[1]
00100001000DBL_EE2[4]
00100010000DBL_ES1[1]
00100100000IMUX_BYP_BOUNCE[6]
00101000000IMUX_FAN_BOUNCE[3]
01000000001DBL_NN1[4]
01000000010DBL_NN0[4]
01000000100DBL_EE1[4]
01000001000DBL_EE0[5]
01000010000DBL_EN2[1]
01000100000IMUX_BYP_BOUNCE[1]
01001000000IMUX_BYP_BOUNCE_S0
10000000001DBL_NN2[1]
10000000010DBL_NN1[1]
10000000100DBL_EE2[1]
10000001000DBL_EE1[1]
10000010000DBL_SW1[1]
10000100000IMUX_FAN_BOUNCE[6]
10001000000OUT[10]
virtex5 INT switchbox INT muxes IMUX_IMUX[40]
BitsDestination
MAIN[24][52]MAIN[23][52]MAIN[24][51]MAIN[19][51]MAIN[21][53]MAIN[21][50]MAIN[25][54]MAIN[22][51]MAIN[18][52]MAIN[19][52]MAIN[13][48]IMUX_IMUX[40]
Source
00000000000PULLUP
00010000001DBL_WW0[2]
00010000010DBL_WW2[5]
00010000100DBL_WS2[2]
00010001000DBL_SS0[1]
00010010000DBL_SS2[5]
00010100000IMUX_BYP_BOUNCE[5]
00011000000IMUX_FAN_BOUNCE[3]
00100000001DBL_WW1[5]
00100000010DBL_WW0[4]
00100000100DBL_WN1[2]
00100001000DBL_SS1[5]
00100010000DBL_SS0[5]
00100100000IMUX_CTRL_BOUNCE_S0
00101000000IMUX_BYP_BOUNCE_S0
01000000001DBL_WW2[2]
01000000010DBL_WW1[2]
01000000100DBL_NW2[1]
01000001000DBL_SS2[2]
01000010000DBL_SS1[2]
01000100000IMUX_FAN_BOUNCE[5]
01001000000OUT[3]
10000000001DBL_SE1[2]
10000000010DBL_SW2[2]
10000000100DBL_NE1[1]
10000001000DBL_ES2[2]
10000010000DBL_EN1[2]
10000100000IMUX_FAN_BOUNCE_S0
10001000000OUT[6]
virtex5 INT switchbox INT muxes IMUX_IMUX[41]
BitsDestination
MAIN[18][62]MAIN[24][62]MAIN[19][62]MAIN[22][62]MAIN[20][61]MAIN[20][63]MAIN[18][61]MAIN[19][63]MAIN[13][63]MAIN[25][61]MAIN[22][63]IMUX_IMUX[41]
Source
00000000000PULLUP
00010000001DBL_WS1_S0
00010000010DBL_WN2_S0
00010000100DBL_NW1[2]
00010001000DBL_NE2[2]
00010010000DBL_SE2[2]
00010100000IMUX_FAN_BOUNCE_S0
00011000000OUT[15]
00100000001DBL_NN1[5]
00100000010DBL_NN0[5]
00100000100DBL_EE0_S3
00100001000DBL_EE1[5]
00100010000DBL_EN2[2]
00100100000IMUX_CTRL_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE[3]
01000000001DBL_NN0_S0
01000000010DBL_NN2[5]
01000000100DBL_EE2[5]
01000001000DBL_EE0[2]
01000010000DBL_ES1[2]
01000100000IMUX_BYP_BOUNCE[5]
01001000000IMUX_BYP_BOUNCE_S4
10000000001DBL_NN2[2]
10000000010DBL_NN1[2]
10000000100DBL_EE1[2]
10000001000DBL_EE2[2]
10000010000DBL_SW1[2]
10000100000IMUX_FAN_BOUNCE[5]
10001000000OUT[17]
virtex5 INT switchbox INT muxes IMUX_IMUX[42]
BitsDestination
MAIN[22][10]MAIN[24][10]MAIN[25][8]MAIN[23][8]MAIN[21][8]MAIN[20][9]MAIN[24][8]MAIN[23][10]MAIN[21][9]MAIN[18][9]MAIN[18][8]IMUX_IMUX[42]
Source
00000000000PULLUP
00010000001DBL_WW0_N5
00010000010DBL_WW1[3]
00010000100DBL_WN1[0]
00010001000DBL_SS1[3]
00010010000DBL_SS0[3]
00010100000IMUX_CTRL_BOUNCE[2]
00011000000IMUX_BYP_BOUNCE_N3
00100000001DBL_WW2[3]
00100000010DBL_WW0[0]
00100000100DBL_WS2[0]
00100001000DBL_SS0_N2
00100010000DBL_SS2[3]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_BYP_BOUNCE[4]
01000000001DBL_WW1[0]
01000000010DBL_WW2[0]
01000000100DBL_NW2_N2
01000001000DBL_SS2[0]
01000010000DBL_SS1[0]
01000100000IMUX_FAN_BOUNCE_N7
01001000000OUT[8]
10000000001DBL_SW2[0]
10000000010DBL_SE1[0]
10000000100DBL_NE1_N2
10000001000DBL_ES2[0]
10000010000DBL_EN1[0]
10000100000IMUX_FAN_BOUNCE[2]
10001000000OUT[22]
virtex5 INT switchbox INT muxes IMUX_IMUX[43]
BitsDestination
MAIN[22][20]MAIN[18][18]MAIN[23][19]MAIN[25][20]MAIN[21][19]MAIN[21][20]MAIN[20][19]MAIN[18][19]MAIN[20][20]MAIN[25][19]MAIN[22][21]IMUX_IMUX[43]
Source
00000000000PULLUP
00010000001DBL_WS1[1]
00010000010DBL_WN2[1]
00010000100DBL_NE2[0]
00010001000DBL_NW1[0]
00010010000DBL_SE2[0]
00010100000IMUX_FAN_BOUNCE[2]
00011000000OUT[4]
00100000001DBL_NN0[1]
00100000010DBL_NN2[3]
00100000100DBL_EE0[0]
00100001000DBL_EE2[3]
00100010000DBL_ES1[0]
00100100000IMUX_BYP_BOUNCE[2]
00101000000IMUX_FAN_BOUNCE[4]
01000000001DBL_NN1[3]
01000000010DBL_NN0[3]
01000000100DBL_EE1[3]
01000001000DBL_EE0[4]
01000010000DBL_EN2[0]
01000100000IMUX_CTRL_BOUNCE_N3
01001000000IMUX_BYP_BOUNCE_N7
10000000001DBL_NN2[0]
10000000010DBL_NN1[0]
10000000100DBL_EE2[0]
10000001000DBL_EE1[0]
10000010000DBL_SW1[0]
10000100000IMUX_FAN_BOUNCE_N7
10001000000OUT[1]
virtex5 INT switchbox INT muxes IMUX_IMUX[44]
BitsDestination
MAIN[24][31]MAIN[25][31]MAIN[23][29]MAIN[23][30]MAIN[21][31]MAIN[20][30]MAIN[23][31]MAIN[24][29]MAIN[21][30]MAIN[18][31]MAIN[19][29]IMUX_IMUX[44]
Source
00000000000PULLUP
00010000001DBL_WW0[1]
00010000010DBL_WW2[4]
00010000100DBL_WS2[1]
00010001000DBL_SS0[0]
00010010000DBL_SS2[4]
00010100000IMUX_BYP_BOUNCE[6]
00011000000IMUX_FAN_BOUNCE[4]
00100000001DBL_WW1[4]
00100000010DBL_WW0[3]
00100000100DBL_WN1[1]
00100001000DBL_SS1[4]
00100010000DBL_SS0[4]
00100100000IMUX_BYP_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE_N7
01000000001DBL_WW2[1]
01000000010DBL_WW1[1]
01000000100DBL_NW2[0]
01000001000DBL_SS2[1]
01000010000DBL_SS1[1]
01000100000IMUX_FAN_BOUNCE[6]
01001000000OUT[19]
10000000001DBL_SE1[1]
10000000010DBL_SW2[1]
10000000100DBL_NE1[0]
10000001000DBL_ES2[1]
10000010000DBL_EN1[1]
10000100000IMUX_FAN_BOUNCE[1]
10001000000OUT[13]
virtex5 INT switchbox INT muxes IMUX_IMUX[45]
BitsDestination
MAIN[24][42]MAIN[23][40]MAIN[25][40]MAIN[22][42]MAIN[21][40]MAIN[20][41]MAIN[21][41]MAIN[18][40]MAIN[18][41]MAIN[24][40]MAIN[23][42]IMUX_IMUX[45]
Source
00000000000PULLUP
00010000001DBL_WS1[2]
00010000010DBL_WN2[2]
00010000100DBL_NE2[1]
00010001000DBL_NW1[1]
00010010000DBL_SE2[1]
00010100000IMUX_FAN_BOUNCE[1]
00011000000OUT[20]
00100000001DBL_NN0[2]
00100000010DBL_NN2[4]
00100000100DBL_EE0[1]
00100001000DBL_EE2[4]
00100010000DBL_ES1[1]
00100100000IMUX_BYP_BOUNCE[6]
00101000000IMUX_FAN_BOUNCE[3]
01000000001DBL_NN1[4]
01000000010DBL_NN0[4]
01000000100DBL_EE1[4]
01000001000DBL_EE0[5]
01000010000DBL_EN2[1]
01000100000IMUX_BYP_BOUNCE[1]
01001000000IMUX_BYP_BOUNCE_S0
10000000001DBL_NN2[1]
10000000010DBL_NN1[1]
10000000100DBL_EE2[1]
10000001000DBL_EE1[1]
10000010000DBL_SW1[1]
10000100000IMUX_FAN_BOUNCE[6]
10001000000OUT[10]
virtex5 INT switchbox INT muxes IMUX_IMUX[46]
BitsDestination
MAIN[25][52]MAIN[22][52]MAIN[18][50]MAIN[23][51]MAIN[21][51]MAIN[21][52]MAIN[25][51]MAIN[22][53]MAIN[20][51]MAIN[18][51]MAIN[20][52]IMUX_IMUX[46]
Source
00000000000PULLUP
00010000001DBL_WW0[2]
00010000010DBL_WW2[5]
00010000100DBL_WS2[2]
00010001000DBL_SS0[1]
00010010000DBL_SS2[5]
00010100000IMUX_BYP_BOUNCE[5]
00011000000IMUX_FAN_BOUNCE[3]
00100000001DBL_WW1[5]
00100000010DBL_WW0[4]
00100000100DBL_WN1[2]
00100001000DBL_SS1[5]
00100010000DBL_SS0[5]
00100100000IMUX_CTRL_BOUNCE_S0
00101000000IMUX_BYP_BOUNCE_S0
01000000001DBL_WW2[2]
01000000010DBL_WW1[2]
01000000100DBL_NW2[1]
01000001000DBL_SS2[2]
01000010000DBL_SS1[2]
01000100000IMUX_FAN_BOUNCE[5]
01001000000OUT[3]
10000000001DBL_SE1[2]
10000000010DBL_SW2[2]
10000000100DBL_NE1[1]
10000001000DBL_ES2[2]
10000010000DBL_EN1[2]
10000100000IMUX_FAN_BOUNCE_S0
10001000000OUT[6]
virtex5 INT switchbox INT muxes IMUX_IMUX[47]
BitsDestination
MAIN[25][63]MAIN[23][62]MAIN[23][61]MAIN[24][63]MAIN[21][63]MAIN[20][62]MAIN[21][62]MAIN[19][61]MAIN[18][63]MAIN[23][63]MAIN[24][61]IMUX_IMUX[47]
Source
00000000000PULLUP
00010000001DBL_WS1_S0
00010000010DBL_WN2_S0
00010000100DBL_NW1[2]
00010001000DBL_NE2[2]
00010010000DBL_SE2[2]
00010100000IMUX_FAN_BOUNCE_S0
00011000000OUT[15]
00100000001DBL_NN1[5]
00100000010DBL_NN0[5]
00100000100DBL_EE0_S3
00100001000DBL_EE1[5]
00100010000DBL_EN2[2]
00100100000IMUX_CTRL_BOUNCE[1]
00101000000IMUX_BYP_BOUNCE[3]
01000000001DBL_NN0_S0
01000000010DBL_NN2[5]
01000000100DBL_EE2[5]
01000001000DBL_EE0[2]
01000010000DBL_ES1[2]
01000100000IMUX_BYP_BOUNCE[5]
01001000000IMUX_BYP_BOUNCE_S4
10000000001DBL_NN2[2]
10000000010DBL_NN1[2]
10000000100DBL_EE1[2]
10000001000DBL_EE2[2]
10000010000DBL_SW1[2]
10000100000IMUX_FAN_BOUNCE[5]
10001000000OUT[17]

Bitstream

virtex5 INT rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 INT: mux PENT_WW0_S0 bit 1 INT: mux PENT_WW0_S0 bit 0 INT: mux PENT_WW0_S0 bit 3 INT: mux PENT_NW0[2] bit 3 INT: mux PENT_WW0_S0 bit 5 INT: mux PENT_WW0_S0 bit 4 INT: mux DBL_NW0[2] bit 3 INT: mux DBL_WW0_S0 bit 2 INT: mux DBL_WW0_S0 bit 6 INT: mux DBL_WW0_S0 bit 7 INT: mux DBL_NW0[2] bit 1 INT: mux DBL_WW0_S0 bit 0 INT: mux DBL_WW0_S0 bit 5 INT: mux IMUX_IMUX[41] bit 2 INT: mux IMUX_FAN[7] bit 1 INT: mux LV[0] bit 6 INT: mux LH[0] bit 6 INT: mux IMUX_FAN[6] bit 3 INT: mux IMUX_IMUX[47] bit 2 INT: mux IMUX_IMUX[41] bit 3 INT: mux IMUX_IMUX[41] bit 5 INT: mux IMUX_IMUX[47] bit 6 INT: mux IMUX_IMUX[41] bit 0 INT: mux IMUX_IMUX[47] bit 1 INT: mux IMUX_IMUX[47] bit 7 INT: mux IMUX_IMUX[47] bit 10 - -
B62 INT: mux PENT_NW0[2] bit 4 INT: mux PENT_NW0[2] bit 6 INT: mux PENT_NW0[2] bit 0 INT: mux PENT_WW0_S0 bit 2 INT: mux PENT_NW0[2] bit 5 INT: mux PENT_NW0[2] bit 7 INT: mux DBL_NW0[2] bit 6 INT: mux DBL_NW0[2] bit 8 INT: mux DBL_NW0[2] bit 9 INT: mux DBL_NW0[2] bit 7 INT: mux DBL_NW0[2] bit 4 INT: mux DBL_NW0[2] bit 0 INT: mux DBL_WW0_S0 bit 4 INT: mux DBL_NW0[2] bit 5 INT: mux LH[0] bit 1 INT: mux LV[0] bit 1 INT: mux LH[0] bit 3 INT: mux LV[0] bit 3 INT: mux IMUX_IMUX[41] bit 10 INT: mux IMUX_IMUX[41] bit 8 INT: mux IMUX_IMUX[47] bit 5 INT: mux IMUX_IMUX[47] bit 4 INT: mux IMUX_IMUX[41] bit 7 INT: mux IMUX_IMUX[47] bit 9 INT: mux IMUX_IMUX[41] bit 9 INT: mux IMUX_IMUX[29] bit 1 - -
B61 INT: mux PENT_NW0[2] bit 1 INT: mux PENT_WW0_S0 bit 6 INT: mux PENT_NW0[2] bit 2 INT: mux PENT_NE0[2] bit 3 INT: mux PENT_NE0[2] bit 6 INT: mux PENT_WW0_S0 bit 7 INT: mux DBL_NW0[2] bit 2 INT: mux DBL_WW0_S0 bit 8 INT: mux DBL_WW0_S0 bit 9 INT: mux DBL_EE0_S3 bit 2 INT: mux DBL_NE0[2] bit 1 INT: mux DBL_WW0_S0 bit 1 INT: mux DBL_WW0_S0 bit 3 INT: mux DBL_NE0[2] bit 4 INT: mux LV[0] bit 2 INT: mux IMUX_BYP[6] bit 3 INT: mux IMUX_BYP[3] bit 4 INT: mux LH[0] bit 4 INT: mux IMUX_IMUX[41] bit 4 INT: mux IMUX_IMUX[47] bit 3 INT: mux IMUX_IMUX[41] bit 6 INT: mux IMUX_IMUX[29] bit 6 INT: mux IMUX_IMUX[35] bit 0 INT: mux IMUX_IMUX[47] bit 8 INT: mux IMUX_IMUX[47] bit 0 INT: mux IMUX_IMUX[41] bit 1 - -
B60 INT: mux PENT_EE0[5] bit 0 INT: mux PENT_NE0[2] bit 1 INT: mux PENT_EE0[5] bit 6 INT: mux PENT_EE0[5] bit 2 INT: mux PENT_NE0[2] bit 7 INT: mux PENT_EE0[5] bit 7 INT: mux DBL_NE0[2] bit 8 INT: mux DBL_EE0_S3 bit 8 INT: mux DBL_EE0_S3 bit 9 INT: mux DBL_NE0[2] bit 9 INT: mux DBL_EE0_S3 bit 0 INT: mux DBL_EE0_S3 bit 5 INT: mux IMUX_FAN[5] bit 7 INT: mux DBL_NE0[2] bit 3 INT: mux LH[0] bit 2 INT: mux LV[0] bit 0 INT: mux LH[0] bit 0 INT: mux LV[0] bit 4 INT: mux IMUX_IMUX[29] bit 4 INT: mux IMUX_IMUX[29] bit 2 INT: mux IMUX_IMUX[35] bit 3 INT: mux IMUX_IMUX[35] bit 5 INT: mux IMUX_IMUX[35] bit 10 INT: mux IMUX_IMUX[29] bit 10 INT: mux IMUX_IMUX[29] bit 7 INT: mux IMUX_IMUX[35] bit 7 - -
B59 INT: mux PENT_NE0[2] bit 4 INT: mux PENT_EE0[5] bit 4 INT: mux PENT_EE0[5] bit 1 INT: mux PENT_EE0[5] bit 3 INT: mux PENT_NE0[2] bit 5 INT: mux PENT_EE0[5] bit 5 INT: mux DBL_NE0[2] bit 6 INT: mux DBL_EE0_S3 bit 6 INT: mux DBL_EE0_S3 bit 7 INT: mux DBL_NE0[2] bit 7 INT: mux DBL_EE0_S3 bit 1 INT: mux DBL_EE0_S3 bit 4 INT: mux IMUX_FAN[4] bit 9 INT: mux DBL_EE0_S3 bit 3 INT: mux LV[0] bit 5 INT: mux LV[0] bit 9 INT: mux LH[0] bit 9 INT: mux LH[0] bit 5 INT: mux IMUX_IMUX[35] bit 2 INT: mux IMUX_IMUX[29] bit 9 INT: mux IMUX_IMUX[35] bit 4 INT: mux IMUX_IMUX[35] bit 6 INT: mux IMUX_IMUX[29] bit 0 INT: mux IMUX_IMUX[35] bit 9 INT: mux IMUX_IMUX[29] bit 8 INT: mux IMUX_IMUX[35] bit 1 - -
B58 INT: mux PENT_NE0[2] bit 0 INT: mux PENT_NN0[2] bit 4 INT: mux PENT_EN0[2] bit 6 INT: mux PENT_NE0[2] bit 2 INT: mux PENT_NN0[2] bit 2 INT: mux PENT_NN0[2] bit 3 INT: mux DBL_NE0[2] bit 2 INT: mux DBL_NN0_S0 bit 2 INT: mux DBL_NN0_S0 bit 9 INT: mux DBL_NN0_S0 bit 8 INT: mux DBL_NE0[2] bit 0 INT: mux DBL_NN0_S0 bit 1 INT: mux DBL_NN0_S0 bit 5 INT: mux DBL_NE0[2] bit 5 INT: mux LV[0] bit 8 INT: mux LV[0] bit 7 INT: mux LH[0] bit 7 INT: mux LH[0] bit 8 INT: mux IMUX_IMUX[35] bit 8 INT: mux IMUX_IMUX[17] bit 4 INT: mux IMUX_IMUX[17] bit 6 INT: mux IMUX_IMUX[29] bit 5 INT: mux IMUX_IMUX[23] bit 7 INT: mux IMUX_IMUX[23] bit 0 INT: mux IMUX_IMUX[23] bit 10 INT: mux IMUX_IMUX[17] bit 1 - -
B57 INT: mux PENT_EN0[2] bit 1 INT: mux PENT_EN0[2] bit 3 INT: mux PENT_EN0[2] bit 5 INT: mux PENT_NN0[2] bit 6 INT: mux PENT_EN0[2] bit 0 INT: mux PENT_EN0[2] bit 2 INT: mux DBL_EN0[2] bit 7 INT: mux DBL_EN0[2] bit 8 INT: mux DBL_EN0[2] bit 9 INT: mux DBL_EN0[2] bit 6 INT: mux DBL_EN0[2] bit 0 INT: mux DBL_EN0[2] bit 4 INT: mux DBL_EN0[2] bit 5 INT: mux DBL_EN0[2] bit 3 INT: mux IMUX_FAN[6] bit 4 INT: mux IMUX_FAN[7] bit 4 INT: mux IMUX_FAN[7] bit 0 INT: mux IMUX_FAN[7] bit 5 INT: mux IMUX_IMUX[23] bit 3 INT: mux IMUX_IMUX[17] bit 2 INT: mux IMUX_IMUX[23] bit 5 INT: mux IMUX_IMUX[23] bit 4 INT: mux IMUX_IMUX[17] bit 8 INT: mux IMUX_IMUX[17] bit 10 INT: mux IMUX_IMUX[17] bit 7 INT: mux IMUX_IMUX[17] bit 9 - -
B56 INT: mux PENT_EN0[2] bit 4 INT: mux PENT_NN0[2] bit 5 INT: mux PENT_NN0[2] bit 7 INT: mux PENT_EN0[2] bit 7 INT: mux PENT_NN0[2] bit 1 INT: mux PENT_NN0[2] bit 0 INT: mux DBL_NN0_S0 bit 3 INT: mux DBL_EN0[2] bit 2 INT: mux DBL_NN0_S0 bit 6 INT: mux DBL_NN0_S0 bit 7 INT: mux DBL_EN0[2] bit 1 INT: mux DBL_NN0_S0 bit 0 INT: mux DBL_NN0_S0 bit 4 INT: mux IMUX_IMUX[29] bit 3 INT: mux IMUX_BYP[3] bit 7 INT: mux IMUX_FAN[6] bit 2 INT: mux IMUX_FAN[6] bit 0 INT: mux IMUX_BYP[7] bit 7 INT: mux IMUX_IMUX[23] bit 2 INT: mux IMUX_IMUX[17] bit 3 INT: mux IMUX_IMUX[17] bit 5 INT: mux IMUX_IMUX[23] bit 6 INT: mux IMUX_IMUX[17] bit 0 INT: mux IMUX_IMUX[23] bit 8 INT: mux IMUX_IMUX[23] bit 1 INT: mux IMUX_IMUX[23] bit 9 - -
B55 INT: mux PENT_ES0[2] bit 4 INT: mux PENT_ES0[2] bit 5 INT: mux PENT_ES0[2] bit 7 INT: mux PENT_SS0[5] bit 7 INT: mux PENT_ES0[2] bit 1 INT: mux PENT_ES0[2] bit 0 INT: mux DBL_SS0[5] bit 3 INT: mux DBL_ES0[2] bit 2 INT: mux DBL_ES0[2] bit 6 INT: mux DBL_ES0[2] bit 7 INT: mux DBL_SS0[5] bit 1 INT: mux DBL_ES0[2] bit 0 INT: mux DBL_ES0[2] bit 5 INT: mux IMUX_IMUX[5] bit 2 INT: mux IMUX_FAN[6] bit 1 INT: mux IMUX_FAN[7] bit 2 INT: mux IMUX_FAN[6] bit 5 INT: mux IMUX_FAN[7] bit 3 INT: mux IMUX_IMUX[11] bit 2 INT: mux IMUX_IMUX[5] bit 3 INT: mux IMUX_IMUX[5] bit 5 INT: mux IMUX_IMUX[11] bit 6 INT: mux IMUX_IMUX[5] bit 0 INT: mux IMUX_IMUX[11] bit 1 INT: mux IMUX_IMUX[11] bit 7 INT: mux IMUX_IMUX[11] bit 10 - -
B54 INT: mux PENT_SS0[5] bit 0 INT: mux PENT_SS0[5] bit 3 INT: mux PENT_SS0[5] bit 5 INT: mux PENT_ES0[2] bit 6 INT: mux PENT_SS0[5] bit 1 INT: mux PENT_SS0[5] bit 2 INT: mux DBL_SS0[5] bit 6 INT: mux DBL_SS0[5] bit 9 INT: mux DBL_SS0[5] bit 8 INT: mux DBL_SS0[5] bit 7 INT: mux DBL_SS0[5] bit 4 INT: mux DBL_SS0[5] bit 0 INT: mux DBL_ES0[2] bit 4 INT: mux DBL_SS0[5] bit 5 INT: mux IMUX_FAN[6] bit 7 INT: mux IMUX_FAN[6] bit 6 INT: mux IMUX_FAN[7] bit 6 INT: mux IMUX_FAN[7] bit 8 INT: mux IMUX_IMUX[5] bit 10 INT: mux IMUX_IMUX[5] bit 8 INT: mux IMUX_IMUX[11] bit 5 INT: mux IMUX_IMUX[11] bit 4 INT: mux IMUX_IMUX[5] bit 7 INT: mux IMUX_IMUX[11] bit 9 INT: mux IMUX_IMUX[5] bit 9 INT: mux IMUX_IMUX[40] bit 4 - -
B53 INT: mux PENT_SS0[5] bit 4 INT: mux PENT_ES0[2] bit 3 INT: mux PENT_SS0[5] bit 6 INT: mux PENT_EE0[2] bit 3 INT: mux PENT_EE0[2] bit 5 INT: mux PENT_ES0[2] bit 2 INT: mux DBL_SS0[5] bit 2 INT: mux DBL_ES0[2] bit 9 INT: mux DBL_ES0[2] bit 8 INT: mux DBL_SE0[2] bit 3 INT: mux DBL_EE0[2] bit 0 INT: mux DBL_ES0[2] bit 1 INT: mux DBL_ES0[2] bit 3 INT: mux DBL_EE0[2] bit 5 INT: mux IMUX_FAN[6] bit 9 INT: mux IMUX_FAN[6] bit 8 INT: mux IMUX_FAN[7] bit 7 INT: mux IMUX_FAN[7] bit 9 INT: mux IMUX_IMUX[5] bit 4 INT: mux IMUX_IMUX[11] bit 3 INT: mux IMUX_IMUX[5] bit 6 INT: mux IMUX_IMUX[40] bit 6 INT: mux IMUX_IMUX[46] bit 3 INT: mux IMUX_IMUX[11] bit 8 INT: mux IMUX_IMUX[11] bit 0 INT: mux IMUX_IMUX[5] bit 1 - -
B52 INT: mux PENT_SE0[2] bit 1 INT: mux PENT_EE0[2] bit 0 INT: mux PENT_SE0[2] bit 5 INT: mux PENT_SE0[2] bit 2 INT: mux PENT_EE0[2] bit 4 INT: mux PENT_SE0[2] bit 4 INT: mux DBL_EE0[2] bit 7 INT: mux DBL_SE0[2] bit 7 INT: mux DBL_SE0[2] bit 6 INT: mux DBL_EE0[2] bit 6 INT: mux DBL_SE0[2] bit 1 INT: mux DBL_SE0[2] bit 4 INT: mux IMUX_FAN[4] bit 5 INT: mux DBL_EE0[2] bit 2 INT: mux IMUX_BYP[3] bit 6 INT: mux IMUX_BYP[3] bit 9 INT: mux IMUX_BYP[7] bit 8 INT: mux IMUX_BYP[7] bit 6 INT: mux IMUX_IMUX[40] bit 2 INT: mux IMUX_IMUX[40] bit 1 INT: mux IMUX_IMUX[46] bit 0 INT: mux IMUX_IMUX[46] bit 5 INT: mux IMUX_IMUX[46] bit 9 INT: mux IMUX_IMUX[40] bit 9 INT: mux IMUX_IMUX[40] bit 10 INT: mux IMUX_IMUX[46] bit 10 - -
B51 INT: mux PENT_EE0[2] bit 6 INT: mux PENT_SE0[2] bit 6 INT: mux PENT_SE0[2] bit 0 INT: mux PENT_SE0[2] bit 3 INT: mux PENT_EE0[2] bit 7 INT: mux PENT_SE0[2] bit 7 INT: mux DBL_EE0[2] bit 8 INT: mux DBL_SE0[2] bit 8 INT: mux DBL_SE0[2] bit 9 INT: mux DBL_EE0[2] bit 9 INT: mux DBL_SE0[2] bit 0 INT: mux DBL_SE0[2] bit 5 INT: mux IMUX_CTRL[3] bit 0 INT: mux DBL_SE0[2] bit 2 INT: mux IMUX_BYP[3] bit 8 INT: mux IMUX_BYP[7] bit 1 INT: mux IMUX_BYP[3] bit 0 INT: mux IMUX_BYP[7] bit 9 INT: mux IMUX_IMUX[46] bit 1 INT: mux IMUX_IMUX[40] bit 7 INT: mux IMUX_IMUX[46] bit 2 INT: mux IMUX_IMUX[46] bit 6 INT: mux IMUX_IMUX[40] bit 3 INT: mux IMUX_IMUX[46] bit 7 INT: mux IMUX_IMUX[40] bit 8 INT: mux IMUX_IMUX[46] bit 4 - -
B50 INT: mux PENT_EE0[2] bit 1 INT: mux PENT_SW0[2] bit 0 INT: mux PENT_WW0[5] bit 2 INT: mux PENT_EE0[2] bit 2 INT: mux PENT_SW0[2] bit 6 INT: mux PENT_SW0[2] bit 7 INT: mux DBL_EE0[2] bit 3 INT: mux DBL_SW0[2] bit 2 INT: mux DBL_SW0[2] bit 9 INT: mux DBL_SW0[2] bit 8 INT: mux DBL_EE0[2] bit 1 INT: mux DBL_SW0[2] bit 1 INT: mux DBL_SW0[2] bit 4 INT: mux DBL_EE0[2] bit 4 INT: mux IMUX_BYP[3] bit 1 INT: mux IMUX_BYP[3] bit 3 INT: mux IMUX_BYP[7] bit 4 INT: mux IMUX_BYP[3] bit 5 INT: mux IMUX_IMUX[46] bit 8 INT: mux IMUX_IMUX[28] bit 2 INT: mux IMUX_IMUX[28] bit 6 INT: mux IMUX_IMUX[40] bit 5 INT: mux IMUX_IMUX[34] bit 10 INT: mux IMUX_IMUX[34] bit 3 INT: mux IMUX_IMUX[34] bit 9 INT: mux IMUX_IMUX[28] bit 4 - -
B49 INT: mux PENT_WW0[5] bit 4 INT: mux PENT_WW0[5] bit 7 INT: mux PENT_WW0[5] bit 1 INT: mux PENT_SW0[2] bit 2 INT: mux PENT_WW0[5] bit 5 INT: mux PENT_WW0[5] bit 6 INT: mux DBL_WW0[4] bit 6 INT: mux DBL_WW0[4] bit 8 INT: mux DBL_WW0[4] bit 9 INT: mux DBL_WW0[4] bit 7 INT: mux DBL_WW0[4] bit 0 INT: mux DBL_WW0[4] bit 5 INT: mux DBL_WW0[4] bit 4 INT: mux DBL_WW0[4] bit 3 INT: mux IMUX_BYP[3] bit 2 INT: mux IMUX_BYP[7] bit 2 INT: mux IMUX_BYP[7] bit 5 INT: mux IMUX_BYP[7] bit 0 INT: mux IMUX_IMUX[34] bit 0 INT: mux IMUX_IMUX[28] bit 1 INT: mux IMUX_IMUX[34] bit 5 INT: mux IMUX_IMUX[34] bit 2 INT: mux IMUX_IMUX[28] bit 8 INT: mux IMUX_IMUX[28] bit 9 INT: mux IMUX_IMUX[28] bit 10 INT: mux IMUX_IMUX[28] bit 7 - -
B48 INT: mux PENT_WW0[5] bit 0 INT: mux PENT_SW0[2] bit 1 INT: mux PENT_SW0[2] bit 3 INT: mux PENT_WW0[5] bit 3 INT: mux PENT_SW0[2] bit 4 INT: mux PENT_SW0[2] bit 5 INT: mux DBL_SW0[2] bit 3 INT: mux DBL_WW0[4] bit 2 INT: mux DBL_SW0[2] bit 7 INT: mux DBL_SW0[2] bit 6 INT: mux DBL_WW0[4] bit 1 INT: mux DBL_SW0[2] bit 0 INT: mux DBL_SW0[2] bit 5 INT: mux IMUX_IMUX[40] bit 0 INT: mux IMUX_BYP[2] bit 2 INT: mux IMUX_BYP[2] bit 3 INT: mux IMUX_BYP[6] bit 4 INT: mux IMUX_BYP[6] bit 0 INT: mux IMUX_IMUX[34] bit 1 INT: mux IMUX_IMUX[28] bit 0 INT: mux IMUX_IMUX[28] bit 5 INT: mux IMUX_IMUX[34] bit 6 INT: mux IMUX_IMUX[28] bit 3 INT: mux IMUX_IMUX[34] bit 8 INT: mux IMUX_IMUX[34] bit 4 INT: mux IMUX_IMUX[34] bit 7 - -
B47 INT: mux PENT_SS0[2] bit 4 INT: mux PENT_SS0[2] bit 5 INT: mux PENT_SS0[2] bit 7 INT: mux PENT_WS0[2] bit 7 INT: mux PENT_SS0[2] bit 2 INT: mux PENT_SS0[2] bit 3 INT: mux DBL_WS0[2] bit 3 INT: mux DBL_SS0[1] bit 2 INT: mux DBL_SS0[1] bit 9 INT: mux DBL_SS0[1] bit 8 INT: mux DBL_WS0[2] bit 1 INT: mux DBL_SS0[1] bit 0 INT: mux DBL_SS0[1] bit 4 INT: mux IMUX_IMUX[16] bit 1 INT: mux IMUX_BYP[7] bit 3 INT: mux IMUX_BYP[6] bit 2 INT: mux IMUX_BYP[6] bit 5 INT: mux IMUX_BYP[2] bit 4 INT: mux IMUX_IMUX[22] bit 1 INT: mux IMUX_IMUX[16] bit 0 INT: mux IMUX_IMUX[16] bit 5 INT: mux IMUX_IMUX[22] bit 6 INT: mux IMUX_IMUX[16] bit 3 INT: mux IMUX_IMUX[22] bit 4 INT: mux IMUX_IMUX[22] bit 10 INT: mux IMUX_IMUX[22] bit 9 - -
B46 INT: mux PENT_WS0[2] bit 3 INT: mux PENT_WS0[2] bit 0 INT: mux PENT_WS0[2] bit 5 INT: mux PENT_SS0[2] bit 6 INT: mux PENT_WS0[2] bit 2 INT: mux PENT_WS0[2] bit 1 INT: mux DBL_WS0[2] bit 9 INT: mux DBL_WS0[2] bit 6 INT: mux DBL_WS0[2] bit 7 INT: mux DBL_WS0[2] bit 8 INT: mux DBL_WS0[2] bit 5 INT: mux DBL_WS0[2] bit 0 INT: mux DBL_SS0[1] bit 5 INT: mux DBL_WS0[2] bit 4 INT: mux IMUX_BYP[6] bit 1 INT: mux IMUX_BYP[2] bit 1 INT: mux IMUX_BYP[2] bit 5 INT: mux IMUX_BYP[2] bit 0 INT: mux IMUX_IMUX[16] bit 9 INT: mux IMUX_IMUX[16] bit 8 INT: mux IMUX_IMUX[22] bit 5 INT: mux IMUX_IMUX[22] bit 2 INT: mux IMUX_IMUX[16] bit 10 INT: mux IMUX_IMUX[22] bit 7 INT: mux IMUX_IMUX[16] bit 7 INT: mux IMUX_IMUX[4] bit 4 - -
B45 INT: mux PENT_WS0[2] bit 4 INT: mux PENT_SS0[2] bit 0 INT: mux PENT_WS0[2] bit 6 INT: mux PENT_WN0[2] bit 7 INT: mux PENT_WN0[2] bit 0 INT: mux PENT_SS0[2] bit 1 INT: mux DBL_WS0[2] bit 2 INT: mux DBL_SS0[1] bit 6 INT: mux DBL_SS0[1] bit 7 INT: mux DBL_NN0[4] bit 2 INT: mux DBL_WN0[2] bit 1 INT: mux DBL_SS0[1] bit 1 INT: mux DBL_SS0[1] bit 3 INT: mux DBL_WN0[2] bit 5 INT: mux IMUX_BYP[2] bit 7 INT: mux IMUX_BYP[2] bit 8 INT: mux IMUX_BYP[6] bit 9 INT: mux IMUX_BYP[6] bit 7 INT: mux IMUX_IMUX[16] bit 2 INT: mux IMUX_IMUX[22] bit 0 INT: mux IMUX_IMUX[16] bit 6 INT: mux IMUX_IMUX[4] bit 6 INT: mux IMUX_IMUX[10] bit 3 INT: mux IMUX_IMUX[22] bit 8 INT: mux IMUX_IMUX[22] bit 3 INT: mux IMUX_IMUX[16] bit 4 - -
B44 INT: mux PENT_NN0[4] bit 4 INT: mux PENT_WN0[2] bit 5 INT: mux PENT_NN0[4] bit 0 INT: mux PENT_NN0[4] bit 6 INT: mux PENT_WN0[2] bit 1 INT: mux PENT_NN0[4] bit 1 INT: mux DBL_WN0[2] bit 6 INT: mux DBL_NN0[4] bit 6 INT: mux DBL_NN0[4] bit 7 INT: mux DBL_WN0[2] bit 7 INT: mux DBL_NN0[4] bit 0 INT: mux DBL_NN0[4] bit 4 INT: mux IMUX_CTRL[3] bit 7 INT: mux DBL_WN0[2] bit 3 INT: mux IMUX_BYP[2] bit 9 INT: mux IMUX_BYP[2] bit 6 INT: mux IMUX_BYP[6] bit 6 INT: mux IMUX_BYP[6] bit 8 INT: mux IMUX_IMUX[4] bit 2 INT: mux IMUX_IMUX[4] bit 1 INT: mux IMUX_IMUX[10] bit 0 INT: mux IMUX_IMUX[10] bit 5 INT: mux IMUX_IMUX[10] bit 9 INT: mux IMUX_IMUX[4] bit 9 INT: mux IMUX_IMUX[4] bit 10 INT: mux IMUX_IMUX[10] bit 10 - -
B43 INT: mux PENT_WN0[2] bit 2 INT: mux PENT_NN0[4] bit 2 INT: mux PENT_NN0[4] bit 5 INT: mux PENT_NN0[4] bit 7 INT: mux PENT_WN0[2] bit 3 INT: mux PENT_NN0[4] bit 3 INT: mux DBL_WN0[2] bit 8 INT: mux DBL_NN0[4] bit 8 INT: mux DBL_NN0[4] bit 9 INT: mux DBL_WN0[2] bit 9 INT: mux DBL_NN0[4] bit 1 INT: mux DBL_NN0[4] bit 5 INT: mux IMUX_CTRL[2] bit 7 INT: mux DBL_NN0[4] bit 3 INT: mux IMUX_FAN[4] bit 8 INT: mux IMUX_FAN[4] bit 6 INT: mux IMUX_FAN[5] bit 6 INT: mux IMUX_FAN[5] bit 8 INT: mux IMUX_IMUX[10] bit 1 INT: mux IMUX_IMUX[4] bit 7 INT: mux IMUX_IMUX[10] bit 2 INT: mux IMUX_IMUX[10] bit 6 INT: mux IMUX_IMUX[4] bit 3 INT: mux IMUX_IMUX[10] bit 7 INT: mux IMUX_IMUX[4] bit 8 INT: mux IMUX_IMUX[10] bit 4 - -
B42 INT: mux PENT_WN0[2] bit 4 INT: mux PENT_WW0[2] bit 1 INT: mux PENT_NW0[1] bit 2 INT: mux PENT_WN0[2] bit 6 INT: mux PENT_WW0[2] bit 4 INT: mux PENT_WW0[2] bit 5 INT: mux DBL_WN0[2] bit 2 INT: mux DBL_WW0[2] bit 2 INT: mux DBL_WW0[2] bit 7 INT: mux DBL_WW0[2] bit 6 INT: mux DBL_WN0[2] bit 0 INT: mux DBL_WW0[2] bit 1 INT: mux DBL_WW0[2] bit 4 INT: mux DBL_WN0[2] bit 4 INT: mux IMUX_FAN[4] bit 7 INT: mux IMUX_FAN[5] bit 2 INT: mux IMUX_FAN[4] bit 3 INT: mux IMUX_FAN[5] bit 9 INT: mux IMUX_IMUX[10] bit 8 INT: mux IMUX_IMUX[39] bit 4 INT: mux IMUX_IMUX[39] bit 6 INT: mux IMUX_IMUX[4] bit 5 INT: mux IMUX_IMUX[45] bit 7 INT: mux IMUX_IMUX[45] bit 0 INT: mux IMUX_IMUX[45] bit 10 INT: mux IMUX_IMUX[39] bit 1 - -
B41 INT: mux PENT_NW0[1] bit 7 INT: mux PENT_NW0[1] bit 5 INT: mux PENT_NW0[1] bit 0 INT: mux PENT_WW0[2] bit 2 INT: mux PENT_NW0[1] bit 6 INT: mux PENT_NW0[1] bit 4 INT: mux DBL_NW0[1] bit 9 INT: mux DBL_NW0[1] bit 6 INT: mux DBL_NW0[1] bit 7 INT: mux DBL_NW0[1] bit 8 INT: mux DBL_NW0[1] bit 0 INT: mux DBL_NW0[1] bit 5 INT: mux DBL_NW0[1] bit 4 INT: mux DBL_NW0[1] bit 3 INT: mux IMUX_FAN[4] bit 1 INT: mux IMUX_FAN[4] bit 2 INT: mux IMUX_FAN[4] bit 0 INT: mux IMUX_FAN[5] bit 5 INT: mux IMUX_IMUX[45] bit 2 INT: mux IMUX_IMUX[39] bit 3 INT: mux IMUX_IMUX[45] bit 5 INT: mux IMUX_IMUX[45] bit 4 INT: mux IMUX_IMUX[39] bit 9 INT: mux IMUX_IMUX[39] bit 10 INT: mux IMUX_IMUX[39] bit 7 INT: mux IMUX_IMUX[39] bit 8 - -
B40 INT: mux PENT_NW0[1] bit 1 INT: mux PENT_WW0[2] bit 0 INT: mux PENT_WW0[2] bit 3 INT: mux PENT_NW0[1] bit 3 INT: mux PENT_WW0[2] bit 7 INT: mux PENT_WW0[2] bit 6 INT: mux DBL_WW0[2] bit 3 INT: mux DBL_NW0[1] bit 2 INT: mux DBL_WW0[2] bit 8 INT: mux DBL_WW0[2] bit 9 INT: mux DBL_NW0[1] bit 1 INT: mux DBL_WW0[2] bit 0 INT: mux DBL_WW0[2] bit 5 INT: mux IMUX_IMUX[4] bit 0 INT: mux IMUX_FAN[5] bit 1 INT: mux IMUX_FAN[5] bit 4 INT: mux IMUX_FAN[5] bit 0 INT: mux IMUX_FAN[5] bit 3 INT: mux IMUX_IMUX[45] bit 3 INT: mux IMUX_IMUX[39] bit 2 INT: mux IMUX_IMUX[39] bit 5 INT: mux IMUX_IMUX[45] bit 6 INT: mux IMUX_IMUX[39] bit 0 INT: mux IMUX_IMUX[45] bit 9 INT: mux IMUX_IMUX[45] bit 1 INT: mux IMUX_IMUX[45] bit 8 - -
B39 INT: mux PENT_NE0[1] bit 0 INT: mux PENT_NE0[1] bit 1 INT: mux PENT_NE0[1] bit 3 INT: mux PENT_EE0[4] bit 3 INT: mux PENT_NE0[1] bit 7 INT: mux PENT_NE0[1] bit 6 INT: mux DBL_EE0[5] bit 3 INT: mux DBL_NE0[1] bit 2 INT: mux DBL_NE0[1] bit 8 INT: mux DBL_NE0[1] bit 9 INT: mux DBL_EE0[5] bit 1 INT: mux DBL_NE0[1] bit 0 INT: mux DBL_NE0[1] bit 4 INT: mux IMUX_IMUX[27] bit 3 INT: mux IMUX_FAN[4] bit 4 INT: mux IMUX_CTRL[3] bit 3 INT: mux IMUX_CTRL[3] bit 5 INT: mux IMUX_CTRL[3] bit 2 INT: mux IMUX_IMUX[33] bit 3 INT: mux IMUX_IMUX[27] bit 2 INT: mux IMUX_IMUX[27] bit 5 INT: mux IMUX_IMUX[33] bit 6 INT: mux IMUX_IMUX[27] bit 0 INT: mux IMUX_IMUX[33] bit 1 INT: mux IMUX_IMUX[33] bit 7 INT: mux IMUX_IMUX[33] bit 10 - -
B38 INT: mux PENT_EE0[4] bit 6 INT: mux PENT_EE0[4] bit 4 INT: mux PENT_EE0[4] bit 1 INT: mux PENT_NE0[1] bit 2 INT: mux PENT_EE0[4] bit 7 INT: mux PENT_EE0[4] bit 5 INT: mux DBL_EE0[5] bit 8 INT: mux DBL_EE0[5] bit 6 INT: mux DBL_EE0[5] bit 7 INT: mux DBL_EE0[5] bit 9 INT: mux DBL_EE0[5] bit 5 INT: mux DBL_EE0[5] bit 0 INT: mux DBL_NE0[1] bit 5 INT: mux DBL_EE0[5] bit 4 INT: mux IMUX_CTRL[2] bit 3 INT: mux IMUX_CTRL[2] bit 1 INT: mux IMUX_CTRL[2] bit 5 INT: mux IMUX_CTRL[2] bit 4 INT: mux IMUX_IMUX[27] bit 10 INT: mux IMUX_IMUX[27] bit 9 INT: mux IMUX_IMUX[33] bit 5 INT: mux IMUX_IMUX[33] bit 4 INT: mux IMUX_IMUX[27] bit 7 INT: mux IMUX_IMUX[33] bit 8 INT: mux IMUX_IMUX[27] bit 8 INT: mux IMUX_IMUX[15] bit 1 - -
B37 INT: mux PENT_EE0[4] bit 0 INT: mux PENT_NE0[1] bit 4 INT: mux PENT_EE0[4] bit 2 INT: mux PENT_NN0[1] bit 7 INT: mux PENT_NN0[1] bit 2 INT: mux PENT_NE0[1] bit 5 INT: mux DBL_EE0[5] bit 2 INT: mux DBL_NE0[1] bit 6 INT: mux DBL_NE0[1] bit 7 INT: mux DBL_EN0[1] bit 2 INT: mux DBL_NN0[2] bit 1 INT: mux DBL_NE0[1] bit 1 INT: mux DBL_NE0[1] bit 3 INT: mux DBL_NN0[2] bit 5 INT: mux IMUX_CTRL[3] bit 1 INT: mux IMUX_CTRL[2] bit 0 INT: mux IMUX_CTRL[3] bit 4 INT: mux IMUX_CTRL[2] bit 2 INT: mux IMUX_IMUX[27] bit 4 INT: mux IMUX_IMUX[33] bit 2 INT: mux IMUX_IMUX[27] bit 6 INT: mux IMUX_IMUX[15] bit 6 INT: mux IMUX_IMUX[21] bit 0 INT: mux IMUX_IMUX[33] bit 9 INT: mux IMUX_IMUX[33] bit 0 INT: mux IMUX_IMUX[27] bit 1 - -
B36 INT: mux PENT_EN0[1] bit 4 INT: mux PENT_NN0[1] bit 5 INT: mux PENT_EN0[1] bit 2 INT: mux PENT_EN0[1] bit 6 INT: mux PENT_NN0[1] bit 3 INT: mux PENT_EN0[1] bit 3 INT: mux DBL_NN0[2] bit 8 INT: mux DBL_EN0[1] bit 8 INT: mux DBL_EN0[1] bit 9 INT: mux DBL_NN0[2] bit 9 INT: mux DBL_EN0[1] bit 0 INT: mux DBL_EN0[1] bit 4 INT: mux IMUX_GFAN[1] bit 5 INT: mux DBL_NN0[2] bit 3 INT: mux IMUX_CTRL[2] bit 6 INT: mux IMUX_CTRL[2] bit 9 INT: mux IMUX_CTRL[3] bit 8 INT: mux IMUX_CTRL[3] bit 6 INT: mux IMUX_IMUX[15] bit 4 INT: mux IMUX_IMUX[15] bit 3 INT: mux IMUX_IMUX[21] bit 2 INT: mux IMUX_IMUX[21] bit 5 INT: mux IMUX_IMUX[21] bit 10 INT: mux IMUX_IMUX[15] bit 10 INT: mux IMUX_IMUX[15] bit 7 INT: mux IMUX_IMUX[21] bit 7 - -
B35 INT: mux PENT_NN0[1] bit 0 INT: mux PENT_EN0[1] bit 0 INT: mux PENT_EN0[1] bit 5 INT: mux PENT_EN0[1] bit 7 INT: mux PENT_NN0[1] bit 1 INT: mux PENT_EN0[1] bit 1 INT: mux DBL_NN0[2] bit 6 INT: mux DBL_EN0[1] bit 6 INT: mux DBL_EN0[1] bit 7 INT: mux DBL_NN0[2] bit 7 INT: mux DBL_EN0[1] bit 1 INT: mux DBL_EN0[1] bit 5 INT: mux IMUX_GFAN[1] bit 6 INT: mux DBL_EN0[1] bit 3 INT: mux IMUX_CTRL[2] bit 8 INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CTRL[3] bit 9 INT: mux IMUX_IMUX[21] bit 3 INT: mux IMUX_IMUX[15] bit 8 INT: mux IMUX_IMUX[21] bit 4 INT: mux IMUX_IMUX[21] bit 6 INT: mux IMUX_IMUX[15] bit 0 INT: mux IMUX_IMUX[21] bit 8 INT: mux IMUX_IMUX[15] bit 9 INT: mux IMUX_IMUX[21] bit 1 - -
B34 INT: mux PENT_NN0[1] bit 4 INT: mux PENT_ES0[1] bit 4 INT: mux PENT_SS0[4] bit 6 INT: mux PENT_NN0[1] bit 6 INT: mux PENT_ES0[1] bit 0 INT: mux PENT_ES0[1] bit 1 INT: mux DBL_NN0[2] bit 2 INT: mux DBL_ES0[1] bit 2 INT: mux DBL_ES0[1] bit 7 INT: mux DBL_ES0[1] bit 6 INT: mux DBL_NN0[2] bit 0 INT: mux DBL_ES0[1] bit 1 INT: mux DBL_ES0[1] bit 4 INT: mux DBL_NN0[2] bit 4 INT: mux IMUX_GFAN[1] bit 7 INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_GFAN[1] bit 4 INT: mux IMUX_IMUX[21] bit 9 INT: mux IMUX_IMUX[3] bit 4 INT: mux IMUX_IMUX[3] bit 6 INT: mux IMUX_IMUX[15] bit 5 INT: mux IMUX_IMUX[9] bit 7 INT: mux IMUX_IMUX[9] bit 0 INT: mux IMUX_IMUX[9] bit 10 INT: mux IMUX_IMUX[3] bit 1 - -
B33 INT: mux PENT_SS0[4] bit 2 INT: mux PENT_SS0[4] bit 1 INT: mux PENT_SS0[4] bit 5 INT: mux PENT_ES0[1] bit 6 INT: mux PENT_SS0[4] bit 3 INT: mux PENT_SS0[4] bit 0 INT: mux DBL_SS0[4] bit 8 INT: mux DBL_SS0[4] bit 6 INT: mux DBL_SS0[4] bit 7 INT: mux DBL_SS0[4] bit 9 INT: mux DBL_SS0[4] bit 0 INT: mux DBL_SS0[4] bit 5 INT: mux DBL_SS0[4] bit 4 INT: mux DBL_SS0[4] bit 3 INT: mux IMUX_GFAN[1] bit 3 INT: mux IMUX_GFAN[1] bit 2 INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[1] bit 3 INT: mux IMUX_IMUX[9] bit 2 INT: mux IMUX_IMUX[3] bit 3 INT: mux IMUX_IMUX[9] bit 5 INT: mux IMUX_IMUX[9] bit 4 INT: mux IMUX_IMUX[3] bit 9 INT: mux IMUX_IMUX[3] bit 10 INT: mux IMUX_IMUX[3] bit 7 INT: mux IMUX_IMUX[3] bit 8 - -
B32 INT: mux PENT_SS0[4] bit 4 INT: mux PENT_ES0[1] bit 5 INT: mux PENT_ES0[1] bit 7 INT: mux PENT_SS0[4] bit 7 INT: mux PENT_ES0[1] bit 2 INT: mux PENT_ES0[1] bit 3 INT: mux DBL_ES0[1] bit 3 INT: mux DBL_SS0[4] bit 2 INT: mux DBL_ES0[1] bit 9 INT: mux DBL_ES0[1] bit 8 INT: mux DBL_SS0[4] bit 1 INT: mux DBL_ES0[1] bit 0 INT: mux DBL_ES0[1] bit 5 INT: mux IMUX_IMUX[15] bit 2 INT: mux IMUX_GFAN[1] bit 0 INT: mux IMUX_GFAN[1] bit 1 INT: mux IMUX_CLK[1] bit 1 INT: mux IMUX_CLK[1] bit 0 INT: mux IMUX_IMUX[9] bit 3 INT: mux IMUX_IMUX[3] bit 2 INT: mux IMUX_IMUX[3] bit 5 INT: mux IMUX_IMUX[9] bit 6 INT: mux IMUX_IMUX[3] bit 0 INT: mux IMUX_IMUX[9] bit 9 INT: mux IMUX_IMUX[9] bit 1 INT: mux IMUX_IMUX[9] bit 8 - -
B31 INT: mux PENT_EE0[1] bit 1 INT: mux PENT_EE0[1] bit 0 INT: mux PENT_EE0[1] bit 3 INT: mux PENT_SE0[1] bit 3 INT: mux PENT_EE0[1] bit 4 INT: mux PENT_EE0[1] bit 5 INT: mux DBL_SE0[1] bit 2 INT: mux DBL_EE0[1] bit 3 INT: mux DBL_EE0[1] bit 7 INT: mux DBL_EE0[1] bit 6 INT: mux DBL_SE0[1] bit 0 INT: mux DBL_EE0[1] bit 1 INT: mux DBL_EE0[1] bit 5 INT: mux IMUX_IMUX[38] bit 1 INT: mux IMUX_GFAN[0] bit 0 INT: mux IMUX_GFAN[0] bit 1 INT: mux IMUX_CLK[0] bit 1 INT: mux IMUX_CLK[0] bit 0 INT: mux IMUX_IMUX[44] bit 1 INT: mux IMUX_IMUX[38] bit 0 INT: mux IMUX_IMUX[38] bit 5 INT: mux IMUX_IMUX[44] bit 6 INT: mux IMUX_IMUX[38] bit 3 INT: mux IMUX_IMUX[44] bit 4 INT: mux IMUX_IMUX[44] bit 10 INT: mux IMUX_IMUX[44] bit 9 - -
B30 INT: mux PENT_SE0[1] bit 5 INT: mux PENT_SE0[1] bit 6 INT: mux PENT_SE0[1] bit 0 INT: mux PENT_EE0[1] bit 2 INT: mux PENT_SE0[1] bit 4 INT: mux PENT_SE0[1] bit 7 INT: mux DBL_SE0[1] bit 7 INT: mux DBL_SE0[1] bit 8 INT: mux DBL_SE0[1] bit 9 INT: mux DBL_SE0[1] bit 6 INT: mux DBL_SE0[1] bit 4 INT: mux DBL_SE0[1] bit 1 INT: mux DBL_EE0[1] bit 4 INT: mux DBL_SE0[1] bit 5 INT: mux IMUX_GFAN[0] bit 3 INT: mux IMUX_GFAN[0] bit 2 INT: mux IMUX_CLK[0] bit 2 INT: mux IMUX_CLK[0] bit 3 INT: mux IMUX_IMUX[38] bit 9 INT: mux IMUX_IMUX[38] bit 8 INT: mux IMUX_IMUX[44] bit 5 INT: mux IMUX_IMUX[44] bit 2 INT: mux IMUX_IMUX[38] bit 10 INT: mux IMUX_IMUX[44] bit 7 INT: mux IMUX_IMUX[38] bit 7 INT: mux IMUX_IMUX[26] bit 4 - -
B29 INT: mux PENT_SE0[1] bit 1 INT: mux PENT_EE0[1] bit 6 INT: mux PENT_SE0[1] bit 2 INT: mux PENT_SW0[1] bit 3 INT: mux PENT_SW0[1] bit 6 INT: mux PENT_EE0[1] bit 7 INT: mux DBL_SE0[1] bit 3 INT: mux DBL_EE0[1] bit 8 INT: mux DBL_EE0[1] bit 9 INT: mux DBL_WW0[3] bit 2 INT: mux DBL_SW0[1] bit 1 INT: mux DBL_EE0[1] bit 0 INT: mux DBL_EE0[1] bit 2 INT: mux DBL_SW0[1] bit 4 INT: mux IMUX_GFAN[0] bit 7 INT: mux IMUX_CLK[0] bit 7 INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_GFAN[0] bit 4 INT: mux IMUX_IMUX[38] bit 2 INT: mux IMUX_IMUX[44] bit 0 INT: mux IMUX_IMUX[38] bit 6 INT: mux IMUX_IMUX[26] bit 6 INT: mux IMUX_IMUX[32] bit 3 INT: mux IMUX_IMUX[44] bit 8 INT: mux IMUX_IMUX[44] bit 3 INT: mux IMUX_IMUX[38] bit 4 - -
B28 INT: mux PENT_WW0[4] bit 0 INT: mux PENT_SW0[1] bit 1 INT: mux PENT_WW0[4] bit 6 INT: mux PENT_WW0[4] bit 2 INT: mux PENT_SW0[1] bit 7 INT: mux PENT_WW0[4] bit 7 INT: mux DBL_SW0[1] bit 8 INT: mux DBL_WW0[3] bit 8 INT: mux DBL_WW0[3] bit 9 INT: mux DBL_SW0[1] bit 9 INT: mux DBL_WW0[3] bit 0 INT: mux DBL_WW0[3] bit 5 INT: mux IMUX_GFAN[0] bit 6 INT: mux DBL_SW0[1] bit 3 INT: mux IMUX_CTRL[0] bit 8 INT: mux IMUX_CLK[0] bit 6 INT: mux IMUX_CLK[0] bit 5 INT: mux IMUX_CTRL[1] bit 9 INT: mux IMUX_IMUX[26] bit 2 INT: mux IMUX_IMUX[26] bit 1 INT: mux IMUX_IMUX[32] bit 0 INT: mux IMUX_IMUX[32] bit 5 INT: mux IMUX_IMUX[32] bit 9 INT: mux IMUX_IMUX[26] bit 9 INT: mux IMUX_IMUX[26] bit 10 INT: mux IMUX_IMUX[32] bit 10 - -
B27 INT: mux PENT_SW0[1] bit 5 INT: mux PENT_WW0[4] bit 5 INT: mux PENT_WW0[4] bit 1 INT: mux PENT_WW0[4] bit 3 INT: mux PENT_SW0[1] bit 4 INT: mux PENT_WW0[4] bit 4 INT: mux DBL_SW0[1] bit 7 INT: mux DBL_WW0[3] bit 7 INT: mux DBL_WW0[3] bit 6 INT: mux DBL_SW0[1] bit 6 INT: mux DBL_WW0[3] bit 1 INT: mux DBL_WW0[3] bit 4 INT: mux IMUX_GFAN[0] bit 5 INT: mux DBL_WW0[3] bit 3 INT: mux IMUX_CTRL[0] bit 7 INT: mux IMUX_CTRL[0] bit 9 INT: mux IMUX_CTRL[1] bit 8 INT: mux IMUX_CTRL[1] bit 7 INT: mux IMUX_IMUX[32] bit 1 INT: mux IMUX_IMUX[26] bit 7 INT: mux IMUX_IMUX[32] bit 2 INT: mux IMUX_IMUX[32] bit 6 INT: mux IMUX_IMUX[26] bit 3 INT: mux IMUX_IMUX[32] bit 7 INT: mux IMUX_IMUX[26] bit 8 INT: mux IMUX_IMUX[32] bit 4 - -
B26 INT: mux PENT_SW0[1] bit 0 INT: mux PENT_SS0[1] bit 4 INT: mux PENT_WS0[1] bit 6 INT: mux PENT_SW0[1] bit 2 INT: mux PENT_SS0[1] bit 3 INT: mux PENT_SS0[1] bit 2 INT: mux DBL_SW0[1] bit 2 INT: mux DBL_SS0[0] bit 2 INT: mux DBL_SS0[0] bit 8 INT: mux DBL_SS0[0] bit 9 INT: mux DBL_SW0[1] bit 0 INT: mux DBL_SS0[0] bit 1 INT: mux DBL_SS0[0] bit 5 INT: mux DBL_SW0[1] bit 5 INT: mux IMUX_CTRL[1] bit 1 INT: mux IMUX_CTRL[0] bit 3 INT: mux IMUX_CTRL[1] bit 4 INT: mux IMUX_CTRL[0] bit 0 INT: mux IMUX_IMUX[32] bit 8 INT: mux IMUX_IMUX[14] bit 2 INT: mux IMUX_IMUX[14] bit 6 INT: mux IMUX_IMUX[26] bit 5 INT: mux IMUX_IMUX[20] bit 10 INT: mux IMUX_IMUX[20] bit 3 INT: mux IMUX_IMUX[20] bit 9 INT: mux IMUX_IMUX[14] bit 4 - -
B25 INT: mux PENT_WS0[1] bit 1 INT: mux PENT_WS0[1] bit 2 INT: mux PENT_WS0[1] bit 5 INT: mux PENT_SS0[1] bit 6 INT: mux PENT_WS0[1] bit 0 INT: mux PENT_WS0[1] bit 3 INT: mux DBL_WS0[1] bit 7 INT: mux DBL_WS0[1] bit 9 INT: mux DBL_WS0[1] bit 8 INT: mux DBL_WS0[1] bit 6 INT: mux DBL_WS0[1] bit 0 INT: mux DBL_WS0[1] bit 4 INT: mux DBL_WS0[1] bit 5 INT: mux DBL_WS0[1] bit 3 INT: mux IMUX_CTRL[0] bit 2 INT: mux IMUX_CTRL[0] bit 1 INT: mux IMUX_CTRL[0] bit 5 INT: mux IMUX_CTRL[0] bit 4 INT: mux IMUX_IMUX[20] bit 0 INT: mux IMUX_IMUX[14] bit 1 INT: mux IMUX_IMUX[20] bit 5 INT: mux IMUX_IMUX[20] bit 2 INT: mux IMUX_IMUX[14] bit 8 INT: mux IMUX_IMUX[14] bit 9 INT: mux IMUX_IMUX[14] bit 10 INT: mux IMUX_IMUX[14] bit 7 - -
B24 INT: mux PENT_WS0[1] bit 4 INT: mux PENT_SS0[1] bit 5 INT: mux PENT_SS0[1] bit 7 INT: mux PENT_WS0[1] bit 7 INT: mux PENT_SS0[1] bit 1 INT: mux PENT_SS0[1] bit 0 INT: mux DBL_SS0[0] bit 3 INT: mux DBL_WS0[1] bit 2 INT: mux DBL_SS0[0] bit 6 INT: mux DBL_SS0[0] bit 7 INT: mux DBL_WS0[1] bit 1 INT: mux DBL_SS0[0] bit 0 INT: mux DBL_SS0[0] bit 4 INT: mux IMUX_IMUX[26] bit 0 INT: mux IMUX_FAN[2] bit 3 INT: mux IMUX_CTRL[1] bit 2 INT: mux IMUX_CTRL[1] bit 5 INT: mux IMUX_CTRL[1] bit 0 INT: mux IMUX_IMUX[20] bit 1 INT: mux IMUX_IMUX[14] bit 0 INT: mux IMUX_IMUX[14] bit 5 INT: mux IMUX_IMUX[20] bit 6 INT: mux IMUX_IMUX[14] bit 3 INT: mux IMUX_IMUX[20] bit 8 INT: mux IMUX_IMUX[20] bit 4 INT: mux IMUX_IMUX[20] bit 7 - -
B23 INT: mux PENT_WN0[1] bit 4 INT: mux PENT_WN0[1] bit 5 INT: mux PENT_WN0[1] bit 7 INT: mux PENT_NN0[3] bit 7 INT: mux PENT_WN0[1] bit 1 INT: mux PENT_WN0[1] bit 0 INT: mux DBL_NN0[3] bit 3 INT: mux DBL_WN0[1] bit 2 INT: mux DBL_WN0[1] bit 6 INT: mux DBL_WN0[1] bit 7 INT: mux DBL_NN0[3] bit 1 INT: mux DBL_WN0[1] bit 0 INT: mux DBL_WN0[1] bit 5 INT: mux IMUX_IMUX[2] bit 1 INT: mux IMUX_FAN[3] bit 4 INT: mux IMUX_FAN[3] bit 3 INT: mux IMUX_FAN[3] bit 0 INT: mux IMUX_FAN[3] bit 1 INT: mux IMUX_IMUX[8] bit 1 INT: mux IMUX_IMUX[2] bit 0 INT: mux IMUX_IMUX[2] bit 5 INT: mux IMUX_IMUX[8] bit 6 INT: mux IMUX_IMUX[2] bit 3 INT: mux IMUX_IMUX[8] bit 4 INT: mux IMUX_IMUX[8] bit 10 INT: mux IMUX_IMUX[8] bit 9 - -
B22 INT: mux PENT_NN0[3] bit 0 INT: mux PENT_NN0[3] bit 2 INT: mux PENT_NN0[3] bit 5 INT: mux PENT_WN0[1] bit 6 INT: mux PENT_NN0[3] bit 1 INT: mux PENT_NN0[3] bit 3 INT: mux DBL_NN0[3] bit 6 INT: mux DBL_NN0[3] bit 8 INT: mux DBL_NN0[3] bit 9 INT: mux DBL_NN0[3] bit 7 INT: mux DBL_NN0[3] bit 4 INT: mux DBL_NN0[3] bit 0 INT: mux DBL_WN0[1] bit 4 INT: mux DBL_NN0[3] bit 5 INT: mux IMUX_FAN[2] bit 4 INT: mux IMUX_FAN[2] bit 2 INT: mux IMUX_FAN[2] bit 0 INT: mux IMUX_FAN[3] bit 5 INT: mux IMUX_IMUX[2] bit 9 INT: mux IMUX_IMUX[2] bit 8 INT: mux IMUX_IMUX[8] bit 5 INT: mux IMUX_IMUX[8] bit 2 INT: mux IMUX_IMUX[2] bit 10 INT: mux IMUX_IMUX[8] bit 7 INT: mux IMUX_IMUX[2] bit 7 INT: mux IMUX_IMUX[37] bit 1 - -
B21 INT: mux PENT_NN0[3] bit 4 INT: mux PENT_WN0[1] bit 2 INT: mux PENT_NN0[3] bit 6 INT: mux PENT_WW0[1] bit 3 INT: mux PENT_WW0[1] bit 4 INT: mux PENT_WN0[1] bit 3 INT: mux DBL_NN0[3] bit 2 INT: mux DBL_WN0[1] bit 8 INT: mux DBL_WN0[1] bit 9 INT: mux DBL_NW0[0] bit 2 INT: mux DBL_WW0[1] bit 1 INT: mux DBL_WN0[1] bit 1 INT: mux DBL_WN0[1] bit 3 INT: mux DBL_WW0[1] bit 5 INT: mux IMUX_FAN[2] bit 7 INT: mux IMUX_FAN[3] bit 2 INT: mux IMUX_FAN[2] bit 1 INT: mux IMUX_FAN[3] bit 9 INT: mux IMUX_IMUX[2] bit 2 INT: mux IMUX_IMUX[8] bit 0 INT: mux IMUX_IMUX[2] bit 6 INT: mux IMUX_IMUX[37] bit 6 INT: mux IMUX_IMUX[43] bit 0 INT: mux IMUX_IMUX[8] bit 8 INT: mux IMUX_IMUX[8] bit 3 INT: mux IMUX_IMUX[2] bit 4 - -
B20 INT: mux PENT_NW0[0] bit 1 INT: mux PENT_WW0[1] bit 0 INT: mux PENT_NW0[0] bit 4 INT: mux PENT_NW0[0] bit 2 INT: mux PENT_WW0[1] bit 5 INT: mux PENT_NW0[0] bit 5 INT: mux DBL_WW0[1] bit 6 INT: mux DBL_NW0[0] bit 6 INT: mux DBL_NW0[0] bit 7 INT: mux DBL_WW0[1] bit 7 INT: mux DBL_NW0[0] bit 0 INT: mux DBL_NW0[0] bit 4 INT: mux IMUX_CTRL[0] bit 6 INT: mux DBL_WW0[1] bit 3 INT: mux IMUX_FAN[2] bit 8 INT: mux IMUX_FAN[2] bit 6 INT: mux IMUX_FAN[3] bit 6 INT: mux IMUX_FAN[3] bit 8 INT: mux IMUX_IMUX[37] bit 4 INT: mux IMUX_IMUX[37] bit 3 INT: mux IMUX_IMUX[43] bit 2 INT: mux IMUX_IMUX[43] bit 5 INT: mux IMUX_IMUX[43] bit 10 INT: mux IMUX_IMUX[37] bit 10 INT: mux IMUX_IMUX[37] bit 7 INT: mux IMUX_IMUX[43] bit 7 - -
B19 INT: mux PENT_WW0[1] bit 6 INT: mux PENT_NW0[0] bit 6 INT: mux PENT_NW0[0] bit 0 INT: mux PENT_NW0[0] bit 3 INT: mux PENT_WW0[1] bit 7 INT: mux PENT_NW0[0] bit 7 INT: mux DBL_WW0[1] bit 8 INT: mux DBL_NW0[0] bit 8 INT: mux DBL_NW0[0] bit 9 INT: mux DBL_WW0[1] bit 9 INT: mux DBL_NW0[0] bit 1 INT: mux DBL_NW0[0] bit 5 INT: mux IMUX_CTRL[1] bit 6 INT: mux DBL_NW0[0] bit 3 INT: mux IMUX_BYP[1] bit 9 INT: mux IMUX_BYP[1] bit 7 INT: mux IMUX_BYP[5] bit 7 INT: mux IMUX_BYP[5] bit 8 INT: mux IMUX_IMUX[43] bit 3 INT: mux IMUX_IMUX[37] bit 8 INT: mux IMUX_IMUX[43] bit 4 INT: mux IMUX_IMUX[43] bit 6 INT: mux IMUX_IMUX[37] bit 0 INT: mux IMUX_IMUX[43] bit 8 INT: mux IMUX_IMUX[37] bit 9 INT: mux IMUX_IMUX[43] bit 1 - -
B18 INT: mux PENT_WW0[1] bit 1 INT: mux PENT_NE0[0] bit 0 INT: mux PENT_EE0[3] bit 2 INT: mux PENT_WW0[1] bit 2 INT: mux PENT_NE0[0] bit 6 INT: mux PENT_NE0[0] bit 7 INT: mux DBL_WW0[1] bit 2 INT: mux DBL_NE0[0] bit 2 INT: mux DBL_NE0[0] bit 9 INT: mux DBL_NE0[0] bit 8 INT: mux DBL_WW0[1] bit 0 INT: mux DBL_NE0[0] bit 1 INT: mux DBL_NE0[0] bit 4 INT: mux DBL_WW0[1] bit 4 INT: mux IMUX_BYP[1] bit 6 INT: mux IMUX_BYP[1] bit 8 INT: mux IMUX_BYP[5] bit 9 INT: mux IMUX_BYP[5] bit 6 INT: mux IMUX_IMUX[43] bit 9 INT: mux IMUX_IMUX[25] bit 4 INT: mux IMUX_IMUX[25] bit 6 INT: mux IMUX_IMUX[37] bit 5 INT: mux IMUX_IMUX[31] bit 7 INT: mux IMUX_IMUX[31] bit 0 INT: mux IMUX_IMUX[31] bit 10 INT: mux IMUX_IMUX[25] bit 1 - -
B17 INT: mux PENT_EE0[3] bit 5 INT: mux PENT_EE0[3] bit 7 INT: mux PENT_EE0[3] bit 1 INT: mux PENT_NE0[0] bit 2 INT: mux PENT_EE0[3] bit 4 INT: mux PENT_EE0[3] bit 6 INT: mux DBL_EE0[4] bit 7 INT: mux DBL_EE0[4] bit 8 INT: mux DBL_EE0[4] bit 9 INT: mux DBL_EE0[4] bit 6 INT: mux DBL_EE0[4] bit 0 INT: mux DBL_EE0[4] bit 5 INT: mux DBL_EE0[4] bit 4 INT: mux DBL_EE0[4] bit 3 INT: mux IMUX_BYP[5] bit 0 INT: mux IMUX_BYP[1] bit 0 INT: mux IMUX_BYP[1] bit 5 INT: mux IMUX_BYP[1] bit 2 INT: mux IMUX_IMUX[31] bit 2 INT: mux IMUX_IMUX[25] bit 3 INT: mux IMUX_IMUX[31] bit 5 INT: mux IMUX_IMUX[31] bit 4 INT: mux IMUX_IMUX[25] bit 9 INT: mux IMUX_IMUX[25] bit 10 INT: mux IMUX_IMUX[25] bit 7 INT: mux IMUX_IMUX[25] bit 8 - -
B16 INT: mux PENT_EE0[3] bit 0 INT: mux PENT_NE0[0] bit 1 INT: mux PENT_NE0[0] bit 3 INT: mux PENT_EE0[3] bit 3 INT: mux PENT_NE0[0] bit 5 INT: mux PENT_NE0[0] bit 4 INT: mux DBL_NE0[0] bit 3 INT: mux DBL_EE0[4] bit 2 INT: mux DBL_NE0[0] bit 6 INT: mux DBL_NE0[0] bit 7 INT: mux DBL_EE0[4] bit 1 INT: mux DBL_NE0[0] bit 0 INT: mux DBL_NE0[0] bit 5 INT: mux IMUX_IMUX[37] bit 2 INT: mux IMUX_BYP[4] bit 1 INT: mux IMUX_BYP[5] bit 3 INT: mux IMUX_BYP[5] bit 5 INT: mux IMUX_BYP[1] bit 4 INT: mux IMUX_IMUX[31] bit 3 INT: mux IMUX_IMUX[25] bit 2 INT: mux IMUX_IMUX[25] bit 5 INT: mux IMUX_IMUX[31] bit 6 INT: mux IMUX_IMUX[25] bit 0 INT: mux IMUX_IMUX[31] bit 9 INT: mux IMUX_IMUX[31] bit 1 INT: mux IMUX_IMUX[31] bit 8 - -
B15 INT: mux PENT_NN0[0] bit 4 INT: mux PENT_NN0[0] bit 5 INT: mux PENT_NN0[0] bit 7 INT: mux PENT_EN0[0] bit 7 INT: mux PENT_NN0[0] bit 3 INT: mux PENT_NN0[0] bit 2 INT: mux DBL_EN0[0] bit 3 INT: mux DBL_NN0[1] bit 2 INT: mux DBL_NN0[1] bit 8 INT: mux DBL_NN0[1] bit 9 INT: mux DBL_EN0[0] bit 1 INT: mux DBL_NN0[1] bit 0 INT: mux DBL_NN0[1] bit 4 INT: mux IMUX_IMUX[13] bit 3 INT: mux IMUX_BYP[1] bit 3 INT: mux IMUX_BYP[1] bit 1 INT: mux IMUX_BYP[5] bit 4 INT: mux IMUX_BYP[5] bit 2 INT: mux IMUX_IMUX[19] bit 3 INT: mux IMUX_IMUX[13] bit 2 INT: mux IMUX_IMUX[13] bit 5 INT: mux IMUX_IMUX[19] bit 6 INT: mux IMUX_IMUX[13] bit 0 INT: mux IMUX_IMUX[19] bit 1 INT: mux IMUX_IMUX[19] bit 7 INT: mux IMUX_IMUX[19] bit 10 - -
B14 INT: mux PENT_EN0[0] bit 2 INT: mux PENT_EN0[0] bit 0 INT: mux PENT_EN0[0] bit 5 INT: mux PENT_NN0[0] bit 6 INT: mux PENT_EN0[0] bit 3 INT: mux PENT_EN0[0] bit 1 INT: mux DBL_EN0[0] bit 8 INT: mux DBL_EN0[0] bit 6 INT: mux DBL_EN0[0] bit 7 INT: mux DBL_EN0[0] bit 9 INT: mux DBL_EN0[0] bit 5 INT: mux DBL_EN0[0] bit 0 INT: mux DBL_NN0[1] bit 5 INT: mux DBL_EN0[0] bit 4 INT: mux IMUX_BYP[0] bit 3 INT: mux IMUX_BYP[4] bit 3 INT: mux IMUX_BYP[4] bit 5 INT: mux IMUX_BYP[4] bit 2 INT: mux IMUX_IMUX[13] bit 10 INT: mux IMUX_IMUX[13] bit 9 INT: mux IMUX_IMUX[19] bit 5 INT: mux IMUX_IMUX[19] bit 4 INT: mux IMUX_IMUX[13] bit 7 INT: mux IMUX_IMUX[19] bit 8 INT: mux IMUX_IMUX[13] bit 8 INT: mux IMUX_IMUX[1] bit 1 - -
B13 INT: mux PENT_EN0[0] bit 4 INT: mux PENT_NN0[0] bit 0 INT: mux PENT_EN0[0] bit 6 INT: mux PENT_ES0[0] bit 7 INT: mux PENT_ES0[0] bit 0 INT: mux PENT_NN0[0] bit 1 INT: mux DBL_EN0[0] bit 2 INT: mux DBL_NN0[1] bit 6 INT: mux DBL_NN0[1] bit 7 INT: mux DBL_SS0[3] bit 2 INT: mux DBL_ES0[0] bit 1 INT: mux DBL_NN0[1] bit 1 INT: mux DBL_NN0[1] bit 3 INT: mux DBL_ES0[0] bit 5 INT: mux IMUX_BYP[0] bit 0 INT: mux IMUX_BYP[0] bit 1 INT: mux IMUX_BYP[4] bit 4 INT: mux IMUX_BYP[0] bit 5 INT: mux IMUX_IMUX[13] bit 4 INT: mux IMUX_IMUX[19] bit 2 INT: mux IMUX_IMUX[13] bit 6 INT: mux IMUX_IMUX[1] bit 6 INT: mux IMUX_IMUX[7] bit 0 INT: mux IMUX_IMUX[19] bit 9 INT: mux IMUX_IMUX[19] bit 0 INT: mux IMUX_IMUX[13] bit 1 - -
B12 INT: mux PENT_SS0[3] bit 4 INT: mux PENT_ES0[0] bit 5 INT: mux PENT_SS0[3] bit 0 INT: mux PENT_SS0[3] bit 6 INT: mux PENT_ES0[0] bit 1 INT: mux PENT_SS0[3] bit 1 INT: mux DBL_ES0[0] bit 6 INT: mux DBL_SS0[3] bit 6 INT: mux DBL_SS0[3] bit 7 INT: mux DBL_ES0[0] bit 7 INT: mux DBL_SS0[3] bit 0 INT: mux DBL_SS0[3] bit 4 INT: mux IMUX_CTRL[1] bit 3 INT: mux DBL_ES0[0] bit 3 INT: mux IMUX_BYP[0] bit 8 INT: mux IMUX_BYP[4] bit 0 INT: mux IMUX_BYP[0] bit 2 INT: mux IMUX_BYP[4] bit 9 INT: mux IMUX_IMUX[1] bit 4 INT: mux IMUX_IMUX[1] bit 3 INT: mux IMUX_IMUX[7] bit 2 INT: mux IMUX_IMUX[7] bit 5 INT: mux IMUX_IMUX[7] bit 10 INT: mux IMUX_IMUX[1] bit 10 INT: mux IMUX_IMUX[1] bit 7 INT: mux IMUX_IMUX[7] bit 7 - -
B11 INT: mux PENT_ES0[0] bit 3 INT: mux PENT_SS0[3] bit 3 INT: mux PENT_SS0[3] bit 5 INT: mux PENT_SS0[3] bit 7 INT: mux PENT_ES0[0] bit 2 INT: mux PENT_SS0[3] bit 2 INT: mux DBL_ES0[0] bit 9 INT: mux DBL_SS0[3] bit 9 INT: mux DBL_SS0[3] bit 8 INT: mux DBL_ES0[0] bit 8 INT: mux DBL_SS0[3] bit 1 INT: mux DBL_SS0[3] bit 5 INT: mux IMUX_FAN[2] bit 5 INT: mux DBL_SS0[3] bit 3 INT: mux IMUX_BYP[0] bit 7 INT: mux IMUX_BYP[0] bit 9 INT: mux IMUX_BYP[4] bit 8 INT: mux IMUX_BYP[4] bit 7 INT: mux IMUX_IMUX[7] bit 3 INT: mux IMUX_IMUX[1] bit 8 INT: mux IMUX_IMUX[7] bit 4 INT: mux IMUX_IMUX[7] bit 6 INT: mux IMUX_IMUX[1] bit 0 INT: mux IMUX_IMUX[7] bit 8 INT: mux IMUX_IMUX[1] bit 9 INT: mux IMUX_IMUX[7] bit 1 - -
B10 INT: mux PENT_ES0[0] bit 4 INT: mux PENT_EE0[0] bit 1 INT: mux PENT_SE0[0] bit 2 INT: mux PENT_ES0[0] bit 6 INT: mux PENT_EE0[0] bit 5 INT: mux PENT_EE0[0] bit 4 INT: mux DBL_ES0[0] bit 2 INT: mux DBL_EE0[0] bit 3 INT: mux DBL_EE0[0] bit 6 INT: mux DBL_EE0[0] bit 7 INT: mux DBL_ES0[0] bit 0 INT: mux DBL_EE0[0] bit 0 INT: mux DBL_EE0[0] bit 4 INT: mux DBL_ES0[0] bit 4 INT: mux IMUX_FAN[0] bit 9 INT: mux IMUX_FAN[0] bit 8 INT: mux IMUX_FAN[1] bit 7 INT: mux IMUX_FAN[1] bit 9 INT: mux IMUX_IMUX[7] bit 9 INT: mux IMUX_IMUX[36] bit 2 INT: mux IMUX_IMUX[36] bit 6 INT: mux IMUX_IMUX[1] bit 5 INT: mux IMUX_IMUX[42] bit 10 INT: mux IMUX_IMUX[42] bit 3 INT: mux IMUX_IMUX[42] bit 9 INT: mux IMUX_IMUX[36] bit 4 - -
B9 INT: mux PENT_SE0[0] bit 7 INT: mux PENT_SE0[0] bit 4 INT: mux PENT_SE0[0] bit 0 INT: mux PENT_EE0[0] bit 2 INT: mux PENT_SE0[0] bit 6 INT: mux PENT_SE0[0] bit 5 INT: mux DBL_SE0[0] bit 9 INT: mux DBL_SE0[0] bit 7 INT: mux DBL_SE0[0] bit 6 INT: mux DBL_SE0[0] bit 8 INT: mux DBL_SE0[0] bit 1 INT: mux DBL_SE0[0] bit 5 INT: mux DBL_SE0[0] bit 4 INT: mux DBL_SE0[0] bit 2 INT: mux IMUX_FAN[0] bit 7 INT: mux IMUX_FAN[0] bit 6 INT: mux IMUX_FAN[1] bit 6 INT: mux IMUX_FAN[1] bit 8 INT: mux IMUX_IMUX[42] bit 1 INT: mux IMUX_IMUX[36] bit 0 INT: mux IMUX_IMUX[42] bit 5 INT: mux IMUX_IMUX[42] bit 2 INT: mux IMUX_IMUX[36] bit 7 INT: mux IMUX_IMUX[36] bit 9 INT: mux IMUX_IMUX[36] bit 10 INT: mux IMUX_IMUX[36] bit 8 - -
B8 INT: mux PENT_SE0[0] bit 1 INT: mux PENT_EE0[0] bit 0 INT: mux PENT_EE0[0] bit 3 INT: mux PENT_SE0[0] bit 3 INT: mux PENT_EE0[0] bit 7 INT: mux PENT_EE0[0] bit 6 INT: mux DBL_EE0[0] bit 2 INT: mux DBL_SE0[0] bit 3 INT: mux DBL_EE0[0] bit 8 INT: mux DBL_EE0[0] bit 9 INT: mux DBL_SE0[0] bit 0 INT: mux DBL_EE0[0] bit 1 INT: mux DBL_EE0[0] bit 5 INT: mux IMUX_IMUX[1] bit 2 INT: mux IMUX_FAN[0] bit 4 INT: mux IMUX_FAN[1] bit 2 INT: mux IMUX_FAN[0] bit 5 INT: mux IMUX_FAN[1] bit 1 INT: mux IMUX_IMUX[42] bit 0 INT: mux IMUX_IMUX[36] bit 1 INT: mux IMUX_IMUX[36] bit 5 INT: mux IMUX_IMUX[42] bit 6 INT: mux IMUX_IMUX[36] bit 3 INT: mux IMUX_IMUX[42] bit 7 INT: mux IMUX_IMUX[42] bit 4 INT: mux IMUX_IMUX[42] bit 8 - -
B7 INT: mux PENT_SW0[0] bit 0 INT: mux PENT_SW0[0] bit 1 INT: mux PENT_SW0[0] bit 3 INT: mux PENT_WW0[3] bit 3 INT: mux PENT_SW0[0] bit 7 INT: mux PENT_SW0[0] bit 6 INT: mux DBL_WW0_N5 bit 3 INT: mux DBL_SW0[0] bit 2 INT: mux DBL_SW0[0] bit 8 INT: mux DBL_SW0[0] bit 9 INT: mux DBL_WW0_N5 bit 1 INT: mux DBL_SW0[0] bit 0 INT: mux DBL_SW0[0] bit 4 INT: mux IMUX_IMUX[24] bit 0 INT: mux IMUX_BYP[0] bit 6 INT: mux IMUX_FAN[0] bit 2 INT: mux IMUX_FAN[0] bit 0 INT: mux IMUX_BYP[4] bit 6 INT: mux IMUX_IMUX[30] bit 0 INT: mux IMUX_IMUX[24] bit 1 INT: mux IMUX_IMUX[24] bit 5 INT: mux IMUX_IMUX[30] bit 6 INT: mux IMUX_IMUX[24] bit 3 INT: mux IMUX_IMUX[30] bit 4 INT: mux IMUX_IMUX[30] bit 10 INT: mux IMUX_IMUX[30] bit 9 - -
B6 INT: mux PENT_WW0[3] bit 6 INT: mux PENT_WW0[3] bit 5 INT: mux PENT_WW0[3] bit 1 INT: mux PENT_SW0[0] bit 2 INT: mux PENT_WW0[3] bit 7 INT: mux PENT_WW0[3] bit 4 INT: mux DBL_WW0_N5 bit 8 INT: mux DBL_WW0_N5 bit 7 INT: mux DBL_WW0_N5 bit 6 INT: mux DBL_WW0_N5 bit 9 INT: mux DBL_WW0_N5 bit 5 INT: mux DBL_WW0_N5 bit 0 INT: mux DBL_SW0[0] bit 5 INT: mux DBL_WW0_N5 bit 4 INT: mux IMUX_FAN[0] bit 3 INT: mux IMUX_FAN[1] bit 3 INT: mux IMUX_FAN[1] bit 0 INT: mux IMUX_FAN[1] bit 5 INT: mux IMUX_IMUX[24] bit 9 INT: mux IMUX_IMUX[24] bit 7 INT: mux IMUX_IMUX[30] bit 5 INT: mux IMUX_IMUX[30] bit 2 INT: mux IMUX_IMUX[24] bit 10 INT: mux IMUX_IMUX[30] bit 8 INT: mux IMUX_IMUX[24] bit 8 INT: mux IMUX_IMUX[12] bit 4 - -
B5 INT: mux PENT_WW0[3] bit 0 INT: mux PENT_SW0[0] bit 5 INT: mux PENT_WW0[3] bit 2 INT: mux PENT_SS0[0] bit 7 INT: mux PENT_SS0[0] bit 3 INT: mux PENT_SW0[0] bit 4 INT: mux DBL_WW0_N5 bit 2 INT: mux DBL_SW0[0] bit 7 INT: mux DBL_SW0[0] bit 6 INT: mux DBL_WS0[0] bit 2 INT: mux DBL_SS0_N2 bit 1 INT: mux DBL_SW0[0] bit 1 INT: mux DBL_SW0[0] bit 3 INT: mux DBL_SS0_N2 bit 5 INT: mux LV[18] bit 7 INT: mux LV[18] bit 6 INT: mux LH[18] bit 6 INT: mux LH[18] bit 7 INT: mux IMUX_IMUX[24] bit 2 INT: mux IMUX_IMUX[30] bit 1 INT: mux IMUX_IMUX[24] bit 6 INT: mux IMUX_IMUX[12] bit 6 INT: mux IMUX_IMUX[18] bit 3 INT: mux IMUX_IMUX[30] bit 7 INT: mux IMUX_IMUX[30] bit 3 INT: mux IMUX_IMUX[24] bit 4 - -
B4 INT: mux PENT_WS0[0] bit 4 INT: mux PENT_SS0[0] bit 5 INT: mux PENT_WS0[0] bit 3 INT: mux PENT_WS0[0] bit 6 INT: mux PENT_SS0[0] bit 2 INT: mux PENT_WS0[0] bit 2 INT: mux DBL_SS0_N2 bit 9 INT: mux DBL_WS0[0] bit 9 INT: mux DBL_WS0[0] bit 8 INT: mux DBL_SS0_N2 bit 8 INT: mux DBL_WS0[0] bit 0 INT: mux DBL_WS0[0] bit 4 INT: mux IMUX_FAN[2] bit 9 INT: mux DBL_SS0_N2 bit 3 INT: mux LV[18] bit 5 INT: mux LV[18] bit 9 INT: mux LH[18] bit 9 INT: mux LH[18] bit 5 INT: mux IMUX_IMUX[12] bit 2 INT: mux IMUX_IMUX[12] bit 0 INT: mux IMUX_IMUX[18] bit 1 INT: mux IMUX_IMUX[18] bit 5 INT: mux IMUX_IMUX[18] bit 9 INT: mux IMUX_IMUX[12] bit 9 INT: mux IMUX_IMUX[12] bit 10 INT: mux IMUX_IMUX[18] bit 10 - -
B3 INT: mux PENT_SS0[0] bit 0 INT: mux PENT_WS0[0] bit 0 INT: mux PENT_WS0[0] bit 5 INT: mux PENT_WS0[0] bit 7 INT: mux PENT_SS0[0] bit 1 INT: mux PENT_WS0[0] bit 1 INT: mux DBL_SS0_N2 bit 6 INT: mux DBL_WS0[0] bit 6 INT: mux DBL_WS0[0] bit 7 INT: mux DBL_SS0_N2 bit 7 INT: mux DBL_WS0[0] bit 1 INT: mux DBL_WS0[0] bit 5 INT: mux IMUX_FAN[3] bit 7 INT: mux DBL_WS0[0] bit 3 INT: mux LH[18] bit 2 INT: mux LV[18] bit 0 INT: mux LH[18] bit 0 INT: mux LV[18] bit 4 INT: mux IMUX_IMUX[18] bit 0 INT: mux IMUX_IMUX[12] bit 8 INT: mux IMUX_IMUX[18] bit 2 INT: mux IMUX_IMUX[18] bit 6 INT: mux IMUX_IMUX[12] bit 3 INT: mux IMUX_IMUX[18] bit 8 INT: mux IMUX_IMUX[12] bit 7 INT: mux IMUX_IMUX[18] bit 4 - -
B2 INT: mux PENT_SS0[0] bit 4 INT: mux PENT_WN0[0] bit 4 INT: mux PENT_NN0_N5 bit 6 INT: mux PENT_SS0[0] bit 6 INT: mux PENT_WN0[0] bit 0 INT: mux PENT_WN0[0] bit 1 INT: mux DBL_SS0_N2 bit 2 INT: mux DBL_WN0[0] bit 2 INT: mux DBL_WN0[0] bit 7 INT: mux DBL_WN0[0] bit 6 INT: mux DBL_SS0_N2 bit 0 INT: mux DBL_WN0[0] bit 1 INT: mux DBL_WN0[0] bit 4 INT: mux DBL_SS0_N2 bit 4 INT: mux LV[18] bit 2 INT: mux IMUX_BYP[5] bit 1 INT: mux IMUX_BYP[0] bit 4 INT: mux LH[18] bit 4 INT: mux IMUX_IMUX[18] bit 7 INT: mux IMUX_IMUX[0] bit 2 INT: mux IMUX_IMUX[0] bit 6 INT: mux IMUX_IMUX[12] bit 5 INT: mux IMUX_IMUX[6] bit 10 INT: mux IMUX_IMUX[6] bit 3 INT: mux IMUX_IMUX[6] bit 9 INT: mux IMUX_IMUX[0] bit 4 - -
B1 INT: mux PENT_NN0_N5 bit 3 INT: mux PENT_NN0_N5 bit 1 INT: mux PENT_NN0_N5 bit 5 INT: mux PENT_WN0[0] bit 6 INT: mux PENT_NN0_N5 bit 2 INT: mux PENT_NN0_N5 bit 0 INT: mux DBL_NN0_N5 bit 9 INT: mux DBL_NN0_N5 bit 6 INT: mux DBL_NN0_N5 bit 7 INT: mux DBL_NN0_N5 bit 8 INT: mux DBL_NN0_N5 bit 0 INT: mux DBL_NN0_N5 bit 5 INT: mux DBL_NN0_N5 bit 4 INT: mux DBL_NN0_N5 bit 3 INT: mux LH[18] bit 3 INT: mux LV[18] bit 3 INT: mux LH[18] bit 1 INT: mux LV[18] bit 1 INT: mux IMUX_IMUX[6] bit 1 INT: mux IMUX_IMUX[0] bit 0 INT: mux IMUX_IMUX[6] bit 5 INT: mux IMUX_IMUX[6] bit 2 INT: mux IMUX_IMUX[0] bit 7 INT: mux IMUX_IMUX[0] bit 9 INT: mux IMUX_IMUX[0] bit 10 INT: mux IMUX_IMUX[0] bit 8 - -
B0 INT: mux PENT_NN0_N5 bit 4 INT: mux PENT_WN0[0] bit 5 INT: mux PENT_WN0[0] bit 7 INT: mux PENT_NN0_N5 bit 7 INT: mux PENT_WN0[0] bit 3 INT: mux PENT_WN0[0] bit 2 INT: mux DBL_WN0[0] bit 3 INT: mux DBL_NN0_N5 bit 2 INT: mux DBL_WN0[0] bit 8 INT: mux DBL_WN0[0] bit 9 INT: mux DBL_NN0_N5 bit 1 INT: mux DBL_WN0[0] bit 0 INT: mux DBL_WN0[0] bit 5 INT: mux IMUX_IMUX[12] bit 1 INT: mux IMUX_FAN[1] bit 4 INT: mux LV[18] bit 8 INT: mux LH[18] bit 8 INT: mux IMUX_FAN[0] bit 1 INT: mux IMUX_IMUX[6] bit 0 INT: mux IMUX_IMUX[0] bit 1 INT: mux IMUX_IMUX[0] bit 5 INT: mux IMUX_IMUX[6] bit 6 INT: mux IMUX_IMUX[0] bit 3 INT: mux IMUX_IMUX[6] bit 7 INT: mux IMUX_IMUX[6] bit 4 INT: mux IMUX_IMUX[6] bit 8 - -

Tile INTF

Cells: 1

Switchbox INTF_INT

virtex5 INTF switchbox INTF_INT muxes OUT_TEST[0]
BitsDestination
MAIN[27][15]OUT_TEST[0]
Source
0IMUX_IMUX[31]
1IMUX_IMUX[25]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[1]
BitsDestination
MAIN[26][13]OUT_TEST[1]
Source
0IMUX_IMUX[19]
1IMUX_IMUX[13]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[2]
BitsDestination
MAIN[26][50]OUT_TEST[2]
Source
0IMUX_IMUX[34]
1IMUX_IMUX[28]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[3]
BitsDestination
MAIN[27][48]OUT_TEST[3]
Source
0IMUX_IMUX[22]
1IMUX_IMUX[16]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[4]
BitsDestination
MAIN[26][14]MAIN[26][10]OUT_TEST[4]
Source
00IMUX_CLK[0]
01IMUX_IMUX[1]
10IMUX_IMUX[7]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[5]
BitsDestination
MAIN[27][19]OUT_TEST[5]
Source
0IMUX_IMUX[43]
1IMUX_IMUX[37]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[6]
BitsDestination
MAIN[27][49]MAIN[27][44]OUT_TEST[6]
Source
00IMUX_CLK[1]
01IMUX_IMUX[4]
10IMUX_IMUX[10]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[7]
BitsDestination
MAIN[26][53]OUT_TEST[7]
Source
0IMUX_IMUX[46]
1IMUX_IMUX[40]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[8]
BitsDestination
MAIN[26][4]OUT_TEST[8]
Source
0IMUX_IMUX[18]
1IMUX_IMUX[12]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[9]
BitsDestination
MAIN[27][25]OUT_TEST[9]
Source
0IMUX_IMUX[32]
1IMUX_IMUX[26]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[10]
BitsDestination
MAIN[27][38]OUT_TEST[10]
Source
0IMUX_IMUX[21]
1IMUX_IMUX[15]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[11]
BitsDestination
MAIN[26][59]OUT_TEST[11]
Source
0IMUX_IMUX[35]
1IMUX_IMUX[29]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[12]
BitsDestination
MAIN[26][9]OUT_TEST[12]
Source
0IMUX_IMUX[42]
1IMUX_IMUX[36]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[13]
BitsDestination
MAIN[26][24]MAIN[26][19]OUT_TEST[13]
Source
00IMUX_SPEC[1]
01IMUX_IMUX[2]
10IMUX_IMUX[8]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[14]
BitsDestination
MAIN[26][44]OUT_TEST[14]
Source
0IMUX_IMUX[45]
1IMUX_IMUX[39]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[15]
BitsDestination
MAIN[27][59]MAIN[27][54]OUT_TEST[15]
Source
00IMUX_SPEC[3]
01IMUX_IMUX[5]
10IMUX_IMUX[11]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[16]
BitsDestination
MAIN[26][40]OUT_TEST[16]
Source
0IMUX_IMUX[33]
1IMUX_IMUX[27]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[17]
BitsDestination
MAIN[27][58]OUT_TEST[17]
Source
0IMUX_IMUX[23]
1IMUX_IMUX[17]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[18]
BitsDestination
MAIN[27][5]OUT_TEST[18]
Source
0IMUX_IMUX[30]
1IMUX_IMUX[24]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[19]
BitsDestination
MAIN[26][23]OUT_TEST[19]
Source
0IMUX_IMUX[20]
1IMUX_IMUX[14]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[20]
BitsDestination
MAIN[26][39]MAIN[27][35]OUT_TEST[20]
Source
00IMUX_SPEC[2]
01IMUX_IMUX[3]
10IMUX_IMUX[9]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[21]
BitsDestination
MAIN[26][63]OUT_TEST[21]
Source
0IMUX_IMUX[47]
1IMUX_IMUX[41]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[22]
BitsDestination
MAIN[27][4]MAIN[26][0]OUT_TEST[22]
Source
00IMUX_SPEC[0]
01IMUX_IMUX[0]
10IMUX_IMUX[6]
virtex5 INTF switchbox INTF_INT muxes OUT_TEST[23]
BitsDestination
MAIN[27][28]OUT_TEST[23]
Source
0IMUX_IMUX[44]
1IMUX_IMUX[38]

Test mux INTF_TESTMUX

virtex5 INTF INTF_TESTMUX mux
DestinationPrimary source Test source 0
OUT[0]OUT_BEL[0] OUT_TEST[0]
OUT[1]OUT_BEL[1] OUT_TEST[1]
OUT[2]OUT_BEL[2] OUT_TEST[2]
OUT[3]OUT_BEL[3] OUT_TEST[3]
OUT[4]OUT_BEL[4] OUT_TEST[4]
OUT[5]OUT_BEL[5] OUT_TEST[5]
OUT[6]OUT_BEL[6] OUT_TEST[6]
OUT[7]OUT_BEL[7] OUT_TEST[7]
OUT[8]OUT_BEL[8] OUT_TEST[8]
OUT[9]OUT_BEL[9] OUT_TEST[9]
OUT[10]OUT_BEL[10] OUT_TEST[10]
OUT[11]OUT_BEL[11] OUT_TEST[11]
OUT[12]OUT_BEL[12] OUT_TEST[12]
OUT[13]OUT_BEL[13] OUT_TEST[13]
OUT[14]OUT_BEL[14] OUT_TEST[14]
OUT[15]OUT_BEL[15] OUT_TEST[15]
OUT[16]OUT_BEL[16] OUT_TEST[16]
OUT[17]OUT_BEL[17] OUT_TEST[17]
OUT[18]OUT_BEL[18] OUT_TEST[18]
OUT[19]OUT_BEL[19] OUT_TEST[19]
OUT[20]OUT_BEL[20] OUT_TEST[20]
OUT[21]OUT_BEL[21] OUT_TEST[21]
OUT[22]OUT_BEL[22] OUT_TEST[22]
OUT[23]OUT_BEL[23] OUT_TEST[23]
virtex5 INTF INTF_TESTMUX bits
GroupMAIN[27][30]
Primary0
Test 01

Bitstream

virtex5 INTF rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[21] bit 0 -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[11] bit 0 INTF_INT: mux OUT_TEST[15] bit 1
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[17] bit 0
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[15] bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[7] bit 0 -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[2] bit 0 -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[6] bit 1
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[3] bit 0
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[14] bit 0 INTF_INT: mux OUT_TEST[6] bit 0
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[16] bit 0 -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[20] bit 1 -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[10] bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[20] bit 0
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_TESTMUX: test mux bit 0
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[23] bit 0
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[9] bit 0
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[13] bit 1 -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[19] bit 0 -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[13] bit 0 INTF_INT: mux OUT_TEST[5] bit 0
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[0] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[4] bit 1 -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[1] bit 0 -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[4] bit 0 -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[12] bit 0 -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[18] bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[8] bit 0 INTF_INT: mux OUT_TEST[22] bit 1
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[22] bit 0 -

Tile INTF_DELAY

Cells: 1

Switchbox INTF_INT

virtex5 INTF_DELAY switchbox INTF_INT delays
DestinationSourceBits
IMUX_IMUX_DELAY[0]IMUX_IMUX[0]MAIN[27][0]
IMUX_IMUX_DELAY[1]IMUX_IMUX[1]MAIN[27][11]
IMUX_IMUX_DELAY[2]IMUX_IMUX[2]MAIN[26][21]
IMUX_IMUX_DELAY[3]IMUX_IMUX[3]MAIN[27][32]
IMUX_IMUX_DELAY[4]IMUX_IMUX[4]MAIN[27][42]
IMUX_IMUX_DELAY[5]IMUX_IMUX[5]MAIN[27][53]
IMUX_IMUX_DELAY[6]IMUX_IMUX[6]MAIN[26][1]
IMUX_IMUX_DELAY[7]IMUX_IMUX[7]MAIN[26][12]
IMUX_IMUX_DELAY[8]IMUX_IMUX[8]MAIN[27][22]
IMUX_IMUX_DELAY[9]IMUX_IMUX[9]MAIN[26][33]
IMUX_IMUX_DELAY[10]IMUX_IMUX[10]MAIN[26][43]
IMUX_IMUX_DELAY[11]IMUX_IMUX[11]MAIN[27][55]
IMUX_IMUX_DELAY[12]IMUX_IMUX[12]MAIN[27][2]
IMUX_IMUX_DELAY[13]IMUX_IMUX[13]MAIN[27][13]
IMUX_IMUX_DELAY[14]IMUX_IMUX[14]MAIN[27][24]
IMUX_IMUX_DELAY[15]IMUX_IMUX[15]MAIN[27][34]
IMUX_IMUX_DELAY[16]IMUX_IMUX[16]MAIN[26][45]
IMUX_IMUX_DELAY[17]IMUX_IMUX[17]MAIN[27][56]
IMUX_IMUX_DELAY[18]IMUX_IMUX[18]MAIN[26][3]
IMUX_IMUX_DELAY[19]IMUX_IMUX[19]MAIN[26][15]
IMUX_IMUX_DELAY[20]IMUX_IMUX[20]MAIN[26][26]
IMUX_IMUX_DELAY[21]IMUX_IMUX[21]MAIN[26][36]
IMUX_IMUX_DELAY[22]IMUX_IMUX[22]MAIN[27][46]
IMUX_IMUX_DELAY[23]IMUX_IMUX[23]MAIN[26][57]
IMUX_IMUX_DELAY[24]IMUX_IMUX[24]MAIN[26][6]
IMUX_IMUX_DELAY[25]IMUX_IMUX[25]MAIN[27][16]
IMUX_IMUX_DELAY[26]IMUX_IMUX[26]MAIN[27][27]
IMUX_IMUX_DELAY[27]IMUX_IMUX[27]MAIN[27][37]
IMUX_IMUX_DELAY[28]IMUX_IMUX[28]MAIN[26][47]
IMUX_IMUX_DELAY[29]IMUX_IMUX[29]MAIN[26][60]
IMUX_IMUX_DELAY[30]IMUX_IMUX[30]MAIN[27][7]
IMUX_IMUX_DELAY[31]IMUX_IMUX[31]MAIN[26][17]
IMUX_IMUX_DELAY[32]IMUX_IMUX[32]MAIN[26][28]
IMUX_IMUX_DELAY[33]IMUX_IMUX[33]MAIN[26][38]
IMUX_IMUX_DELAY[34]IMUX_IMUX[34]MAIN[26][49]
IMUX_IMUX_DELAY[35]IMUX_IMUX[35]MAIN[27][61]
IMUX_IMUX_DELAY[36]IMUX_IMUX[36]MAIN[26][8]
IMUX_IMUX_DELAY[37]IMUX_IMUX[37]MAIN[27][18]
IMUX_IMUX_DELAY[38]IMUX_IMUX[38]MAIN[26][29]
IMUX_IMUX_DELAY[39]IMUX_IMUX[39]MAIN[27][40]
IMUX_IMUX_DELAY[40]IMUX_IMUX[40]MAIN[27][51]
IMUX_IMUX_DELAY[41]IMUX_IMUX[41]MAIN[26][62]
IMUX_IMUX_DELAY[42]IMUX_IMUX[42]MAIN[27][9]
IMUX_IMUX_DELAY[43]IMUX_IMUX[43]MAIN[27][20]
IMUX_IMUX_DELAY[44]IMUX_IMUX[44]MAIN[27][31]
IMUX_IMUX_DELAY[45]IMUX_IMUX[45]MAIN[26][41]
IMUX_IMUX_DELAY[46]IMUX_IMUX[46]MAIN[26][52]
IMUX_IMUX_DELAY[47]IMUX_IMUX[47]MAIN[27][63]
Delay step
00
11
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[0]
BitsDestination
MAIN[27][15]OUT_TEST[0]
Source
0IMUX_IMUX_DELAY[31]
1IMUX_IMUX_DELAY[25]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[1]
BitsDestination
MAIN[26][13]OUT_TEST[1]
Source
0IMUX_IMUX_DELAY[19]
1IMUX_IMUX_DELAY[13]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[2]
BitsDestination
MAIN[26][50]OUT_TEST[2]
Source
0IMUX_IMUX_DELAY[34]
1IMUX_IMUX_DELAY[28]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[3]
BitsDestination
MAIN[27][48]OUT_TEST[3]
Source
0IMUX_IMUX_DELAY[22]
1IMUX_IMUX_DELAY[16]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[4]
BitsDestination
MAIN[26][14]MAIN[26][10]OUT_TEST[4]
Source
00IMUX_CLK[0]
01IMUX_IMUX_DELAY[1]
10IMUX_IMUX_DELAY[7]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[5]
BitsDestination
MAIN[27][19]OUT_TEST[5]
Source
0IMUX_IMUX_DELAY[43]
1IMUX_IMUX_DELAY[37]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[6]
BitsDestination
MAIN[27][49]MAIN[27][44]OUT_TEST[6]
Source
00IMUX_CLK[1]
01IMUX_IMUX_DELAY[4]
10IMUX_IMUX_DELAY[10]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[7]
BitsDestination
MAIN[26][53]OUT_TEST[7]
Source
0IMUX_IMUX_DELAY[46]
1IMUX_IMUX_DELAY[40]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[8]
BitsDestination
MAIN[26][4]OUT_TEST[8]
Source
0IMUX_IMUX_DELAY[18]
1IMUX_IMUX_DELAY[12]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[9]
BitsDestination
MAIN[27][25]OUT_TEST[9]
Source
0IMUX_IMUX_DELAY[32]
1IMUX_IMUX_DELAY[26]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[10]
BitsDestination
MAIN[27][38]OUT_TEST[10]
Source
0IMUX_IMUX_DELAY[21]
1IMUX_IMUX_DELAY[15]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[11]
BitsDestination
MAIN[26][59]OUT_TEST[11]
Source
0IMUX_IMUX_DELAY[35]
1IMUX_IMUX_DELAY[29]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[12]
BitsDestination
MAIN[26][9]OUT_TEST[12]
Source
0IMUX_IMUX_DELAY[42]
1IMUX_IMUX_DELAY[36]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[13]
BitsDestination
MAIN[26][24]MAIN[26][19]OUT_TEST[13]
Source
00IMUX_SPEC[1]
01IMUX_IMUX_DELAY[2]
10IMUX_IMUX_DELAY[8]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[14]
BitsDestination
MAIN[26][44]OUT_TEST[14]
Source
0IMUX_IMUX_DELAY[45]
1IMUX_IMUX_DELAY[39]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[15]
BitsDestination
MAIN[27][59]MAIN[27][54]OUT_TEST[15]
Source
00IMUX_SPEC[3]
01IMUX_IMUX_DELAY[5]
10IMUX_IMUX_DELAY[11]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[16]
BitsDestination
MAIN[26][40]OUT_TEST[16]
Source
0IMUX_IMUX_DELAY[33]
1IMUX_IMUX_DELAY[27]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[17]
BitsDestination
MAIN[27][58]OUT_TEST[17]
Source
0IMUX_IMUX_DELAY[23]
1IMUX_IMUX_DELAY[17]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[18]
BitsDestination
MAIN[27][5]OUT_TEST[18]
Source
0IMUX_IMUX_DELAY[30]
1IMUX_IMUX_DELAY[24]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[19]
BitsDestination
MAIN[26][23]OUT_TEST[19]
Source
0IMUX_IMUX_DELAY[20]
1IMUX_IMUX_DELAY[14]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[20]
BitsDestination
MAIN[26][39]MAIN[27][35]OUT_TEST[20]
Source
00IMUX_SPEC[2]
01IMUX_IMUX_DELAY[3]
10IMUX_IMUX_DELAY[9]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[21]
BitsDestination
MAIN[26][63]OUT_TEST[21]
Source
0IMUX_IMUX_DELAY[47]
1IMUX_IMUX_DELAY[41]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[22]
BitsDestination
MAIN[27][4]MAIN[26][0]OUT_TEST[22]
Source
00IMUX_SPEC[0]
01IMUX_IMUX_DELAY[0]
10IMUX_IMUX_DELAY[6]
virtex5 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[23]
BitsDestination
MAIN[27][28]OUT_TEST[23]
Source
0IMUX_IMUX_DELAY[44]
1IMUX_IMUX_DELAY[38]

Test mux INTF_TESTMUX

virtex5 INTF_DELAY INTF_TESTMUX mux
DestinationPrimary source Test source 0
OUT[0]OUT_BEL[0] OUT_TEST[0]
OUT[1]OUT_BEL[1] OUT_TEST[1]
OUT[2]OUT_BEL[2] OUT_TEST[2]
OUT[3]OUT_BEL[3] OUT_TEST[3]
OUT[4]OUT_BEL[4] OUT_TEST[4]
OUT[5]OUT_BEL[5] OUT_TEST[5]
OUT[6]OUT_BEL[6] OUT_TEST[6]
OUT[7]OUT_BEL[7] OUT_TEST[7]
OUT[8]OUT_BEL[8] OUT_TEST[8]
OUT[9]OUT_BEL[9] OUT_TEST[9]
OUT[10]OUT_BEL[10] OUT_TEST[10]
OUT[11]OUT_BEL[11] OUT_TEST[11]
OUT[12]OUT_BEL[12] OUT_TEST[12]
OUT[13]OUT_BEL[13] OUT_TEST[13]
OUT[14]OUT_BEL[14] OUT_TEST[14]
OUT[15]OUT_BEL[15] OUT_TEST[15]
OUT[16]OUT_BEL[16] OUT_TEST[16]
OUT[17]OUT_BEL[17] OUT_TEST[17]
OUT[18]OUT_BEL[18] OUT_TEST[18]
OUT[19]OUT_BEL[19] OUT_TEST[19]
OUT[20]OUT_BEL[20] OUT_TEST[20]
OUT[21]OUT_BEL[21] OUT_TEST[21]
OUT[22]OUT_BEL[22] OUT_TEST[22]
OUT[23]OUT_BEL[23] OUT_TEST[23]
virtex5 INTF_DELAY INTF_TESTMUX bits
GroupMAIN[27][30]
Primary0
Test 01

Bitstream

virtex5 INTF_DELAY rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[21] bit 0 INTF_INT: delay IMUX_IMUX_DELAY[47] ← IMUX_IMUX[47] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[41] ← IMUX_IMUX[41] bit 0 -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[35] ← IMUX_IMUX[35] bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[29] ← IMUX_IMUX[29] bit 0 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[11] bit 0 INTF_INT: mux OUT_TEST[15] bit 1
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[17] bit 0
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[23] ← IMUX_IMUX[23] bit 0 -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[17] ← IMUX_IMUX[17] bit 0
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[11] ← IMUX_IMUX[11] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[15] bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[7] bit 0 INTF_INT: delay IMUX_IMUX_DELAY[5] ← IMUX_IMUX[5] bit 0
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[46] ← IMUX_IMUX[46] bit 0 -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[40] ← IMUX_IMUX[40] bit 0
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[2] bit 0 -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[34] ← IMUX_IMUX[34] bit 0 INTF_INT: mux OUT_TEST[6] bit 1
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[3] bit 0
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[28] ← IMUX_IMUX[28] bit 0 -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[22] ← IMUX_IMUX[22] bit 0
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[16] ← IMUX_IMUX[16] bit 0 -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[14] bit 0 INTF_INT: mux OUT_TEST[6] bit 0
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[10] ← IMUX_IMUX[10] bit 0 -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[4] ← IMUX_IMUX[4] bit 0
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[45] ← IMUX_IMUX[45] bit 0 -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[16] bit 0 INTF_INT: delay IMUX_IMUX_DELAY[39] ← IMUX_IMUX[39] bit 0
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[20] bit 1 -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[33] ← IMUX_IMUX[33] bit 0 INTF_INT: mux OUT_TEST[10] bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[27] ← IMUX_IMUX[27] bit 0
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[21] ← IMUX_IMUX[21] bit 0 -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[20] bit 0
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[15] ← IMUX_IMUX[15] bit 0
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[9] ← IMUX_IMUX[9] bit 0 -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[3] ← IMUX_IMUX[3] bit 0
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[44] ← IMUX_IMUX[44] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_TESTMUX: test mux bit 0
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[38] ← IMUX_IMUX[38] bit 0 -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[32] ← IMUX_IMUX[32] bit 0 INTF_INT: mux OUT_TEST[23] bit 0
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[26] ← IMUX_IMUX[26] bit 0
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[20] ← IMUX_IMUX[20] bit 0 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[9] bit 0
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[13] bit 1 INTF_INT: delay IMUX_IMUX_DELAY[14] ← IMUX_IMUX[14] bit 0
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[19] bit 0 -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[8] ← IMUX_IMUX[8] bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[2] ← IMUX_IMUX[2] bit 0 -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[43] ← IMUX_IMUX[43] bit 0
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[13] bit 0 INTF_INT: mux OUT_TEST[5] bit 0
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[37] ← IMUX_IMUX[37] bit 0
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[31] ← IMUX_IMUX[31] bit 0 -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[25] ← IMUX_IMUX[25] bit 0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[19] ← IMUX_IMUX[19] bit 0 INTF_INT: mux OUT_TEST[0] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[4] bit 1 -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[1] bit 0 INTF_INT: delay IMUX_IMUX_DELAY[13] ← IMUX_IMUX[13] bit 0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[7] ← IMUX_IMUX[7] bit 0 -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[1] ← IMUX_IMUX[1] bit 0
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[4] bit 0 -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[12] bit 0 INTF_INT: delay IMUX_IMUX_DELAY[42] ← IMUX_IMUX[42] bit 0
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[36] ← IMUX_IMUX[36] bit 0 -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[30] ← IMUX_IMUX[30] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[24] ← IMUX_IMUX[24] bit 0 -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[18] bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[8] bit 0 INTF_INT: mux OUT_TEST[22] bit 1
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[18] ← IMUX_IMUX[18] bit 0 -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[12] ← IMUX_IMUX[12] bit 0
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: delay IMUX_IMUX_DELAY[6] ← IMUX_IMUX[6] bit 0 -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_TEST[22] bit 0 INTF_INT: delay IMUX_IMUX_DELAY[0] ← IMUX_IMUX[0] bit 0