DSP

Tile DSP

Cells: 5

Switchbox SPEC_INT

virtex6 DSP switchbox SPEC_INT muxes IMUX_BYP_DSP[0]
Bits		Destination
MAIN[1][26][63]	MAIN[2][27][2]	CELL[0].IMUX_BYP_DSP[0]	-	-	-	-
MAIN[1][26][28]	MAIN[1][27][20]	-	CELL[1].IMUX_BYP_DSP[0]	-	-	-
MAIN[2][26][22]	MAIN[2][27][19]	-	-	CELL[2].IMUX_BYP_DSP[0]	-	-
MAIN[3][26][60]	MAIN[3][27][52]	-	-	-	CELL[3].IMUX_BYP_DSP[0]	-
MAIN[4][26][31]	MAIN[4][27][34]	-	-	-	-	CELL[4].IMUX_BYP_DSP[0]
		Source
0	0	CELL[0].IMUX_BYP_SITE[0]	CELL[1].IMUX_BYP_SITE[0]	CELL[2].IMUX_BYP_SITE[0]	CELL[3].IMUX_BYP_SITE[0]	CELL[4].IMUX_BYP_SITE[0]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_BYP_DSP[1]
Bits		Destination
MAIN[0][27][14]	MAIN[0][27][15]	CELL[0].IMUX_BYP_DSP[1]	-	-	-	-
MAIN[0][27][39]	MAIN[0][27][41]	-	CELL[1].IMUX_BYP_DSP[1]	-	-	-
MAIN[0][27][57]	MAIN[0][26][62]	-	-	CELL[2].IMUX_BYP_DSP[1]	-	-
MAIN[1][27][43]	MAIN[1][27][45]	-	-	-	CELL[3].IMUX_BYP_DSP[1]	-
MAIN[2][27][3]	MAIN[2][26][7]	-	-	-	-	CELL[4].IMUX_BYP_DSP[1]
		Source
0	0	CELL[0].IMUX_BYP_SITE[1]	CELL[1].IMUX_BYP_SITE[1]	CELL[2].IMUX_BYP_SITE[1]	CELL[3].IMUX_BYP_SITE[1]	CELL[4].IMUX_BYP_SITE[1]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_BYP_DSP[2]
Bits		Destination
MAIN[2][26][31]	MAIN[2][27][28]	CELL[0].IMUX_BYP_DSP[2]	-	-	-	-
MAIN[4][27][20]	MAIN[4][27][24]	-	CELL[1].IMUX_BYP_DSP[2]	-	-	-
MAIN[0][26][15]	MAIN[0][26][19]	-	-	CELL[2].IMUX_BYP_DSP[2]	-	-
MAIN[2][27][23]	MAIN[2][26][25]	-	-	-	CELL[3].IMUX_BYP_DSP[2]	-
MAIN[2][26][47]	MAIN[2][26][51]	-	-	-	-	CELL[4].IMUX_BYP_DSP[2]
		Source
0	0	CELL[0].IMUX_BYP_SITE[2]	CELL[1].IMUX_BYP_SITE[2]	CELL[2].IMUX_BYP_SITE[2]	CELL[3].IMUX_BYP_SITE[2]	CELL[4].IMUX_BYP_SITE[2]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_BYP_DSP[3]
Bits		Destination
MAIN[0][27][13]	MAIN[0][27][11]	CELL[0].IMUX_BYP_DSP[3]	-	-	-	-
MAIN[0][27][37]	MAIN[0][27][34]	-	CELL[1].IMUX_BYP_DSP[3]	-	-	-
MAIN[0][26][56]	MAIN[0][26][53]	-	-	CELL[2].IMUX_BYP_DSP[3]	-	-
MAIN[1][26][40]	MAIN[1][27][39]	-	-	-	CELL[3].IMUX_BYP_DSP[3]	-
MAIN[2][26][1]	MAIN[1][26][61]	-	-	-	-	CELL[4].IMUX_BYP_DSP[3]
		Source
0	0	CELL[0].IMUX_BYP_SITE[3]	CELL[1].IMUX_BYP_SITE[3]	CELL[2].IMUX_BYP_SITE[3]	CELL[3].IMUX_BYP_SITE[3]	CELL[4].IMUX_BYP_SITE[3]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_BYP_DSP[4]
Bits		Destination
MAIN[1][27][8]	MAIN[1][27][10]	CELL[0].IMUX_BYP_DSP[4]	-	-	-	-
MAIN[1][26][19]	MAIN[1][27][14]	-	CELL[1].IMUX_BYP_DSP[4]	-	-	-
MAIN[4][26][9]	MAIN[4][26][5]	-	-	CELL[2].IMUX_BYP_DSP[4]	-	-
MAIN[3][27][40]	MAIN[3][27][42]	-	-	-	CELL[3].IMUX_BYP_DSP[4]	-
MAIN[3][26][39]	MAIN[3][26][41]	-	-	-	-	CELL[4].IMUX_BYP_DSP[4]
		Source
0	0	CELL[0].IMUX_BYP_SITE[4]	CELL[1].IMUX_BYP_SITE[4]	CELL[2].IMUX_BYP_SITE[4]	CELL[3].IMUX_BYP_SITE[4]	CELL[4].IMUX_BYP_SITE[4]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_BYP_DSP[5]
Bits		Destination
MAIN[0][27][6]	MAIN[0][26][7]	CELL[0].IMUX_BYP_DSP[5]	-	-	-	-
MAIN[0][26][24]	MAIN[0][26][26]	-	CELL[1].IMUX_BYP_DSP[5]	-	-	-
MAIN[0][26][49]	MAIN[0][26][52]	-	-	CELL[2].IMUX_BYP_DSP[5]	-	-
MAIN[1][26][34]	MAIN[1][27][35]	-	-	-	CELL[3].IMUX_BYP_DSP[5]	-
MAIN[1][26][53]	MAIN[1][27][55]	-	-	-	-	CELL[4].IMUX_BYP_DSP[5]
		Source
0	0	CELL[0].IMUX_BYP_SITE[5]	CELL[1].IMUX_BYP_SITE[5]	CELL[2].IMUX_BYP_SITE[5]	CELL[3].IMUX_BYP_SITE[5]	CELL[4].IMUX_BYP_SITE[5]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_BYP_DSP[6]
Bits		Destination
MAIN[2][26][12]	MAIN[2][27][9]	CELL[0].IMUX_BYP_DSP[6]	-	-	-	-
MAIN[2][27][14]	MAIN[2][26][16]	-	CELL[1].IMUX_BYP_DSP[6]	-	-	-
MAIN[1][26][7]	MAIN[1][26][9]	-	-	CELL[2].IMUX_BYP_DSP[6]	-	-
MAIN[1][26][41]	MAIN[1][26][37]	-	-	-	CELL[3].IMUX_BYP_DSP[6]	-
MAIN[3][26][51]	MAIN[3][27][46]	-	-	-	-	CELL[4].IMUX_BYP_DSP[6]
		Source
0	0	CELL[0].IMUX_BYP_SITE[6]	CELL[1].IMUX_BYP_SITE[6]	CELL[2].IMUX_BYP_SITE[6]	CELL[3].IMUX_BYP_SITE[6]	CELL[4].IMUX_BYP_SITE[6]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_BYP_DSP[7]
Bits		Destination
MAIN[0][27][4]	MAIN[0][26][1]	CELL[0].IMUX_BYP_DSP[7]	-	-	-	-
MAIN[0][27][22]	MAIN[0][26][21]	-	CELL[1].IMUX_BYP_DSP[7]	-	-	-
MAIN[0][27][47]	MAIN[0][26][44]	-	-	CELL[2].IMUX_BYP_DSP[7]	-	-
MAIN[1][26][33]	MAIN[1][27][30]	-	-	-	CELL[3].IMUX_BYP_DSP[7]	-
MAIN[1][27][51]	MAIN[1][27][48]	-	-	-	-	CELL[4].IMUX_BYP_DSP[7]
		Source
0	0	CELL[0].IMUX_BYP_SITE[7]	CELL[1].IMUX_BYP_SITE[7]	CELL[2].IMUX_BYP_SITE[7]	CELL[3].IMUX_BYP_SITE[7]	CELL[4].IMUX_BYP_SITE[7]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_FAN_DSP[0]
Bits		Destination
MAIN[2][26][19]	MAIN[2][26][14]	CELL[0].IMUX_FAN_DSP[0]	-	-	-	-
MAIN[1][26][13]	MAIN[1][26][26]	-	CELL[1].IMUX_FAN_DSP[0]	-	-	-
MAIN[4][26][54]	MAIN[4][27][51]	-	-	CELL[2].IMUX_FAN_DSP[0]	-	-
MAIN[3][26][45]	MAIN[3][26][58]	-	-	-	CELL[3].IMUX_FAN_DSP[0]	-
MAIN[4][26][51]	MAIN[4][26][46]	-	-	-	-	CELL[4].IMUX_FAN_DSP[0]
		Source
0	0	CELL[0].IMUX_FAN_SITE[0]	CELL[1].IMUX_FAN_SITE[0]	CELL[2].IMUX_FAN_SITE[0]	CELL[3].IMUX_FAN_SITE[0]	CELL[4].IMUX_FAN_SITE[0]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_FAN_DSP[1]
Bits		Destination
MAIN[4][26][44]	MAIN[4][27][41]	CELL[0].IMUX_FAN_DSP[1]	-	-	-
MAIN[4][27][46]	MAIN[4][26][48]	-	CELL[1].IMUX_FAN_DSP[1]	-	-
MAIN[0][27][60]	MAIN[0][26][63]	-	-	CELL[2].IMUX_FAN_DSP[1]	-
MAIN[0][26][29]	MAIN[0][27][24]	-	-	-	CELL[3].IMUX_FAN_DSP[1]
		Source
0	0	CELL[0].IMUX_FAN_SITE[1]	CELL[1].IMUX_FAN_SITE[1]	CELL[2].IMUX_FAN_SITE[1]	CELL[3].IMUX_FAN_SITE[1]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_FAN_DSP[2]
Bits		Destination
MAIN[1][27][4]	MAIN[1][27][15]	CELL[0].IMUX_FAN_DSP[2]	-	-	-
MAIN[2][26][61]	MAIN[2][27][56]	-	CELL[2].IMUX_FAN_DSP[2]	-	-
MAIN[3][27][36]	MAIN[3][27][47]	-	-	CELL[3].IMUX_FAN_DSP[2]	-
MAIN[3][26][5]	MAIN[3][27][10]	-	-	-	CELL[4].IMUX_FAN_DSP[2]
		Source
0	0	CELL[0].IMUX_FAN_SITE[2]	CELL[2].IMUX_FAN_SITE[2]	CELL[3].IMUX_FAN_SITE[2]	CELL[4].IMUX_FAN_SITE[2]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_FAN_DSP[3]
Bits		Destination
MAIN[2][27][36]	MAIN[2][26][33]	CELL[0].IMUX_FAN_DSP[3]	-	-	-	-
MAIN[2][27][54]	MAIN[2][26][53]	-	CELL[1].IMUX_FAN_DSP[3]	-	-	-
MAIN[3][27][15]	MAIN[3][26][12]	-	-	CELL[2].IMUX_FAN_DSP[3]	-	-
MAIN[4][26][1]	MAIN[3][27][62]	-	-	-	CELL[3].IMUX_FAN_DSP[3]	-
MAIN[4][27][19]	MAIN[4][27][16]	-	-	-	-	CELL[4].IMUX_FAN_DSP[3]
		Source
0	0	CELL[0].IMUX_FAN_SITE[3]	CELL[1].IMUX_FAN_SITE[3]	CELL[2].IMUX_FAN_SITE[3]	CELL[3].IMUX_FAN_SITE[3]	CELL[4].IMUX_FAN_SITE[3]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_FAN_DSP[4]
Bits		Destination
MAIN[2][27][46]	MAIN[2][27][47]	CELL[0].IMUX_FAN_DSP[4]	-	-	-	-
MAIN[3][27][7]	MAIN[3][27][9]	-	CELL[1].IMUX_FAN_DSP[4]	-	-	-
MAIN[3][27][25]	MAIN[3][26][30]	-	-	CELL[2].IMUX_FAN_DSP[4]	-	-
MAIN[4][27][11]	MAIN[4][27][13]	-	-	-	CELL[3].IMUX_FAN_DSP[4]	-
MAIN[4][27][35]	MAIN[4][26][39]	-	-	-	-	CELL[4].IMUX_FAN_DSP[4]
		Source
0	0	CELL[0].IMUX_FAN_SITE[4]	CELL[1].IMUX_FAN_SITE[4]	CELL[2].IMUX_FAN_SITE[4]	CELL[3].IMUX_FAN_SITE[4]	CELL[4].IMUX_FAN_SITE[4]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_FAN_DSP[5]
Bits		Destination
MAIN[2][27][45]	MAIN[2][27][43]	CELL[0].IMUX_FAN_DSP[5]	-	-	-	-
MAIN[3][27][5]	MAIN[3][27][2]	-	CELL[1].IMUX_FAN_DSP[5]	-	-	-
MAIN[3][26][24]	MAIN[3][26][21]	-	-	CELL[2].IMUX_FAN_DSP[5]	-	-
MAIN[4][26][8]	MAIN[4][27][7]	-	-	-	CELL[3].IMUX_FAN_DSP[5]	-
MAIN[4][26][33]	MAIN[4][26][29]	-	-	-	-	CELL[4].IMUX_FAN_DSP[5]
		Source
0	0	CELL[0].IMUX_FAN_SITE[5]	CELL[1].IMUX_FAN_SITE[5]	CELL[2].IMUX_FAN_SITE[5]	CELL[3].IMUX_FAN_SITE[5]	CELL[4].IMUX_FAN_SITE[5]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_FAN_DSP[6]
Bits		Destination
MAIN[2][27][38]	MAIN[2][26][39]	CELL[0].IMUX_FAN_DSP[6]	-	-	-	-
MAIN[2][26][56]	MAIN[2][26][58]	-	CELL[1].IMUX_FAN_DSP[6]	-	-	-
MAIN[3][26][17]	MAIN[3][26][20]	-	-	CELL[2].IMUX_FAN_DSP[6]	-	-
MAIN[4][26][2]	MAIN[4][27][3]	-	-	-	CELL[3].IMUX_FAN_DSP[6]	-
MAIN[4][26][21]	MAIN[4][27][23]	-	-	-	-	CELL[4].IMUX_FAN_DSP[6]
		Source
0	0	CELL[0].IMUX_FAN_SITE[6]	CELL[1].IMUX_FAN_SITE[6]	CELL[2].IMUX_FAN_SITE[6]	CELL[3].IMUX_FAN_SITE[6]	CELL[4].IMUX_FAN_SITE[6]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

virtex6 DSP switchbox SPEC_INT muxes IMUX_FAN_DSP[7]
Bits		Destination
MAIN[4][26][63]	MAIN[4][27][60]	CELL[0].IMUX_FAN_DSP[7]	-	-	-	-
MAIN[1][27][52]	MAIN[1][27][56]	-	CELL[1].IMUX_FAN_DSP[7]	-	-	-
MAIN[0][26][37]	MAIN[0][27][42]	-	-	CELL[2].IMUX_FAN_DSP[7]	-	-
MAIN[4][27][55]	MAIN[4][26][57]	-	-	-	CELL[3].IMUX_FAN_DSP[7]	-
MAIN[3][27][28]	MAIN[3][26][31]	-	-	-	-	CELL[4].IMUX_FAN_DSP[7]
		Source
0	0	CELL[0].IMUX_FAN_SITE[7]	CELL[1].IMUX_FAN_SITE[7]	CELL[2].IMUX_FAN_SITE[7]	CELL[3].IMUX_FAN_SITE[7]	CELL[4].IMUX_FAN_SITE[7]
0	1	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0	CELL[0].TIE_0
1	0	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1	CELL[0].TIE_1

Bels DSP_V6

virtex6 DSP bel DSP_V6 pins
Pin	Direction	DSP[0]	DSP[1]
CLK	in	CELL[1].IMUX_CLK[0] invert by !MAIN[1][26][18]	CELL[3].IMUX_CLK[0] invert by !MAIN[3][26][50]
A[0]	in	CELL[0].IMUX_IMUX[23]	CELL[0].IMUX_IMUX[15]
A[1]	in	CELL[0].IMUX_IMUX[19]	CELL[0].IMUX_IMUX[11]
A[2]	in	CELL[0].IMUX_IMUX[21]	CELL[0].IMUX_IMUX[13]
A[3]	in	CELL[0].IMUX_IMUX[17]	CELL[0].IMUX_IMUX[9]
A[4]	in	CELL[1].IMUX_IMUX[23]	CELL[1].IMUX_IMUX[15]
A[5]	in	CELL[1].IMUX_IMUX[19]	CELL[1].IMUX_IMUX[11]
A[6]	in	CELL[1].IMUX_IMUX[21]	CELL[1].IMUX_IMUX[13]
A[7]	in	CELL[1].IMUX_IMUX[17]	CELL[1].IMUX_IMUX[9]
A[8]	in	CELL[2].IMUX_IMUX[23]	CELL[2].IMUX_IMUX[15]
A[9]	in	CELL[2].IMUX_IMUX[19]	CELL[2].IMUX_IMUX[11]
A[10]	in	CELL[2].IMUX_IMUX[21]	CELL[2].IMUX_IMUX[13]
A[11]	in	CELL[2].IMUX_IMUX[17]	CELL[2].IMUX_IMUX[9]
A[12]	in	CELL[3].IMUX_IMUX[47]	CELL[3].IMUX_IMUX[45]
A[13]	in	CELL[3].IMUX_IMUX[7]	CELL[3].IMUX_IMUX[5]
A[14]	in	CELL[3].IMUX_IMUX[46]	CELL[3].IMUX_IMUX[44]
A[15]	in	CELL[3].IMUX_IMUX[6]	CELL[3].IMUX_IMUX[4]
A[16]	in	CELL[4].IMUX_IMUX[47]	CELL[4].IMUX_IMUX[45]
A[17]	in	CELL[4].IMUX_IMUX[7]	CELL[4].IMUX_IMUX[5]
A[18]	in	CELL[4].IMUX_IMUX[46]	CELL[4].IMUX_IMUX[44]
A[19]	in	CELL[4].IMUX_IMUX[6]	CELL[4].IMUX_IMUX[4]
A[20]	in	CELL[0].IMUX_IMUX[47]	CELL[0].IMUX_IMUX[45]
A[21]	in	CELL[0].IMUX_IMUX[7]	CELL[0].IMUX_IMUX[5]
A[22]	in	CELL[0].IMUX_IMUX[46]	CELL[0].IMUX_IMUX[44]
A[23]	in	CELL[0].IMUX_IMUX[6]	CELL[0].IMUX_IMUX[4]
A[24]	in	CELL[1].IMUX_IMUX[47]	CELL[1].IMUX_IMUX[45]
A[25]	in	CELL[1].IMUX_IMUX[7]	CELL[1].IMUX_IMUX[5]
A[26]	in	CELL[1].IMUX_IMUX[46]	CELL[1].IMUX_IMUX[44]
A[27]	in	CELL[1].IMUX_IMUX[6]	CELL[1].IMUX_IMUX[4]
A[28]	in	CELL[2].IMUX_IMUX[47]	CELL[2].IMUX_IMUX[45]
A[29]	in	CELL[2].IMUX_IMUX[7]	CELL[2].IMUX_IMUX[5]
RSTA	in	CELL[0].IMUX_CTRL[1]	CELL[2].IMUX_CTRL[1]
CEA1	in	CELL[1].IMUX_IMUX[40]	CELL[3].IMUX_IMUX[9]
CEA2	in	CELL[1].IMUX_IMUX[0]	CELL[3].IMUX_IMUX[17]
B[0]	in	CELL[0].IMUX_IMUX[22]	CELL[0].IMUX_IMUX[14]
B[1]	in	CELL[0].IMUX_IMUX[34]	CELL[0].IMUX_IMUX[26]
B[2]	in	CELL[0].IMUX_IMUX[36]	CELL[0].IMUX_IMUX[28]
B[3]	in	CELL[0].IMUX_IMUX[40]	CELL[0].IMUX_IMUX[0]
B[4]	in	CELL[1].IMUX_IMUX[38]	CELL[1].IMUX_IMUX[30]
B[5]	in	CELL[1].IMUX_IMUX[18]	CELL[1].IMUX_IMUX[10]
B[6]	in	CELL[1].IMUX_IMUX[36]	CELL[1].IMUX_IMUX[28]
B[7]	in	CELL[1].IMUX_IMUX[16]	CELL[1].IMUX_IMUX[8]
B[8]	in	CELL[2].IMUX_IMUX[22]	CELL[2].IMUX_IMUX[14]
B[9]	in	CELL[2].IMUX_IMUX[18]	CELL[2].IMUX_IMUX[42]
B[10]	in	CELL[2].IMUX_IMUX[36]	CELL[2].IMUX_IMUX[44]
B[11]	in	CELL[2].IMUX_IMUX[16]	CELL[2].IMUX_IMUX[8]
B[12]	in	CELL[3].IMUX_IMUX[43]	CELL[3].IMUX_IMUX[41]
B[13]	in	CELL[3].IMUX_IMUX[3]	CELL[3].IMUX_IMUX[1]
B[14]	in	CELL[3].IMUX_IMUX[42]	CELL[3].IMUX_IMUX[40]
B[15]	in	CELL[3].IMUX_IMUX[2]	CELL[3].IMUX_IMUX[0]
B[16]	in	CELL[4].IMUX_IMUX[43]	CELL[4].IMUX_IMUX[42]
B[17]	in	CELL[4].IMUX_IMUX[3]	CELL[4].IMUX_IMUX[2]
RSTB	in	CELL[2].IMUX_CTRL[0]	CELL[4].IMUX_CTRL[1]
CEB1	in	CELL[1].IMUX_IMUX[41]	CELL[3].IMUX_IMUX[8]
CEB2	in	CELL[1].IMUX_IMUX[1]	CELL[3].IMUX_IMUX[16]
C[0]	in	CELL[0].IMUX_IMUX[39]	CELL[0].IMUX_IMUX[31]
C[1]	in	CELL[0].IMUX_IMUX[3]	CELL[0].IMUX_IMUX[43]
C[2]	in	CELL[0].IMUX_IMUX[37]	CELL[0].IMUX_IMUX[29]
C[3]	in	CELL[0].IMUX_IMUX[1]	CELL[0].IMUX_IMUX[41]
C[4]	in	CELL[1].IMUX_IMUX[39]	CELL[1].IMUX_IMUX[31]
C[5]	in	CELL[1].IMUX_IMUX[35]	CELL[1].IMUX_IMUX[27]
C[6]	in	CELL[1].IMUX_IMUX[37]	CELL[1].IMUX_IMUX[29]
C[7]	in	CELL[1].IMUX_IMUX[33]	CELL[1].IMUX_IMUX[25]
C[8]	in	CELL[2].IMUX_IMUX[39]	CELL[2].IMUX_IMUX[31]
C[9]	in	CELL[2].IMUX_IMUX[3]	CELL[2].IMUX_IMUX[43]
C[10]	in	CELL[2].IMUX_IMUX[37]	CELL[2].IMUX_IMUX[29]
C[11]	in	CELL[2].IMUX_IMUX[33]	CELL[2].IMUX_IMUX[25]
C[12]	in	CELL[3].IMUX_IMUX[39]	CELL[3].IMUX_IMUX[31]
C[13]	in	CELL[3].IMUX_IMUX[35]	CELL[3].IMUX_IMUX[27]
C[14]	in	CELL[3].IMUX_IMUX[37]	CELL[3].IMUX_IMUX[29]
C[15]	in	CELL[3].IMUX_IMUX[33]	CELL[3].IMUX_IMUX[25]
C[16]	in	CELL[4].IMUX_IMUX[39]	CELL[4].IMUX_IMUX[31]
C[17]	in	CELL[4].IMUX_IMUX[35]	CELL[4].IMUX_IMUX[27]
C[18]	in	CELL[4].IMUX_IMUX[21]	CELL[4].IMUX_IMUX[13]
C[19]	in	CELL[4].IMUX_IMUX[1]	CELL[4].IMUX_IMUX[41]
C[20]	in	CELL[0].IMUX_IMUX[38]	CELL[0].IMUX_IMUX[30]
C[21]	in	CELL[0].IMUX_IMUX[18]	CELL[0].IMUX_IMUX[10]
C[22]	in	CELL[0].IMUX_IMUX[20]	CELL[0].IMUX_IMUX[12]
C[23]	in	CELL[0].IMUX_IMUX[32]	CELL[0].IMUX_IMUX[24]
C[24]	in	CELL[1].IMUX_IMUX[22]	CELL[1].IMUX_IMUX[14]
C[25]	in	CELL[1].IMUX_IMUX[34]	CELL[1].IMUX_IMUX[26]
C[26]	in	CELL[1].IMUX_IMUX[20]	CELL[1].IMUX_IMUX[12]
C[27]	in	CELL[1].IMUX_IMUX[32]	CELL[1].IMUX_IMUX[24]
C[28]	in	CELL[2].IMUX_IMUX[6]	CELL[2].IMUX_IMUX[46]
C[29]	in	CELL[2].IMUX_IMUX[2]	CELL[2].IMUX_IMUX[10]
C[30]	in	CELL[2].IMUX_IMUX[4]	CELL[2].IMUX_IMUX[28]
C[31]	in	CELL[2].IMUX_IMUX[32]	CELL[2].IMUX_IMUX[24]
C[32]	in	CELL[3].IMUX_IMUX[38]	CELL[3].IMUX_IMUX[22]
C[33]	in	CELL[3].IMUX_IMUX[18]	CELL[3].IMUX_IMUX[10]
C[34]	in	CELL[3].IMUX_IMUX[20]	CELL[3].IMUX_IMUX[12]
C[35]	in	CELL[3].IMUX_IMUX[32]	CELL[3].IMUX_IMUX[24]
C[36]	in	CELL[4].IMUX_IMUX[38]	CELL[4].IMUX_IMUX[30]
C[37]	in	CELL[4].IMUX_IMUX[32]	CELL[4].IMUX_IMUX[24]
C[38]	in	CELL[4].IMUX_IMUX[20]	CELL[4].IMUX_IMUX[12]
C[39]	in	CELL[4].IMUX_IMUX[18]	CELL[4].IMUX_IMUX[10]
C[40]	in	CELL[0].IMUX_IMUX[35]	CELL[0].IMUX_IMUX[27]
C[41]	in	CELL[0].IMUX_IMUX[16]	CELL[0].IMUX_IMUX[8]
C[42]	in	CELL[0].IMUX_IMUX[42]	CELL[0].IMUX_IMUX[2]
C[43]	in	CELL[0].IMUX_IMUX[33]	CELL[0].IMUX_IMUX[25]
C[44]	in	CELL[4].IMUX_IMUX[34]	CELL[4].IMUX_IMUX[26]
C[45]	in	CELL[4].IMUX_IMUX[37]	CELL[4].IMUX_IMUX[29]
C[46]	in	CELL[4].IMUX_IMUX[19]	CELL[4].IMUX_IMUX[11]
C[47]	in	CELL[4].IMUX_IMUX[33]	CELL[4].IMUX_IMUX[25]
RSTC	in	CELL[1].IMUX_CTRL[0]	CELL[3].IMUX_CTRL[0]
CEC	in	CELL[2].IMUX_IMUX[40]	CELL[3].IMUX_IMUX[34]
D[0]	in	CELL[0].IMUX_BYP_DSP[7]	CELL[0].IMUX_FAN_DSP[3]
D[1]	in	CELL[0].IMUX_BYP_DSP[5]	CELL[0].IMUX_FAN_DSP[6]
D[2]	in	CELL[0].IMUX_BYP_DSP[3]	CELL[0].IMUX_FAN_DSP[5]
D[3]	in	CELL[0].IMUX_BYP_DSP[1]	CELL[0].IMUX_FAN_DSP[4]
D[4]	in	CELL[1].IMUX_BYP_DSP[7]	CELL[1].IMUX_FAN_DSP[3]
D[5]	in	CELL[1].IMUX_BYP_DSP[5]	CELL[1].IMUX_FAN_DSP[6]
D[6]	in	CELL[1].IMUX_BYP_DSP[3]	CELL[1].IMUX_FAN_DSP[5]
D[7]	in	CELL[1].IMUX_BYP_DSP[1]	CELL[1].IMUX_FAN_DSP[4]
D[8]	in	CELL[2].IMUX_BYP_DSP[7]	CELL[2].IMUX_FAN_DSP[3]
D[9]	in	CELL[2].IMUX_BYP_DSP[5]	CELL[2].IMUX_FAN_DSP[6]
D[10]	in	CELL[2].IMUX_BYP_DSP[3]	CELL[2].IMUX_FAN_DSP[5]
D[11]	in	CELL[2].IMUX_BYP_DSP[1]	CELL[2].IMUX_FAN_DSP[4]
D[12]	in	CELL[3].IMUX_BYP_DSP[7]	CELL[3].IMUX_FAN_DSP[3]
D[13]	in	CELL[3].IMUX_BYP_DSP[5]	CELL[3].IMUX_FAN_DSP[6]
D[14]	in	CELL[3].IMUX_BYP_DSP[3]	CELL[3].IMUX_FAN_DSP[5]
D[15]	in	CELL[3].IMUX_BYP_DSP[1]	CELL[3].IMUX_FAN_DSP[4]
D[16]	in	CELL[4].IMUX_BYP_DSP[7]	CELL[4].IMUX_FAN_DSP[3]
D[17]	in	CELL[4].IMUX_BYP_DSP[5]	CELL[4].IMUX_FAN_DSP[6]
D[18]	in	CELL[4].IMUX_BYP_DSP[3]	CELL[4].IMUX_FAN_DSP[5]
D[19]	in	CELL[4].IMUX_BYP_DSP[1]	CELL[4].IMUX_FAN_DSP[4]
D[20]	in	CELL[0].IMUX_BYP_DSP[6]	CELL[0].IMUX_FAN_DSP[1]
D[21]	in	CELL[1].IMUX_BYP_DSP[6]	CELL[1].IMUX_FAN_DSP[1]
D[22]	in	CELL[2].IMUX_BYP_DSP[0]	CELL[2].IMUX_FAN_DSP[0]
D[23]	in	CELL[3].IMUX_BYP_DSP[2]	CELL[3].IMUX_FAN_DSP[7]
D[24]	in	CELL[0].IMUX_BYP_DSP[2]	CELL[0].IMUX_FAN_DSP[7]
RSTD	in	CELL[1].IMUX_BYP_DSP[4]	CELL[4].IMUX_BYP_DSP[6]
CED	in	CELL[1].IMUX_FAN_DSP[0]	CELL[3].IMUX_FAN_DSP[0]
INMODE[0]	in	CELL[3].IMUX_BYP_DSP[6] invert by !MAIN[1][27][42]	CELL[2].IMUX_BYP_DSP[4] invert by !MAIN[4][27][10]
INMODE[1]	in	CELL[1].IMUX_FAN_DSP[7] invert by !MAIN[1][27][50]	CELL[1].IMUX_BYP_DSP[2] invert by !MAIN[4][27][18]
INMODE[2]	in	CELL[2].IMUX_FAN_DSP[1] invert by !MAIN[1][27][2]	CELL[4].IMUX_FAN_DSP[7] invert by !MAIN[3][27][34]
INMODE[3]	in	CELL[2].IMUX_BYP_DSP[6] invert by !MAIN[1][27][11]	CELL[4].IMUX_BYP_DSP[4] invert by !MAIN[3][27][43]
INMODE[4]	in	CELL[3].IMUX_FAN_DSP[1] invert by !MAIN[0][27][26]	CELL[2].IMUX_FAN_DSP[2] invert by !MAIN[2][27][58]
RSTINMODE	in	CELL[1].IMUX_IMUX[42]	CELL[4].IMUX_IMUX[23]
CEINMODE	in	CELL[0].IMUX_FAN_DSP[2]	CELL[3].IMUX_FAN_DSP[2]
CEAD	in	CELL[1].IMUX_BYP_DSP[0]	CELL[3].IMUX_BYP_DSP[0]
RSTM	in	CELL[1].IMUX_CTRL[1]	CELL[3].IMUX_CTRL[1]
CEM	in	CELL[2].IMUX_IMUX[1]	CELL[3].IMUX_IMUX[19]
OPMODE[0]	in	CELL[2].IMUX_IMUX[35] invert by !MAIN[1][27][60]	CELL[3].IMUX_IMUX[28] invert by !MAIN[4][27][28]
OPMODE[1]	in	CELL[2].IMUX_IMUX[30] invert by !MAIN[1][27][58]	CELL[4].IMUX_IMUX[8] invert by !MAIN[4][27][26]
OPMODE[2]	in	CELL[2].IMUX_IMUX[27] invert by !MAIN[1][27][32]	CELL[3].IMUX_IMUX[36] invert by !MAIN[4][27][0]
OPMODE[3]	in	CELL[2].IMUX_IMUX[38] invert by !MAIN[1][26][35]	CELL[4].IMUX_IMUX[16] invert by !MAIN[4][26][3]
OPMODE[4]	in	CELL[2].IMUX_IMUX[20] invert by !MAIN[0][27][20]	CELL[4].IMUX_IMUX[17] invert by !MAIN[2][27][52]
OPMODE[5]	in	CELL[2].IMUX_IMUX[12] invert by !MAIN[0][26][35]	CELL[4].IMUX_IMUX[9] invert by !MAIN[3][26][3]
OPMODE[6]	in	CELL[2].IMUX_FAN_DSP[7] invert by !MAIN[0][27][40]	CELL[4].IMUX_FAN_DSP[2] invert by !MAIN[3][27][8]
CARRYINSEL[0]	in	CELL[3].IMUX_IMUX[30]	CELL[4].IMUX_IMUX[36]
CARRYINSEL[1]	in	CELL[3].IMUX_IMUX[14]	CELL[4].IMUX_IMUX[28]
CARRYINSEL[2]	in	CELL[2].IMUX_BYP_DSP[2]	CELL[4].IMUX_BYP_DSP[2]
RSTCTRL	in	CELL[1].IMUX_IMUX[43]	CELL[4].IMUX_IMUX[14]
CECTRL	in	CELL[2].IMUX_IMUX[41]	CELL[3].IMUX_IMUX[11]
CARRYIN	in	CELL[3].IMUX_IMUX[23] invert by !MAIN[0][26][4]	CELL[3].IMUX_IMUX[15] invert by !MAIN[2][26][36]
RSTALLCARRYIN	in	CELL[1].IMUX_IMUX[2]	CELL[4].IMUX_IMUX[15]
CECARRYIN	in	CELL[2].IMUX_IMUX[0]	CELL[3].IMUX_IMUX[26]
RSTALUMODE	in	CELL[1].IMUX_IMUX[3]	CELL[4].IMUX_IMUX[22]
CEALUMODE	in	CELL[0].IMUX_BYP_DSP[4]	CELL[3].IMUX_BYP_DSP[4]
ALUMODE[0]	in	CELL[3].IMUX_IMUX[21] invert by !MAIN[2][27][24]	CELL[4].IMUX_IMUX[0] invert by !MAIN[4][27][56]
ALUMODE[1]	in	CELL[3].IMUX_IMUX[13] invert by !MAIN[2][27][20]	CELL[4].IMUX_IMUX[40] invert by !MAIN[4][27][52]
ALUMODE[2]	in	CELL[0].IMUX_FAN_DSP[0] invert by !MAIN[2][27][16]	CELL[4].IMUX_FAN_DSP[0] invert by !MAIN[4][27][48]
ALUMODE[3]	in	CELL[0].IMUX_BYP_DSP[0] invert by !MAIN[2][26][0]	CELL[4].IMUX_BYP_DSP[0] invert by !MAIN[4][26][32]
RSTP	in	CELL[0].IMUX_CTRL[0]	CELL[4].IMUX_CTRL[0]
CEP	in	CELL[2].IMUX_IMUX[34]	CELL[2].IMUX_IMUX[26]
P[0]	out	CELL[0].OUT_BEL[21]	CELL[0].OUT_BEL[3]
P[1]	out	CELL[0].OUT_BEL[23]	CELL[0].OUT_BEL[1]
P[2]	out	CELL[0].OUT_BEL[16]	CELL[0].OUT_BEL[6]
P[3]	out	CELL[0].OUT_BEL[18]	CELL[0].OUT_BEL[4]
P[4]	out	CELL[1].OUT_BEL[21]	CELL[1].OUT_BEL[3]
P[5]	out	CELL[1].OUT_BEL[23]	CELL[1].OUT_BEL[1]
P[6]	out	CELL[1].OUT_BEL[16]	CELL[1].OUT_BEL[6]
P[7]	out	CELL[1].OUT_BEL[18]	CELL[1].OUT_BEL[4]
P[8]	out	CELL[2].OUT_BEL[21]	CELL[2].OUT_BEL[3]
P[9]	out	CELL[2].OUT_BEL[23]	CELL[2].OUT_BEL[1]
P[10]	out	CELL[2].OUT_BEL[16]	CELL[2].OUT_BEL[6]
P[11]	out	CELL[2].OUT_BEL[18]	CELL[2].OUT_BEL[4]
P[12]	out	CELL[3].OUT_BEL[21]	CELL[3].OUT_BEL[3]
P[13]	out	CELL[3].OUT_BEL[23]	CELL[3].OUT_BEL[1]
P[14]	out	CELL[3].OUT_BEL[16]	CELL[3].OUT_BEL[6]
P[15]	out	CELL[3].OUT_BEL[18]	CELL[3].OUT_BEL[4]
P[16]	out	CELL[4].OUT_BEL[21]	CELL[4].OUT_BEL[3]
P[17]	out	CELL[4].OUT_BEL[23]	CELL[4].OUT_BEL[1]
P[18]	out	CELL[4].OUT_BEL[16]	CELL[4].OUT_BEL[6]
P[19]	out	CELL[4].OUT_BEL[18]	CELL[4].OUT_BEL[4]
P[20]	out	CELL[0].OUT_BEL[17]	CELL[0].OUT_BEL[7]
P[21]	out	CELL[0].OUT_BEL[19]	CELL[0].OUT_BEL[5]
P[22]	out	CELL[0].OUT_BEL[20]	CELL[0].OUT_BEL[2]
P[23]	out	CELL[0].OUT_BEL[22]	CELL[0].OUT_BEL[0]
P[24]	out	CELL[1].OUT_BEL[17]	CELL[1].OUT_BEL[7]
P[25]	out	CELL[1].OUT_BEL[19]	CELL[1].OUT_BEL[5]
P[26]	out	CELL[1].OUT_BEL[20]	CELL[1].OUT_BEL[2]
P[27]	out	CELL[1].OUT_BEL[22]	CELL[1].OUT_BEL[0]
P[28]	out	CELL[2].OUT_BEL[17]	CELL[2].OUT_BEL[7]
P[29]	out	CELL[2].OUT_BEL[19]	CELL[2].OUT_BEL[5]
P[30]	out	CELL[2].OUT_BEL[20]	CELL[2].OUT_BEL[2]
P[31]	out	CELL[2].OUT_BEL[22]	CELL[2].OUT_BEL[0]
P[32]	out	CELL[3].OUT_BEL[17]	CELL[3].OUT_BEL[7]
P[33]	out	CELL[3].OUT_BEL[19]	CELL[3].OUT_BEL[5]
P[34]	out	CELL[3].OUT_BEL[20]	CELL[3].OUT_BEL[2]
P[35]	out	CELL[3].OUT_BEL[22]	CELL[3].OUT_BEL[0]
P[36]	out	CELL[4].OUT_BEL[17]	CELL[4].OUT_BEL[7]
P[37]	out	CELL[4].OUT_BEL[22]	CELL[4].OUT_BEL[0]
P[38]	out	CELL[4].OUT_BEL[20]	CELL[4].OUT_BEL[2]
P[39]	out	CELL[4].OUT_BEL[19]	CELL[4].OUT_BEL[5]
P[40]	out	CELL[0].OUT_BEL[13]	CELL[0].OUT_BEL[15]
P[41]	out	CELL[0].OUT_BEL[12]	CELL[0].OUT_BEL[11]
P[42]	out	CELL[0].OUT_BEL[9]	CELL[0].OUT_BEL[10]
P[43]	out	CELL[0].OUT_BEL[8]	CELL[0].OUT_BEL[14]
P[44]	out	CELL[4].OUT_BEL[9]	CELL[4].OUT_BEL[12]
P[45]	out	CELL[4].OUT_BEL[10]	CELL[4].OUT_BEL[11]
P[46]	out	CELL[4].OUT_BEL[13]	CELL[4].OUT_BEL[14]
P[47]	out	CELL[4].OUT_BEL[8]	CELL[4].OUT_BEL[15]
CARRYOUT[0]	out	CELL[1].OUT_BEL[12]	CELL[3].OUT_BEL[8]
CARRYOUT[1]	out	CELL[1].OUT_BEL[11]	CELL[3].OUT_BEL[11]
CARRYOUT[2]	out	CELL[1].OUT_BEL[13]	CELL[3].OUT_BEL[10]
CARRYOUT[3]	out	CELL[1].OUT_BEL[10]	CELL[3].OUT_BEL[15]
PATTERNDETECT	out	CELL[2].OUT_BEL[11]	CELL[2].OUT_BEL[13]
PATTERNBDETECT	out	CELL[2].OUT_BEL[14]	CELL[2].OUT_BEL[15]
OVERFLOW	out	CELL[2].OUT_BEL[10]	CELL[2].OUT_BEL[8]
UNDERFLOW	out	CELL[2].OUT_BEL[9]	CELL[3].OUT_BEL[14]

virtex6 DSP bel DSP_V6 attribute bits
Attribute	DSP[0]	DSP[1]
AREG	[enum: DSP_REG2_CASC]	[enum: DSP_REG2_CASC]
A_INPUT	[enum: DSP_AB_INPUT]	[enum: DSP_AB_INPUT]
BREG	[enum: DSP_REG2_CASC]	[enum: DSP_REG2_CASC]
B_INPUT	[enum: DSP_AB_INPUT]	[enum: DSP_AB_INPUT]
CREG	!MAIN[1][26][15]	!MAIN[3][26][47]
DREG	!MAIN[1][26][23]	!MAIN[3][26][55]
USE_DPORT	MAIN[1][27][21]	MAIN[3][27][53]
INMODEREG	!MAIN[1][26][2]	!MAIN[3][26][34]
ADREG	!MAIN[1][26][25]	!MAIN[3][26][57]
MREG	!MAIN[1][26][21]	!MAIN[3][26][53]
USE_MULT	!MAIN[2][27][30]	!MAIN[4][27][62]
OPMODEREG	!MAIN[1][26][45]	!MAIN[4][26][13]
CARRYINSELREG	!MAIN[0][26][17]	!MAIN[2][26][49]
CARRYINREG	!MAIN[0][26][13]	!MAIN[2][26][45]
ALUMODEREG	!MAIN[2][26][11]	!MAIN[4][26][43]
USE_SIMD	[enum: DSP_USE_SIMD]	[enum: DSP_USE_SIMD]
PREG	!MAIN[1][27][16]	!MAIN[3][27][48]
PATTERN bit 0	MAIN[0][26][0]	MAIN[2][26][32]
PATTERN bit 1	MAIN[0][26][3]	MAIN[2][26][35]
PATTERN bit 2	MAIN[0][27][5]	MAIN[2][27][37]
PATTERN bit 3	MAIN[0][27][7]	MAIN[2][27][39]
PATTERN bit 4	MAIN[0][27][9]	MAIN[2][27][41]
PATTERN bit 5	MAIN[0][26][12]	MAIN[2][26][44]
PATTERN bit 6	MAIN[0][27][17]	MAIN[2][27][49]
PATTERN bit 7	MAIN[0][26][20]	MAIN[2][26][52]
PATTERN bit 8	MAIN[0][26][23]	MAIN[2][26][55]
PATTERN bit 9	MAIN[0][26][25]	MAIN[2][26][57]
PATTERN bit 10	MAIN[0][27][27]	MAIN[2][27][59]
PATTERN bit 11	MAIN[0][26][30]	MAIN[2][26][62]
PATTERN bit 12	MAIN[0][27][33]	MAIN[3][27][1]
PATTERN bit 13	MAIN[0][26][36]	MAIN[3][26][4]
PATTERN bit 14	MAIN[0][27][38]	MAIN[3][27][6]
PATTERN bit 15	MAIN[0][26][40]	MAIN[3][26][8]
PATTERN bit 16	MAIN[0][26][43]	MAIN[3][26][11]
PATTERN bit 17	MAIN[0][27][45]	MAIN[3][27][13]
PATTERN bit 18	MAIN[0][26][51]	MAIN[3][26][19]
PATTERN bit 19	MAIN[0][27][53]	MAIN[3][27][21]
PATTERN bit 20	MAIN[0][27][55]	MAIN[3][27][23]
PATTERN bit 21	MAIN[0][27][58]	MAIN[3][27][26]
PATTERN bit 22	MAIN[0][26][61]	MAIN[3][26][29]
PATTERN bit 23	MAIN[0][27][63]	MAIN[3][27][31]
PATTERN bit 24	MAIN[1][27][23]	MAIN[3][27][55]
PATTERN bit 25	MAIN[1][27][25]	MAIN[3][27][57]
PATTERN bit 26	MAIN[1][27][28]	MAIN[3][27][60]
PATTERN bit 27	MAIN[1][26][31]	MAIN[3][26][63]
PATTERN bit 28	MAIN[1][27][33]	MAIN[4][27][1]
PATTERN bit 29	MAIN[1][26][36]	MAIN[4][26][4]
PATTERN bit 30	MAIN[1][27][40]	MAIN[4][27][8]
PATTERN bit 31	MAIN[1][26][43]	MAIN[4][26][11]
PATTERN bit 32	MAIN[1][26][46]	MAIN[4][26][14]
PATTERN bit 33	MAIN[1][26][48]	MAIN[4][26][16]
PATTERN bit 34	MAIN[1][26][51]	MAIN[4][26][19]
PATTERN bit 35	MAIN[1][27][53]	MAIN[4][27][21]
PATTERN bit 36	MAIN[1][26][56]	MAIN[4][26][24]
PATTERN bit 37	MAIN[1][26][59]	MAIN[4][26][27]
PATTERN bit 38	MAIN[1][27][61]	MAIN[4][27][29]
PATTERN bit 39	MAIN[1][27][63]	MAIN[4][27][31]
PATTERN bit 40	MAIN[2][26][2]	MAIN[4][26][34]
PATTERN bit 41	MAIN[2][26][5]	MAIN[4][26][37]
PATTERN bit 42	MAIN[2][26][10]	MAIN[4][26][42]
PATTERN bit 43	MAIN[2][27][12]	MAIN[4][27][44]
PATTERN bit 44	MAIN[2][26][15]	MAIN[4][26][47]
PATTERN bit 45	MAIN[2][27][17]	MAIN[4][27][49]
PATTERN bit 46	MAIN[2][26][20]	MAIN[4][26][52]
PATTERN bit 47	MAIN[2][27][22]	MAIN[4][27][54]
SEL_PATTERN	[enum: DSP_SEL_PATTERN]	[enum: DSP_SEL_PATTERN]
MASK bit 0	MAIN[0][27][0]	MAIN[2][27][32]
MASK bit 1	MAIN[0][27][3]	MAIN[2][27][35]
MASK bit 2	MAIN[0][26][6]	MAIN[2][26][38]
MASK bit 3	MAIN[0][27][8]	MAIN[2][27][40]
MASK bit 4	MAIN[0][27][10]	MAIN[2][27][42]
MASK bit 5	MAIN[0][26][14]	MAIN[2][26][46]
MASK bit 6	MAIN[0][27][18]	MAIN[2][27][50]
MASK bit 7	MAIN[0][27][21]	MAIN[2][27][53]
MASK bit 8	MAIN[0][27][23]	MAIN[2][27][55]
MASK bit 9	MAIN[0][27][25]	MAIN[2][27][57]
MASK bit 10	MAIN[0][26][28]	MAIN[2][26][60]
MASK bit 11	MAIN[0][26][31]	MAIN[2][26][63]
MASK bit 12	MAIN[0][26][34]	MAIN[3][26][2]
MASK bit 13	MAIN[0][27][36]	MAIN[3][27][4]
MASK bit 14	MAIN[0][26][39]	MAIN[3][26][7]
MASK bit 15	MAIN[0][26][41]	MAIN[3][26][9]
MASK bit 16	MAIN[0][27][43]	MAIN[3][27][11]
MASK bit 17	MAIN[0][27][46]	MAIN[3][27][14]
MASK bit 18	MAIN[0][27][51]	MAIN[3][27][19]
MASK bit 19	MAIN[0][26][54]	MAIN[3][26][22]
MASK bit 20	MAIN[0][27][56]	MAIN[3][27][24]
MASK bit 21	MAIN[0][26][59]	MAIN[3][26][27]
MASK bit 22	MAIN[0][27][61]	MAIN[3][27][29]
MASK bit 23	MAIN[1][26][0]	MAIN[3][26][32]
MASK bit 24	MAIN[1][26][24]	MAIN[3][26][56]
MASK bit 25	MAIN[1][27][26]	MAIN[3][27][58]
MASK bit 26	MAIN[1][26][29]	MAIN[3][26][61]
MASK bit 27	MAIN[1][27][31]	MAIN[3][27][63]
MASK bit 28	MAIN[1][27][34]	MAIN[4][27][2]
MASK bit 29	MAIN[1][27][36]	MAIN[4][27][4]
MASK bit 30	MAIN[1][27][41]	MAIN[4][27][9]
MASK bit 31	MAIN[1][26][44]	MAIN[4][26][12]
MASK bit 32	MAIN[1][27][46]	MAIN[4][27][14]
MASK bit 33	MAIN[1][26][49]	MAIN[4][26][17]
MASK bit 34	MAIN[1][26][52]	MAIN[4][26][20]
MASK bit 35	MAIN[1][26][54]	MAIN[4][26][22]
MASK bit 36	MAIN[1][26][57]	MAIN[4][26][25]
MASK bit 37	MAIN[1][27][59]	MAIN[4][27][27]
MASK bit 38	MAIN[1][27][62]	MAIN[4][27][30]
MASK bit 39	MAIN[2][27][0]	MAIN[4][27][32]
MASK bit 40	MAIN[2][26][3]	MAIN[4][26][35]
MASK bit 41	MAIN[2][26][6]	MAIN[4][26][38]
MASK bit 42	MAIN[2][27][10]	MAIN[4][27][42]
MASK bit 43	MAIN[2][27][13]	MAIN[4][27][45]
MASK bit 44	MAIN[2][27][15]	MAIN[4][27][47]
MASK bit 45	MAIN[2][26][18]	MAIN[4][26][50]
MASK bit 46	MAIN[2][26][21]	MAIN[4][26][53]
MASK bit 47	MAIN[2][26][23]	MAIN[4][26][55]
SEL_MASK	[enum: DSP_SEL_MASK]	[enum: DSP_SEL_MASK]
SEL_ROUNDING_MASK	[enum: DSP_SEL_ROUNDING_MASK]	[enum: DSP_SEL_ROUNDING_MASK]
AUTORESET_PATTERN_DETECT	MAIN[1][26][8]	MAIN[3][26][40]
AUTORESET_PATTERN_DETECT_OPTINV	MAIN[1][27][9]	MAIN[3][27][41]

virtex6 DSP enum DSP_REG2_CASC
DSP[0].AREG	MAIN[1][27][18]	MAIN[2][27][4]	MAIN[1][27][49]	MAIN[1][26][47]	MAIN[1][26][17]
DSP[1].AREG	MAIN[3][27][50]	MAIN[4][27][36]	MAIN[4][27][17]	MAIN[4][26][15]	MAIN[3][26][49]
DSP[0].BREG	MAIN[0][27][52]	MAIN[0][27][30]	MAIN[0][26][10]	MAIN[0][27][32]	MAIN[0][27][50]
DSP[1].BREG	MAIN[3][27][20]	MAIN[2][27][62]	MAIN[2][26][42]	MAIN[3][27][0]	MAIN[3][27][18]
NONE	0	0	0	0	0
_0	0	1	1	1	1
_1	0	0	0	0	1
_2	1	0	0	0	1
DIRECT_2_CASC_1	1	0	0	0	0
_1_INMODE_GND	0	0	0	1	1

virtex6 DSP enum DSP_AB_INPUT
DSP[0].A_INPUT	MAIN[2][27][8]
DSP[1].A_INPUT	MAIN[4][27][40]
DSP[0].B_INPUT	MAIN[0][26][9]
DSP[1].B_INPUT	MAIN[2][26][41]
DIRECT	0
CASCADE	1

virtex6 DSP enum DSP_USE_SIMD
DSP[0].USE_SIMD	MAIN[2][26][13]	MAIN[0][27][44]	MAIN[1][27][24]
DSP[1].USE_SIMD	MAIN[4][26][45]	MAIN[3][27][12]	MAIN[3][27][56]
ONE48	0	0	0
TWO24	0	0	1
FOUR12	1	1	1

virtex6 DSP enum DSP_SEL_PATTERN
DSP[0].SEL_PATTERN	MAIN[1][26][3]
DSP[1].SEL_PATTERN	MAIN[3][26][35]
PATTERN	0
C	1

virtex6 DSP enum DSP_SEL_MASK
DSP[0].SEL_MASK	MAIN[1][26][5]
DSP[1].SEL_MASK	MAIN[3][26][37]
MASK	0
C	1

virtex6 DSP enum DSP_SEL_ROUNDING_MASK
DSP[0].SEL_ROUNDING_MASK	MAIN[1][26][4]	MAIN[1][27][3]
DSP[1].SEL_ROUNDING_MASK	MAIN[3][26][36]	MAIN[3][27][35]
SEL_MASK	0	0
MODE1	0	1
MODE2	1	1

Bel wires

virtex6 DSP bel wires
Wire	Pins
CELL[0].IMUX_CTRL[0]	DSP[0].RSTP
CELL[0].IMUX_CTRL[1]	DSP[0].RSTA
CELL[0].IMUX_BYP_DSP[0]	DSP[0].ALUMODE[3]
CELL[0].IMUX_BYP_DSP[1]	DSP[0].D[3]
CELL[0].IMUX_BYP_DSP[2]	DSP[0].D[24]
CELL[0].IMUX_BYP_DSP[3]	DSP[0].D[2]
CELL[0].IMUX_BYP_DSP[4]	DSP[0].CEALUMODE
CELL[0].IMUX_BYP_DSP[5]	DSP[0].D[1]
CELL[0].IMUX_BYP_DSP[6]	DSP[0].D[20]
CELL[0].IMUX_BYP_DSP[7]	DSP[0].D[0]
CELL[0].IMUX_FAN_DSP[0]	DSP[0].ALUMODE[2]
CELL[0].IMUX_FAN_DSP[1]	DSP[1].D[20]
CELL[0].IMUX_FAN_DSP[2]	DSP[0].CEINMODE
CELL[0].IMUX_FAN_DSP[3]	DSP[1].D[0]
CELL[0].IMUX_FAN_DSP[4]	DSP[1].D[3]
CELL[0].IMUX_FAN_DSP[5]	DSP[1].D[2]
CELL[0].IMUX_FAN_DSP[6]	DSP[1].D[1]
CELL[0].IMUX_FAN_DSP[7]	DSP[1].D[24]
CELL[0].IMUX_IMUX[0]	DSP[1].B[3]
CELL[0].IMUX_IMUX[1]	DSP[0].C[3]
CELL[0].IMUX_IMUX[2]	DSP[1].C[42]
CELL[0].IMUX_IMUX[3]	DSP[0].C[1]
CELL[0].IMUX_IMUX[4]	DSP[1].A[23]
CELL[0].IMUX_IMUX[5]	DSP[1].A[21]
CELL[0].IMUX_IMUX[6]	DSP[0].A[23]
CELL[0].IMUX_IMUX[7]	DSP[0].A[21]
CELL[0].IMUX_IMUX[8]	DSP[1].C[41]
CELL[0].IMUX_IMUX[9]	DSP[1].A[3]
CELL[0].IMUX_IMUX[10]	DSP[1].C[21]
CELL[0].IMUX_IMUX[11]	DSP[1].A[1]
CELL[0].IMUX_IMUX[12]	DSP[1].C[22]
CELL[0].IMUX_IMUX[13]	DSP[1].A[2]
CELL[0].IMUX_IMUX[14]	DSP[1].B[0]
CELL[0].IMUX_IMUX[15]	DSP[1].A[0]
CELL[0].IMUX_IMUX[16]	DSP[0].C[41]
CELL[0].IMUX_IMUX[17]	DSP[0].A[3]
CELL[0].IMUX_IMUX[18]	DSP[0].C[21]
CELL[0].IMUX_IMUX[19]	DSP[0].A[1]
CELL[0].IMUX_IMUX[20]	DSP[0].C[22]
CELL[0].IMUX_IMUX[21]	DSP[0].A[2]
CELL[0].IMUX_IMUX[22]	DSP[0].B[0]
CELL[0].IMUX_IMUX[23]	DSP[0].A[0]
CELL[0].IMUX_IMUX[24]	DSP[1].C[23]
CELL[0].IMUX_IMUX[25]	DSP[1].C[43]
CELL[0].IMUX_IMUX[26]	DSP[1].B[1]
CELL[0].IMUX_IMUX[27]	DSP[1].C[40]
CELL[0].IMUX_IMUX[28]	DSP[1].B[2]
CELL[0].IMUX_IMUX[29]	DSP[1].C[2]
CELL[0].IMUX_IMUX[30]	DSP[1].C[20]
CELL[0].IMUX_IMUX[31]	DSP[1].C[0]
CELL[0].IMUX_IMUX[32]	DSP[0].C[23]
CELL[0].IMUX_IMUX[33]	DSP[0].C[43]
CELL[0].IMUX_IMUX[34]	DSP[0].B[1]
CELL[0].IMUX_IMUX[35]	DSP[0].C[40]
CELL[0].IMUX_IMUX[36]	DSP[0].B[2]
CELL[0].IMUX_IMUX[37]	DSP[0].C[2]
CELL[0].IMUX_IMUX[38]	DSP[0].C[20]
CELL[0].IMUX_IMUX[39]	DSP[0].C[0]
CELL[0].IMUX_IMUX[40]	DSP[0].B[3]
CELL[0].IMUX_IMUX[41]	DSP[1].C[3]
CELL[0].IMUX_IMUX[42]	DSP[0].C[42]
CELL[0].IMUX_IMUX[43]	DSP[1].C[1]
CELL[0].IMUX_IMUX[44]	DSP[1].A[22]
CELL[0].IMUX_IMUX[45]	DSP[1].A[20]
CELL[0].IMUX_IMUX[46]	DSP[0].A[22]
CELL[0].IMUX_IMUX[47]	DSP[0].A[20]
CELL[0].OUT_BEL[0]	DSP[1].P[23]
CELL[0].OUT_BEL[1]	DSP[1].P[1]
CELL[0].OUT_BEL[2]	DSP[1].P[22]
CELL[0].OUT_BEL[3]	DSP[1].P[0]
CELL[0].OUT_BEL[4]	DSP[1].P[3]
CELL[0].OUT_BEL[5]	DSP[1].P[21]
CELL[0].OUT_BEL[6]	DSP[1].P[2]
CELL[0].OUT_BEL[7]	DSP[1].P[20]
CELL[0].OUT_BEL[8]	DSP[0].P[43]
CELL[0].OUT_BEL[9]	DSP[0].P[42]
CELL[0].OUT_BEL[10]	DSP[1].P[42]
CELL[0].OUT_BEL[11]	DSP[1].P[41]
CELL[0].OUT_BEL[12]	DSP[0].P[41]
CELL[0].OUT_BEL[13]	DSP[0].P[40]
CELL[0].OUT_BEL[14]	DSP[1].P[43]
CELL[0].OUT_BEL[15]	DSP[1].P[40]
CELL[0].OUT_BEL[16]	DSP[0].P[2]
CELL[0].OUT_BEL[17]	DSP[0].P[20]
CELL[0].OUT_BEL[18]	DSP[0].P[3]
CELL[0].OUT_BEL[19]	DSP[0].P[21]
CELL[0].OUT_BEL[20]	DSP[0].P[22]
CELL[0].OUT_BEL[21]	DSP[0].P[0]
CELL[0].OUT_BEL[22]	DSP[0].P[23]
CELL[0].OUT_BEL[23]	DSP[0].P[1]
CELL[1].IMUX_CLK[0]	DSP[0].CLK
CELL[1].IMUX_CTRL[0]	DSP[0].RSTC
CELL[1].IMUX_CTRL[1]	DSP[0].RSTM
CELL[1].IMUX_BYP_DSP[0]	DSP[0].CEAD
CELL[1].IMUX_BYP_DSP[1]	DSP[0].D[7]
CELL[1].IMUX_BYP_DSP[2]	DSP[1].INMODE[1]
CELL[1].IMUX_BYP_DSP[3]	DSP[0].D[6]
CELL[1].IMUX_BYP_DSP[4]	DSP[0].RSTD
CELL[1].IMUX_BYP_DSP[5]	DSP[0].D[5]
CELL[1].IMUX_BYP_DSP[6]	DSP[0].D[21]
CELL[1].IMUX_BYP_DSP[7]	DSP[0].D[4]
CELL[1].IMUX_FAN_DSP[0]	DSP[0].CED
CELL[1].IMUX_FAN_DSP[1]	DSP[1].D[21]
CELL[1].IMUX_FAN_DSP[3]	DSP[1].D[4]
CELL[1].IMUX_FAN_DSP[4]	DSP[1].D[7]
CELL[1].IMUX_FAN_DSP[5]	DSP[1].D[6]
CELL[1].IMUX_FAN_DSP[6]	DSP[1].D[5]
CELL[1].IMUX_FAN_DSP[7]	DSP[0].INMODE[1]
CELL[1].IMUX_IMUX[0]	DSP[0].CEA2
CELL[1].IMUX_IMUX[1]	DSP[0].CEB2
CELL[1].IMUX_IMUX[2]	DSP[0].RSTALLCARRYIN
CELL[1].IMUX_IMUX[3]	DSP[0].RSTALUMODE
CELL[1].IMUX_IMUX[4]	DSP[1].A[27]
CELL[1].IMUX_IMUX[5]	DSP[1].A[25]
CELL[1].IMUX_IMUX[6]	DSP[0].A[27]
CELL[1].IMUX_IMUX[7]	DSP[0].A[25]
CELL[1].IMUX_IMUX[8]	DSP[1].B[7]
CELL[1].IMUX_IMUX[9]	DSP[1].A[7]
CELL[1].IMUX_IMUX[10]	DSP[1].B[5]
CELL[1].IMUX_IMUX[11]	DSP[1].A[5]
CELL[1].IMUX_IMUX[12]	DSP[1].C[26]
CELL[1].IMUX_IMUX[13]	DSP[1].A[6]
CELL[1].IMUX_IMUX[14]	DSP[1].C[24]
CELL[1].IMUX_IMUX[15]	DSP[1].A[4]
CELL[1].IMUX_IMUX[16]	DSP[0].B[7]
CELL[1].IMUX_IMUX[17]	DSP[0].A[7]
CELL[1].IMUX_IMUX[18]	DSP[0].B[5]
CELL[1].IMUX_IMUX[19]	DSP[0].A[5]
CELL[1].IMUX_IMUX[20]	DSP[0].C[26]
CELL[1].IMUX_IMUX[21]	DSP[0].A[6]
CELL[1].IMUX_IMUX[22]	DSP[0].C[24]
CELL[1].IMUX_IMUX[23]	DSP[0].A[4]
CELL[1].IMUX_IMUX[24]	DSP[1].C[27]
CELL[1].IMUX_IMUX[25]	DSP[1].C[7]
CELL[1].IMUX_IMUX[26]	DSP[1].C[25]
CELL[1].IMUX_IMUX[27]	DSP[1].C[5]
CELL[1].IMUX_IMUX[28]	DSP[1].B[6]
CELL[1].IMUX_IMUX[29]	DSP[1].C[6]
CELL[1].IMUX_IMUX[30]	DSP[1].B[4]
CELL[1].IMUX_IMUX[31]	DSP[1].C[4]
CELL[1].IMUX_IMUX[32]	DSP[0].C[27]
CELL[1].IMUX_IMUX[33]	DSP[0].C[7]
CELL[1].IMUX_IMUX[34]	DSP[0].C[25]
CELL[1].IMUX_IMUX[35]	DSP[0].C[5]
CELL[1].IMUX_IMUX[36]	DSP[0].B[6]
CELL[1].IMUX_IMUX[37]	DSP[0].C[6]
CELL[1].IMUX_IMUX[38]	DSP[0].B[4]
CELL[1].IMUX_IMUX[39]	DSP[0].C[4]
CELL[1].IMUX_IMUX[40]	DSP[0].CEA1
CELL[1].IMUX_IMUX[41]	DSP[0].CEB1
CELL[1].IMUX_IMUX[42]	DSP[0].RSTINMODE
CELL[1].IMUX_IMUX[43]	DSP[0].RSTCTRL
CELL[1].IMUX_IMUX[44]	DSP[1].A[26]
CELL[1].IMUX_IMUX[45]	DSP[1].A[24]
CELL[1].IMUX_IMUX[46]	DSP[0].A[26]
CELL[1].IMUX_IMUX[47]	DSP[0].A[24]
CELL[1].OUT_BEL[0]	DSP[1].P[27]
CELL[1].OUT_BEL[1]	DSP[1].P[5]
CELL[1].OUT_BEL[2]	DSP[1].P[26]
CELL[1].OUT_BEL[3]	DSP[1].P[4]
CELL[1].OUT_BEL[4]	DSP[1].P[7]
CELL[1].OUT_BEL[5]	DSP[1].P[25]
CELL[1].OUT_BEL[6]	DSP[1].P[6]
CELL[1].OUT_BEL[7]	DSP[1].P[24]
CELL[1].OUT_BEL[10]	DSP[0].CARRYOUT[3]
CELL[1].OUT_BEL[11]	DSP[0].CARRYOUT[1]
CELL[1].OUT_BEL[12]	DSP[0].CARRYOUT[0]
CELL[1].OUT_BEL[13]	DSP[0].CARRYOUT[2]
CELL[1].OUT_BEL[16]	DSP[0].P[6]
CELL[1].OUT_BEL[17]	DSP[0].P[24]
CELL[1].OUT_BEL[18]	DSP[0].P[7]
CELL[1].OUT_BEL[19]	DSP[0].P[25]
CELL[1].OUT_BEL[20]	DSP[0].P[26]
CELL[1].OUT_BEL[21]	DSP[0].P[4]
CELL[1].OUT_BEL[22]	DSP[0].P[27]
CELL[1].OUT_BEL[23]	DSP[0].P[5]
CELL[2].IMUX_CTRL[0]	DSP[0].RSTB
CELL[2].IMUX_CTRL[1]	DSP[1].RSTA
CELL[2].IMUX_BYP_DSP[0]	DSP[0].D[22]
CELL[2].IMUX_BYP_DSP[1]	DSP[0].D[11]
CELL[2].IMUX_BYP_DSP[2]	DSP[0].CARRYINSEL[2]
CELL[2].IMUX_BYP_DSP[3]	DSP[0].D[10]
CELL[2].IMUX_BYP_DSP[4]	DSP[1].INMODE[0]
CELL[2].IMUX_BYP_DSP[5]	DSP[0].D[9]
CELL[2].IMUX_BYP_DSP[6]	DSP[0].INMODE[3]
CELL[2].IMUX_BYP_DSP[7]	DSP[0].D[8]
CELL[2].IMUX_FAN_DSP[0]	DSP[1].D[22]
CELL[2].IMUX_FAN_DSP[1]	DSP[0].INMODE[2]
CELL[2].IMUX_FAN_DSP[2]	DSP[1].INMODE[4]
CELL[2].IMUX_FAN_DSP[3]	DSP[1].D[8]
CELL[2].IMUX_FAN_DSP[4]	DSP[1].D[11]
CELL[2].IMUX_FAN_DSP[5]	DSP[1].D[10]
CELL[2].IMUX_FAN_DSP[6]	DSP[1].D[9]
CELL[2].IMUX_FAN_DSP[7]	DSP[0].OPMODE[6]
CELL[2].IMUX_IMUX[0]	DSP[0].CECARRYIN
CELL[2].IMUX_IMUX[1]	DSP[0].CEM
CELL[2].IMUX_IMUX[2]	DSP[0].C[29]
CELL[2].IMUX_IMUX[3]	DSP[0].C[9]
CELL[2].IMUX_IMUX[4]	DSP[0].C[30]
CELL[2].IMUX_IMUX[5]	DSP[1].A[29]
CELL[2].IMUX_IMUX[6]	DSP[0].C[28]
CELL[2].IMUX_IMUX[7]	DSP[0].A[29]
CELL[2].IMUX_IMUX[8]	DSP[1].B[11]
CELL[2].IMUX_IMUX[9]	DSP[1].A[11]
CELL[2].IMUX_IMUX[10]	DSP[1].C[29]
CELL[2].IMUX_IMUX[11]	DSP[1].A[9]
CELL[2].IMUX_IMUX[12]	DSP[0].OPMODE[5]
CELL[2].IMUX_IMUX[13]	DSP[1].A[10]
CELL[2].IMUX_IMUX[14]	DSP[1].B[8]
CELL[2].IMUX_IMUX[15]	DSP[1].A[8]
CELL[2].IMUX_IMUX[16]	DSP[0].B[11]
CELL[2].IMUX_IMUX[17]	DSP[0].A[11]
CELL[2].IMUX_IMUX[18]	DSP[0].B[9]
CELL[2].IMUX_IMUX[19]	DSP[0].A[9]
CELL[2].IMUX_IMUX[20]	DSP[0].OPMODE[4]
CELL[2].IMUX_IMUX[21]	DSP[0].A[10]
CELL[2].IMUX_IMUX[22]	DSP[0].B[8]
CELL[2].IMUX_IMUX[23]	DSP[0].A[8]
CELL[2].IMUX_IMUX[24]	DSP[1].C[31]
CELL[2].IMUX_IMUX[25]	DSP[1].C[11]
CELL[2].IMUX_IMUX[26]	DSP[1].CEP
CELL[2].IMUX_IMUX[27]	DSP[0].OPMODE[2]
CELL[2].IMUX_IMUX[28]	DSP[1].C[30]
CELL[2].IMUX_IMUX[29]	DSP[1].C[10]
CELL[2].IMUX_IMUX[30]	DSP[0].OPMODE[1]
CELL[2].IMUX_IMUX[31]	DSP[1].C[8]
CELL[2].IMUX_IMUX[32]	DSP[0].C[31]
CELL[2].IMUX_IMUX[33]	DSP[0].C[11]
CELL[2].IMUX_IMUX[34]	DSP[0].CEP
CELL[2].IMUX_IMUX[35]	DSP[0].OPMODE[0]
CELL[2].IMUX_IMUX[36]	DSP[0].B[10]
CELL[2].IMUX_IMUX[37]	DSP[0].C[10]
CELL[2].IMUX_IMUX[38]	DSP[0].OPMODE[3]
CELL[2].IMUX_IMUX[39]	DSP[0].C[8]
CELL[2].IMUX_IMUX[40]	DSP[0].CEC
CELL[2].IMUX_IMUX[41]	DSP[0].CECTRL
CELL[2].IMUX_IMUX[42]	DSP[1].B[9]
CELL[2].IMUX_IMUX[43]	DSP[1].C[9]
CELL[2].IMUX_IMUX[44]	DSP[1].B[10]
CELL[2].IMUX_IMUX[45]	DSP[1].A[28]
CELL[2].IMUX_IMUX[46]	DSP[1].C[28]
CELL[2].IMUX_IMUX[47]	DSP[0].A[28]
CELL[2].OUT_BEL[0]	DSP[1].P[31]
CELL[2].OUT_BEL[1]	DSP[1].P[9]
CELL[2].OUT_BEL[2]	DSP[1].P[30]
CELL[2].OUT_BEL[3]	DSP[1].P[8]
CELL[2].OUT_BEL[4]	DSP[1].P[11]
CELL[2].OUT_BEL[5]	DSP[1].P[29]
CELL[2].OUT_BEL[6]	DSP[1].P[10]
CELL[2].OUT_BEL[7]	DSP[1].P[28]
CELL[2].OUT_BEL[8]	DSP[1].OVERFLOW
CELL[2].OUT_BEL[9]	DSP[0].UNDERFLOW
CELL[2].OUT_BEL[10]	DSP[0].OVERFLOW
CELL[2].OUT_BEL[11]	DSP[0].PATTERNDETECT
CELL[2].OUT_BEL[13]	DSP[1].PATTERNDETECT
CELL[2].OUT_BEL[14]	DSP[0].PATTERNBDETECT
CELL[2].OUT_BEL[15]	DSP[1].PATTERNBDETECT
CELL[2].OUT_BEL[16]	DSP[0].P[10]
CELL[2].OUT_BEL[17]	DSP[0].P[28]
CELL[2].OUT_BEL[18]	DSP[0].P[11]
CELL[2].OUT_BEL[19]	DSP[0].P[29]
CELL[2].OUT_BEL[20]	DSP[0].P[30]
CELL[2].OUT_BEL[21]	DSP[0].P[8]
CELL[2].OUT_BEL[22]	DSP[0].P[31]
CELL[2].OUT_BEL[23]	DSP[0].P[9]
CELL[3].IMUX_CLK[0]	DSP[1].CLK
CELL[3].IMUX_CTRL[0]	DSP[1].RSTC
CELL[3].IMUX_CTRL[1]	DSP[1].RSTM
CELL[3].IMUX_BYP_DSP[0]	DSP[1].CEAD
CELL[3].IMUX_BYP_DSP[1]	DSP[0].D[15]
CELL[3].IMUX_BYP_DSP[2]	DSP[0].D[23]
CELL[3].IMUX_BYP_DSP[3]	DSP[0].D[14]
CELL[3].IMUX_BYP_DSP[4]	DSP[1].CEALUMODE
CELL[3].IMUX_BYP_DSP[5]	DSP[0].D[13]
CELL[3].IMUX_BYP_DSP[6]	DSP[0].INMODE[0]
CELL[3].IMUX_BYP_DSP[7]	DSP[0].D[12]
CELL[3].IMUX_FAN_DSP[0]	DSP[1].CED
CELL[3].IMUX_FAN_DSP[1]	DSP[0].INMODE[4]
CELL[3].IMUX_FAN_DSP[2]	DSP[1].CEINMODE
CELL[3].IMUX_FAN_DSP[3]	DSP[1].D[12]
CELL[3].IMUX_FAN_DSP[4]	DSP[1].D[15]
CELL[3].IMUX_FAN_DSP[5]	DSP[1].D[14]
CELL[3].IMUX_FAN_DSP[6]	DSP[1].D[13]
CELL[3].IMUX_FAN_DSP[7]	DSP[1].D[23]
CELL[3].IMUX_IMUX[0]	DSP[1].B[15]
CELL[3].IMUX_IMUX[1]	DSP[1].B[13]
CELL[3].IMUX_IMUX[2]	DSP[0].B[15]
CELL[3].IMUX_IMUX[3]	DSP[0].B[13]
CELL[3].IMUX_IMUX[4]	DSP[1].A[15]
CELL[3].IMUX_IMUX[5]	DSP[1].A[13]
CELL[3].IMUX_IMUX[6]	DSP[0].A[15]
CELL[3].IMUX_IMUX[7]	DSP[0].A[13]
CELL[3].IMUX_IMUX[8]	DSP[1].CEB1
CELL[3].IMUX_IMUX[9]	DSP[1].CEA1
CELL[3].IMUX_IMUX[10]	DSP[1].C[33]
CELL[3].IMUX_IMUX[11]	DSP[1].CECTRL
CELL[3].IMUX_IMUX[12]	DSP[1].C[34]
CELL[3].IMUX_IMUX[13]	DSP[0].ALUMODE[1]
CELL[3].IMUX_IMUX[14]	DSP[0].CARRYINSEL[1]
CELL[3].IMUX_IMUX[15]	DSP[1].CARRYIN
CELL[3].IMUX_IMUX[16]	DSP[1].CEB2
CELL[3].IMUX_IMUX[17]	DSP[1].CEA2
CELL[3].IMUX_IMUX[18]	DSP[0].C[33]
CELL[3].IMUX_IMUX[19]	DSP[1].CEM
CELL[3].IMUX_IMUX[20]	DSP[0].C[34]
CELL[3].IMUX_IMUX[21]	DSP[0].ALUMODE[0]
CELL[3].IMUX_IMUX[22]	DSP[1].C[32]
CELL[3].IMUX_IMUX[23]	DSP[0].CARRYIN
CELL[3].IMUX_IMUX[24]	DSP[1].C[35]
CELL[3].IMUX_IMUX[25]	DSP[1].C[15]
CELL[3].IMUX_IMUX[26]	DSP[1].CECARRYIN
CELL[3].IMUX_IMUX[27]	DSP[1].C[13]
CELL[3].IMUX_IMUX[28]	DSP[1].OPMODE[0]
CELL[3].IMUX_IMUX[29]	DSP[1].C[14]
CELL[3].IMUX_IMUX[30]	DSP[0].CARRYINSEL[0]
CELL[3].IMUX_IMUX[31]	DSP[1].C[12]
CELL[3].IMUX_IMUX[32]	DSP[0].C[35]
CELL[3].IMUX_IMUX[33]	DSP[0].C[15]
CELL[3].IMUX_IMUX[34]	DSP[1].CEC
CELL[3].IMUX_IMUX[35]	DSP[0].C[13]
CELL[3].IMUX_IMUX[36]	DSP[1].OPMODE[2]
CELL[3].IMUX_IMUX[37]	DSP[0].C[14]
CELL[3].IMUX_IMUX[38]	DSP[0].C[32]
CELL[3].IMUX_IMUX[39]	DSP[0].C[12]
CELL[3].IMUX_IMUX[40]	DSP[1].B[14]
CELL[3].IMUX_IMUX[41]	DSP[1].B[12]
CELL[3].IMUX_IMUX[42]	DSP[0].B[14]
CELL[3].IMUX_IMUX[43]	DSP[0].B[12]
CELL[3].IMUX_IMUX[44]	DSP[1].A[14]
CELL[3].IMUX_IMUX[45]	DSP[1].A[12]
CELL[3].IMUX_IMUX[46]	DSP[0].A[14]
CELL[3].IMUX_IMUX[47]	DSP[0].A[12]
CELL[3].OUT_BEL[0]	DSP[1].P[35]
CELL[3].OUT_BEL[1]	DSP[1].P[13]
CELL[3].OUT_BEL[2]	DSP[1].P[34]
CELL[3].OUT_BEL[3]	DSP[1].P[12]
CELL[3].OUT_BEL[4]	DSP[1].P[15]
CELL[3].OUT_BEL[5]	DSP[1].P[33]
CELL[3].OUT_BEL[6]	DSP[1].P[14]
CELL[3].OUT_BEL[7]	DSP[1].P[32]
CELL[3].OUT_BEL[8]	DSP[1].CARRYOUT[0]
CELL[3].OUT_BEL[10]	DSP[1].CARRYOUT[2]
CELL[3].OUT_BEL[11]	DSP[1].CARRYOUT[1]
CELL[3].OUT_BEL[14]	DSP[1].UNDERFLOW
CELL[3].OUT_BEL[15]	DSP[1].CARRYOUT[3]
CELL[3].OUT_BEL[16]	DSP[0].P[14]
CELL[3].OUT_BEL[17]	DSP[0].P[32]
CELL[3].OUT_BEL[18]	DSP[0].P[15]
CELL[3].OUT_BEL[19]	DSP[0].P[33]
CELL[3].OUT_BEL[20]	DSP[0].P[34]
CELL[3].OUT_BEL[21]	DSP[0].P[12]
CELL[3].OUT_BEL[22]	DSP[0].P[35]
CELL[3].OUT_BEL[23]	DSP[0].P[13]
CELL[4].IMUX_CTRL[0]	DSP[1].RSTP
CELL[4].IMUX_CTRL[1]	DSP[1].RSTB
CELL[4].IMUX_BYP_DSP[0]	DSP[1].ALUMODE[3]
CELL[4].IMUX_BYP_DSP[1]	DSP[0].D[19]
CELL[4].IMUX_BYP_DSP[2]	DSP[1].CARRYINSEL[2]
CELL[4].IMUX_BYP_DSP[3]	DSP[0].D[18]
CELL[4].IMUX_BYP_DSP[4]	DSP[1].INMODE[3]
CELL[4].IMUX_BYP_DSP[5]	DSP[0].D[17]
CELL[4].IMUX_BYP_DSP[6]	DSP[1].RSTD
CELL[4].IMUX_BYP_DSP[7]	DSP[0].D[16]
CELL[4].IMUX_FAN_DSP[0]	DSP[1].ALUMODE[2]
CELL[4].IMUX_FAN_DSP[2]	DSP[1].OPMODE[6]
CELL[4].IMUX_FAN_DSP[3]	DSP[1].D[16]
CELL[4].IMUX_FAN_DSP[4]	DSP[1].D[19]
CELL[4].IMUX_FAN_DSP[5]	DSP[1].D[18]
CELL[4].IMUX_FAN_DSP[6]	DSP[1].D[17]
CELL[4].IMUX_FAN_DSP[7]	DSP[1].INMODE[2]
CELL[4].IMUX_IMUX[0]	DSP[1].ALUMODE[0]
CELL[4].IMUX_IMUX[1]	DSP[0].C[19]
CELL[4].IMUX_IMUX[2]	DSP[1].B[17]
CELL[4].IMUX_IMUX[3]	DSP[0].B[17]
CELL[4].IMUX_IMUX[4]	DSP[1].A[19]
CELL[4].IMUX_IMUX[5]	DSP[1].A[17]
CELL[4].IMUX_IMUX[6]	DSP[0].A[19]
CELL[4].IMUX_IMUX[7]	DSP[0].A[17]
CELL[4].IMUX_IMUX[8]	DSP[1].OPMODE[1]
CELL[4].IMUX_IMUX[9]	DSP[1].OPMODE[5]
CELL[4].IMUX_IMUX[10]	DSP[1].C[39]
CELL[4].IMUX_IMUX[11]	DSP[1].C[46]
CELL[4].IMUX_IMUX[12]	DSP[1].C[38]
CELL[4].IMUX_IMUX[13]	DSP[1].C[18]
CELL[4].IMUX_IMUX[14]	DSP[1].RSTCTRL
CELL[4].IMUX_IMUX[15]	DSP[1].RSTALLCARRYIN
CELL[4].IMUX_IMUX[16]	DSP[1].OPMODE[3]
CELL[4].IMUX_IMUX[17]	DSP[1].OPMODE[4]
CELL[4].IMUX_IMUX[18]	DSP[0].C[39]
CELL[4].IMUX_IMUX[19]	DSP[0].C[46]
CELL[4].IMUX_IMUX[20]	DSP[0].C[38]
CELL[4].IMUX_IMUX[21]	DSP[0].C[18]
CELL[4].IMUX_IMUX[22]	DSP[1].RSTALUMODE
CELL[4].IMUX_IMUX[23]	DSP[1].RSTINMODE
CELL[4].IMUX_IMUX[24]	DSP[1].C[37]
CELL[4].IMUX_IMUX[25]	DSP[1].C[47]
CELL[4].IMUX_IMUX[26]	DSP[1].C[44]
CELL[4].IMUX_IMUX[27]	DSP[1].C[17]
CELL[4].IMUX_IMUX[28]	DSP[1].CARRYINSEL[1]
CELL[4].IMUX_IMUX[29]	DSP[1].C[45]
CELL[4].IMUX_IMUX[30]	DSP[1].C[36]
CELL[4].IMUX_IMUX[31]	DSP[1].C[16]
CELL[4].IMUX_IMUX[32]	DSP[0].C[37]
CELL[4].IMUX_IMUX[33]	DSP[0].C[47]
CELL[4].IMUX_IMUX[34]	DSP[0].C[44]
CELL[4].IMUX_IMUX[35]	DSP[0].C[17]
CELL[4].IMUX_IMUX[36]	DSP[1].CARRYINSEL[0]
CELL[4].IMUX_IMUX[37]	DSP[0].C[45]
CELL[4].IMUX_IMUX[38]	DSP[0].C[36]
CELL[4].IMUX_IMUX[39]	DSP[0].C[16]
CELL[4].IMUX_IMUX[40]	DSP[1].ALUMODE[1]
CELL[4].IMUX_IMUX[41]	DSP[1].C[19]
CELL[4].IMUX_IMUX[42]	DSP[1].B[16]
CELL[4].IMUX_IMUX[43]	DSP[0].B[16]
CELL[4].IMUX_IMUX[44]	DSP[1].A[18]
CELL[4].IMUX_IMUX[45]	DSP[1].A[16]
CELL[4].IMUX_IMUX[46]	DSP[0].A[18]
CELL[4].IMUX_IMUX[47]	DSP[0].A[16]
CELL[4].OUT_BEL[0]	DSP[1].P[37]
CELL[4].OUT_BEL[1]	DSP[1].P[17]
CELL[4].OUT_BEL[2]	DSP[1].P[38]
CELL[4].OUT_BEL[3]	DSP[1].P[16]
CELL[4].OUT_BEL[4]	DSP[1].P[19]
CELL[4].OUT_BEL[5]	DSP[1].P[39]
CELL[4].OUT_BEL[6]	DSP[1].P[18]
CELL[4].OUT_BEL[7]	DSP[1].P[36]
CELL[4].OUT_BEL[8]	DSP[0].P[47]
CELL[4].OUT_BEL[9]	DSP[0].P[44]
CELL[4].OUT_BEL[10]	DSP[0].P[45]
CELL[4].OUT_BEL[11]	DSP[1].P[45]
CELL[4].OUT_BEL[12]	DSP[1].P[44]
CELL[4].OUT_BEL[13]	DSP[0].P[46]
CELL[4].OUT_BEL[14]	DSP[1].P[46]
CELL[4].OUT_BEL[15]	DSP[1].P[47]
CELL[4].OUT_BEL[16]	DSP[0].P[18]
CELL[4].OUT_BEL[17]	DSP[0].P[36]
CELL[4].OUT_BEL[18]	DSP[0].P[19]
CELL[4].OUT_BEL[19]	DSP[0].P[39]
CELL[4].OUT_BEL[20]	DSP[0].P[38]
CELL[4].OUT_BEL[21]	DSP[0].P[16]
CELL[4].OUT_BEL[22]	DSP[0].P[37]
CELL[4].OUT_BEL[23]	DSP[0].P[17]

Bitstream

virtex6 DSP rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[1] bit 0	DSP[0]: PATTERN bit 23
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[1] bit 0	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 22	DSP[0]: MASK bit 22
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[1] bit 1
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 21	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 21
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[1] bit 1
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[3] bit 1	DSP[0]: MASK bit 20
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 20
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 19	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[3] bit 0	DSP[0]: PATTERN bit 19
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[5] bit 0	DSP[0]: BREG bit 4
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 18	DSP[0]: MASK bit 18
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: BREG bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[5] bit 1	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[7] bit 1
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 17
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 17
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[7] bit 0	DSP[0]: USE_SIMD bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 16	DSP[0]: MASK bit 16
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[7] bit 0
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 15	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[1] bit 0
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 15	DSP[0]: !invert OPMODE[6]
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 14	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[1] bit 1
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 14
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[7] bit 1	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[3] bit 1
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 13	DSP[0]: MASK bit 13
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert OPMODE[5]	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 12	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[3] bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 12
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: BREG bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 11	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 11	DSP[0]: BREG bit 3
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[1] bit 1	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 10	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 10
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[5] bit 0	DSP[0]: !invert INMODE[4]
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 9	DSP[0]: MASK bit 9
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[5] bit 1	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[1] bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 8	DSP[0]: MASK bit 8
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[7] bit 1
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[7] bit 0	DSP[0]: MASK bit 7
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 7	DSP[0]: !invert OPMODE[4]
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[2] bit 0	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 6
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! CARRYINSELREG	DSP[0]: PATTERN bit 6
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[2] bit 1	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[1] bit 0
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 5	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[1] bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! CARRYINREG	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[3] bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 5	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[3] bit 0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: BREG bit 2	DSP[0]: MASK bit 4
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: B_INPUT bit 0	DSP[0]: PATTERN bit 4
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 3
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[5] bit 0	DSP[0]: PATTERN bit 3
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 2	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[5] bit 1
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 2
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert CARRYIN	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[7] bit 1
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 1	DSP[0]: MASK bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[7] bit 0	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 0	DSP[0]: MASK bit 0

virtex6 DSP rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[0] bit 1	DSP[0]: PATTERN bit 39
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 38
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[3] bit 0	DSP[0]: PATTERN bit 38
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert OPMODE[0]
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 37	DSP[0]: MASK bit 37
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert OPMODE[1]
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 36	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 36	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[7] bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[5] bit 0
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 35	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[5] bit 1	DSP[0]: PATTERN bit 35
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 34	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[7] bit 1
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 34	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[7] bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert INMODE[1]
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 33	DSP[0]: AREG bit 2
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 33	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[7] bit 0
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: AREG bit 1	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 32	DSP[0]: MASK bit 32
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! OPMODEREG	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[1] bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 31	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 31	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[1] bit 1
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert INMODE[0]
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[6] bit 1	DSP[0]: MASK bit 30
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[3] bit 1	DSP[0]: PATTERN bit 30
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[3] bit 0
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[6] bit 0	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 29	DSP[0]: MASK bit 29
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert OPMODE[3]	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[5] bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[5] bit 1	DSP[0]: MASK bit 28
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[7] bit 1	DSP[0]: PATTERN bit 28
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert OPMODE[2]
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 27	DSP[0]: MASK bit 27
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[7] bit 0
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 26	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[0] bit 1	DSP[0]: PATTERN bit 26
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[0] bit 0	DSP[0]: MASK bit 25
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! ADREG	DSP[0]: PATTERN bit 25
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 24	DSP[0]: USE_SIMD bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! DREG	DSP[0]: PATTERN bit 24
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! MREG	DSP[0]: USE_DPORT
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[0] bit 0
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[4] bit 1	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert CLK	DSP[0]: AREG bit 4
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: AREG bit 0	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! PREG
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! CREG	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[2] bit 0
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[4] bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[0] bit 1	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert INMODE[3]
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[4] bit 0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[6] bit 0	DSP[0]: AUTORESET_PATTERN_DETECT_OPTINV
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: AUTORESET_PATTERN_DETECT	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[4] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[6] bit 1	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: SEL_MASK bit 0	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: SEL_ROUNDING_MASK bit 1	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[2] bit 1
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: SEL_PATTERN bit 0	DSP[0]: SEL_ROUNDING_MASK bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! INMODEREG	DSP[0]: !invert INMODE[2]
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 23	-

virtex6 DSP rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 11	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 11	DSP[1]: BREG bit 3
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[2] bit 1	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 10	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 10
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[6] bit 0	DSP[1]: !invert INMODE[4]
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 9	DSP[1]: MASK bit 9
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[6] bit 1	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[2] bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 8	DSP[1]: MASK bit 8
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[3] bit 1
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[3] bit 0	DSP[1]: MASK bit 7
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 7	DSP[1]: !invert OPMODE[4]
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[2] bit 0	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 6
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! CARRYINSELREG	DSP[1]: PATTERN bit 6
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[2] bit 1	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[4] bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 5	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[4] bit 1
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! CARRYINREG	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[5] bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 5	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[5] bit 0
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: BREG bit 2	DSP[1]: MASK bit 4
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: B_INPUT bit 0	DSP[1]: PATTERN bit 4
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 3
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[6] bit 0	DSP[1]: PATTERN bit 3
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 2	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[6] bit 1
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 2
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert CARRYIN	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[3] bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 1	DSP[1]: MASK bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[3] bit 0	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 0	DSP[1]: MASK bit 0
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[2] bit 1	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! USE_MULT
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[2] bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[2] bit 0	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert ALUMODE[0]
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 47	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[2] bit 1
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[0] bit 1	DSP[0]: PATTERN bit 47
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 46	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 46	DSP[0]: !invert ALUMODE[1]
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[0] bit 1	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[0] bit 0
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 45	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 45
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[6] bit 0	DSP[0]: !invert ALUMODE[2]
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 44	DSP[0]: MASK bit 44
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[0] bit 0	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[6] bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: USE_SIMD bit 2	DSP[0]: MASK bit 43
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[6] bit 1	DSP[0]: PATTERN bit 43
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: ! ALUMODEREG	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 42	DSP[0]: MASK bit 42
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[6] bit 0
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: A_INPUT bit 0
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[1] bit 0	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 41	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 41	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: AREG bit 3
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: MASK bit 40	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[1] bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: PATTERN bit 40	SPEC_INT: mux CELL[0].IMUX_BYP_DSP[0] bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[3] bit 1	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[0]: !invert ALUMODE[3]	DSP[0]: MASK bit 39

virtex6 DSP rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 27	DSP[1]: MASK bit 27
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[3] bit 0
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 26	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[0] bit 1	DSP[1]: PATTERN bit 26
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[0] bit 0	DSP[1]: MASK bit 25
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! ADREG	DSP[1]: PATTERN bit 25
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 24	DSP[1]: USE_SIMD bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! DREG	DSP[1]: PATTERN bit 24
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! MREG	DSP[1]: USE_DPORT
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[0] bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[6] bit 1	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert CLK	DSP[1]: AREG bit 4
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: AREG bit 0	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! PREG
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! CREG	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[2] bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[6] bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[0] bit 1	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert INMODE[3]
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[4] bit 0
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[4] bit 0	DSP[1]: AUTORESET_PATTERN_DETECT_OPTINV
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: AUTORESET_PATTERN_DETECT	SPEC_INT: mux CELL[3].IMUX_BYP_DSP[4] bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[4] bit 1	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: SEL_MASK bit 0	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: SEL_ROUNDING_MASK bit 1	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[2] bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: SEL_PATTERN bit 0	DSP[1]: SEL_ROUNDING_MASK bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! INMODEREG	DSP[1]: !invert INMODE[2]
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 23	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[7] bit 0	DSP[1]: PATTERN bit 23
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[4] bit 0	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 22	DSP[1]: MASK bit 22
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[7] bit 1
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 21	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 21
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[4] bit 1
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[5] bit 1	DSP[1]: MASK bit 20
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 20
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 19	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[5] bit 0	DSP[1]: PATTERN bit 19
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[6] bit 0	DSP[1]: BREG bit 4
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 18	DSP[1]: MASK bit 18
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: BREG bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[6] bit 1	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[3] bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 17
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 17
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[3] bit 0	DSP[1]: USE_SIMD bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 16	DSP[1]: MASK bit 16
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[2] bit 0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 15	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[4] bit 0
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 15	DSP[1]: !invert OPMODE[6]
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 14	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[4] bit 1
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 14
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[2] bit 1	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[5] bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 13	DSP[1]: MASK bit 13
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert OPMODE[5]	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 12	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[5] bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 12
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: BREG bit 1

virtex6 DSP rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[7] bit 1	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! USE_MULT
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[7] bit 0
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[7] bit 0	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert ALUMODE[0]
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 47	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[7] bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[0] bit 1	DSP[1]: PATTERN bit 47
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 46	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 46	DSP[1]: !invert ALUMODE[1]
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[0] bit 1	SPEC_INT: mux CELL[2].IMUX_FAN_DSP[0] bit 0
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 45	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 45
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[1] bit 0	DSP[1]: !invert ALUMODE[2]
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 44	DSP[1]: MASK bit 44
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[0] bit 0	SPEC_INT: mux CELL[1].IMUX_FAN_DSP[1] bit 1
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: USE_SIMD bit 2	DSP[1]: MASK bit 43
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[1] bit 1	DSP[1]: PATTERN bit 43
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! ALUMODEREG	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 42	DSP[1]: MASK bit 42
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_FAN_DSP[1] bit 0
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: A_INPUT bit 0
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[4] bit 0	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 41	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 41	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: AREG bit 3
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 40	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[4] bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 40	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[0] bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[5] bit 1	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert ALUMODE[3]	DSP[1]: MASK bit 39
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_BYP_DSP[0] bit 1	DSP[1]: PATTERN bit 39
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 38
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[5] bit 0	DSP[1]: PATTERN bit 38
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert OPMODE[0]
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 37	DSP[1]: MASK bit 37
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert OPMODE[1]
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 36	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 36	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[2] bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[6] bit 0
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 35	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[6] bit 1	DSP[1]: PATTERN bit 35
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 34	SPEC_INT: mux CELL[1].IMUX_BYP_DSP[2] bit 1
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 34	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[3] bit 1
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert INMODE[1]
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 33	DSP[1]: AREG bit 2
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 33	SPEC_INT: mux CELL[4].IMUX_FAN_DSP[3] bit 0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: AREG bit 1	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 32	DSP[1]: MASK bit 32
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: ! OPMODEREG	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[4] bit 0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: MASK bit 31	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 31	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[4] bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert INMODE[0]
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[4] bit 1	DSP[1]: MASK bit 30
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[5] bit 1	DSP[1]: PATTERN bit 30
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[5] bit 0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_BYP_DSP[4] bit 0	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: PATTERN bit 29	DSP[1]: MASK bit 29
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert OPMODE[3]	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[6] bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[6] bit 1	DSP[1]: MASK bit 28
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_FAN_DSP[3] bit 1	DSP[1]: PATTERN bit 28
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DSP[1]: !invert OPMODE[2]

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