Interconnect

TODO: document

Tile slots

virtex6 tile slots
Slot	Tiles	Bel slots
INT	INT	INT
INTF	INTF, INTF_DELAY	INTF_INT, INTF_TESTMUX
BEL	CLBLL, CLBLM, BRAM, DSP, IO, CMT, PMVIOB, EMAC, PCIE, GTX, GTH, CLK_BUFG_S, CLK_BUFG_N	SPEC_INT, SLICE[0], SLICE[1], SLICE[2], SLICE[3], BRAM, BRAM_F, BRAM_H[0], BRAM_H[1], BRAM_ADDR, DSP[0], DSP[1], DSP_C, ILOGIC[0], ILOGIC[1], OLOGIC[0], OLOGIC[1], IODELAY[0], IODELAY[1], IDELAY[0], IDELAY[1], ODELAY[0], ODELAY[1], IOB[0], IOB[1], DCM[0], DCM[1], PLL[0], PLL[1], PPR_FRAME, PHASER_IN[0], PHASER_IN[1], PHASER_IN[2], PHASER_IN[3], PHASER_OUT[0], PHASER_OUT[1], PHASER_OUT[2], PHASER_OUT[3], PHASER_REF, PHY_CONTROL, BUFMRCE[0], BUFMRCE[1], CCM, PMCD[0], PMCD[1], DPM, BUFHCE_W[0], BUFHCE_W[1], BUFHCE_W[2], BUFHCE_W[3], BUFHCE_W[4], BUFHCE_W[5], BUFHCE_W[6], BUFHCE_W[7], BUFHCE_W[8], BUFHCE_W[9], BUFHCE_W[10], BUFHCE_W[11], BUFHCE_E[0], BUFHCE_E[1], BUFHCE_E[2], BUFHCE_E[3], BUFHCE_E[4], BUFHCE_E[5], BUFHCE_E[6], BUFHCE_E[7], BUFHCE_E[8], BUFHCE_E[9], BUFHCE_E[10], BUFHCE_E[11], PMV_CLK, PMVIOB_CLK, PMV2, PMV2_SVT, MTBF2, PPC, EMAC, PCIE, PCIE3, GT11[0], GT11[1], GT11CLK, GTP_DUAL, GTX_DUAL, HCLK_GTX, GTCLK[0], GTCLK[1], GTX[0], GTX[1], GTX[2], GTX[3], GTH_QUAD, HCLK_DRP_GTP_MID, GTP_COMMON, GTX_COMMON, GTP_CHANNEL, GTX_CHANNEL, CRC32[0], CRC32[1], CRC32[2], CRC32[3], BUFGCTRL[0], BUFGCTRL[1], BUFGCTRL[2], BUFGCTRL[3], BUFGCTRL[4], BUFGCTRL[5], BUFGCTRL[6], BUFGCTRL[7], BUFGCTRL[8], BUFGCTRL[9], BUFGCTRL[10], BUFGCTRL[11], BUFGCTRL[12], BUFGCTRL[13], BUFGCTRL[14], BUFGCTRL[15], BUFGCTRL[16], BUFGCTRL[17], BUFGCTRL[18], BUFGCTRL[19], BUFGCTRL[20], BUFGCTRL[21], BUFGCTRL[22], BUFGCTRL[23], BUFGCTRL[24], BUFGCTRL[25], BUFGCTRL[26], BUFGCTRL[27], BUFGCTRL[28], BUFGCTRL[29], BUFGCTRL[30], BUFGCTRL[31], PS
CMT_FIFO		CMT_FIFO_INT, IN_FIFO, OUT_FIFO
CFG	CFG	SYSMON_INT, BSCAN[0], BSCAN[1], BSCAN[2], BSCAN[3], ICAP[0], ICAP[1], STARTUP, CAPTURE, JTAGPPC, PMV_CFG[0], PMV_CFG[1], DCIRESET, FRAME_ECC, USR_ACCESS, KEY_CLEAR, EFUSE_USR, DNA_PORT, CFG_IO_ACCESS, PMVIOB_CFG, MISC_CFG, SYSMON
CLK		CLK_INT
HROW		HROW_INT
HCLK	HCLK	HCLK, GLOBALSIG, HCLK_DRP[0], HCLK_DRP[1]
HCLK_BEL	PMVBRAM, HCLK_IO	PMVBRAM, HCLK_IO_INT, HCLK_CMT_DRP, BUFR[0], BUFR[1], BUFR[2], BUFR[3], BUFIO[0], BUFIO[1], BUFIO[2], BUFIO[3], IDELAYCTRL, DCI, BANK, LVDS
GLOBAL	GLOBAL	GLOBAL

Bel slots

virtex6 bel slots
Slot	Class	Tile slot	Tiles
INT	routing	INT	INT
INTF_INT	routing	INTF	INTF, INTF_DELAY
INTF_TESTMUX	routing	INTF	INTF, INTF_DELAY
SPEC_INT	routing	BEL	DSP, IO, CMT, GTX, CLK_BUFG_S, CLK_BUFG_N
SLICE[0]	SLICE_V5	BEL	CLBLL, CLBLM
SLICE[1]	SLICE_V5	BEL	CLBLL, CLBLM
SLICE[2]	SLICE_V5	BEL
SLICE[3]	SLICE_V5	BEL
BRAM	legacy	BEL
BRAM_F	legacy	BEL	BRAM
BRAM_H[0]	legacy	BEL	BRAM
BRAM_H[1]	legacy	BEL	BRAM
BRAM_ADDR	legacy	BEL
DSP[0]	DSP_V6	BEL	DSP
DSP[1]	DSP_V6	BEL	DSP
DSP_C	DSP_C	BEL
ILOGIC[0]	ILOGIC	BEL	IO
ILOGIC[1]	ILOGIC	BEL	IO
OLOGIC[0]	OLOGIC	BEL	IO
OLOGIC[1]	OLOGIC	BEL	IO
IODELAY[0]	IODELAY_V6	BEL	IO
IODELAY[1]	IODELAY_V6	BEL	IO
IDELAY[0]	IDELAY	BEL
IDELAY[1]	IDELAY	BEL
ODELAY[0]	ODELAY	BEL
ODELAY[1]	ODELAY	BEL
IOB[0]	IOB	BEL	IO
IOB[1]	IOB	BEL	IO
DCM[0]	DCM_V5	BEL
DCM[1]	DCM_V5	BEL
PLL[0]	PLL_V6	BEL	CMT
PLL[1]	PLL_V6	BEL	CMT
PPR_FRAME	PPR_FRAME	BEL	CMT
PHASER_IN[0]	PHASER_IN	BEL
PHASER_IN[1]	PHASER_IN	BEL
PHASER_IN[2]	PHASER_IN	BEL
PHASER_IN[3]	PHASER_IN	BEL
PHASER_OUT[0]	PHASER_OUT	BEL
PHASER_OUT[1]	PHASER_OUT	BEL
PHASER_OUT[2]	PHASER_OUT	BEL
PHASER_OUT[3]	PHASER_OUT	BEL
PHASER_REF	PHASER_REF	BEL
PHY_CONTROL	PHY_CONTROL	BEL
BUFMRCE[0]	BUFHCE	BEL
BUFMRCE[1]	BUFHCE	BEL
CCM	CCM	BEL
PMCD[0]	PMCD	BEL
PMCD[1]	PMCD	BEL
DPM	DPM	BEL
BUFHCE_W[0]	BUFHCE	BEL	CMT
BUFHCE_W[1]	BUFHCE	BEL	CMT
BUFHCE_W[2]	BUFHCE	BEL	CMT
BUFHCE_W[3]	BUFHCE	BEL	CMT
BUFHCE_W[4]	BUFHCE	BEL	CMT
BUFHCE_W[5]	BUFHCE	BEL	CMT
BUFHCE_W[6]	BUFHCE	BEL	CMT
BUFHCE_W[7]	BUFHCE	BEL	CMT
BUFHCE_W[8]	BUFHCE	BEL	CMT
BUFHCE_W[9]	BUFHCE	BEL	CMT
BUFHCE_W[10]	BUFHCE	BEL	CMT
BUFHCE_W[11]	BUFHCE	BEL	CMT
BUFHCE_E[0]	BUFHCE	BEL	CMT
BUFHCE_E[1]	BUFHCE	BEL	CMT
BUFHCE_E[2]	BUFHCE	BEL	CMT
BUFHCE_E[3]	BUFHCE	BEL	CMT
BUFHCE_E[4]	BUFHCE	BEL	CMT
BUFHCE_E[5]	BUFHCE	BEL	CMT
BUFHCE_E[6]	BUFHCE	BEL	CMT
BUFHCE_E[7]	BUFHCE	BEL	CMT
BUFHCE_E[8]	BUFHCE	BEL	CMT
BUFHCE_E[9]	BUFHCE	BEL	CMT
BUFHCE_E[10]	BUFHCE	BEL	CMT
BUFHCE_E[11]	BUFHCE	BEL	CMT
PMV_CLK	PMV	BEL
PMVIOB_CLK	PMVIOB	BEL	PMVIOB
PMV2	PMV2	BEL
PMV2_SVT	PMV2	BEL
MTBF2	MTBF2	BEL
PPC	PPC440	BEL
EMAC	EMAC_V6	BEL	EMAC
PCIE	PCIE_V6	BEL	PCIE
PCIE3	PCIE3	BEL
GT11[0]	GT11	BEL
GT11[1]	GT11	BEL
GT11CLK	GT11CLK	BEL
GTP_DUAL	GTP_DUAL	BEL
GTX_DUAL	GTX_DUAL	BEL
HCLK_GTX	HCLK_GTX	BEL	GTX
GTCLK[0]	GTCLK	BEL	GTX
GTCLK[1]	GTCLK	BEL	GTX
GTX[0]	GTX	BEL	GTX
GTX[1]	GTX	BEL	GTX
GTX[2]	GTX	BEL	GTX
GTX[3]	GTX	BEL	GTX
GTH_QUAD	GTH_QUAD	BEL	GTH
HCLK_DRP_GTP_MID	HCLK_DRP	BEL
GTP_COMMON	GTP_COMMON	BEL
GTX_COMMON	GTX_COMMON	BEL
GTP_CHANNEL	GTP_CHANNEL	BEL
GTX_CHANNEL	GTX_CHANNEL	BEL
CRC32[0]	CRC32	BEL
CRC32[1]	CRC32	BEL
CRC32[2]	CRC32	BEL
CRC32[3]	CRC32	BEL
BUFGCTRL[0]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[1]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[2]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[3]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[4]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[5]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[6]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[7]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[8]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[9]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[10]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[11]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[12]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[13]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[14]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[15]	BUFGCTRL	BEL	CLK_BUFG_S
BUFGCTRL[16]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[17]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[18]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[19]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[20]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[21]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[22]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[23]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[24]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[25]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[26]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[27]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[28]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[29]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[30]	BUFGCTRL	BEL	CLK_BUFG_N
BUFGCTRL[31]	BUFGCTRL	BEL	CLK_BUFG_N
PS	PS	BEL
CMT_FIFO_INT	routing	CMT_FIFO
IN_FIFO	IN_FIFO	CMT_FIFO
OUT_FIFO	OUT_FIFO	CMT_FIFO
SYSMON_INT	routing	CFG
BSCAN[0]	BSCAN	CFG	CFG
BSCAN[1]	BSCAN	CFG	CFG
BSCAN[2]	BSCAN	CFG	CFG
BSCAN[3]	BSCAN	CFG	CFG
ICAP[0]	ICAP_V6	CFG	CFG
ICAP[1]	ICAP_V6	CFG	CFG
STARTUP	STARTUP	CFG	CFG
CAPTURE	CAPTURE	CFG	CFG
JTAGPPC	JTAGPPC	CFG
PMV_CFG[0]	PMV	CFG	CFG
PMV_CFG[1]	PMV	CFG	CFG
DCIRESET	DCIRESET	CFG	CFG
FRAME_ECC	FRAME_ECC_V6	CFG	CFG
USR_ACCESS	USR_ACCESS	CFG	CFG
KEY_CLEAR	KEY_CLEAR	CFG
EFUSE_USR	EFUSE_USR	CFG	CFG
DNA_PORT	DNA_PORT	CFG	CFG
CFG_IO_ACCESS	CFG_IO_ACCESS_V6	CFG	CFG
PMVIOB_CFG	PMVIOB	CFG
MISC_CFG	MISC_CFG	CFG	CFG
SYSMON	SYSMON_V5	CFG	CFG
CLK_INT	routing	CLK
HROW_INT	routing	HROW
HCLK	routing	HCLK	HCLK
GLOBALSIG	GLOBALSIG	HCLK	HCLK
HCLK_DRP[0]	HCLK_DRP	HCLK	HCLK
HCLK_DRP[1]	HCLK_DRP	HCLK
PMVBRAM	PMVBRAM_V6	HCLK_BEL	PMVBRAM
HCLK_IO_INT	routing	HCLK_BEL	HCLK_IO
HCLK_CMT_DRP	HCLK_CMT_DRP	HCLK_BEL
BUFR[0]	BUFR	HCLK_BEL	HCLK_IO
BUFR[1]	BUFR	HCLK_BEL	HCLK_IO
BUFR[2]	BUFR	HCLK_BEL
BUFR[3]	BUFR	HCLK_BEL
BUFIO[0]	BUFIO	HCLK_BEL	HCLK_IO
BUFIO[1]	BUFIO	HCLK_BEL	HCLK_IO
BUFIO[2]	BUFIO	HCLK_BEL	HCLK_IO
BUFIO[3]	BUFIO	HCLK_BEL	HCLK_IO
IDELAYCTRL	IDELAYCTRL	HCLK_BEL	HCLK_IO
DCI	DCI	HCLK_BEL	HCLK_IO
BANK	BANK	HCLK_BEL	HCLK_IO
LVDS	LVDS_V4	HCLK_BEL
GLOBAL	GLOBAL	GLOBAL	GLOBAL

Connector slots

virtex6 connector slots
Slot	Opposite	Connectors
W	E	PASS_W, TERM_W
E	W	PASS_E, TERM_E
S	N	PASS_S, TERM_S, TERM_S_HOLE
N	S	PASS_N, TERM_N, TERM_N_HOLE
IO_S	IO_N	IO_S
IO_N	IO_S	IO_N
CLK_PREV	CLK_NEXT	CLK_PREV
CLK_NEXT	CLK_PREV	CLK_NEXT
BEL_S	BEL_N
BEL_N	BEL_S
CMT_PREV	CMT_NEXT
CMT_NEXT	CMT_PREV
HCLK_ROW_PREV	HCLK_ROW_NEXT	HCLK_ROW_PREV
HCLK_ROW_NEXT	HCLK_ROW_PREV	HCLK_ROW_NEXT, HCLK_ROW_NEXT_PASS

Region slots

virtex6 region slots
Slot	Wires
GLOBAL	GCLK[0], GCLK[1], GCLK[2], GCLK[3], GCLK[4], GCLK[5], GCLK[6], GCLK[7], GCLK[8], GCLK[9], GCLK[10], GCLK[11], GCLK[12], GCLK[13], GCLK[14], GCLK[15], GCLK[16], GCLK[17], GCLK[18], GCLK[19], GCLK[20], GCLK[21], GCLK[22], GCLK[23], GCLK[24], GCLK[25], GCLK[26], GCLK[27], GCLK[28], GCLK[29], GCLK[30], GCLK[31], GIOB[0], GIOB[1], GIOB[2], GIOB[3], GIOB[4], GIOB[5], GIOB[6], GIOB[7]
HROW	HCLK_ROW[0], HCLK_ROW[1], HCLK_ROW[2], HCLK_ROW[3], HCLK_ROW[4], HCLK_ROW[5], HCLK_ROW[6], HCLK_ROW[7], HCLK_ROW[8], HCLK_ROW[9], HCLK_ROW[10], HCLK_ROW[11], RCLK_ROW[0], RCLK_ROW[1], RCLK_ROW[2], RCLK_ROW[3], RCLK_ROW[4], RCLK_ROW[5], MGT_ROW[0], MGT_ROW[1], MGT_ROW[2], MGT_ROW[3], MGT_ROW[4], MGT_ROW[5], MGT_ROW[6], MGT_ROW[7], MGT_ROW[8], MGT_ROW[9]
LEAF	LCLK[0], LCLK[1], LCLK[2], LCLK[3], LCLK[4], LCLK[5], LCLK[6], LCLK[7]
LEAF_IO	HCLK_IO[0], HCLK_IO[1], HCLK_IO[2], HCLK_IO[3], HCLK_IO[4], HCLK_IO[5], HCLK_IO[6], HCLK_IO[7], HCLK_IO[8], HCLK_IO[9], HCLK_IO[10], HCLK_IO[11], RCLK_IO[0], RCLK_IO[1], RCLK_IO[2], RCLK_IO[3], RCLK_IO[4], RCLK_IO[5], IOCLK[0], IOCLK[1], IOCLK[2], IOCLK[3], IOCLK[4], IOCLK[5], IOCLK[6], IOCLK[7], OCLK[0], OCLK[1]

Wires

virtex6 wires
Wire	Kind
PULLUP	pullup
TIE_0	tie 0
TIE_1	tie 1
LCLK[0]	regional LEAF
LCLK[1]	regional LEAF
LCLK[2]	regional LEAF
LCLK[3]	regional LEAF
LCLK[4]	regional LEAF
LCLK[5]	regional LEAF
LCLK[6]	regional LEAF
LCLK[7]	regional LEAF
SNG_W0_N3	mux
SNG_W0_S4	mux
SNG_W0[0]	mux
SNG_W0[1]	mux
SNG_W0[2]	mux
SNG_W0[3]	branch N
SNG_W0[4]	branch S
SNG_W0[5]	mux
SNG_W0[6]	mux
SNG_W0[7]	mux
SNG_W1[0]	branch E
SNG_W1[1]	branch E
SNG_W1[2]	branch E
SNG_W1[3]	branch E
SNG_W1[4]	branch E
SNG_W1[5]	branch E
SNG_W1[6]	branch E
SNG_W1[7]	branch E
SNG_W1_S4	branch N
SNG_W1_N3	branch S
SNG_E0_N3	mux
SNG_E0_S4	mux
SNG_E0[0]	mux
SNG_E0[1]	mux
SNG_E0[2]	mux
SNG_E0[3]	branch N
SNG_E0[4]	branch S
SNG_E0[5]	mux
SNG_E0[6]	mux
SNG_E0[7]	mux
SNG_E1[0]	branch W
SNG_E1[1]	branch W
SNG_E1[2]	branch W
SNG_E1[3]	branch W
SNG_E1[4]	branch W
SNG_E1[5]	branch W
SNG_E1[6]	branch W
SNG_E1[7]	branch W
SNG_E1_S0	branch N
SNG_E1_N7	branch S
SNG_S0_S4	mux
SNG_S0[0]	mux
SNG_S0[1]	mux
SNG_S0[2]	mux
SNG_S0[3]	mux
SNG_S0[4]	branch S
SNG_S0[5]	mux
SNG_S0[6]	mux
SNG_S0[7]	mux
SNG_S1[0]	branch N
SNG_S1[1]	branch N
SNG_S1[2]	branch N
SNG_S1[3]	branch N
SNG_S1[4]	branch N
SNG_S1[5]	branch N
SNG_S1[6]	branch N
SNG_S1[7]	branch N
SNG_S1_N7	branch S
SNG_N0_N3	mux
SNG_N0[0]	mux
SNG_N0[1]	mux
SNG_N0[2]	mux
SNG_N0[3]	branch N
SNG_N0[4]	mux
SNG_N0[5]	mux
SNG_N0[6]	mux
SNG_N0[7]	mux
SNG_N1[0]	branch S
SNG_N1[1]	branch S
SNG_N1[2]	branch S
SNG_N1[3]	branch S
SNG_N1[4]	branch S
SNG_N1[5]	branch S
SNG_N1[6]	branch S
SNG_N1[7]	branch S
SNG_N1_S0	branch N
DBL_WW0[0]	mux
DBL_WW0[1]	mux
DBL_WW0[2]	mux
DBL_WW0[3]	mux
DBL_WW1[0]	branch E
DBL_WW1[1]	branch E
DBL_WW1[2]	branch E
DBL_WW1[3]	branch E
DBL_WW2[0]	branch E
DBL_WW2[1]	branch E
DBL_WW2[2]	branch E
DBL_WW2[3]	branch E
DBL_WW2_N3	branch S
DBL_EE0[0]	mux
DBL_EE0[1]	mux
DBL_EE0[2]	mux
DBL_EE0[3]	mux
DBL_EE1[0]	branch W
DBL_EE1[1]	branch W
DBL_EE1[2]	branch W
DBL_EE1[3]	branch W
DBL_EE2[0]	branch W
DBL_EE2[1]	branch W
DBL_EE2[2]	branch W
DBL_EE2[3]	branch W
DBL_SS0[0]	mux
DBL_SS0[1]	mux
DBL_SS0[2]	mux
DBL_SS0[3]	mux
DBL_SS1[0]	branch N
DBL_SS1[1]	branch N
DBL_SS1[2]	branch N
DBL_SS1[3]	branch N
DBL_SS2[0]	branch N
DBL_SS2[1]	branch N
DBL_SS2[2]	branch N
DBL_SS2[3]	branch N
DBL_SS2_N3	branch S
DBL_SW0[0]	mux
DBL_SW0[1]	mux
DBL_SW0[2]	mux
DBL_SW0[3]	mux
DBL_SW1[0]	branch N
DBL_SW1[1]	branch N
DBL_SW1[2]	branch N
DBL_SW1[3]	branch N
DBL_SW2[0]	branch E
DBL_SW2[1]	branch E
DBL_SW2[2]	branch E
DBL_SW2[3]	branch E
DBL_SW2_N3	branch S
DBL_SE0[0]	mux
DBL_SE0[1]	mux
DBL_SE0[2]	mux
DBL_SE0[3]	mux
DBL_SE1[0]	branch N
DBL_SE1[1]	branch N
DBL_SE1[2]	branch N
DBL_SE1[3]	branch N
DBL_SE2[0]	branch W
DBL_SE2[1]	branch W
DBL_SE2[2]	branch W
DBL_SE2[3]	branch W
DBL_NN0[0]	mux
DBL_NN0[1]	mux
DBL_NN0[2]	mux
DBL_NN0[3]	mux
DBL_NN1[0]	branch S
DBL_NN1[1]	branch S
DBL_NN1[2]	branch S
DBL_NN1[3]	branch S
DBL_NN2[0]	branch S
DBL_NN2[1]	branch S
DBL_NN2[2]	branch S
DBL_NN2[3]	branch S
DBL_NN2_S0	branch N
DBL_NW0[0]	mux
DBL_NW0[1]	mux
DBL_NW0[2]	mux
DBL_NW0[3]	mux
DBL_NW1[0]	branch S
DBL_NW1[1]	branch S
DBL_NW1[2]	branch S
DBL_NW1[3]	branch S
DBL_NW2[0]	branch E
DBL_NW2[1]	branch E
DBL_NW2[2]	branch E
DBL_NW2[3]	branch E
DBL_NW2_S0	branch N
DBL_NE0[0]	mux
DBL_NE0[1]	mux
DBL_NE0[2]	mux
DBL_NE0[3]	mux
DBL_NE1[0]	branch S
DBL_NE1[1]	branch S
DBL_NE1[2]	branch S
DBL_NE1[3]	branch S
DBL_NE2[0]	branch W
DBL_NE2[1]	branch W
DBL_NE2[2]	branch W
DBL_NE2[3]	branch W
DBL_NE2_S0	branch N
QUAD_WW0[0]	mux
QUAD_WW0[1]	mux
QUAD_WW0[2]	mux
QUAD_WW0[3]	mux
QUAD_WW1[0]	branch E
QUAD_WW1[1]	branch E
QUAD_WW1[2]	branch E
QUAD_WW1[3]	branch E
QUAD_WW2[0]	branch E
QUAD_WW2[1]	branch E
QUAD_WW2[2]	branch E
QUAD_WW2[3]	branch E
QUAD_WW3[0]	branch E
QUAD_WW3[1]	branch E
QUAD_WW3[2]	branch E
QUAD_WW3[3]	branch E
QUAD_WW4[0]	branch E
QUAD_WW4[1]	branch E
QUAD_WW4[2]	branch E
QUAD_WW4[3]	branch E
QUAD_WW4_S0	branch N
QUAD_EE0[0]	mux
QUAD_EE0[1]	mux
QUAD_EE0[2]	mux
QUAD_EE0[3]	mux
QUAD_EE1[0]	branch W
QUAD_EE1[1]	branch W
QUAD_EE1[2]	branch W
QUAD_EE1[3]	branch W
QUAD_EE2[0]	branch W
QUAD_EE2[1]	branch W
QUAD_EE2[2]	branch W
QUAD_EE2[3]	branch W
QUAD_EE3[0]	branch W
QUAD_EE3[1]	branch W
QUAD_EE3[2]	branch W
QUAD_EE3[3]	branch W
QUAD_EE4[0]	branch W
QUAD_EE4[1]	branch W
QUAD_EE4[2]	branch W
QUAD_EE4[3]	branch W
QUAD_SS0[0]	mux
QUAD_SS0[1]	mux
QUAD_SS0[2]	mux
QUAD_SS0[3]	mux
QUAD_SS1[0]	branch N
QUAD_SS1[1]	branch N
QUAD_SS1[2]	branch N
QUAD_SS1[3]	branch N
QUAD_SS2[0]	branch N
QUAD_SS2[1]	branch N
QUAD_SS2[2]	branch N
QUAD_SS2[3]	branch N
QUAD_SS3[0]	branch N
QUAD_SS3[1]	branch N
QUAD_SS3[2]	branch N
QUAD_SS3[3]	branch N
QUAD_SS4[0]	branch N
QUAD_SS4[1]	branch N
QUAD_SS4[2]	branch N
QUAD_SS4[3]	branch N
QUAD_SS4_N3	branch S
QUAD_SW0[0]	mux
QUAD_SW0[1]	mux
QUAD_SW0[2]	mux
QUAD_SW0[3]	mux
QUAD_SW1[0]	branch E
QUAD_SW1[1]	branch E
QUAD_SW1[2]	branch E
QUAD_SW1[3]	branch E
QUAD_SW2[0]	branch N
QUAD_SW2[1]	branch N
QUAD_SW2[2]	branch N
QUAD_SW2[3]	branch N
QUAD_SW3[0]	branch N
QUAD_SW3[1]	branch N
QUAD_SW3[2]	branch N
QUAD_SW3[3]	branch N
QUAD_SW4[0]	branch E
QUAD_SW4[1]	branch E
QUAD_SW4[2]	branch E
QUAD_SW4[3]	branch E
QUAD_SW4_N3	branch S
QUAD_SE0[0]	mux
QUAD_SE0[1]	mux
QUAD_SE0[2]	mux
QUAD_SE0[3]	mux
QUAD_SE1[0]	branch W
QUAD_SE1[1]	branch W
QUAD_SE1[2]	branch W
QUAD_SE1[3]	branch W
QUAD_SE2[0]	branch N
QUAD_SE2[1]	branch N
QUAD_SE2[2]	branch N
QUAD_SE2[3]	branch N
QUAD_SE3[0]	branch N
QUAD_SE3[1]	branch N
QUAD_SE3[2]	branch N
QUAD_SE3[3]	branch N
QUAD_SE4[0]	branch W
QUAD_SE4[1]	branch W
QUAD_SE4[2]	branch W
QUAD_SE4[3]	branch W
QUAD_NN0[0]	mux
QUAD_NN0[1]	mux
QUAD_NN0[2]	mux
QUAD_NN0[3]	mux
QUAD_NN1[0]	branch S
QUAD_NN1[1]	branch S
QUAD_NN1[2]	branch S
QUAD_NN1[3]	branch S
QUAD_NN2[0]	branch S
QUAD_NN2[1]	branch S
QUAD_NN2[2]	branch S
QUAD_NN2[3]	branch S
QUAD_NN3[0]	branch S
QUAD_NN3[1]	branch S
QUAD_NN3[2]	branch S
QUAD_NN3[3]	branch S
QUAD_NN4[0]	branch S
QUAD_NN4[1]	branch S
QUAD_NN4[2]	branch S
QUAD_NN4[3]	branch S
QUAD_NN4_S0	branch N
QUAD_NW0[0]	mux
QUAD_NW0[1]	mux
QUAD_NW0[2]	mux
QUAD_NW0[3]	mux
QUAD_NW1[0]	branch E
QUAD_NW1[1]	branch E
QUAD_NW1[2]	branch E
QUAD_NW1[3]	branch E
QUAD_NW2[0]	branch S
QUAD_NW2[1]	branch S
QUAD_NW2[2]	branch S
QUAD_NW2[3]	branch S
QUAD_NW3[0]	branch S
QUAD_NW3[1]	branch S
QUAD_NW3[2]	branch S
QUAD_NW3[3]	branch S
QUAD_NW4[0]	branch E
QUAD_NW4[1]	branch E
QUAD_NW4[2]	branch E
QUAD_NW4[3]	branch E
QUAD_NW4_S0	branch N
QUAD_NE0[0]	mux
QUAD_NE0[1]	mux
QUAD_NE0[2]	mux
QUAD_NE0[3]	mux
QUAD_NE1[0]	branch W
QUAD_NE1[1]	branch W
QUAD_NE1[2]	branch W
QUAD_NE1[3]	branch W
QUAD_NE2[0]	branch S
QUAD_NE2[1]	branch S
QUAD_NE2[2]	branch S
QUAD_NE2[3]	branch S
QUAD_NE3[0]	branch S
QUAD_NE3[1]	branch S
QUAD_NE3[2]	branch S
QUAD_NE3[3]	branch S
QUAD_NE4[0]	branch W
QUAD_NE4[1]	branch W
QUAD_NE4[2]	branch W
QUAD_NE4[3]	branch W
LH[0]	multi_branch W
LH[1]	multi_branch W
LH[2]	multi_branch W
LH[3]	multi_branch W
LH[4]	multi_branch W
LH[5]	multi_branch W
LH[6]	multi_branch W
LH[7]	multi_branch W
LH[8]	multi_root
LH[9]	multi_branch E
LH[10]	multi_branch E
LH[11]	multi_branch E
LH[12]	multi_branch E
LH[13]	multi_branch E
LH[14]	multi_branch E
LH[15]	multi_branch E
LH[16]	multi_branch E
LV[0]	multi_branch N
LV[1]	multi_branch N
LV[2]	multi_branch N
LV[3]	multi_branch N
LV[4]	multi_branch N
LV[5]	multi_branch N
LV[6]	multi_branch N
LV[7]	multi_branch N
LV[8]	multi_root
LV[9]	multi_branch S
LV[10]	multi_branch S
LV[11]	multi_branch S
LV[12]	multi_branch S
LV[13]	multi_branch S
LV[14]	multi_branch S
LV[15]	multi_branch S
LV[16]	multi_branch S
IMUX_GFAN[0]	mux
IMUX_GFAN[1]	mux
IMUX_CLK[0]	mux
IMUX_CLK[1]	mux
IMUX_CTRL[0]	mux
IMUX_CTRL[1]	mux
IMUX_BYP[0]	mux
IMUX_BYP[1]	mux
IMUX_BYP[2]	mux
IMUX_BYP[3]	mux
IMUX_BYP[4]	mux
IMUX_BYP[5]	mux
IMUX_BYP[6]	mux
IMUX_BYP[7]	mux
IMUX_BYP_SITE[0]	mux
IMUX_BYP_SITE[1]	mux
IMUX_BYP_SITE[2]	mux
IMUX_BYP_SITE[3]	mux
IMUX_BYP_SITE[4]	mux
IMUX_BYP_SITE[5]	mux
IMUX_BYP_SITE[6]	mux
IMUX_BYP_SITE[7]	mux
IMUX_BYP_BOUNCE[0]	mux
IMUX_BYP_BOUNCE[1]	mux
IMUX_BYP_BOUNCE[2]	mux
IMUX_BYP_BOUNCE[3]	mux
IMUX_BYP_BOUNCE[4]	mux
IMUX_BYP_BOUNCE[5]	mux
IMUX_BYP_BOUNCE[6]	mux
IMUX_BYP_BOUNCE[7]	mux
IMUX_BYP_BOUNCE_N[0]	branch S
IMUX_BYP_BOUNCE_N[1]	branch S
IMUX_BYP_BOUNCE_N[2]	branch S
IMUX_BYP_BOUNCE_N[3]	branch S
IMUX_BYP_BOUNCE_N[4]	branch S
IMUX_BYP_BOUNCE_N[5]	branch S
IMUX_BYP_BOUNCE_N[6]	branch S
IMUX_BYP_BOUNCE_N[7]	branch S
IMUX_BYP_DSP[0]	mux
IMUX_BYP_DSP[1]	mux
IMUX_BYP_DSP[2]	mux
IMUX_BYP_DSP[3]	mux
IMUX_BYP_DSP[4]	mux
IMUX_BYP_DSP[5]	mux
IMUX_BYP_DSP[6]	mux
IMUX_BYP_DSP[7]	mux
IMUX_FAN[0]	mux
IMUX_FAN[1]	mux
IMUX_FAN[2]	mux
IMUX_FAN[3]	mux
IMUX_FAN[4]	mux
IMUX_FAN[5]	mux
IMUX_FAN[6]	mux
IMUX_FAN[7]	mux
IMUX_FAN_SITE[0]	mux
IMUX_FAN_SITE[1]	mux
IMUX_FAN_SITE[2]	mux
IMUX_FAN_SITE[3]	mux
IMUX_FAN_SITE[4]	mux
IMUX_FAN_SITE[5]	mux
IMUX_FAN_SITE[6]	mux
IMUX_FAN_SITE[7]	mux
IMUX_FAN_BOUNCE[0]	mux
IMUX_FAN_BOUNCE[1]	mux
IMUX_FAN_BOUNCE[2]	mux
IMUX_FAN_BOUNCE[3]	mux
IMUX_FAN_BOUNCE[4]	mux
IMUX_FAN_BOUNCE[5]	mux
IMUX_FAN_BOUNCE[6]	mux
IMUX_FAN_BOUNCE[7]	mux
IMUX_FAN_BOUNCE_S[0]	branch N
IMUX_FAN_BOUNCE_S[1]	branch N
IMUX_FAN_BOUNCE_S[2]	branch N
IMUX_FAN_BOUNCE_S[3]	branch N
IMUX_FAN_BOUNCE_S[4]	branch N
IMUX_FAN_BOUNCE_S[5]	branch N
IMUX_FAN_BOUNCE_S[6]	branch N
IMUX_FAN_BOUNCE_S[7]	branch N
IMUX_FAN_DSP[0]	mux
IMUX_FAN_DSP[1]	mux
IMUX_FAN_DSP[2]	mux
IMUX_FAN_DSP[3]	mux
IMUX_FAN_DSP[4]	mux
IMUX_FAN_DSP[5]	mux
IMUX_FAN_DSP[6]	mux
IMUX_FAN_DSP[7]	mux
IMUX_IMUX[0]	mux
IMUX_IMUX[1]	mux
IMUX_IMUX[2]	mux
IMUX_IMUX[3]	mux
IMUX_IMUX[4]	mux
IMUX_IMUX[5]	mux
IMUX_IMUX[6]	mux
IMUX_IMUX[7]	mux
IMUX_IMUX[8]	mux
IMUX_IMUX[9]	mux
IMUX_IMUX[10]	mux
IMUX_IMUX[11]	mux
IMUX_IMUX[12]	mux
IMUX_IMUX[13]	mux
IMUX_IMUX[14]	mux
IMUX_IMUX[15]	mux
IMUX_IMUX[16]	mux
IMUX_IMUX[17]	mux
IMUX_IMUX[18]	mux
IMUX_IMUX[19]	mux
IMUX_IMUX[20]	mux
IMUX_IMUX[21]	mux
IMUX_IMUX[22]	mux
IMUX_IMUX[23]	mux
IMUX_IMUX[24]	mux
IMUX_IMUX[25]	mux
IMUX_IMUX[26]	mux
IMUX_IMUX[27]	mux
IMUX_IMUX[28]	mux
IMUX_IMUX[29]	mux
IMUX_IMUX[30]	mux
IMUX_IMUX[31]	mux
IMUX_IMUX[32]	mux
IMUX_IMUX[33]	mux
IMUX_IMUX[34]	mux
IMUX_IMUX[35]	mux
IMUX_IMUX[36]	mux
IMUX_IMUX[37]	mux
IMUX_IMUX[38]	mux
IMUX_IMUX[39]	mux
IMUX_IMUX[40]	mux
IMUX_IMUX[41]	mux
IMUX_IMUX[42]	mux
IMUX_IMUX[43]	mux
IMUX_IMUX[44]	mux
IMUX_IMUX[45]	mux
IMUX_IMUX[46]	mux
IMUX_IMUX[47]	mux
IMUX_IMUX_DELAY[0]	mux
IMUX_IMUX_DELAY[1]	mux
IMUX_IMUX_DELAY[2]	mux
IMUX_IMUX_DELAY[3]	mux
IMUX_IMUX_DELAY[4]	mux
IMUX_IMUX_DELAY[5]	mux
IMUX_IMUX_DELAY[6]	mux
IMUX_IMUX_DELAY[7]	mux
IMUX_IMUX_DELAY[8]	mux
IMUX_IMUX_DELAY[9]	mux
IMUX_IMUX_DELAY[10]	mux
IMUX_IMUX_DELAY[11]	mux
IMUX_IMUX_DELAY[12]	mux
IMUX_IMUX_DELAY[13]	mux
IMUX_IMUX_DELAY[14]	mux
IMUX_IMUX_DELAY[15]	mux
IMUX_IMUX_DELAY[16]	mux
IMUX_IMUX_DELAY[17]	mux
IMUX_IMUX_DELAY[18]	mux
IMUX_IMUX_DELAY[19]	mux
IMUX_IMUX_DELAY[20]	mux
IMUX_IMUX_DELAY[21]	mux
IMUX_IMUX_DELAY[22]	mux
IMUX_IMUX_DELAY[23]	mux
IMUX_IMUX_DELAY[24]	mux
IMUX_IMUX_DELAY[25]	mux
IMUX_IMUX_DELAY[26]	mux
IMUX_IMUX_DELAY[27]	mux
IMUX_IMUX_DELAY[28]	mux
IMUX_IMUX_DELAY[29]	mux
IMUX_IMUX_DELAY[30]	mux
IMUX_IMUX_DELAY[31]	mux
IMUX_IMUX_DELAY[32]	mux
IMUX_IMUX_DELAY[33]	mux
IMUX_IMUX_DELAY[34]	mux
IMUX_IMUX_DELAY[35]	mux
IMUX_IMUX_DELAY[36]	mux
IMUX_IMUX_DELAY[37]	mux
IMUX_IMUX_DELAY[38]	mux
IMUX_IMUX_DELAY[39]	mux
IMUX_IMUX_DELAY[40]	mux
IMUX_IMUX_DELAY[41]	mux
IMUX_IMUX_DELAY[42]	mux
IMUX_IMUX_DELAY[43]	mux
IMUX_IMUX_DELAY[44]	mux
IMUX_IMUX_DELAY[45]	mux
IMUX_IMUX_DELAY[46]	mux
IMUX_IMUX_DELAY[47]	mux
OUT[0]	bel
OUT[1]	bel
OUT[2]	bel
OUT[3]	bel
OUT[4]	bel
OUT[5]	bel
OUT[6]	bel
OUT[7]	bel
OUT[8]	bel
OUT[9]	bel
OUT[10]	bel
OUT[11]	bel
OUT[12]	bel
OUT[13]	bel
OUT[14]	bel
OUT[15]	bel
OUT[16]	bel
OUT[17]	bel
OUT[18]	bel
OUT[19]	bel
OUT[20]	bel
OUT[21]	bel
OUT[22]	bel
OUT[23]	bel
OUT_BEL[0]	bel
OUT_BEL[1]	bel
OUT_BEL[2]	bel
OUT_BEL[3]	bel
OUT_BEL[4]	bel
OUT_BEL[5]	bel
OUT_BEL[6]	bel
OUT_BEL[7]	bel
OUT_BEL[8]	bel
OUT_BEL[9]	bel
OUT_BEL[10]	bel
OUT_BEL[11]	bel
OUT_BEL[12]	bel
OUT_BEL[13]	bel
OUT_BEL[14]	bel
OUT_BEL[15]	bel
OUT_BEL[16]	bel
OUT_BEL[17]	bel
OUT_BEL[18]	bel
OUT_BEL[19]	bel
OUT_BEL[20]	bel
OUT_BEL[21]	bel
OUT_BEL[22]	bel
OUT_BEL[23]	bel
OUT_TEST[0]	test
OUT_TEST[1]	test
OUT_TEST[2]	test
OUT_TEST[3]	test
OUT_TEST[4]	test
OUT_TEST[5]	test
OUT_TEST[6]	test
OUT_TEST[7]	test
OUT_TEST[8]	test
OUT_TEST[9]	test
OUT_TEST[10]	test
OUT_TEST[11]	test
OUT_TEST[12]	test
OUT_TEST[13]	test
OUT_TEST[14]	test
OUT_TEST[15]	test
OUT_TEST[16]	test
OUT_TEST[17]	test
OUT_TEST[18]	test
OUT_TEST[19]	test
OUT_TEST[20]	test
OUT_TEST[21]	test
OUT_TEST[22]	test
OUT_TEST[23]	test
IMUX_SPEC[0]	test
IMUX_SPEC[1]	test
IMUX_SPEC[2]	test
IMUX_SPEC[3]	test
HCLK_ROW[0]	regional HROW
HCLK_ROW[1]	regional HROW
HCLK_ROW[2]	regional HROW
HCLK_ROW[3]	regional HROW
HCLK_ROW[4]	regional HROW
HCLK_ROW[5]	regional HROW
HCLK_ROW[6]	regional HROW
HCLK_ROW[7]	regional HROW
HCLK_ROW[8]	regional HROW
HCLK_ROW[9]	regional HROW
HCLK_ROW[10]	regional HROW
HCLK_ROW[11]	regional HROW
RCLK_ROW[0]	regional HROW
RCLK_ROW[1]	regional HROW
RCLK_ROW[2]	regional HROW
RCLK_ROW[3]	regional HROW
RCLK_ROW[4]	regional HROW
RCLK_ROW[5]	regional HROW
MGT_ROW[0]	regional HROW
MGT_ROW[1]	regional HROW
MGT_ROW[2]	regional HROW
MGT_ROW[3]	regional HROW
MGT_ROW[4]	regional HROW
MGT_ROW[5]	regional HROW
MGT_ROW[6]	regional HROW
MGT_ROW[7]	regional HROW
MGT_ROW[8]	regional HROW
MGT_ROW[9]	regional HROW
HCLK_BUF[0]	mux
HCLK_BUF[1]	mux
HCLK_BUF[2]	mux
HCLK_BUF[3]	mux
HCLK_BUF[4]	mux
HCLK_BUF[5]	mux
HCLK_BUF[6]	mux
HCLK_BUF[7]	mux
HCLK_BUF[8]	mux
HCLK_BUF[9]	mux
HCLK_BUF[10]	mux
HCLK_BUF[11]	mux
RCLK_BUF[0]	mux
RCLK_BUF[1]	mux
RCLK_BUF[2]	mux
RCLK_BUF[3]	mux
RCLK_BUF[4]	mux
RCLK_BUF[5]	mux
PERF_ROW[0]	branch HCLK_ROW_NEXT
PERF_ROW[1]	branch HCLK_ROW_NEXT
PERF_ROW[2]	branch HCLK_ROW_NEXT
PERF_ROW[3]	branch HCLK_ROW_NEXT
PERF_ROW_OUTER[0]	mux
PERF_ROW_OUTER[1]	mux
PERF_ROW_OUTER[2]	mux
PERF_ROW_OUTER[3]	mux
PERF_BUF[0]	mux
PERF_BUF[1]	mux
PERF_BUF[2]	mux
PERF_BUF[3]	mux
HCLK_IO[0]	regional LEAF_IO
HCLK_IO[1]	regional LEAF_IO
HCLK_IO[2]	regional LEAF_IO
HCLK_IO[3]	regional LEAF_IO
HCLK_IO[4]	regional LEAF_IO
HCLK_IO[5]	regional LEAF_IO
HCLK_IO[6]	regional LEAF_IO
HCLK_IO[7]	regional LEAF_IO
HCLK_IO[8]	regional LEAF_IO
HCLK_IO[9]	regional LEAF_IO
HCLK_IO[10]	regional LEAF_IO
HCLK_IO[11]	regional LEAF_IO
RCLK_IO[0]	regional LEAF_IO
RCLK_IO[1]	regional LEAF_IO
RCLK_IO[2]	regional LEAF_IO
RCLK_IO[3]	regional LEAF_IO
RCLK_IO[4]	regional LEAF_IO
RCLK_IO[5]	regional LEAF_IO
IMUX_IDELAYCTRL_REFCLK	mux
IMUX_BUFIO[0]	mux
IMUX_BUFIO[1]	mux
IMUX_BUFIO[2]	mux
IMUX_BUFIO[3]	mux
IMUX_BUFR[0]	mux
IMUX_BUFR[1]	mux
VRCLK[0]	bel
VRCLK[1]	bel
VRCLK_S[0]	branch IO_N
VRCLK_S[1]	branch IO_N
VRCLK_N[0]	branch IO_S
VRCLK_N[1]	branch IO_S
SIOCLK[0]	bel
SIOCLK[1]	bel
VIOCLK[0]	bel
VIOCLK[1]	bel
VIOCLK_S[0]	branch IO_N
VIOCLK_S[1]	branch IO_N
VIOCLK_N[0]	branch IO_S
VIOCLK_N[1]	branch IO_S
VIOCLK_S_BUF[0]	mux
VIOCLK_S_BUF[1]	mux
VIOCLK_N_BUF[0]	mux
VIOCLK_N_BUF[1]	mux
IOCLK[0]	regional LEAF_IO
IOCLK[1]	regional LEAF_IO
IOCLK[2]	regional LEAF_IO
IOCLK[3]	regional LEAF_IO
IOCLK[4]	regional LEAF_IO
IOCLK[5]	regional LEAF_IO
IOCLK[6]	regional LEAF_IO
IOCLK[7]	regional LEAF_IO
VOCLK[0]	mux
VOCLK[1]	mux
VOCLK_S[0]	branch IO_N
VOCLK_S[1]	branch IO_N
VOCLK_N[0]	branch IO_S
VOCLK_N[1]	branch IO_S
OCLK[0]	regional LEAF_IO
OCLK[1]	regional LEAF_IO
OUT_CLKPAD	bel
IMUX_IOI_ICLK[0]	mux
IMUX_IOI_ICLK[1]	mux
IMUX_IOI_OCLK[0]	mux
IMUX_IOI_OCLK[1]	mux
IMUX_IOI_OCLKDIV[0]	mux
IMUX_IOI_OCLKDIV[1]	mux
IMUX_IOI_OCLKPERF	mux
IMUX_GTX_PERFCLK	mux
GCLK[0]	regional GLOBAL
GCLK[1]	regional GLOBAL
GCLK[2]	regional GLOBAL
GCLK[3]	regional GLOBAL
GCLK[4]	regional GLOBAL
GCLK[5]	regional GLOBAL
GCLK[6]	regional GLOBAL
GCLK[7]	regional GLOBAL
GCLK[8]	regional GLOBAL
GCLK[9]	regional GLOBAL
GCLK[10]	regional GLOBAL
GCLK[11]	regional GLOBAL
GCLK[12]	regional GLOBAL
GCLK[13]	regional GLOBAL
GCLK[14]	regional GLOBAL
GCLK[15]	regional GLOBAL
GCLK[16]	regional GLOBAL
GCLK[17]	regional GLOBAL
GCLK[18]	regional GLOBAL
GCLK[19]	regional GLOBAL
GCLK[20]	regional GLOBAL
GCLK[21]	regional GLOBAL
GCLK[22]	regional GLOBAL
GCLK[23]	regional GLOBAL
GCLK[24]	regional GLOBAL
GCLK[25]	regional GLOBAL
GCLK[26]	regional GLOBAL
GCLK[27]	regional GLOBAL
GCLK[28]	regional GLOBAL
GCLK[29]	regional GLOBAL
GCLK[30]	regional GLOBAL
GCLK[31]	regional GLOBAL
GIOB[0]	regional GLOBAL
GIOB[1]	regional GLOBAL
GIOB[2]	regional GLOBAL
GIOB[3]	regional GLOBAL
GIOB[4]	regional GLOBAL
GIOB[5]	regional GLOBAL
GIOB[6]	regional GLOBAL
GIOB[7]	regional GLOBAL
OUT_BUFG[0]	bel
OUT_BUFG[1]	bel
OUT_BUFG[2]	bel
OUT_BUFG[3]	bel
OUT_BUFG[4]	bel
OUT_BUFG[5]	bel
OUT_BUFG[6]	bel
OUT_BUFG[7]	bel
OUT_BUFG[8]	bel
OUT_BUFG[9]	bel
OUT_BUFG[10]	bel
OUT_BUFG[11]	bel
OUT_BUFG[12]	bel
OUT_BUFG[13]	bel
OUT_BUFG[14]	bel
OUT_BUFG[15]	bel
OUT_BUFG_GFB[0]	mux
OUT_BUFG_GFB[1]	mux
OUT_BUFG_GFB[2]	mux
OUT_BUFG_GFB[3]	mux
OUT_BUFG_GFB[4]	mux
OUT_BUFG_GFB[5]	mux
OUT_BUFG_GFB[6]	mux
OUT_BUFG_GFB[7]	mux
OUT_BUFG_GFB[8]	mux
OUT_BUFG_GFB[9]	mux
OUT_BUFG_GFB[10]	mux
OUT_BUFG_GFB[11]	mux
OUT_BUFG_GFB[12]	mux
OUT_BUFG_GFB[13]	mux
OUT_BUFG_GFB[14]	mux
OUT_BUFG_GFB[15]	mux
IMUX_BUFG_O[0]	mux
IMUX_BUFG_O[1]	mux
IMUX_BUFG_O[2]	mux
IMUX_BUFG_O[3]	mux
IMUX_BUFG_O[4]	mux
IMUX_BUFG_O[5]	mux
IMUX_BUFG_O[6]	mux
IMUX_BUFG_O[7]	mux
IMUX_BUFG_O[8]	mux
IMUX_BUFG_O[9]	mux
IMUX_BUFG_O[10]	mux
IMUX_BUFG_O[11]	mux
IMUX_BUFG_O[12]	mux
IMUX_BUFG_O[13]	mux
IMUX_BUFG_O[14]	mux
IMUX_BUFG_O[15]	mux
IMUX_BUFG_O[16]	mux
IMUX_BUFG_O[17]	mux
IMUX_BUFG_O[18]	mux
IMUX_BUFG_O[19]	mux
IMUX_BUFG_O[20]	mux
IMUX_BUFG_O[21]	mux
IMUX_BUFG_O[22]	mux
IMUX_BUFG_O[23]	mux
IMUX_BUFG_O[24]	mux
IMUX_BUFG_O[25]	mux
IMUX_BUFG_O[26]	mux
IMUX_BUFG_O[27]	mux
IMUX_BUFG_O[28]	mux
IMUX_BUFG_O[29]	mux
IMUX_BUFG_O[30]	mux
IMUX_BUFG_O[31]	mux
IMUX_BUFG_I[0]	branch CLK_PREV
IMUX_BUFG_I[1]	branch CLK_PREV
IMUX_BUFG_I[2]	branch CLK_PREV
IMUX_BUFG_I[3]	branch CLK_PREV
IMUX_BUFG_I[4]	branch CLK_PREV
IMUX_BUFG_I[5]	branch CLK_PREV
IMUX_BUFG_I[6]	branch CLK_PREV
IMUX_BUFG_I[7]	branch CLK_PREV
IMUX_BUFG_I[8]	branch CLK_PREV
IMUX_BUFG_I[9]	branch CLK_PREV
IMUX_BUFG_I[10]	branch CLK_PREV
IMUX_BUFG_I[11]	branch CLK_PREV
IMUX_BUFG_I[12]	branch CLK_PREV
IMUX_BUFG_I[13]	branch CLK_PREV
IMUX_BUFG_I[14]	branch CLK_PREV
IMUX_BUFG_I[15]	branch CLK_PREV
IMUX_BUFG_I[16]	branch CLK_PREV
IMUX_BUFG_I[17]	branch CLK_PREV
IMUX_BUFG_I[18]	branch CLK_PREV
IMUX_BUFG_I[19]	branch CLK_PREV
IMUX_BUFG_I[20]	branch CLK_PREV
IMUX_BUFG_I[21]	branch CLK_PREV
IMUX_BUFG_I[22]	branch CLK_PREV
IMUX_BUFG_I[23]	branch CLK_PREV
IMUX_BUFG_I[24]	branch CLK_PREV
IMUX_BUFG_I[25]	branch CLK_PREV
IMUX_BUFG_I[26]	branch CLK_PREV
IMUX_BUFG_I[27]	branch CLK_PREV
IMUX_BUFG_I[28]	branch CLK_PREV
IMUX_BUFG_I[29]	branch CLK_PREV
IMUX_BUFG_I[30]	branch CLK_PREV
IMUX_BUFG_I[31]	branch CLK_PREV
GCLK_CMT[0]	mux
GCLK_CMT[1]	mux
GCLK_CMT[2]	mux
GCLK_CMT[3]	mux
GCLK_CMT[4]	mux
GCLK_CMT[5]	mux
GCLK_CMT[6]	mux
GCLK_CMT[7]	mux
GCLK_CMT[8]	mux
GCLK_CMT[9]	mux
GCLK_CMT[10]	mux
GCLK_CMT[11]	mux
GCLK_CMT[12]	mux
GCLK_CMT[13]	mux
GCLK_CMT[14]	mux
GCLK_CMT[15]	mux
GCLK_CMT[16]	mux
GCLK_CMT[17]	mux
GCLK_CMT[18]	mux
GCLK_CMT[19]	mux
GCLK_CMT[20]	mux
GCLK_CMT[21]	mux
GCLK_CMT[22]	mux
GCLK_CMT[23]	mux
GCLK_CMT[24]	mux
GCLK_CMT[25]	mux
GCLK_CMT[26]	mux
GCLK_CMT[27]	mux
GCLK_CMT[28]	mux
GCLK_CMT[29]	mux
GCLK_CMT[30]	mux
GCLK_CMT[31]	mux
BUFH_INT_W[0]	mux
BUFH_INT_W[1]	mux
BUFH_INT_E[0]	mux
BUFH_INT_E[1]	mux
GCLK_TEST[0]	mux
GCLK_TEST[1]	mux
GCLK_TEST[2]	mux
GCLK_TEST[3]	mux
GCLK_TEST[4]	mux
GCLK_TEST[5]	mux
GCLK_TEST[6]	mux
GCLK_TEST[7]	mux
GCLK_TEST[8]	mux
GCLK_TEST[9]	mux
GCLK_TEST[10]	mux
GCLK_TEST[11]	mux
GCLK_TEST[12]	mux
GCLK_TEST[13]	mux
GCLK_TEST[14]	mux
GCLK_TEST[15]	mux
GCLK_TEST[16]	mux
GCLK_TEST[17]	mux
GCLK_TEST[18]	mux
GCLK_TEST[19]	mux
GCLK_TEST[20]	mux
GCLK_TEST[21]	mux
GCLK_TEST[22]	mux
GCLK_TEST[23]	mux
GCLK_TEST[24]	mux
GCLK_TEST[25]	mux
GCLK_TEST[26]	mux
GCLK_TEST[27]	mux
GCLK_TEST[28]	mux
GCLK_TEST[29]	mux
GCLK_TEST[30]	mux
GCLK_TEST[31]	mux
GCLK_TEST_IN[0]	mux
GCLK_TEST_IN[1]	mux
GCLK_TEST_IN[2]	mux
GCLK_TEST_IN[3]	mux
GCLK_TEST_IN[4]	mux
GCLK_TEST_IN[5]	mux
GCLK_TEST_IN[6]	mux
GCLK_TEST_IN[7]	mux
GCLK_TEST_IN[8]	mux
GCLK_TEST_IN[9]	mux
GCLK_TEST_IN[10]	mux
GCLK_TEST_IN[11]	mux
GCLK_TEST_IN[12]	mux
GCLK_TEST_IN[13]	mux
GCLK_TEST_IN[14]	mux
GCLK_TEST_IN[15]	mux
GCLK_TEST_IN[16]	mux
GCLK_TEST_IN[17]	mux
GCLK_TEST_IN[18]	mux
GCLK_TEST_IN[19]	mux
GCLK_TEST_IN[20]	mux
GCLK_TEST_IN[21]	mux
GCLK_TEST_IN[22]	mux
GCLK_TEST_IN[23]	mux
GCLK_TEST_IN[24]	mux
GCLK_TEST_IN[25]	mux
GCLK_TEST_IN[26]	mux
GCLK_TEST_IN[27]	mux
GCLK_TEST_IN[28]	mux
GCLK_TEST_IN[29]	mux
GCLK_TEST_IN[30]	mux
GCLK_TEST_IN[31]	mux
BUFH_TEST_W	mux
BUFH_TEST_E	mux
BUFH_TEST_W_IN	mux
BUFH_TEST_E_IN	mux
IMUX_BUFHCE_W[0]	mux
IMUX_BUFHCE_W[1]	mux
IMUX_BUFHCE_W[2]	mux
IMUX_BUFHCE_W[3]	mux
IMUX_BUFHCE_W[4]	mux
IMUX_BUFHCE_W[5]	mux
IMUX_BUFHCE_W[6]	mux
IMUX_BUFHCE_W[7]	mux
IMUX_BUFHCE_W[8]	mux
IMUX_BUFHCE_W[9]	mux
IMUX_BUFHCE_W[10]	mux
IMUX_BUFHCE_W[11]	mux
IMUX_BUFHCE_E[0]	mux
IMUX_BUFHCE_E[1]	mux
IMUX_BUFHCE_E[2]	mux
IMUX_BUFHCE_E[3]	mux
IMUX_BUFHCE_E[4]	mux
IMUX_BUFHCE_E[5]	mux
IMUX_BUFHCE_E[6]	mux
IMUX_BUFHCE_E[7]	mux
IMUX_BUFHCE_E[8]	mux
IMUX_BUFHCE_E[9]	mux
IMUX_BUFHCE_E[10]	mux
IMUX_BUFHCE_E[11]	mux
CCIO_CMT_W[0]	mux
CCIO_CMT_W[1]	mux
CCIO_CMT_W[2]	mux
CCIO_CMT_W[3]	mux
CCIO_CMT_E[0]	mux
CCIO_CMT_E[1]	mux
CCIO_CMT_E[2]	mux
CCIO_CMT_E[3]	mux
MGT_CMT_W[0]	mux
MGT_CMT_W[1]	mux
MGT_CMT_W[2]	mux
MGT_CMT_W[3]	mux
MGT_CMT_W[4]	mux
MGT_CMT_W[5]	mux
MGT_CMT_W[6]	mux
MGT_CMT_W[7]	mux
MGT_CMT_W[8]	mux
MGT_CMT_W[9]	mux
MGT_CMT_E[0]	mux
MGT_CMT_E[1]	mux
MGT_CMT_E[2]	mux
MGT_CMT_E[3]	mux
MGT_CMT_E[4]	mux
MGT_CMT_E[5]	mux
MGT_CMT_E[6]	mux
MGT_CMT_E[7]	mux
MGT_CMT_E[8]	mux
MGT_CMT_E[9]	mux
HCLK_CMT_W[0]	mux
HCLK_CMT_W[1]	mux
HCLK_CMT_W[2]	mux
HCLK_CMT_W[3]	mux
HCLK_CMT_W[4]	mux
HCLK_CMT_W[5]	mux
HCLK_CMT_W[6]	mux
HCLK_CMT_W[7]	mux
HCLK_CMT_W[8]	mux
HCLK_CMT_W[9]	mux
HCLK_CMT_W[10]	mux
HCLK_CMT_W[11]	mux
HCLK_CMT_E[0]	mux
HCLK_CMT_E[1]	mux
HCLK_CMT_E[2]	mux
HCLK_CMT_E[3]	mux
HCLK_CMT_E[4]	mux
HCLK_CMT_E[5]	mux
HCLK_CMT_E[6]	mux
HCLK_CMT_E[7]	mux
HCLK_CMT_E[8]	mux
HCLK_CMT_E[9]	mux
HCLK_CMT_E[10]	mux
HCLK_CMT_E[11]	mux
RCLK_CMT_W[0]	mux
RCLK_CMT_W[1]	mux
RCLK_CMT_W[2]	mux
RCLK_CMT_W[3]	mux
RCLK_CMT_W[4]	mux
RCLK_CMT_W[5]	mux
RCLK_CMT_W[6]	mux
RCLK_CMT_W[7]	mux
RCLK_CMT_W[8]	mux
RCLK_CMT_W[9]	mux
RCLK_CMT_W[10]	mux
RCLK_CMT_W[11]	mux
RCLK_CMT_E[0]	mux
RCLK_CMT_E[1]	mux
RCLK_CMT_E[2]	mux
RCLK_CMT_E[3]	mux
RCLK_CMT_E[4]	mux
RCLK_CMT_E[5]	mux
RCLK_CMT_E[6]	mux
RCLK_CMT_E[7]	mux
RCLK_CMT_E[8]	mux
RCLK_CMT_E[9]	mux
RCLK_CMT_E[10]	mux
RCLK_CMT_E[11]	mux
GIOB_CMT[0]	mux
GIOB_CMT[1]	mux
GIOB_CMT[2]	mux
GIOB_CMT[3]	mux
GIOB_CMT[4]	mux
GIOB_CMT[5]	mux
GIOB_CMT[6]	mux
GIOB_CMT[7]	mux
IMUX_PLL_CLKIN1_HCLK_W[0]	mux
IMUX_PLL_CLKIN1_HCLK_W[1]	mux
IMUX_PLL_CLKIN2_HCLK_W[0]	mux
IMUX_PLL_CLKIN2_HCLK_W[1]	mux
IMUX_PLL_CLKFB_HCLK_W[0]	mux
IMUX_PLL_CLKFB_HCLK_W[1]	mux
IMUX_PLL_CLKIN1_HCLK_E[0]	mux
IMUX_PLL_CLKIN1_HCLK_E[1]	mux
IMUX_PLL_CLKIN2_HCLK_E[0]	mux
IMUX_PLL_CLKIN2_HCLK_E[1]	mux
IMUX_PLL_CLKFB_HCLK_E[0]	mux
IMUX_PLL_CLKFB_HCLK_E[1]	mux
IMUX_PLL_CLKIN1_HCLK[0]	mux
IMUX_PLL_CLKIN1_HCLK[1]	mux
IMUX_PLL_CLKIN2_HCLK[0]	mux
IMUX_PLL_CLKIN2_HCLK[1]	mux
IMUX_PLL_CLKFB_HCLK[0]	mux
IMUX_PLL_CLKFB_HCLK[1]	mux
IMUX_PLL_CLKIN1_IO[0]	mux
IMUX_PLL_CLKIN1_IO[1]	mux
IMUX_PLL_CLKIN2_IO[0]	mux
IMUX_PLL_CLKIN2_IO[1]	mux
IMUX_PLL_CLKFB_IO[0]	mux
IMUX_PLL_CLKFB_IO[1]	mux
IMUX_PLL_CLKIN1_MGT[0]	mux
IMUX_PLL_CLKIN1_MGT[1]	mux
IMUX_PLL_CLKIN2_MGT[0]	mux
IMUX_PLL_CLKIN2_MGT[1]	mux
IMUX_PLL_CLKIN1[0]	mux
IMUX_PLL_CLKIN1[1]	mux
IMUX_PLL_CLKIN2[0]	mux
IMUX_PLL_CLKIN2[1]	mux
IMUX_PLL_CLKFB[0]	mux
IMUX_PLL_CLKFB[1]	mux
OUT_PLL_S[0]	bel
OUT_PLL_S[1]	bel
OUT_PLL_S[2]	bel
OUT_PLL_S[3]	bel
OUT_PLL_S[4]	bel
OUT_PLL_S[5]	bel
OUT_PLL_S[6]	bel
OUT_PLL_S[7]	bel
OUT_PLL_S[8]	bel
OUT_PLL_S[9]	bel
OUT_PLL_S[10]	bel
OUT_PLL_S[11]	bel
OUT_PLL_S[12]	bel
OUT_PLL_S[13]	bel
OUT_PLL_N[0]	bel
OUT_PLL_N[1]	bel
OUT_PLL_N[2]	bel
OUT_PLL_N[3]	bel
OUT_PLL_N[4]	bel
OUT_PLL_N[5]	bel
OUT_PLL_N[6]	bel
OUT_PLL_N[7]	bel
OUT_PLL_N[8]	bel
OUT_PLL_N[9]	bel
OUT_PLL_N[10]	bel
OUT_PLL_N[11]	bel
OUT_PLL_N[12]	bel
OUT_PLL_N[13]	bel
OMUX_PLL_CASC[0]	bel
OMUX_PLL_CASC[1]	bel
OMUX_PLL_PERF_S[0]	bel
OMUX_PLL_PERF_S[1]	bel
OMUX_PLL_PERF_S[2]	bel
OMUX_PLL_PERF_S[3]	bel
OMUX_PLL_PERF_N[0]	bel
OMUX_PLL_PERF_N[1]	bel
OMUX_PLL_PERF_N[2]	bel
OMUX_PLL_PERF_N[3]	bel

Connectors — W

virtex6 wires
Wire	PASS_W	TERM_W
SNG_E1[0]	→ SNG_E0[0]	← SNG_W0[0]
SNG_E1[1]	→ SNG_E0[1]	← SNG_W0[1]
SNG_E1[2]	→ SNG_E0[2]	← SNG_W0[2]
SNG_E1[3]	→ SNG_E0[3]	← SNG_W0[3]
SNG_E1[4]	→ SNG_E0[4]	← SNG_W0[4]
SNG_E1[5]	→ SNG_E0[5]	← SNG_W0[5]
SNG_E1[6]	→ SNG_E0[6]	← SNG_W0[6]
SNG_E1[7]	→ SNG_E0[7]	← SNG_W0[7]
DBL_EE1[0]	→ DBL_EE0[0]	← DBL_WW0[0]
DBL_EE1[1]	→ DBL_EE0[1]	← DBL_WW0[1]
DBL_EE1[2]	→ DBL_EE0[2]	← DBL_WW0[2]
DBL_EE1[3]	→ DBL_EE0[3]	← DBL_WW0[3]
DBL_EE2[0]	→ DBL_EE1[0]	← DBL_WW1[0]
DBL_EE2[1]	→ DBL_EE1[1]	← DBL_WW1[1]
DBL_EE2[2]	→ DBL_EE1[2]	← DBL_WW1[2]
DBL_EE2[3]	→ DBL_EE1[3]	← DBL_WW1[3]
DBL_SE2[0]	→ DBL_SE1[0]	← DBL_SW1[0]
DBL_SE2[1]	→ DBL_SE1[1]	← DBL_SW1[1]
DBL_SE2[2]	→ DBL_SE1[2]	← DBL_SW1[2]
DBL_SE2[3]	→ DBL_SE1[3]	← DBL_SW1[3]
DBL_NE2[0]	→ DBL_NE1[0]	← DBL_NW1[0]
DBL_NE2[1]	→ DBL_NE1[1]	← DBL_NW1[1]
DBL_NE2[2]	→ DBL_NE1[2]	← DBL_NW1[2]
DBL_NE2[3]	→ DBL_NE1[3]	← DBL_NW1[3]
QUAD_EE1[0]	→ QUAD_EE0[0]	← QUAD_WW0[0]
QUAD_EE1[1]	→ QUAD_EE0[1]	← QUAD_WW0[1]
QUAD_EE1[2]	→ QUAD_EE0[2]	← QUAD_WW0[2]
QUAD_EE1[3]	→ QUAD_EE0[3]	← QUAD_WW0[3]
QUAD_EE2[0]	→ QUAD_EE1[0]	← QUAD_WW1[0]
QUAD_EE2[1]	→ QUAD_EE1[1]	← QUAD_WW1[1]
QUAD_EE2[2]	→ QUAD_EE1[2]	← QUAD_WW1[2]
QUAD_EE2[3]	→ QUAD_EE1[3]	← QUAD_WW1[3]
QUAD_EE3[0]	→ QUAD_EE2[0]	← QUAD_WW2[0]
QUAD_EE3[1]	→ QUAD_EE2[1]	← QUAD_WW2[1]
QUAD_EE3[2]	→ QUAD_EE2[2]	← QUAD_WW2[2]
QUAD_EE3[3]	→ QUAD_EE2[3]	← QUAD_WW2[3]
QUAD_EE4[0]	→ QUAD_EE3[0]	← QUAD_WW3[0]
QUAD_EE4[1]	→ QUAD_EE3[1]	← QUAD_WW3[1]
QUAD_EE4[2]	→ QUAD_EE3[2]	← QUAD_WW3[2]
QUAD_EE4[3]	→ QUAD_EE3[3]	← QUAD_WW3[3]
QUAD_SE1[0]	→ QUAD_SE0[0]	← QUAD_SW0[0]
QUAD_SE1[1]	→ QUAD_SE0[1]	← QUAD_SW0[1]
QUAD_SE1[2]	→ QUAD_SE0[2]	← QUAD_SW0[2]
QUAD_SE1[3]	→ QUAD_SE0[3]	← QUAD_SW0[3]
QUAD_SE4[0]	→ QUAD_SE3[0]	← QUAD_SW3[0]
QUAD_SE4[1]	→ QUAD_SE3[1]	← QUAD_SW3[1]
QUAD_SE4[2]	→ QUAD_SE3[2]	← QUAD_SW3[2]
QUAD_SE4[3]	→ QUAD_SE3[3]	← QUAD_SW3[3]
QUAD_NE1[0]	→ QUAD_NE0[0]	← QUAD_NW0[0]
QUAD_NE1[1]	→ QUAD_NE0[1]	← QUAD_NW0[1]
QUAD_NE1[2]	→ QUAD_NE0[2]	← QUAD_NW0[2]
QUAD_NE1[3]	→ QUAD_NE0[3]	← QUAD_NW0[3]
QUAD_NE4[0]	→ QUAD_NE3[0]	← QUAD_NW3[0]
QUAD_NE4[1]	→ QUAD_NE3[1]	← QUAD_NW3[1]
QUAD_NE4[2]	→ QUAD_NE3[2]	← QUAD_NW3[2]
QUAD_NE4[3]	→ QUAD_NE3[3]	← QUAD_NW3[3]
LH[0]	→ LH[1]	← LH[15]
LH[1]	→ LH[2]	← LH[14]
LH[2]	→ LH[3]	← LH[13]
LH[3]	→ LH[4]	← LH[12]
LH[4]	→ LH[5]	← LH[11]
LH[5]	→ LH[6]	← LH[10]
LH[6]	→ LH[7]	← LH[9]
LH[7]	→ LH[8]	← LH[8]

Connectors — E

virtex6 wires
Wire	PASS_E	TERM_E
SNG_W1[0]	→ SNG_W0[0]	← SNG_E0[0]
SNG_W1[1]	→ SNG_W0[1]	← SNG_E0[1]
SNG_W1[2]	→ SNG_W0[2]	← SNG_E0[2]
SNG_W1[3]	→ SNG_W0[3]	← SNG_E0[3]
SNG_W1[4]	→ SNG_W0[4]	← SNG_E0[4]
SNG_W1[5]	→ SNG_W0[5]	← SNG_E0[5]
SNG_W1[6]	→ SNG_W0[6]	← SNG_E0[6]
SNG_W1[7]	→ SNG_W0[7]	← SNG_E0[7]
DBL_WW1[0]	→ DBL_WW0[0]	← DBL_EE0[0]
DBL_WW1[1]	→ DBL_WW0[1]	← DBL_EE0[1]
DBL_WW1[2]	→ DBL_WW0[2]	← DBL_EE0[2]
DBL_WW1[3]	→ DBL_WW0[3]	← DBL_EE0[3]
DBL_WW2[0]	→ DBL_WW1[0]	← DBL_EE1[0]
DBL_WW2[1]	→ DBL_WW1[1]	← DBL_EE1[1]
DBL_WW2[2]	→ DBL_WW1[2]	← DBL_EE1[2]
DBL_WW2[3]	→ DBL_WW1[3]	← DBL_EE1[3]
DBL_SW2[0]	→ DBL_SW1[0]	← DBL_SE1[0]
DBL_SW2[1]	→ DBL_SW1[1]	← DBL_SE1[1]
DBL_SW2[2]	→ DBL_SW1[2]	← DBL_SE1[2]
DBL_SW2[3]	→ DBL_SW1[3]	← DBL_SE1[3]
DBL_NW2[0]	→ DBL_NW1[0]	← DBL_NE1[0]
DBL_NW2[1]	→ DBL_NW1[1]	← DBL_NE1[1]
DBL_NW2[2]	→ DBL_NW1[2]	← DBL_NE1[2]
DBL_NW2[3]	→ DBL_NW1[3]	← DBL_NE1[3]
QUAD_WW1[0]	→ QUAD_WW0[0]	← QUAD_EE0[0]
QUAD_WW1[1]	→ QUAD_WW0[1]	← QUAD_EE0[1]
QUAD_WW1[2]	→ QUAD_WW0[2]	← QUAD_EE0[2]
QUAD_WW1[3]	→ QUAD_WW0[3]	← QUAD_EE0[3]
QUAD_WW2[0]	→ QUAD_WW1[0]	← QUAD_EE1[0]
QUAD_WW2[1]	→ QUAD_WW1[1]	← QUAD_EE1[1]
QUAD_WW2[2]	→ QUAD_WW1[2]	← QUAD_EE1[2]
QUAD_WW2[3]	→ QUAD_WW1[3]	← QUAD_EE1[3]
QUAD_WW3[0]	→ QUAD_WW2[0]	← QUAD_EE2[0]
QUAD_WW3[1]	→ QUAD_WW2[1]	← QUAD_EE2[1]
QUAD_WW3[2]	→ QUAD_WW2[2]	← QUAD_EE2[2]
QUAD_WW3[3]	→ QUAD_WW2[3]	← QUAD_EE2[3]
QUAD_WW4[0]	→ QUAD_WW3[0]	← QUAD_EE3[0]
QUAD_WW4[1]	→ QUAD_WW3[1]	← QUAD_EE3[1]
QUAD_WW4[2]	→ QUAD_WW3[2]	← QUAD_EE3[2]
QUAD_WW4[3]	→ QUAD_WW3[3]	← QUAD_EE3[3]
QUAD_SW1[0]	→ QUAD_SW0[0]	← QUAD_SE0[0]
QUAD_SW1[1]	→ QUAD_SW0[1]	← QUAD_SE0[1]
QUAD_SW1[2]	→ QUAD_SW0[2]	← QUAD_SE0[2]
QUAD_SW1[3]	→ QUAD_SW0[3]	← QUAD_SE0[3]
QUAD_SW4[0]	→ QUAD_SW3[0]	← QUAD_SE3[0]
QUAD_SW4[1]	→ QUAD_SW3[1]	← QUAD_SE3[1]
QUAD_SW4[2]	→ QUAD_SW3[2]	← QUAD_SE3[2]
QUAD_SW4[3]	→ QUAD_SW3[3]	← QUAD_SE3[3]
QUAD_NW1[0]	→ QUAD_NW0[0]	← QUAD_NE0[0]
QUAD_NW1[1]	→ QUAD_NW0[1]	← QUAD_NE0[1]
QUAD_NW1[2]	→ QUAD_NW0[2]	← QUAD_NE0[2]
QUAD_NW1[3]	→ QUAD_NW0[3]	← QUAD_NE0[3]
QUAD_NW4[0]	→ QUAD_NW3[0]	← QUAD_NE3[0]
QUAD_NW4[1]	→ QUAD_NW3[1]	← QUAD_NE3[1]
QUAD_NW4[2]	→ QUAD_NW3[2]	← QUAD_NE3[2]
QUAD_NW4[3]	→ QUAD_NW3[3]	← QUAD_NE3[3]
LH[9]	→ LH[8]	← LH[8]
LH[10]	→ LH[9]	← LH[7]
LH[11]	→ LH[10]	← LH[6]
LH[12]	→ LH[11]	← LH[5]
LH[13]	→ LH[12]	← LH[4]
LH[14]	→ LH[13]	← LH[3]
LH[15]	→ LH[14]	← LH[2]
LH[16]	→ LH[15]	← LH[1]

Connectors — S

virtex6 wires
Wire	PASS_S	TERM_S	TERM_S_HOLE
SNG_W0[4]	→ SNG_W0_S4	← SNG_W0_N3	-
SNG_W1_N3	→ SNG_W1[3]	← SNG_W1[4]	-
SNG_E0[4]	→ SNG_E0_S4	← SNG_E0_N3	-
SNG_E1_N7	→ SNG_E1[7]	← SNG_E1[0]	-
SNG_S0[4]	→ SNG_S0_S4	-	-
SNG_S1_N7	→ SNG_S1[7]	-	-
SNG_N1[0]	→ SNG_N0[0]	← SNG_S0[7]	-
SNG_N1[1]	→ SNG_N0[1]	← SNG_S0[6]	-
SNG_N1[2]	→ SNG_N0[2]	← SNG_S0[5]	-
SNG_N1[3]	→ SNG_N0[3]	-	-
SNG_N1[4]	→ SNG_N0[4]	← SNG_S0[3]	-
SNG_N1[5]	→ SNG_N0[5]	← SNG_S0[2]	-
SNG_N1[6]	→ SNG_N0[6]	← SNG_S0[1]	-
SNG_N1[7]	→ SNG_N0[7]	← SNG_S0[0]	-
DBL_WW2_N3	→ DBL_WW2[3]	-	-
DBL_SS2_N3	→ DBL_SS2[3]	-	-
DBL_SW2_N3	→ DBL_SW2[3]	-	-
DBL_NN1[0]	→ DBL_NN0[0]	← DBL_SS0[3]	-
DBL_NN1[1]	→ DBL_NN0[1]	← DBL_SS0[2]	-
DBL_NN1[2]	→ DBL_NN0[2]	← DBL_SS0[1]	-
DBL_NN1[3]	→ DBL_NN0[3]	← DBL_SS0[0]	-
DBL_NN2[0]	→ DBL_NN1[0]	← DBL_SS1[3]	-
DBL_NN2[1]	→ DBL_NN1[1]	← DBL_SS1[2]	-
DBL_NN2[2]	→ DBL_NN1[2]	← DBL_SS1[1]	-
DBL_NN2[3]	→ DBL_NN1[3]	← DBL_SS1[0]	-
DBL_NW1[0]	→ DBL_NW0[0]	← DBL_SW0[3]	-
DBL_NW1[1]	→ DBL_NW0[1]	← DBL_SW0[2]	-
DBL_NW1[2]	→ DBL_NW0[2]	← DBL_SW0[1]	-
DBL_NW1[3]	→ DBL_NW0[3]	← DBL_SW0[0]	-
DBL_NE1[0]	→ DBL_NE0[0]	← DBL_SE0[3]	-
DBL_NE1[1]	→ DBL_NE0[1]	← DBL_SE0[2]	-
DBL_NE1[2]	→ DBL_NE0[2]	← DBL_SE0[1]	-
DBL_NE1[3]	→ DBL_NE0[3]	← DBL_SE0[0]	-
QUAD_SS4_N3	→ QUAD_SS4[3]	-	-
QUAD_SW4_N3	→ QUAD_SW4[3]	← QUAD_NW4[0]	-
QUAD_NN1[0]	→ QUAD_NN0[0]	← QUAD_SS0[3]	-
QUAD_NN1[1]	→ QUAD_NN0[1]	← QUAD_SS0[2]	-
QUAD_NN1[2]	→ QUAD_NN0[2]	← QUAD_SS0[1]	-
QUAD_NN1[3]	→ QUAD_NN0[3]	← QUAD_SS0[0]	-
QUAD_NN2[0]	→ QUAD_NN1[0]	← QUAD_SS1[3]	-
QUAD_NN2[1]	→ QUAD_NN1[1]	← QUAD_SS1[2]	-
QUAD_NN2[2]	→ QUAD_NN1[2]	← QUAD_SS1[1]	-
QUAD_NN2[3]	→ QUAD_NN1[3]	← QUAD_SS1[0]	-
QUAD_NN3[0]	→ QUAD_NN2[0]	← QUAD_SS2[3]	-
QUAD_NN3[1]	→ QUAD_NN2[1]	← QUAD_SS2[2]	-
QUAD_NN3[2]	→ QUAD_NN2[2]	← QUAD_SS2[1]	-
QUAD_NN3[3]	→ QUAD_NN2[3]	← QUAD_SS2[0]	-
QUAD_NN4[0]	→ QUAD_NN3[0]	← QUAD_SS3[3]	-
QUAD_NN4[1]	→ QUAD_NN3[1]	← QUAD_SS3[2]	-
QUAD_NN4[2]	→ QUAD_NN3[2]	← QUAD_SS3[1]	-
QUAD_NN4[3]	→ QUAD_NN3[3]	← QUAD_SS3[0]	-
QUAD_NW2[0]	→ QUAD_NW1[0]	← QUAD_SW1[3]	-
QUAD_NW2[1]	→ QUAD_NW1[1]	← QUAD_SW1[2]	-
QUAD_NW2[2]	→ QUAD_NW1[2]	← QUAD_SW1[1]	-
QUAD_NW2[3]	→ QUAD_NW1[3]	← QUAD_SW1[0]	-
QUAD_NW3[0]	→ QUAD_NW2[0]	← QUAD_SW2[3]	-
QUAD_NW3[1]	→ QUAD_NW2[1]	← QUAD_SW2[2]	-
QUAD_NW3[2]	→ QUAD_NW2[2]	← QUAD_SW2[1]	-
QUAD_NW3[3]	→ QUAD_NW2[3]	← QUAD_SW2[0]	-
QUAD_NE2[0]	→ QUAD_NE1[0]	← QUAD_SE1[3]	-
QUAD_NE2[1]	→ QUAD_NE1[1]	← QUAD_SE1[2]	-
QUAD_NE2[2]	→ QUAD_NE1[2]	← QUAD_SE1[1]	-
QUAD_NE2[3]	→ QUAD_NE1[3]	← QUAD_SE1[0]	-
QUAD_NE3[0]	→ QUAD_NE2[0]	← QUAD_SE2[3]	-
QUAD_NE3[1]	→ QUAD_NE2[1]	← QUAD_SE2[2]	-
QUAD_NE3[2]	→ QUAD_NE2[2]	← QUAD_SE2[1]	-
QUAD_NE3[3]	→ QUAD_NE2[3]	← QUAD_SE2[0]	-
LV[9]	→ LV[8]	← LV[8]	[BLACKHOLE]
LV[10]	→ LV[9]	← LV[7]	[BLACKHOLE]
LV[11]	→ LV[10]	← LV[6]	[BLACKHOLE]
LV[12]	→ LV[11]	← LV[5]	[BLACKHOLE]
LV[13]	→ LV[12]	← LV[4]	[BLACKHOLE]
LV[14]	→ LV[13]	← LV[3]	[BLACKHOLE]
LV[15]	→ LV[14]	← LV[2]	[BLACKHOLE]
LV[16]	→ LV[15]	← LV[1]	[BLACKHOLE]
IMUX_BYP_BOUNCE_N[0]	→ IMUX_BYP_BOUNCE[0]	-	-
IMUX_BYP_BOUNCE_N[1]	→ IMUX_BYP_BOUNCE[1]	-	-
IMUX_BYP_BOUNCE_N[2]	→ IMUX_BYP_BOUNCE[2]	← IMUX_FAN_BOUNCE[6]	-
IMUX_BYP_BOUNCE_N[3]	→ IMUX_BYP_BOUNCE[3]	← IMUX_FAN_BOUNCE[2]	-
IMUX_BYP_BOUNCE_N[4]	→ IMUX_BYP_BOUNCE[4]	-	-
IMUX_BYP_BOUNCE_N[5]	→ IMUX_BYP_BOUNCE[5]	-	-
IMUX_BYP_BOUNCE_N[6]	→ IMUX_BYP_BOUNCE[6]	← IMUX_FAN_BOUNCE[4]	-
IMUX_BYP_BOUNCE_N[7]	→ IMUX_BYP_BOUNCE[7]	← IMUX_FAN_BOUNCE[0]	-

Connectors — N

virtex6 wires
Wire	PASS_N	TERM_N	TERM_N_HOLE
SNG_W0[3]	→ SNG_W0_N3	← SNG_W0_S4	-
SNG_W1_S4	→ SNG_W1[4]	← SNG_W1[3]	-
SNG_E0[3]	→ SNG_E0_N3	← SNG_E0_S4	-
SNG_E1_S0	→ SNG_E1[0]	← SNG_E1[7]	-
SNG_S1[0]	→ SNG_S0[0]	← SNG_N0[7]	-
SNG_S1[1]	→ SNG_S0[1]	← SNG_N0[6]	-
SNG_S1[2]	→ SNG_S0[2]	← SNG_N0[5]	-
SNG_S1[3]	→ SNG_S0[3]	← SNG_N0[4]	-
SNG_S1[4]	→ SNG_S0[4]	-	-
SNG_S1[5]	→ SNG_S0[5]	← SNG_N0[2]	-
SNG_S1[6]	→ SNG_S0[6]	← SNG_N0[1]	-
SNG_S1[7]	→ SNG_S0[7]	← SNG_N0[0]	-
SNG_N0[3]	→ SNG_N0_N3	-	-
SNG_N1_S0	→ SNG_N1[0]	-	-
DBL_SS1[0]	→ DBL_SS0[0]	← DBL_NN0[3]	-
DBL_SS1[1]	→ DBL_SS0[1]	← DBL_NN0[2]	-
DBL_SS1[2]	→ DBL_SS0[2]	← DBL_NN0[1]	-
DBL_SS1[3]	→ DBL_SS0[3]	← DBL_NN0[0]	-
DBL_SS2[0]	→ DBL_SS1[0]	← DBL_NN1[3]	-
DBL_SS2[1]	→ DBL_SS1[1]	← DBL_NN1[2]	-
DBL_SS2[2]	→ DBL_SS1[2]	← DBL_NN1[1]	-
DBL_SS2[3]	→ DBL_SS1[3]	← DBL_NN1[0]	-
DBL_SW1[0]	→ DBL_SW0[0]	← DBL_NW0[3]	-
DBL_SW1[1]	→ DBL_SW0[1]	← DBL_NW0[2]	-
DBL_SW1[2]	→ DBL_SW0[2]	← DBL_NW0[1]	-
DBL_SW1[3]	→ DBL_SW0[3]	← DBL_NW0[0]	-
DBL_SE1[0]	→ DBL_SE0[0]	← DBL_NE0[3]	-
DBL_SE1[1]	→ DBL_SE0[1]	← DBL_NE0[2]	-
DBL_SE1[2]	→ DBL_SE0[2]	← DBL_NE0[1]	-
DBL_SE1[3]	→ DBL_SE0[3]	← DBL_NE0[0]	-
DBL_NN2_S0	→ DBL_NN2[0]	-	-
DBL_NW2_S0	→ DBL_NW2[0]	-	-
DBL_NE2_S0	→ DBL_NE2[0]	-	-
QUAD_WW4_S0	→ QUAD_WW4[0]	-	-
QUAD_SS1[0]	→ QUAD_SS0[0]	← QUAD_NN0[3]	-
QUAD_SS1[1]	→ QUAD_SS0[1]	← QUAD_NN0[2]	-
QUAD_SS1[2]	→ QUAD_SS0[2]	← QUAD_NN0[1]	-
QUAD_SS1[3]	→ QUAD_SS0[3]	← QUAD_NN0[0]	-
QUAD_SS2[0]	→ QUAD_SS1[0]	← QUAD_NN1[3]	-
QUAD_SS2[1]	→ QUAD_SS1[1]	← QUAD_NN1[2]	-
QUAD_SS2[2]	→ QUAD_SS1[2]	← QUAD_NN1[1]	-
QUAD_SS2[3]	→ QUAD_SS1[3]	← QUAD_NN1[0]	-
QUAD_SS3[0]	→ QUAD_SS2[0]	← QUAD_NN2[3]	-
QUAD_SS3[1]	→ QUAD_SS2[1]	← QUAD_NN2[2]	-
QUAD_SS3[2]	→ QUAD_SS2[2]	← QUAD_NN2[1]	-
QUAD_SS3[3]	→ QUAD_SS2[3]	← QUAD_NN2[0]	-
QUAD_SS4[0]	→ QUAD_SS3[0]	← QUAD_NN3[3]	-
QUAD_SS4[1]	→ QUAD_SS3[1]	← QUAD_NN3[2]	-
QUAD_SS4[2]	→ QUAD_SS3[2]	← QUAD_NN3[1]	-
QUAD_SS4[3]	→ QUAD_SS3[3]	← QUAD_NN3[0]	-
QUAD_SW2[0]	→ QUAD_SW1[0]	← QUAD_NW1[3]	-
QUAD_SW2[1]	→ QUAD_SW1[1]	← QUAD_NW1[2]	-
QUAD_SW2[2]	→ QUAD_SW1[2]	← QUAD_NW1[1]	-
QUAD_SW2[3]	→ QUAD_SW1[3]	← QUAD_NW1[0]	-
QUAD_SW3[0]	→ QUAD_SW2[0]	← QUAD_NW2[3]	-
QUAD_SW3[1]	→ QUAD_SW2[1]	← QUAD_NW2[2]	-
QUAD_SW3[2]	→ QUAD_SW2[2]	← QUAD_NW2[1]	-
QUAD_SW3[3]	→ QUAD_SW2[3]	← QUAD_NW2[0]	-
QUAD_SE2[0]	→ QUAD_SE1[0]	← QUAD_NE1[3]	-
QUAD_SE2[1]	→ QUAD_SE1[1]	← QUAD_NE1[2]	-
QUAD_SE2[2]	→ QUAD_SE1[2]	← QUAD_NE1[1]	-
QUAD_SE2[3]	→ QUAD_SE1[3]	← QUAD_NE1[0]	-
QUAD_SE3[0]	→ QUAD_SE2[0]	← QUAD_NE2[3]	-
QUAD_SE3[1]	→ QUAD_SE2[1]	← QUAD_NE2[2]	-
QUAD_SE3[2]	→ QUAD_SE2[2]	← QUAD_NE2[1]	-
QUAD_SE3[3]	→ QUAD_SE2[3]	← QUAD_NE2[0]	-
QUAD_NN4_S0	→ QUAD_NN4[0]	-	-
QUAD_NW4_S0	→ QUAD_NW4[0]	-	-
LV[0]	→ LV[1]	← LV[15]	[BLACKHOLE]
LV[1]	→ LV[2]	← LV[14]	[BLACKHOLE]
LV[2]	→ LV[3]	← LV[13]	[BLACKHOLE]
LV[3]	→ LV[4]	← LV[12]	[BLACKHOLE]
LV[4]	→ LV[5]	← LV[11]	[BLACKHOLE]
LV[5]	→ LV[6]	← LV[10]	[BLACKHOLE]
LV[6]	→ LV[7]	← LV[9]	[BLACKHOLE]
LV[7]	→ LV[8]	← LV[8]	[BLACKHOLE]
IMUX_FAN_BOUNCE_S[0]	→ IMUX_FAN_BOUNCE[0]	← IMUX_BYP_BOUNCE[7]	-
IMUX_FAN_BOUNCE_S[1]	→ IMUX_FAN_BOUNCE[1]	-	-
IMUX_FAN_BOUNCE_S[2]	→ IMUX_FAN_BOUNCE[2]	← IMUX_BYP_BOUNCE[3]	-
IMUX_FAN_BOUNCE_S[3]	→ IMUX_FAN_BOUNCE[3]	-	-
IMUX_FAN_BOUNCE_S[4]	→ IMUX_FAN_BOUNCE[4]	← IMUX_BYP_BOUNCE[6]	-
IMUX_FAN_BOUNCE_S[5]	→ IMUX_FAN_BOUNCE[5]	-	-
IMUX_FAN_BOUNCE_S[6]	→ IMUX_FAN_BOUNCE[6]	← IMUX_BYP_BOUNCE[2]	-
IMUX_FAN_BOUNCE_S[7]	→ IMUX_FAN_BOUNCE[7]	-	-

Connectors — IO_S

virtex6 wires
Wire	IO_S
VRCLK_N[0]	→ VRCLK[0]
VRCLK_N[1]	→ VRCLK[1]
VIOCLK_N[0]	→ VIOCLK[0]
VIOCLK_N[1]	→ VIOCLK[1]
VOCLK_N[0]	→ VOCLK[0]
VOCLK_N[1]	→ VOCLK[1]

Connectors — IO_N

virtex6 wires
Wire	IO_N
VRCLK_S[0]	→ VRCLK[0]
VRCLK_S[1]	→ VRCLK[1]
VIOCLK_S[0]	→ VIOCLK[0]
VIOCLK_S[1]	→ VIOCLK[1]
VOCLK_S[0]	→ VOCLK[0]
VOCLK_S[1]	→ VOCLK[1]

Connectors — CLK_PREV

virtex6 wires
Wire	CLK_PREV
IMUX_BUFG_I[0]	→ IMUX_BUFG_O[0]
IMUX_BUFG_I[1]	→ IMUX_BUFG_O[1]
IMUX_BUFG_I[2]	→ IMUX_BUFG_O[2]
IMUX_BUFG_I[3]	→ IMUX_BUFG_O[3]
IMUX_BUFG_I[4]	→ IMUX_BUFG_O[4]
IMUX_BUFG_I[5]	→ IMUX_BUFG_O[5]
IMUX_BUFG_I[6]	→ IMUX_BUFG_O[6]
IMUX_BUFG_I[7]	→ IMUX_BUFG_O[7]
IMUX_BUFG_I[8]	→ IMUX_BUFG_O[8]
IMUX_BUFG_I[9]	→ IMUX_BUFG_O[9]
IMUX_BUFG_I[10]	→ IMUX_BUFG_O[10]
IMUX_BUFG_I[11]	→ IMUX_BUFG_O[11]
IMUX_BUFG_I[12]	→ IMUX_BUFG_O[12]
IMUX_BUFG_I[13]	→ IMUX_BUFG_O[13]
IMUX_BUFG_I[14]	→ IMUX_BUFG_O[14]
IMUX_BUFG_I[15]	→ IMUX_BUFG_O[15]
IMUX_BUFG_I[16]	→ IMUX_BUFG_O[16]
IMUX_BUFG_I[17]	→ IMUX_BUFG_O[17]
IMUX_BUFG_I[18]	→ IMUX_BUFG_O[18]
IMUX_BUFG_I[19]	→ IMUX_BUFG_O[19]
IMUX_BUFG_I[20]	→ IMUX_BUFG_O[20]
IMUX_BUFG_I[21]	→ IMUX_BUFG_O[21]
IMUX_BUFG_I[22]	→ IMUX_BUFG_O[22]
IMUX_BUFG_I[23]	→ IMUX_BUFG_O[23]
IMUX_BUFG_I[24]	→ IMUX_BUFG_O[24]
IMUX_BUFG_I[25]	→ IMUX_BUFG_O[25]
IMUX_BUFG_I[26]	→ IMUX_BUFG_O[26]
IMUX_BUFG_I[27]	→ IMUX_BUFG_O[27]
IMUX_BUFG_I[28]	→ IMUX_BUFG_O[28]
IMUX_BUFG_I[29]	→ IMUX_BUFG_O[29]
IMUX_BUFG_I[30]	→ IMUX_BUFG_O[30]
IMUX_BUFG_I[31]	→ IMUX_BUFG_O[31]

Connectors — CLK_NEXT

virtex6 wires
Wire	CLK_NEXT

Connectors — BEL_S

virtex6 wires
Wire

Connectors — BEL_N

virtex6 wires
Wire

Connectors — CMT_PREV

virtex6 wires
Wire

Connectors — CMT_NEXT

virtex6 wires
Wire

Connectors — HCLK_ROW_PREV

virtex6 wires
Wire	HCLK_ROW_PREV

Connectors — HCLK_ROW_NEXT

virtex6 wires
Wire	HCLK_ROW_NEXT	HCLK_ROW_NEXT_PASS
PERF_ROW[0]	→ PERF_ROW_OUTER[0]	→ PERF_ROW[0]
PERF_ROW[1]	→ PERF_ROW_OUTER[1]	→ PERF_ROW[1]
PERF_ROW[2]	→ PERF_ROW_OUTER[2]	→ PERF_ROW[2]
PERF_ROW[3]	→ PERF_ROW_OUTER[3]	→ PERF_ROW[3]

Tile INT

Cells: 1

Switchbox INT

virtex6 INT switchbox INT permanent buffers
Destination	Source
IMUX_BYP_SITE[0]	IMUX_BYP[0]
IMUX_BYP_SITE[1]	IMUX_BYP[1]
IMUX_BYP_SITE[2]	IMUX_BYP[2]
IMUX_BYP_SITE[3]	IMUX_BYP[3]
IMUX_BYP_SITE[4]	IMUX_BYP[4]
IMUX_BYP_SITE[5]	IMUX_BYP[5]
IMUX_BYP_SITE[6]	IMUX_BYP[6]
IMUX_BYP_SITE[7]	IMUX_BYP[7]
IMUX_BYP_BOUNCE[0]	IMUX_BYP[0]
IMUX_BYP_BOUNCE[1]	IMUX_BYP[1]
IMUX_BYP_BOUNCE[2]	IMUX_BYP[2]
IMUX_BYP_BOUNCE[3]	IMUX_BYP[3]
IMUX_BYP_BOUNCE[4]	IMUX_BYP[4]
IMUX_BYP_BOUNCE[5]	IMUX_BYP[5]
IMUX_BYP_BOUNCE[6]	IMUX_BYP[6]
IMUX_BYP_BOUNCE[7]	IMUX_BYP[7]
IMUX_FAN_SITE[0]	IMUX_FAN[0]
IMUX_FAN_SITE[1]	IMUX_FAN[1]
IMUX_FAN_SITE[2]	IMUX_FAN[2]
IMUX_FAN_SITE[3]	IMUX_FAN[3]
IMUX_FAN_SITE[4]	IMUX_FAN[4]
IMUX_FAN_SITE[5]	IMUX_FAN[5]
IMUX_FAN_SITE[6]	IMUX_FAN[6]
IMUX_FAN_SITE[7]	IMUX_FAN[7]
IMUX_FAN_BOUNCE[0]	IMUX_FAN[0]
IMUX_FAN_BOUNCE[1]	IMUX_FAN[1]
IMUX_FAN_BOUNCE[2]	IMUX_FAN[2]
IMUX_FAN_BOUNCE[3]	IMUX_FAN[3]
IMUX_FAN_BOUNCE[4]	IMUX_FAN[4]
IMUX_FAN_BOUNCE[5]	IMUX_FAN[5]
IMUX_FAN_BOUNCE[6]	IMUX_FAN[6]
IMUX_FAN_BOUNCE[7]	IMUX_FAN[7]

virtex6 INT switchbox INT muxes SNG_W0_N3
Bits									Destination
MAIN[10][12]	MAIN[11][12]	MAIN[4][12]	MAIN[12][12]	MAIN[12][14]	MAIN[11][13]	MAIN[5][13]	MAIN[12][13]	MAIN[11][14]	SNG_W0_N3
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[0]
0	0	0	1	0	0	0	1	0	SNG_S0_S4
0	0	0	1	0	0	1	0	0	OUT[22]
0	0	0	1	0	1	0	0	0	QUAD_SW4[0]
0	0	0	1	1	0	0	0	0	QUAD_WW4[1]
0	0	1	0	0	0	0	0	1	SNG_W1[5]
0	0	1	0	0	0	0	1	0	SNG_S1[0]
0	0	1	0	0	0	1	0	0	OUT[8]
0	0	1	0	0	1	0	0	0	QUAD_SS4[0]
0	0	1	0	1	0	0	0	0	QUAD_NW4[1]
0	1	0	0	0	0	0	0	1	OUT[12]
0	1	0	0	0	0	0	1	0	OUT[4]
0	1	0	0	0	0	1	0	0	DBL_WW2[0]
0	1	0	0	0	1	0	0	0	DBL_SS2[0]
0	1	0	0	1	0	0	0	0	DBL_NN2[1]
1	0	0	0	0	0	0	0	1	OUT[0]
1	0	0	0	0	0	0	1	0	OUT[18]
1	0	0	0	0	0	1	0	0	DBL_SW2[0]
1	0	0	0	0	1	0	0	0	DBL_SE2[0]
1	0	0	0	1	0	0	0	0	DBL_NW2[1]

virtex6 INT switchbox INT muxes SNG_W0_S4
Bits									Destination
MAIN[11][51]	MAIN[10][51]	MAIN[13][51]	MAIN[12][51]	MAIN[4][50]	MAIN[10][50]	MAIN[5][49]	MAIN[5][51]	MAIN[10][49]	SNG_W0_S4
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[2]
0	0	0	1	0	0	0	1	0	SNG_N1[7]
0	0	0	1	0	0	1	0	0	QUAD_WW4[3]
0	0	0	1	0	1	0	0	0	QUAD_NE4[3]
0	0	0	1	1	0	0	0	0	OUT[17]
0	0	1	0	0	0	0	0	1	SNG_W1[7]
0	0	1	0	0	0	0	1	0	SNG_N0_N3
0	0	1	0	0	0	1	0	0	QUAD_NW4[3]
0	0	1	0	0	1	0	0	0	QUAD_NN4[3]
0	0	1	0	1	0	0	0	0	OUT[15]
0	1	0	0	0	0	0	0	1	OUT[11]
0	1	0	0	0	0	0	1	0	OUT[3]
0	1	0	0	0	0	1	0	0	DBL_WW2[2]
0	1	0	0	0	1	0	0	0	DBL_EE2[3]
0	1	0	0	1	0	0	0	0	DBL_NN2[3]
1	0	0	0	0	0	0	0	1	OUT[7]
1	0	0	0	0	0	0	1	0	OUT[21]
1	0	0	0	0	0	1	0	0	DBL_SW2[2]
1	0	0	0	0	1	0	0	0	DBL_NE2[3]
1	0	0	0	1	0	0	0	0	DBL_NW2[3]

virtex6 INT switchbox INT muxes SNG_W0[0]
Bits									Destination
MAIN[10][28]	MAIN[11][28]	MAIN[4][28]	MAIN[12][28]	MAIN[12][30]	MAIN[11][29]	MAIN[5][29]	MAIN[12][29]	MAIN[11][30]	SNG_W0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[1]
0	0	0	1	0	0	0	1	0	SNG_S1[5]
0	0	0	1	0	0	1	0	0	OUT[19]
0	0	0	1	0	1	0	0	0	QUAD_SW4[1]
0	0	0	1	1	0	0	0	0	QUAD_WW4[2]
0	0	1	0	0	0	0	0	1	SNG_W1[6]
0	0	1	0	0	0	0	1	0	SNG_S1[1]
0	0	1	0	0	0	1	0	0	OUT[13]
0	0	1	0	0	1	0	0	0	QUAD_SS4[1]
0	0	1	0	1	0	0	0	0	QUAD_NW4[2]
0	1	0	0	0	0	0	0	1	OUT[9]
0	1	0	0	0	0	0	1	0	OUT[1]
0	1	0	0	0	0	1	0	0	DBL_WW2[1]
0	1	0	0	0	1	0	0	0	DBL_SS2[1]
0	1	0	0	1	0	0	0	0	DBL_NN2[2]
1	0	0	0	0	0	0	0	1	OUT[5]
1	0	0	0	0	0	0	1	0	OUT[23]
1	0	0	0	0	0	1	0	0	DBL_SW2[1]
1	0	0	0	0	1	0	0	0	DBL_SE2[1]
1	0	0	0	1	0	0	0	0	DBL_NW2[2]

virtex6 INT switchbox INT muxes SNG_W0[1]
Bits									Destination
MAIN[10][44]	MAIN[11][44]	MAIN[4][44]	MAIN[12][44]	MAIN[12][46]	MAIN[11][45]	MAIN[5][45]	MAIN[12][45]	MAIN[11][46]	SNG_W0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[2]
0	0	0	1	0	0	0	1	0	SNG_S1[6]
0	0	0	1	0	0	1	0	0	OUT[20]
0	0	0	1	0	1	0	0	0	QUAD_SW4[2]
0	0	0	1	1	0	0	0	0	QUAD_WW4[3]
0	0	1	0	0	0	0	0	1	SNG_W1[7]
0	0	1	0	0	0	0	1	0	SNG_S1[2]
0	0	1	0	0	0	1	0	0	OUT[10]
0	0	1	0	0	1	0	0	0	QUAD_SS4[2]
0	0	1	0	1	0	0	0	0	QUAD_NW4[3]
0	1	0	0	0	0	0	0	1	OUT[14]
0	1	0	0	0	0	0	1	0	OUT[6]
0	1	0	0	0	0	1	0	0	DBL_WW2[2]
0	1	0	0	0	1	0	0	0	DBL_SS2[2]
0	1	0	0	1	0	0	0	0	DBL_NN2[3]
1	0	0	0	0	0	0	0	1	OUT[2]
1	0	0	0	0	0	0	1	0	OUT[16]
1	0	0	0	0	0	1	0	0	DBL_SW2[2]
1	0	0	0	0	1	0	0	0	DBL_SE2[2]
1	0	0	0	1	0	0	0	0	DBL_NW2[3]

virtex6 INT switchbox INT muxes SNG_W0[2]
Bits									Destination
MAIN[10][60]	MAIN[11][60]	MAIN[4][60]	MAIN[12][60]	MAIN[12][62]	MAIN[11][61]	MAIN[5][61]	MAIN[12][61]	MAIN[11][62]	SNG_W0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[3]
0	0	0	1	0	0	0	1	0	SNG_S1[7]
0	0	0	1	0	0	1	0	0	OUT[17]
0	0	0	1	0	1	0	0	0	QUAD_SW4[3]
0	0	0	1	1	0	0	0	0	QUAD_WW4_S0
0	0	1	0	0	0	0	0	1	SNG_W1_S4
0	0	1	0	0	0	0	1	0	SNG_S1[3]
0	0	1	0	0	0	1	0	0	OUT[15]
0	0	1	0	0	1	0	0	0	QUAD_SS4[3]
0	0	1	0	1	0	0	0	0	QUAD_NW4_S0
0	1	0	0	0	0	0	0	1	OUT[11]
0	1	0	0	0	0	0	1	0	OUT[3]
0	1	0	0	0	0	1	0	0	DBL_WW2[3]
0	1	0	0	0	1	0	0	0	DBL_SS2[3]
0	1	0	0	1	0	0	0	0	DBL_NN2_S0
1	0	0	0	0	0	0	0	1	OUT[7]
1	0	0	0	0	0	0	1	0	OUT[21]
1	0	0	0	0	0	1	0	0	DBL_SW2[3]
1	0	0	0	0	1	0	0	0	DBL_SE2[3]
1	0	0	0	1	0	0	0	0	DBL_NW2_S0

virtex6 INT switchbox INT muxes SNG_W0[5]
Bits									Destination
MAIN[11][3]	MAIN[10][3]	MAIN[12][3]	MAIN[13][3]	MAIN[4][2]	MAIN[10][2]	MAIN[5][1]	MAIN[5][3]	MAIN[10][1]	SNG_W0[5]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[4]
0	0	0	1	0	0	0	1	0	SNG_N1[0]
0	0	0	1	0	0	1	0	0	QUAD_NW4[0]
0	0	0	1	0	1	0	0	0	QUAD_NN4[0]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	SNG_W1_N3
0	0	1	0	0	0	0	1	0	SNG_N1[4]
0	0	1	0	0	0	1	0	0	QUAD_WW4[0]
0	0	1	0	0	1	0	0	0	QUAD_NE4[0]
0	0	1	0	1	0	0	0	0	OUT[22]
0	1	0	0	0	0	0	0	1	OUT[12]
0	1	0	0	0	0	0	1	0	OUT[4]
0	1	0	0	0	0	1	0	0	DBL_WW2_N3
0	1	0	0	0	1	0	0	0	DBL_EE2[0]
0	1	0	0	1	0	0	0	0	DBL_NN2[0]
1	0	0	0	0	0	0	0	1	OUT[0]
1	0	0	0	0	0	0	1	0	OUT[18]
1	0	0	0	0	0	1	0	0	DBL_SW2_N3
1	0	0	0	0	1	0	0	0	DBL_NE2[0]
1	0	0	0	1	0	0	0	0	DBL_NW2[0]

virtex6 INT switchbox INT muxes SNG_W0[6]
Bits									Destination
MAIN[11][19]	MAIN[10][19]	MAIN[13][19]	MAIN[12][19]	MAIN[4][18]	MAIN[10][18]	MAIN[5][17]	MAIN[5][19]	MAIN[10][17]	SNG_W0[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[0]
0	0	0	1	0	0	0	1	0	SNG_N1[5]
0	0	0	1	0	0	1	0	0	QUAD_WW4[1]
0	0	0	1	0	1	0	0	0	QUAD_NE4[1]
0	0	0	1	1	0	0	0	0	OUT[19]
0	0	1	0	0	0	0	0	1	SNG_W1[5]
0	0	1	0	0	0	0	1	0	SNG_N1[1]
0	0	1	0	0	0	1	0	0	QUAD_NW4[1]
0	0	1	0	0	1	0	0	0	QUAD_NN4[1]
0	0	1	0	1	0	0	0	0	OUT[13]
0	1	0	0	0	0	0	0	1	OUT[9]
0	1	0	0	0	0	0	1	0	OUT[1]
0	1	0	0	0	0	1	0	0	DBL_WW2[0]
0	1	0	0	0	1	0	0	0	DBL_EE2[1]
0	1	0	0	1	0	0	0	0	DBL_NN2[1]
1	0	0	0	0	0	0	0	1	OUT[5]
1	0	0	0	0	0	0	1	0	OUT[23]
1	0	0	0	0	0	1	0	0	DBL_SW2[0]
1	0	0	0	0	1	0	0	0	DBL_NE2[1]
1	0	0	0	1	0	0	0	0	DBL_NW2[1]

virtex6 INT switchbox INT muxes SNG_W0[7]
Bits									Destination
MAIN[11][35]	MAIN[10][35]	MAIN[13][35]	MAIN[12][35]	MAIN[4][34]	MAIN[10][34]	MAIN[5][33]	MAIN[5][35]	MAIN[10][33]	SNG_W0[7]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[1]
0	0	0	1	0	0	0	1	0	SNG_N1[6]
0	0	0	1	0	0	1	0	0	QUAD_WW4[2]
0	0	0	1	0	1	0	0	0	QUAD_NE4[2]
0	0	0	1	1	0	0	0	0	OUT[20]
0	0	1	0	0	0	0	0	1	SNG_W1[6]
0	0	1	0	0	0	0	1	0	SNG_N1[2]
0	0	1	0	0	0	1	0	0	QUAD_NW4[2]
0	0	1	0	0	1	0	0	0	QUAD_NN4[2]
0	0	1	0	1	0	0	0	0	OUT[10]
0	1	0	0	0	0	0	0	1	OUT[14]
0	1	0	0	0	0	0	1	0	OUT[6]
0	1	0	0	0	0	1	0	0	DBL_WW2[1]
0	1	0	0	0	1	0	0	0	DBL_EE2[2]
0	1	0	0	1	0	0	0	0	DBL_NN2[2]
1	0	0	0	0	0	0	0	1	OUT[2]
1	0	0	0	0	0	0	1	0	OUT[16]
1	0	0	0	0	0	1	0	0	DBL_SW2[1]
1	0	0	0	0	1	0	0	0	DBL_NE2[2]
1	0	0	0	1	0	0	0	0	DBL_NW2[2]

virtex6 INT switchbox INT muxes SNG_E0_N3
Bits									Destination
MAIN[10][4]	MAIN[11][4]	MAIN[4][4]	MAIN[12][4]	MAIN[11][5]	MAIN[12][6]	MAIN[13][5]	MAIN[12][5]	MAIN[11][6]	SNG_E0_N3
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[0]
0	0	0	1	0	0	0	1	0	SNG_N1[4]
0	0	0	1	0	0	1	0	0	OUT[22]
0	0	0	1	0	1	0	0	0	QUAD_EE4[0]
0	0	0	1	1	0	0	0	0	QUAD_NE4[0]
0	0	1	0	0	0	0	0	1	SNG_E1[4]
0	0	1	0	0	0	0	1	0	SNG_N1[0]
0	0	1	0	0	0	1	0	0	OUT[8]
0	0	1	0	0	1	0	0	0	QUAD_SE4[0]
0	0	1	0	1	0	0	0	0	QUAD_NN4[0]
0	1	0	0	0	0	0	0	1	OUT[12]
0	1	0	0	0	0	0	1	0	OUT[4]
0	1	0	0	0	0	1	0	0	DBL_EE2[0]
0	1	0	0	0	1	0	0	0	DBL_SS2[0]
0	1	0	0	1	0	0	0	0	DBL_NN2[0]
1	0	0	0	0	0	0	0	1	OUT[0]
1	0	0	0	0	0	0	1	0	OUT[18]
1	0	0	0	0	0	1	0	0	DBL_NE2[0]
1	0	0	0	0	1	0	0	0	DBL_SE2[0]
1	0	0	0	1	0	0	0	0	DBL_NW2[0]

virtex6 INT switchbox INT muxes SNG_E0_S4
Bits									Destination
MAIN[11][59]	MAIN[10][59]	MAIN[13][59]	MAIN[12][59]	MAIN[4][58]	MAIN[13][57]	MAIN[10][58]	MAIN[5][59]	MAIN[10][57]	SNG_E0_S4
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[3]
0	0	0	1	0	0	0	1	0	SNG_S1[7]
0	0	0	1	0	0	1	0	0	QUAD_SW4[3]
0	0	0	1	0	1	0	0	0	QUAD_EE4[3]
0	0	0	1	1	0	0	0	0	OUT[17]
0	0	1	0	0	0	0	0	1	SNG_E1[7]
0	0	1	0	0	0	0	1	0	SNG_S1[3]
0	0	1	0	0	0	1	0	0	QUAD_SS4[3]
0	0	1	0	0	1	0	0	0	QUAD_SE4[3]
0	0	1	0	1	0	0	0	0	OUT[15]
0	1	0	0	0	0	0	0	1	OUT[11]
0	1	0	0	0	0	0	1	0	OUT[3]
0	1	0	0	0	0	1	0	0	DBL_WW2[3]
0	1	0	0	0	1	0	0	0	DBL_EE2[3]
0	1	0	0	1	0	0	0	0	DBL_SS2[3]
1	0	0	0	0	0	0	0	1	OUT[7]
1	0	0	0	0	0	0	1	0	OUT[21]
1	0	0	0	0	0	1	0	0	DBL_SW2[3]
1	0	0	0	0	1	0	0	0	DBL_NE2[3]
1	0	0	0	1	0	0	0	0	DBL_SE2[3]

virtex6 INT switchbox INT muxes SNG_E0[0]
Bits									Destination
MAIN[10][20]	MAIN[11][20]	MAIN[4][20]	MAIN[12][20]	MAIN[11][21]	MAIN[12][22]	MAIN[13][21]	MAIN[12][21]	MAIN[11][22]	SNG_E0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[1]
0	0	0	1	0	0	0	1	0	SNG_N1[5]
0	0	0	1	0	0	1	0	0	OUT[19]
0	0	0	1	0	1	0	0	0	QUAD_EE4[1]
0	0	0	1	1	0	0	0	0	QUAD_NE4[1]
0	0	1	0	0	0	0	0	1	SNG_E1[5]
0	0	1	0	0	0	0	1	0	SNG_N1[1]
0	0	1	0	0	0	1	0	0	OUT[13]
0	0	1	0	0	1	0	0	0	QUAD_SE4[1]
0	0	1	0	1	0	0	0	0	QUAD_NN4[1]
0	1	0	0	0	0	0	0	1	OUT[9]
0	1	0	0	0	0	0	1	0	OUT[1]
0	1	0	0	0	0	1	0	0	DBL_EE2[1]
0	1	0	0	0	1	0	0	0	DBL_SS2[1]
0	1	0	0	1	0	0	0	0	DBL_NN2[1]
1	0	0	0	0	0	0	0	1	OUT[5]
1	0	0	0	0	0	0	1	0	OUT[23]
1	0	0	0	0	0	1	0	0	DBL_NE2[1]
1	0	0	0	0	1	0	0	0	DBL_SE2[1]
1	0	0	0	1	0	0	0	0	DBL_NW2[1]

virtex6 INT switchbox INT muxes SNG_E0[1]
Bits									Destination
MAIN[10][36]	MAIN[11][36]	MAIN[4][36]	MAIN[12][36]	MAIN[11][37]	MAIN[12][38]	MAIN[13][37]	MAIN[12][37]	MAIN[11][38]	SNG_E0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[2]
0	0	0	1	0	0	0	1	0	SNG_N1[6]
0	0	0	1	0	0	1	0	0	OUT[20]
0	0	0	1	0	1	0	0	0	QUAD_EE4[2]
0	0	0	1	1	0	0	0	0	QUAD_NE4[2]
0	0	1	0	0	0	0	0	1	SNG_E1[6]
0	0	1	0	0	0	0	1	0	SNG_N1[2]
0	0	1	0	0	0	1	0	0	OUT[10]
0	0	1	0	0	1	0	0	0	QUAD_SE4[2]
0	0	1	0	1	0	0	0	0	QUAD_NN4[2]
0	1	0	0	0	0	0	0	1	OUT[14]
0	1	0	0	0	0	0	1	0	OUT[6]
0	1	0	0	0	0	1	0	0	DBL_EE2[2]
0	1	0	0	0	1	0	0	0	DBL_SS2[2]
0	1	0	0	1	0	0	0	0	DBL_NN2[2]
1	0	0	0	0	0	0	0	1	OUT[2]
1	0	0	0	0	0	0	1	0	OUT[16]
1	0	0	0	0	0	1	0	0	DBL_NE2[2]
1	0	0	0	0	1	0	0	0	DBL_SE2[2]
1	0	0	0	1	0	0	0	0	DBL_NW2[2]

virtex6 INT switchbox INT muxes SNG_E0[2]
Bits									Destination
MAIN[10][52]	MAIN[11][52]	MAIN[4][52]	MAIN[12][52]	MAIN[11][53]	MAIN[12][54]	MAIN[13][53]	MAIN[12][53]	MAIN[11][54]	SNG_E0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[3]
0	0	0	1	0	0	0	1	0	SNG_N1[7]
0	0	0	1	0	0	1	0	0	OUT[17]
0	0	0	1	0	1	0	0	0	QUAD_EE4[3]
0	0	0	1	1	0	0	0	0	QUAD_NE4[3]
0	0	1	0	0	0	0	0	1	SNG_E1[7]
0	0	1	0	0	0	0	1	0	SNG_N0_N3
0	0	1	0	0	0	1	0	0	OUT[15]
0	0	1	0	0	1	0	0	0	QUAD_SE4[3]
0	0	1	0	1	0	0	0	0	QUAD_NN4[3]
0	1	0	0	0	0	0	0	1	OUT[11]
0	1	0	0	0	0	0	1	0	OUT[3]
0	1	0	0	0	0	1	0	0	DBL_EE2[3]
0	1	0	0	0	1	0	0	0	DBL_SS2[3]
0	1	0	0	1	0	0	0	0	DBL_NN2[3]
1	0	0	0	0	0	0	0	1	OUT[7]
1	0	0	0	0	0	0	1	0	OUT[21]
1	0	0	0	0	0	1	0	0	DBL_NE2[3]
1	0	0	0	0	1	0	0	0	DBL_SE2[3]
1	0	0	0	1	0	0	0	0	DBL_NW2[3]

virtex6 INT switchbox INT muxes SNG_E0[5]
Bits									Destination
MAIN[11][11]	MAIN[10][11]	MAIN[13][11]	MAIN[12][11]	MAIN[4][10]	MAIN[13][9]	MAIN[10][10]	MAIN[5][11]	MAIN[10][9]	SNG_E0[5]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[0]
0	0	0	1	0	0	0	1	0	SNG_S0_S4
0	0	0	1	0	0	1	0	0	QUAD_SW4[0]
0	0	0	1	0	1	0	0	0	QUAD_EE4[0]
0	0	0	1	1	0	0	0	0	OUT[22]
0	0	1	0	0	0	0	0	1	SNG_E1[4]
0	0	1	0	0	0	0	1	0	SNG_S1[0]
0	0	1	0	0	0	1	0	0	QUAD_SS4[0]
0	0	1	0	0	1	0	0	0	QUAD_SE4[0]
0	0	1	0	1	0	0	0	0	OUT[8]
0	1	0	0	0	0	0	0	1	OUT[12]
0	1	0	0	0	0	0	1	0	OUT[4]
0	1	0	0	0	0	1	0	0	DBL_WW2[0]
0	1	0	0	0	1	0	0	0	DBL_EE2[0]
0	1	0	0	1	0	0	0	0	DBL_SS2[0]
1	0	0	0	0	0	0	0	1	OUT[0]
1	0	0	0	0	0	0	1	0	OUT[18]
1	0	0	0	0	0	1	0	0	DBL_SW2[0]
1	0	0	0	0	1	0	0	0	DBL_NE2[0]
1	0	0	0	1	0	0	0	0	DBL_SE2[0]

virtex6 INT switchbox INT muxes SNG_E0[6]
Bits									Destination
MAIN[11][27]	MAIN[10][27]	MAIN[13][27]	MAIN[12][27]	MAIN[4][26]	MAIN[13][25]	MAIN[10][26]	MAIN[5][27]	MAIN[10][25]	SNG_E0[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[1]
0	0	0	1	0	0	0	1	0	SNG_S1[5]
0	0	0	1	0	0	1	0	0	QUAD_SW4[1]
0	0	0	1	0	1	0	0	0	QUAD_EE4[1]
0	0	0	1	1	0	0	0	0	OUT[19]
0	0	1	0	0	0	0	0	1	SNG_E1[5]
0	0	1	0	0	0	0	1	0	SNG_S1[1]
0	0	1	0	0	0	1	0	0	QUAD_SS4[1]
0	0	1	0	0	1	0	0	0	QUAD_SE4[1]
0	0	1	0	1	0	0	0	0	OUT[13]
0	1	0	0	0	0	0	0	1	OUT[9]
0	1	0	0	0	0	0	1	0	OUT[1]
0	1	0	0	0	0	1	0	0	DBL_WW2[1]
0	1	0	0	0	1	0	0	0	DBL_EE2[1]
0	1	0	0	1	0	0	0	0	DBL_SS2[1]
1	0	0	0	0	0	0	0	1	OUT[5]
1	0	0	0	0	0	0	1	0	OUT[23]
1	0	0	0	0	0	1	0	0	DBL_SW2[1]
1	0	0	0	0	1	0	0	0	DBL_NE2[1]
1	0	0	0	1	0	0	0	0	DBL_SE2[1]

virtex6 INT switchbox INT muxes SNG_E0[7]
Bits									Destination
MAIN[11][43]	MAIN[10][43]	MAIN[13][43]	MAIN[12][43]	MAIN[4][42]	MAIN[13][41]	MAIN[10][42]	MAIN[5][43]	MAIN[10][41]	SNG_E0[7]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[2]
0	0	0	1	0	0	0	1	0	SNG_S1[6]
0	0	0	1	0	0	1	0	0	QUAD_SW4[2]
0	0	0	1	0	1	0	0	0	QUAD_EE4[2]
0	0	0	1	1	0	0	0	0	OUT[20]
0	0	1	0	0	0	0	0	1	SNG_E1[6]
0	0	1	0	0	0	0	1	0	SNG_S1[2]
0	0	1	0	0	0	1	0	0	QUAD_SS4[2]
0	0	1	0	0	1	0	0	0	QUAD_SE4[2]
0	0	1	0	1	0	0	0	0	OUT[10]
0	1	0	0	0	0	0	0	1	OUT[14]
0	1	0	0	0	0	0	1	0	OUT[6]
0	1	0	0	0	0	1	0	0	DBL_WW2[2]
0	1	0	0	0	1	0	0	0	DBL_EE2[2]
0	1	0	0	1	0	0	0	0	DBL_SS2[2]
1	0	0	0	0	0	0	0	1	OUT[2]
1	0	0	0	0	0	0	1	0	OUT[16]
1	0	0	0	0	0	1	0	0	DBL_SW2[2]
1	0	0	0	0	1	0	0	0	DBL_NE2[2]
1	0	0	0	1	0	0	0	0	DBL_SE2[2]

virtex6 INT switchbox INT muxes SNG_S0_S4
Bits									Destination
MAIN[11][63]	MAIN[10][63]	MAIN[13][63]	MAIN[12][63]	MAIN[10][62]	MAIN[13][61]	MAIN[4][62]	MAIN[10][61]	MAIN[5][63]	SNG_S0_S4
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[3]
0	0	0	1	0	0	0	1	0	SNG_S1[7]
0	0	0	1	0	0	1	0	0	OUT[17]
0	0	0	1	0	1	0	0	0	QUAD_SW4[3]
0	0	0	1	1	0	0	0	0	QUAD_WW4_S0
0	0	1	0	0	0	0	0	1	SNG_W1_S4
0	0	1	0	0	0	0	1	0	SNG_S1[3]
0	0	1	0	0	0	1	0	0	OUT[15]
0	0	1	0	0	1	0	0	0	QUAD_SS4[3]
0	0	1	0	1	0	0	0	0	QUAD_NW4_S0
0	1	0	0	0	0	0	0	1	OUT[11]
0	1	0	0	0	0	0	1	0	OUT[3]
0	1	0	0	0	0	1	0	0	DBL_WW2[3]
0	1	0	0	0	1	0	0	0	DBL_SS2[3]
0	1	0	0	1	0	0	0	0	DBL_NN2_S0
1	0	0	0	0	0	0	0	1	OUT[7]
1	0	0	0	0	0	0	1	0	OUT[21]
1	0	0	0	0	0	1	0	0	DBL_SW2[3]
1	0	0	0	0	1	0	0	0	DBL_SE2[3]
1	0	0	0	1	0	0	0	0	DBL_NW2_S0

virtex6 INT switchbox INT muxes SNG_S0[0]
Bits									Destination
MAIN[10][8]	MAIN[11][8]	MAIN[4][8]	MAIN[12][8]	MAIN[5][9]	MAIN[11][9]	MAIN[12][10]	MAIN[11][10]	MAIN[12][9]	SNG_S0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[0]
0	0	0	1	0	0	0	1	0	SNG_S0_S4
0	0	0	1	0	0	1	0	0	QUAD_SW4[0]
0	0	0	1	0	1	0	0	0	QUAD_EE4[0]
0	0	0	1	1	0	0	0	0	OUT[22]
0	0	1	0	0	0	0	0	1	SNG_E1[4]
0	0	1	0	0	0	0	1	0	SNG_S1[0]
0	0	1	0	0	0	1	0	0	QUAD_SS4[0]
0	0	1	0	0	1	0	0	0	QUAD_SE4[0]
0	0	1	0	1	0	0	0	0	OUT[8]
0	1	0	0	0	0	0	0	1	OUT[12]
0	1	0	0	0	0	0	1	0	OUT[4]
0	1	0	0	0	0	1	0	0	DBL_WW2[0]
0	1	0	0	0	1	0	0	0	DBL_EE2[0]
0	1	0	0	1	0	0	0	0	DBL_SS2[0]
1	0	0	0	0	0	0	0	1	OUT[0]
1	0	0	0	0	0	0	1	0	OUT[18]
1	0	0	0	0	0	1	0	0	DBL_SW2[0]
1	0	0	0	0	1	0	0	0	DBL_NE2[0]
1	0	0	0	1	0	0	0	0	DBL_SE2[0]

virtex6 INT switchbox INT muxes SNG_S0[1]
Bits									Destination
MAIN[10][24]	MAIN[11][24]	MAIN[4][24]	MAIN[12][24]	MAIN[5][25]	MAIN[11][25]	MAIN[12][26]	MAIN[11][26]	MAIN[12][25]	SNG_S0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[1]
0	0	0	1	0	0	0	1	0	SNG_S1[5]
0	0	0	1	0	0	1	0	0	QUAD_SW4[1]
0	0	0	1	0	1	0	0	0	QUAD_EE4[1]
0	0	0	1	1	0	0	0	0	OUT[19]
0	0	1	0	0	0	0	0	1	SNG_E1[5]
0	0	1	0	0	0	0	1	0	SNG_S1[1]
0	0	1	0	0	0	1	0	0	QUAD_SS4[1]
0	0	1	0	0	1	0	0	0	QUAD_SE4[1]
0	0	1	0	1	0	0	0	0	OUT[13]
0	1	0	0	0	0	0	0	1	OUT[9]
0	1	0	0	0	0	0	1	0	OUT[1]
0	1	0	0	0	0	1	0	0	DBL_WW2[1]
0	1	0	0	0	1	0	0	0	DBL_EE2[1]
0	1	0	0	1	0	0	0	0	DBL_SS2[1]
1	0	0	0	0	0	0	0	1	OUT[5]
1	0	0	0	0	0	0	1	0	OUT[23]
1	0	0	0	0	0	1	0	0	DBL_SW2[1]
1	0	0	0	0	1	0	0	0	DBL_NE2[1]
1	0	0	0	1	0	0	0	0	DBL_SE2[1]

virtex6 INT switchbox INT muxes SNG_S0[2]
Bits									Destination
MAIN[10][40]	MAIN[11][40]	MAIN[4][40]	MAIN[12][40]	MAIN[5][41]	MAIN[11][41]	MAIN[12][42]	MAIN[11][42]	MAIN[12][41]	SNG_S0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[2]
0	0	0	1	0	0	0	1	0	SNG_S1[6]
0	0	0	1	0	0	1	0	0	QUAD_SW4[2]
0	0	0	1	0	1	0	0	0	QUAD_EE4[2]
0	0	0	1	1	0	0	0	0	OUT[20]
0	0	1	0	0	0	0	0	1	SNG_E1[6]
0	0	1	0	0	0	0	1	0	SNG_S1[2]
0	0	1	0	0	0	1	0	0	QUAD_SS4[2]
0	0	1	0	0	1	0	0	0	QUAD_SE4[2]
0	0	1	0	1	0	0	0	0	OUT[10]
0	1	0	0	0	0	0	0	1	OUT[14]
0	1	0	0	0	0	0	1	0	OUT[6]
0	1	0	0	0	0	1	0	0	DBL_WW2[2]
0	1	0	0	0	1	0	0	0	DBL_EE2[2]
0	1	0	0	1	0	0	0	0	DBL_SS2[2]
1	0	0	0	0	0	0	0	1	OUT[2]
1	0	0	0	0	0	0	1	0	OUT[16]
1	0	0	0	0	0	1	0	0	DBL_SW2[2]
1	0	0	0	0	1	0	0	0	DBL_NE2[2]
1	0	0	0	1	0	0	0	0	DBL_SE2[2]

virtex6 INT switchbox INT muxes SNG_S0[3]
Bits									Destination
MAIN[10][56]	MAIN[11][56]	MAIN[4][56]	MAIN[12][56]	MAIN[5][57]	MAIN[11][57]	MAIN[12][58]	MAIN[11][58]	MAIN[12][57]	SNG_S0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[3]
0	0	0	1	0	0	0	1	0	SNG_S1[7]
0	0	0	1	0	0	1	0	0	QUAD_SW4[3]
0	0	0	1	0	1	0	0	0	QUAD_EE4[3]
0	0	0	1	1	0	0	0	0	OUT[17]
0	0	1	0	0	0	0	0	1	SNG_E1[7]
0	0	1	0	0	0	0	1	0	SNG_S1[3]
0	0	1	0	0	0	1	0	0	QUAD_SS4[3]
0	0	1	0	0	1	0	0	0	QUAD_SE4[3]
0	0	1	0	1	0	0	0	0	OUT[15]
0	1	0	0	0	0	0	0	1	OUT[11]
0	1	0	0	0	0	0	1	0	OUT[3]
0	1	0	0	0	0	1	0	0	DBL_WW2[3]
0	1	0	0	0	1	0	0	0	DBL_EE2[3]
0	1	0	0	1	0	0	0	0	DBL_SS2[3]
1	0	0	0	0	0	0	0	1	OUT[7]
1	0	0	0	0	0	0	1	0	OUT[21]
1	0	0	0	0	0	1	0	0	DBL_SW2[3]
1	0	0	0	0	1	0	0	0	DBL_NE2[3]
1	0	0	0	1	0	0	0	0	DBL_SE2[3]

virtex6 INT switchbox INT muxes SNG_S0[5]
Bits									Destination
MAIN[11][15]	MAIN[10][15]	MAIN[13][15]	MAIN[12][15]	MAIN[10][14]	MAIN[13][13]	MAIN[4][14]	MAIN[10][13]	MAIN[5][15]	SNG_S0[5]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[0]
0	0	0	1	0	0	0	1	0	SNG_S0_S4
0	0	0	1	0	0	1	0	0	OUT[22]
0	0	0	1	0	1	0	0	0	QUAD_SW4[0]
0	0	0	1	1	0	0	0	0	QUAD_WW4[1]
0	0	1	0	0	0	0	0	1	SNG_W1[5]
0	0	1	0	0	0	0	1	0	SNG_S1[0]
0	0	1	0	0	0	1	0	0	OUT[8]
0	0	1	0	0	1	0	0	0	QUAD_SS4[0]
0	0	1	0	1	0	0	0	0	QUAD_NW4[1]
0	1	0	0	0	0	0	0	1	OUT[12]
0	1	0	0	0	0	0	1	0	OUT[4]
0	1	0	0	0	0	1	0	0	DBL_WW2[0]
0	1	0	0	0	1	0	0	0	DBL_SS2[0]
0	1	0	0	1	0	0	0	0	DBL_NN2[1]
1	0	0	0	0	0	0	0	1	OUT[0]
1	0	0	0	0	0	0	1	0	OUT[18]
1	0	0	0	0	0	1	0	0	DBL_SW2[0]
1	0	0	0	0	1	0	0	0	DBL_SE2[0]
1	0	0	0	1	0	0	0	0	DBL_NW2[1]

virtex6 INT switchbox INT muxes SNG_S0[6]
Bits									Destination
MAIN[11][31]	MAIN[10][31]	MAIN[13][31]	MAIN[12][31]	MAIN[10][30]	MAIN[13][29]	MAIN[4][30]	MAIN[10][29]	MAIN[5][31]	SNG_S0[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[1]
0	0	0	1	0	0	0	1	0	SNG_S1[5]
0	0	0	1	0	0	1	0	0	OUT[19]
0	0	0	1	0	1	0	0	0	QUAD_SW4[1]
0	0	0	1	1	0	0	0	0	QUAD_WW4[2]
0	0	1	0	0	0	0	0	1	SNG_W1[6]
0	0	1	0	0	0	0	1	0	SNG_S1[1]
0	0	1	0	0	0	1	0	0	OUT[13]
0	0	1	0	0	1	0	0	0	QUAD_SS4[1]
0	0	1	0	1	0	0	0	0	QUAD_NW4[2]
0	1	0	0	0	0	0	0	1	OUT[9]
0	1	0	0	0	0	0	1	0	OUT[1]
0	1	0	0	0	0	1	0	0	DBL_WW2[1]
0	1	0	0	0	1	0	0	0	DBL_SS2[1]
0	1	0	0	1	0	0	0	0	DBL_NN2[2]
1	0	0	0	0	0	0	0	1	OUT[5]
1	0	0	0	0	0	0	1	0	OUT[23]
1	0	0	0	0	0	1	0	0	DBL_SW2[1]
1	0	0	0	0	1	0	0	0	DBL_SE2[1]
1	0	0	0	1	0	0	0	0	DBL_NW2[2]

virtex6 INT switchbox INT muxes SNG_S0[7]
Bits									Destination
MAIN[11][47]	MAIN[10][47]	MAIN[13][47]	MAIN[12][47]	MAIN[10][46]	MAIN[13][45]	MAIN[4][46]	MAIN[10][45]	MAIN[5][47]	SNG_S0[7]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[2]
0	0	0	1	0	0	0	1	0	SNG_S1[6]
0	0	0	1	0	0	1	0	0	OUT[20]
0	0	0	1	0	1	0	0	0	QUAD_SW4[2]
0	0	0	1	1	0	0	0	0	QUAD_WW4[3]
0	0	1	0	0	0	0	0	1	SNG_W1[7]
0	0	1	0	0	0	0	1	0	SNG_S1[2]
0	0	1	0	0	0	1	0	0	OUT[10]
0	0	1	0	0	1	0	0	0	QUAD_SS4[2]
0	0	1	0	1	0	0	0	0	QUAD_NW4[3]
0	1	0	0	0	0	0	0	1	OUT[14]
0	1	0	0	0	0	0	1	0	OUT[6]
0	1	0	0	0	0	1	0	0	DBL_WW2[2]
0	1	0	0	0	1	0	0	0	DBL_SS2[2]
0	1	0	0	1	0	0	0	0	DBL_NN2[3]
1	0	0	0	0	0	0	0	1	OUT[2]
1	0	0	0	0	0	0	1	0	OUT[16]
1	0	0	0	0	0	1	0	0	DBL_SW2[2]
1	0	0	0	0	1	0	0	0	DBL_SE2[2]
1	0	0	0	1	0	0	0	0	DBL_NW2[3]

virtex6 INT switchbox INT muxes SNG_N0_N3
Bits									Destination
MAIN[10][0]	MAIN[11][0]	MAIN[12][0]	MAIN[4][0]	MAIN[13][1]	MAIN[12][2]	MAIN[11][1]	MAIN[11][2]	MAIN[12][1]	SNG_N0_N3
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[4]
0	0	0	1	0	0	0	1	0	SNG_N1[0]
0	0	0	1	0	0	1	0	0	QUAD_NW4[0]
0	0	0	1	0	1	0	0	0	QUAD_NN4[0]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	SNG_W1_N3
0	0	1	0	0	0	0	1	0	SNG_N1[4]
0	0	1	0	0	0	1	0	0	QUAD_WW4[0]
0	0	1	0	0	1	0	0	0	QUAD_NE4[0]
0	0	1	0	1	0	0	0	0	OUT[22]
0	1	0	0	0	0	0	0	1	OUT[12]
0	1	0	0	0	0	0	1	0	OUT[4]
0	1	0	0	0	0	1	0	0	DBL_WW2_N3
0	1	0	0	0	1	0	0	0	DBL_EE2[0]
0	1	0	0	1	0	0	0	0	DBL_NN2[0]
1	0	0	0	0	0	0	0	1	OUT[0]
1	0	0	0	0	0	0	1	0	OUT[18]
1	0	0	0	0	0	1	0	0	DBL_SW2_N3
1	0	0	0	0	1	0	0	0	DBL_NE2[0]
1	0	0	0	1	0	0	0	0	DBL_NW2[0]

virtex6 INT switchbox INT muxes SNG_N0[0]
Bits									Destination
MAIN[10][16]	MAIN[11][16]	MAIN[4][16]	MAIN[12][16]	MAIN[13][17]	MAIN[12][18]	MAIN[11][17]	MAIN[11][18]	MAIN[12][17]	SNG_N0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[0]
0	0	0	1	0	0	0	1	0	SNG_N1[5]
0	0	0	1	0	0	1	0	0	QUAD_WW4[1]
0	0	0	1	0	1	0	0	0	QUAD_NE4[1]
0	0	0	1	1	0	0	0	0	OUT[19]
0	0	1	0	0	0	0	0	1	SNG_W1[5]
0	0	1	0	0	0	0	1	0	SNG_N1[1]
0	0	1	0	0	0	1	0	0	QUAD_NW4[1]
0	0	1	0	0	1	0	0	0	QUAD_NN4[1]
0	0	1	0	1	0	0	0	0	OUT[13]
0	1	0	0	0	0	0	0	1	OUT[9]
0	1	0	0	0	0	0	1	0	OUT[1]
0	1	0	0	0	0	1	0	0	DBL_WW2[0]
0	1	0	0	0	1	0	0	0	DBL_EE2[1]
0	1	0	0	1	0	0	0	0	DBL_NN2[1]
1	0	0	0	0	0	0	0	1	OUT[5]
1	0	0	0	0	0	0	1	0	OUT[23]
1	0	0	0	0	0	1	0	0	DBL_SW2[0]
1	0	0	0	0	1	0	0	0	DBL_NE2[1]
1	0	0	0	1	0	0	0	0	DBL_NW2[1]

virtex6 INT switchbox INT muxes SNG_N0[1]
Bits									Destination
MAIN[10][32]	MAIN[11][32]	MAIN[4][32]	MAIN[12][32]	MAIN[13][33]	MAIN[12][34]	MAIN[11][33]	MAIN[11][34]	MAIN[12][33]	SNG_N0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[1]
0	0	0	1	0	0	0	1	0	SNG_N1[6]
0	0	0	1	0	0	1	0	0	QUAD_WW4[2]
0	0	0	1	0	1	0	0	0	QUAD_NE4[2]
0	0	0	1	1	0	0	0	0	OUT[20]
0	0	1	0	0	0	0	0	1	SNG_W1[6]
0	0	1	0	0	0	0	1	0	SNG_N1[2]
0	0	1	0	0	0	1	0	0	QUAD_NW4[2]
0	0	1	0	0	1	0	0	0	QUAD_NN4[2]
0	0	1	0	1	0	0	0	0	OUT[10]
0	1	0	0	0	0	0	0	1	OUT[14]
0	1	0	0	0	0	0	1	0	OUT[6]
0	1	0	0	0	0	1	0	0	DBL_WW2[1]
0	1	0	0	0	1	0	0	0	DBL_EE2[2]
0	1	0	0	1	0	0	0	0	DBL_NN2[2]
1	0	0	0	0	0	0	0	1	OUT[2]
1	0	0	0	0	0	0	1	0	OUT[16]
1	0	0	0	0	0	1	0	0	DBL_SW2[1]
1	0	0	0	0	1	0	0	0	DBL_NE2[2]
1	0	0	0	1	0	0	0	0	DBL_NW2[2]

virtex6 INT switchbox INT muxes SNG_N0[2]
Bits									Destination
MAIN[10][48]	MAIN[11][48]	MAIN[4][48]	MAIN[12][48]	MAIN[13][49]	MAIN[12][50]	MAIN[11][49]	MAIN[11][50]	MAIN[12][49]	SNG_N0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[2]
0	0	0	1	0	0	0	1	0	SNG_N1[7]
0	0	0	1	0	0	1	0	0	QUAD_WW4[3]
0	0	0	1	0	1	0	0	0	QUAD_NE4[3]
0	0	0	1	1	0	0	0	0	OUT[17]
0	0	1	0	0	0	0	0	1	SNG_W1[7]
0	0	1	0	0	0	0	1	0	SNG_N0_N3
0	0	1	0	0	0	1	0	0	QUAD_NW4[3]
0	0	1	0	0	1	0	0	0	QUAD_NN4[3]
0	0	1	0	1	0	0	0	0	OUT[15]
0	1	0	0	0	0	0	0	1	OUT[11]
0	1	0	0	0	0	0	1	0	OUT[3]
0	1	0	0	0	0	1	0	0	DBL_WW2[2]
0	1	0	0	0	1	0	0	0	DBL_EE2[3]
0	1	0	0	1	0	0	0	0	DBL_NN2[3]
1	0	0	0	0	0	0	0	1	OUT[7]
1	0	0	0	0	0	0	1	0	OUT[21]
1	0	0	0	0	0	1	0	0	DBL_SW2[2]
1	0	0	0	0	1	0	0	0	DBL_NE2[3]
1	0	0	0	1	0	0	0	0	DBL_NW2[3]

virtex6 INT switchbox INT muxes SNG_N0[4]
Bits									Destination
MAIN[11][7]	MAIN[10][7]	MAIN[13][7]	MAIN[12][7]	MAIN[5][5]	MAIN[10][6]	MAIN[4][6]	MAIN[10][5]	MAIN[5][7]	SNG_N0[4]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[0]
0	0	0	1	0	0	0	1	0	SNG_N1[4]
0	0	0	1	0	0	1	0	0	OUT[22]
0	0	0	1	0	1	0	0	0	QUAD_EE4[0]
0	0	0	1	1	0	0	0	0	QUAD_NE4[0]
0	0	1	0	0	0	0	0	1	SNG_E1[4]
0	0	1	0	0	0	0	1	0	SNG_N1[0]
0	0	1	0	0	0	1	0	0	OUT[8]
0	0	1	0	0	1	0	0	0	QUAD_SE4[0]
0	0	1	0	1	0	0	0	0	QUAD_NN4[0]
0	1	0	0	0	0	0	0	1	OUT[12]
0	1	0	0	0	0	0	1	0	OUT[4]
0	1	0	0	0	0	1	0	0	DBL_EE2[0]
0	1	0	0	0	1	0	0	0	DBL_SS2[0]
0	1	0	0	1	0	0	0	0	DBL_NN2[0]
1	0	0	0	0	0	0	0	1	OUT[0]
1	0	0	0	0	0	0	1	0	OUT[18]
1	0	0	0	0	0	1	0	0	DBL_NE2[0]
1	0	0	0	0	1	0	0	0	DBL_SE2[0]
1	0	0	0	1	0	0	0	0	DBL_NW2[0]

virtex6 INT switchbox INT muxes SNG_N0[5]
Bits									Destination
MAIN[11][23]	MAIN[10][23]	MAIN[13][23]	MAIN[12][23]	MAIN[5][21]	MAIN[10][22]	MAIN[4][22]	MAIN[10][21]	MAIN[5][23]	SNG_N0[5]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[1]
0	0	0	1	0	0	0	1	0	SNG_N1[5]
0	0	0	1	0	0	1	0	0	OUT[19]
0	0	0	1	0	1	0	0	0	QUAD_EE4[1]
0	0	0	1	1	0	0	0	0	QUAD_NE4[1]
0	0	1	0	0	0	0	0	1	SNG_E1[5]
0	0	1	0	0	0	0	1	0	SNG_N1[1]
0	0	1	0	0	0	1	0	0	OUT[13]
0	0	1	0	0	1	0	0	0	QUAD_SE4[1]
0	0	1	0	1	0	0	0	0	QUAD_NN4[1]
0	1	0	0	0	0	0	0	1	OUT[9]
0	1	0	0	0	0	0	1	0	OUT[1]
0	1	0	0	0	0	1	0	0	DBL_EE2[1]
0	1	0	0	0	1	0	0	0	DBL_SS2[1]
0	1	0	0	1	0	0	0	0	DBL_NN2[1]
1	0	0	0	0	0	0	0	1	OUT[5]
1	0	0	0	0	0	0	1	0	OUT[23]
1	0	0	0	0	0	1	0	0	DBL_NE2[1]
1	0	0	0	0	1	0	0	0	DBL_SE2[1]
1	0	0	0	1	0	0	0	0	DBL_NW2[1]

virtex6 INT switchbox INT muxes SNG_N0[6]
Bits									Destination
MAIN[11][39]	MAIN[10][39]	MAIN[13][39]	MAIN[12][39]	MAIN[5][37]	MAIN[10][38]	MAIN[4][38]	MAIN[10][37]	MAIN[5][39]	SNG_N0[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[2]
0	0	0	1	0	0	0	1	0	SNG_N1[6]
0	0	0	1	0	0	1	0	0	OUT[20]
0	0	0	1	0	1	0	0	0	QUAD_EE4[2]
0	0	0	1	1	0	0	0	0	QUAD_NE4[2]
0	0	1	0	0	0	0	0	1	SNG_E1[6]
0	0	1	0	0	0	0	1	0	SNG_N1[2]
0	0	1	0	0	0	1	0	0	OUT[10]
0	0	1	0	0	1	0	0	0	QUAD_SE4[2]
0	0	1	0	1	0	0	0	0	QUAD_NN4[2]
0	1	0	0	0	0	0	0	1	OUT[14]
0	1	0	0	0	0	0	1	0	OUT[6]
0	1	0	0	0	0	1	0	0	DBL_EE2[2]
0	1	0	0	0	1	0	0	0	DBL_SS2[2]
0	1	0	0	1	0	0	0	0	DBL_NN2[2]
1	0	0	0	0	0	0	0	1	OUT[2]
1	0	0	0	0	0	0	1	0	OUT[16]
1	0	0	0	0	0	1	0	0	DBL_NE2[2]
1	0	0	0	0	1	0	0	0	DBL_SE2[2]
1	0	0	0	1	0	0	0	0	DBL_NW2[2]

virtex6 INT switchbox INT muxes SNG_N0[7]
Bits									Destination
MAIN[11][55]	MAIN[10][55]	MAIN[13][55]	MAIN[12][55]	MAIN[5][53]	MAIN[10][54]	MAIN[4][54]	MAIN[10][53]	MAIN[5][55]	SNG_N0[7]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[3]
0	0	0	1	0	0	0	1	0	SNG_N1[7]
0	0	0	1	0	0	1	0	0	OUT[17]
0	0	0	1	0	1	0	0	0	QUAD_EE4[3]
0	0	0	1	1	0	0	0	0	QUAD_NE4[3]
0	0	1	0	0	0	0	0	1	SNG_E1[7]
0	0	1	0	0	0	0	1	0	SNG_N0_N3
0	0	1	0	0	0	1	0	0	OUT[15]
0	0	1	0	0	1	0	0	0	QUAD_SE4[3]
0	0	1	0	1	0	0	0	0	QUAD_NN4[3]
0	1	0	0	0	0	0	0	1	OUT[11]
0	1	0	0	0	0	0	1	0	OUT[3]
0	1	0	0	0	0	1	0	0	DBL_EE2[3]
0	1	0	0	0	1	0	0	0	DBL_SS2[3]
0	1	0	0	1	0	0	0	0	DBL_NN2[3]
1	0	0	0	0	0	0	0	1	OUT[7]
1	0	0	0	0	0	0	1	0	OUT[21]
1	0	0	0	0	0	1	0	0	DBL_NE2[3]
1	0	0	0	0	1	0	0	0	DBL_SE2[3]
1	0	0	0	1	0	0	0	0	DBL_NW2[3]

virtex6 INT switchbox INT muxes DBL_WW0[0]
Bits									Destination
MAIN[8][15]	MAIN[9][15]	MAIN[6][15]	MAIN[7][15]	MAIN[6][14]	MAIN[6][13]	MAIN[8][14]	MAIN[8][13]	MAIN[4][15]	DBL_WW0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[0]
0	0	0	1	0	0	0	1	0	SNG_S0_S4
0	0	0	1	0	0	1	0	0	DBL_NW2[1]
0	0	0	1	0	1	0	0	0	DBL_SS2[0]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	SNG_W1[5]
0	0	1	0	0	0	0	1	0	SNG_S1[0]
0	0	1	0	0	0	1	0	0	DBL_WW2[0]
0	0	1	0	0	1	0	0	0	DBL_SW2[0]
0	0	1	0	1	0	0	0	0	OUT[22]
0	1	0	0	0	0	0	0	1	OUT[0]
0	1	0	0	0	0	0	1	0	OUT[18]
0	1	0	0	0	0	1	0	0	QUAD_NN4[1]
0	1	0	0	0	1	0	0	0	QUAD_SS4[0]
0	1	0	0	1	0	0	0	0	QUAD_WW4[1]
1	0	0	0	0	0	0	0	1	OUT[12]
1	0	0	0	0	0	0	1	0	OUT[4]
1	0	0	0	0	0	1	0	0	QUAD_NW4[1]
1	0	0	0	0	1	0	0	0	QUAD_SE4[0]
1	0	0	0	1	0	0	0	0	QUAD_SW4[0]

virtex6 INT switchbox INT muxes DBL_WW0[1]
Bits									Destination
MAIN[8][31]	MAIN[9][31]	MAIN[6][31]	MAIN[7][31]	MAIN[6][30]	MAIN[6][29]	MAIN[8][30]	MAIN[8][29]	MAIN[4][31]	DBL_WW0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[1]
0	0	0	1	0	0	0	1	0	SNG_S1[5]
0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	1	0	1	0	0	0	DBL_SS2[1]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	SNG_W1[6]
0	0	1	0	0	0	0	1	0	SNG_S1[1]
0	0	1	0	0	0	1	0	0	DBL_WW2[1]
0	0	1	0	0	1	0	0	0	DBL_SW2[1]
0	0	1	0	1	0	0	0	0	OUT[19]
0	1	0	0	0	0	0	0	1	OUT[5]
0	1	0	0	0	0	0	1	0	OUT[23]
0	1	0	0	0	0	1	0	0	QUAD_NN4[2]
0	1	0	0	0	1	0	0	0	QUAD_SS4[1]
0	1	0	0	1	0	0	0	0	QUAD_WW4[2]
1	0	0	0	0	0	0	0	1	OUT[9]
1	0	0	0	0	0	0	1	0	OUT[1]
1	0	0	0	0	0	1	0	0	QUAD_NW4[2]
1	0	0	0	0	1	0	0	0	QUAD_SE4[1]
1	0	0	0	1	0	0	0	0	QUAD_SW4[1]

virtex6 INT switchbox INT muxes DBL_WW0[2]
Bits									Destination
MAIN[8][47]	MAIN[9][47]	MAIN[6][47]	MAIN[7][47]	MAIN[6][46]	MAIN[6][45]	MAIN[8][46]	MAIN[8][45]	MAIN[4][47]	DBL_WW0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[2]
0	0	0	1	0	0	0	1	0	SNG_S1[6]
0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	1	0	1	0	0	0	DBL_SS2[2]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	SNG_W1[7]
0	0	1	0	0	0	0	1	0	SNG_S1[2]
0	0	1	0	0	0	1	0	0	DBL_WW2[2]
0	0	1	0	0	1	0	0	0	DBL_SW2[2]
0	0	1	0	1	0	0	0	0	OUT[20]
0	1	0	0	0	0	0	0	1	OUT[2]
0	1	0	0	0	0	0	1	0	OUT[16]
0	1	0	0	0	0	1	0	0	QUAD_NN4[3]
0	1	0	0	0	1	0	0	0	QUAD_SS4[2]
0	1	0	0	1	0	0	0	0	QUAD_WW4[3]
1	0	0	0	0	0	0	0	1	OUT[14]
1	0	0	0	0	0	0	1	0	OUT[6]
1	0	0	0	0	0	1	0	0	QUAD_NW4[3]
1	0	0	0	0	1	0	0	0	QUAD_SE4[2]
1	0	0	0	1	0	0	0	0	QUAD_SW4[2]

virtex6 INT switchbox INT muxes DBL_WW0[3]
Bits									Destination
MAIN[8][63]	MAIN[9][63]	MAIN[6][63]	MAIN[7][63]	MAIN[6][62]	MAIN[6][61]	MAIN[8][62]	MAIN[8][61]	MAIN[4][63]	DBL_WW0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[3]
0	0	0	1	0	0	0	1	0	SNG_S1[7]
0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	1	0	1	0	0	0	DBL_SS2[3]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	SNG_W1_S4
0	0	1	0	0	0	0	1	0	SNG_S1[3]
0	0	1	0	0	0	1	0	0	DBL_WW2[3]
0	0	1	0	0	1	0	0	0	DBL_SW2[3]
0	0	1	0	1	0	0	0	0	OUT[17]
0	1	0	0	0	0	0	0	1	OUT[7]
0	1	0	0	0	0	0	1	0	OUT[21]
0	1	0	0	0	0	1	0	0	QUAD_NN4_S0
0	1	0	0	0	1	0	0	0	QUAD_SS4[3]
0	1	0	0	1	0	0	0	0	QUAD_WW4_S0
1	0	0	0	0	0	0	0	1	OUT[11]
1	0	0	0	0	0	0	1	0	OUT[3]
1	0	0	0	0	0	1	0	0	QUAD_NW4_S0
1	0	0	0	0	1	0	0	0	QUAD_SE4[3]
1	0	0	0	1	0	0	0	0	QUAD_SW4[3]

virtex6 INT switchbox INT muxes DBL_EE0[0]
Bits									Destination
MAIN[8][7]	MAIN[9][7]	MAIN[6][7]	MAIN[7][7]	MAIN[6][6]	MAIN[6][5]	MAIN[8][6]	MAIN[8][5]	MAIN[4][7]	DBL_EE0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[0]
0	0	0	1	0	0	0	1	0	SNG_N1[4]
0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	1	0	1	0	0	0	DBL_NN2[0]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	SNG_E1[4]
0	0	1	0	0	0	0	1	0	SNG_N1[0]
0	0	1	0	0	0	1	0	0	DBL_EE2[0]
0	0	1	0	0	1	0	0	0	DBL_NE2[0]
0	0	1	0	1	0	0	0	0	OUT[22]
0	1	0	0	0	0	0	0	1	OUT[0]
0	1	0	0	0	0	0	1	0	OUT[18]
0	1	0	0	0	0	1	0	0	QUAD_SS4[0]
0	1	0	0	0	1	0	0	0	QUAD_NN4[0]
0	1	0	0	1	0	0	0	0	QUAD_EE4[0]
1	0	0	0	0	0	0	0	1	OUT[12]
1	0	0	0	0	0	0	1	0	OUT[4]
1	0	0	0	0	0	1	0	0	QUAD_SE4[0]
1	0	0	0	0	1	0	0	0	QUAD_NW4[0]
1	0	0	0	1	0	0	0	0	QUAD_NE4[0]

virtex6 INT switchbox INT muxes DBL_EE0[1]
Bits									Destination
MAIN[8][23]	MAIN[9][23]	MAIN[6][23]	MAIN[7][23]	MAIN[6][22]	MAIN[6][21]	MAIN[8][22]	MAIN[8][21]	MAIN[4][23]	DBL_EE0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[1]
0	0	0	1	0	0	0	1	0	SNG_N1[5]
0	0	0	1	0	0	1	0	0	DBL_SE2[1]
0	0	0	1	0	1	0	0	0	DBL_NN2[1]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	SNG_E1[5]
0	0	1	0	0	0	0	1	0	SNG_N1[1]
0	0	1	0	0	0	1	0	0	DBL_EE2[1]
0	0	1	0	0	1	0	0	0	DBL_NE2[1]
0	0	1	0	1	0	0	0	0	OUT[19]
0	1	0	0	0	0	0	0	1	OUT[5]
0	1	0	0	0	0	0	1	0	OUT[23]
0	1	0	0	0	0	1	0	0	QUAD_SS4[1]
0	1	0	0	0	1	0	0	0	QUAD_NN4[1]
0	1	0	0	1	0	0	0	0	QUAD_EE4[1]
1	0	0	0	0	0	0	0	1	OUT[9]
1	0	0	0	0	0	0	1	0	OUT[1]
1	0	0	0	0	0	1	0	0	QUAD_SE4[1]
1	0	0	0	0	1	0	0	0	QUAD_NW4[1]
1	0	0	0	1	0	0	0	0	QUAD_NE4[1]

virtex6 INT switchbox INT muxes DBL_EE0[2]
Bits									Destination
MAIN[8][39]	MAIN[9][39]	MAIN[6][39]	MAIN[7][39]	MAIN[6][38]	MAIN[6][37]	MAIN[8][38]	MAIN[8][37]	MAIN[4][39]	DBL_EE0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[2]
0	0	0	1	0	0	0	1	0	SNG_N1[6]
0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	1	0	1	0	0	0	DBL_NN2[2]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	SNG_E1[6]
0	0	1	0	0	0	0	1	0	SNG_N1[2]
0	0	1	0	0	0	1	0	0	DBL_EE2[2]
0	0	1	0	0	1	0	0	0	DBL_NE2[2]
0	0	1	0	1	0	0	0	0	OUT[20]
0	1	0	0	0	0	0	0	1	OUT[2]
0	1	0	0	0	0	0	1	0	OUT[16]
0	1	0	0	0	0	1	0	0	QUAD_SS4[2]
0	1	0	0	0	1	0	0	0	QUAD_NN4[2]
0	1	0	0	1	0	0	0	0	QUAD_EE4[2]
1	0	0	0	0	0	0	0	1	OUT[14]
1	0	0	0	0	0	0	1	0	OUT[6]
1	0	0	0	0	0	1	0	0	QUAD_SE4[2]
1	0	0	0	0	1	0	0	0	QUAD_NW4[2]
1	0	0	0	1	0	0	0	0	QUAD_NE4[2]

virtex6 INT switchbox INT muxes DBL_EE0[3]
Bits									Destination
MAIN[8][55]	MAIN[9][55]	MAIN[6][55]	MAIN[7][55]	MAIN[6][54]	MAIN[6][53]	MAIN[8][54]	MAIN[8][53]	MAIN[4][55]	DBL_EE0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[3]
0	0	0	1	0	0	0	1	0	SNG_N1[7]
0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	1	0	1	0	0	0	DBL_NN2[3]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	SNG_E1[7]
0	0	1	0	0	0	0	1	0	SNG_N0_N3
0	0	1	0	0	0	1	0	0	DBL_EE2[3]
0	0	1	0	0	1	0	0	0	DBL_NE2[3]
0	0	1	0	1	0	0	0	0	OUT[17]
0	1	0	0	0	0	0	0	1	OUT[7]
0	1	0	0	0	0	0	1	0	OUT[21]
0	1	0	0	0	0	1	0	0	QUAD_SS4[3]
0	1	0	0	0	1	0	0	0	QUAD_NN4[3]
0	1	0	0	1	0	0	0	0	QUAD_EE4[3]
1	0	0	0	0	0	0	0	1	OUT[11]
1	0	0	0	0	0	0	1	0	OUT[3]
1	0	0	0	0	0	1	0	0	QUAD_SE4[3]
1	0	0	0	0	1	0	0	0	QUAD_NW4[3]
1	0	0	0	1	0	0	0	0	QUAD_NE4[3]

virtex6 INT switchbox INT muxes DBL_SS0[0]
Bits									Destination
MAIN[8][11]	MAIN[9][11]	MAIN[6][11]	MAIN[7][11]	MAIN[6][10]	MAIN[8][10]	MAIN[6][9]	MAIN[4][11]	MAIN[8][9]	DBL_SS0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[0]
0	0	0	1	0	0	0	1	0	SNG_S0_S4
0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	1	0	1	0	0	0	DBL_SS2[0]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	SNG_E1[4]
0	0	1	0	0	0	0	1	0	SNG_S1[0]
0	0	1	0	0	0	1	0	0	DBL_EE2[0]
0	0	1	0	0	1	0	0	0	DBL_SW2[0]
0	0	1	0	1	0	0	0	0	OUT[22]
0	1	0	0	0	0	0	0	1	OUT[0]
0	1	0	0	0	0	0	1	0	OUT[18]
0	1	0	0	0	0	1	0	0	QUAD_EE4[0]
0	1	0	0	0	1	0	0	0	QUAD_WW4[1]
0	1	0	0	1	0	0	0	0	QUAD_SS4[0]
1	0	0	0	0	0	0	0	1	OUT[12]
1	0	0	0	0	0	0	1	0	OUT[4]
1	0	0	0	0	0	1	0	0	QUAD_NE4[0]
1	0	0	0	0	1	0	0	0	QUAD_SW4[0]
1	0	0	0	1	0	0	0	0	QUAD_SE4[0]

virtex6 INT switchbox INT muxes DBL_SS0[1]
Bits									Destination
MAIN[8][27]	MAIN[9][27]	MAIN[6][27]	MAIN[7][27]	MAIN[6][26]	MAIN[8][26]	MAIN[6][25]	MAIN[4][27]	MAIN[8][25]	DBL_SS0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[1]
0	0	0	1	0	0	0	1	0	SNG_S1[5]
0	0	0	1	0	0	1	0	0	DBL_SE2[1]
0	0	0	1	0	1	0	0	0	DBL_SS2[1]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	SNG_E1[5]
0	0	1	0	0	0	0	1	0	SNG_S1[1]
0	0	1	0	0	0	1	0	0	DBL_EE2[1]
0	0	1	0	0	1	0	0	0	DBL_SW2[1]
0	0	1	0	1	0	0	0	0	OUT[19]
0	1	0	0	0	0	0	0	1	OUT[5]
0	1	0	0	0	0	0	1	0	OUT[23]
0	1	0	0	0	0	1	0	0	QUAD_EE4[1]
0	1	0	0	0	1	0	0	0	QUAD_WW4[2]
0	1	0	0	1	0	0	0	0	QUAD_SS4[1]
1	0	0	0	0	0	0	0	1	OUT[9]
1	0	0	0	0	0	0	1	0	OUT[1]
1	0	0	0	0	0	1	0	0	QUAD_NE4[1]
1	0	0	0	0	1	0	0	0	QUAD_SW4[1]
1	0	0	0	1	0	0	0	0	QUAD_SE4[1]

virtex6 INT switchbox INT muxes DBL_SS0[2]
Bits									Destination
MAIN[8][43]	MAIN[9][43]	MAIN[6][43]	MAIN[7][43]	MAIN[6][42]	MAIN[8][42]	MAIN[6][41]	MAIN[4][43]	MAIN[8][41]	DBL_SS0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[2]
0	0	0	1	0	0	0	1	0	SNG_S1[6]
0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	1	0	1	0	0	0	DBL_SS2[2]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	SNG_E1[6]
0	0	1	0	0	0	0	1	0	SNG_S1[2]
0	0	1	0	0	0	1	0	0	DBL_EE2[2]
0	0	1	0	0	1	0	0	0	DBL_SW2[2]
0	0	1	0	1	0	0	0	0	OUT[20]
0	1	0	0	0	0	0	0	1	OUT[2]
0	1	0	0	0	0	0	1	0	OUT[16]
0	1	0	0	0	0	1	0	0	QUAD_EE4[2]
0	1	0	0	0	1	0	0	0	QUAD_WW4[3]
0	1	0	0	1	0	0	0	0	QUAD_SS4[2]
1	0	0	0	0	0	0	0	1	OUT[14]
1	0	0	0	0	0	0	1	0	OUT[6]
1	0	0	0	0	0	1	0	0	QUAD_NE4[2]
1	0	0	0	0	1	0	0	0	QUAD_SW4[2]
1	0	0	0	1	0	0	0	0	QUAD_SE4[2]

virtex6 INT switchbox INT muxes DBL_SS0[3]
Bits									Destination
MAIN[8][59]	MAIN[9][59]	MAIN[6][59]	MAIN[7][59]	MAIN[6][58]	MAIN[8][58]	MAIN[6][57]	MAIN[4][59]	MAIN[8][57]	DBL_SS0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[3]
0	0	0	1	0	0	0	1	0	SNG_S1[7]
0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	1	0	1	0	0	0	DBL_SS2[3]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	SNG_E1[7]
0	0	1	0	0	0	0	1	0	SNG_S1[3]
0	0	1	0	0	0	1	0	0	DBL_EE2[3]
0	0	1	0	0	1	0	0	0	DBL_SW2[3]
0	0	1	0	1	0	0	0	0	OUT[17]
0	1	0	0	0	0	0	0	1	OUT[7]
0	1	0	0	0	0	0	1	0	OUT[21]
0	1	0	0	0	0	1	0	0	QUAD_EE4[3]
0	1	0	0	0	1	0	0	0	QUAD_WW4_S0
0	1	0	0	1	0	0	0	0	QUAD_SS4[3]
1	0	0	0	0	0	0	0	1	OUT[11]
1	0	0	0	0	0	0	1	0	OUT[3]
1	0	0	0	0	0	1	0	0	QUAD_NE4[3]
1	0	0	0	0	1	0	0	0	QUAD_SW4[3]
1	0	0	0	1	0	0	0	0	QUAD_SE4[3]

virtex6 INT switchbox INT muxes DBL_SW0[0]
Bits									Destination
MAIN[9][12]	MAIN[8][12]	MAIN[7][12]	MAIN[6][12]	MAIN[7][13]	MAIN[9][13]	MAIN[7][14]	MAIN[4][13]	MAIN[9][14]	DBL_SW0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[0]
0	0	0	1	0	0	0	1	0	SNG_S0_S4
0	0	0	1	0	0	1	0	0	DBL_NW2[1]
0	0	0	1	0	1	0	0	0	DBL_SS2[0]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	SNG_W1[5]
0	0	1	0	0	0	0	1	0	SNG_S1[0]
0	0	1	0	0	0	1	0	0	DBL_WW2[0]
0	0	1	0	0	1	0	0	0	DBL_SW2[0]
0	0	1	0	1	0	0	0	0	OUT[22]
0	1	0	0	0	0	0	0	1	OUT[0]
0	1	0	0	0	0	0	1	0	OUT[18]
0	1	0	0	0	0	1	0	0	QUAD_NN4[1]
0	1	0	0	0	1	0	0	0	QUAD_SS4[0]
0	1	0	0	1	0	0	0	0	QUAD_WW4[1]
1	0	0	0	0	0	0	0	1	OUT[12]
1	0	0	0	0	0	0	1	0	OUT[4]
1	0	0	0	0	0	1	0	0	QUAD_NW4[1]
1	0	0	0	0	1	0	0	0	QUAD_SE4[0]
1	0	0	0	1	0	0	0	0	QUAD_SW4[0]

virtex6 INT switchbox INT muxes DBL_SW0[1]
Bits									Destination
MAIN[9][28]	MAIN[8][28]	MAIN[7][28]	MAIN[6][28]	MAIN[7][29]	MAIN[9][29]	MAIN[7][30]	MAIN[4][29]	MAIN[9][30]	DBL_SW0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[1]
0	0	0	1	0	0	0	1	0	SNG_S1[5]
0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	1	0	1	0	0	0	DBL_SS2[1]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	SNG_W1[6]
0	0	1	0	0	0	0	1	0	SNG_S1[1]
0	0	1	0	0	0	1	0	0	DBL_WW2[1]
0	0	1	0	0	1	0	0	0	DBL_SW2[1]
0	0	1	0	1	0	0	0	0	OUT[19]
0	1	0	0	0	0	0	0	1	OUT[5]
0	1	0	0	0	0	0	1	0	OUT[23]
0	1	0	0	0	0	1	0	0	QUAD_NN4[2]
0	1	0	0	0	1	0	0	0	QUAD_SS4[1]
0	1	0	0	1	0	0	0	0	QUAD_WW4[2]
1	0	0	0	0	0	0	0	1	OUT[9]
1	0	0	0	0	0	0	1	0	OUT[1]
1	0	0	0	0	0	1	0	0	QUAD_NW4[2]
1	0	0	0	0	1	0	0	0	QUAD_SE4[1]
1	0	0	0	1	0	0	0	0	QUAD_SW4[1]

virtex6 INT switchbox INT muxes DBL_SW0[2]
Bits									Destination
MAIN[9][44]	MAIN[8][44]	MAIN[7][44]	MAIN[6][44]	MAIN[7][45]	MAIN[9][45]	MAIN[7][46]	MAIN[4][45]	MAIN[9][46]	DBL_SW0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[2]
0	0	0	1	0	0	0	1	0	SNG_S1[6]
0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	1	0	1	0	0	0	DBL_SS2[2]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	SNG_W1[7]
0	0	1	0	0	0	0	1	0	SNG_S1[2]
0	0	1	0	0	0	1	0	0	DBL_WW2[2]
0	0	1	0	0	1	0	0	0	DBL_SW2[2]
0	0	1	0	1	0	0	0	0	OUT[20]
0	1	0	0	0	0	0	0	1	OUT[2]
0	1	0	0	0	0	0	1	0	OUT[16]
0	1	0	0	0	0	1	0	0	QUAD_NN4[3]
0	1	0	0	0	1	0	0	0	QUAD_SS4[2]
0	1	0	0	1	0	0	0	0	QUAD_WW4[3]
1	0	0	0	0	0	0	0	1	OUT[14]
1	0	0	0	0	0	0	1	0	OUT[6]
1	0	0	0	0	0	1	0	0	QUAD_NW4[3]
1	0	0	0	0	1	0	0	0	QUAD_SE4[2]
1	0	0	0	1	0	0	0	0	QUAD_SW4[2]

virtex6 INT switchbox INT muxes DBL_SW0[3]
Bits									Destination
MAIN[9][60]	MAIN[8][60]	MAIN[7][60]	MAIN[6][60]	MAIN[7][61]	MAIN[9][61]	MAIN[7][62]	MAIN[4][61]	MAIN[9][62]	DBL_SW0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[3]
0	0	0	1	0	0	0	1	0	SNG_S1[7]
0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	1	0	1	0	0	0	DBL_SS2[3]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	SNG_W1_S4
0	0	1	0	0	0	0	1	0	SNG_S1[3]
0	0	1	0	0	0	1	0	0	DBL_WW2[3]
0	0	1	0	0	1	0	0	0	DBL_SW2[3]
0	0	1	0	1	0	0	0	0	OUT[17]
0	1	0	0	0	0	0	0	1	OUT[7]
0	1	0	0	0	0	0	1	0	OUT[21]
0	1	0	0	0	0	1	0	0	QUAD_NN4_S0
0	1	0	0	0	1	0	0	0	QUAD_SS4[3]
0	1	0	0	1	0	0	0	0	QUAD_WW4_S0
1	0	0	0	0	0	0	0	1	OUT[11]
1	0	0	0	0	0	0	1	0	OUT[3]
1	0	0	0	0	0	1	0	0	QUAD_NW4_S0
1	0	0	0	0	1	0	0	0	QUAD_SE4[3]
1	0	0	0	1	0	0	0	0	QUAD_SW4[3]

virtex6 INT switchbox INT muxes DBL_SE0[0]
Bits									Destination
MAIN[9][8]	MAIN[8][8]	MAIN[7][8]	MAIN[6][8]	MAIN[7][9]	MAIN[7][10]	MAIN[9][9]	MAIN[9][10]	MAIN[4][9]	DBL_SE0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[0]
0	0	0	1	0	0	0	1	0	SNG_S0_S4
0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	1	0	1	0	0	0	DBL_SS2[0]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	SNG_E1[4]
0	0	1	0	0	0	0	1	0	SNG_S1[0]
0	0	1	0	0	0	1	0	0	DBL_EE2[0]
0	0	1	0	0	1	0	0	0	DBL_SW2[0]
0	0	1	0	1	0	0	0	0	OUT[22]
0	1	0	0	0	0	0	0	1	OUT[0]
0	1	0	0	0	0	0	1	0	OUT[18]
0	1	0	0	0	0	1	0	0	QUAD_EE4[0]
0	1	0	0	0	1	0	0	0	QUAD_WW4[1]
0	1	0	0	1	0	0	0	0	QUAD_SS4[0]
1	0	0	0	0	0	0	0	1	OUT[12]
1	0	0	0	0	0	0	1	0	OUT[4]
1	0	0	0	0	0	1	0	0	QUAD_NE4[0]
1	0	0	0	0	1	0	0	0	QUAD_SW4[0]
1	0	0	0	1	0	0	0	0	QUAD_SE4[0]

virtex6 INT switchbox INT muxes DBL_SE0[1]
Bits									Destination
MAIN[9][24]	MAIN[8][24]	MAIN[7][24]	MAIN[6][24]	MAIN[7][25]	MAIN[7][26]	MAIN[9][25]	MAIN[9][26]	MAIN[4][25]	DBL_SE0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[1]
0	0	0	1	0	0	0	1	0	SNG_S1[5]
0	0	0	1	0	0	1	0	0	DBL_SE2[1]
0	0	0	1	0	1	0	0	0	DBL_SS2[1]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	SNG_E1[5]
0	0	1	0	0	0	0	1	0	SNG_S1[1]
0	0	1	0	0	0	1	0	0	DBL_EE2[1]
0	0	1	0	0	1	0	0	0	DBL_SW2[1]
0	0	1	0	1	0	0	0	0	OUT[19]
0	1	0	0	0	0	0	0	1	OUT[5]
0	1	0	0	0	0	0	1	0	OUT[23]
0	1	0	0	0	0	1	0	0	QUAD_EE4[1]
0	1	0	0	0	1	0	0	0	QUAD_WW4[2]
0	1	0	0	1	0	0	0	0	QUAD_SS4[1]
1	0	0	0	0	0	0	0	1	OUT[9]
1	0	0	0	0	0	0	1	0	OUT[1]
1	0	0	0	0	0	1	0	0	QUAD_NE4[1]
1	0	0	0	0	1	0	0	0	QUAD_SW4[1]
1	0	0	0	1	0	0	0	0	QUAD_SE4[1]

virtex6 INT switchbox INT muxes DBL_SE0[2]
Bits									Destination
MAIN[9][40]	MAIN[8][40]	MAIN[7][40]	MAIN[6][40]	MAIN[7][41]	MAIN[7][42]	MAIN[9][41]	MAIN[9][42]	MAIN[4][41]	DBL_SE0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[2]
0	0	0	1	0	0	0	1	0	SNG_S1[6]
0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	1	0	1	0	0	0	DBL_SS2[2]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	SNG_E1[6]
0	0	1	0	0	0	0	1	0	SNG_S1[2]
0	0	1	0	0	0	1	0	0	DBL_EE2[2]
0	0	1	0	0	1	0	0	0	DBL_SW2[2]
0	0	1	0	1	0	0	0	0	OUT[20]
0	1	0	0	0	0	0	0	1	OUT[2]
0	1	0	0	0	0	0	1	0	OUT[16]
0	1	0	0	0	0	1	0	0	QUAD_EE4[2]
0	1	0	0	0	1	0	0	0	QUAD_WW4[3]
0	1	0	0	1	0	0	0	0	QUAD_SS4[2]
1	0	0	0	0	0	0	0	1	OUT[14]
1	0	0	0	0	0	0	1	0	OUT[6]
1	0	0	0	0	0	1	0	0	QUAD_NE4[2]
1	0	0	0	0	1	0	0	0	QUAD_SW4[2]
1	0	0	0	1	0	0	0	0	QUAD_SE4[2]

virtex6 INT switchbox INT muxes DBL_SE0[3]
Bits									Destination
MAIN[9][56]	MAIN[8][56]	MAIN[7][56]	MAIN[6][56]	MAIN[7][57]	MAIN[7][58]	MAIN[9][57]	MAIN[9][58]	MAIN[4][57]	DBL_SE0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[3]
0	0	0	1	0	0	0	1	0	SNG_S1[7]
0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	1	0	1	0	0	0	DBL_SS2[3]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	SNG_E1[7]
0	0	1	0	0	0	0	1	0	SNG_S1[3]
0	0	1	0	0	0	1	0	0	DBL_EE2[3]
0	0	1	0	0	1	0	0	0	DBL_SW2[3]
0	0	1	0	1	0	0	0	0	OUT[17]
0	1	0	0	0	0	0	0	1	OUT[7]
0	1	0	0	0	0	0	1	0	OUT[21]
0	1	0	0	0	0	1	0	0	QUAD_EE4[3]
0	1	0	0	0	1	0	0	0	QUAD_WW4_S0
0	1	0	0	1	0	0	0	0	QUAD_SS4[3]
1	0	0	0	0	0	0	0	1	OUT[11]
1	0	0	0	0	0	0	1	0	OUT[3]
1	0	0	0	0	0	1	0	0	QUAD_NE4[3]
1	0	0	0	0	1	0	0	0	QUAD_SW4[3]
1	0	0	0	1	0	0	0	0	QUAD_SE4[3]

virtex6 INT switchbox INT muxes DBL_NN0[0]
Bits									Destination
MAIN[8][3]	MAIN[9][3]	MAIN[7][3]	MAIN[6][3]	MAIN[6][2]	MAIN[8][2]	MAIN[6][1]	MAIN[4][3]	MAIN[8][1]	DBL_NN0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[4]
0	0	0	1	0	0	0	1	0	SNG_N1[0]
0	0	0	1	0	0	1	0	0	DBL_WW2_N3
0	0	0	1	0	1	0	0	0	DBL_NE2[0]
0	0	0	1	1	0	0	0	0	OUT[22]
0	0	1	0	0	0	0	0	1	SNG_W1_N3
0	0	1	0	0	0	0	1	0	SNG_N1[4]
0	0	1	0	0	0	1	0	0	DBL_NW2[0]
0	0	1	0	0	1	0	0	0	DBL_NN2[0]
0	0	1	0	1	0	0	0	0	OUT[8]
0	1	0	0	0	0	0	0	1	OUT[0]
0	1	0	0	0	0	0	1	0	OUT[18]
0	1	0	0	0	0	1	0	0	QUAD_WW4[0]
0	1	0	0	0	1	0	0	0	QUAD_EE4[0]
0	1	0	0	1	0	0	0	0	QUAD_NN4[0]
1	0	0	0	0	0	0	0	1	OUT[12]
1	0	0	0	0	0	0	1	0	OUT[4]
1	0	0	0	0	0	1	0	0	QUAD_SW4_N3
1	0	0	0	0	1	0	0	0	QUAD_NE4[0]
1	0	0	0	1	0	0	0	0	QUAD_NW4[0]

virtex6 INT switchbox INT muxes DBL_NN0[1]
Bits									Destination
MAIN[8][19]	MAIN[9][19]	MAIN[6][19]	MAIN[7][19]	MAIN[6][18]	MAIN[8][18]	MAIN[6][17]	MAIN[4][19]	MAIN[8][17]	DBL_NN0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[0]
0	0	0	1	0	0	0	1	0	SNG_N1[5]
0	0	0	1	0	0	1	0	0	DBL_NW2[1]
0	0	0	1	0	1	0	0	0	DBL_NN2[1]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	SNG_W1[5]
0	0	1	0	0	0	0	1	0	SNG_N1[1]
0	0	1	0	0	0	1	0	0	DBL_WW2[0]
0	0	1	0	0	1	0	0	0	DBL_NE2[1]
0	0	1	0	1	0	0	0	0	OUT[19]
0	1	0	0	0	0	0	0	1	OUT[5]
0	1	0	0	0	0	0	1	0	OUT[23]
0	1	0	0	0	0	1	0	0	QUAD_WW4[1]
0	1	0	0	0	1	0	0	0	QUAD_EE4[1]
0	1	0	0	1	0	0	0	0	QUAD_NN4[1]
1	0	0	0	0	0	0	0	1	OUT[9]
1	0	0	0	0	0	0	1	0	OUT[1]
1	0	0	0	0	0	1	0	0	QUAD_SW4[0]
1	0	0	0	0	1	0	0	0	QUAD_NE4[1]
1	0	0	0	1	0	0	0	0	QUAD_NW4[1]

virtex6 INT switchbox INT muxes DBL_NN0[2]
Bits									Destination
MAIN[8][35]	MAIN[9][35]	MAIN[6][35]	MAIN[7][35]	MAIN[6][34]	MAIN[8][34]	MAIN[6][33]	MAIN[4][35]	MAIN[8][33]	DBL_NN0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[1]
0	0	0	1	0	0	0	1	0	SNG_N1[6]
0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	1	0	1	0	0	0	DBL_NN2[2]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	SNG_W1[6]
0	0	1	0	0	0	0	1	0	SNG_N1[2]
0	0	1	0	0	0	1	0	0	DBL_WW2[1]
0	0	1	0	0	1	0	0	0	DBL_NE2[2]
0	0	1	0	1	0	0	0	0	OUT[20]
0	1	0	0	0	0	0	0	1	OUT[2]
0	1	0	0	0	0	0	1	0	OUT[16]
0	1	0	0	0	0	1	0	0	QUAD_WW4[2]
0	1	0	0	0	1	0	0	0	QUAD_EE4[2]
0	1	0	0	1	0	0	0	0	QUAD_NN4[2]
1	0	0	0	0	0	0	0	1	OUT[14]
1	0	0	0	0	0	0	1	0	OUT[6]
1	0	0	0	0	0	1	0	0	QUAD_SW4[1]
1	0	0	0	0	1	0	0	0	QUAD_NE4[2]
1	0	0	0	1	0	0	0	0	QUAD_NW4[2]

virtex6 INT switchbox INT muxes DBL_NN0[3]
Bits									Destination
MAIN[8][51]	MAIN[9][51]	MAIN[6][51]	MAIN[7][51]	MAIN[6][50]	MAIN[8][50]	MAIN[6][49]	MAIN[4][51]	MAIN[8][49]	DBL_NN0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[2]
0	0	0	1	0	0	0	1	0	SNG_N1[7]
0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	1	0	1	0	0	0	DBL_NN2[3]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	SNG_W1[7]
0	0	1	0	0	0	0	1	0	SNG_N0_N3
0	0	1	0	0	0	1	0	0	DBL_WW2[2]
0	0	1	0	0	1	0	0	0	DBL_NE2[3]
0	0	1	0	1	0	0	0	0	OUT[17]
0	1	0	0	0	0	0	0	1	OUT[7]
0	1	0	0	0	0	0	1	0	OUT[21]
0	1	0	0	0	0	1	0	0	QUAD_WW4[3]
0	1	0	0	0	1	0	0	0	QUAD_EE4[3]
0	1	0	0	1	0	0	0	0	QUAD_NN4[3]
1	0	0	0	0	0	0	0	1	OUT[11]
1	0	0	0	0	0	0	1	0	OUT[3]
1	0	0	0	0	0	1	0	0	QUAD_SW4[2]
1	0	0	0	0	1	0	0	0	QUAD_NE4[3]
1	0	0	0	1	0	0	0	0	QUAD_NW4[3]

virtex6 INT switchbox INT muxes DBL_NW0[0]
Bits									Destination
MAIN[9][0]	MAIN[8][0]	MAIN[6][0]	MAIN[7][0]	MAIN[7][1]	MAIN[7][2]	MAIN[9][1]	MAIN[9][2]	MAIN[4][1]	DBL_NW0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[4]
0	0	0	1	0	0	0	1	0	SNG_N1[0]
0	0	0	1	0	0	1	0	0	DBL_WW2_N3
0	0	0	1	0	1	0	0	0	DBL_NE2[0]
0	0	0	1	1	0	0	0	0	OUT[22]
0	0	1	0	0	0	0	0	1	SNG_W1_N3
0	0	1	0	0	0	0	1	0	SNG_N1[4]
0	0	1	0	0	0	1	0	0	DBL_NW2[0]
0	0	1	0	0	1	0	0	0	DBL_NN2[0]
0	0	1	0	1	0	0	0	0	OUT[8]
0	1	0	0	0	0	0	0	1	OUT[0]
0	1	0	0	0	0	0	1	0	OUT[18]
0	1	0	0	0	0	1	0	0	QUAD_WW4[0]
0	1	0	0	0	1	0	0	0	QUAD_EE4[0]
0	1	0	0	1	0	0	0	0	QUAD_NN4[0]
1	0	0	0	0	0	0	0	1	OUT[12]
1	0	0	0	0	0	0	1	0	OUT[4]
1	0	0	0	0	0	1	0	0	QUAD_SW4_N3
1	0	0	0	0	1	0	0	0	QUAD_NE4[0]
1	0	0	0	1	0	0	0	0	QUAD_NW4[0]

virtex6 INT switchbox INT muxes DBL_NW0[1]
Bits									Destination
MAIN[9][16]	MAIN[8][16]	MAIN[7][16]	MAIN[6][16]	MAIN[7][17]	MAIN[7][18]	MAIN[9][17]	MAIN[9][18]	MAIN[4][17]	DBL_NW0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[0]
0	0	0	1	0	0	0	1	0	SNG_N1[5]
0	0	0	1	0	0	1	0	0	DBL_NW2[1]
0	0	0	1	0	1	0	0	0	DBL_NN2[1]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	SNG_W1[5]
0	0	1	0	0	0	0	1	0	SNG_N1[1]
0	0	1	0	0	0	1	0	0	DBL_WW2[0]
0	0	1	0	0	1	0	0	0	DBL_NE2[1]
0	0	1	0	1	0	0	0	0	OUT[19]
0	1	0	0	0	0	0	0	1	OUT[5]
0	1	0	0	0	0	0	1	0	OUT[23]
0	1	0	0	0	0	1	0	0	QUAD_WW4[1]
0	1	0	0	0	1	0	0	0	QUAD_EE4[1]
0	1	0	0	1	0	0	0	0	QUAD_NN4[1]
1	0	0	0	0	0	0	0	1	OUT[9]
1	0	0	0	0	0	0	1	0	OUT[1]
1	0	0	0	0	0	1	0	0	QUAD_SW4[0]
1	0	0	0	0	1	0	0	0	QUAD_NE4[1]
1	0	0	0	1	0	0	0	0	QUAD_NW4[1]

virtex6 INT switchbox INT muxes DBL_NW0[2]
Bits									Destination
MAIN[9][32]	MAIN[8][32]	MAIN[7][32]	MAIN[6][32]	MAIN[7][33]	MAIN[7][34]	MAIN[9][33]	MAIN[9][34]	MAIN[4][33]	DBL_NW0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[1]
0	0	0	1	0	0	0	1	0	SNG_N1[6]
0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	1	0	1	0	0	0	DBL_NN2[2]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	SNG_W1[6]
0	0	1	0	0	0	0	1	0	SNG_N1[2]
0	0	1	0	0	0	1	0	0	DBL_WW2[1]
0	0	1	0	0	1	0	0	0	DBL_NE2[2]
0	0	1	0	1	0	0	0	0	OUT[20]
0	1	0	0	0	0	0	0	1	OUT[2]
0	1	0	0	0	0	0	1	0	OUT[16]
0	1	0	0	0	0	1	0	0	QUAD_WW4[2]
0	1	0	0	0	1	0	0	0	QUAD_EE4[2]
0	1	0	0	1	0	0	0	0	QUAD_NN4[2]
1	0	0	0	0	0	0	0	1	OUT[14]
1	0	0	0	0	0	0	1	0	OUT[6]
1	0	0	0	0	0	1	0	0	QUAD_SW4[1]
1	0	0	0	0	1	0	0	0	QUAD_NE4[2]
1	0	0	0	1	0	0	0	0	QUAD_NW4[2]

virtex6 INT switchbox INT muxes DBL_NW0[3]
Bits									Destination
MAIN[9][48]	MAIN[8][48]	MAIN[7][48]	MAIN[6][48]	MAIN[7][49]	MAIN[7][50]	MAIN[9][49]	MAIN[9][50]	MAIN[4][49]	DBL_NW0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_W1[2]
0	0	0	1	0	0	0	1	0	SNG_N1[7]
0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	1	0	1	0	0	0	DBL_NN2[3]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	SNG_W1[7]
0	0	1	0	0	0	0	1	0	SNG_N0_N3
0	0	1	0	0	0	1	0	0	DBL_WW2[2]
0	0	1	0	0	1	0	0	0	DBL_NE2[3]
0	0	1	0	1	0	0	0	0	OUT[17]
0	1	0	0	0	0	0	0	1	OUT[7]
0	1	0	0	0	0	0	1	0	OUT[21]
0	1	0	0	0	0	1	0	0	QUAD_WW4[3]
0	1	0	0	0	1	0	0	0	QUAD_EE4[3]
0	1	0	0	1	0	0	0	0	QUAD_NN4[3]
1	0	0	0	0	0	0	0	1	OUT[11]
1	0	0	0	0	0	0	1	0	OUT[3]
1	0	0	0	0	0	1	0	0	QUAD_SW4[2]
1	0	0	0	0	1	0	0	0	QUAD_NE4[3]
1	0	0	0	1	0	0	0	0	QUAD_NW4[3]

virtex6 INT switchbox INT muxes DBL_NE0[0]
Bits									Destination
MAIN[9][4]	MAIN[8][4]	MAIN[7][4]	MAIN[6][4]	MAIN[7][5]	MAIN[9][5]	MAIN[7][6]	MAIN[4][5]	MAIN[9][6]	DBL_NE0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[0]
0	0	0	1	0	0	0	1	0	SNG_N1[4]
0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	1	0	1	0	0	0	DBL_NN2[0]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	SNG_E1[4]
0	0	1	0	0	0	0	1	0	SNG_N1[0]
0	0	1	0	0	0	1	0	0	DBL_EE2[0]
0	0	1	0	0	1	0	0	0	DBL_NE2[0]
0	0	1	0	1	0	0	0	0	OUT[22]
0	1	0	0	0	0	0	0	1	OUT[0]
0	1	0	0	0	0	0	1	0	OUT[18]
0	1	0	0	0	0	1	0	0	QUAD_SS4[0]
0	1	0	0	0	1	0	0	0	QUAD_NN4[0]
0	1	0	0	1	0	0	0	0	QUAD_EE4[0]
1	0	0	0	0	0	0	0	1	OUT[12]
1	0	0	0	0	0	0	1	0	OUT[4]
1	0	0	0	0	0	1	0	0	QUAD_SE4[0]
1	0	0	0	0	1	0	0	0	QUAD_NW4[0]
1	0	0	0	1	0	0	0	0	QUAD_NE4[0]

virtex6 INT switchbox INT muxes DBL_NE0[1]
Bits									Destination
MAIN[9][20]	MAIN[8][20]	MAIN[7][20]	MAIN[6][20]	MAIN[7][21]	MAIN[9][21]	MAIN[7][22]	MAIN[4][21]	MAIN[9][22]	DBL_NE0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[1]
0	0	0	1	0	0	0	1	0	SNG_N1[5]
0	0	0	1	0	0	1	0	0	DBL_SE2[1]
0	0	0	1	0	1	0	0	0	DBL_NN2[1]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	SNG_E1[5]
0	0	1	0	0	0	0	1	0	SNG_N1[1]
0	0	1	0	0	0	1	0	0	DBL_EE2[1]
0	0	1	0	0	1	0	0	0	DBL_NE2[1]
0	0	1	0	1	0	0	0	0	OUT[19]
0	1	0	0	0	0	0	0	1	OUT[5]
0	1	0	0	0	0	0	1	0	OUT[23]
0	1	0	0	0	0	1	0	0	QUAD_SS4[1]
0	1	0	0	0	1	0	0	0	QUAD_NN4[1]
0	1	0	0	1	0	0	0	0	QUAD_EE4[1]
1	0	0	0	0	0	0	0	1	OUT[9]
1	0	0	0	0	0	0	1	0	OUT[1]
1	0	0	0	0	0	1	0	0	QUAD_SE4[1]
1	0	0	0	0	1	0	0	0	QUAD_NW4[1]
1	0	0	0	1	0	0	0	0	QUAD_NE4[1]

virtex6 INT switchbox INT muxes DBL_NE0[2]
Bits									Destination
MAIN[9][36]	MAIN[8][36]	MAIN[7][36]	MAIN[6][36]	MAIN[7][37]	MAIN[9][37]	MAIN[7][38]	MAIN[4][37]	MAIN[9][38]	DBL_NE0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[2]
0	0	0	1	0	0	0	1	0	SNG_N1[6]
0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	1	0	1	0	0	0	DBL_NN2[2]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	SNG_E1[6]
0	0	1	0	0	0	0	1	0	SNG_N1[2]
0	0	1	0	0	0	1	0	0	DBL_EE2[2]
0	0	1	0	0	1	0	0	0	DBL_NE2[2]
0	0	1	0	1	0	0	0	0	OUT[20]
0	1	0	0	0	0	0	0	1	OUT[2]
0	1	0	0	0	0	0	1	0	OUT[16]
0	1	0	0	0	0	1	0	0	QUAD_SS4[2]
0	1	0	0	0	1	0	0	0	QUAD_NN4[2]
0	1	0	0	1	0	0	0	0	QUAD_EE4[2]
1	0	0	0	0	0	0	0	1	OUT[14]
1	0	0	0	0	0	0	1	0	OUT[6]
1	0	0	0	0	0	1	0	0	QUAD_SE4[2]
1	0	0	0	0	1	0	0	0	QUAD_NW4[2]
1	0	0	0	1	0	0	0	0	QUAD_NE4[2]

virtex6 INT switchbox INT muxes DBL_NE0[3]
Bits									Destination
MAIN[9][52]	MAIN[8][52]	MAIN[7][52]	MAIN[6][52]	MAIN[7][53]	MAIN[9][53]	MAIN[7][54]	MAIN[4][53]	MAIN[9][54]	DBL_NE0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	SNG_E1[3]
0	0	0	1	0	0	0	1	0	SNG_N1[7]
0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	1	0	1	0	0	0	DBL_NN2[3]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	SNG_E1[7]
0	0	1	0	0	0	0	1	0	SNG_N0_N3
0	0	1	0	0	0	1	0	0	DBL_EE2[3]
0	0	1	0	0	1	0	0	0	DBL_NE2[3]
0	0	1	0	1	0	0	0	0	OUT[17]
0	1	0	0	0	0	0	0	1	OUT[7]
0	1	0	0	0	0	0	1	0	OUT[21]
0	1	0	0	0	0	1	0	0	QUAD_SS4[3]
0	1	0	0	0	1	0	0	0	QUAD_NN4[3]
0	1	0	0	1	0	0	0	0	QUAD_EE4[3]
1	0	0	0	0	0	0	0	1	OUT[11]
1	0	0	0	0	0	0	1	0	OUT[3]
1	0	0	0	0	0	1	0	0	QUAD_SE4[3]
1	0	0	0	0	1	0	0	0	QUAD_NW4[3]
1	0	0	0	1	0	0	0	0	QUAD_NE4[3]

virtex6 INT switchbox INT muxes QUAD_WW0[0]
Bits									Destination
MAIN[3][0]	MAIN[2][0]	MAIN[1][0]	MAIN[0][0]	MAIN[3][2]	MAIN[1][1]	MAIN[1][2]	MAIN[5][0]	MAIN[3][1]	QUAD_WW0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2_N3
0	0	0	1	0	0	0	1	0	DBL_SS2_N3
0	0	0	1	0	0	1	0	0	DBL_NN2[0]
0	0	0	1	0	1	0	0	0	OUT[8]
0	0	0	1	1	0	0	0	0	OUT[12]
0	0	1	0	0	0	0	0	1	DBL_NW2[0]
0	0	1	0	0	0	0	1	0	DBL_SW2_N3
0	0	1	0	0	0	1	0	0	DBL_NE2[0]
0	0	1	0	0	1	0	0	0	OUT[4]
0	0	1	0	1	0	0	0	0	OUT[0]
0	1	0	0	0	0	0	0	1	QUAD_WW4[0]
0	1	0	0	0	0	0	1	0	QUAD_SW4_N3
0	1	0	0	0	0	1	0	0	QUAD_NE4[0]
0	1	0	0	0	1	0	0	0	LH[16]
0	1	0	0	1	0	0	0	0	LV[0]
1	0	0	0	0	0	0	0	1	QUAD_NW4[0]
1	0	0	0	0	0	0	1	0	QUAD_SS4_N3
1	0	0	0	0	0	1	0	0	QUAD_NN4[0]
1	0	0	0	0	1	0	0	0	OUT[18]
1	0	0	0	1	0	0	0	0	OUT[22]

virtex6 INT switchbox INT muxes QUAD_WW0[1]
Bits									Destination
MAIN[3][16]	MAIN[2][16]	MAIN[1][16]	MAIN[0][16]	MAIN[3][18]	MAIN[1][17]	MAIN[1][18]	MAIN[5][16]	MAIN[3][17]	QUAD_WW0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[0]
0	0	0	1	0	0	0	1	0	DBL_SS2[0]
0	0	0	1	0	0	1	0	0	DBL_NN2[1]
0	0	0	1	0	1	0	0	0	OUT[13]
0	0	0	1	1	0	0	0	0	OUT[9]
0	0	1	0	0	0	0	0	1	DBL_NW2[1]
0	0	1	0	0	0	0	1	0	DBL_SW2[0]
0	0	1	0	0	0	1	0	0	DBL_NE2[1]
0	0	1	0	0	1	0	0	0	OUT[1]
0	0	1	0	1	0	0	0	0	OUT[5]
0	1	0	0	0	0	0	0	1	QUAD_WW4[1]
0	1	0	0	0	0	0	1	0	QUAD_SW4[0]
0	1	0	0	0	0	1	0	0	QUAD_NE4[1]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[1]
1	0	0	0	0	0	0	1	0	QUAD_SS4[0]
1	0	0	0	0	0	1	0	0	QUAD_NN4[1]
1	0	0	0	0	1	0	0	0	OUT[23]
1	0	0	0	1	0	0	0	0	OUT[19]

virtex6 INT switchbox INT muxes QUAD_WW0[2]
Bits									Destination
MAIN[3][32]	MAIN[2][32]	MAIN[1][32]	MAIN[0][32]	MAIN[3][34]	MAIN[1][33]	MAIN[1][34]	MAIN[5][32]	MAIN[3][33]	QUAD_WW0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[1]
0	0	0	1	0	0	0	1	0	DBL_SS2[1]
0	0	0	1	0	0	1	0	0	DBL_NN2[2]
0	0	0	1	0	1	0	0	0	OUT[10]
0	0	0	1	1	0	0	0	0	OUT[14]
0	0	1	0	0	0	0	0	1	DBL_NW2[2]
0	0	1	0	0	0	0	1	0	DBL_SW2[1]
0	0	1	0	0	0	1	0	0	DBL_NE2[2]
0	0	1	0	0	1	0	0	0	OUT[6]
0	0	1	0	1	0	0	0	0	OUT[2]
0	1	0	0	0	0	0	0	1	QUAD_WW4[2]
0	1	0	0	0	0	0	1	0	QUAD_SW4[1]
0	1	0	0	0	0	1	0	0	QUAD_NE4[2]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[2]
1	0	0	0	0	0	0	1	0	QUAD_SS4[1]
1	0	0	0	0	0	1	0	0	QUAD_NN4[2]
1	0	0	0	0	1	0	0	0	OUT[16]
1	0	0	0	1	0	0	0	0	OUT[20]

virtex6 INT switchbox INT muxes QUAD_WW0[3]
Bits									Destination
MAIN[3][48]	MAIN[2][48]	MAIN[1][48]	MAIN[0][48]	MAIN[1][49]	MAIN[3][50]	MAIN[1][50]	MAIN[5][48]	MAIN[3][49]	QUAD_WW0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[2]
0	0	0	1	0	0	0	1	0	DBL_SS2[2]
0	0	0	1	0	0	1	0	0	DBL_NN2[3]
0	0	0	1	0	1	0	0	0	OUT[11]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	DBL_NW2[3]
0	0	1	0	0	0	0	1	0	DBL_SW2[2]
0	0	1	0	0	0	1	0	0	DBL_NE2[3]
0	0	1	0	0	1	0	0	0	OUT[7]
0	0	1	0	1	0	0	0	0	OUT[3]
0	1	0	0	0	0	0	0	1	QUAD_WW4[3]
0	1	0	0	0	0	0	1	0	QUAD_SW4[2]
0	1	0	0	0	0	1	0	0	QUAD_NE4[3]
0	1	0	0	0	1	0	0	0	LH[0]
0	1	0	0	1	0	0	0	0	LV[16]
1	0	0	0	0	0	0	0	1	QUAD_NW4[3]
1	0	0	0	0	0	0	1	0	QUAD_SS4[2]
1	0	0	0	0	0	1	0	0	QUAD_NN4[3]
1	0	0	0	0	1	0	0	0	OUT[17]
1	0	0	0	1	0	0	0	0	OUT[21]

virtex6 INT switchbox INT muxes QUAD_EE0[0]
Bits									Destination
MAIN[3][8]	MAIN[2][8]	MAIN[1][8]	MAIN[0][8]	MAIN[3][10]	MAIN[1][9]	MAIN[5][8]	MAIN[1][10]	MAIN[3][9]	QUAD_EE0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_EE2[0]
0	0	0	1	0	0	0	1	0	DBL_SS2[0]
0	0	0	1	0	0	1	0	0	DBL_NN2[0]
0	0	0	1	0	1	0	0	0	OUT[8]
0	0	0	1	1	0	0	0	0	OUT[12]
0	0	1	0	0	0	0	0	1	DBL_SE2[0]
0	0	1	0	0	0	0	1	0	DBL_SW2[0]
0	0	1	0	0	0	1	0	0	DBL_NE2[0]
0	0	1	0	0	1	0	0	0	OUT[4]
0	0	1	0	1	0	0	0	0	OUT[0]
0	1	0	0	0	0	0	0	1	QUAD_EE4[0]
0	1	0	0	0	0	0	1	0	QUAD_SW4[0]
0	1	0	0	0	0	1	0	0	QUAD_NE4[0]
0	1	0	0	0	1	0	0	0	LH[16]
0	1	0	0	1	0	0	0	0	LV[0]
1	0	0	0	0	0	0	0	1	QUAD_SE4[0]
1	0	0	0	0	0	0	1	0	QUAD_SS4[0]
1	0	0	0	0	0	1	0	0	QUAD_NN4[0]
1	0	0	0	0	1	0	0	0	OUT[18]
1	0	0	0	1	0	0	0	0	OUT[22]

virtex6 INT switchbox INT muxes QUAD_EE0[1]
Bits									Destination
MAIN[3][24]	MAIN[2][24]	MAIN[1][24]	MAIN[0][24]	MAIN[3][26]	MAIN[1][25]	MAIN[5][24]	MAIN[1][26]	MAIN[3][25]	QUAD_EE0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_EE2[1]
0	0	0	1	0	0	0	1	0	DBL_SS2[1]
0	0	0	1	0	0	1	0	0	DBL_NN2[1]
0	0	0	1	0	1	0	0	0	OUT[13]
0	0	0	1	1	0	0	0	0	OUT[9]
0	0	1	0	0	0	0	0	1	DBL_SE2[1]
0	0	1	0	0	0	0	1	0	DBL_SW2[1]
0	0	1	0	0	0	1	0	0	DBL_NE2[1]
0	0	1	0	0	1	0	0	0	OUT[1]
0	0	1	0	1	0	0	0	0	OUT[5]
0	1	0	0	0	0	0	0	1	QUAD_EE4[1]
0	1	0	0	0	0	0	1	0	QUAD_SW4[1]
0	1	0	0	0	0	1	0	0	QUAD_NE4[1]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_SE4[1]
1	0	0	0	0	0	0	1	0	QUAD_SS4[1]
1	0	0	0	0	0	1	0	0	QUAD_NN4[1]
1	0	0	0	0	1	0	0	0	OUT[23]
1	0	0	0	1	0	0	0	0	OUT[19]

virtex6 INT switchbox INT muxes QUAD_EE0[2]
Bits									Destination
MAIN[3][40]	MAIN[2][40]	MAIN[1][40]	MAIN[0][40]	MAIN[3][42]	MAIN[1][41]	MAIN[5][40]	MAIN[1][42]	MAIN[3][41]	QUAD_EE0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_EE2[2]
0	0	0	1	0	0	0	1	0	DBL_SS2[2]
0	0	0	1	0	0	1	0	0	DBL_NN2[2]
0	0	0	1	0	1	0	0	0	OUT[10]
0	0	0	1	1	0	0	0	0	OUT[14]
0	0	1	0	0	0	0	0	1	DBL_SE2[2]
0	0	1	0	0	0	0	1	0	DBL_SW2[2]
0	0	1	0	0	0	1	0	0	DBL_NE2[2]
0	0	1	0	0	1	0	0	0	OUT[6]
0	0	1	0	1	0	0	0	0	OUT[2]
0	1	0	0	0	0	0	0	1	QUAD_EE4[2]
0	1	0	0	0	0	0	1	0	QUAD_SW4[2]
0	1	0	0	0	0	1	0	0	QUAD_NE4[2]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_SE4[2]
1	0	0	0	0	0	0	1	0	QUAD_SS4[2]
1	0	0	0	0	0	1	0	0	QUAD_NN4[2]
1	0	0	0	0	1	0	0	0	OUT[16]
1	0	0	0	1	0	0	0	0	OUT[20]

virtex6 INT switchbox INT muxes QUAD_EE0[3]
Bits									Destination
MAIN[3][56]	MAIN[2][56]	MAIN[1][56]	MAIN[0][56]	MAIN[1][57]	MAIN[3][58]	MAIN[5][56]	MAIN[1][58]	MAIN[3][57]	QUAD_EE0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_EE2[3]
0	0	0	1	0	0	0	1	0	DBL_SS2[3]
0	0	0	1	0	0	1	0	0	DBL_NN2[3]
0	0	0	1	0	1	0	0	0	OUT[11]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	DBL_SE2[3]
0	0	1	0	0	0	0	1	0	DBL_SW2[3]
0	0	1	0	0	0	1	0	0	DBL_NE2[3]
0	0	1	0	0	1	0	0	0	OUT[7]
0	0	1	0	1	0	0	0	0	OUT[3]
0	1	0	0	0	0	0	0	1	QUAD_EE4[3]
0	1	0	0	0	0	0	1	0	QUAD_SW4[3]
0	1	0	0	0	0	1	0	0	QUAD_NE4[3]
0	1	0	0	0	1	0	0	0	LH[0]
0	1	0	0	1	0	0	0	0	LV[16]
1	0	0	0	0	0	0	0	1	QUAD_SE4[3]
1	0	0	0	0	0	0	1	0	QUAD_SS4[3]
1	0	0	0	0	0	1	0	0	QUAD_NN4[3]
1	0	0	0	0	1	0	0	0	OUT[17]
1	0	0	0	1	0	0	0	0	OUT[21]

virtex6 INT switchbox INT muxes QUAD_SS0[0]
Bits									Destination
MAIN[3][12]	MAIN[2][12]	MAIN[1][12]	MAIN[0][12]	MAIN[3][14]	MAIN[1][13]	MAIN[3][13]	MAIN[5][12]	MAIN[1][14]	QUAD_SS0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[0]
0	0	0	1	0	0	0	1	0	DBL_EE2[0]
0	0	0	1	0	0	1	0	0	DBL_SS2[0]
0	0	0	1	0	1	0	0	0	OUT[12]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	DBL_NW2[1]
0	0	1	0	0	0	0	1	0	DBL_SE2[0]
0	0	1	0	0	0	1	0	0	DBL_SW2[0]
0	0	1	0	0	1	0	0	0	OUT[0]
0	0	1	0	1	0	0	0	0	OUT[4]
0	1	0	0	0	0	0	0	1	QUAD_WW4[1]
0	1	0	0	0	0	0	1	0	QUAD_EE4[0]
0	1	0	0	0	0	1	0	0	QUAD_SW4[0]
0	1	0	0	0	1	0	0	0	LH[16]
0	1	0	0	1	0	0	0	0	LV[0]
1	0	0	0	0	0	0	0	1	QUAD_NW4[1]
1	0	0	0	0	0	0	1	0	QUAD_SE4[0]
1	0	0	0	0	0	1	0	0	QUAD_SS4[0]
1	0	0	0	0	1	0	0	0	OUT[22]
1	0	0	0	1	0	0	0	0	OUT[18]

virtex6 INT switchbox INT muxes QUAD_SS0[1]
Bits									Destination
MAIN[3][28]	MAIN[2][28]	MAIN[1][28]	MAIN[0][28]	MAIN[3][30]	MAIN[1][29]	MAIN[3][29]	MAIN[5][28]	MAIN[1][30]	QUAD_SS0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[1]
0	0	0	1	0	0	0	1	0	DBL_EE2[1]
0	0	0	1	0	0	1	0	0	DBL_SS2[1]
0	0	0	1	0	1	0	0	0	OUT[9]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	DBL_NW2[2]
0	0	1	0	0	0	0	1	0	DBL_SE2[1]
0	0	1	0	0	0	1	0	0	DBL_SW2[1]
0	0	1	0	0	1	0	0	0	OUT[5]
0	0	1	0	1	0	0	0	0	OUT[1]
0	1	0	0	0	0	0	0	1	QUAD_WW4[2]
0	1	0	0	0	0	0	1	0	QUAD_EE4[1]
0	1	0	0	0	0	1	0	0	QUAD_SW4[1]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[2]
1	0	0	0	0	0	0	1	0	QUAD_SE4[1]
1	0	0	0	0	0	1	0	0	QUAD_SS4[1]
1	0	0	0	0	1	0	0	0	OUT[19]
1	0	0	0	1	0	0	0	0	OUT[23]

virtex6 INT switchbox INT muxes QUAD_SS0[2]
Bits									Destination
MAIN[3][44]	MAIN[2][44]	MAIN[1][44]	MAIN[0][44]	MAIN[3][46]	MAIN[1][45]	MAIN[3][45]	MAIN[5][44]	MAIN[1][46]	QUAD_SS0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[2]
0	0	0	1	0	0	0	1	0	DBL_EE2[2]
0	0	0	1	0	0	1	0	0	DBL_SS2[2]
0	0	0	1	0	1	0	0	0	OUT[14]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	DBL_NW2[3]
0	0	1	0	0	0	0	1	0	DBL_SE2[2]
0	0	1	0	0	0	1	0	0	DBL_SW2[2]
0	0	1	0	0	1	0	0	0	OUT[2]
0	0	1	0	1	0	0	0	0	OUT[6]
0	1	0	0	0	0	0	0	1	QUAD_WW4[3]
0	1	0	0	0	0	0	1	0	QUAD_EE4[2]
0	1	0	0	0	0	1	0	0	QUAD_SW4[2]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[3]
1	0	0	0	0	0	0	1	0	QUAD_SE4[2]
1	0	0	0	0	0	1	0	0	QUAD_SS4[2]
1	0	0	0	0	1	0	0	0	OUT[20]
1	0	0	0	1	0	0	0	0	OUT[16]

virtex6 INT switchbox INT muxes QUAD_SS0[3]
Bits									Destination
MAIN[3][60]	MAIN[2][60]	MAIN[1][60]	MAIN[0][60]	MAIN[1][61]	MAIN[3][62]	MAIN[3][61]	MAIN[5][60]	MAIN[1][62]	QUAD_SS0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[3]
0	0	0	1	0	0	0	1	0	DBL_EE2[3]
0	0	0	1	0	0	1	0	0	DBL_SS2[3]
0	0	0	1	0	1	0	0	0	OUT[15]
0	0	0	1	1	0	0	0	0	OUT[11]
0	0	1	0	0	0	0	0	1	DBL_NW2_S0
0	0	1	0	0	0	0	1	0	DBL_SE2[3]
0	0	1	0	0	0	1	0	0	DBL_SW2[3]
0	0	1	0	0	1	0	0	0	OUT[3]
0	0	1	0	1	0	0	0	0	OUT[7]
0	1	0	0	0	0	0	0	1	QUAD_WW4_S0
0	1	0	0	0	0	0	1	0	QUAD_EE4[3]
0	1	0	0	0	0	1	0	0	QUAD_SW4[3]
0	1	0	0	0	1	0	0	0	LH[0]
0	1	0	0	1	0	0	0	0	LV[16]
1	0	0	0	0	0	0	0	1	QUAD_NW4_S0
1	0	0	0	0	0	0	1	0	QUAD_SE4[3]
1	0	0	0	0	0	1	0	0	QUAD_SS4[3]
1	0	0	0	0	1	0	0	0	OUT[21]
1	0	0	0	1	0	0	0	0	OUT[17]

virtex6 INT switchbox INT muxes QUAD_SW0[0]
Bits									Destination
MAIN[2][15]	MAIN[3][15]	MAIN[0][15]	MAIN[1][15]	MAIN[0][14]	MAIN[2][13]	MAIN[2][14]	MAIN[0][13]	MAIN[5][14]	QUAD_SW0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[0]
0	0	0	1	0	0	0	1	0	DBL_EE2[0]
0	0	0	1	0	0	1	0	0	DBL_SS2[0]
0	0	0	1	0	1	0	0	0	OUT[12]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	DBL_NW2[1]
0	0	1	0	0	0	0	1	0	DBL_SE2[0]
0	0	1	0	0	0	1	0	0	DBL_SW2[0]
0	0	1	0	0	1	0	0	0	OUT[0]
0	0	1	0	1	0	0	0	0	OUT[4]
0	1	0	0	0	0	0	0	1	QUAD_WW4[1]
0	1	0	0	0	0	0	1	0	QUAD_EE4[0]
0	1	0	0	0	0	1	0	0	QUAD_SW4[0]
0	1	0	0	0	1	0	0	0	LH[16]
0	1	0	0	1	0	0	0	0	LV[0]
1	0	0	0	0	0	0	0	1	QUAD_NW4[1]
1	0	0	0	0	0	0	1	0	QUAD_SE4[0]
1	0	0	0	0	0	1	0	0	QUAD_SS4[0]
1	0	0	0	0	1	0	0	0	OUT[22]
1	0	0	0	1	0	0	0	0	OUT[18]

virtex6 INT switchbox INT muxes QUAD_SW0[1]
Bits									Destination
MAIN[2][31]	MAIN[3][31]	MAIN[0][31]	MAIN[1][31]	MAIN[0][30]	MAIN[2][29]	MAIN[2][30]	MAIN[0][29]	MAIN[5][30]	QUAD_SW0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[1]
0	0	0	1	0	0	0	1	0	DBL_EE2[1]
0	0	0	1	0	0	1	0	0	DBL_SS2[1]
0	0	0	1	0	1	0	0	0	OUT[9]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	DBL_NW2[2]
0	0	1	0	0	0	0	1	0	DBL_SE2[1]
0	0	1	0	0	0	1	0	0	DBL_SW2[1]
0	0	1	0	0	1	0	0	0	OUT[5]
0	0	1	0	1	0	0	0	0	OUT[1]
0	1	0	0	0	0	0	0	1	QUAD_WW4[2]
0	1	0	0	0	0	0	1	0	QUAD_EE4[1]
0	1	0	0	0	0	1	0	0	QUAD_SW4[1]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[2]
1	0	0	0	0	0	0	1	0	QUAD_SE4[1]
1	0	0	0	0	0	1	0	0	QUAD_SS4[1]
1	0	0	0	0	1	0	0	0	OUT[19]
1	0	0	0	1	0	0	0	0	OUT[23]

virtex6 INT switchbox INT muxes QUAD_SW0[2]
Bits									Destination
MAIN[2][47]	MAIN[3][47]	MAIN[0][47]	MAIN[1][47]	MAIN[0][46]	MAIN[2][45]	MAIN[2][46]	MAIN[0][45]	MAIN[5][46]	QUAD_SW0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[2]
0	0	0	1	0	0	0	1	0	DBL_EE2[2]
0	0	0	1	0	0	1	0	0	DBL_SS2[2]
0	0	0	1	0	1	0	0	0	OUT[14]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	DBL_NW2[3]
0	0	1	0	0	0	0	1	0	DBL_SE2[2]
0	0	1	0	0	0	1	0	0	DBL_SW2[2]
0	0	1	0	0	1	0	0	0	OUT[2]
0	0	1	0	1	0	0	0	0	OUT[6]
0	1	0	0	0	0	0	0	1	QUAD_WW4[3]
0	1	0	0	0	0	0	1	0	QUAD_EE4[2]
0	1	0	0	0	0	1	0	0	QUAD_SW4[2]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[3]
1	0	0	0	0	0	0	1	0	QUAD_SE4[2]
1	0	0	0	0	0	1	0	0	QUAD_SS4[2]
1	0	0	0	0	1	0	0	0	OUT[20]
1	0	0	0	1	0	0	0	0	OUT[16]

virtex6 INT switchbox INT muxes QUAD_SW0[3]
Bits									Destination
MAIN[2][63]	MAIN[3][63]	MAIN[0][63]	MAIN[1][63]	MAIN[2][61]	MAIN[0][62]	MAIN[2][62]	MAIN[0][61]	MAIN[5][62]	QUAD_SW0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[3]
0	0	0	1	0	0	0	1	0	DBL_EE2[3]
0	0	0	1	0	0	1	0	0	DBL_SS2[3]
0	0	0	1	0	1	0	0	0	OUT[15]
0	0	0	1	1	0	0	0	0	OUT[11]
0	0	1	0	0	0	0	0	1	DBL_NW2_S0
0	0	1	0	0	0	0	1	0	DBL_SE2[3]
0	0	1	0	0	0	1	0	0	DBL_SW2[3]
0	0	1	0	0	1	0	0	0	OUT[3]
0	0	1	0	1	0	0	0	0	OUT[7]
0	1	0	0	0	0	0	0	1	QUAD_WW4_S0
0	1	0	0	0	0	0	1	0	QUAD_EE4[3]
0	1	0	0	0	0	1	0	0	QUAD_SW4[3]
0	1	0	0	0	1	0	0	0	LH[0]
0	1	0	0	1	0	0	0	0	LV[16]
1	0	0	0	0	0	0	0	1	QUAD_NW4_S0
1	0	0	0	0	0	0	1	0	QUAD_SE4[3]
1	0	0	0	0	0	1	0	0	QUAD_SS4[3]
1	0	0	0	0	1	0	0	0	OUT[21]
1	0	0	0	1	0	0	0	0	OUT[17]

virtex6 INT switchbox INT muxes QUAD_SE0[0]
Bits									Destination
MAIN[2][11]	MAIN[3][11]	MAIN[0][11]	MAIN[1][11]	MAIN[0][10]	MAIN[2][9]	MAIN[0][9]	MAIN[5][10]	MAIN[2][10]	QUAD_SE0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_EE2[0]
0	0	0	1	0	0	0	1	0	DBL_SS2[0]
0	0	0	1	0	0	1	0	0	DBL_NN2[0]
0	0	0	1	0	1	0	0	0	OUT[8]
0	0	0	1	1	0	0	0	0	OUT[12]
0	0	1	0	0	0	0	0	1	DBL_SE2[0]
0	0	1	0	0	0	0	1	0	DBL_SW2[0]
0	0	1	0	0	0	1	0	0	DBL_NE2[0]
0	0	1	0	0	1	0	0	0	OUT[4]
0	0	1	0	1	0	0	0	0	OUT[0]
0	1	0	0	0	0	0	0	1	QUAD_EE4[0]
0	1	0	0	0	0	0	1	0	QUAD_SW4[0]
0	1	0	0	0	0	1	0	0	QUAD_NE4[0]
0	1	0	0	0	1	0	0	0	LH[16]
0	1	0	0	1	0	0	0	0	LV[0]
1	0	0	0	0	0	0	0	1	QUAD_SE4[0]
1	0	0	0	0	0	0	1	0	QUAD_SS4[0]
1	0	0	0	0	0	1	0	0	QUAD_NN4[0]
1	0	0	0	0	1	0	0	0	OUT[18]
1	0	0	0	1	0	0	0	0	OUT[22]

virtex6 INT switchbox INT muxes QUAD_SE0[1]
Bits									Destination
MAIN[2][27]	MAIN[3][27]	MAIN[0][27]	MAIN[1][27]	MAIN[0][26]	MAIN[2][25]	MAIN[0][25]	MAIN[5][26]	MAIN[2][26]	QUAD_SE0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_EE2[1]
0	0	0	1	0	0	0	1	0	DBL_SS2[1]
0	0	0	1	0	0	1	0	0	DBL_NN2[1]
0	0	0	1	0	1	0	0	0	OUT[13]
0	0	0	1	1	0	0	0	0	OUT[9]
0	0	1	0	0	0	0	0	1	DBL_SE2[1]
0	0	1	0	0	0	0	1	0	DBL_SW2[1]
0	0	1	0	0	0	1	0	0	DBL_NE2[1]
0	0	1	0	0	1	0	0	0	OUT[1]
0	0	1	0	1	0	0	0	0	OUT[5]
0	1	0	0	0	0	0	0	1	QUAD_EE4[1]
0	1	0	0	0	0	0	1	0	QUAD_SW4[1]
0	1	0	0	0	0	1	0	0	QUAD_NE4[1]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_SE4[1]
1	0	0	0	0	0	0	1	0	QUAD_SS4[1]
1	0	0	0	0	0	1	0	0	QUAD_NN4[1]
1	0	0	0	0	1	0	0	0	OUT[23]
1	0	0	0	1	0	0	0	0	OUT[19]

virtex6 INT switchbox INT muxes QUAD_SE0[2]
Bits									Destination
MAIN[2][43]	MAIN[3][43]	MAIN[0][43]	MAIN[1][43]	MAIN[0][42]	MAIN[2][41]	MAIN[0][41]	MAIN[5][42]	MAIN[2][42]	QUAD_SE0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_EE2[2]
0	0	0	1	0	0	0	1	0	DBL_SS2[2]
0	0	0	1	0	0	1	0	0	DBL_NN2[2]
0	0	0	1	0	1	0	0	0	OUT[10]
0	0	0	1	1	0	0	0	0	OUT[14]
0	0	1	0	0	0	0	0	1	DBL_SE2[2]
0	0	1	0	0	0	0	1	0	DBL_SW2[2]
0	0	1	0	0	0	1	0	0	DBL_NE2[2]
0	0	1	0	0	1	0	0	0	OUT[6]
0	0	1	0	1	0	0	0	0	OUT[2]
0	1	0	0	0	0	0	0	1	QUAD_EE4[2]
0	1	0	0	0	0	0	1	0	QUAD_SW4[2]
0	1	0	0	0	0	1	0	0	QUAD_NE4[2]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_SE4[2]
1	0	0	0	0	0	0	1	0	QUAD_SS4[2]
1	0	0	0	0	0	1	0	0	QUAD_NN4[2]
1	0	0	0	0	1	0	0	0	OUT[16]
1	0	0	0	1	0	0	0	0	OUT[20]

virtex6 INT switchbox INT muxes QUAD_SE0[3]
Bits									Destination
MAIN[2][59]	MAIN[3][59]	MAIN[0][59]	MAIN[1][59]	MAIN[2][57]	MAIN[0][58]	MAIN[0][57]	MAIN[5][58]	MAIN[2][58]	QUAD_SE0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_EE2[3]
0	0	0	1	0	0	0	1	0	DBL_SS2[3]
0	0	0	1	0	0	1	0	0	DBL_NN2[3]
0	0	0	1	0	1	0	0	0	OUT[11]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	DBL_SE2[3]
0	0	1	0	0	0	0	1	0	DBL_SW2[3]
0	0	1	0	0	0	1	0	0	DBL_NE2[3]
0	0	1	0	0	1	0	0	0	OUT[7]
0	0	1	0	1	0	0	0	0	OUT[3]
0	1	0	0	0	0	0	0	1	QUAD_EE4[3]
0	1	0	0	0	0	0	1	0	QUAD_SW4[3]
0	1	0	0	0	0	1	0	0	QUAD_NE4[3]
0	1	0	0	0	1	0	0	0	LH[0]
0	1	0	0	1	0	0	0	0	LV[16]
1	0	0	0	0	0	0	0	1	QUAD_SE4[3]
1	0	0	0	0	0	0	1	0	QUAD_SS4[3]
1	0	0	0	0	0	1	0	0	QUAD_NN4[3]
1	0	0	0	0	1	0	0	0	OUT[17]
1	0	0	0	1	0	0	0	0	OUT[21]

virtex6 INT switchbox INT muxes QUAD_NN0[0]
Bits									Destination
MAIN[3][4]	MAIN[2][4]	MAIN[1][4]	MAIN[0][4]	MAIN[3][6]	MAIN[1][5]	MAIN[3][5]	MAIN[1][6]	MAIN[5][4]	QUAD_NN0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2_N3
0	0	0	1	0	0	0	1	0	DBL_EE2[0]
0	0	0	1	0	0	1	0	0	DBL_NN2[0]
0	0	0	1	0	1	0	0	0	OUT[12]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	DBL_NW2[0]
0	0	1	0	0	0	0	1	0	DBL_SE2[0]
0	0	1	0	0	0	1	0	0	DBL_NE2[0]
0	0	1	0	0	1	0	0	0	OUT[0]
0	0	1	0	1	0	0	0	0	OUT[4]
0	1	0	0	0	0	0	0	1	QUAD_WW4[0]
0	1	0	0	0	0	0	1	0	QUAD_EE4[0]
0	1	0	0	0	0	1	0	0	QUAD_NE4[0]
0	1	0	0	0	1	0	0	0	LH[16]
0	1	0	0	1	0	0	0	0	LV[0]
1	0	0	0	0	0	0	0	1	QUAD_NW4[0]
1	0	0	0	0	0	0	1	0	QUAD_SE4[0]
1	0	0	0	0	0	1	0	0	QUAD_NN4[0]
1	0	0	0	0	1	0	0	0	OUT[22]
1	0	0	0	1	0	0	0	0	OUT[18]

virtex6 INT switchbox INT muxes QUAD_NN0[1]
Bits									Destination
MAIN[3][20]	MAIN[2][20]	MAIN[1][20]	MAIN[0][20]	MAIN[3][22]	MAIN[1][21]	MAIN[3][21]	MAIN[1][22]	MAIN[5][20]	QUAD_NN0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[0]
0	0	0	1	0	0	0	1	0	DBL_EE2[1]
0	0	0	1	0	0	1	0	0	DBL_NN2[1]
0	0	0	1	0	1	0	0	0	OUT[9]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	DBL_NW2[1]
0	0	1	0	0	0	0	1	0	DBL_SE2[1]
0	0	1	0	0	0	1	0	0	DBL_NE2[1]
0	0	1	0	0	1	0	0	0	OUT[5]
0	0	1	0	1	0	0	0	0	OUT[1]
0	1	0	0	0	0	0	0	1	QUAD_WW4[1]
0	1	0	0	0	0	0	1	0	QUAD_EE4[1]
0	1	0	0	0	0	1	0	0	QUAD_NE4[1]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[1]
1	0	0	0	0	0	0	1	0	QUAD_SE4[1]
1	0	0	0	0	0	1	0	0	QUAD_NN4[1]
1	0	0	0	0	1	0	0	0	OUT[19]
1	0	0	0	1	0	0	0	0	OUT[23]

virtex6 INT switchbox INT muxes QUAD_NN0[2]
Bits									Destination
MAIN[3][36]	MAIN[2][36]	MAIN[1][36]	MAIN[0][36]	MAIN[3][38]	MAIN[1][37]	MAIN[3][37]	MAIN[1][38]	MAIN[5][36]	QUAD_NN0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[1]
0	0	0	1	0	0	0	1	0	DBL_EE2[2]
0	0	0	1	0	0	1	0	0	DBL_NN2[2]
0	0	0	1	0	1	0	0	0	OUT[14]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	DBL_NW2[2]
0	0	1	0	0	0	0	1	0	DBL_SE2[2]
0	0	1	0	0	0	1	0	0	DBL_NE2[2]
0	0	1	0	0	1	0	0	0	OUT[2]
0	0	1	0	1	0	0	0	0	OUT[6]
0	1	0	0	0	0	0	0	1	QUAD_WW4[2]
0	1	0	0	0	0	0	1	0	QUAD_EE4[2]
0	1	0	0	0	0	1	0	0	QUAD_NE4[2]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[2]
1	0	0	0	0	0	0	1	0	QUAD_SE4[2]
1	0	0	0	0	0	1	0	0	QUAD_NN4[2]
1	0	0	0	0	1	0	0	0	OUT[20]
1	0	0	0	1	0	0	0	0	OUT[16]

virtex6 INT switchbox INT muxes QUAD_NN0[3]
Bits									Destination
MAIN[3][52]	MAIN[2][52]	MAIN[1][52]	MAIN[0][52]	MAIN[1][53]	MAIN[3][54]	MAIN[3][53]	MAIN[1][54]	MAIN[5][52]	QUAD_NN0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[2]
0	0	0	1	0	0	0	1	0	DBL_EE2[3]
0	0	0	1	0	0	1	0	0	DBL_NN2[3]
0	0	0	1	0	1	0	0	0	OUT[15]
0	0	0	1	1	0	0	0	0	OUT[11]
0	0	1	0	0	0	0	0	1	DBL_NW2[3]
0	0	1	0	0	0	0	1	0	DBL_SE2[3]
0	0	1	0	0	0	1	0	0	DBL_NE2[3]
0	0	1	0	0	1	0	0	0	OUT[3]
0	0	1	0	1	0	0	0	0	OUT[7]
0	1	0	0	0	0	0	0	1	QUAD_WW4[3]
0	1	0	0	0	0	0	1	0	QUAD_EE4[3]
0	1	0	0	0	0	1	0	0	QUAD_NE4[3]
0	1	0	0	0	1	0	0	0	LH[0]
0	1	0	0	1	0	0	0	0	LV[16]
1	0	0	0	0	0	0	0	1	QUAD_NW4[3]
1	0	0	0	0	0	0	1	0	QUAD_SE4[3]
1	0	0	0	0	0	1	0	0	QUAD_NN4[3]
1	0	0	0	0	1	0	0	0	OUT[21]
1	0	0	0	1	0	0	0	0	OUT[17]

virtex6 INT switchbox INT muxes QUAD_NW0[0]
Bits									Destination
MAIN[2][3]	MAIN[3][3]	MAIN[0][3]	MAIN[1][3]	MAIN[0][2]	MAIN[2][1]	MAIN[5][2]	MAIN[0][1]	MAIN[2][2]	QUAD_NW0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2_N3
0	0	0	1	0	0	0	1	0	DBL_SS2_N3
0	0	0	1	0	0	1	0	0	DBL_NN2[0]
0	0	0	1	0	1	0	0	0	OUT[8]
0	0	0	1	1	0	0	0	0	OUT[12]
0	0	1	0	0	0	0	0	1	DBL_NW2[0]
0	0	1	0	0	0	0	1	0	DBL_SW2_N3
0	0	1	0	0	0	1	0	0	DBL_NE2[0]
0	0	1	0	0	1	0	0	0	OUT[4]
0	0	1	0	1	0	0	0	0	OUT[0]
0	1	0	0	0	0	0	0	1	QUAD_WW4[0]
0	1	0	0	0	0	0	1	0	QUAD_SW4_N3
0	1	0	0	0	0	1	0	0	QUAD_NE4[0]
0	1	0	0	0	1	0	0	0	LH[16]
0	1	0	0	1	0	0	0	0	LV[0]
1	0	0	0	0	0	0	0	1	QUAD_NW4[0]
1	0	0	0	0	0	0	1	0	QUAD_SS4_N3
1	0	0	0	0	0	1	0	0	QUAD_NN4[0]
1	0	0	0	0	1	0	0	0	OUT[18]
1	0	0	0	1	0	0	0	0	OUT[22]

virtex6 INT switchbox INT muxes QUAD_NW0[1]
Bits									Destination
MAIN[2][19]	MAIN[3][19]	MAIN[0][19]	MAIN[1][19]	MAIN[0][18]	MAIN[2][17]	MAIN[5][18]	MAIN[0][17]	MAIN[2][18]	QUAD_NW0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[0]
0	0	0	1	0	0	0	1	0	DBL_SS2[0]
0	0	0	1	0	0	1	0	0	DBL_NN2[1]
0	0	0	1	0	1	0	0	0	OUT[13]
0	0	0	1	1	0	0	0	0	OUT[9]
0	0	1	0	0	0	0	0	1	DBL_NW2[1]
0	0	1	0	0	0	0	1	0	DBL_SW2[0]
0	0	1	0	0	0	1	0	0	DBL_NE2[1]
0	0	1	0	0	1	0	0	0	OUT[1]
0	0	1	0	1	0	0	0	0	OUT[5]
0	1	0	0	0	0	0	0	1	QUAD_WW4[1]
0	1	0	0	0	0	0	1	0	QUAD_SW4[0]
0	1	0	0	0	0	1	0	0	QUAD_NE4[1]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[1]
1	0	0	0	0	0	0	1	0	QUAD_SS4[0]
1	0	0	0	0	0	1	0	0	QUAD_NN4[1]
1	0	0	0	0	1	0	0	0	OUT[23]
1	0	0	0	1	0	0	0	0	OUT[19]

virtex6 INT switchbox INT muxes QUAD_NW0[2]
Bits									Destination
MAIN[2][35]	MAIN[3][35]	MAIN[0][35]	MAIN[1][35]	MAIN[0][34]	MAIN[2][33]	MAIN[5][34]	MAIN[0][33]	MAIN[2][34]	QUAD_NW0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[1]
0	0	0	1	0	0	0	1	0	DBL_SS2[1]
0	0	0	1	0	0	1	0	0	DBL_NN2[2]
0	0	0	1	0	1	0	0	0	OUT[10]
0	0	0	1	1	0	0	0	0	OUT[14]
0	0	1	0	0	0	0	0	1	DBL_NW2[2]
0	0	1	0	0	0	0	1	0	DBL_SW2[1]
0	0	1	0	0	0	1	0	0	DBL_NE2[2]
0	0	1	0	0	1	0	0	0	OUT[6]
0	0	1	0	1	0	0	0	0	OUT[2]
0	1	0	0	0	0	0	0	1	QUAD_WW4[2]
0	1	0	0	0	0	0	1	0	QUAD_SW4[1]
0	1	0	0	0	0	1	0	0	QUAD_NE4[2]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[2]
1	0	0	0	0	0	0	1	0	QUAD_SS4[1]
1	0	0	0	0	0	1	0	0	QUAD_NN4[2]
1	0	0	0	0	1	0	0	0	OUT[16]
1	0	0	0	1	0	0	0	0	OUT[20]

virtex6 INT switchbox INT muxes QUAD_NW0[3]
Bits									Destination
MAIN[2][51]	MAIN[3][51]	MAIN[0][51]	MAIN[1][51]	MAIN[2][49]	MAIN[0][50]	MAIN[5][50]	MAIN[0][49]	MAIN[2][50]	QUAD_NW0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[2]
0	0	0	1	0	0	0	1	0	DBL_SS2[2]
0	0	0	1	0	0	1	0	0	DBL_NN2[3]
0	0	0	1	0	1	0	0	0	OUT[11]
0	0	0	1	1	0	0	0	0	OUT[15]
0	0	1	0	0	0	0	0	1	DBL_NW2[3]
0	0	1	0	0	0	0	1	0	DBL_SW2[2]
0	0	1	0	0	0	1	0	0	DBL_NE2[3]
0	0	1	0	0	1	0	0	0	OUT[7]
0	0	1	0	1	0	0	0	0	OUT[3]
0	1	0	0	0	0	0	0	1	QUAD_WW4[3]
0	1	0	0	0	0	0	1	0	QUAD_SW4[2]
0	1	0	0	0	0	1	0	0	QUAD_NE4[3]
0	1	0	0	0	1	0	0	0	LH[0]
0	1	0	0	1	0	0	0	0	LV[16]
1	0	0	0	0	0	0	0	1	QUAD_NW4[3]
1	0	0	0	0	0	0	1	0	QUAD_SS4[2]
1	0	0	0	0	0	1	0	0	QUAD_NN4[3]
1	0	0	0	0	1	0	0	0	OUT[17]
1	0	0	0	1	0	0	0	0	OUT[21]

virtex6 INT switchbox INT muxes QUAD_NE0[0]
Bits									Destination
MAIN[2][7]	MAIN[3][7]	MAIN[0][7]	MAIN[1][7]	MAIN[0][6]	MAIN[2][5]	MAIN[2][6]	MAIN[5][6]	MAIN[0][5]	QUAD_NE0[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2_N3
0	0	0	1	0	0	0	1	0	DBL_EE2[0]
0	0	0	1	0	0	1	0	0	DBL_NN2[0]
0	0	0	1	0	1	0	0	0	OUT[12]
0	0	0	1	1	0	0	0	0	OUT[8]
0	0	1	0	0	0	0	0	1	DBL_NW2[0]
0	0	1	0	0	0	0	1	0	DBL_SE2[0]
0	0	1	0	0	0	1	0	0	DBL_NE2[0]
0	0	1	0	0	1	0	0	0	OUT[0]
0	0	1	0	1	0	0	0	0	OUT[4]
0	1	0	0	0	0	0	0	1	QUAD_WW4[0]
0	1	0	0	0	0	0	1	0	QUAD_EE4[0]
0	1	0	0	0	0	1	0	0	QUAD_NE4[0]
0	1	0	0	0	1	0	0	0	LH[16]
0	1	0	0	1	0	0	0	0	LV[0]
1	0	0	0	0	0	0	0	1	QUAD_NW4[0]
1	0	0	0	0	0	0	1	0	QUAD_SE4[0]
1	0	0	0	0	0	1	0	0	QUAD_NN4[0]
1	0	0	0	0	1	0	0	0	OUT[22]
1	0	0	0	1	0	0	0	0	OUT[18]

virtex6 INT switchbox INT muxes QUAD_NE0[1]
Bits									Destination
MAIN[2][23]	MAIN[3][23]	MAIN[0][23]	MAIN[1][23]	MAIN[0][22]	MAIN[2][21]	MAIN[2][22]	MAIN[5][22]	MAIN[0][21]	QUAD_NE0[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[0]
0	0	0	1	0	0	0	1	0	DBL_EE2[1]
0	0	0	1	0	0	1	0	0	DBL_NN2[1]
0	0	0	1	0	1	0	0	0	OUT[9]
0	0	0	1	1	0	0	0	0	OUT[13]
0	0	1	0	0	0	0	0	1	DBL_NW2[1]
0	0	1	0	0	0	0	1	0	DBL_SE2[1]
0	0	1	0	0	0	1	0	0	DBL_NE2[1]
0	0	1	0	0	1	0	0	0	OUT[5]
0	0	1	0	1	0	0	0	0	OUT[1]
0	1	0	0	0	0	0	0	1	QUAD_WW4[1]
0	1	0	0	0	0	0	1	0	QUAD_EE4[1]
0	1	0	0	0	0	1	0	0	QUAD_NE4[1]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[1]
1	0	0	0	0	0	0	1	0	QUAD_SE4[1]
1	0	0	0	0	0	1	0	0	QUAD_NN4[1]
1	0	0	0	0	1	0	0	0	OUT[19]
1	0	0	0	1	0	0	0	0	OUT[23]

virtex6 INT switchbox INT muxes QUAD_NE0[2]
Bits									Destination
MAIN[2][39]	MAIN[3][39]	MAIN[0][39]	MAIN[1][39]	MAIN[0][38]	MAIN[2][37]	MAIN[2][38]	MAIN[5][38]	MAIN[0][37]	QUAD_NE0[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[1]
0	0	0	1	0	0	0	1	0	DBL_EE2[2]
0	0	0	1	0	0	1	0	0	DBL_NN2[2]
0	0	0	1	0	1	0	0	0	OUT[14]
0	0	0	1	1	0	0	0	0	OUT[10]
0	0	1	0	0	0	0	0	1	DBL_NW2[2]
0	0	1	0	0	0	0	1	0	DBL_SE2[2]
0	0	1	0	0	0	1	0	0	DBL_NE2[2]
0	0	1	0	0	1	0	0	0	OUT[2]
0	0	1	0	1	0	0	0	0	OUT[6]
0	1	0	0	0	0	0	0	1	QUAD_WW4[2]
0	1	0	0	0	0	0	1	0	QUAD_EE4[2]
0	1	0	0	0	0	1	0	0	QUAD_NE4[2]
0	1	0	0	0	1	0	0	0	LH[8]
0	1	0	0	1	0	0	0	0	LV[8]
1	0	0	0	0	0	0	0	1	QUAD_NW4[2]
1	0	0	0	0	0	0	1	0	QUAD_SE4[2]
1	0	0	0	0	0	1	0	0	QUAD_NN4[2]
1	0	0	0	0	1	0	0	0	OUT[20]
1	0	0	0	1	0	0	0	0	OUT[16]

virtex6 INT switchbox INT muxes QUAD_NE0[3]
Bits									Destination
MAIN[2][55]	MAIN[3][55]	MAIN[0][55]	MAIN[1][55]	MAIN[2][53]	MAIN[0][54]	MAIN[2][54]	MAIN[5][54]	MAIN[0][53]	QUAD_NE0[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	1	DBL_WW2[2]
0	0	0	1	0	0	0	1	0	DBL_EE2[3]
0	0	0	1	0	0	1	0	0	DBL_NN2[3]
0	0	0	1	0	1	0	0	0	OUT[15]
0	0	0	1	1	0	0	0	0	OUT[11]
0	0	1	0	0	0	0	0	1	DBL_NW2[3]
0	0	1	0	0	0	0	1	0	DBL_SE2[3]
0	0	1	0	0	0	1	0	0	DBL_NE2[3]
0	0	1	0	0	1	0	0	0	OUT[3]
0	0	1	0	1	0	0	0	0	OUT[7]
0	1	0	0	0	0	0	0	1	QUAD_WW4[3]
0	1	0	0	0	0	0	1	0	QUAD_EE4[3]
0	1	0	0	0	0	1	0	0	QUAD_NE4[3]
0	1	0	0	0	1	0	0	0	LH[0]
0	1	0	0	1	0	0	0	0	LV[16]
1	0	0	0	0	0	0	0	1	QUAD_NW4[3]
1	0	0	0	0	0	0	1	0	QUAD_SE4[3]
1	0	0	0	0	0	1	0	0	QUAD_NN4[3]
1	0	0	0	0	1	0	0	0	OUT[21]
1	0	0	0	1	0	0	0	0	OUT[17]

virtex6 INT switchbox INT muxes LH[0]
Bits								Destination
MAIN[25][52]	MAIN[24][53]	MAIN[23][54]	MAIN[23][50]	MAIN[23][56]	MAIN[23][58]	MAIN[23][48]	MAIN[23][52]	LH[0]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	1	1	QUAD_SE4[3]
0	0	0	0	0	1	0	1	LV[16]
0	0	0	0	1	0	0	1	LV[8]
0	0	0	1	0	0	0	1	QUAD_SW4[3]
0	0	1	0	0	0	0	1	LV[0]
0	1	0	0	0	0	0	1	LH[16]
1	0	0	0	0	0	1	1	SNG_W1[7]
1	0	0	0	0	1	0	1	SNG_E1[7]
1	0	0	0	1	0	0	1	SNG_S1[7]
1	0	0	1	0	0	0	1	SNG_N1[7]
1	0	1	0	0	0	0	1	QUAD_NW4[3]
1	1	0	0	0	0	0	1	QUAD_NE4[3]

virtex6 INT switchbox INT muxes LH[16]
Bits								Destination
MAIN[25][49]	MAIN[23][46]	MAIN[24][52]	MAIN[25][50]	MAIN[25][51]	MAIN[24][51]	MAIN[24][50]	MAIN[23][44]	LH[16]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	1	1	QUAD_SE4[3]
0	0	0	0	0	1	0	1	LV[16]
0	0	0	0	1	0	0	1	LV[8]
0	0	0	1	0	0	0	1	QUAD_SW4[3]
0	0	1	0	0	0	0	1	LV[0]
0	1	0	0	0	0	0	1	QUAD_NE4[3]
1	0	0	0	0	0	1	1	SNG_W1[7]
1	0	0	0	0	1	0	1	SNG_E1[7]
1	0	0	0	1	0	0	1	SNG_S1[7]
1	0	0	1	0	0	0	1	SNG_N1[7]
1	0	1	0	0	0	0	1	QUAD_NW4[3]
1	1	0	0	0	0	0	1	LH[0]

virtex6 INT switchbox INT muxes LV[0]
Bits								Destination
MAIN[24][14]	MAIN[25][12]	MAIN[24][13]	MAIN[25][11]	MAIN[25][13]	MAIN[23][14]	MAIN[24][12]	MAIN[23][16]	LV[0]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	1	1	QUAD_SE4[0]
0	0	0	0	0	1	0	1	SNG_E1[4]
0	0	0	0	1	0	0	1	SNG_S0_S4
0	0	0	1	0	0	0	1	QUAD_SW4[0]
0	0	1	0	0	0	0	1	QUAD_NW4[0]
0	1	0	0	0	0	0	1	QUAD_NE4[0]
1	0	0	0	0	0	1	1	SNG_W1[4]
1	0	0	0	0	1	0	1	LV[16]
1	0	0	0	1	0	0	1	LH[16]
1	0	0	1	0	0	0	1	SNG_N1[4]
1	0	1	0	0	0	0	1	LH[8]
1	1	0	0	0	0	0	1	LH[0]

virtex6 INT switchbox INT muxes LV[16]
Bits								Destination
MAIN[24][11]	MAIN[23][12]	MAIN[23][20]	MAIN[23][6]	MAIN[23][18]	MAIN[25][10]	MAIN[23][4]	MAIN[23][8]	LV[16]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	1	1	QUAD_SE4[0]
0	0	0	0	0	1	0	1	LV[0]
0	0	0	0	1	0	0	1	SNG_S0_S4
0	0	0	1	0	0	0	1	QUAD_SW4[0]
0	0	1	0	0	0	0	1	QUAD_NW4[0]
0	1	0	0	0	0	0	1	QUAD_NE4[0]
1	0	0	0	0	0	1	1	SNG_W1[4]
1	0	0	0	0	1	0	1	SNG_E1[4]
1	0	0	0	1	0	0	1	LH[16]
1	0	0	1	0	0	0	1	SNG_N1[4]
1	0	1	0	0	0	0	1	LH[8]
1	1	0	0	0	0	0	1	LH[0]

virtex6 INT switchbox INT muxes IMUX_GFAN[0]
Bits									Destination
MAIN[24][25]	MAIN[24][24]	MAIN[23][26]	MAIN[25][28]	MAIN[25][15]	MAIN[23][28]	MAIN[25][27]	MAIN[25][26]	MAIN[25][25]	IMUX_GFAN[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	1	0	0	0	0	0	0	1	TIE_0
0	1	0	0	0	0	0	1	0	LCLK[0]
0	1	0	0	0	0	1	0	0	LCLK[1]
0	1	0	0	0	1	0	0	0	LCLK[5]
0	1	0	0	1	0	0	0	0	LCLK[4]
0	1	0	1	0	0	0	0	0	SNG_S1[5]
0	1	1	0	0	0	0	0	0	IMUX_FAN_BOUNCE[7]
1	0	0	0	0	0	0	0	1	IMUX_BYP_BOUNCE[1]
1	0	0	0	0	0	0	1	0	LCLK[7]
1	0	0	0	0	0	1	0	0	LCLK[6]
1	0	0	0	0	1	0	0	0	LCLK[2]
1	0	0	0	1	0	0	0	0	LCLK[3]
1	0	0	1	0	0	0	0	0	SNG_E1[5]
1	0	1	0	0	0	0	0	0	SNG_N1[5]

virtex6 INT switchbox INT muxes IMUX_GFAN[1]
Bits									Destination
MAIN[25][21]	MAIN[24][22]	MAIN[24][20]	MAIN[24][29]	MAIN[24][17]	MAIN[24][15]	MAIN[24][28]	MAIN[24][27]	MAIN[24][26]	IMUX_GFAN[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	1	0	0	0	0	0	0	1	TIE_0
0	1	0	0	0	0	0	1	0	LCLK[0]
0	1	0	0	0	0	1	0	0	LCLK[1]
0	1	0	0	0	1	0	0	0	LCLK[5]
0	1	0	0	1	0	0	0	0	LCLK[4]
0	1	0	1	0	0	0	0	0	SNG_S1[5]
0	1	1	0	0	0	0	0	0	IMUX_FAN_BOUNCE[7]
1	0	0	0	0	0	0	0	1	IMUX_BYP_BOUNCE[1]
1	0	0	0	0	0	0	1	0	LCLK[7]
1	0	0	0	0	0	1	0	0	LCLK[6]
1	0	0	0	0	1	0	0	0	LCLK[2]
1	0	0	0	1	0	0	0	0	LCLK[3]
1	0	0	1	0	0	0	0	0	SNG_E1[5]
1	0	1	0	0	0	0	0	0	SNG_N1[5]

virtex6 INT switchbox INT muxes IMUX_CLK[0]
Bits									Destination
MAIN[24][30]	MAIN[25][29]	MAIN[24][33]	MAIN[23][30]	MAIN[23][40]	MAIN[24][43]	MAIN[24][32]	MAIN[24][31]	MAIN[23][22]	IMUX_CLK[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	1	0	0	0	0	0	0	1	LCLK[0]
0	1	0	0	0	0	0	1	0	LCLK[1]
0	1	0	0	0	0	1	0	0	LCLK[6]
0	1	0	0	0	1	0	0	0	LCLK[7]
0	1	0	0	1	0	0	0	0	SNG_W1[6]
0	1	0	1	0	0	0	0	0	SNG_S1[5]
0	1	1	0	0	0	0	0	0	IMUX_FAN_BOUNCE[5]
1	0	0	0	0	0	0	0	1	LCLK[4]
1	0	0	0	0	0	0	1	0	LCLK[5]
1	0	0	0	0	0	1	0	0	LCLK[2]
1	0	0	0	0	1	0	0	0	LCLK[3]
1	0	0	0	1	0	0	0	0	SNG_N1[6]
1	0	0	1	0	0	0	0	0	SNG_E1[5]
1	0	1	0	0	0	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_CLK[1]
Bits									Destination
MAIN[25][33]	MAIN[24][34]	MAIN[25][32]	MAIN[23][24]	MAIN[23][38]	MAIN[23][32]	MAIN[25][31]	MAIN[25][30]	MAIN[25][20]	IMUX_CLK[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	1	0	0	0	0	0	0	1	LCLK[0]
0	1	0	0	0	0	0	1	0	LCLK[1]
0	1	0	0	0	0	1	0	0	LCLK[6]
0	1	0	0	0	1	0	0	0	LCLK[7]
0	1	0	0	1	0	0	0	0	SNG_W1[6]
0	1	0	1	0	0	0	0	0	SNG_S1[5]
0	1	1	0	0	0	0	0	0	IMUX_FAN_BOUNCE[5]
1	0	0	0	0	0	0	0	1	LCLK[4]
1	0	0	0	0	0	0	1	0	LCLK[5]
1	0	0	0	0	0	1	0	0	LCLK[2]
1	0	0	0	0	1	0	0	0	LCLK[3]
1	0	0	0	1	0	0	0	0	SNG_N1[6]
1	0	0	1	0	0	0	0	0	SNG_E1[5]
1	0	1	0	0	0	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_CTRL[0]
Bits									Destination
MAIN[24][42]	MAIN[25][41]	MAIN[25][36]	MAIN[25][43]	MAIN[25][37]	MAIN[25][35]	MAIN[25][46]	MAIN[25][48]	MAIN[25][34]	IMUX_CTRL[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	1	0	0	0	0	0	0	1	SNG_W1[6]
0	1	0	0	0	0	0	1	0	SNG_E1[6]
0	1	0	0	0	0	1	0	0	DBL_SE2[2]
0	1	0	0	0	1	0	0	0	DBL_NW2[2]
0	1	0	0	1	0	0	0	0	IMUX_GFAN[0]
0	1	0	1	0	0	0	0	0	IMUX_BYP_BOUNCE[5]
0	1	1	0	0	0	0	0	0	IMUX_FAN_BOUNCE[3]
1	0	0	0	0	0	0	0	1	SNG_N1[6]
1	0	0	0	0	0	0	1	0	SNG_S1[6]
1	0	0	0	0	0	1	0	0	DBL_SW2[2]
1	0	0	0	0	1	0	0	0	DBL_NE2[2]
1	0	0	0	1	0	0	0	0	IMUX_GFAN[1]
1	0	0	1	0	0	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	1	0	0	0	0	0	0	IMUX_FAN_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_CTRL[1]
Bits									Destination
MAIN[25][38]	MAIN[25][39]	MAIN[24][37]	MAIN[23][42]	MAIN[24][38]	MAIN[24][36]	MAIN[24][48]	MAIN[23][34]	MAIN[24][35]	IMUX_CTRL[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	1	0	0	0	0	0	0	1	SNG_W1[6]
0	1	0	0	0	0	0	1	0	SNG_E1[6]
0	1	0	0	0	0	1	0	0	DBL_SE2[2]
0	1	0	0	0	1	0	0	0	DBL_NW2[2]
0	1	0	0	1	0	0	0	0	IMUX_GFAN[0]
0	1	0	1	0	0	0	0	0	IMUX_BYP_BOUNCE[5]
0	1	1	0	0	0	0	0	0	IMUX_FAN_BOUNCE[3]
1	0	0	0	0	0	0	0	1	SNG_N1[6]
1	0	0	0	0	0	0	1	0	SNG_S1[6]
1	0	0	0	0	0	1	0	0	DBL_SW2[2]
1	0	0	0	0	1	0	0	0	DBL_NE2[2]
1	0	0	0	1	0	0	0	0	IMUX_GFAN[1]
1	0	0	1	0	0	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	1	0	0	0	0	0	0	IMUX_FAN_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_BYP[0]
Bits										Destination
MAIN[15][7]	MAIN[14][7]	MAIN[20][7]	MAIN[13][6]	MAIN[23][7]	MAIN[21][7]	MAIN[17][6]	MAIN[19][7]	MAIN[19][6]	MAIN[17][7]	IMUX_BYP[0]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[0]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[2]
0	0	0	0	0	1	1	0	0	0	DBL_EE2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[0]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	1	0	1	0	0	0	DBL_SE2[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[0]
0	0	0	1	1	1	0	1	0	0	SNG_N1[0]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[4]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	OUT[0]
0	1	0	0	1	1	0	0	1	0	DBL_WW2_N3
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[3]
0	1	0	0	1	1	1	0	0	0	IMUX_GFAN[0]
1	0	0	0	1	1	0	0	0	1	OUT[12]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[0]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[7]
1	0	0	0	1	1	1	0	0	0	OUT[22]

virtex6 INT switchbox INT muxes IMUX_BYP[1]
Bits										Destination
MAIN[15][15]	MAIN[14][15]	MAIN[20][15]	MAIN[13][14]	MAIN[23][15]	MAIN[21][15]	MAIN[17][14]	MAIN[19][15]	MAIN[17][15]	MAIN[19][14]	IMUX_BYP[1]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	0	1	1	0	0	0	DBL_WW2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	1	0	0	0	DBL_NW2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[0]
0	1	0	0	1	1	0	0	1	0	OUT[4]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE[0]
0	1	0	0	1	1	1	0	0	0	IMUX_GFAN[0]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[0]
1	0	0	0	1	1	0	0	1	0	OUT[8]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	1	0	0	0	OUT[18]

virtex6 INT switchbox INT muxes IMUX_BYP[2]
Bits										Destination
MAIN[15][39]	MAIN[14][39]	MAIN[20][39]	MAIN[13][38]	MAIN[23][39]	MAIN[21][39]	MAIN[19][39]	MAIN[17][38]	MAIN[19][38]	MAIN[17][39]	IMUX_BYP[2]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	OUT[2]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[1]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	OUT[14]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[2]
1	0	0	0	1	1	0	1	0	0	OUT[20]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_BYP[3]
Bits										Destination
MAIN[15][47]	MAIN[14][47]	MAIN[20][47]	MAIN[13][46]	MAIN[23][47]	MAIN[21][47]	MAIN[19][47]	MAIN[17][46]	MAIN[17][47]	MAIN[19][46]	IMUX_BYP[3]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[2]
0	1	0	0	1	1	0	0	1	0	OUT[6]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[2]
1	0	0	0	1	1	0	0	1	0	OUT[10]
1	0	0	0	1	1	0	1	0	0	OUT[16]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_BYP[4]
Bits										Destination
MAIN[15][23]	MAIN[14][23]	MAIN[20][23]	MAIN[13][22]	MAIN[23][23]	MAIN[21][23]	MAIN[19][23]	MAIN[17][22]	MAIN[19][22]	MAIN[17][23]	IMUX_BYP[4]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[1]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	OUT[5]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[0]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]
1	0	0	0	1	1	0	0	0	1	OUT[9]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[1]
1	0	0	0	1	1	0	1	0	0	OUT[19]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[7]

virtex6 INT switchbox INT muxes IMUX_BYP[5]
Bits										Destination
MAIN[15][31]	MAIN[14][31]	MAIN[20][31]	MAIN[13][30]	MAIN[23][31]	MAIN[21][31]	MAIN[19][31]	MAIN[17][30]	MAIN[17][31]	MAIN[19][30]	IMUX_BYP[5]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[1]
0	1	0	0	1	1	0	0	1	0	OUT[1]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[0]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[1]
1	0	0	0	1	1	0	0	1	0	OUT[13]
1	0	0	0	1	1	0	1	0	0	OUT[23]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_BYP[6]
Bits										Destination
MAIN[15][55]	MAIN[14][55]	MAIN[20][55]	MAIN[13][54]	MAIN[23][55]	MAIN[21][55]	MAIN[19][55]	MAIN[17][54]	MAIN[19][54]	MAIN[17][55]	IMUX_BYP[6]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	OUT[7]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[2]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	OUT[11]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[3]
1	0	0	0	1	1	0	1	0	0	OUT[17]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[3]

virtex6 INT switchbox INT muxes IMUX_BYP[7]
Bits										Destination
MAIN[15][63]	MAIN[14][63]	MAIN[20][63]	MAIN[13][62]	MAIN[23][63]	MAIN[21][63]	MAIN[19][63]	MAIN[17][62]	MAIN[17][63]	MAIN[19][62]	IMUX_BYP[7]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2_S0
0	0	0	0	0	1	0	1	0	0	DBL_WW2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[6]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2_S0
0	0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1_S0
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N1_S0
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1_S4
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[3]
0	1	0	0	1	1	0	0	1	0	OUT[3]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[6]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[3]
1	0	0	0	1	1	0	0	1	0	OUT[15]
1	0	0	0	1	1	0	1	0	0	OUT[21]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_FAN[0]
Bits										Destination
MAIN[14][0]	MAIN[15][0]	MAIN[20][1]	MAIN[13][0]	MAIN[20][0]	MAIN[22][0]	MAIN[18][0]	MAIN[16][1]	MAIN[16][0]	MAIN[18][1]	IMUX_FAN[0]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_NN2[0]
0	0	0	0	0	1	0	0	1	0	DBL_SS2_N3
0	0	0	0	0	1	0	1	0	0	DBL_EE2[0]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	1	0	0	0	0	1	DBL_NE2[0]
0	0	0	0	1	0	0	0	1	0	DBL_SW2_N3
0	0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[4]
0	0	0	1	1	1	0	0	0	1	SNG_W1[4]
0	0	0	1	1	1	0	0	1	0	SNG_E1_N7
0	0	0	1	1	1	0	1	0	0	SNG_N1[4]
0	0	0	1	1	1	1	0	0	0	SNG_S1_N7
0	0	1	0	1	1	0	0	0	1	SNG_E1[0]
0	0	1	0	1	1	0	0	1	0	SNG_W1_N3
0	0	1	0	1	1	0	1	0	0	SNG_S1[0]
0	0	1	0	1	1	1	0	0	0	SNG_N1[0]
0	1	0	0	1	1	0	0	0	1	DBL_WW2_N3
0	1	0	0	1	1	0	0	1	0	OUT[0]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	0	0	0	1	DBL_NW2[0]
1	0	0	0	1	1	0	0	1	0	OUT[12]
1	0	0	0	1	1	0	1	0	0	OUT[22]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[2]

virtex6 INT switchbox INT muxes IMUX_FAN[1]
Bits										Destination
MAIN[14][48]	MAIN[15][48]	MAIN[13][48]	MAIN[20][49]	MAIN[20][48]	MAIN[22][48]	MAIN[18][48]	MAIN[16][49]	MAIN[18][49]	MAIN[16][48]	IMUX_FAN[1]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	OUT[7]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[2]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	0	0	1	1	0	0	0	1	OUT[11]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[3]
1	0	0	0	1	1	0	1	0	0	OUT[17]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_FAN[2]
Bits										Destination
MAIN[14][16]	MAIN[15][16]	MAIN[13][16]	MAIN[20][17]	MAIN[20][16]	MAIN[22][16]	MAIN[16][17]	MAIN[18][16]	MAIN[18][17]	MAIN[16][16]	IMUX_FAN[2]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	0	1	1	0	0	0	DBL_EE2[1]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	1	0	0	0	DBL_SE2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[5]
0	1	0	0	1	1	0	0	0	1	OUT[5]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE[0]
0	1	0	0	1	1	1	0	0	0	IMUX_GFAN[0]
1	0	0	0	1	1	0	0	0	1	OUT[9]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[1]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	1	0	0	0	OUT[19]

virtex6 INT switchbox INT muxes IMUX_FAN[3]
Bits										Destination
MAIN[14][56]	MAIN[15][56]	MAIN[13][56]	MAIN[20][57]	MAIN[20][56]	MAIN[22][56]	MAIN[18][56]	MAIN[16][57]	MAIN[16][56]	MAIN[18][57]	IMUX_FAN[3]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[3]
0	1	0	0	1	1	0	0	1	0	OUT[3]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[3]
1	0	0	0	1	1	0	0	1	0	OUT[15]
1	0	0	0	1	1	0	1	0	0	OUT[21]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[3]

virtex6 INT switchbox INT muxes IMUX_FAN[4]
Bits										Destination
MAIN[14][8]	MAIN[15][8]	MAIN[13][8]	MAIN[20][9]	MAIN[20][8]	MAIN[22][8]	MAIN[16][9]	MAIN[18][8]	MAIN[16][8]	MAIN[18][9]	IMUX_FAN[4]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[0]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[2]
0	0	0	0	0	1	1	0	0	0	DBL_WW2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[0]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	1	0	1	0	0	0	DBL_NW2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[0]
0	0	0	1	1	1	0	1	0	0	SNG_N1[0]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[4]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[0]
0	1	0	0	1	1	0	0	1	0	OUT[4]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[3]
0	1	0	0	1	1	1	0	0	0	IMUX_GFAN[0]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[0]
1	0	0	0	1	1	0	0	1	0	OUT[8]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[7]
1	0	0	0	1	1	1	0	0	0	OUT[18]

virtex6 INT switchbox INT muxes IMUX_FAN[5]
Bits										Destination
MAIN[14][40]	MAIN[15][40]	MAIN[13][40]	MAIN[20][41]	MAIN[20][40]	MAIN[22][40]	MAIN[18][40]	MAIN[16][41]	MAIN[16][40]	MAIN[18][41]	IMUX_FAN[5]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[2]
0	1	0	0	1	1	0	0	1	0	OUT[6]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[2]
1	0	0	0	1	1	0	0	1	0	OUT[10]
1	0	0	0	1	1	0	1	0	0	OUT[16]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_FAN[6]
Bits										Destination
MAIN[14][24]	MAIN[15][24]	MAIN[13][24]	MAIN[20][25]	MAIN[20][24]	MAIN[22][24]	MAIN[18][24]	MAIN[16][25]	MAIN[16][24]	MAIN[18][25]	IMUX_FAN[6]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[1]
0	1	0	0	1	1	0	0	1	0	OUT[1]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[1]
1	0	0	0	1	1	0	0	1	0	OUT[13]
1	0	0	0	1	1	0	1	0	0	OUT[23]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[7]

virtex6 INT switchbox INT muxes IMUX_FAN[7]
Bits										Destination
MAIN[14][32]	MAIN[15][32]	MAIN[13][32]	MAIN[20][33]	MAIN[20][32]	MAIN[22][32]	MAIN[18][32]	MAIN[16][33]	MAIN[18][33]	MAIN[16][32]	IMUX_FAN[7]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	OUT[2]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[1]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[0]
1	0	0	0	1	1	0	0	0	1	OUT[14]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[2]
1	0	0	0	1	1	0	1	0	0	OUT[20]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_IMUX[0]
Bits										Destination
MAIN[15][1]	MAIN[14][1]	MAIN[22][1]	MAIN[21][0]	MAIN[21][1]	MAIN[23][1]	MAIN[19][1]	MAIN[17][1]	MAIN[17][0]	MAIN[19][0]	IMUX_IMUX[0]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_NN2[0]
0	0	0	0	0	1	0	0	1	0	DBL_SS2_N3
0	0	0	0	0	1	0	1	0	0	DBL_EE2[0]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[2]
0	0	0	0	1	0	0	0	0	1	DBL_NE2[0]
0	0	0	0	1	0	0	0	1	0	DBL_SW2_N3
0	0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	1	1	1	0	0	0	1	SNG_W1[4]
0	0	0	1	1	1	0	0	1	0	SNG_E1_N7
0	0	0	1	1	1	0	1	0	0	SNG_N1[4]
0	0	0	1	1	1	1	0	0	0	SNG_S1_N7
0	0	1	0	1	1	0	0	0	1	SNG_E1[0]
0	0	1	0	1	1	0	0	1	0	SNG_W1_N3
0	0	1	0	1	1	0	1	0	0	SNG_S1[0]
0	0	1	0	1	1	1	0	0	0	SNG_N1[0]
0	1	0	0	1	1	0	0	0	1	DBL_WW2_N3
0	1	0	0	1	1	0	0	1	0	OUT[0]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	0	0	0	1	DBL_NW2[0]
1	0	0	0	1	1	0	0	1	0	OUT[12]
1	0	0	0	1	1	0	1	0	0	OUT[22]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[1]
Bits										Destination
MAIN[15][9]	MAIN[14][9]	MAIN[21][8]	MAIN[22][9]	MAIN[21][9]	MAIN[23][9]	MAIN[17][9]	MAIN[19][9]	MAIN[17][8]	MAIN[19][8]	IMUX_IMUX[1]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[0]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	0	1	1	0	0	0	DBL_WW2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[0]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	1	0	0	0	DBL_NW2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[0]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[4]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[0]
0	1	0	0	1	1	0	0	1	0	OUT[4]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[3]
0	1	0	0	1	1	1	0	0	0	IMUX_GFAN[0]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[0]
1	0	0	0	1	1	0	0	1	0	OUT[8]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[7]
1	0	0	0	1	1	1	0	0	0	OUT[18]

virtex6 INT switchbox INT muxes IMUX_IMUX[2]
Bits										Destination
MAIN[15][17]	MAIN[14][17]	MAIN[21][16]	MAIN[22][17]	MAIN[21][17]	MAIN[23][17]	MAIN[17][17]	MAIN[19][17]	MAIN[19][16]	MAIN[17][16]	IMUX_IMUX[2]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	0	1	1	0	0	0	DBL_EE2[1]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	0	1	0	1	0	0	0	DBL_SE2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[5]
0	1	0	0	1	1	0	0	0	1	OUT[5]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE[0]
0	1	0	0	1	1	1	0	0	0	IMUX_GFAN[0]
1	0	0	0	1	1	0	0	0	1	OUT[9]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[1]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	1	0	0	0	OUT[19]

virtex6 INT switchbox INT muxes IMUX_IMUX[3]
Bits										Destination
MAIN[15][25]	MAIN[14][25]	MAIN[21][24]	MAIN[22][25]	MAIN[21][25]	MAIN[23][25]	MAIN[19][25]	MAIN[17][25]	MAIN[17][24]	MAIN[19][24]	IMUX_IMUX[3]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[1]
0	1	0	0	1	1	0	0	1	0	OUT[1]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[1]
1	0	0	0	1	1	0	0	1	0	OUT[13]
1	0	0	0	1	1	0	1	0	0	OUT[23]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[7]

virtex6 INT switchbox INT muxes IMUX_IMUX[4]
Bits										Destination
MAIN[15][33]	MAIN[14][33]	MAIN[21][32]	MAIN[22][33]	MAIN[21][33]	MAIN[23][33]	MAIN[19][33]	MAIN[17][33]	MAIN[19][32]	MAIN[17][32]	IMUX_IMUX[4]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	OUT[2]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[1]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[0]
1	0	0	0	1	1	0	0	0	1	OUT[14]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[2]
1	0	0	0	1	1	0	1	0	0	OUT[20]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_IMUX[5]
Bits										Destination
MAIN[15][41]	MAIN[14][41]	MAIN[21][40]	MAIN[22][41]	MAIN[21][41]	MAIN[23][41]	MAIN[19][41]	MAIN[17][41]	MAIN[17][40]	MAIN[19][40]	IMUX_IMUX[5]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[2]
0	1	0	0	1	1	0	0	1	0	OUT[6]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[2]
1	0	0	0	1	1	0	0	1	0	OUT[10]
1	0	0	0	1	1	0	1	0	0	OUT[16]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_IMUX[6]
Bits										Destination
MAIN[15][49]	MAIN[14][49]	MAIN[21][48]	MAIN[22][49]	MAIN[21][49]	MAIN[23][49]	MAIN[19][49]	MAIN[17][49]	MAIN[19][48]	MAIN[17][48]	IMUX_IMUX[6]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	OUT[7]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[2]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	0	0	1	1	0	0	0	1	OUT[11]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[3]
1	0	0	0	1	1	0	1	0	0	OUT[17]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[7]
Bits										Destination
MAIN[15][57]	MAIN[14][57]	MAIN[21][56]	MAIN[22][57]	MAIN[21][57]	MAIN[23][57]	MAIN[19][57]	MAIN[17][57]	MAIN[17][56]	MAIN[19][56]	IMUX_IMUX[7]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[6]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N1_S0
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[3]
0	1	0	0	1	1	0	0	1	0	OUT[3]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[3]
1	0	0	0	1	1	0	0	1	0	OUT[15]
1	0	0	0	1	1	0	1	0	0	OUT[21]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[3]

virtex6 INT switchbox INT muxes IMUX_IMUX[8]
Bits										Destination
MAIN[14][2]	MAIN[15][2]	MAIN[21][2]	MAIN[22][3]	MAIN[22][2]	MAIN[20][2]	MAIN[18][2]	MAIN[16][3]	MAIN[16][2]	MAIN[18][3]	IMUX_IMUX[8]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_NN2[0]
0	0	0	0	0	1	0	0	1	0	DBL_SS2_N3
0	0	0	0	0	1	0	1	0	0	DBL_EE2[0]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[2]
0	0	0	0	1	0	0	0	0	1	DBL_NE2[0]
0	0	0	0	1	0	0	0	1	0	DBL_SW2_N3
0	0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	1	1	1	0	0	0	1	SNG_W1[4]
0	0	0	1	1	1	0	0	1	0	SNG_E1_N7
0	0	0	1	1	1	0	1	0	0	SNG_N1[4]
0	0	0	1	1	1	1	0	0	0	SNG_S1_N7
0	0	1	0	1	1	0	0	0	1	SNG_E1[0]
0	0	1	0	1	1	0	0	1	0	SNG_W1_N3
0	0	1	0	1	1	0	1	0	0	SNG_S1[0]
0	0	1	0	1	1	1	0	0	0	SNG_N1[0]
0	1	0	0	1	1	0	0	0	1	DBL_WW2_N3
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	OUT[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	0	0	0	1	DBL_NW2[0]
1	0	0	0	1	1	0	0	1	0	OUT[22]
1	0	0	0	1	1	0	1	0	0	OUT[12]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[9]
Bits										Destination
MAIN[14][10]	MAIN[15][10]	MAIN[22][11]	MAIN[21][10]	MAIN[22][10]	MAIN[20][10]	MAIN[16][11]	MAIN[18][10]	MAIN[16][10]	MAIN[18][11]	IMUX_IMUX[9]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[0]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	0	1	1	0	0	0	DBL_WW2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[0]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	1	0	0	0	DBL_NW2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[0]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[4]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[0]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[3]
0	1	0	0	1	1	1	0	0	0	OUT[4]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[0]
1	0	0	0	1	1	0	0	1	0	OUT[18]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[7]
1	0	0	0	1	1	1	0	0	0	OUT[8]

virtex6 INT switchbox INT muxes IMUX_IMUX[10]
Bits										Destination
MAIN[14][18]	MAIN[15][18]	MAIN[22][19]	MAIN[21][18]	MAIN[22][18]	MAIN[20][18]	MAIN[16][19]	MAIN[18][18]	MAIN[18][19]	MAIN[16][18]	IMUX_IMUX[10]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	0	1	1	0	0	0	DBL_EE2[1]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	0	1	0	1	0	0	0	DBL_SE2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[5]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[0]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE[0]
0	1	0	0	1	1	1	0	0	0	OUT[5]
1	0	0	0	1	1	0	0	0	1	OUT[19]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[1]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	1	0	0	0	OUT[9]

virtex6 INT switchbox INT muxes IMUX_IMUX[11]
Bits										Destination
MAIN[14][26]	MAIN[15][26]	MAIN[22][27]	MAIN[21][26]	MAIN[22][26]	MAIN[20][26]	MAIN[18][26]	MAIN[16][27]	MAIN[16][26]	MAIN[18][27]	IMUX_IMUX[11]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[1]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	OUT[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[1]
1	0	0	0	1	1	0	0	1	0	OUT[23]
1	0	0	0	1	1	0	1	0	0	OUT[13]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[7]

virtex6 INT switchbox INT muxes IMUX_IMUX[12]
Bits										Destination
MAIN[14][34]	MAIN[15][34]	MAIN[22][35]	MAIN[21][34]	MAIN[22][34]	MAIN[20][34]	MAIN[18][34]	MAIN[16][35]	MAIN[18][35]	MAIN[16][34]	IMUX_IMUX[12]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[1]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[1]
0	1	0	0	1	1	0	1	0	0	OUT[2]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[0]
1	0	0	0	1	1	0	0	0	1	OUT[20]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[2]
1	0	0	0	1	1	0	1	0	0	OUT[14]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_IMUX[13]
Bits										Destination
MAIN[14][42]	MAIN[15][42]	MAIN[22][43]	MAIN[21][42]	MAIN[22][42]	MAIN[20][42]	MAIN[18][42]	MAIN[16][43]	MAIN[16][42]	MAIN[18][43]	IMUX_IMUX[13]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[2]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[1]
0	1	0	0	1	1	0	1	0	0	OUT[6]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[2]
1	0	0	0	1	1	0	0	1	0	OUT[16]
1	0	0	0	1	1	0	1	0	0	OUT[10]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_IMUX[14]
Bits										Destination
MAIN[14][50]	MAIN[15][50]	MAIN[22][51]	MAIN[21][50]	MAIN[22][50]	MAIN[20][50]	MAIN[18][50]	MAIN[16][51]	MAIN[18][51]	MAIN[16][50]	IMUX_IMUX[14]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[1]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[2]
0	1	0	0	1	1	0	1	0	0	OUT[7]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	0	0	1	1	0	0	0	1	OUT[17]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[3]
1	0	0	0	1	1	0	1	0	0	OUT[11]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[15]
Bits										Destination
MAIN[14][58]	MAIN[15][58]	MAIN[22][59]	MAIN[21][58]	MAIN[22][58]	MAIN[20][58]	MAIN[18][58]	MAIN[16][59]	MAIN[16][58]	MAIN[18][59]	IMUX_IMUX[15]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[6]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N1_S0
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[3]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[1]
0	1	0	0	1	1	0	1	0	0	OUT[3]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[3]
1	0	0	0	1	1	0	0	1	0	OUT[21]
1	0	0	0	1	1	0	1	0	0	OUT[15]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[3]

virtex6 INT switchbox INT muxes IMUX_IMUX[16]
Bits										Destination
MAIN[15][3]	MAIN[14][3]	MAIN[13][2]	MAIN[20][3]	MAIN[23][3]	MAIN[21][3]	MAIN[19][3]	MAIN[17][3]	MAIN[17][2]	MAIN[19][2]	IMUX_IMUX[16]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_NN2[0]
0	0	0	0	0	1	0	0	1	0	DBL_SS2_N3
0	0	0	0	0	1	0	1	0	0	DBL_EE2[0]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[2]
0	0	0	0	1	0	0	0	0	1	DBL_NE2[0]
0	0	0	0	1	0	0	0	1	0	DBL_SW2_N3
0	0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	1	1	1	0	0	0	1	SNG_W1[4]
0	0	0	1	1	1	0	0	1	0	SNG_E1_N7
0	0	0	1	1	1	0	1	0	0	SNG_N1[4]
0	0	0	1	1	1	1	0	0	0	SNG_S1_N7
0	0	1	0	1	1	0	0	0	1	SNG_E1[0]
0	0	1	0	1	1	0	0	1	0	SNG_W1_N3
0	0	1	0	1	1	0	1	0	0	SNG_S1[0]
0	0	1	0	1	1	1	0	0	0	SNG_N1[0]
0	1	0	0	1	1	0	0	0	1	DBL_WW2_N3
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	OUT[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	0	0	0	1	DBL_NW2[0]
1	0	0	0	1	1	0	0	1	0	OUT[22]
1	0	0	0	1	1	0	1	0	0	OUT[12]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[17]
Bits										Destination
MAIN[15][11]	MAIN[14][11]	MAIN[20][11]	MAIN[13][10]	MAIN[23][11]	MAIN[21][11]	MAIN[17][11]	MAIN[19][11]	MAIN[17][10]	MAIN[19][10]	IMUX_IMUX[17]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[0]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	0	1	1	0	0	0	DBL_WW2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[0]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	1	0	0	0	DBL_NW2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[0]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[4]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[0]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[3]
0	1	0	0	1	1	1	0	0	0	OUT[4]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[0]
1	0	0	0	1	1	0	0	1	0	OUT[18]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[7]
1	0	0	0	1	1	1	0	0	0	OUT[8]

virtex6 INT switchbox INT muxes IMUX_IMUX[18]
Bits										Destination
MAIN[15][19]	MAIN[14][19]	MAIN[20][19]	MAIN[13][18]	MAIN[23][19]	MAIN[21][19]	MAIN[17][19]	MAIN[19][19]	MAIN[19][18]	MAIN[17][18]	IMUX_IMUX[18]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	0	1	1	0	0	0	DBL_EE2[1]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	0	1	0	1	0	0	0	DBL_SE2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[5]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[0]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE[0]
0	1	0	0	1	1	1	0	0	0	OUT[5]
1	0	0	0	1	1	0	0	0	1	OUT[19]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[1]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	1	0	0	0	OUT[9]

virtex6 INT switchbox INT muxes IMUX_IMUX[19]
Bits										Destination
MAIN[15][27]	MAIN[14][27]	MAIN[20][27]	MAIN[13][26]	MAIN[23][27]	MAIN[21][27]	MAIN[19][27]	MAIN[17][27]	MAIN[17][26]	MAIN[19][26]	IMUX_IMUX[19]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[1]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	OUT[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[1]
1	0	0	0	1	1	0	0	1	0	OUT[23]
1	0	0	0	1	1	0	1	0	0	OUT[13]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[7]

virtex6 INT switchbox INT muxes IMUX_IMUX[20]
Bits										Destination
MAIN[15][35]	MAIN[14][35]	MAIN[20][35]	MAIN[13][34]	MAIN[23][35]	MAIN[21][35]	MAIN[19][35]	MAIN[17][35]	MAIN[19][34]	MAIN[17][34]	IMUX_IMUX[20]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[1]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[1]
0	1	0	0	1	1	0	1	0	0	OUT[2]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[0]
1	0	0	0	1	1	0	0	0	1	OUT[20]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[2]
1	0	0	0	1	1	0	1	0	0	OUT[14]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_IMUX[21]
Bits										Destination
MAIN[15][43]	MAIN[14][43]	MAIN[20][43]	MAIN[13][42]	MAIN[23][43]	MAIN[21][43]	MAIN[19][43]	MAIN[17][43]	MAIN[17][42]	MAIN[19][42]	IMUX_IMUX[21]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[2]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[1]
0	1	0	0	1	1	0	1	0	0	OUT[6]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[2]
1	0	0	0	1	1	0	0	1	0	OUT[16]
1	0	0	0	1	1	0	1	0	0	OUT[10]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_IMUX[22]
Bits										Destination
MAIN[15][51]	MAIN[14][51]	MAIN[20][51]	MAIN[13][50]	MAIN[23][51]	MAIN[21][51]	MAIN[19][51]	MAIN[17][51]	MAIN[19][50]	MAIN[17][50]	IMUX_IMUX[22]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[1]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[2]
0	1	0	0	1	1	0	1	0	0	OUT[7]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	0	0	1	1	0	0	0	1	OUT[17]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[3]
1	0	0	0	1	1	0	1	0	0	OUT[11]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[23]
Bits										Destination
MAIN[15][59]	MAIN[14][59]	MAIN[20][59]	MAIN[13][58]	MAIN[23][59]	MAIN[21][59]	MAIN[19][59]	MAIN[17][59]	MAIN[17][58]	MAIN[19][58]	IMUX_IMUX[23]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[6]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N1_S0
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[3]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[1]
0	1	0	0	1	1	0	1	0	0	OUT[3]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[3]
1	0	0	0	1	1	0	0	1	0	OUT[21]
1	0	0	0	1	1	0	1	0	0	OUT[15]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[3]

virtex6 INT switchbox INT muxes IMUX_IMUX[24]
Bits										Destination
MAIN[14][4]	MAIN[15][4]	MAIN[13][4]	MAIN[20][5]	MAIN[22][4]	MAIN[20][4]	MAIN[18][4]	MAIN[16][4]	MAIN[18][5]	MAIN[16][5]	IMUX_IMUX[24]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[0]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[0]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[0]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[0]
0	0	0	1	1	1	0	1	0	0	SNG_S1[0]
0	0	0	1	1	1	1	0	0	0	SNG_N1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[4]
0	0	1	0	1	1	0	1	0	0	SNG_N1[4]
0	0	1	0	1	1	1	0	0	0	SNG_S1_N7
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[0]
0	1	0	0	1	1	0	0	1	0	DBL_WW2_N3
0	1	0	0	1	1	0	1	0	0	OUT[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	0	0	0	1	OUT[22]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[0]
1	0	0	0	1	1	0	1	0	0	OUT[12]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[25]
Bits										Destination
MAIN[14][12]	MAIN[15][12]	MAIN[13][12]	MAIN[20][13]	MAIN[22][12]	MAIN[20][12]	MAIN[16][12]	MAIN[18][12]	MAIN[16][13]	MAIN[18][13]	IMUX_IMUX[25]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	0	1	1	0	0	0	DBL_WW2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	1	0	0	0	DBL_NW2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[0]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[3]
0	1	0	0	1	1	1	0	0	0	OUT[4]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[0]
1	0	0	0	1	1	0	0	1	0	OUT[18]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[7]
1	0	0	0	1	1	1	0	0	0	OUT[8]

virtex6 INT switchbox INT muxes IMUX_IMUX[26]
Bits										Destination
MAIN[14][20]	MAIN[15][20]	MAIN[13][20]	MAIN[20][21]	MAIN[22][20]	MAIN[20][20]	MAIN[16][20]	MAIN[18][20]	MAIN[18][21]	MAIN[16][21]	IMUX_IMUX[26]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	0	1	1	0	0	0	DBL_EE2[1]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	0	1	0	1	0	0	0	DBL_SE2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[5]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[0]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE[0]
0	1	0	0	1	1	1	0	0	0	OUT[5]
1	0	0	0	1	1	0	0	0	1	OUT[19]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[1]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	1	0	0	0	OUT[9]

virtex6 INT switchbox INT muxes IMUX_IMUX[27]
Bits										Destination
MAIN[14][28]	MAIN[15][28]	MAIN[13][28]	MAIN[20][29]	MAIN[22][28]	MAIN[20][28]	MAIN[18][28]	MAIN[16][28]	MAIN[16][29]	MAIN[18][29]	IMUX_IMUX[27]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[1]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	OUT[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[1]
1	0	0	0	1	1	0	0	1	0	OUT[23]
1	0	0	0	1	1	0	1	0	0	OUT[13]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[7]

virtex6 INT switchbox INT muxes IMUX_IMUX[28]
Bits										Destination
MAIN[14][36]	MAIN[15][36]	MAIN[13][36]	MAIN[20][37]	MAIN[22][36]	MAIN[20][36]	MAIN[18][36]	MAIN[16][36]	MAIN[18][37]	MAIN[16][37]	IMUX_IMUX[28]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[1]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[1]
0	1	0	0	1	1	0	1	0	0	OUT[2]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[0]
1	0	0	0	1	1	0	0	0	1	OUT[20]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[2]
1	0	0	0	1	1	0	1	0	0	OUT[14]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_IMUX[29]
Bits										Destination
MAIN[14][44]	MAIN[15][44]	MAIN[13][44]	MAIN[20][45]	MAIN[22][44]	MAIN[20][44]	MAIN[18][44]	MAIN[16][44]	MAIN[16][45]	MAIN[18][45]	IMUX_IMUX[29]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[2]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[1]
0	1	0	0	1	1	0	1	0	0	OUT[6]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[2]
1	0	0	0	1	1	0	0	1	0	OUT[16]
1	0	0	0	1	1	0	1	0	0	OUT[10]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_IMUX[30]
Bits										Destination
MAIN[14][52]	MAIN[15][52]	MAIN[13][52]	MAIN[20][53]	MAIN[22][52]	MAIN[20][52]	MAIN[18][52]	MAIN[16][52]	MAIN[18][53]	MAIN[16][53]	IMUX_IMUX[30]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[1]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[2]
0	1	0	0	1	1	0	1	0	0	OUT[7]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	0	0	1	1	0	0	0	1	OUT[17]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[3]
1	0	0	0	1	1	0	1	0	0	OUT[11]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[31]
Bits										Destination
MAIN[14][60]	MAIN[15][60]	MAIN[13][60]	MAIN[20][61]	MAIN[22][60]	MAIN[20][60]	MAIN[18][60]	MAIN[16][60]	MAIN[16][61]	MAIN[18][61]	IMUX_IMUX[31]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2_S0
0	0	0	0	0	1	0	1	0	0	DBL_WW2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[6]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2_S0
0	0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1_S0
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N1_S0
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1_S4
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[3]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[1]
0	1	0	0	1	1	0	1	0	0	OUT[3]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[3]
1	0	0	0	1	1	0	0	1	0	OUT[21]
1	0	0	0	1	1	0	1	0	0	OUT[15]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[3]

virtex6 INT switchbox INT muxes IMUX_IMUX[32]
Bits										Destination
MAIN[15][5]	MAIN[14][5]	MAIN[21][4]	MAIN[22][5]	MAIN[21][5]	MAIN[23][5]	MAIN[19][5]	MAIN[17][4]	MAIN[19][4]	MAIN[17][5]	IMUX_IMUX[32]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[0]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[0]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[0]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[0]
0	0	0	1	1	1	0	1	0	0	SNG_S1[0]
0	0	0	1	1	1	1	0	0	0	SNG_N1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[4]
0	0	1	0	1	1	0	1	0	0	SNG_N1[4]
0	0	1	0	1	1	1	0	0	0	SNG_S1_N7
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[0]
0	1	0	0	1	1	0	0	1	0	DBL_WW2_N3
0	1	0	0	1	1	0	1	0	0	OUT[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	0	0	0	1	OUT[22]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[0]
1	0	0	0	1	1	0	1	0	0	OUT[12]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[33]
Bits										Destination
MAIN[15][13]	MAIN[14][13]	MAIN[21][12]	MAIN[22][13]	MAIN[21][13]	MAIN[23][13]	MAIN[17][12]	MAIN[19][13]	MAIN[17][13]	MAIN[19][12]	IMUX_IMUX[33]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	0	1	1	0	0	0	DBL_WW2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	1	0	0	0	DBL_NW2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[0]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[3]
0	1	0	0	1	1	1	0	0	0	OUT[4]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[0]
1	0	0	0	1	1	0	0	1	0	OUT[18]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[7]
1	0	0	0	1	1	1	0	0	0	OUT[8]

virtex6 INT switchbox INT muxes IMUX_IMUX[34]
Bits										Destination
MAIN[15][21]	MAIN[14][21]	MAIN[21][20]	MAIN[22][21]	MAIN[21][21]	MAIN[23][21]	MAIN[17][20]	MAIN[19][21]	MAIN[19][20]	MAIN[17][21]	IMUX_IMUX[34]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	0	1	1	0	0	0	DBL_EE2[1]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	0	1	0	1	0	0	0	DBL_SE2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[5]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[0]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE[0]
0	1	0	0	1	1	1	0	0	0	OUT[5]
1	0	0	0	1	1	0	0	0	1	OUT[19]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[1]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	1	0	0	0	OUT[9]

virtex6 INT switchbox INT muxes IMUX_IMUX[35]
Bits										Destination
MAIN[15][29]	MAIN[14][29]	MAIN[21][28]	MAIN[22][29]	MAIN[21][29]	MAIN[23][29]	MAIN[19][29]	MAIN[17][28]	MAIN[17][29]	MAIN[19][28]	IMUX_IMUX[35]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[1]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[0]
0	1	0	0	1	1	0	1	0	0	OUT[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[1]
1	0	0	0	1	1	0	0	1	0	OUT[23]
1	0	0	0	1	1	0	1	0	0	OUT[13]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[7]

virtex6 INT switchbox INT muxes IMUX_IMUX[36]
Bits										Destination
MAIN[15][37]	MAIN[14][37]	MAIN[21][36]	MAIN[22][37]	MAIN[21][37]	MAIN[23][37]	MAIN[19][37]	MAIN[17][36]	MAIN[19][36]	MAIN[17][37]	IMUX_IMUX[36]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[1]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[1]
0	1	0	0	1	1	0	1	0	0	OUT[2]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[0]
1	0	0	0	1	1	0	0	0	1	OUT[20]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[2]
1	0	0	0	1	1	0	1	0	0	OUT[14]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_IMUX[37]
Bits										Destination
MAIN[15][45]	MAIN[14][45]	MAIN[21][44]	MAIN[22][45]	MAIN[21][45]	MAIN[23][45]	MAIN[19][45]	MAIN[17][44]	MAIN[17][45]	MAIN[19][44]	IMUX_IMUX[37]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[2]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[1]
0	1	0	0	1	1	0	1	0	0	OUT[6]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[2]
1	0	0	0	1	1	0	0	1	0	OUT[16]
1	0	0	0	1	1	0	1	0	0	OUT[10]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_IMUX[38]
Bits										Destination
MAIN[15][53]	MAIN[14][53]	MAIN[21][52]	MAIN[22][53]	MAIN[21][53]	MAIN[23][53]	MAIN[19][53]	MAIN[17][52]	MAIN[19][52]	MAIN[17][53]	IMUX_IMUX[38]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	IMUX_GFAN[1]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[2]
0	1	0	0	1	1	0	1	0	0	OUT[7]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	0	0	1	1	0	0	0	1	OUT[17]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[3]
1	0	0	0	1	1	0	1	0	0	OUT[11]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[39]
Bits										Destination
MAIN[15][61]	MAIN[14][61]	MAIN[21][60]	MAIN[22][61]	MAIN[21][61]	MAIN[23][61]	MAIN[19][61]	MAIN[17][60]	MAIN[17][61]	MAIN[19][60]	IMUX_IMUX[39]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2_S0
0	0	0	0	0	1	0	1	0	0	DBL_WW2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[6]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2_S0
0	0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1_S0
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N1_S0
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1_S4
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[3]
0	1	0	0	1	1	0	0	1	0	IMUX_GFAN[1]
0	1	0	0	1	1	0	1	0	0	OUT[3]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[3]
1	0	0	0	1	1	0	0	1	0	OUT[21]
1	0	0	0	1	1	0	1	0	0	OUT[15]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[3]

virtex6 INT switchbox INT muxes IMUX_IMUX[40]
Bits										Destination
MAIN[14][6]	MAIN[15][6]	MAIN[22][7]	MAIN[21][6]	MAIN[22][6]	MAIN[20][6]	MAIN[18][6]	MAIN[16][6]	MAIN[18][7]	MAIN[16][7]	IMUX_IMUX[40]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[0]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[0]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[0]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[0]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[0]
0	0	0	1	1	1	0	1	0	0	SNG_S1[0]
0	0	0	1	1	1	1	0	0	0	SNG_N1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[4]
0	0	1	0	1	1	0	1	0	0	SNG_N1[4]
0	0	1	0	1	1	1	0	0	0	SNG_S1_N7
0	1	0	0	1	1	0	0	0	1	OUT[0]
0	1	0	0	1	1	0	0	1	0	DBL_WW2_N3
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	0	0	0	1	OUT[12]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[0]
1	0	0	0	1	1	0	1	0	0	OUT[22]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[41]
Bits										Destination
MAIN[14][14]	MAIN[15][14]	MAIN[22][15]	MAIN[21][14]	MAIN[22][14]	MAIN[20][14]	MAIN[16][14]	MAIN[18][14]	MAIN[16][15]	MAIN[18][15]	IMUX_IMUX[41]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[0]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[6]
0	0	0	0	0	1	1	0	0	0	DBL_WW2[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[0]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	1	0	0	0	DBL_NW2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[0]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[0]
0	0	1	0	1	1	0	0	0	1	SNG_E1[4]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[4]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[0]
0	1	0	0	1	1	0	0	1	0	OUT[4]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[3]
0	1	0	0	1	1	1	0	0	0	IMUX_GFAN[0]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[0]
1	0	0	0	1	1	0	0	1	0	OUT[8]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[7]
1	0	0	0	1	1	1	0	0	0	OUT[18]

virtex6 INT switchbox INT muxes IMUX_IMUX[42]
Bits										Destination
MAIN[14][22]	MAIN[15][22]	MAIN[22][23]	MAIN[21][22]	MAIN[22][22]	MAIN[20][22]	MAIN[16][22]	MAIN[18][22]	MAIN[18][23]	MAIN[16][23]	IMUX_IMUX[42]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[1]
0	0	0	0	0	1	0	1	0	0	IMUX_FAN_BOUNCE[7]
0	0	0	0	0	1	1	0	0	0	DBL_EE2[1]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[1]
0	0	0	0	1	0	0	1	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	0	1	0	1	0	0	0	DBL_SE2[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[1]
0	0	0	1	1	1	0	1	0	0	SNG_N1[1]
0	0	0	1	1	1	1	0	0	0	SNG_S1[1]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[5]
0	0	1	0	1	1	0	1	0	0	SNG_S0_S4
0	0	1	0	1	1	1	0	0	0	SNG_N1[5]
0	1	0	0	1	1	0	0	0	1	OUT[5]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[0]
0	1	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE[0]
0	1	0	0	1	1	1	0	0	0	IMUX_GFAN[0]
1	0	0	0	1	1	0	0	0	1	OUT[9]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[1]
1	0	0	0	1	1	0	1	0	0	IMUX_BYP_BOUNCE_N[6]
1	0	0	0	1	1	1	0	0	0	OUT[19]

virtex6 INT switchbox INT muxes IMUX_IMUX[43]
Bits										Destination
MAIN[14][30]	MAIN[15][30]	MAIN[22][31]	MAIN[21][30]	MAIN[22][30]	MAIN[20][30]	MAIN[18][30]	MAIN[16][30]	MAIN[16][31]	MAIN[18][31]	IMUX_IMUX[43]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[1]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[1]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE[5]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[1]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[1]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[1]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[5]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[5]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[1]
0	1	0	0	1	1	0	0	1	0	OUT[1]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[0]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[1]
1	0	0	0	1	1	0	0	1	0	OUT[13]
1	0	0	0	1	1	0	1	0	0	OUT[23]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE_N[7]

virtex6 INT switchbox INT muxes IMUX_IMUX[44]
Bits										Destination
MAIN[14][38]	MAIN[15][38]	MAIN[22][39]	MAIN[21][38]	MAIN[22][38]	MAIN[20][38]	MAIN[18][38]	MAIN[16][38]	MAIN[18][39]	MAIN[16][39]	IMUX_IMUX[44]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[2]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[2]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[2]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[1]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[2]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N1[2]
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[6]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[5]
0	1	0	0	1	1	0	0	0	1	OUT[2]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[1]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[0]
1	0	0	0	1	1	0	0	0	1	OUT[14]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[2]
1	0	0	0	1	1	0	1	0	0	OUT[20]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]

virtex6 INT switchbox INT muxes IMUX_IMUX[45]
Bits										Destination
MAIN[14][46]	MAIN[15][46]	MAIN[22][47]	MAIN[21][46]	MAIN[22][46]	MAIN[20][46]	MAIN[18][46]	MAIN[16][46]	MAIN[16][47]	MAIN[18][47]	IMUX_IMUX[45]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[2]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_WW2[2]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[2]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_NW2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE[3]
0	0	0	1	1	1	0	0	0	1	SNG_W1[2]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[2]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[6]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[6]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[2]
0	1	0	0	1	1	0	0	1	0	OUT[6]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[2]
1	0	0	0	1	1	0	0	1	0	OUT[10]
1	0	0	0	1	1	0	1	0	0	OUT[16]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[1]

virtex6 INT switchbox INT muxes IMUX_IMUX[46]
Bits										Destination
MAIN[14][54]	MAIN[15][54]	MAIN[22][55]	MAIN[21][54]	MAIN[22][54]	MAIN[20][54]	MAIN[18][54]	MAIN[16][54]	MAIN[18][55]	MAIN[16][55]	IMUX_IMUX[46]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2[3]
0	0	0	0	0	1	0	1	0	0	DBL_EE2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[2]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2[3]
0	0	0	0	1	0	0	1	0	0	DBL_SE2[3]
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[0]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1[3]
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N0_N3
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1[7]
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[6]
0	1	0	0	1	1	0	0	0	1	OUT[7]
0	1	0	0	1	1	0	0	1	0	DBL_WW2[2]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[4]
1	0	0	0	1	1	0	0	0	1	OUT[11]
1	0	0	0	1	1	0	0	1	0	DBL_NW2[3]
1	0	0	0	1	1	0	1	0	0	OUT[17]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[2]

virtex6 INT switchbox INT muxes IMUX_IMUX[47]
Bits										Destination
MAIN[14][62]	MAIN[15][62]	MAIN[22][63]	MAIN[21][62]	MAIN[22][62]	MAIN[20][62]	MAIN[18][62]	MAIN[16][62]	MAIN[16][63]	MAIN[18][63]	IMUX_IMUX[47]
										Source
0	0	0	0	0	0	0	0	0	0	TIE_1
0	0	0	0	0	1	0	0	0	1	DBL_SS2[3]
0	0	0	0	0	1	0	0	1	0	DBL_NN2_S0
0	0	0	0	0	1	0	1	0	0	DBL_WW2[3]
0	0	0	0	0	1	1	0	0	0	IMUX_FAN_BOUNCE_S[6]
0	0	0	0	1	0	0	0	0	1	DBL_SW2[3]
0	0	0	0	1	0	0	0	1	0	DBL_NE2_S0
0	0	0	0	1	0	0	1	0	0	DBL_NW2_S0
0	0	0	0	1	0	1	0	0	0	IMUX_FAN_BOUNCE_S[4]
0	0	0	1	1	1	0	0	0	1	SNG_W1[3]
0	0	0	1	1	1	0	0	1	0	SNG_E1_S0
0	0	0	1	1	1	0	1	0	0	SNG_S1[3]
0	0	0	1	1	1	1	0	0	0	SNG_N1_S0
0	0	1	0	1	1	0	0	0	1	SNG_E1[7]
0	0	1	0	1	1	0	0	1	0	SNG_W1_S4
0	0	1	0	1	1	0	1	0	0	SNG_N1[7]
0	0	1	0	1	1	1	0	0	0	SNG_S1[7]
0	1	0	0	1	1	0	0	0	1	DBL_EE2[3]
0	1	0	0	1	1	0	0	1	0	OUT[3]
0	1	0	0	1	1	0	1	0	0	IMUX_GFAN[1]
0	1	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[5]
1	0	0	0	1	1	0	0	0	1	DBL_SE2[3]
1	0	0	0	1	1	0	0	1	0	OUT[15]
1	0	0	0	1	1	0	1	0	0	OUT[21]
1	0	0	0	1	1	1	0	0	0	IMUX_BYP_BOUNCE[3]

Bitstream

virtex6 INT rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B63	INT: mux QUAD_SW0[3] bit 6	INT: mux QUAD_SW0[3] bit 5	INT: mux QUAD_SW0[3] bit 8	INT: mux QUAD_SW0[3] bit 7	INT: mux DBL_WW0[3] bit 0	INT: mux SNG_S0_S4 bit 0	INT: mux DBL_WW0[3] bit 6	INT: mux DBL_WW0[3] bit 5	INT: mux DBL_WW0[3] bit 8	INT: mux DBL_WW0[3] bit 7	INT: mux SNG_S0_S4 bit 7	INT: mux SNG_S0_S4 bit 8	INT: mux SNG_S0_S4 bit 5	INT: mux SNG_S0_S4 bit 6	INT: mux IMUX_BYP[7] bit 8	INT: mux IMUX_BYP[7] bit 9	INT: mux IMUX_IMUX[47] bit 1	INT: mux IMUX_BYP[7] bit 1	INT: mux IMUX_IMUX[47] bit 0	INT: mux IMUX_BYP[7] bit 3	INT: mux IMUX_BYP[7] bit 7	INT: mux IMUX_BYP[7] bit 4	INT: mux IMUX_IMUX[47] bit 7	INT: mux IMUX_BYP[7] bit 5	-	-	-	-
B62	INT: mux QUAD_SW0[3] bit 3	INT: mux QUAD_SS0[3] bit 0	INT: mux QUAD_SW0[3] bit 2	INT: mux QUAD_SS0[3] bit 3	INT: mux SNG_S0_S4 bit 2	INT: mux QUAD_SW0[3] bit 0	INT: mux DBL_WW0[3] bit 4	INT: mux DBL_SW0[3] bit 2	INT: mux DBL_WW0[3] bit 2	INT: mux DBL_SW0[3] bit 0	INT: mux SNG_S0_S4 bit 4	INT: mux SNG_W0[2] bit 0	INT: mux SNG_W0[2] bit 4	INT: mux IMUX_BYP[7] bit 6	INT: mux IMUX_IMUX[47] bit 9	INT: mux IMUX_IMUX[47] bit 8	INT: mux IMUX_IMUX[47] bit 2	INT: mux IMUX_BYP[7] bit 2	INT: mux IMUX_IMUX[47] bit 3	INT: mux IMUX_BYP[7] bit 0	INT: mux IMUX_IMUX[47] bit 4	INT: mux IMUX_IMUX[47] bit 6	INT: mux IMUX_IMUX[47] bit 5	-	-	-	-	-
B61	INT: mux QUAD_SW0[3] bit 1	INT: mux QUAD_SS0[3] bit 4	INT: mux QUAD_SW0[3] bit 4	INT: mux QUAD_SS0[3] bit 2	INT: mux DBL_SW0[3] bit 1	INT: mux SNG_W0[2] bit 2	INT: mux DBL_WW0[3] bit 3	INT: mux DBL_SW0[3] bit 4	INT: mux DBL_WW0[3] bit 1	INT: mux DBL_SW0[3] bit 3	INT: mux SNG_S0_S4 bit 1	INT: mux SNG_W0[2] bit 3	INT: mux SNG_W0[2] bit 1	INT: mux SNG_S0_S4 bit 3	INT: mux IMUX_IMUX[39] bit 8	INT: mux IMUX_IMUX[39] bit 9	INT: mux IMUX_IMUX[31] bit 1	INT: mux IMUX_IMUX[39] bit 1	INT: mux IMUX_IMUX[31] bit 0	INT: mux IMUX_IMUX[39] bit 3	INT: mux IMUX_IMUX[31] bit 6	INT: mux IMUX_IMUX[39] bit 5	INT: mux IMUX_IMUX[39] bit 6	INT: mux IMUX_IMUX[39] bit 4	-	-	-	-
B60	INT: mux QUAD_SS0[3] bit 5	INT: mux QUAD_SS0[3] bit 6	INT: mux QUAD_SS0[3] bit 7	INT: mux QUAD_SS0[3] bit 8	INT: mux SNG_W0[2] bit 6	INT: mux QUAD_SS0[3] bit 1	INT: mux DBL_SW0[3] bit 5	INT: mux DBL_SW0[3] bit 6	INT: mux DBL_SW0[3] bit 7	INT: mux DBL_SW0[3] bit 8	INT: mux SNG_W0[2] bit 8	INT: mux SNG_W0[2] bit 7	INT: mux SNG_W0[2] bit 5	INT: mux IMUX_IMUX[31] bit 7	INT: mux IMUX_IMUX[31] bit 9	INT: mux IMUX_IMUX[31] bit 8	INT: mux IMUX_IMUX[31] bit 2	INT: mux IMUX_IMUX[39] bit 2	INT: mux IMUX_IMUX[31] bit 3	INT: mux IMUX_IMUX[39] bit 0	INT: mux IMUX_IMUX[31] bit 4	INT: mux IMUX_IMUX[39] bit 7	INT: mux IMUX_IMUX[31] bit 5	-	-	-	-	-
B59	INT: mux QUAD_SE0[3] bit 6	INT: mux QUAD_SE0[3] bit 5	INT: mux QUAD_SE0[3] bit 8	INT: mux QUAD_SE0[3] bit 7	INT: mux DBL_SS0[3] bit 1	INT: mux SNG_E0_S4 bit 1	INT: mux DBL_SS0[3] bit 6	INT: mux DBL_SS0[3] bit 5	INT: mux DBL_SS0[3] bit 8	INT: mux DBL_SS0[3] bit 7	INT: mux SNG_E0_S4 bit 7	INT: mux SNG_E0_S4 bit 8	INT: mux SNG_E0_S4 bit 5	INT: mux SNG_E0_S4 bit 6	INT: mux IMUX_IMUX[23] bit 8	INT: mux IMUX_IMUX[23] bit 9	INT: mux IMUX_IMUX[15] bit 2	INT: mux IMUX_IMUX[23] bit 2	INT: mux IMUX_IMUX[15] bit 0	INT: mux IMUX_IMUX[23] bit 3	INT: mux IMUX_IMUX[23] bit 7	INT: mux IMUX_IMUX[23] bit 4	INT: mux IMUX_IMUX[15] bit 7	INT: mux IMUX_IMUX[23] bit 5	-	-	-	-
B58	INT: mux QUAD_SE0[3] bit 3	INT: mux QUAD_EE0[3] bit 1	INT: mux QUAD_SE0[3] bit 0	INT: mux QUAD_EE0[3] bit 3	INT: mux SNG_E0_S4 bit 4	INT: mux QUAD_SE0[3] bit 1	INT: mux DBL_SS0[3] bit 4	INT: mux DBL_SE0[3] bit 3	INT: mux DBL_SS0[3] bit 3	INT: mux DBL_SE0[3] bit 1	INT: mux SNG_E0_S4 bit 2	INT: mux SNG_S0[3] bit 1	INT: mux SNG_S0[3] bit 2	INT: mux IMUX_IMUX[23] bit 6	INT: mux IMUX_IMUX[15] bit 9	INT: mux IMUX_IMUX[15] bit 8	INT: mux IMUX_IMUX[15] bit 1	INT: mux IMUX_IMUX[23] bit 1	INT: mux IMUX_IMUX[15] bit 3	INT: mux IMUX_IMUX[23] bit 0	INT: mux IMUX_IMUX[15] bit 4	INT: mux IMUX_IMUX[15] bit 6	INT: mux IMUX_IMUX[15] bit 5	INT: mux LH[0] bit 2	-	-	-	-
B57	INT: mux QUAD_SE0[3] bit 2	INT: mux QUAD_EE0[3] bit 4	INT: mux QUAD_SE0[3] bit 4	INT: mux QUAD_EE0[3] bit 0	INT: mux DBL_SE0[3] bit 0	INT: mux SNG_S0[3] bit 4	INT: mux DBL_SS0[3] bit 2	INT: mux DBL_SE0[3] bit 4	INT: mux DBL_SS0[3] bit 0	INT: mux DBL_SE0[3] bit 2	INT: mux SNG_E0_S4 bit 0	INT: mux SNG_S0[3] bit 3	INT: mux SNG_S0[3] bit 0	INT: mux SNG_E0_S4 bit 3	INT: mux IMUX_IMUX[7] bit 8	INT: mux IMUX_IMUX[7] bit 9	INT: mux IMUX_FAN[3] bit 2	INT: mux IMUX_IMUX[7] bit 2	INT: mux IMUX_FAN[3] bit 0	INT: mux IMUX_IMUX[7] bit 3	INT: mux IMUX_FAN[3] bit 6	INT: mux IMUX_IMUX[7] bit 5	INT: mux IMUX_IMUX[7] bit 6	INT: mux IMUX_IMUX[7] bit 4	-	-	-	-
B56	INT: mux QUAD_EE0[3] bit 5	INT: mux QUAD_EE0[3] bit 6	INT: mux QUAD_EE0[3] bit 7	INT: mux QUAD_EE0[3] bit 8	INT: mux SNG_S0[3] bit 6	INT: mux QUAD_EE0[3] bit 2	INT: mux DBL_SE0[3] bit 5	INT: mux DBL_SE0[3] bit 6	INT: mux DBL_SE0[3] bit 7	INT: mux DBL_SE0[3] bit 8	INT: mux SNG_S0[3] bit 8	INT: mux SNG_S0[3] bit 7	INT: mux SNG_S0[3] bit 5	INT: mux IMUX_FAN[3] bit 7	INT: mux IMUX_FAN[3] bit 9	INT: mux IMUX_FAN[3] bit 8	INT: mux IMUX_FAN[3] bit 1	INT: mux IMUX_IMUX[7] bit 1	INT: mux IMUX_FAN[3] bit 3	INT: mux IMUX_IMUX[7] bit 0	INT: mux IMUX_FAN[3] bit 5	INT: mux IMUX_IMUX[7] bit 7	INT: mux IMUX_FAN[3] bit 4	INT: mux LH[0] bit 3	-	-	-	-
B55	INT: mux QUAD_NE0[3] bit 6	INT: mux QUAD_NE0[3] bit 5	INT: mux QUAD_NE0[3] bit 8	INT: mux QUAD_NE0[3] bit 7	INT: mux DBL_EE0[3] bit 0	INT: mux SNG_N0[7] bit 0	INT: mux DBL_EE0[3] bit 6	INT: mux DBL_EE0[3] bit 5	INT: mux DBL_EE0[3] bit 8	INT: mux DBL_EE0[3] bit 7	INT: mux SNG_N0[7] bit 7	INT: mux SNG_N0[7] bit 8	INT: mux SNG_N0[7] bit 5	INT: mux SNG_N0[7] bit 6	INT: mux IMUX_BYP[6] bit 8	INT: mux IMUX_BYP[6] bit 9	INT: mux IMUX_IMUX[46] bit 0	INT: mux IMUX_BYP[6] bit 0	INT: mux IMUX_IMUX[46] bit 1	INT: mux IMUX_BYP[6] bit 3	INT: mux IMUX_BYP[6] bit 7	INT: mux IMUX_BYP[6] bit 4	INT: mux IMUX_IMUX[46] bit 7	INT: mux IMUX_BYP[6] bit 5	-	-	-	-
B54	INT: mux QUAD_NE0[3] bit 3	INT: mux QUAD_NN0[3] bit 1	INT: mux QUAD_NE0[3] bit 2	INT: mux QUAD_NN0[3] bit 3	INT: mux SNG_N0[7] bit 2	INT: mux QUAD_NE0[3] bit 1	INT: mux DBL_EE0[3] bit 4	INT: mux DBL_NE0[3] bit 2	INT: mux DBL_EE0[3] bit 2	INT: mux DBL_NE0[3] bit 0	INT: mux SNG_N0[7] bit 3	INT: mux SNG_E0[2] bit 0	INT: mux SNG_E0[2] bit 3	INT: mux IMUX_BYP[6] bit 6	INT: mux IMUX_IMUX[46] bit 9	INT: mux IMUX_IMUX[46] bit 8	INT: mux IMUX_IMUX[46] bit 2	INT: mux IMUX_BYP[6] bit 2	INT: mux IMUX_IMUX[46] bit 3	INT: mux IMUX_BYP[6] bit 1	INT: mux IMUX_IMUX[46] bit 4	INT: mux IMUX_IMUX[46] bit 6	INT: mux IMUX_IMUX[46] bit 5	INT: mux LH[0] bit 5	-	-	-	-
B53	INT: mux QUAD_NE0[3] bit 0	INT: mux QUAD_NN0[3] bit 4	INT: mux QUAD_NE0[3] bit 4	INT: mux QUAD_NN0[3] bit 2	INT: mux DBL_NE0[3] bit 1	INT: mux SNG_N0[7] bit 4	INT: mux DBL_EE0[3] bit 3	INT: mux DBL_NE0[3] bit 4	INT: mux DBL_EE0[3] bit 1	INT: mux DBL_NE0[3] bit 3	INT: mux SNG_N0[7] bit 1	INT: mux SNG_E0[2] bit 4	INT: mux SNG_E0[2] bit 1	INT: mux SNG_E0[2] bit 2	INT: mux IMUX_IMUX[38] bit 8	INT: mux IMUX_IMUX[38] bit 9	INT: mux IMUX_IMUX[30] bit 0	INT: mux IMUX_IMUX[38] bit 0	INT: mux IMUX_IMUX[30] bit 1	INT: mux IMUX_IMUX[38] bit 3	INT: mux IMUX_IMUX[30] bit 6	INT: mux IMUX_IMUX[38] bit 5	INT: mux IMUX_IMUX[38] bit 6	INT: mux IMUX_IMUX[38] bit 4	INT: mux LH[0] bit 6	-	-	-
B52	INT: mux QUAD_NN0[3] bit 5	INT: mux QUAD_NN0[3] bit 6	INT: mux QUAD_NN0[3] bit 7	INT: mux QUAD_NN0[3] bit 8	INT: mux SNG_E0[2] bit 6	INT: mux QUAD_NN0[3] bit 0	INT: mux DBL_NE0[3] bit 5	INT: mux DBL_NE0[3] bit 6	INT: mux DBL_NE0[3] bit 7	INT: mux DBL_NE0[3] bit 8	INT: mux SNG_E0[2] bit 8	INT: mux SNG_E0[2] bit 7	INT: mux SNG_E0[2] bit 5	INT: mux IMUX_IMUX[30] bit 7	INT: mux IMUX_IMUX[30] bit 9	INT: mux IMUX_IMUX[30] bit 8	INT: mux IMUX_IMUX[30] bit 2	INT: mux IMUX_IMUX[38] bit 2	INT: mux IMUX_IMUX[30] bit 3	INT: mux IMUX_IMUX[38] bit 1	INT: mux IMUX_IMUX[30] bit 4	INT: mux IMUX_IMUX[38] bit 7	INT: mux IMUX_IMUX[30] bit 5	INT: mux LH[0] bit 0	INT: mux LH[16] bit 5	INT: mux LH[0] bit 7	-	-
B51	INT: mux QUAD_NW0[3] bit 6	INT: mux QUAD_NW0[3] bit 5	INT: mux QUAD_NW0[3] bit 8	INT: mux QUAD_NW0[3] bit 7	INT: mux DBL_NN0[3] bit 1	INT: mux SNG_W0_S4 bit 1	INT: mux DBL_NN0[3] bit 6	INT: mux DBL_NN0[3] bit 5	INT: mux DBL_NN0[3] bit 8	INT: mux DBL_NN0[3] bit 7	INT: mux SNG_W0_S4 bit 7	INT: mux SNG_W0_S4 bit 8	INT: mux SNG_W0_S4 bit 5	INT: mux SNG_W0_S4 bit 6	INT: mux IMUX_IMUX[22] bit 8	INT: mux IMUX_IMUX[22] bit 9	INT: mux IMUX_IMUX[14] bit 2	INT: mux IMUX_IMUX[22] bit 2	INT: mux IMUX_IMUX[14] bit 1	INT: mux IMUX_IMUX[22] bit 3	INT: mux IMUX_IMUX[22] bit 7	INT: mux IMUX_IMUX[22] bit 4	INT: mux IMUX_IMUX[14] bit 7	INT: mux IMUX_IMUX[22] bit 5	INT: mux LH[16] bit 2	INT: mux LH[16] bit 3	-	-
B50	INT: mux QUAD_NW0[3] bit 3	INT: mux QUAD_WW0[3] bit 2	INT: mux QUAD_NW0[3] bit 0	INT: mux QUAD_WW0[3] bit 3	INT: mux SNG_W0_S4 bit 4	INT: mux QUAD_NW0[3] bit 2	INT: mux DBL_NN0[3] bit 4	INT: mux DBL_NW0[3] bit 3	INT: mux DBL_NN0[3] bit 3	INT: mux DBL_NW0[3] bit 1	INT: mux SNG_W0_S4 bit 3	INT: mux SNG_N0[2] bit 1	INT: mux SNG_N0[2] bit 3	INT: mux IMUX_IMUX[22] bit 6	INT: mux IMUX_IMUX[14] bit 9	INT: mux IMUX_IMUX[14] bit 8	INT: mux IMUX_IMUX[14] bit 0	INT: mux IMUX_IMUX[22] bit 0	INT: mux IMUX_IMUX[14] bit 3	INT: mux IMUX_IMUX[22] bit 1	INT: mux IMUX_IMUX[14] bit 4	INT: mux IMUX_IMUX[14] bit 6	INT: mux IMUX_IMUX[14] bit 5	INT: mux LH[0] bit 4	INT: mux LH[16] bit 1	INT: mux LH[16] bit 4	-	-
B49	INT: mux QUAD_NW0[3] bit 1	INT: mux QUAD_WW0[3] bit 4	INT: mux QUAD_NW0[3] bit 4	INT: mux QUAD_WW0[3] bit 0	INT: mux DBL_NW0[3] bit 0	INT: mux SNG_W0_S4 bit 2	INT: mux DBL_NN0[3] bit 2	INT: mux DBL_NW0[3] bit 4	INT: mux DBL_NN0[3] bit 0	INT: mux DBL_NW0[3] bit 2	INT: mux SNG_W0_S4 bit 0	INT: mux SNG_N0[2] bit 2	INT: mux SNG_N0[2] bit 0	INT: mux SNG_N0[2] bit 4	INT: mux IMUX_IMUX[6] bit 8	INT: mux IMUX_IMUX[6] bit 9	INT: mux IMUX_FAN[1] bit 2	INT: mux IMUX_IMUX[6] bit 2	INT: mux IMUX_FAN[1] bit 1	INT: mux IMUX_IMUX[6] bit 3	INT: mux IMUX_FAN[1] bit 6	INT: mux IMUX_IMUX[6] bit 5	INT: mux IMUX_IMUX[6] bit 6	INT: mux IMUX_IMUX[6] bit 4	-	INT: mux LH[16] bit 7	-	-
B48	INT: mux QUAD_WW0[3] bit 5	INT: mux QUAD_WW0[3] bit 6	INT: mux QUAD_WW0[3] bit 7	INT: mux QUAD_WW0[3] bit 8	INT: mux SNG_N0[2] bit 6	INT: mux QUAD_WW0[3] bit 1	INT: mux DBL_NW0[3] bit 5	INT: mux DBL_NW0[3] bit 6	INT: mux DBL_NW0[3] bit 7	INT: mux DBL_NW0[3] bit 8	INT: mux SNG_N0[2] bit 8	INT: mux SNG_N0[2] bit 7	INT: mux SNG_N0[2] bit 5	INT: mux IMUX_FAN[1] bit 7	INT: mux IMUX_FAN[1] bit 9	INT: mux IMUX_FAN[1] bit 8	INT: mux IMUX_FAN[1] bit 0	INT: mux IMUX_IMUX[6] bit 0	INT: mux IMUX_FAN[1] bit 3	INT: mux IMUX_IMUX[6] bit 1	INT: mux IMUX_FAN[1] bit 5	INT: mux IMUX_IMUX[6] bit 7	INT: mux IMUX_FAN[1] bit 4	INT: mux LH[0] bit 1	INT: mux IMUX_CTRL[1] bit 2	INT: mux IMUX_CTRL[0] bit 1	-	-
B47	INT: mux QUAD_SW0[2] bit 6	INT: mux QUAD_SW0[2] bit 5	INT: mux QUAD_SW0[2] bit 8	INT: mux QUAD_SW0[2] bit 7	INT: mux DBL_WW0[2] bit 0	INT: mux SNG_S0[7] bit 0	INT: mux DBL_WW0[2] bit 6	INT: mux DBL_WW0[2] bit 5	INT: mux DBL_WW0[2] bit 8	INT: mux DBL_WW0[2] bit 7	INT: mux SNG_S0[7] bit 7	INT: mux SNG_S0[7] bit 8	INT: mux SNG_S0[7] bit 5	INT: mux SNG_S0[7] bit 6	INT: mux IMUX_BYP[3] bit 8	INT: mux IMUX_BYP[3] bit 9	INT: mux IMUX_IMUX[45] bit 1	INT: mux IMUX_BYP[3] bit 1	INT: mux IMUX_IMUX[45] bit 0	INT: mux IMUX_BYP[3] bit 3	INT: mux IMUX_BYP[3] bit 7	INT: mux IMUX_BYP[3] bit 4	INT: mux IMUX_IMUX[45] bit 7	INT: mux IMUX_BYP[3] bit 5	-	-	-	-
B46	INT: mux QUAD_SW0[2] bit 4	INT: mux QUAD_SS0[2] bit 0	INT: mux QUAD_SW0[2] bit 2	INT: mux QUAD_SS0[2] bit 4	INT: mux SNG_S0[7] bit 2	INT: mux QUAD_SW0[2] bit 0	INT: mux DBL_WW0[2] bit 4	INT: mux DBL_SW0[2] bit 2	INT: mux DBL_WW0[2] bit 2	INT: mux DBL_SW0[2] bit 0	INT: mux SNG_S0[7] bit 4	INT: mux SNG_W0[1] bit 0	INT: mux SNG_W0[1] bit 4	INT: mux IMUX_BYP[3] bit 6	INT: mux IMUX_IMUX[45] bit 9	INT: mux IMUX_IMUX[45] bit 8	INT: mux IMUX_IMUX[45] bit 2	INT: mux IMUX_BYP[3] bit 2	INT: mux IMUX_IMUX[45] bit 3	INT: mux IMUX_BYP[3] bit 0	INT: mux IMUX_IMUX[45] bit 4	INT: mux IMUX_IMUX[45] bit 6	INT: mux IMUX_IMUX[45] bit 5	INT: mux LH[16] bit 6	-	INT: mux IMUX_CTRL[0] bit 2	-	-
B45	INT: mux QUAD_SW0[2] bit 1	INT: mux QUAD_SS0[2] bit 3	INT: mux QUAD_SW0[2] bit 3	INT: mux QUAD_SS0[2] bit 2	INT: mux DBL_SW0[2] bit 1	INT: mux SNG_W0[1] bit 2	INT: mux DBL_WW0[2] bit 3	INT: mux DBL_SW0[2] bit 4	INT: mux DBL_WW0[2] bit 1	INT: mux DBL_SW0[2] bit 3	INT: mux SNG_S0[7] bit 1	INT: mux SNG_W0[1] bit 3	INT: mux SNG_W0[1] bit 1	INT: mux SNG_S0[7] bit 3	INT: mux IMUX_IMUX[37] bit 8	INT: mux IMUX_IMUX[37] bit 9	INT: mux IMUX_IMUX[29] bit 1	INT: mux IMUX_IMUX[37] bit 1	INT: mux IMUX_IMUX[29] bit 0	INT: mux IMUX_IMUX[37] bit 3	INT: mux IMUX_IMUX[29] bit 6	INT: mux IMUX_IMUX[37] bit 5	INT: mux IMUX_IMUX[37] bit 6	INT: mux IMUX_IMUX[37] bit 4	-	-	-	-
B44	INT: mux QUAD_SS0[2] bit 5	INT: mux QUAD_SS0[2] bit 6	INT: mux QUAD_SS0[2] bit 7	INT: mux QUAD_SS0[2] bit 8	INT: mux SNG_W0[1] bit 6	INT: mux QUAD_SS0[2] bit 1	INT: mux DBL_SW0[2] bit 5	INT: mux DBL_SW0[2] bit 6	INT: mux DBL_SW0[2] bit 7	INT: mux DBL_SW0[2] bit 8	INT: mux SNG_W0[1] bit 8	INT: mux SNG_W0[1] bit 7	INT: mux SNG_W0[1] bit 5	INT: mux IMUX_IMUX[29] bit 7	INT: mux IMUX_IMUX[29] bit 9	INT: mux IMUX_IMUX[29] bit 8	INT: mux IMUX_IMUX[29] bit 2	INT: mux IMUX_IMUX[37] bit 2	INT: mux IMUX_IMUX[29] bit 3	INT: mux IMUX_IMUX[37] bit 0	INT: mux IMUX_IMUX[29] bit 4	INT: mux IMUX_IMUX[37] bit 7	INT: mux IMUX_IMUX[29] bit 5	INT: mux LH[16] bit 0	-	-	-	-
B43	INT: mux QUAD_SE0[2] bit 6	INT: mux QUAD_SE0[2] bit 5	INT: mux QUAD_SE0[2] bit 8	INT: mux QUAD_SE0[2] bit 7	INT: mux DBL_SS0[2] bit 1	INT: mux SNG_E0[7] bit 1	INT: mux DBL_SS0[2] bit 6	INT: mux DBL_SS0[2] bit 5	INT: mux DBL_SS0[2] bit 8	INT: mux DBL_SS0[2] bit 7	INT: mux SNG_E0[7] bit 7	INT: mux SNG_E0[7] bit 8	INT: mux SNG_E0[7] bit 5	INT: mux SNG_E0[7] bit 6	INT: mux IMUX_IMUX[21] bit 8	INT: mux IMUX_IMUX[21] bit 9	INT: mux IMUX_IMUX[13] bit 2	INT: mux IMUX_IMUX[21] bit 2	INT: mux IMUX_IMUX[13] bit 0	INT: mux IMUX_IMUX[21] bit 3	INT: mux IMUX_IMUX[21] bit 7	INT: mux IMUX_IMUX[21] bit 4	INT: mux IMUX_IMUX[13] bit 7	INT: mux IMUX_IMUX[21] bit 5	INT: mux IMUX_CLK[0] bit 3	INT: mux IMUX_CTRL[0] bit 5	-	-
B42	INT: mux QUAD_SE0[2] bit 4	INT: mux QUAD_EE0[2] bit 1	INT: mux QUAD_SE0[2] bit 0	INT: mux QUAD_EE0[2] bit 4	INT: mux SNG_E0[7] bit 4	INT: mux QUAD_SE0[2] bit 1	INT: mux DBL_SS0[2] bit 4	INT: mux DBL_SE0[2] bit 3	INT: mux DBL_SS0[2] bit 3	INT: mux DBL_SE0[2] bit 1	INT: mux SNG_E0[7] bit 2	INT: mux SNG_S0[2] bit 1	INT: mux SNG_S0[2] bit 2	INT: mux IMUX_IMUX[21] bit 6	INT: mux IMUX_IMUX[13] bit 9	INT: mux IMUX_IMUX[13] bit 8	INT: mux IMUX_IMUX[13] bit 1	INT: mux IMUX_IMUX[21] bit 1	INT: mux IMUX_IMUX[13] bit 3	INT: mux IMUX_IMUX[21] bit 0	INT: mux IMUX_IMUX[13] bit 4	INT: mux IMUX_IMUX[13] bit 6	INT: mux IMUX_IMUX[13] bit 5	INT: mux IMUX_CTRL[1] bit 5	INT: mux IMUX_CTRL[0] bit 8	-	-	-
B41	INT: mux QUAD_SE0[2] bit 2	INT: mux QUAD_EE0[2] bit 3	INT: mux QUAD_SE0[2] bit 3	INT: mux QUAD_EE0[2] bit 0	INT: mux DBL_SE0[2] bit 0	INT: mux SNG_S0[2] bit 4	INT: mux DBL_SS0[2] bit 2	INT: mux DBL_SE0[2] bit 4	INT: mux DBL_SS0[2] bit 0	INT: mux DBL_SE0[2] bit 2	INT: mux SNG_E0[7] bit 0	INT: mux SNG_S0[2] bit 3	INT: mux SNG_S0[2] bit 0	INT: mux SNG_E0[7] bit 3	INT: mux IMUX_IMUX[5] bit 8	INT: mux IMUX_IMUX[5] bit 9	INT: mux IMUX_FAN[5] bit 2	INT: mux IMUX_IMUX[5] bit 2	INT: mux IMUX_FAN[5] bit 0	INT: mux IMUX_IMUX[5] bit 3	INT: mux IMUX_FAN[5] bit 6	INT: mux IMUX_IMUX[5] bit 5	INT: mux IMUX_IMUX[5] bit 6	INT: mux IMUX_IMUX[5] bit 4	-	INT: mux IMUX_CTRL[0] bit 7	-	-
B40	INT: mux QUAD_EE0[2] bit 5	INT: mux QUAD_EE0[2] bit 6	INT: mux QUAD_EE0[2] bit 7	INT: mux QUAD_EE0[2] bit 8	INT: mux SNG_S0[2] bit 6	INT: mux QUAD_EE0[2] bit 2	INT: mux DBL_SE0[2] bit 5	INT: mux DBL_SE0[2] bit 6	INT: mux DBL_SE0[2] bit 7	INT: mux DBL_SE0[2] bit 8	INT: mux SNG_S0[2] bit 8	INT: mux SNG_S0[2] bit 7	INT: mux SNG_S0[2] bit 5	INT: mux IMUX_FAN[5] bit 7	INT: mux IMUX_FAN[5] bit 9	INT: mux IMUX_FAN[5] bit 8	INT: mux IMUX_FAN[5] bit 1	INT: mux IMUX_IMUX[5] bit 1	INT: mux IMUX_FAN[5] bit 3	INT: mux IMUX_IMUX[5] bit 0	INT: mux IMUX_FAN[5] bit 5	INT: mux IMUX_IMUX[5] bit 7	INT: mux IMUX_FAN[5] bit 4	INT: mux IMUX_CLK[0] bit 4	-	-	-	-
B39	INT: mux QUAD_NE0[2] bit 6	INT: mux QUAD_NE0[2] bit 5	INT: mux QUAD_NE0[2] bit 8	INT: mux QUAD_NE0[2] bit 7	INT: mux DBL_EE0[2] bit 0	INT: mux SNG_N0[6] bit 0	INT: mux DBL_EE0[2] bit 6	INT: mux DBL_EE0[2] bit 5	INT: mux DBL_EE0[2] bit 8	INT: mux DBL_EE0[2] bit 7	INT: mux SNG_N0[6] bit 7	INT: mux SNG_N0[6] bit 8	INT: mux SNG_N0[6] bit 5	INT: mux SNG_N0[6] bit 6	INT: mux IMUX_BYP[2] bit 8	INT: mux IMUX_BYP[2] bit 9	INT: mux IMUX_IMUX[44] bit 0	INT: mux IMUX_BYP[2] bit 0	INT: mux IMUX_IMUX[44] bit 1	INT: mux IMUX_BYP[2] bit 3	INT: mux IMUX_BYP[2] bit 7	INT: mux IMUX_BYP[2] bit 4	INT: mux IMUX_IMUX[44] bit 7	INT: mux IMUX_BYP[2] bit 5	-	INT: mux IMUX_CTRL[1] bit 7	-	-
B38	INT: mux QUAD_NE0[2] bit 4	INT: mux QUAD_NN0[2] bit 1	INT: mux QUAD_NE0[2] bit 2	INT: mux QUAD_NN0[2] bit 4	INT: mux SNG_N0[6] bit 2	INT: mux QUAD_NE0[2] bit 1	INT: mux DBL_EE0[2] bit 4	INT: mux DBL_NE0[2] bit 2	INT: mux DBL_EE0[2] bit 2	INT: mux DBL_NE0[2] bit 0	INT: mux SNG_N0[6] bit 3	INT: mux SNG_E0[1] bit 0	INT: mux SNG_E0[1] bit 3	INT: mux IMUX_BYP[2] bit 6	INT: mux IMUX_IMUX[44] bit 9	INT: mux IMUX_IMUX[44] bit 8	INT: mux IMUX_IMUX[44] bit 2	INT: mux IMUX_BYP[2] bit 2	INT: mux IMUX_IMUX[44] bit 3	INT: mux IMUX_BYP[2] bit 1	INT: mux IMUX_IMUX[44] bit 4	INT: mux IMUX_IMUX[44] bit 6	INT: mux IMUX_IMUX[44] bit 5	INT: mux IMUX_CLK[1] bit 4	INT: mux IMUX_CTRL[1] bit 4	INT: mux IMUX_CTRL[1] bit 8	-	-
B37	INT: mux QUAD_NE0[2] bit 0	INT: mux QUAD_NN0[2] bit 3	INT: mux QUAD_NE0[2] bit 3	INT: mux QUAD_NN0[2] bit 2	INT: mux DBL_NE0[2] bit 1	INT: mux SNG_N0[6] bit 4	INT: mux DBL_EE0[2] bit 3	INT: mux DBL_NE0[2] bit 4	INT: mux DBL_EE0[2] bit 1	INT: mux DBL_NE0[2] bit 3	INT: mux SNG_N0[6] bit 1	INT: mux SNG_E0[1] bit 4	INT: mux SNG_E0[1] bit 1	INT: mux SNG_E0[1] bit 2	INT: mux IMUX_IMUX[36] bit 8	INT: mux IMUX_IMUX[36] bit 9	INT: mux IMUX_IMUX[28] bit 0	INT: mux IMUX_IMUX[36] bit 0	INT: mux IMUX_IMUX[28] bit 1	INT: mux IMUX_IMUX[36] bit 3	INT: mux IMUX_IMUX[28] bit 6	INT: mux IMUX_IMUX[36] bit 5	INT: mux IMUX_IMUX[36] bit 6	INT: mux IMUX_IMUX[36] bit 4	INT: mux IMUX_CTRL[1] bit 6	INT: mux IMUX_CTRL[0] bit 4	-	-
B36	INT: mux QUAD_NN0[2] bit 5	INT: mux QUAD_NN0[2] bit 6	INT: mux QUAD_NN0[2] bit 7	INT: mux QUAD_NN0[2] bit 8	INT: mux SNG_E0[1] bit 6	INT: mux QUAD_NN0[2] bit 0	INT: mux DBL_NE0[2] bit 5	INT: mux DBL_NE0[2] bit 6	INT: mux DBL_NE0[2] bit 7	INT: mux DBL_NE0[2] bit 8	INT: mux SNG_E0[1] bit 8	INT: mux SNG_E0[1] bit 7	INT: mux SNG_E0[1] bit 5	INT: mux IMUX_IMUX[28] bit 7	INT: mux IMUX_IMUX[28] bit 9	INT: mux IMUX_IMUX[28] bit 8	INT: mux IMUX_IMUX[28] bit 2	INT: mux IMUX_IMUX[36] bit 2	INT: mux IMUX_IMUX[28] bit 3	INT: mux IMUX_IMUX[36] bit 1	INT: mux IMUX_IMUX[28] bit 4	INT: mux IMUX_IMUX[36] bit 7	INT: mux IMUX_IMUX[28] bit 5	-	INT: mux IMUX_CTRL[1] bit 3	INT: mux IMUX_CTRL[0] bit 6	-	-
B35	INT: mux QUAD_NW0[2] bit 6	INT: mux QUAD_NW0[2] bit 5	INT: mux QUAD_NW0[2] bit 8	INT: mux QUAD_NW0[2] bit 7	INT: mux DBL_NN0[2] bit 1	INT: mux SNG_W0[7] bit 1	INT: mux DBL_NN0[2] bit 6	INT: mux DBL_NN0[2] bit 5	INT: mux DBL_NN0[2] bit 8	INT: mux DBL_NN0[2] bit 7	INT: mux SNG_W0[7] bit 7	INT: mux SNG_W0[7] bit 8	INT: mux SNG_W0[7] bit 5	INT: mux SNG_W0[7] bit 6	INT: mux IMUX_IMUX[20] bit 8	INT: mux IMUX_IMUX[20] bit 9	INT: mux IMUX_IMUX[12] bit 2	INT: mux IMUX_IMUX[20] bit 2	INT: mux IMUX_IMUX[12] bit 1	INT: mux IMUX_IMUX[20] bit 3	INT: mux IMUX_IMUX[20] bit 7	INT: mux IMUX_IMUX[20] bit 4	INT: mux IMUX_IMUX[12] bit 7	INT: mux IMUX_IMUX[20] bit 5	INT: mux IMUX_CTRL[1] bit 0	INT: mux IMUX_CTRL[0] bit 3	-	-
B34	INT: mux QUAD_NW0[2] bit 4	INT: mux QUAD_WW0[2] bit 2	INT: mux QUAD_NW0[2] bit 0	INT: mux QUAD_WW0[2] bit 4	INT: mux SNG_W0[7] bit 4	INT: mux QUAD_NW0[2] bit 2	INT: mux DBL_NN0[2] bit 4	INT: mux DBL_NW0[2] bit 3	INT: mux DBL_NN0[2] bit 3	INT: mux DBL_NW0[2] bit 1	INT: mux SNG_W0[7] bit 3	INT: mux SNG_N0[1] bit 1	INT: mux SNG_N0[1] bit 3	INT: mux IMUX_IMUX[20] bit 6	INT: mux IMUX_IMUX[12] bit 9	INT: mux IMUX_IMUX[12] bit 8	INT: mux IMUX_IMUX[12] bit 0	INT: mux IMUX_IMUX[20] bit 0	INT: mux IMUX_IMUX[12] bit 3	INT: mux IMUX_IMUX[20] bit 1	INT: mux IMUX_IMUX[12] bit 4	INT: mux IMUX_IMUX[12] bit 6	INT: mux IMUX_IMUX[12] bit 5	INT: mux IMUX_CTRL[1] bit 1	INT: mux IMUX_CLK[1] bit 7	INT: mux IMUX_CTRL[0] bit 0	-	-
B33	INT: mux QUAD_NW0[2] bit 1	INT: mux QUAD_WW0[2] bit 3	INT: mux QUAD_NW0[2] bit 3	INT: mux QUAD_WW0[2] bit 0	INT: mux DBL_NW0[2] bit 0	INT: mux SNG_W0[7] bit 2	INT: mux DBL_NN0[2] bit 2	INT: mux DBL_NW0[2] bit 4	INT: mux DBL_NN0[2] bit 0	INT: mux DBL_NW0[2] bit 2	INT: mux SNG_W0[7] bit 0	INT: mux SNG_N0[1] bit 2	INT: mux SNG_N0[1] bit 0	INT: mux SNG_N0[1] bit 4	INT: mux IMUX_IMUX[4] bit 8	INT: mux IMUX_IMUX[4] bit 9	INT: mux IMUX_FAN[7] bit 2	INT: mux IMUX_IMUX[4] bit 2	INT: mux IMUX_FAN[7] bit 1	INT: mux IMUX_IMUX[4] bit 3	INT: mux IMUX_FAN[7] bit 6	INT: mux IMUX_IMUX[4] bit 5	INT: mux IMUX_IMUX[4] bit 6	INT: mux IMUX_IMUX[4] bit 4	INT: mux IMUX_CLK[0] bit 6	INT: mux IMUX_CLK[1] bit 8	-	-
B32	INT: mux QUAD_WW0[2] bit 5	INT: mux QUAD_WW0[2] bit 6	INT: mux QUAD_WW0[2] bit 7	INT: mux QUAD_WW0[2] bit 8	INT: mux SNG_N0[1] bit 6	INT: mux QUAD_WW0[2] bit 1	INT: mux DBL_NW0[2] bit 5	INT: mux DBL_NW0[2] bit 6	INT: mux DBL_NW0[2] bit 7	INT: mux DBL_NW0[2] bit 8	INT: mux SNG_N0[1] bit 8	INT: mux SNG_N0[1] bit 7	INT: mux SNG_N0[1] bit 5	INT: mux IMUX_FAN[7] bit 7	INT: mux IMUX_FAN[7] bit 9	INT: mux IMUX_FAN[7] bit 8	INT: mux IMUX_FAN[7] bit 0	INT: mux IMUX_IMUX[4] bit 0	INT: mux IMUX_FAN[7] bit 3	INT: mux IMUX_IMUX[4] bit 1	INT: mux IMUX_FAN[7] bit 5	INT: mux IMUX_IMUX[4] bit 7	INT: mux IMUX_FAN[7] bit 4	INT: mux IMUX_CLK[1] bit 3	INT: mux IMUX_CLK[0] bit 2	INT: mux IMUX_CLK[1] bit 6	-	-
B31	INT: mux QUAD_SW0[1] bit 6	INT: mux QUAD_SW0[1] bit 5	INT: mux QUAD_SW0[1] bit 8	INT: mux QUAD_SW0[1] bit 7	INT: mux DBL_WW0[1] bit 0	INT: mux SNG_S0[6] bit 0	INT: mux DBL_WW0[1] bit 6	INT: mux DBL_WW0[1] bit 5	INT: mux DBL_WW0[1] bit 8	INT: mux DBL_WW0[1] bit 7	INT: mux SNG_S0[6] bit 7	INT: mux SNG_S0[6] bit 8	INT: mux SNG_S0[6] bit 5	INT: mux SNG_S0[6] bit 6	INT: mux IMUX_BYP[5] bit 8	INT: mux IMUX_BYP[5] bit 9	INT: mux IMUX_IMUX[43] bit 1	INT: mux IMUX_BYP[5] bit 1	INT: mux IMUX_IMUX[43] bit 0	INT: mux IMUX_BYP[5] bit 3	INT: mux IMUX_BYP[5] bit 7	INT: mux IMUX_BYP[5] bit 4	INT: mux IMUX_IMUX[43] bit 7	INT: mux IMUX_BYP[5] bit 5	INT: mux IMUX_CLK[0] bit 1	INT: mux IMUX_CLK[1] bit 2	-	-
B30	INT: mux QUAD_SW0[1] bit 4	INT: mux QUAD_SS0[1] bit 0	INT: mux QUAD_SW0[1] bit 2	INT: mux QUAD_SS0[1] bit 4	INT: mux SNG_S0[6] bit 2	INT: mux QUAD_SW0[1] bit 0	INT: mux DBL_WW0[1] bit 4	INT: mux DBL_SW0[1] bit 2	INT: mux DBL_WW0[1] bit 2	INT: mux DBL_SW0[1] bit 0	INT: mux SNG_S0[6] bit 4	INT: mux SNG_W0[0] bit 0	INT: mux SNG_W0[0] bit 4	INT: mux IMUX_BYP[5] bit 6	INT: mux IMUX_IMUX[43] bit 9	INT: mux IMUX_IMUX[43] bit 8	INT: mux IMUX_IMUX[43] bit 2	INT: mux IMUX_BYP[5] bit 2	INT: mux IMUX_IMUX[43] bit 3	INT: mux IMUX_BYP[5] bit 0	INT: mux IMUX_IMUX[43] bit 4	INT: mux IMUX_IMUX[43] bit 6	INT: mux IMUX_IMUX[43] bit 5	INT: mux IMUX_CLK[0] bit 5	INT: mux IMUX_CLK[0] bit 8	INT: mux IMUX_CLK[1] bit 1	-	-
B29	INT: mux QUAD_SW0[1] bit 1	INT: mux QUAD_SS0[1] bit 3	INT: mux QUAD_SW0[1] bit 3	INT: mux QUAD_SS0[1] bit 2	INT: mux DBL_SW0[1] bit 1	INT: mux SNG_W0[0] bit 2	INT: mux DBL_WW0[1] bit 3	INT: mux DBL_SW0[1] bit 4	INT: mux DBL_WW0[1] bit 1	INT: mux DBL_SW0[1] bit 3	INT: mux SNG_S0[6] bit 1	INT: mux SNG_W0[0] bit 3	INT: mux SNG_W0[0] bit 1	INT: mux SNG_S0[6] bit 3	INT: mux IMUX_IMUX[35] bit 8	INT: mux IMUX_IMUX[35] bit 9	INT: mux IMUX_IMUX[27] bit 1	INT: mux IMUX_IMUX[35] bit 1	INT: mux IMUX_IMUX[27] bit 0	INT: mux IMUX_IMUX[35] bit 3	INT: mux IMUX_IMUX[27] bit 6	INT: mux IMUX_IMUX[35] bit 5	INT: mux IMUX_IMUX[35] bit 6	INT: mux IMUX_IMUX[35] bit 4	INT: mux IMUX_GFAN[1] bit 5	INT: mux IMUX_CLK[0] bit 7	-	-
B28	INT: mux QUAD_SS0[1] bit 5	INT: mux QUAD_SS0[1] bit 6	INT: mux QUAD_SS0[1] bit 7	INT: mux QUAD_SS0[1] bit 8	INT: mux SNG_W0[0] bit 6	INT: mux QUAD_SS0[1] bit 1	INT: mux DBL_SW0[1] bit 5	INT: mux DBL_SW0[1] bit 6	INT: mux DBL_SW0[1] bit 7	INT: mux DBL_SW0[1] bit 8	INT: mux SNG_W0[0] bit 8	INT: mux SNG_W0[0] bit 7	INT: mux SNG_W0[0] bit 5	INT: mux IMUX_IMUX[27] bit 7	INT: mux IMUX_IMUX[27] bit 9	INT: mux IMUX_IMUX[27] bit 8	INT: mux IMUX_IMUX[27] bit 2	INT: mux IMUX_IMUX[35] bit 2	INT: mux IMUX_IMUX[27] bit 3	INT: mux IMUX_IMUX[35] bit 0	INT: mux IMUX_IMUX[27] bit 4	INT: mux IMUX_IMUX[35] bit 7	INT: mux IMUX_IMUX[27] bit 5	INT: mux IMUX_GFAN[0] bit 3	INT: mux IMUX_GFAN[1] bit 2	INT: mux IMUX_GFAN[0] bit 5	-	-
B27	INT: mux QUAD_SE0[1] bit 6	INT: mux QUAD_SE0[1] bit 5	INT: mux QUAD_SE0[1] bit 8	INT: mux QUAD_SE0[1] bit 7	INT: mux DBL_SS0[1] bit 1	INT: mux SNG_E0[6] bit 1	INT: mux DBL_SS0[1] bit 6	INT: mux DBL_SS0[1] bit 5	INT: mux DBL_SS0[1] bit 8	INT: mux DBL_SS0[1] bit 7	INT: mux SNG_E0[6] bit 7	INT: mux SNG_E0[6] bit 8	INT: mux SNG_E0[6] bit 5	INT: mux SNG_E0[6] bit 6	INT: mux IMUX_IMUX[19] bit 8	INT: mux IMUX_IMUX[19] bit 9	INT: mux IMUX_IMUX[11] bit 2	INT: mux IMUX_IMUX[19] bit 2	INT: mux IMUX_IMUX[11] bit 0	INT: mux IMUX_IMUX[19] bit 3	INT: mux IMUX_IMUX[19] bit 7	INT: mux IMUX_IMUX[19] bit 4	INT: mux IMUX_IMUX[11] bit 7	INT: mux IMUX_IMUX[19] bit 5	INT: mux IMUX_GFAN[1] bit 1	INT: mux IMUX_GFAN[0] bit 2	-	-
B26	INT: mux QUAD_SE0[1] bit 4	INT: mux QUAD_EE0[1] bit 1	INT: mux QUAD_SE0[1] bit 0	INT: mux QUAD_EE0[1] bit 4	INT: mux SNG_E0[6] bit 4	INT: mux QUAD_SE0[1] bit 1	INT: mux DBL_SS0[1] bit 4	INT: mux DBL_SE0[1] bit 3	INT: mux DBL_SS0[1] bit 3	INT: mux DBL_SE0[1] bit 1	INT: mux SNG_E0[6] bit 2	INT: mux SNG_S0[1] bit 1	INT: mux SNG_S0[1] bit 2	INT: mux IMUX_IMUX[19] bit 6	INT: mux IMUX_IMUX[11] bit 9	INT: mux IMUX_IMUX[11] bit 8	INT: mux IMUX_IMUX[11] bit 1	INT: mux IMUX_IMUX[19] bit 1	INT: mux IMUX_IMUX[11] bit 3	INT: mux IMUX_IMUX[19] bit 0	INT: mux IMUX_IMUX[11] bit 4	INT: mux IMUX_IMUX[11] bit 6	INT: mux IMUX_IMUX[11] bit 5	INT: mux IMUX_GFAN[0] bit 6	INT: mux IMUX_GFAN[1] bit 0	INT: mux IMUX_GFAN[0] bit 1	-	-
B25	INT: mux QUAD_SE0[1] bit 2	INT: mux QUAD_EE0[1] bit 3	INT: mux QUAD_SE0[1] bit 3	INT: mux QUAD_EE0[1] bit 0	INT: mux DBL_SE0[1] bit 0	INT: mux SNG_S0[1] bit 4	INT: mux DBL_SS0[1] bit 2	INT: mux DBL_SE0[1] bit 4	INT: mux DBL_SS0[1] bit 0	INT: mux DBL_SE0[1] bit 2	INT: mux SNG_E0[6] bit 0	INT: mux SNG_S0[1] bit 3	INT: mux SNG_S0[1] bit 0	INT: mux SNG_E0[6] bit 3	INT: mux IMUX_IMUX[3] bit 8	INT: mux IMUX_IMUX[3] bit 9	INT: mux IMUX_FAN[6] bit 2	INT: mux IMUX_IMUX[3] bit 2	INT: mux IMUX_FAN[6] bit 0	INT: mux IMUX_IMUX[3] bit 3	INT: mux IMUX_FAN[6] bit 6	INT: mux IMUX_IMUX[3] bit 5	INT: mux IMUX_IMUX[3] bit 6	INT: mux IMUX_IMUX[3] bit 4	INT: mux IMUX_GFAN[0] bit 8	INT: mux IMUX_GFAN[0] bit 0	-	-
B24	INT: mux QUAD_EE0[1] bit 5	INT: mux QUAD_EE0[1] bit 6	INT: mux QUAD_EE0[1] bit 7	INT: mux QUAD_EE0[1] bit 8	INT: mux SNG_S0[1] bit 6	INT: mux QUAD_EE0[1] bit 2	INT: mux DBL_SE0[1] bit 5	INT: mux DBL_SE0[1] bit 6	INT: mux DBL_SE0[1] bit 7	INT: mux DBL_SE0[1] bit 8	INT: mux SNG_S0[1] bit 8	INT: mux SNG_S0[1] bit 7	INT: mux SNG_S0[1] bit 5	INT: mux IMUX_FAN[6] bit 7	INT: mux IMUX_FAN[6] bit 9	INT: mux IMUX_FAN[6] bit 8	INT: mux IMUX_FAN[6] bit 1	INT: mux IMUX_IMUX[3] bit 1	INT: mux IMUX_FAN[6] bit 3	INT: mux IMUX_IMUX[3] bit 0	INT: mux IMUX_FAN[6] bit 5	INT: mux IMUX_IMUX[3] bit 7	INT: mux IMUX_FAN[6] bit 4	INT: mux IMUX_CLK[1] bit 5	INT: mux IMUX_GFAN[0] bit 7	-	-	-
B23	INT: mux QUAD_NE0[1] bit 6	INT: mux QUAD_NE0[1] bit 5	INT: mux QUAD_NE0[1] bit 8	INT: mux QUAD_NE0[1] bit 7	INT: mux DBL_EE0[1] bit 0	INT: mux SNG_N0[5] bit 0	INT: mux DBL_EE0[1] bit 6	INT: mux DBL_EE0[1] bit 5	INT: mux DBL_EE0[1] bit 8	INT: mux DBL_EE0[1] bit 7	INT: mux SNG_N0[5] bit 7	INT: mux SNG_N0[5] bit 8	INT: mux SNG_N0[5] bit 5	INT: mux SNG_N0[5] bit 6	INT: mux IMUX_BYP[4] bit 8	INT: mux IMUX_BYP[4] bit 9	INT: mux IMUX_IMUX[42] bit 0	INT: mux IMUX_BYP[4] bit 0	INT: mux IMUX_IMUX[42] bit 1	INT: mux IMUX_BYP[4] bit 3	INT: mux IMUX_BYP[4] bit 7	INT: mux IMUX_BYP[4] bit 4	INT: mux IMUX_IMUX[42] bit 7	INT: mux IMUX_BYP[4] bit 5	-	-	-	-
B22	INT: mux QUAD_NE0[1] bit 4	INT: mux QUAD_NN0[1] bit 1	INT: mux QUAD_NE0[1] bit 2	INT: mux QUAD_NN0[1] bit 4	INT: mux SNG_N0[5] bit 2	INT: mux QUAD_NE0[1] bit 1	INT: mux DBL_EE0[1] bit 4	INT: mux DBL_NE0[1] bit 2	INT: mux DBL_EE0[1] bit 2	INT: mux DBL_NE0[1] bit 0	INT: mux SNG_N0[5] bit 3	INT: mux SNG_E0[0] bit 0	INT: mux SNG_E0[0] bit 3	INT: mux IMUX_BYP[4] bit 6	INT: mux IMUX_IMUX[42] bit 9	INT: mux IMUX_IMUX[42] bit 8	INT: mux IMUX_IMUX[42] bit 3	INT: mux IMUX_BYP[4] bit 2	INT: mux IMUX_IMUX[42] bit 2	INT: mux IMUX_BYP[4] bit 1	INT: mux IMUX_IMUX[42] bit 4	INT: mux IMUX_IMUX[42] bit 6	INT: mux IMUX_IMUX[42] bit 5	INT: mux IMUX_CLK[0] bit 0	INT: mux IMUX_GFAN[1] bit 7	-	-	-
B21	INT: mux QUAD_NE0[1] bit 0	INT: mux QUAD_NN0[1] bit 3	INT: mux QUAD_NE0[1] bit 3	INT: mux QUAD_NN0[1] bit 2	INT: mux DBL_NE0[1] bit 1	INT: mux SNG_N0[5] bit 4	INT: mux DBL_EE0[1] bit 3	INT: mux DBL_NE0[1] bit 4	INT: mux DBL_EE0[1] bit 1	INT: mux DBL_NE0[1] bit 3	INT: mux SNG_N0[5] bit 1	INT: mux SNG_E0[0] bit 4	INT: mux SNG_E0[0] bit 1	INT: mux SNG_E0[0] bit 2	INT: mux IMUX_IMUX[34] bit 8	INT: mux IMUX_IMUX[34] bit 9	INT: mux IMUX_IMUX[26] bit 0	INT: mux IMUX_IMUX[34] bit 0	INT: mux IMUX_IMUX[26] bit 1	INT: mux IMUX_IMUX[34] bit 2	INT: mux IMUX_IMUX[26] bit 6	INT: mux IMUX_IMUX[34] bit 5	INT: mux IMUX_IMUX[34] bit 6	INT: mux IMUX_IMUX[34] bit 4	-	INT: mux IMUX_GFAN[1] bit 8	-	-
B20	INT: mux QUAD_NN0[1] bit 5	INT: mux QUAD_NN0[1] bit 6	INT: mux QUAD_NN0[1] bit 7	INT: mux QUAD_NN0[1] bit 8	INT: mux SNG_E0[0] bit 6	INT: mux QUAD_NN0[1] bit 0	INT: mux DBL_NE0[1] bit 5	INT: mux DBL_NE0[1] bit 6	INT: mux DBL_NE0[1] bit 7	INT: mux DBL_NE0[1] bit 8	INT: mux SNG_E0[0] bit 8	INT: mux SNG_E0[0] bit 7	INT: mux SNG_E0[0] bit 5	INT: mux IMUX_IMUX[26] bit 7	INT: mux IMUX_IMUX[26] bit 9	INT: mux IMUX_IMUX[26] bit 8	INT: mux IMUX_IMUX[26] bit 3	INT: mux IMUX_IMUX[34] bit 3	INT: mux IMUX_IMUX[26] bit 2	INT: mux IMUX_IMUX[34] bit 1	INT: mux IMUX_IMUX[26] bit 4	INT: mux IMUX_IMUX[34] bit 7	INT: mux IMUX_IMUX[26] bit 5	INT: mux LV[16] bit 5	INT: mux IMUX_GFAN[1] bit 6	INT: mux IMUX_CLK[1] bit 0	-	-
B19	INT: mux QUAD_NW0[1] bit 6	INT: mux QUAD_NW0[1] bit 5	INT: mux QUAD_NW0[1] bit 8	INT: mux QUAD_NW0[1] bit 7	INT: mux DBL_NN0[1] bit 1	INT: mux SNG_W0[6] bit 1	INT: mux DBL_NN0[1] bit 6	INT: mux DBL_NN0[1] bit 5	INT: mux DBL_NN0[1] bit 8	INT: mux DBL_NN0[1] bit 7	INT: mux SNG_W0[6] bit 7	INT: mux SNG_W0[6] bit 8	INT: mux SNG_W0[6] bit 5	INT: mux SNG_W0[6] bit 6	INT: mux IMUX_IMUX[18] bit 8	INT: mux IMUX_IMUX[18] bit 9	INT: mux IMUX_IMUX[10] bit 3	INT: mux IMUX_IMUX[18] bit 3	INT: mux IMUX_IMUX[10] bit 1	INT: mux IMUX_IMUX[18] bit 2	INT: mux IMUX_IMUX[18] bit 7	INT: mux IMUX_IMUX[18] bit 4	INT: mux IMUX_IMUX[10] bit 7	INT: mux IMUX_IMUX[18] bit 5	-	-	-	-
B18	INT: mux QUAD_NW0[1] bit 4	INT: mux QUAD_WW0[1] bit 2	INT: mux QUAD_NW0[1] bit 0	INT: mux QUAD_WW0[1] bit 4	INT: mux SNG_W0[6] bit 4	INT: mux QUAD_NW0[1] bit 2	INT: mux DBL_NN0[1] bit 4	INT: mux DBL_NW0[1] bit 3	INT: mux DBL_NN0[1] bit 3	INT: mux DBL_NW0[1] bit 1	INT: mux SNG_W0[6] bit 3	INT: mux SNG_N0[0] bit 1	INT: mux SNG_N0[0] bit 3	INT: mux IMUX_IMUX[18] bit 6	INT: mux IMUX_IMUX[10] bit 9	INT: mux IMUX_IMUX[10] bit 8	INT: mux IMUX_IMUX[10] bit 0	INT: mux IMUX_IMUX[18] bit 0	INT: mux IMUX_IMUX[10] bit 2	INT: mux IMUX_IMUX[18] bit 1	INT: mux IMUX_IMUX[10] bit 4	INT: mux IMUX_IMUX[10] bit 6	INT: mux IMUX_IMUX[10] bit 5	INT: mux LV[16] bit 3	-	-	-	-
B17	INT: mux QUAD_NW0[1] bit 1	INT: mux QUAD_WW0[1] bit 3	INT: mux QUAD_NW0[1] bit 3	INT: mux QUAD_WW0[1] bit 0	INT: mux DBL_NW0[1] bit 0	INT: mux SNG_W0[6] bit 2	INT: mux DBL_NN0[1] bit 2	INT: mux DBL_NW0[1] bit 4	INT: mux DBL_NN0[1] bit 0	INT: mux DBL_NW0[1] bit 2	INT: mux SNG_W0[6] bit 0	INT: mux SNG_N0[0] bit 2	INT: mux SNG_N0[0] bit 0	INT: mux SNG_N0[0] bit 4	INT: mux IMUX_IMUX[2] bit 8	INT: mux IMUX_IMUX[2] bit 9	INT: mux IMUX_FAN[2] bit 3	INT: mux IMUX_IMUX[2] bit 3	INT: mux IMUX_FAN[2] bit 1	INT: mux IMUX_IMUX[2] bit 2	INT: mux IMUX_FAN[2] bit 6	INT: mux IMUX_IMUX[2] bit 5	INT: mux IMUX_IMUX[2] bit 6	INT: mux IMUX_IMUX[2] bit 4	INT: mux IMUX_GFAN[1] bit 4	-	-	-
B16	INT: mux QUAD_WW0[1] bit 5	INT: mux QUAD_WW0[1] bit 6	INT: mux QUAD_WW0[1] bit 7	INT: mux QUAD_WW0[1] bit 8	INT: mux SNG_N0[0] bit 6	INT: mux QUAD_WW0[1] bit 1	INT: mux DBL_NW0[1] bit 5	INT: mux DBL_NW0[1] bit 6	INT: mux DBL_NW0[1] bit 7	INT: mux DBL_NW0[1] bit 8	INT: mux SNG_N0[0] bit 8	INT: mux SNG_N0[0] bit 7	INT: mux SNG_N0[0] bit 5	INT: mux IMUX_FAN[2] bit 7	INT: mux IMUX_FAN[2] bit 9	INT: mux IMUX_FAN[2] bit 8	INT: mux IMUX_FAN[2] bit 0	INT: mux IMUX_IMUX[2] bit 0	INT: mux IMUX_FAN[2] bit 2	INT: mux IMUX_IMUX[2] bit 1	INT: mux IMUX_FAN[2] bit 5	INT: mux IMUX_IMUX[2] bit 7	INT: mux IMUX_FAN[2] bit 4	INT: mux LV[0] bit 0	-	-	-	-
B15	INT: mux QUAD_SW0[0] bit 6	INT: mux QUAD_SW0[0] bit 5	INT: mux QUAD_SW0[0] bit 8	INT: mux QUAD_SW0[0] bit 7	INT: mux DBL_WW0[0] bit 0	INT: mux SNG_S0[5] bit 0	INT: mux DBL_WW0[0] bit 6	INT: mux DBL_WW0[0] bit 5	INT: mux DBL_WW0[0] bit 8	INT: mux DBL_WW0[0] bit 7	INT: mux SNG_S0[5] bit 7	INT: mux SNG_S0[5] bit 8	INT: mux SNG_S0[5] bit 5	INT: mux SNG_S0[5] bit 6	INT: mux IMUX_BYP[1] bit 8	INT: mux IMUX_BYP[1] bit 9	INT: mux IMUX_IMUX[41] bit 1	INT: mux IMUX_BYP[1] bit 1	INT: mux IMUX_IMUX[41] bit 0	INT: mux IMUX_BYP[1] bit 2	INT: mux IMUX_BYP[1] bit 7	INT: mux IMUX_BYP[1] bit 4	INT: mux IMUX_IMUX[41] bit 7	INT: mux IMUX_BYP[1] bit 5	INT: mux IMUX_GFAN[1] bit 3	INT: mux IMUX_GFAN[0] bit 4	-	-
B14	INT: mux QUAD_SW0[0] bit 4	INT: mux QUAD_SS0[0] bit 0	INT: mux QUAD_SW0[0] bit 2	INT: mux QUAD_SS0[0] bit 4	INT: mux SNG_S0[5] bit 2	INT: mux QUAD_SW0[0] bit 0	INT: mux DBL_WW0[0] bit 4	INT: mux DBL_SW0[0] bit 2	INT: mux DBL_WW0[0] bit 2	INT: mux DBL_SW0[0] bit 0	INT: mux SNG_S0[5] bit 4	INT: mux SNG_W0_N3 bit 0	INT: mux SNG_W0_N3 bit 4	INT: mux IMUX_BYP[1] bit 6	INT: mux IMUX_IMUX[41] bit 9	INT: mux IMUX_IMUX[41] bit 8	INT: mux IMUX_IMUX[41] bit 3	INT: mux IMUX_BYP[1] bit 3	INT: mux IMUX_IMUX[41] bit 2	INT: mux IMUX_BYP[1] bit 0	INT: mux IMUX_IMUX[41] bit 4	INT: mux IMUX_IMUX[41] bit 6	INT: mux IMUX_IMUX[41] bit 5	INT: mux LV[0] bit 2	INT: mux LV[0] bit 7	-	-	-
B13	INT: mux QUAD_SW0[0] bit 1	INT: mux QUAD_SS0[0] bit 3	INT: mux QUAD_SW0[0] bit 3	INT: mux QUAD_SS0[0] bit 2	INT: mux DBL_SW0[0] bit 1	INT: mux SNG_W0_N3 bit 2	INT: mux DBL_WW0[0] bit 3	INT: mux DBL_SW0[0] bit 4	INT: mux DBL_WW0[0] bit 1	INT: mux DBL_SW0[0] bit 3	INT: mux SNG_S0[5] bit 1	INT: mux SNG_W0_N3 bit 3	INT: mux SNG_W0_N3 bit 1	INT: mux SNG_S0[5] bit 3	INT: mux IMUX_IMUX[33] bit 8	INT: mux IMUX_IMUX[33] bit 9	INT: mux IMUX_IMUX[25] bit 1	INT: mux IMUX_IMUX[33] bit 1	INT: mux IMUX_IMUX[25] bit 0	INT: mux IMUX_IMUX[33] bit 2	INT: mux IMUX_IMUX[25] bit 6	INT: mux IMUX_IMUX[33] bit 5	INT: mux IMUX_IMUX[33] bit 6	INT: mux IMUX_IMUX[33] bit 4	INT: mux LV[0] bit 5	INT: mux LV[0] bit 3	-	-
B12	INT: mux QUAD_SS0[0] bit 5	INT: mux QUAD_SS0[0] bit 6	INT: mux QUAD_SS0[0] bit 7	INT: mux QUAD_SS0[0] bit 8	INT: mux SNG_W0_N3 bit 6	INT: mux QUAD_SS0[0] bit 1	INT: mux DBL_SW0[0] bit 5	INT: mux DBL_SW0[0] bit 6	INT: mux DBL_SW0[0] bit 7	INT: mux DBL_SW0[0] bit 8	INT: mux SNG_W0_N3 bit 8	INT: mux SNG_W0_N3 bit 7	INT: mux SNG_W0_N3 bit 5	INT: mux IMUX_IMUX[25] bit 7	INT: mux IMUX_IMUX[25] bit 9	INT: mux IMUX_IMUX[25] bit 8	INT: mux IMUX_IMUX[25] bit 3	INT: mux IMUX_IMUX[33] bit 3	INT: mux IMUX_IMUX[25] bit 2	INT: mux IMUX_IMUX[33] bit 0	INT: mux IMUX_IMUX[25] bit 4	INT: mux IMUX_IMUX[33] bit 7	INT: mux IMUX_IMUX[25] bit 5	INT: mux LV[16] bit 6	INT: mux LV[0] bit 1	INT: mux LV[0] bit 6	-	-
B11	INT: mux QUAD_SE0[0] bit 6	INT: mux QUAD_SE0[0] bit 5	INT: mux QUAD_SE0[0] bit 8	INT: mux QUAD_SE0[0] bit 7	INT: mux DBL_SS0[0] bit 1	INT: mux SNG_E0[5] bit 1	INT: mux DBL_SS0[0] bit 6	INT: mux DBL_SS0[0] bit 5	INT: mux DBL_SS0[0] bit 8	INT: mux DBL_SS0[0] bit 7	INT: mux SNG_E0[5] bit 7	INT: mux SNG_E0[5] bit 8	INT: mux SNG_E0[5] bit 5	INT: mux SNG_E0[5] bit 6	INT: mux IMUX_IMUX[17] bit 8	INT: mux IMUX_IMUX[17] bit 9	INT: mux IMUX_IMUX[9] bit 3	INT: mux IMUX_IMUX[17] bit 3	INT: mux IMUX_IMUX[9] bit 0	INT: mux IMUX_IMUX[17] bit 2	INT: mux IMUX_IMUX[17] bit 7	INT: mux IMUX_IMUX[17] bit 4	INT: mux IMUX_IMUX[9] bit 7	INT: mux IMUX_IMUX[17] bit 5	INT: mux LV[16] bit 7	INT: mux LV[0] bit 4	-	-
B10	INT: mux QUAD_SE0[0] bit 4	INT: mux QUAD_EE0[0] bit 1	INT: mux QUAD_SE0[0] bit 0	INT: mux QUAD_EE0[0] bit 4	INT: mux SNG_E0[5] bit 4	INT: mux QUAD_SE0[0] bit 1	INT: mux DBL_SS0[0] bit 4	INT: mux DBL_SE0[0] bit 3	INT: mux DBL_SS0[0] bit 3	INT: mux DBL_SE0[0] bit 1	INT: mux SNG_E0[5] bit 2	INT: mux SNG_S0[0] bit 1	INT: mux SNG_S0[0] bit 2	INT: mux IMUX_IMUX[17] bit 6	INT: mux IMUX_IMUX[9] bit 9	INT: mux IMUX_IMUX[9] bit 8	INT: mux IMUX_IMUX[9] bit 1	INT: mux IMUX_IMUX[17] bit 1	INT: mux IMUX_IMUX[9] bit 2	INT: mux IMUX_IMUX[17] bit 0	INT: mux IMUX_IMUX[9] bit 4	INT: mux IMUX_IMUX[9] bit 6	INT: mux IMUX_IMUX[9] bit 5	-	-	INT: mux LV[16] bit 2	-	-
B9	INT: mux QUAD_SE0[0] bit 2	INT: mux QUAD_EE0[0] bit 3	INT: mux QUAD_SE0[0] bit 3	INT: mux QUAD_EE0[0] bit 0	INT: mux DBL_SE0[0] bit 0	INT: mux SNG_S0[0] bit 4	INT: mux DBL_SS0[0] bit 2	INT: mux DBL_SE0[0] bit 4	INT: mux DBL_SS0[0] bit 0	INT: mux DBL_SE0[0] bit 2	INT: mux SNG_E0[5] bit 0	INT: mux SNG_S0[0] bit 3	INT: mux SNG_S0[0] bit 0	INT: mux SNG_E0[5] bit 3	INT: mux IMUX_IMUX[1] bit 8	INT: mux IMUX_IMUX[1] bit 9	INT: mux IMUX_FAN[4] bit 3	INT: mux IMUX_IMUX[1] bit 3	INT: mux IMUX_FAN[4] bit 0	INT: mux IMUX_IMUX[1] bit 2	INT: mux IMUX_FAN[4] bit 6	INT: mux IMUX_IMUX[1] bit 5	INT: mux IMUX_IMUX[1] bit 6	INT: mux IMUX_IMUX[1] bit 4	-	-	-	-
B8	INT: mux QUAD_EE0[0] bit 5	INT: mux QUAD_EE0[0] bit 6	INT: mux QUAD_EE0[0] bit 7	INT: mux QUAD_EE0[0] bit 8	INT: mux SNG_S0[0] bit 6	INT: mux QUAD_EE0[0] bit 2	INT: mux DBL_SE0[0] bit 5	INT: mux DBL_SE0[0] bit 6	INT: mux DBL_SE0[0] bit 7	INT: mux DBL_SE0[0] bit 8	INT: mux SNG_S0[0] bit 8	INT: mux SNG_S0[0] bit 7	INT: mux SNG_S0[0] bit 5	INT: mux IMUX_FAN[4] bit 7	INT: mux IMUX_FAN[4] bit 9	INT: mux IMUX_FAN[4] bit 8	INT: mux IMUX_FAN[4] bit 1	INT: mux IMUX_IMUX[1] bit 1	INT: mux IMUX_FAN[4] bit 2	INT: mux IMUX_IMUX[1] bit 0	INT: mux IMUX_FAN[4] bit 5	INT: mux IMUX_IMUX[1] bit 7	INT: mux IMUX_FAN[4] bit 4	INT: mux LV[16] bit 0	-	-	-	-
B7	INT: mux QUAD_NE0[0] bit 6	INT: mux QUAD_NE0[0] bit 5	INT: mux QUAD_NE0[0] bit 8	INT: mux QUAD_NE0[0] bit 7	INT: mux DBL_EE0[0] bit 0	INT: mux SNG_N0[4] bit 0	INT: mux DBL_EE0[0] bit 6	INT: mux DBL_EE0[0] bit 5	INT: mux DBL_EE0[0] bit 8	INT: mux DBL_EE0[0] bit 7	INT: mux SNG_N0[4] bit 7	INT: mux SNG_N0[4] bit 8	INT: mux SNG_N0[4] bit 5	INT: mux SNG_N0[4] bit 6	INT: mux IMUX_BYP[0] bit 8	INT: mux IMUX_BYP[0] bit 9	INT: mux IMUX_IMUX[40] bit 0	INT: mux IMUX_BYP[0] bit 0	INT: mux IMUX_IMUX[40] bit 1	INT: mux IMUX_BYP[0] bit 2	INT: mux IMUX_BYP[0] bit 7	INT: mux IMUX_BYP[0] bit 4	INT: mux IMUX_IMUX[40] bit 7	INT: mux IMUX_BYP[0] bit 5	-	-	-	-
B6	INT: mux QUAD_NE0[0] bit 4	INT: mux QUAD_NN0[0] bit 1	INT: mux QUAD_NE0[0] bit 2	INT: mux QUAD_NN0[0] bit 4	INT: mux SNG_N0[4] bit 2	INT: mux QUAD_NE0[0] bit 1	INT: mux DBL_EE0[0] bit 4	INT: mux DBL_NE0[0] bit 2	INT: mux DBL_EE0[0] bit 2	INT: mux DBL_NE0[0] bit 0	INT: mux SNG_N0[4] bit 3	INT: mux SNG_E0_N3 bit 0	INT: mux SNG_E0_N3 bit 3	INT: mux IMUX_BYP[0] bit 6	INT: mux IMUX_IMUX[40] bit 9	INT: mux IMUX_IMUX[40] bit 8	INT: mux IMUX_IMUX[40] bit 2	INT: mux IMUX_BYP[0] bit 3	INT: mux IMUX_IMUX[40] bit 3	INT: mux IMUX_BYP[0] bit 1	INT: mux IMUX_IMUX[40] bit 4	INT: mux IMUX_IMUX[40] bit 6	INT: mux IMUX_IMUX[40] bit 5	INT: mux LV[16] bit 4	-	-	-	-
B5	INT: mux QUAD_NE0[0] bit 0	INT: mux QUAD_NN0[0] bit 3	INT: mux QUAD_NE0[0] bit 3	INT: mux QUAD_NN0[0] bit 2	INT: mux DBL_NE0[0] bit 1	INT: mux SNG_N0[4] bit 4	INT: mux DBL_EE0[0] bit 3	INT: mux DBL_NE0[0] bit 4	INT: mux DBL_EE0[0] bit 1	INT: mux DBL_NE0[0] bit 3	INT: mux SNG_N0[4] bit 1	INT: mux SNG_E0_N3 bit 4	INT: mux SNG_E0_N3 bit 1	INT: mux SNG_E0_N3 bit 2	INT: mux IMUX_IMUX[32] bit 8	INT: mux IMUX_IMUX[32] bit 9	INT: mux IMUX_IMUX[24] bit 0	INT: mux IMUX_IMUX[32] bit 0	INT: mux IMUX_IMUX[24] bit 1	INT: mux IMUX_IMUX[32] bit 3	INT: mux IMUX_IMUX[24] bit 6	INT: mux IMUX_IMUX[32] bit 5	INT: mux IMUX_IMUX[32] bit 6	INT: mux IMUX_IMUX[32] bit 4	-	-	-	-
B4	INT: mux QUAD_NN0[0] bit 5	INT: mux QUAD_NN0[0] bit 6	INT: mux QUAD_NN0[0] bit 7	INT: mux QUAD_NN0[0] bit 8	INT: mux SNG_E0_N3 bit 6	INT: mux QUAD_NN0[0] bit 0	INT: mux DBL_NE0[0] bit 5	INT: mux DBL_NE0[0] bit 6	INT: mux DBL_NE0[0] bit 7	INT: mux DBL_NE0[0] bit 8	INT: mux SNG_E0_N3 bit 8	INT: mux SNG_E0_N3 bit 7	INT: mux SNG_E0_N3 bit 5	INT: mux IMUX_IMUX[24] bit 7	INT: mux IMUX_IMUX[24] bit 9	INT: mux IMUX_IMUX[24] bit 8	INT: mux IMUX_IMUX[24] bit 2	INT: mux IMUX_IMUX[32] bit 2	INT: mux IMUX_IMUX[24] bit 3	INT: mux IMUX_IMUX[32] bit 1	INT: mux IMUX_IMUX[24] bit 4	INT: mux IMUX_IMUX[32] bit 7	INT: mux IMUX_IMUX[24] bit 5	INT: mux LV[16] bit 1	-	-	-	-
B3	INT: mux QUAD_NW0[0] bit 6	INT: mux QUAD_NW0[0] bit 5	INT: mux QUAD_NW0[0] bit 8	INT: mux QUAD_NW0[0] bit 7	INT: mux DBL_NN0[0] bit 1	INT: mux SNG_W0[5] bit 1	INT: mux DBL_NN0[0] bit 5	INT: mux DBL_NN0[0] bit 6	INT: mux DBL_NN0[0] bit 8	INT: mux DBL_NN0[0] bit 7	INT: mux SNG_W0[5] bit 7	INT: mux SNG_W0[5] bit 8	INT: mux SNG_W0[5] bit 6	INT: mux SNG_W0[5] bit 5	INT: mux IMUX_IMUX[16] bit 8	INT: mux IMUX_IMUX[16] bit 9	INT: mux IMUX_IMUX[8] bit 2	INT: mux IMUX_IMUX[16] bit 2	INT: mux IMUX_IMUX[8] bit 0	INT: mux IMUX_IMUX[16] bit 3	INT: mux IMUX_IMUX[16] bit 6	INT: mux IMUX_IMUX[16] bit 4	INT: mux IMUX_IMUX[8] bit 6	INT: mux IMUX_IMUX[16] bit 5	-	-	-	-
B2	INT: mux QUAD_NW0[0] bit 4	INT: mux QUAD_WW0[0] bit 2	INT: mux QUAD_NW0[0] bit 0	INT: mux QUAD_WW0[0] bit 4	INT: mux SNG_W0[5] bit 4	INT: mux QUAD_NW0[0] bit 2	INT: mux DBL_NN0[0] bit 4	INT: mux DBL_NW0[0] bit 3	INT: mux DBL_NN0[0] bit 3	INT: mux DBL_NW0[0] bit 1	INT: mux SNG_W0[5] bit 3	INT: mux SNG_N0_N3 bit 1	INT: mux SNG_N0_N3 bit 3	INT: mux IMUX_IMUX[16] bit 7	INT: mux IMUX_IMUX[8] bit 9	INT: mux IMUX_IMUX[8] bit 8	INT: mux IMUX_IMUX[8] bit 1	INT: mux IMUX_IMUX[16] bit 1	INT: mux IMUX_IMUX[8] bit 3	INT: mux IMUX_IMUX[16] bit 0	INT: mux IMUX_IMUX[8] bit 4	INT: mux IMUX_IMUX[8] bit 7	INT: mux IMUX_IMUX[8] bit 5	-	-	-	-	-
B1	INT: mux QUAD_NW0[0] bit 1	INT: mux QUAD_WW0[0] bit 3	INT: mux QUAD_NW0[0] bit 3	INT: mux QUAD_WW0[0] bit 0	INT: mux DBL_NW0[0] bit 0	INT: mux SNG_W0[5] bit 2	INT: mux DBL_NN0[0] bit 2	INT: mux DBL_NW0[0] bit 4	INT: mux DBL_NN0[0] bit 0	INT: mux DBL_NW0[0] bit 2	INT: mux SNG_W0[5] bit 0	INT: mux SNG_N0_N3 bit 2	INT: mux SNG_N0_N3 bit 0	INT: mux SNG_N0_N3 bit 4	INT: mux IMUX_IMUX[0] bit 8	INT: mux IMUX_IMUX[0] bit 9	INT: mux IMUX_FAN[0] bit 2	INT: mux IMUX_IMUX[0] bit 2	INT: mux IMUX_FAN[0] bit 0	INT: mux IMUX_IMUX[0] bit 3	INT: mux IMUX_FAN[0] bit 7	INT: mux IMUX_IMUX[0] bit 5	INT: mux IMUX_IMUX[0] bit 7	INT: mux IMUX_IMUX[0] bit 4	-	-	-	-
B0	INT: mux QUAD_WW0[0] bit 5	INT: mux QUAD_WW0[0] bit 6	INT: mux QUAD_WW0[0] bit 7	INT: mux QUAD_WW0[0] bit 8	INT: mux SNG_N0_N3 bit 5	INT: mux QUAD_WW0[0] bit 1	INT: mux DBL_NW0[0] bit 6	INT: mux DBL_NW0[0] bit 5	INT: mux DBL_NW0[0] bit 7	INT: mux DBL_NW0[0] bit 8	INT: mux SNG_N0_N3 bit 8	INT: mux SNG_N0_N3 bit 7	INT: mux SNG_N0_N3 bit 6	INT: mux IMUX_FAN[0] bit 6	INT: mux IMUX_FAN[0] bit 9	INT: mux IMUX_FAN[0] bit 8	INT: mux IMUX_FAN[0] bit 1	INT: mux IMUX_IMUX[0] bit 1	INT: mux IMUX_FAN[0] bit 3	INT: mux IMUX_IMUX[0] bit 0	INT: mux IMUX_FAN[0] bit 5	INT: mux IMUX_IMUX[0] bit 6	INT: mux IMUX_FAN[0] bit 4	-	-	-	-	-

Tile INTF

Cells: 1

Switchbox INTF_INT

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[0]
Bits		Destination
MAIN[24][8]	MAIN[24][7]	OUT_TEST[0]
		Source
0	0	off
0	1	IMUX_IMUX[17]
1	0	IMUX_IMUX[25]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[1]
Bits		Destination
MAIN[25][17]	MAIN[25][16]	OUT_TEST[1]
		Source
0	0	off
0	1	IMUX_IMUX[18]
1	0	IMUX_IMUX[26]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[2]
Bits		Destination
MAIN[24][47]	MAIN[24][46]	OUT_TEST[2]
		Source
0	0	off
0	1	IMUX_IMUX[21]
1	0	IMUX_IMUX[29]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[3]
Bits		Destination
MAIN[25][56]	MAIN[25][55]	OUT_TEST[3]
		Source
0	0	off
0	1	IMUX_IMUX[22]
1	0	IMUX_IMUX[30]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[4]
Bits		Destination
MAIN[24][3]	MAIN[25][1]	OUT_TEST[4]
		Source
0	0	off
0	1	IMUX_IMUX[16]
1	0	IMUX_IMUX[24]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[5]
Bits		Destination
MAIN[25][22]	MAIN[24][10]	OUT_TEST[5]
		Source
0	0	off
0	1	IMUX_IMUX[19]
1	0	IMUX_IMUX[27]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[6]
Bits		Destination
MAIN[24][56]	MAIN[24][41]	OUT_TEST[6]
		Source
0	0	off
0	1	IMUX_IMUX[20]
1	0	IMUX_IMUX[28]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[7]
Bits		Destination
MAIN[24][62]	MAIN[25][60]	OUT_TEST[7]
		Source
0	0	off
0	1	IMUX_IMUX[23]
1	0	IMUX_IMUX[31]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[8]
Bits		Destination
MAIN[23][0]	MAIN[24][0]	OUT_TEST[8]
		Source
0	0	off
0	1	IMUX_IMUX[0]
1	0	IMUX_IMUX[8]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[9]
Bits		Destination
MAIN[24][21]	MAIN[25][19]	OUT_TEST[9]
		Source
0	0	off
0	1	IMUX_IMUX[3]
1	0	IMUX_IMUX[11]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[10]
Bits				Destination
MAIN[24][40]	MAIN[24][39]	MAIN[25][40]	MAIN[24][45]	OUT_TEST[10]
				Source
0	0	0	0	off
0	0	0	1	IMUX_CTRL[0]
0	0	1	0	IMUX_CTRL[1]
0	1	0	0	IMUX_IMUX[4]
1	0	0	0	IMUX_IMUX[12]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[11]
Bits				Destination
MAIN[23][60]	MAIN[25][59]	MAIN[25][58]	MAIN[24][60]	OUT_TEST[11]
				Source
0	0	0	0	off
0	0	0	1	IMUX_BYP_SITE[7]
0	0	1	0	IMUX_IMUX[7]
0	1	0	0	IMUX_IMUX[15]
1	0	0	0	IMUX_SPEC[3]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[12]
Bits		Destination
MAIN[25][6]	MAIN[25][5]	OUT_TEST[12]
		Source
0	0	off
0	1	IMUX_IMUX[1]
1	0	IMUX_IMUX[9]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[13]
Bits		Destination
MAIN[24][16]	MAIN[25][14]	OUT_TEST[13]
		Source
0	0	off
0	1	IMUX_IMUX[2]
1	0	IMUX_IMUX[10]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[14]
Bits		Destination
MAIN[25][45]	MAIN[25][44]	OUT_TEST[14]
		Source
0	0	off
0	1	IMUX_IMUX[5]
1	0	IMUX_IMUX[13]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[15]
Bits				Destination
MAIN[24][54]	MAIN[25][54]	MAIN[25][53]	MAIN[24][55]	OUT_TEST[15]
				Source
0	0	0	0	off
0	0	0	1	IMUX_BYP_SITE[6]
0	0	1	0	IMUX_IMUX[6]
0	1	0	0	IMUX_IMUX[14]
1	0	0	0	IMUX_SPEC[2]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[16]
Bits		Destination
MAIN[24][44]	MAIN[25][42]	OUT_TEST[16]
		Source
0	0	off
0	1	IMUX_IMUX[36]
1	0	IMUX_IMUX[44]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[17]
Bits		Destination
MAIN[25][63]	MAIN[23][62]	OUT_TEST[17]
		Source
0	0	off
0	1	IMUX_IMUX[39]
1	0	IMUX_IMUX[47]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[18]
Bits				Destination
MAIN[23][2]	MAIN[24][5]	MAIN[24][4]	MAIN[25][3]	OUT_TEST[18]
				Source
0	0	0	0	off
0	0	0	1	IMUX_FAN_SITE[0]
0	0	1	0	IMUX_IMUX[32]
0	1	0	0	IMUX_IMUX[40]
1	0	0	0	IMUX_SPEC[0]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[19]
Bits				Destination
MAIN[25][24]	MAIN[25][23]	MAIN[25][18]	MAIN[24][23]	OUT_TEST[19]
				Source
0	0	0	0	off
0	0	0	1	IMUX_CLK[0]
0	0	1	0	IMUX_CLK[1]
0	1	0	0	IMUX_IMUX[35]
1	0	0	0	IMUX_IMUX[43]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[20]
Bits		Destination
MAIN[24][49]	MAIN[25][47]	OUT_TEST[20]
		Source
0	0	off
0	1	IMUX_IMUX[37]
1	0	IMUX_IMUX[45]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[21]
Bits		Destination
MAIN[24][58]	MAIN[24][57]	OUT_TEST[21]
		Source
0	0	off
0	1	IMUX_IMUX[38]
1	0	IMUX_IMUX[46]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[22]
Bits				Destination
MAIN[25][9]	MAIN[23][10]	MAIN[24][9]	MAIN[25][8]	OUT_TEST[22]
				Source
0	0	0	0	off
0	0	0	1	IMUX_FAN_SITE[4]
0	0	1	0	IMUX_IMUX[33]
0	1	0	0	IMUX_IMUX[41]
1	0	0	0	IMUX_SPEC[1]

virtex6 INTF switchbox INTF_INT muxes OUT_TEST[23]
Bits		Destination
MAIN[24][19]	MAIN[24][18]	OUT_TEST[23]
		Source
0	0	off
0	1	IMUX_IMUX[34]
1	0	IMUX_IMUX[42]

Test mux INTF_TESTMUX

virtex6 INTF INTF_TESTMUX mux
Destination	Primary source	Test source 0
OUT[0]	OUT_BEL[0]	OUT_TEST[0]
OUT[1]	OUT_BEL[1]	OUT_TEST[1]
OUT[2]	OUT_BEL[2]	OUT_TEST[2]
OUT[3]	OUT_BEL[3]	OUT_TEST[3]
OUT[4]	OUT_BEL[4]	OUT_TEST[4]
OUT[5]	OUT_BEL[5]	OUT_TEST[5]
OUT[6]	OUT_BEL[6]	OUT_TEST[6]
OUT[7]	OUT_BEL[7]	OUT_TEST[7]
OUT[8]	OUT_BEL[8]	OUT_TEST[8]
OUT[9]	OUT_BEL[9]	OUT_TEST[9]
OUT[10]	OUT_BEL[10]	OUT_TEST[10]
OUT[11]	OUT_BEL[11]	OUT_TEST[11]
OUT[12]	OUT_BEL[12]	OUT_TEST[12]
OUT[13]	OUT_BEL[13]	OUT_TEST[13]
OUT[14]	OUT_BEL[14]	OUT_TEST[14]
OUT[15]	OUT_BEL[15]	OUT_TEST[15]
OUT[16]	OUT_BEL[16]	OUT_TEST[16]
OUT[17]	OUT_BEL[17]	OUT_TEST[17]
OUT[18]	OUT_BEL[18]	OUT_TEST[18]
OUT[19]	OUT_BEL[19]	OUT_TEST[19]
OUT[20]	OUT_BEL[20]	OUT_TEST[20]
OUT[21]	OUT_BEL[21]	OUT_TEST[21]
OUT[22]	OUT_BEL[22]	OUT_TEST[22]
OUT[23]	OUT_BEL[23]	OUT_TEST[23]

virtex6 INTF INTF_TESTMUX bits
Group	MAIN[23][36]
Primary	0
Test 0	1

Bitstream

virtex6 INTF rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[17] bit 1	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[17] bit 0	INTF_INT: mux OUT_TEST[7] bit 1	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[11] bit 3	INTF_INT: mux OUT_TEST[11] bit 0	INTF_INT: mux OUT_TEST[7] bit 0	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[11] bit 2	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[21] bit 1	INTF_INT: mux OUT_TEST[11] bit 1	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[21] bit 0	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[6] bit 1	INTF_INT: mux OUT_TEST[3] bit 1	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[15] bit 0	INTF_INT: mux OUT_TEST[3] bit 0	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[15] bit 3	INTF_INT: mux OUT_TEST[15] bit 2	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[15] bit 1	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[20] bit 1	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[2] bit 1	INTF_INT: mux OUT_TEST[20] bit 0	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[2] bit 0	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[10] bit 0	INTF_INT: mux OUT_TEST[14] bit 1	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[16] bit 1	INTF_INT: mux OUT_TEST[14] bit 0	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[16] bit 0	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[6] bit 0	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[10] bit 3	INTF_INT: mux OUT_TEST[10] bit 1	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[10] bit 2	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_TESTMUX: test mux bit 0	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[19] bit 3	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[19] bit 0	INTF_INT: mux OUT_TEST[19] bit 2	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[5] bit 1	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[9] bit 1	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[23] bit 1	INTF_INT: mux OUT_TEST[9] bit 0	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[23] bit 0	INTF_INT: mux OUT_TEST[19] bit 1	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[1] bit 1	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[13] bit 1	INTF_INT: mux OUT_TEST[1] bit 0	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[13] bit 0	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[22] bit 2	INTF_INT: mux OUT_TEST[5] bit 0	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[22] bit 1	INTF_INT: mux OUT_TEST[22] bit 3	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[0] bit 1	INTF_INT: mux OUT_TEST[22] bit 0	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[0] bit 0	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[12] bit 1	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[18] bit 2	INTF_INT: mux OUT_TEST[12] bit 0	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[18] bit 1	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[4] bit 1	INTF_INT: mux OUT_TEST[18] bit 0	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[18] bit 3	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[4] bit 0	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[8] bit 1	INTF_INT: mux OUT_TEST[8] bit 0	-	-	-

Tile INTF_DELAY

Cells: 1

Switchbox INTF_INT

virtex6 INTF_DELAY switchbox INTF_INT delays
Destination	Source	Bits
IMUX_IMUX_DELAY[0]	IMUX_IMUX[0]	MAIN[26][0]
IMUX_IMUX_DELAY[1]	IMUX_IMUX[1]	MAIN[26][8]
IMUX_IMUX_DELAY[2]	IMUX_IMUX[2]	MAIN[26][16]
IMUX_IMUX_DELAY[3]	IMUX_IMUX[3]	MAIN[26][24]
IMUX_IMUX_DELAY[4]	IMUX_IMUX[4]	MAIN[26][32]
IMUX_IMUX_DELAY[5]	IMUX_IMUX[5]	MAIN[26][40]
IMUX_IMUX_DELAY[6]	IMUX_IMUX[6]	MAIN[26][48]
IMUX_IMUX_DELAY[7]	IMUX_IMUX[7]	MAIN[26][56]
IMUX_IMUX_DELAY[8]	IMUX_IMUX[8]	MAIN[27][1]
IMUX_IMUX_DELAY[9]	IMUX_IMUX[9]	MAIN[27][9]
IMUX_IMUX_DELAY[10]	IMUX_IMUX[10]	MAIN[27][17]
IMUX_IMUX_DELAY[11]	IMUX_IMUX[11]	MAIN[27][25]
IMUX_IMUX_DELAY[12]	IMUX_IMUX[12]	MAIN[27][33]
IMUX_IMUX_DELAY[13]	IMUX_IMUX[13]	MAIN[27][41]
IMUX_IMUX_DELAY[14]	IMUX_IMUX[14]	MAIN[27][49]
IMUX_IMUX_DELAY[15]	IMUX_IMUX[15]	MAIN[27][57]
IMUX_IMUX_DELAY[16]	IMUX_IMUX[16]	MAIN[27][2]
IMUX_IMUX_DELAY[17]	IMUX_IMUX[17]	MAIN[27][10]
IMUX_IMUX_DELAY[18]	IMUX_IMUX[18]	MAIN[27][18]
IMUX_IMUX_DELAY[19]	IMUX_IMUX[19]	MAIN[27][26]
IMUX_IMUX_DELAY[20]	IMUX_IMUX[20]	MAIN[27][34]
IMUX_IMUX_DELAY[21]	IMUX_IMUX[21]	MAIN[27][42]
IMUX_IMUX_DELAY[22]	IMUX_IMUX[22]	MAIN[27][50]
IMUX_IMUX_DELAY[23]	IMUX_IMUX[23]	MAIN[27][58]
IMUX_IMUX_DELAY[24]	IMUX_IMUX[24]	MAIN[26][5]
IMUX_IMUX_DELAY[25]	IMUX_IMUX[25]	MAIN[26][13]
IMUX_IMUX_DELAY[26]	IMUX_IMUX[26]	MAIN[26][21]
IMUX_IMUX_DELAY[27]	IMUX_IMUX[27]	MAIN[26][29]
IMUX_IMUX_DELAY[28]	IMUX_IMUX[28]	MAIN[26][37]
IMUX_IMUX_DELAY[29]	IMUX_IMUX[29]	MAIN[26][45]
IMUX_IMUX_DELAY[30]	IMUX_IMUX[30]	MAIN[26][53]
IMUX_IMUX_DELAY[31]	IMUX_IMUX[31]	MAIN[26][61]
IMUX_IMUX_DELAY[32]	IMUX_IMUX[32]	MAIN[26][6]
IMUX_IMUX_DELAY[33]	IMUX_IMUX[33]	MAIN[26][14]
IMUX_IMUX_DELAY[34]	IMUX_IMUX[34]	MAIN[26][22]
IMUX_IMUX_DELAY[35]	IMUX_IMUX[35]	MAIN[26][30]
IMUX_IMUX_DELAY[36]	IMUX_IMUX[36]	MAIN[26][38]
IMUX_IMUX_DELAY[37]	IMUX_IMUX[37]	MAIN[26][46]
IMUX_IMUX_DELAY[38]	IMUX_IMUX[38]	MAIN[26][54]
IMUX_IMUX_DELAY[39]	IMUX_IMUX[39]	MAIN[26][62]
IMUX_IMUX_DELAY[40]	IMUX_IMUX[40]	MAIN[27][7]
IMUX_IMUX_DELAY[41]	IMUX_IMUX[41]	MAIN[27][15]
IMUX_IMUX_DELAY[42]	IMUX_IMUX[42]	MAIN[27][23]
IMUX_IMUX_DELAY[43]	IMUX_IMUX[43]	MAIN[27][31]
IMUX_IMUX_DELAY[44]	IMUX_IMUX[44]	MAIN[27][39]
IMUX_IMUX_DELAY[45]	IMUX_IMUX[45]	MAIN[27][47]
IMUX_IMUX_DELAY[46]	IMUX_IMUX[46]	MAIN[27][55]
IMUX_IMUX_DELAY[47]	IMUX_IMUX[47]	MAIN[27][63]
Delay step
0		0
1		1

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[0]
Bits		Destination
MAIN[24][8]	MAIN[24][7]	OUT_TEST[0]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[17]
1	0	IMUX_IMUX_DELAY[25]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[1]
Bits		Destination
MAIN[25][17]	MAIN[25][16]	OUT_TEST[1]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[18]
1	0	IMUX_IMUX_DELAY[26]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[2]
Bits		Destination
MAIN[24][47]	MAIN[24][46]	OUT_TEST[2]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[21]
1	0	IMUX_IMUX_DELAY[29]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[3]
Bits		Destination
MAIN[25][56]	MAIN[25][55]	OUT_TEST[3]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[22]
1	0	IMUX_IMUX_DELAY[30]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[4]
Bits		Destination
MAIN[24][3]	MAIN[25][1]	OUT_TEST[4]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[16]
1	0	IMUX_IMUX_DELAY[24]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[5]
Bits		Destination
MAIN[25][22]	MAIN[24][10]	OUT_TEST[5]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[19]
1	0	IMUX_IMUX_DELAY[27]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[6]
Bits		Destination
MAIN[24][56]	MAIN[24][41]	OUT_TEST[6]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[20]
1	0	IMUX_IMUX_DELAY[28]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[7]
Bits		Destination
MAIN[24][62]	MAIN[25][60]	OUT_TEST[7]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[23]
1	0	IMUX_IMUX_DELAY[31]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[8]
Bits		Destination
MAIN[23][0]	MAIN[24][0]	OUT_TEST[8]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[0]
1	0	IMUX_IMUX_DELAY[8]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[9]
Bits		Destination
MAIN[24][21]	MAIN[25][19]	OUT_TEST[9]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[3]
1	0	IMUX_IMUX_DELAY[11]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[10]
Bits				Destination
MAIN[24][40]	MAIN[24][39]	MAIN[25][40]	MAIN[24][45]	OUT_TEST[10]
				Source
0	0	0	0	off
0	0	0	1	IMUX_CTRL[0]
0	0	1	0	IMUX_CTRL[1]
0	1	0	0	IMUX_IMUX_DELAY[4]
1	0	0	0	IMUX_IMUX_DELAY[12]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[11]
Bits				Destination
MAIN[23][60]	MAIN[25][59]	MAIN[25][58]	MAIN[24][60]	OUT_TEST[11]
				Source
0	0	0	0	off
0	0	0	1	IMUX_BYP_SITE[7]
0	0	1	0	IMUX_IMUX_DELAY[7]
0	1	0	0	IMUX_IMUX_DELAY[15]
1	0	0	0	IMUX_SPEC[3]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[12]
Bits		Destination
MAIN[25][6]	MAIN[25][5]	OUT_TEST[12]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[1]
1	0	IMUX_IMUX_DELAY[9]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[13]
Bits		Destination
MAIN[24][16]	MAIN[25][14]	OUT_TEST[13]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[2]
1	0	IMUX_IMUX_DELAY[10]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[14]
Bits		Destination
MAIN[25][45]	MAIN[25][44]	OUT_TEST[14]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[5]
1	0	IMUX_IMUX_DELAY[13]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[15]
Bits				Destination
MAIN[24][54]	MAIN[25][54]	MAIN[25][53]	MAIN[24][55]	OUT_TEST[15]
				Source
0	0	0	0	off
0	0	0	1	IMUX_BYP_SITE[6]
0	0	1	0	IMUX_IMUX_DELAY[6]
0	1	0	0	IMUX_IMUX_DELAY[14]
1	0	0	0	IMUX_SPEC[2]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[16]
Bits		Destination
MAIN[24][44]	MAIN[25][42]	OUT_TEST[16]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[36]
1	0	IMUX_IMUX_DELAY[44]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[17]
Bits		Destination
MAIN[25][63]	MAIN[23][62]	OUT_TEST[17]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[39]
1	0	IMUX_IMUX_DELAY[47]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[18]
Bits				Destination
MAIN[23][2]	MAIN[24][5]	MAIN[24][4]	MAIN[25][3]	OUT_TEST[18]
				Source
0	0	0	0	off
0	0	0	1	IMUX_FAN_SITE[0]
0	0	1	0	IMUX_IMUX_DELAY[32]
0	1	0	0	IMUX_IMUX_DELAY[40]
1	0	0	0	IMUX_SPEC[0]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[19]
Bits				Destination
MAIN[25][24]	MAIN[25][23]	MAIN[25][18]	MAIN[24][23]	OUT_TEST[19]
				Source
0	0	0	0	off
0	0	0	1	IMUX_CLK[0]
0	0	1	0	IMUX_CLK[1]
0	1	0	0	IMUX_IMUX_DELAY[35]
1	0	0	0	IMUX_IMUX_DELAY[43]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[20]
Bits		Destination
MAIN[24][49]	MAIN[25][47]	OUT_TEST[20]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[37]
1	0	IMUX_IMUX_DELAY[45]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[21]
Bits		Destination
MAIN[24][58]	MAIN[24][57]	OUT_TEST[21]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[38]
1	0	IMUX_IMUX_DELAY[46]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[22]
Bits				Destination
MAIN[25][9]	MAIN[23][10]	MAIN[24][9]	MAIN[25][8]	OUT_TEST[22]
				Source
0	0	0	0	off
0	0	0	1	IMUX_FAN_SITE[4]
0	0	1	0	IMUX_IMUX_DELAY[33]
0	1	0	0	IMUX_IMUX_DELAY[41]
1	0	0	0	IMUX_SPEC[1]

virtex6 INTF_DELAY switchbox INTF_INT muxes OUT_TEST[23]
Bits		Destination
MAIN[24][19]	MAIN[24][18]	OUT_TEST[23]
		Source
0	0	off
0	1	IMUX_IMUX_DELAY[34]
1	0	IMUX_IMUX_DELAY[42]

Test mux INTF_TESTMUX

virtex6 INTF_DELAY INTF_TESTMUX mux
Destination	Primary source	Test source 0
OUT[0]	OUT_BEL[0]	OUT_TEST[0]
OUT[1]	OUT_BEL[1]	OUT_TEST[1]
OUT[2]	OUT_BEL[2]	OUT_TEST[2]
OUT[3]	OUT_BEL[3]	OUT_TEST[3]
OUT[4]	OUT_BEL[4]	OUT_TEST[4]
OUT[5]	OUT_BEL[5]	OUT_TEST[5]
OUT[6]	OUT_BEL[6]	OUT_TEST[6]
OUT[7]	OUT_BEL[7]	OUT_TEST[7]
OUT[8]	OUT_BEL[8]	OUT_TEST[8]
OUT[9]	OUT_BEL[9]	OUT_TEST[9]
OUT[10]	OUT_BEL[10]	OUT_TEST[10]
OUT[11]	OUT_BEL[11]	OUT_TEST[11]
OUT[12]	OUT_BEL[12]	OUT_TEST[12]
OUT[13]	OUT_BEL[13]	OUT_TEST[13]
OUT[14]	OUT_BEL[14]	OUT_TEST[14]
OUT[15]	OUT_BEL[15]	OUT_TEST[15]
OUT[16]	OUT_BEL[16]	OUT_TEST[16]
OUT[17]	OUT_BEL[17]	OUT_TEST[17]
OUT[18]	OUT_BEL[18]	OUT_TEST[18]
OUT[19]	OUT_BEL[19]	OUT_TEST[19]
OUT[20]	OUT_BEL[20]	OUT_TEST[20]
OUT[21]	OUT_BEL[21]	OUT_TEST[21]
OUT[22]	OUT_BEL[22]	OUT_TEST[22]
OUT[23]	OUT_BEL[23]	OUT_TEST[23]

virtex6 INTF_DELAY INTF_TESTMUX bits
Group	MAIN[23][36]
Primary	0
Test 0	1

Bitstream

virtex6 INTF_DELAY rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[17] bit 1	-	INTF_INT: delay IMUX_IMUX_DELAY[47] ← IMUX_IMUX[47] bit 0
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[17] bit 0	INTF_INT: mux OUT_TEST[7] bit 1	-	INTF_INT: delay IMUX_IMUX_DELAY[39] ← IMUX_IMUX[39] bit 0	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[31] ← IMUX_IMUX[31] bit 0	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[11] bit 3	INTF_INT: mux OUT_TEST[11] bit 0	INTF_INT: mux OUT_TEST[7] bit 0	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[11] bit 2	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[21] bit 1	INTF_INT: mux OUT_TEST[11] bit 1	-	INTF_INT: delay IMUX_IMUX_DELAY[23] ← IMUX_IMUX[23] bit 0
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[21] bit 0	-	-	INTF_INT: delay IMUX_IMUX_DELAY[15] ← IMUX_IMUX[15] bit 0
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[6] bit 1	INTF_INT: mux OUT_TEST[3] bit 1	INTF_INT: delay IMUX_IMUX_DELAY[7] ← IMUX_IMUX[7] bit 0	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[15] bit 0	INTF_INT: mux OUT_TEST[3] bit 0	-	INTF_INT: delay IMUX_IMUX_DELAY[46] ← IMUX_IMUX[46] bit 0
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[15] bit 3	INTF_INT: mux OUT_TEST[15] bit 2	INTF_INT: delay IMUX_IMUX_DELAY[38] ← IMUX_IMUX[38] bit 0	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[15] bit 1	INTF_INT: delay IMUX_IMUX_DELAY[30] ← IMUX_IMUX[30] bit 0	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[22] ← IMUX_IMUX[22] bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[20] bit 1	-	-	INTF_INT: delay IMUX_IMUX_DELAY[14] ← IMUX_IMUX[14] bit 0
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[6] ← IMUX_IMUX[6] bit 0	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[2] bit 1	INTF_INT: mux OUT_TEST[20] bit 0	-	INTF_INT: delay IMUX_IMUX_DELAY[45] ← IMUX_IMUX[45] bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[2] bit 0	-	INTF_INT: delay IMUX_IMUX_DELAY[37] ← IMUX_IMUX[37] bit 0	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[10] bit 0	INTF_INT: mux OUT_TEST[14] bit 1	INTF_INT: delay IMUX_IMUX_DELAY[29] ← IMUX_IMUX[29] bit 0	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[16] bit 1	INTF_INT: mux OUT_TEST[14] bit 0	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[16] bit 0	-	INTF_INT: delay IMUX_IMUX_DELAY[21] ← IMUX_IMUX[21] bit 0
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[6] bit 0	-	-	INTF_INT: delay IMUX_IMUX_DELAY[13] ← IMUX_IMUX[13] bit 0
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[10] bit 3	INTF_INT: mux OUT_TEST[10] bit 1	INTF_INT: delay IMUX_IMUX_DELAY[5] ← IMUX_IMUX[5] bit 0	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[10] bit 2	-	-	INTF_INT: delay IMUX_IMUX_DELAY[44] ← IMUX_IMUX[44] bit 0
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[36] ← IMUX_IMUX[36] bit 0	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[28] ← IMUX_IMUX[28] bit 0	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_TESTMUX: test mux bit 0	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[20] ← IMUX_IMUX[20] bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[12] ← IMUX_IMUX[12] bit 0
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[4] ← IMUX_IMUX[4] bit 0	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[43] ← IMUX_IMUX[43] bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[35] ← IMUX_IMUX[35] bit 0	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[27] ← IMUX_IMUX[27] bit 0	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[19] ← IMUX_IMUX[19] bit 0
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[11] ← IMUX_IMUX[11] bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[19] bit 3	INTF_INT: delay IMUX_IMUX_DELAY[3] ← IMUX_IMUX[3] bit 0	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[19] bit 0	INTF_INT: mux OUT_TEST[19] bit 2	-	INTF_INT: delay IMUX_IMUX_DELAY[42] ← IMUX_IMUX[42] bit 0
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[5] bit 1	INTF_INT: delay IMUX_IMUX_DELAY[34] ← IMUX_IMUX[34] bit 0	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[9] bit 1	-	INTF_INT: delay IMUX_IMUX_DELAY[26] ← IMUX_IMUX[26] bit 0	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[23] bit 1	INTF_INT: mux OUT_TEST[9] bit 0	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[23] bit 0	INTF_INT: mux OUT_TEST[19] bit 1	-	INTF_INT: delay IMUX_IMUX_DELAY[18] ← IMUX_IMUX[18] bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[1] bit 1	-	INTF_INT: delay IMUX_IMUX_DELAY[10] ← IMUX_IMUX[10] bit 0
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[13] bit 1	INTF_INT: mux OUT_TEST[1] bit 0	INTF_INT: delay IMUX_IMUX_DELAY[2] ← IMUX_IMUX[2] bit 0	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[41] ← IMUX_IMUX[41] bit 0
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[13] bit 0	INTF_INT: delay IMUX_IMUX_DELAY[33] ← IMUX_IMUX[33] bit 0	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[25] ← IMUX_IMUX[25] bit 0	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[22] bit 2	INTF_INT: mux OUT_TEST[5] bit 0	-	-	INTF_INT: delay IMUX_IMUX_DELAY[17] ← IMUX_IMUX[17] bit 0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[22] bit 1	INTF_INT: mux OUT_TEST[22] bit 3	-	INTF_INT: delay IMUX_IMUX_DELAY[9] ← IMUX_IMUX[9] bit 0
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[0] bit 1	INTF_INT: mux OUT_TEST[22] bit 0	INTF_INT: delay IMUX_IMUX_DELAY[1] ← IMUX_IMUX[1] bit 0	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[0] bit 0	-	-	INTF_INT: delay IMUX_IMUX_DELAY[40] ← IMUX_IMUX[40] bit 0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[12] bit 1	INTF_INT: delay IMUX_IMUX_DELAY[32] ← IMUX_IMUX[32] bit 0	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[18] bit 2	INTF_INT: mux OUT_TEST[12] bit 0	INTF_INT: delay IMUX_IMUX_DELAY[24] ← IMUX_IMUX[24] bit 0	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[18] bit 1	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[4] bit 1	INTF_INT: mux OUT_TEST[18] bit 0	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[18] bit 3	-	-	-	INTF_INT: delay IMUX_IMUX_DELAY[16] ← IMUX_IMUX[16] bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[4] bit 0	-	INTF_INT: delay IMUX_IMUX_DELAY[8] ← IMUX_IMUX[8] bit 0
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INTF_INT: mux OUT_TEST[8] bit 1	INTF_INT: mux OUT_TEST[8] bit 0	-	INTF_INT: delay IMUX_IMUX_DELAY[0] ← IMUX_IMUX[0] bit 0	-

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