GTH transceivers

TODO: document

Tile GTH_COMMON

Cells: 10

Switchbox SPEC_INT

virtex7 GTH_COMMON switchbox SPEC_INT permanent buffers
Destination	Source
CELL[3].HROW_O[4]	CHANNEL[0].OUT_GT_RXOUTCLK
CELL[3].HROW_O[5]	CHANNEL[1].OUT_GT_RXOUTCLK
CELL[3].HROW_O[6]	CHANNEL[0].OUT_GT_TXOUTCLK
CELL[3].HROW_O[7]	CHANNEL[1].OUT_GT_TXOUTCLK
CELL[3].HROW_O[8]	CELL[3].OUT_GT_MGTCLKOUT[0]
CELL[3].HROW_O[9]	CELL[3].OUT_GT_MGTCLKOUT[1]
CELL[3].HROW_O[10]	CHANNEL[2].OUT_GT_RXOUTCLK
CELL[3].HROW_O[11]	CHANNEL[3].OUT_GT_RXOUTCLK
CELL[3].HROW_O[12]	CHANNEL[2].OUT_GT_TXOUTCLK
CELL[3].HROW_O[13]	CHANNEL[3].OUT_GT_TXOUTCLK

Bels GTCLK

virtex7 GTH_COMMON bel GTCLK pins
Pin	Direction	GTCLK[0]	GTCLK[1]
CEB	in	CELL[3].IMUX_IMUX_DELAY[26]	CELL[3].IMUX_IMUX_DELAY[29]
CLKTESTSIG	in	CELL[4].IMUX_CLK[1] invert by MAIN[1][31][32]	CELL[3].IMUX_CLK[0] invert by MAIN[1][30][32]
CLKOUT	out	CELL[3].OUT_GT_MGTCLKOUT[0]	CELL[3].OUT_GT_MGTCLKOUT[1]

virtex7 GTH_COMMON bel GTCLK attribute bits
Attribute	GTCLK[0]	GTCLK[1]
CLKCM_CFG	MAIN[1][30][10]	MAIN[1][31][10]
CLKRCV_TRST	MAIN[1][30][12]	MAIN[1][31][12]
MUX_CLKOUT	[enum: GTCLK_MUX_CLKOUT]	[enum: GTCLK_MUX_CLKOUT]

virtex7 GTH_COMMON enum GTCLK_MUX_CLKOUT
GTCLK[0].MUX_CLKOUT	MAIN[1][30][8]	MAIN[1][31][8]
GTCLK[1].MUX_CLKOUT	MAIN[1][30][9]	MAIN[1][31][9]
O	0	0
ODIV2	1	0
NONE	0	1
CLKTESTSIG	1	1

Bels GTX_COMMON

virtex7 GTH_COMMON bel GTX_COMMON pins
Pin	Direction	GTX_COMMON
DRPCLK	in	CELL[1].IMUX_CLK[1] invert by MAIN[1][31][35]
DRPEN	in	CELL[1].IMUX_IMUX_DELAY[29]
DRPWE	in	CELL[0].IMUX_IMUX_DELAY[29]
DRPADDR[0]	in	CELL[2].IMUX_IMUX_DELAY[24]
DRPADDR[1]	in	CELL[2].IMUX_IMUX_DELAY[25]
DRPADDR[2]	in	CELL[2].IMUX_IMUX_DELAY[28]
DRPADDR[3]	in	CELL[2].IMUX_IMUX_DELAY[29]
DRPADDR[4]	in	CELL[2].IMUX_IMUX_DELAY[26]
DRPADDR[5]	in	CELL[2].IMUX_IMUX_DELAY[27]
DRPADDR[6]	in	CELL[2].IMUX_IMUX_DELAY[30]
DRPADDR[7]	in	CELL[2].IMUX_IMUX_DELAY[31]
DRPDI[0]	in	CELL[0].IMUX_IMUX_DELAY[23]
DRPDI[1]	in	CELL[0].IMUX_IMUX_DELAY[22]
DRPDI[2]	in	CELL[0].IMUX_IMUX_DELAY[19]
DRPDI[3]	in	CELL[0].IMUX_IMUX_DELAY[18]
DRPDI[4]	in	CELL[0].IMUX_IMUX_DELAY[21]
DRPDI[5]	in	CELL[0].IMUX_IMUX_DELAY[20]
DRPDI[6]	in	CELL[0].IMUX_IMUX_DELAY[17]
DRPDI[7]	in	CELL[0].IMUX_IMUX_DELAY[16]
DRPDI[8]	in	CELL[1].IMUX_IMUX_DELAY[23]
DRPDI[9]	in	CELL[1].IMUX_IMUX_DELAY[22]
DRPDI[10]	in	CELL[1].IMUX_IMUX_DELAY[19]
DRPDI[11]	in	CELL[1].IMUX_IMUX_DELAY[18]
DRPDI[12]	in	CELL[1].IMUX_IMUX_DELAY[21]
DRPDI[13]	in	CELL[1].IMUX_IMUX_DELAY[20]
DRPDI[14]	in	CELL[1].IMUX_IMUX_DELAY[17]
DRPDI[15]	in	CELL[1].IMUX_IMUX_DELAY[16]
BGBYPASSB	in	CELL[5].IMUX_IMUX_DELAY[30]
BGMONITORENB	in	CELL[5].IMUX_IMUX_DELAY[27]
BGPDB	in	CELL[5].IMUX_IMUX_DELAY[26]
BGRCALOVRD[0]	in	CELL[4].IMUX_IMUX_DELAY[31]
BGRCALOVRD[1]	in	CELL[4].IMUX_IMUX_DELAY[30]
BGRCALOVRD[2]	in	CELL[4].IMUX_IMUX_DELAY[27]
BGRCALOVRD[3]	in	CELL[4].IMUX_IMUX_DELAY[26]
BGRCALOVRD[4]	in	CELL[4].IMUX_IMUX_DELAY[29]
BGRCALOVRDENB	in	CELL[5].IMUX_IMUX_DELAY[40]
GTGREFCLK	in	CELL[2].IMUX_CLK[0] invert by MAIN[1][30][36]
PMARSVD[0]	in	CELL[2].IMUX_IMUX_DELAY[21]
PMARSVD[1]	in	CELL[3].IMUX_IMUX_DELAY[21]
PMARSVD[2]	in	CELL[4].IMUX_IMUX_DELAY[21]
PMARSVD[3]	in	CELL[5].IMUX_IMUX_DELAY[21]
PMARSVD[4]	in	CELL[2].IMUX_IMUX_DELAY[20]
PMARSVD[5]	in	CELL[3].IMUX_IMUX_DELAY[20]
PMARSVD[6]	in	CELL[4].IMUX_IMUX_DELAY[20]
PMARSVD[7]	in	CELL[5].IMUX_IMUX_DELAY[20]
PMASCANCLK[0]	in	CELL[4].IMUX_CLK[0] invert by MAIN[1][30][35]
PMASCANCLK[1]	in	CELL[1].IMUX_CLK[0] invert by MAIN[1][31][34]
PMASCANENB	in	CELL[1].IMUX_IMUX_DELAY[31]
PMASCANIN[0]	in	CELL[0].IMUX_IMUX_DELAY[25]
PMASCANIN[1]	in	CELL[1].IMUX_IMUX_DELAY[25]
PMASCANIN[2]	in	CELL[3].IMUX_IMUX_DELAY[25]
PMASCANIN[3]	in	CELL[4].IMUX_IMUX_DELAY[25]
PMASCANIN[4]	in	CELL[5].IMUX_IMUX_DELAY[25]
QDPMASCANMODEB	in	CELL[5].IMUX_IMUX_DELAY[29]
QDPMASCANRSTEN	in	CELL[5].IMUX_IMUX_DELAY[28]
QPLLCLKSPARE[0]	in	CELL[0].IMUX_CLK[1] invert by MAIN[1][31][33]
QPLLCLKSPARE[1]	in	CELL[5].IMUX_CLK[0] invert by MAIN[1][30][33]
QPLLLOCKDETCLK	in	CELL[3].IMUX_CLK[1] invert by MAIN[1][30][34]
QPLLLOCKEN	in	CELL[3].IMUX_IMUX_DELAY[24]
QPLLOUTRESET	in	CELL[2].IMUX_CTRL[1]
QPLLPD	in	CELL[3].IMUX_IMUX_DELAY[28]
QPLLREFCLKSEL[0]	in	CELL[3].IMUX_IMUX_DELAY[31]
QPLLREFCLKSEL[1]	in	CELL[3].IMUX_IMUX_DELAY[30]
QPLLREFCLKSEL[2]	in	CELL[3].IMUX_IMUX_DELAY[27]
QPLLRESET	in	CELL[3].IMUX_CTRL[0]
QPLLRSVD1[0]	in	CELL[2].IMUX_IMUX_DELAY[23]
QPLLRSVD1[1]	in	CELL[2].IMUX_IMUX_DELAY[22]
QPLLRSVD1[2]	in	CELL[2].IMUX_IMUX_DELAY[19]
QPLLRSVD1[3]	in	CELL[2].IMUX_IMUX_DELAY[18]
QPLLRSVD1[4]	in	CELL[3].IMUX_IMUX_DELAY[23]
QPLLRSVD1[5]	in	CELL[3].IMUX_IMUX_DELAY[22]
QPLLRSVD1[6]	in	CELL[3].IMUX_IMUX_DELAY[19]
QPLLRSVD1[7]	in	CELL[3].IMUX_IMUX_DELAY[18]
QPLLRSVD1[8]	in	CELL[4].IMUX_IMUX_DELAY[23]
QPLLRSVD1[9]	in	CELL[4].IMUX_IMUX_DELAY[22]
QPLLRSVD1[10]	in	CELL[4].IMUX_IMUX_DELAY[19]
QPLLRSVD1[11]	in	CELL[4].IMUX_IMUX_DELAY[18]
QPLLRSVD1[12]	in	CELL[5].IMUX_IMUX_DELAY[23]
QPLLRSVD1[13]	in	CELL[5].IMUX_IMUX_DELAY[22]
QPLLRSVD1[14]	in	CELL[5].IMUX_IMUX_DELAY[19]
QPLLRSVD1[15]	in	CELL[5].IMUX_IMUX_DELAY[18]
QPLLRSVD2[0]	in	CELL[2].IMUX_IMUX_DELAY[16]
QPLLRSVD2[1]	in	CELL[3].IMUX_IMUX_DELAY[16]
QPLLRSVD2[2]	in	CELL[4].IMUX_IMUX_DELAY[16]
QPLLRSVD2[3]	in	CELL[5].IMUX_IMUX_DELAY[16]
QPLLRSVD2[4]	in	CELL[5].IMUX_IMUX_DELAY[17]
RCALENB	in	CELL[4].IMUX_IMUX_DELAY[28]
DRPRDY	out	CELL[0].OUT_BEL[21]
DRPDO[0]	out	CELL[0].OUT_BEL[15]
DRPDO[1]	out	CELL[0].OUT_BEL[11]
DRPDO[2]	out	CELL[0].OUT_BEL[13]
DRPDO[3]	out	CELL[0].OUT_BEL[9]
DRPDO[4]	out	CELL[0].OUT_BEL[10]
DRPDO[5]	out	CELL[0].OUT_BEL[14]
DRPDO[6]	out	CELL[0].OUT_BEL[8]
DRPDO[7]	out	CELL[0].OUT_BEL[12]
DRPDO[8]	out	CELL[1].OUT_BEL[15]
DRPDO[9]	out	CELL[1].OUT_BEL[11]
DRPDO[10]	out	CELL[1].OUT_BEL[13]
DRPDO[11]	out	CELL[1].OUT_BEL[9]
DRPDO[12]	out	CELL[1].OUT_BEL[10]
DRPDO[13]	out	CELL[1].OUT_BEL[14]
DRPDO[14]	out	CELL[1].OUT_BEL[8]
DRPDO[15]	out	CELL[1].OUT_BEL[12]
PMARSVDOUT[0]	out	CELL[5].OUT_BEL[21]
PMARSVDOUT[1]	out	CELL[5].OUT_BEL[17]
PMARSVDOUT[2]	out	CELL[5].OUT_BEL[23]
PMARSVDOUT[3]	out	CELL[5].OUT_BEL[19]
PMARSVDOUT[4]	out	CELL[5].OUT_BEL[16]
PMARSVDOUT[5]	out	CELL[5].OUT_BEL[20]
PMARSVDOUT[6]	out	CELL[5].OUT_BEL[18]
PMARSVDOUT[7]	out	CELL[5].OUT_BEL[22]
PMARSVDOUT[8]	out	CELL[4].OUT_BEL[21]
PMARSVDOUT[9]	out	CELL[4].OUT_BEL[17]
PMARSVDOUT[10]	out	CELL[4].OUT_BEL[23]
PMARSVDOUT[11]	out	CELL[4].OUT_BEL[19]
PMARSVDOUT[12]	out	CELL[3].OUT_BEL[20]
PMARSVDOUT[13]	out	CELL[3].OUT_BEL[18]
PMARSVDOUT[14]	out	CELL[3].OUT_BEL[8]
PMARSVDOUT[15]	out	CELL[3].OUT_BEL[22]
PMASCANOUT[0]	out	CELL[2].OUT_BEL[9]
PMASCANOUT[1]	out	CELL[3].OUT_BEL[9]
PMASCANOUT[2]	out	CELL[4].OUT_BEL[9]
PMASCANOUT[3]	out	CELL[5].OUT_BEL[9]
PMASCANOUT[4]	out	CELL[3].OUT_BEL[10]
QPLLDMONITOR[0]	out	CELL[3].OUT_BEL[19]
QPLLDMONITOR[1]	out	CELL[3].OUT_BEL[23]
QPLLDMONITOR[2]	out	CELL[3].OUT_BEL[17]
QPLLDMONITOR[3]	out	CELL[3].OUT_BEL[21]
QPLLDMONITOR[4]	out	CELL[4].OUT_BEL[22]
QPLLDMONITOR[5]	out	CELL[4].OUT_BEL[18]
QPLLDMONITOR[6]	out	CELL[4].OUT_BEL[20]
QPLLDMONITOR[7]	out	CELL[4].OUT_BEL[16]
QPLLFBCLKLOST	out	CELL[2].OUT_BEL[19]
QPLLLOCK	out	CELL[2].OUT_BEL[14]
QPLLREFCLKLOST	out	CELL[2].OUT_BEL[10]
REFCLKOUTMONITOR	out	CELL[3].OUT_BEL[2]

virtex7 GTH_COMMON bel GTX_COMMON attribute bits
Attribute	GTX_COMMON
DRP[0] bit 0	MAIN[0][28][0]
DRP[0] bit 1	MAIN[0][29][0]
DRP[0] bit 2	MAIN[0][28][1]
DRP[0] bit 3	MAIN[0][29][1]
DRP[0] bit 4	MAIN[0][28][2]
DRP[0] bit 5	MAIN[0][29][2]
DRP[0] bit 6	MAIN[0][28][3]
DRP[0] bit 7	MAIN[0][29][3]
DRP[0] bit 8	MAIN[0][28][4]
DRP[0] bit 9	MAIN[0][29][4]
DRP[0] bit 10	MAIN[0][28][5]
DRP[0] bit 11	MAIN[0][29][5]
DRP[0] bit 12	MAIN[0][28][6]
DRP[0] bit 13	MAIN[0][29][6]
DRP[0] bit 14	MAIN[0][28][7]
DRP[0] bit 15	MAIN[0][29][7]
DRP[1] bit 0	MAIN[0][28][8]
DRP[1] bit 1	MAIN[0][29][8]
DRP[1] bit 2	MAIN[0][28][9]
DRP[1] bit 3	MAIN[0][29][9]
DRP[1] bit 4	MAIN[0][28][10]
DRP[1] bit 5	MAIN[0][29][10]
DRP[1] bit 6	MAIN[0][28][11]
DRP[1] bit 7	MAIN[0][29][11]
DRP[1] bit 8	MAIN[0][28][12]
DRP[1] bit 9	MAIN[0][29][12]
DRP[1] bit 10	MAIN[0][28][13]
DRP[1] bit 11	MAIN[0][29][13]
DRP[1] bit 12	MAIN[0][28][14]
DRP[1] bit 13	MAIN[0][29][14]
DRP[1] bit 14	MAIN[0][28][15]
DRP[1] bit 15	MAIN[0][29][15]
DRP[2] bit 0	MAIN[0][28][16]
DRP[2] bit 1	MAIN[0][29][16]
DRP[2] bit 2	MAIN[0][28][17]
DRP[2] bit 3	MAIN[0][29][17]
DRP[2] bit 4	MAIN[0][28][18]
DRP[2] bit 5	MAIN[0][29][18]
DRP[2] bit 6	MAIN[0][28][19]
DRP[2] bit 7	MAIN[0][29][19]
DRP[2] bit 8	MAIN[0][28][20]
DRP[2] bit 9	MAIN[0][29][20]
DRP[2] bit 10	MAIN[0][28][21]
DRP[2] bit 11	MAIN[0][29][21]
DRP[2] bit 12	MAIN[0][28][22]
DRP[2] bit 13	MAIN[0][29][22]
DRP[2] bit 14	MAIN[0][28][23]
DRP[2] bit 15	MAIN[0][29][23]
DRP[3] bit 0	MAIN[0][28][24]
DRP[3] bit 1	MAIN[0][29][24]
DRP[3] bit 2	MAIN[0][28][25]
DRP[3] bit 3	MAIN[0][29][25]
DRP[3] bit 4	MAIN[0][28][26]
DRP[3] bit 5	MAIN[0][29][26]
DRP[3] bit 6	MAIN[0][28][27]
DRP[3] bit 7	MAIN[0][29][27]
DRP[3] bit 8	MAIN[0][28][28]
DRP[3] bit 9	MAIN[0][29][28]
DRP[3] bit 10	MAIN[0][28][29]
DRP[3] bit 11	MAIN[0][29][29]
DRP[3] bit 12	MAIN[0][28][30]
DRP[3] bit 13	MAIN[0][29][30]
DRP[3] bit 14	MAIN[0][28][31]
DRP[3] bit 15	MAIN[0][29][31]
DRP[4] bit 0	MAIN[0][28][32]
DRP[4] bit 1	MAIN[0][29][32]
DRP[4] bit 2	MAIN[0][28][33]
DRP[4] bit 3	MAIN[0][29][33]
DRP[4] bit 4	MAIN[0][28][34]
DRP[4] bit 5	MAIN[0][29][34]
DRP[4] bit 6	MAIN[0][28][35]
DRP[4] bit 7	MAIN[0][29][35]
DRP[4] bit 8	MAIN[0][28][36]
DRP[4] bit 9	MAIN[0][29][36]
DRP[4] bit 10	MAIN[0][28][37]
DRP[4] bit 11	MAIN[0][29][37]
DRP[4] bit 12	MAIN[0][28][38]
DRP[4] bit 13	MAIN[0][29][38]
DRP[4] bit 14	MAIN[0][28][39]
DRP[4] bit 15	MAIN[0][29][39]
DRP[5] bit 0	MAIN[0][28][40]
DRP[5] bit 1	MAIN[0][29][40]
DRP[5] bit 2	MAIN[0][28][41]
DRP[5] bit 3	MAIN[0][29][41]
DRP[5] bit 4	MAIN[0][28][42]
DRP[5] bit 5	MAIN[0][29][42]
DRP[5] bit 6	MAIN[0][28][43]
DRP[5] bit 7	MAIN[0][29][43]
DRP[5] bit 8	MAIN[0][28][44]
DRP[5] bit 9	MAIN[0][29][44]
DRP[5] bit 10	MAIN[0][28][45]
DRP[5] bit 11	MAIN[0][29][45]
DRP[5] bit 12	MAIN[0][28][46]
DRP[5] bit 13	MAIN[0][29][46]
DRP[5] bit 14	MAIN[0][28][47]
DRP[5] bit 15	MAIN[0][29][47]
DRP[6] bit 0	MAIN[0][28][48]
DRP[6] bit 1	MAIN[0][29][48]
DRP[6] bit 2	MAIN[0][28][49]
DRP[6] bit 3	MAIN[0][29][49]
DRP[6] bit 4	MAIN[0][28][50]
DRP[6] bit 5	MAIN[0][29][50]
DRP[6] bit 6	MAIN[0][28][51]
DRP[6] bit 7	MAIN[0][29][51]
DRP[6] bit 8	MAIN[0][28][52]
DRP[6] bit 9	MAIN[0][29][52]
DRP[6] bit 10	MAIN[0][28][53]
DRP[6] bit 11	MAIN[0][29][53]
DRP[6] bit 12	MAIN[0][28][54]
DRP[6] bit 13	MAIN[0][29][54]
DRP[6] bit 14	MAIN[0][28][55]
DRP[6] bit 15	MAIN[0][29][55]
DRP[7] bit 0	MAIN[0][28][56]
DRP[7] bit 1	MAIN[0][29][56]
DRP[7] bit 2	MAIN[0][28][57]
DRP[7] bit 3	MAIN[0][29][57]
DRP[7] bit 4	MAIN[0][28][58]
DRP[7] bit 5	MAIN[0][29][58]
DRP[7] bit 6	MAIN[0][28][59]
DRP[7] bit 7	MAIN[0][29][59]
DRP[7] bit 8	MAIN[0][28][60]
DRP[7] bit 9	MAIN[0][29][60]
DRP[7] bit 10	MAIN[0][28][61]
DRP[7] bit 11	MAIN[0][29][61]
DRP[7] bit 12	MAIN[0][28][62]
DRP[7] bit 13	MAIN[0][29][62]
DRP[7] bit 14	MAIN[0][28][63]
DRP[7] bit 15	MAIN[0][29][63]
DRP[8] bit 0	MAIN[1][28][0]
DRP[8] bit 1	MAIN[1][29][0]
DRP[8] bit 2	MAIN[1][28][1]
DRP[8] bit 3	MAIN[1][29][1]
DRP[8] bit 4	MAIN[1][28][2]
DRP[8] bit 5	MAIN[1][29][2]
DRP[8] bit 6	MAIN[1][28][3]
DRP[8] bit 7	MAIN[1][29][3]
DRP[8] bit 8	MAIN[1][28][4]
DRP[8] bit 9	MAIN[1][29][4]
DRP[8] bit 10	MAIN[1][28][5]
DRP[8] bit 11	MAIN[1][29][5]
DRP[8] bit 12	MAIN[1][28][6]
DRP[8] bit 13	MAIN[1][29][6]
DRP[8] bit 14	MAIN[1][28][7]
DRP[8] bit 15	MAIN[1][29][7]
DRP[9] bit 0	MAIN[1][28][8]
DRP[9] bit 1	MAIN[1][29][8]
DRP[9] bit 2	MAIN[1][28][9]
DRP[9] bit 3	MAIN[1][29][9]
DRP[9] bit 4	MAIN[1][28][10]
DRP[9] bit 5	MAIN[1][29][10]
DRP[9] bit 6	MAIN[1][28][11]
DRP[9] bit 7	MAIN[1][29][11]
DRP[9] bit 8	MAIN[1][28][12]
DRP[9] bit 9	MAIN[1][29][12]
DRP[9] bit 10	MAIN[1][28][13]
DRP[9] bit 11	MAIN[1][29][13]
DRP[9] bit 12	MAIN[1][28][14]
DRP[9] bit 13	MAIN[1][29][14]
DRP[9] bit 14	MAIN[1][28][15]
DRP[9] bit 15	MAIN[1][29][15]
DRP[10] bit 0	MAIN[1][28][16]
DRP[10] bit 1	MAIN[1][29][16]
DRP[10] bit 2	MAIN[1][28][17]
DRP[10] bit 3	MAIN[1][29][17]
DRP[10] bit 4	MAIN[1][28][18]
DRP[10] bit 5	MAIN[1][29][18]
DRP[10] bit 6	MAIN[1][28][19]
DRP[10] bit 7	MAIN[1][29][19]
DRP[10] bit 8	MAIN[1][28][20]
DRP[10] bit 9	MAIN[1][29][20]
DRP[10] bit 10	MAIN[1][28][21]
DRP[10] bit 11	MAIN[1][29][21]
DRP[10] bit 12	MAIN[1][28][22]
DRP[10] bit 13	MAIN[1][29][22]
DRP[10] bit 14	MAIN[1][28][23]
DRP[10] bit 15	MAIN[1][29][23]
DRP[11] bit 0	MAIN[1][28][24]
DRP[11] bit 1	MAIN[1][29][24]
DRP[11] bit 2	MAIN[1][28][25]
DRP[11] bit 3	MAIN[1][29][25]
DRP[11] bit 4	MAIN[1][28][26]
DRP[11] bit 5	MAIN[1][29][26]
DRP[11] bit 6	MAIN[1][28][27]
DRP[11] bit 7	MAIN[1][29][27]
DRP[11] bit 8	MAIN[1][28][28]
DRP[11] bit 9	MAIN[1][29][28]
DRP[11] bit 10	MAIN[1][28][29]
DRP[11] bit 11	MAIN[1][29][29]
DRP[11] bit 12	MAIN[1][28][30]
DRP[11] bit 13	MAIN[1][29][30]
DRP[11] bit 14	MAIN[1][28][31]
DRP[11] bit 15	MAIN[1][29][31]
DRP[12] bit 0	MAIN[1][28][32]
DRP[12] bit 1	MAIN[1][29][32]
DRP[12] bit 2	MAIN[1][28][33]
DRP[12] bit 3	MAIN[1][29][33]
DRP[12] bit 4	MAIN[1][28][34]
DRP[12] bit 5	MAIN[1][29][34]
DRP[12] bit 6	MAIN[1][28][35]
DRP[12] bit 7	MAIN[1][29][35]
DRP[12] bit 8	MAIN[1][28][36]
DRP[12] bit 9	MAIN[1][29][36]
DRP[12] bit 10	MAIN[1][28][37]
DRP[12] bit 11	MAIN[1][29][37]
DRP[12] bit 12	MAIN[1][28][38]
DRP[12] bit 13	MAIN[1][29][38]
DRP[12] bit 14	MAIN[1][28][39]
DRP[12] bit 15	MAIN[1][29][39]
DRP[13] bit 0	MAIN[1][28][40]
DRP[13] bit 1	MAIN[1][29][40]
DRP[13] bit 2	MAIN[1][28][41]
DRP[13] bit 3	MAIN[1][29][41]
DRP[13] bit 4	MAIN[1][28][42]
DRP[13] bit 5	MAIN[1][29][42]
DRP[13] bit 6	MAIN[1][28][43]
DRP[13] bit 7	MAIN[1][29][43]
DRP[13] bit 8	MAIN[1][28][44]
DRP[13] bit 9	MAIN[1][29][44]
DRP[13] bit 10	MAIN[1][28][45]
DRP[13] bit 11	MAIN[1][29][45]
DRP[13] bit 12	MAIN[1][28][46]
DRP[13] bit 13	MAIN[1][29][46]
DRP[13] bit 14	MAIN[1][28][47]
DRP[13] bit 15	MAIN[1][29][47]
DRP[14] bit 0	MAIN[1][28][48]
DRP[14] bit 1	MAIN[1][29][48]
DRP[14] bit 2	MAIN[1][28][49]
DRP[14] bit 3	MAIN[1][29][49]
DRP[14] bit 4	MAIN[1][28][50]
DRP[14] bit 5	MAIN[1][29][50]
DRP[14] bit 6	MAIN[1][28][51]
DRP[14] bit 7	MAIN[1][29][51]
DRP[14] bit 8	MAIN[1][28][52]
DRP[14] bit 9	MAIN[1][29][52]
DRP[14] bit 10	MAIN[1][28][53]
DRP[14] bit 11	MAIN[1][29][53]
DRP[14] bit 12	MAIN[1][28][54]
DRP[14] bit 13	MAIN[1][29][54]
DRP[14] bit 14	MAIN[1][28][55]
DRP[14] bit 15	MAIN[1][29][55]
DRP[15] bit 0	MAIN[1][28][56]
DRP[15] bit 1	MAIN[1][29][56]
DRP[15] bit 2	MAIN[1][28][57]
DRP[15] bit 3	MAIN[1][29][57]
DRP[15] bit 4	MAIN[1][28][58]
DRP[15] bit 5	MAIN[1][29][58]
DRP[15] bit 6	MAIN[1][28][59]
DRP[15] bit 7	MAIN[1][29][59]
DRP[15] bit 8	MAIN[1][28][60]
DRP[15] bit 9	MAIN[1][29][60]
DRP[15] bit 10	MAIN[1][28][61]
DRP[15] bit 11	MAIN[1][29][61]
DRP[15] bit 12	MAIN[1][28][62]
DRP[15] bit 13	MAIN[1][29][62]
DRP[15] bit 14	MAIN[1][28][63]
DRP[15] bit 15	MAIN[1][29][63]
DRP[16] bit 0	MAIN[2][28][0]
DRP[16] bit 1	MAIN[2][29][0]
DRP[16] bit 2	MAIN[2][28][1]
DRP[16] bit 3	MAIN[2][29][1]
DRP[16] bit 4	MAIN[2][28][2]
DRP[16] bit 5	MAIN[2][29][2]
DRP[16] bit 6	MAIN[2][28][3]
DRP[16] bit 7	MAIN[2][29][3]
DRP[16] bit 8	MAIN[2][28][4]
DRP[16] bit 9	MAIN[2][29][4]
DRP[16] bit 10	MAIN[2][28][5]
DRP[16] bit 11	MAIN[2][29][5]
DRP[16] bit 12	MAIN[2][28][6]
DRP[16] bit 13	MAIN[2][29][6]
DRP[16] bit 14	MAIN[2][28][7]
DRP[16] bit 15	MAIN[2][29][7]
DRP[17] bit 0	MAIN[2][28][8]
DRP[17] bit 1	MAIN[2][29][8]
DRP[17] bit 2	MAIN[2][28][9]
DRP[17] bit 3	MAIN[2][29][9]
DRP[17] bit 4	MAIN[2][28][10]
DRP[17] bit 5	MAIN[2][29][10]
DRP[17] bit 6	MAIN[2][28][11]
DRP[17] bit 7	MAIN[2][29][11]
DRP[17] bit 8	MAIN[2][28][12]
DRP[17] bit 9	MAIN[2][29][12]
DRP[17] bit 10	MAIN[2][28][13]
DRP[17] bit 11	MAIN[2][29][13]
DRP[17] bit 12	MAIN[2][28][14]
DRP[17] bit 13	MAIN[2][29][14]
DRP[17] bit 14	MAIN[2][28][15]
DRP[17] bit 15	MAIN[2][29][15]
DRP[18] bit 0	MAIN[2][28][16]
DRP[18] bit 1	MAIN[2][29][16]
DRP[18] bit 2	MAIN[2][28][17]
DRP[18] bit 3	MAIN[2][29][17]
DRP[18] bit 4	MAIN[2][28][18]
DRP[18] bit 5	MAIN[2][29][18]
DRP[18] bit 6	MAIN[2][28][19]
DRP[18] bit 7	MAIN[2][29][19]
DRP[18] bit 8	MAIN[2][28][20]
DRP[18] bit 9	MAIN[2][29][20]
DRP[18] bit 10	MAIN[2][28][21]
DRP[18] bit 11	MAIN[2][29][21]
DRP[18] bit 12	MAIN[2][28][22]
DRP[18] bit 13	MAIN[2][29][22]
DRP[18] bit 14	MAIN[2][28][23]
DRP[18] bit 15	MAIN[2][29][23]
DRP[19] bit 0	MAIN[2][28][24]
DRP[19] bit 1	MAIN[2][29][24]
DRP[19] bit 2	MAIN[2][28][25]
DRP[19] bit 3	MAIN[2][29][25]
DRP[19] bit 4	MAIN[2][28][26]
DRP[19] bit 5	MAIN[2][29][26]
DRP[19] bit 6	MAIN[2][28][27]
DRP[19] bit 7	MAIN[2][29][27]
DRP[19] bit 8	MAIN[2][28][28]
DRP[19] bit 9	MAIN[2][29][28]
DRP[19] bit 10	MAIN[2][28][29]
DRP[19] bit 11	MAIN[2][29][29]
DRP[19] bit 12	MAIN[2][28][30]
DRP[19] bit 13	MAIN[2][29][30]
DRP[19] bit 14	MAIN[2][28][31]
DRP[19] bit 15	MAIN[2][29][31]
DRP[20] bit 0	MAIN[2][28][32]
DRP[20] bit 1	MAIN[2][29][32]
DRP[20] bit 2	MAIN[2][28][33]
DRP[20] bit 3	MAIN[2][29][33]
DRP[20] bit 4	MAIN[2][28][34]
DRP[20] bit 5	MAIN[2][29][34]
DRP[20] bit 6	MAIN[2][28][35]
DRP[20] bit 7	MAIN[2][29][35]
DRP[20] bit 8	MAIN[2][28][36]
DRP[20] bit 9	MAIN[2][29][36]
DRP[20] bit 10	MAIN[2][28][37]
DRP[20] bit 11	MAIN[2][29][37]
DRP[20] bit 12	MAIN[2][28][38]
DRP[20] bit 13	MAIN[2][29][38]
DRP[20] bit 14	MAIN[2][28][39]
DRP[20] bit 15	MAIN[2][29][39]
DRP[21] bit 0	MAIN[2][28][40]
DRP[21] bit 1	MAIN[2][29][40]
DRP[21] bit 2	MAIN[2][28][41]
DRP[21] bit 3	MAIN[2][29][41]
DRP[21] bit 4	MAIN[2][28][42]
DRP[21] bit 5	MAIN[2][29][42]
DRP[21] bit 6	MAIN[2][28][43]
DRP[21] bit 7	MAIN[2][29][43]
DRP[21] bit 8	MAIN[2][28][44]
DRP[21] bit 9	MAIN[2][29][44]
DRP[21] bit 10	MAIN[2][28][45]
DRP[21] bit 11	MAIN[2][29][45]
DRP[21] bit 12	MAIN[2][28][46]
DRP[21] bit 13	MAIN[2][29][46]
DRP[21] bit 14	MAIN[2][28][47]
DRP[21] bit 15	MAIN[2][29][47]
DRP[22] bit 0	MAIN[2][28][48]
DRP[22] bit 1	MAIN[2][29][48]
DRP[22] bit 2	MAIN[2][28][49]
DRP[22] bit 3	MAIN[2][29][49]
DRP[22] bit 4	MAIN[2][28][50]
DRP[22] bit 5	MAIN[2][29][50]
DRP[22] bit 6	MAIN[2][28][51]
DRP[22] bit 7	MAIN[2][29][51]
DRP[22] bit 8	MAIN[2][28][52]
DRP[22] bit 9	MAIN[2][29][52]
DRP[22] bit 10	MAIN[2][28][53]
DRP[22] bit 11	MAIN[2][29][53]
DRP[22] bit 12	MAIN[2][28][54]
DRP[22] bit 13	MAIN[2][29][54]
DRP[22] bit 14	MAIN[2][28][55]
DRP[22] bit 15	MAIN[2][29][55]
DRP[23] bit 0	MAIN[2][28][56]
DRP[23] bit 1	MAIN[2][29][56]
DRP[23] bit 2	MAIN[2][28][57]
DRP[23] bit 3	MAIN[2][29][57]
DRP[23] bit 4	MAIN[2][28][58]
DRP[23] bit 5	MAIN[2][29][58]
DRP[23] bit 6	MAIN[2][28][59]
DRP[23] bit 7	MAIN[2][29][59]
DRP[23] bit 8	MAIN[2][28][60]
DRP[23] bit 9	MAIN[2][29][60]
DRP[23] bit 10	MAIN[2][28][61]
DRP[23] bit 11	MAIN[2][29][61]
DRP[23] bit 12	MAIN[2][28][62]
DRP[23] bit 13	MAIN[2][29][62]
DRP[23] bit 14	MAIN[2][28][63]
DRP[23] bit 15	MAIN[2][29][63]
DRP[24] bit 0	MAIN[3][28][0]
DRP[24] bit 1	MAIN[3][29][0]
DRP[24] bit 2	MAIN[3][28][1]
DRP[24] bit 3	MAIN[3][29][1]
DRP[24] bit 4	MAIN[3][28][2]
DRP[24] bit 5	MAIN[3][29][2]
DRP[24] bit 6	MAIN[3][28][3]
DRP[24] bit 7	MAIN[3][29][3]
DRP[24] bit 8	MAIN[3][28][4]
DRP[24] bit 9	MAIN[3][29][4]
DRP[24] bit 10	MAIN[3][28][5]
DRP[24] bit 11	MAIN[3][29][5]
DRP[24] bit 12	MAIN[3][28][6]
DRP[24] bit 13	MAIN[3][29][6]
DRP[24] bit 14	MAIN[3][28][7]
DRP[24] bit 15	MAIN[3][29][7]
DRP[25] bit 0	MAIN[3][28][8]
DRP[25] bit 1	MAIN[3][29][8]
DRP[25] bit 2	MAIN[3][28][9]
DRP[25] bit 3	MAIN[3][29][9]
DRP[25] bit 4	MAIN[3][28][10]
DRP[25] bit 5	MAIN[3][29][10]
DRP[25] bit 6	MAIN[3][28][11]
DRP[25] bit 7	MAIN[3][29][11]
DRP[25] bit 8	MAIN[3][28][12]
DRP[25] bit 9	MAIN[3][29][12]
DRP[25] bit 10	MAIN[3][28][13]
DRP[25] bit 11	MAIN[3][29][13]
DRP[25] bit 12	MAIN[3][28][14]
DRP[25] bit 13	MAIN[3][29][14]
DRP[25] bit 14	MAIN[3][28][15]
DRP[25] bit 15	MAIN[3][29][15]
DRP[26] bit 0	MAIN[3][28][16]
DRP[26] bit 1	MAIN[3][29][16]
DRP[26] bit 2	MAIN[3][28][17]
DRP[26] bit 3	MAIN[3][29][17]
DRP[26] bit 4	MAIN[3][28][18]
DRP[26] bit 5	MAIN[3][29][18]
DRP[26] bit 6	MAIN[3][28][19]
DRP[26] bit 7	MAIN[3][29][19]
DRP[26] bit 8	MAIN[3][28][20]
DRP[26] bit 9	MAIN[3][29][20]
DRP[26] bit 10	MAIN[3][28][21]
DRP[26] bit 11	MAIN[3][29][21]
DRP[26] bit 12	MAIN[3][28][22]
DRP[26] bit 13	MAIN[3][29][22]
DRP[26] bit 14	MAIN[3][28][23]
DRP[26] bit 15	MAIN[3][29][23]
DRP[27] bit 0	MAIN[3][28][24]
DRP[27] bit 1	MAIN[3][29][24]
DRP[27] bit 2	MAIN[3][28][25]
DRP[27] bit 3	MAIN[3][29][25]
DRP[27] bit 4	MAIN[3][28][26]
DRP[27] bit 5	MAIN[3][29][26]
DRP[27] bit 6	MAIN[3][28][27]
DRP[27] bit 7	MAIN[3][29][27]
DRP[27] bit 8	MAIN[3][28][28]
DRP[27] bit 9	MAIN[3][29][28]
DRP[27] bit 10	MAIN[3][28][29]
DRP[27] bit 11	MAIN[3][29][29]
DRP[27] bit 12	MAIN[3][28][30]
DRP[27] bit 13	MAIN[3][29][30]
DRP[27] bit 14	MAIN[3][28][31]
DRP[27] bit 15	MAIN[3][29][31]
DRP[28] bit 0	MAIN[3][28][32]
DRP[28] bit 1	MAIN[3][29][32]
DRP[28] bit 2	MAIN[3][28][33]
DRP[28] bit 3	MAIN[3][29][33]
DRP[28] bit 4	MAIN[3][28][34]
DRP[28] bit 5	MAIN[3][29][34]
DRP[28] bit 6	MAIN[3][28][35]
DRP[28] bit 7	MAIN[3][29][35]
DRP[28] bit 8	MAIN[3][28][36]
DRP[28] bit 9	MAIN[3][29][36]
DRP[28] bit 10	MAIN[3][28][37]
DRP[28] bit 11	MAIN[3][29][37]
DRP[28] bit 12	MAIN[3][28][38]
DRP[28] bit 13	MAIN[3][29][38]
DRP[28] bit 14	MAIN[3][28][39]
DRP[28] bit 15	MAIN[3][29][39]
DRP[29] bit 0	MAIN[3][28][40]
DRP[29] bit 1	MAIN[3][29][40]
DRP[29] bit 2	MAIN[3][28][41]
DRP[29] bit 3	MAIN[3][29][41]
DRP[29] bit 4	MAIN[3][28][42]
DRP[29] bit 5	MAIN[3][29][42]
DRP[29] bit 6	MAIN[3][28][43]
DRP[29] bit 7	MAIN[3][29][43]
DRP[29] bit 8	MAIN[3][28][44]
DRP[29] bit 9	MAIN[3][29][44]
DRP[29] bit 10	MAIN[3][28][45]
DRP[29] bit 11	MAIN[3][29][45]
DRP[29] bit 12	MAIN[3][28][46]
DRP[29] bit 13	MAIN[3][29][46]
DRP[29] bit 14	MAIN[3][28][47]
DRP[29] bit 15	MAIN[3][29][47]
DRP[30] bit 0	MAIN[3][28][48]
DRP[30] bit 1	MAIN[3][29][48]
DRP[30] bit 2	MAIN[3][28][49]
DRP[30] bit 3	MAIN[3][29][49]
DRP[30] bit 4	MAIN[3][28][50]
DRP[30] bit 5	MAIN[3][29][50]
DRP[30] bit 6	MAIN[3][28][51]
DRP[30] bit 7	MAIN[3][29][51]
DRP[30] bit 8	MAIN[3][28][52]
DRP[30] bit 9	MAIN[3][29][52]
DRP[30] bit 10	MAIN[3][28][53]
DRP[30] bit 11	MAIN[3][29][53]
DRP[30] bit 12	MAIN[3][28][54]
DRP[30] bit 13	MAIN[3][29][54]
DRP[30] bit 14	MAIN[3][28][55]
DRP[30] bit 15	MAIN[3][29][55]
DRP[31] bit 0	MAIN[3][28][56]
DRP[31] bit 1	MAIN[3][29][56]
DRP[31] bit 2	MAIN[3][28][57]
DRP[31] bit 3	MAIN[3][29][57]
DRP[31] bit 4	MAIN[3][28][58]
DRP[31] bit 5	MAIN[3][29][58]
DRP[31] bit 6	MAIN[3][28][59]
DRP[31] bit 7	MAIN[3][29][59]
DRP[31] bit 8	MAIN[3][28][60]
DRP[31] bit 9	MAIN[3][29][60]
DRP[31] bit 10	MAIN[3][28][61]
DRP[31] bit 11	MAIN[3][29][61]
DRP[31] bit 12	MAIN[3][28][62]
DRP[31] bit 13	MAIN[3][29][62]
DRP[31] bit 14	MAIN[3][28][63]
DRP[31] bit 15	MAIN[3][29][63]
DRP[32] bit 0	MAIN[4][28][0]
DRP[32] bit 1	MAIN[4][29][0]
DRP[32] bit 2	MAIN[4][28][1]
DRP[32] bit 3	MAIN[4][29][1]
DRP[32] bit 4	MAIN[4][28][2]
DRP[32] bit 5	MAIN[4][29][2]
DRP[32] bit 6	MAIN[4][28][3]
DRP[32] bit 7	MAIN[4][29][3]
DRP[32] bit 8	MAIN[4][28][4]
DRP[32] bit 9	MAIN[4][29][4]
DRP[32] bit 10	MAIN[4][28][5]
DRP[32] bit 11	MAIN[4][29][5]
DRP[32] bit 12	MAIN[4][28][6]
DRP[32] bit 13	MAIN[4][29][6]
DRP[32] bit 14	MAIN[4][28][7]
DRP[32] bit 15	MAIN[4][29][7]
DRP[33] bit 0	MAIN[4][28][8]
DRP[33] bit 1	MAIN[4][29][8]
DRP[33] bit 2	MAIN[4][28][9]
DRP[33] bit 3	MAIN[4][29][9]
DRP[33] bit 4	MAIN[4][28][10]
DRP[33] bit 5	MAIN[4][29][10]
DRP[33] bit 6	MAIN[4][28][11]
DRP[33] bit 7	MAIN[4][29][11]
DRP[33] bit 8	MAIN[4][28][12]
DRP[33] bit 9	MAIN[4][29][12]
DRP[33] bit 10	MAIN[4][28][13]
DRP[33] bit 11	MAIN[4][29][13]
DRP[33] bit 12	MAIN[4][28][14]
DRP[33] bit 13	MAIN[4][29][14]
DRP[33] bit 14	MAIN[4][28][15]
DRP[33] bit 15	MAIN[4][29][15]
DRP[34] bit 0	MAIN[4][28][16]
DRP[34] bit 1	MAIN[4][29][16]
DRP[34] bit 2	MAIN[4][28][17]
DRP[34] bit 3	MAIN[4][29][17]
DRP[34] bit 4	MAIN[4][28][18]
DRP[34] bit 5	MAIN[4][29][18]
DRP[34] bit 6	MAIN[4][28][19]
DRP[34] bit 7	MAIN[4][29][19]
DRP[34] bit 8	MAIN[4][28][20]
DRP[34] bit 9	MAIN[4][29][20]
DRP[34] bit 10	MAIN[4][28][21]
DRP[34] bit 11	MAIN[4][29][21]
DRP[34] bit 12	MAIN[4][28][22]
DRP[34] bit 13	MAIN[4][29][22]
DRP[34] bit 14	MAIN[4][28][23]
DRP[34] bit 15	MAIN[4][29][23]
DRP[35] bit 0	MAIN[4][28][24]
DRP[35] bit 1	MAIN[4][29][24]
DRP[35] bit 2	MAIN[4][28][25]
DRP[35] bit 3	MAIN[4][29][25]
DRP[35] bit 4	MAIN[4][28][26]
DRP[35] bit 5	MAIN[4][29][26]
DRP[35] bit 6	MAIN[4][28][27]
DRP[35] bit 7	MAIN[4][29][27]
DRP[35] bit 8	MAIN[4][28][28]
DRP[35] bit 9	MAIN[4][29][28]
DRP[35] bit 10	MAIN[4][28][29]
DRP[35] bit 11	MAIN[4][29][29]
DRP[35] bit 12	MAIN[4][28][30]
DRP[35] bit 13	MAIN[4][29][30]
DRP[35] bit 14	MAIN[4][28][31]
DRP[35] bit 15	MAIN[4][29][31]
DRP[36] bit 0	MAIN[4][28][32]
DRP[36] bit 1	MAIN[4][29][32]
DRP[36] bit 2	MAIN[4][28][33]
DRP[36] bit 3	MAIN[4][29][33]
DRP[36] bit 4	MAIN[4][28][34]
DRP[36] bit 5	MAIN[4][29][34]
DRP[36] bit 6	MAIN[4][28][35]
DRP[36] bit 7	MAIN[4][29][35]
DRP[36] bit 8	MAIN[4][28][36]
DRP[36] bit 9	MAIN[4][29][36]
DRP[36] bit 10	MAIN[4][28][37]
DRP[36] bit 11	MAIN[4][29][37]
DRP[36] bit 12	MAIN[4][28][38]
DRP[36] bit 13	MAIN[4][29][38]
DRP[36] bit 14	MAIN[4][28][39]
DRP[36] bit 15	MAIN[4][29][39]
DRP[37] bit 0	MAIN[4][28][40]
DRP[37] bit 1	MAIN[4][29][40]
DRP[37] bit 2	MAIN[4][28][41]
DRP[37] bit 3	MAIN[4][29][41]
DRP[37] bit 4	MAIN[4][28][42]
DRP[37] bit 5	MAIN[4][29][42]
DRP[37] bit 6	MAIN[4][28][43]
DRP[37] bit 7	MAIN[4][29][43]
DRP[37] bit 8	MAIN[4][28][44]
DRP[37] bit 9	MAIN[4][29][44]
DRP[37] bit 10	MAIN[4][28][45]
DRP[37] bit 11	MAIN[4][29][45]
DRP[37] bit 12	MAIN[4][28][46]
DRP[37] bit 13	MAIN[4][29][46]
DRP[37] bit 14	MAIN[4][28][47]
DRP[37] bit 15	MAIN[4][29][47]
DRP[38] bit 0	MAIN[4][28][48]
DRP[38] bit 1	MAIN[4][29][48]
DRP[38] bit 2	MAIN[4][28][49]
DRP[38] bit 3	MAIN[4][29][49]
DRP[38] bit 4	MAIN[4][28][50]
DRP[38] bit 5	MAIN[4][29][50]
DRP[38] bit 6	MAIN[4][28][51]
DRP[38] bit 7	MAIN[4][29][51]
DRP[38] bit 8	MAIN[4][28][52]
DRP[38] bit 9	MAIN[4][29][52]
DRP[38] bit 10	MAIN[4][28][53]
DRP[38] bit 11	MAIN[4][29][53]
DRP[38] bit 12	MAIN[4][28][54]
DRP[38] bit 13	MAIN[4][29][54]
DRP[38] bit 14	MAIN[4][28][55]
DRP[38] bit 15	MAIN[4][29][55]
DRP[39] bit 0	MAIN[4][28][56]
DRP[39] bit 1	MAIN[4][29][56]
DRP[39] bit 2	MAIN[4][28][57]
DRP[39] bit 3	MAIN[4][29][57]
DRP[39] bit 4	MAIN[4][28][58]
DRP[39] bit 5	MAIN[4][29][58]
DRP[39] bit 6	MAIN[4][28][59]
DRP[39] bit 7	MAIN[4][29][59]
DRP[39] bit 8	MAIN[4][28][60]
DRP[39] bit 9	MAIN[4][29][60]
DRP[39] bit 10	MAIN[4][28][61]
DRP[39] bit 11	MAIN[4][29][61]
DRP[39] bit 12	MAIN[4][28][62]
DRP[39] bit 13	MAIN[4][29][62]
DRP[39] bit 14	MAIN[4][28][63]
DRP[39] bit 15	MAIN[4][29][63]
DRP[40] bit 0	MAIN[5][28][0]
DRP[40] bit 1	MAIN[5][29][0]
DRP[40] bit 2	MAIN[5][28][1]
DRP[40] bit 3	MAIN[5][29][1]
DRP[40] bit 4	MAIN[5][28][2]
DRP[40] bit 5	MAIN[5][29][2]
DRP[40] bit 6	MAIN[5][28][3]
DRP[40] bit 7	MAIN[5][29][3]
DRP[40] bit 8	MAIN[5][28][4]
DRP[40] bit 9	MAIN[5][29][4]
DRP[40] bit 10	MAIN[5][28][5]
DRP[40] bit 11	MAIN[5][29][5]
DRP[40] bit 12	MAIN[5][28][6]
DRP[40] bit 13	MAIN[5][29][6]
DRP[40] bit 14	MAIN[5][28][7]
DRP[40] bit 15	MAIN[5][29][7]
DRP[41] bit 0	MAIN[5][28][8]
DRP[41] bit 1	MAIN[5][29][8]
DRP[41] bit 2	MAIN[5][28][9]
DRP[41] bit 3	MAIN[5][29][9]
DRP[41] bit 4	MAIN[5][28][10]
DRP[41] bit 5	MAIN[5][29][10]
DRP[41] bit 6	MAIN[5][28][11]
DRP[41] bit 7	MAIN[5][29][11]
DRP[41] bit 8	MAIN[5][28][12]
DRP[41] bit 9	MAIN[5][29][12]
DRP[41] bit 10	MAIN[5][28][13]
DRP[41] bit 11	MAIN[5][29][13]
DRP[41] bit 12	MAIN[5][28][14]
DRP[41] bit 13	MAIN[5][29][14]
DRP[41] bit 14	MAIN[5][28][15]
DRP[41] bit 15	MAIN[5][29][15]
DRP[42] bit 0	MAIN[5][28][16]
DRP[42] bit 1	MAIN[5][29][16]
DRP[42] bit 2	MAIN[5][28][17]
DRP[42] bit 3	MAIN[5][29][17]
DRP[42] bit 4	MAIN[5][28][18]
DRP[42] bit 5	MAIN[5][29][18]
DRP[42] bit 6	MAIN[5][28][19]
DRP[42] bit 7	MAIN[5][29][19]
DRP[42] bit 8	MAIN[5][28][20]
DRP[42] bit 9	MAIN[5][29][20]
DRP[42] bit 10	MAIN[5][28][21]
DRP[42] bit 11	MAIN[5][29][21]
DRP[42] bit 12	MAIN[5][28][22]
DRP[42] bit 13	MAIN[5][29][22]
DRP[42] bit 14	MAIN[5][28][23]
DRP[42] bit 15	MAIN[5][29][23]
DRP[43] bit 0	MAIN[5][28][24]
DRP[43] bit 1	MAIN[5][29][24]
DRP[43] bit 2	MAIN[5][28][25]
DRP[43] bit 3	MAIN[5][29][25]
DRP[43] bit 4	MAIN[5][28][26]
DRP[43] bit 5	MAIN[5][29][26]
DRP[43] bit 6	MAIN[5][28][27]
DRP[43] bit 7	MAIN[5][29][27]
DRP[43] bit 8	MAIN[5][28][28]
DRP[43] bit 9	MAIN[5][29][28]
DRP[43] bit 10	MAIN[5][28][29]
DRP[43] bit 11	MAIN[5][29][29]
DRP[43] bit 12	MAIN[5][28][30]
DRP[43] bit 13	MAIN[5][29][30]
DRP[43] bit 14	MAIN[5][28][31]
DRP[43] bit 15	MAIN[5][29][31]
DRP[44] bit 0	MAIN[5][28][32]
DRP[44] bit 1	MAIN[5][29][32]
DRP[44] bit 2	MAIN[5][28][33]
DRP[44] bit 3	MAIN[5][29][33]
DRP[44] bit 4	MAIN[5][28][34]
DRP[44] bit 5	MAIN[5][29][34]
DRP[44] bit 6	MAIN[5][28][35]
DRP[44] bit 7	MAIN[5][29][35]
DRP[44] bit 8	MAIN[5][28][36]
DRP[44] bit 9	MAIN[5][29][36]
DRP[44] bit 10	MAIN[5][28][37]
DRP[44] bit 11	MAIN[5][29][37]
DRP[44] bit 12	MAIN[5][28][38]
DRP[44] bit 13	MAIN[5][29][38]
DRP[44] bit 14	MAIN[5][28][39]
DRP[44] bit 15	MAIN[5][29][39]
DRP[45] bit 0	MAIN[5][28][40]
DRP[45] bit 1	MAIN[5][29][40]
DRP[45] bit 2	MAIN[5][28][41]
DRP[45] bit 3	MAIN[5][29][41]
DRP[45] bit 4	MAIN[5][28][42]
DRP[45] bit 5	MAIN[5][29][42]
DRP[45] bit 6	MAIN[5][28][43]
DRP[45] bit 7	MAIN[5][29][43]
DRP[45] bit 8	MAIN[5][28][44]
DRP[45] bit 9	MAIN[5][29][44]
DRP[45] bit 10	MAIN[5][28][45]
DRP[45] bit 11	MAIN[5][29][45]
DRP[45] bit 12	MAIN[5][28][46]
DRP[45] bit 13	MAIN[5][29][46]
DRP[45] bit 14	MAIN[5][28][47]
DRP[45] bit 15	MAIN[5][29][47]
DRP[46] bit 0	MAIN[5][28][48]
DRP[46] bit 1	MAIN[5][29][48]
DRP[46] bit 2	MAIN[5][28][49]
DRP[46] bit 3	MAIN[5][29][49]
DRP[46] bit 4	MAIN[5][28][50]
DRP[46] bit 5	MAIN[5][29][50]
DRP[46] bit 6	MAIN[5][28][51]
DRP[46] bit 7	MAIN[5][29][51]
DRP[46] bit 8	MAIN[5][28][52]
DRP[46] bit 9	MAIN[5][29][52]
DRP[46] bit 10	MAIN[5][28][53]
DRP[46] bit 11	MAIN[5][29][53]
DRP[46] bit 12	MAIN[5][28][54]
DRP[46] bit 13	MAIN[5][29][54]
DRP[46] bit 14	MAIN[5][28][55]
DRP[46] bit 15	MAIN[5][29][55]
DRP[47] bit 0	MAIN[5][28][56]
DRP[47] bit 1	MAIN[5][29][56]
DRP[47] bit 2	MAIN[5][28][57]
DRP[47] bit 3	MAIN[5][29][57]
DRP[47] bit 4	MAIN[5][28][58]
DRP[47] bit 5	MAIN[5][29][58]
DRP[47] bit 6	MAIN[5][28][59]
DRP[47] bit 7	MAIN[5][29][59]
DRP[47] bit 8	MAIN[5][28][60]
DRP[47] bit 9	MAIN[5][29][60]
DRP[47] bit 10	MAIN[5][28][61]
DRP[47] bit 11	MAIN[5][29][61]
DRP[47] bit 12	MAIN[5][28][62]
DRP[47] bit 13	MAIN[5][29][62]
DRP[47] bit 14	MAIN[5][28][63]
DRP[47] bit 15	MAIN[5][29][63]
DRP[48] bit 0	MAIN[0][30][0]
DRP[48] bit 1	MAIN[0][31][0]
DRP[48] bit 2	MAIN[0][30][1]
DRP[48] bit 3	MAIN[0][31][1]
DRP[48] bit 4	MAIN[0][30][2]
DRP[48] bit 5	MAIN[0][31][2]
DRP[48] bit 6	MAIN[0][30][3]
DRP[48] bit 7	MAIN[0][31][3]
DRP[48] bit 8	MAIN[0][30][4]
DRP[48] bit 9	MAIN[0][31][4]
DRP[48] bit 10	MAIN[0][30][5]
DRP[48] bit 11	MAIN[0][31][5]
DRP[48] bit 12	MAIN[0][30][6]
DRP[48] bit 13	MAIN[0][31][6]
DRP[48] bit 14	MAIN[0][30][7]
DRP[48] bit 15	MAIN[0][31][7]
DRP[49] bit 0	MAIN[0][30][8]
DRP[49] bit 1	MAIN[0][31][8]
DRP[49] bit 2	MAIN[0][30][9]
DRP[49] bit 3	MAIN[0][31][9]
DRP[49] bit 4	MAIN[0][30][10]
DRP[49] bit 5	MAIN[0][31][10]
DRP[49] bit 6	MAIN[0][30][11]
DRP[49] bit 7	MAIN[0][31][11]
DRP[49] bit 8	MAIN[0][30][12]
DRP[49] bit 9	MAIN[0][31][12]
DRP[49] bit 10	MAIN[0][30][13]
DRP[49] bit 11	MAIN[0][31][13]
DRP[49] bit 12	MAIN[0][30][14]
DRP[49] bit 13	MAIN[0][31][14]
DRP[49] bit 14	MAIN[0][30][15]
DRP[49] bit 15	MAIN[0][31][15]
DRP[50] bit 0	MAIN[0][30][16]
DRP[50] bit 1	MAIN[0][31][16]
DRP[50] bit 2	MAIN[0][30][17]
DRP[50] bit 3	MAIN[0][31][17]
DRP[50] bit 4	MAIN[0][30][18]
DRP[50] bit 5	MAIN[0][31][18]
DRP[50] bit 6	MAIN[0][30][19]
DRP[50] bit 7	MAIN[0][31][19]
DRP[50] bit 8	MAIN[0][30][20]
DRP[50] bit 9	MAIN[0][31][20]
DRP[50] bit 10	MAIN[0][30][21]
DRP[50] bit 11	MAIN[0][31][21]
DRP[50] bit 12	MAIN[0][30][22]
DRP[50] bit 13	MAIN[0][31][22]
DRP[50] bit 14	MAIN[0][30][23]
DRP[50] bit 15	MAIN[0][31][23]
DRP[51] bit 0	MAIN[0][30][24]
DRP[51] bit 1	MAIN[0][31][24]
DRP[51] bit 2	MAIN[0][30][25]
DRP[51] bit 3	MAIN[0][31][25]
DRP[51] bit 4	MAIN[0][30][26]
DRP[51] bit 5	MAIN[0][31][26]
DRP[51] bit 6	MAIN[0][30][27]
DRP[51] bit 7	MAIN[0][31][27]
DRP[51] bit 8	MAIN[0][30][28]
DRP[51] bit 9	MAIN[0][31][28]
DRP[51] bit 10	MAIN[0][30][29]
DRP[51] bit 11	MAIN[0][31][29]
DRP[51] bit 12	MAIN[0][30][30]
DRP[51] bit 13	MAIN[0][31][30]
DRP[51] bit 14	MAIN[0][30][31]
DRP[51] bit 15	MAIN[0][31][31]
DRP[52] bit 0	MAIN[0][30][32]
DRP[52] bit 1	MAIN[0][31][32]
DRP[52] bit 2	MAIN[0][30][33]
DRP[52] bit 3	MAIN[0][31][33]
DRP[52] bit 4	MAIN[0][30][34]
DRP[52] bit 5	MAIN[0][31][34]
DRP[52] bit 6	MAIN[0][30][35]
DRP[52] bit 7	MAIN[0][31][35]
DRP[52] bit 8	MAIN[0][30][36]
DRP[52] bit 9	MAIN[0][31][36]
DRP[52] bit 10	MAIN[0][30][37]
DRP[52] bit 11	MAIN[0][31][37]
DRP[52] bit 12	MAIN[0][30][38]
DRP[52] bit 13	MAIN[0][31][38]
DRP[52] bit 14	MAIN[0][30][39]
DRP[52] bit 15	MAIN[0][31][39]
DRP[53] bit 0	MAIN[0][30][40]
DRP[53] bit 1	MAIN[0][31][40]
DRP[53] bit 2	MAIN[0][30][41]
DRP[53] bit 3	MAIN[0][31][41]
DRP[53] bit 4	MAIN[0][30][42]
DRP[53] bit 5	MAIN[0][31][42]
DRP[53] bit 6	MAIN[0][30][43]
DRP[53] bit 7	MAIN[0][31][43]
DRP[53] bit 8	MAIN[0][30][44]
DRP[53] bit 9	MAIN[0][31][44]
DRP[53] bit 10	MAIN[0][30][45]
DRP[53] bit 11	MAIN[0][31][45]
DRP[53] bit 12	MAIN[0][30][46]
DRP[53] bit 13	MAIN[0][31][46]
DRP[53] bit 14	MAIN[0][30][47]
DRP[53] bit 15	MAIN[0][31][47]
DRP[54] bit 0	MAIN[0][30][48]
DRP[54] bit 1	MAIN[0][31][48]
DRP[54] bit 2	MAIN[0][30][49]
DRP[54] bit 3	MAIN[0][31][49]
DRP[54] bit 4	MAIN[0][30][50]
DRP[54] bit 5	MAIN[0][31][50]
DRP[54] bit 6	MAIN[0][30][51]
DRP[54] bit 7	MAIN[0][31][51]
DRP[54] bit 8	MAIN[0][30][52]
DRP[54] bit 9	MAIN[0][31][52]
DRP[54] bit 10	MAIN[0][30][53]
DRP[54] bit 11	MAIN[0][31][53]
DRP[54] bit 12	MAIN[0][30][54]
DRP[54] bit 13	MAIN[0][31][54]
DRP[54] bit 14	MAIN[0][30][55]
DRP[54] bit 15	MAIN[0][31][55]
DRP[55] bit 0	MAIN[0][30][56]
DRP[55] bit 1	MAIN[0][31][56]
DRP[55] bit 2	MAIN[0][30][57]
DRP[55] bit 3	MAIN[0][31][57]
DRP[55] bit 4	MAIN[0][30][58]
DRP[55] bit 5	MAIN[0][31][58]
DRP[55] bit 6	MAIN[0][30][59]
DRP[55] bit 7	MAIN[0][31][59]
DRP[55] bit 8	MAIN[0][30][60]
DRP[55] bit 9	MAIN[0][31][60]
DRP[55] bit 10	MAIN[0][30][61]
DRP[55] bit 11	MAIN[0][31][61]
DRP[55] bit 12	MAIN[0][30][62]
DRP[55] bit 13	MAIN[0][31][62]
DRP[55] bit 14	MAIN[0][30][63]
DRP[55] bit 15	MAIN[0][31][63]
DRP[56] bit 0	MAIN[1][30][0]
DRP[56] bit 1	MAIN[1][31][0]
DRP[56] bit 2	MAIN[1][30][1]
DRP[56] bit 3	MAIN[1][31][1]
DRP[56] bit 4	MAIN[1][30][2]
DRP[56] bit 5	MAIN[1][31][2]
DRP[56] bit 6	MAIN[1][30][3]
DRP[56] bit 7	MAIN[1][31][3]
DRP[56] bit 8	MAIN[1][30][4]
DRP[56] bit 9	MAIN[1][31][4]
DRP[56] bit 10	MAIN[1][30][5]
DRP[56] bit 11	MAIN[1][31][5]
DRP[56] bit 12	MAIN[1][30][6]
DRP[56] bit 13	MAIN[1][31][6]
DRP[56] bit 14	MAIN[1][30][7]
DRP[56] bit 15	MAIN[1][31][7]
DRP[57] bit 0	MAIN[1][30][8]
DRP[57] bit 1	MAIN[1][31][8]
DRP[57] bit 2	MAIN[1][30][9]
DRP[57] bit 3	MAIN[1][31][9]
DRP[57] bit 4	MAIN[1][30][10]
DRP[57] bit 5	MAIN[1][31][10]
DRP[57] bit 6	MAIN[1][30][11]
DRP[57] bit 7	MAIN[1][31][11]
DRP[57] bit 8	MAIN[1][30][12]
DRP[57] bit 9	MAIN[1][31][12]
DRP[57] bit 10	MAIN[1][30][13]
DRP[57] bit 11	MAIN[1][31][13]
DRP[57] bit 12	MAIN[1][30][14]
DRP[57] bit 13	MAIN[1][31][14]
DRP[57] bit 14	MAIN[1][30][15]
DRP[57] bit 15	MAIN[1][31][15]
DRP[58] bit 0	MAIN[1][30][16]
DRP[58] bit 1	MAIN[1][31][16]
DRP[58] bit 2	MAIN[1][30][17]
DRP[58] bit 3	MAIN[1][31][17]
DRP[58] bit 4	MAIN[1][30][18]
DRP[58] bit 5	MAIN[1][31][18]
DRP[58] bit 6	MAIN[1][30][19]
DRP[58] bit 7	MAIN[1][31][19]
DRP[58] bit 8	MAIN[1][30][20]
DRP[58] bit 9	MAIN[1][31][20]
DRP[58] bit 10	MAIN[1][30][21]
DRP[58] bit 11	MAIN[1][31][21]
DRP[58] bit 12	MAIN[1][30][22]
DRP[58] bit 13	MAIN[1][31][22]
DRP[58] bit 14	MAIN[1][30][23]
DRP[58] bit 15	MAIN[1][31][23]
DRP[59] bit 0	MAIN[1][30][24]
DRP[59] bit 1	MAIN[1][31][24]
DRP[59] bit 2	MAIN[1][30][25]
DRP[59] bit 3	MAIN[1][31][25]
DRP[59] bit 4	MAIN[1][30][26]
DRP[59] bit 5	MAIN[1][31][26]
DRP[59] bit 6	MAIN[1][30][27]
DRP[59] bit 7	MAIN[1][31][27]
DRP[59] bit 8	MAIN[1][30][28]
DRP[59] bit 9	MAIN[1][31][28]
DRP[59] bit 10	MAIN[1][30][29]
DRP[59] bit 11	MAIN[1][31][29]
DRP[59] bit 12	MAIN[1][30][30]
DRP[59] bit 13	MAIN[1][31][30]
DRP[59] bit 14	MAIN[1][30][31]
DRP[59] bit 15	MAIN[1][31][31]
DRP[60] bit 0	MAIN[1][30][32]
DRP[60] bit 1	MAIN[1][31][32]
DRP[60] bit 2	MAIN[1][30][33]
DRP[60] bit 3	MAIN[1][31][33]
DRP[60] bit 4	MAIN[1][30][34]
DRP[60] bit 5	MAIN[1][31][34]
DRP[60] bit 6	MAIN[1][30][35]
DRP[60] bit 7	MAIN[1][31][35]
DRP[60] bit 8	MAIN[1][30][36]
DRP[60] bit 9	MAIN[1][31][36]
DRP[60] bit 10	MAIN[1][30][37]
DRP[60] bit 11	MAIN[1][31][37]
DRP[60] bit 12	MAIN[1][30][38]
DRP[60] bit 13	MAIN[1][31][38]
DRP[60] bit 14	MAIN[1][30][39]
DRP[60] bit 15	MAIN[1][31][39]
DRP[61] bit 0	MAIN[1][30][40]
DRP[61] bit 1	MAIN[1][31][40]
DRP[61] bit 2	MAIN[1][30][41]
DRP[61] bit 3	MAIN[1][31][41]
DRP[61] bit 4	MAIN[1][30][42]
DRP[61] bit 5	MAIN[1][31][42]
DRP[61] bit 6	MAIN[1][30][43]
DRP[61] bit 7	MAIN[1][31][43]
DRP[61] bit 8	MAIN[1][30][44]
DRP[61] bit 9	MAIN[1][31][44]
DRP[61] bit 10	MAIN[1][30][45]
DRP[61] bit 11	MAIN[1][31][45]
DRP[61] bit 12	MAIN[1][30][46]
DRP[61] bit 13	MAIN[1][31][46]
DRP[61] bit 14	MAIN[1][30][47]
DRP[61] bit 15	MAIN[1][31][47]
DRP[62] bit 0	MAIN[1][30][48]
DRP[62] bit 1	MAIN[1][31][48]
DRP[62] bit 2	MAIN[1][30][49]
DRP[62] bit 3	MAIN[1][31][49]
DRP[62] bit 4	MAIN[1][30][50]
DRP[62] bit 5	MAIN[1][31][50]
DRP[62] bit 6	MAIN[1][30][51]
DRP[62] bit 7	MAIN[1][31][51]
DRP[62] bit 8	MAIN[1][30][52]
DRP[62] bit 9	MAIN[1][31][52]
DRP[62] bit 10	MAIN[1][30][53]
DRP[62] bit 11	MAIN[1][31][53]
DRP[62] bit 12	MAIN[1][30][54]
DRP[62] bit 13	MAIN[1][31][54]
DRP[62] bit 14	MAIN[1][30][55]
DRP[62] bit 15	MAIN[1][31][55]
DRP[63] bit 0	MAIN[1][30][56]
DRP[63] bit 1	MAIN[1][31][56]
DRP[63] bit 2	MAIN[1][30][57]
DRP[63] bit 3	MAIN[1][31][57]
DRP[63] bit 4	MAIN[1][30][58]
DRP[63] bit 5	MAIN[1][31][58]
DRP[63] bit 6	MAIN[1][30][59]
DRP[63] bit 7	MAIN[1][31][59]
DRP[63] bit 8	MAIN[1][30][60]
DRP[63] bit 9	MAIN[1][31][60]
DRP[63] bit 10	MAIN[1][30][61]
DRP[63] bit 11	MAIN[1][31][61]
DRP[63] bit 12	MAIN[1][30][62]
DRP[63] bit 13	MAIN[1][31][62]
DRP[63] bit 14	MAIN[1][30][63]
DRP[63] bit 15	MAIN[1][31][63]
DRP[64] bit 0	MAIN[2][30][0]
DRP[64] bit 1	MAIN[2][31][0]
DRP[64] bit 2	MAIN[2][30][1]
DRP[64] bit 3	MAIN[2][31][1]
DRP[64] bit 4	MAIN[2][30][2]
DRP[64] bit 5	MAIN[2][31][2]
DRP[64] bit 6	MAIN[2][30][3]
DRP[64] bit 7	MAIN[2][31][3]
DRP[64] bit 8	MAIN[2][30][4]
DRP[64] bit 9	MAIN[2][31][4]
DRP[64] bit 10	MAIN[2][30][5]
DRP[64] bit 11	MAIN[2][31][5]
DRP[64] bit 12	MAIN[2][30][6]
DRP[64] bit 13	MAIN[2][31][6]
DRP[64] bit 14	MAIN[2][30][7]
DRP[64] bit 15	MAIN[2][31][7]
DRP[65] bit 0	MAIN[2][30][8]
DRP[65] bit 1	MAIN[2][31][8]
DRP[65] bit 2	MAIN[2][30][9]
DRP[65] bit 3	MAIN[2][31][9]
DRP[65] bit 4	MAIN[2][30][10]
DRP[65] bit 5	MAIN[2][31][10]
DRP[65] bit 6	MAIN[2][30][11]
DRP[65] bit 7	MAIN[2][31][11]
DRP[65] bit 8	MAIN[2][30][12]
DRP[65] bit 9	MAIN[2][31][12]
DRP[65] bit 10	MAIN[2][30][13]
DRP[65] bit 11	MAIN[2][31][13]
DRP[65] bit 12	MAIN[2][30][14]
DRP[65] bit 13	MAIN[2][31][14]
DRP[65] bit 14	MAIN[2][30][15]
DRP[65] bit 15	MAIN[2][31][15]
DRP[66] bit 0	MAIN[2][30][16]
DRP[66] bit 1	MAIN[2][31][16]
DRP[66] bit 2	MAIN[2][30][17]
DRP[66] bit 3	MAIN[2][31][17]
DRP[66] bit 4	MAIN[2][30][18]
DRP[66] bit 5	MAIN[2][31][18]
DRP[66] bit 6	MAIN[2][30][19]
DRP[66] bit 7	MAIN[2][31][19]
DRP[66] bit 8	MAIN[2][30][20]
DRP[66] bit 9	MAIN[2][31][20]
DRP[66] bit 10	MAIN[2][30][21]
DRP[66] bit 11	MAIN[2][31][21]
DRP[66] bit 12	MAIN[2][30][22]
DRP[66] bit 13	MAIN[2][31][22]
DRP[66] bit 14	MAIN[2][30][23]
DRP[66] bit 15	MAIN[2][31][23]
DRP[67] bit 0	MAIN[2][30][24]
DRP[67] bit 1	MAIN[2][31][24]
DRP[67] bit 2	MAIN[2][30][25]
DRP[67] bit 3	MAIN[2][31][25]
DRP[67] bit 4	MAIN[2][30][26]
DRP[67] bit 5	MAIN[2][31][26]
DRP[67] bit 6	MAIN[2][30][27]
DRP[67] bit 7	MAIN[2][31][27]
DRP[67] bit 8	MAIN[2][30][28]
DRP[67] bit 9	MAIN[2][31][28]
DRP[67] bit 10	MAIN[2][30][29]
DRP[67] bit 11	MAIN[2][31][29]
DRP[67] bit 12	MAIN[2][30][30]
DRP[67] bit 13	MAIN[2][31][30]
DRP[67] bit 14	MAIN[2][30][31]
DRP[67] bit 15	MAIN[2][31][31]
DRP[68] bit 0	MAIN[2][30][32]
DRP[68] bit 1	MAIN[2][31][32]
DRP[68] bit 2	MAIN[2][30][33]
DRP[68] bit 3	MAIN[2][31][33]
DRP[68] bit 4	MAIN[2][30][34]
DRP[68] bit 5	MAIN[2][31][34]
DRP[68] bit 6	MAIN[2][30][35]
DRP[68] bit 7	MAIN[2][31][35]
DRP[68] bit 8	MAIN[2][30][36]
DRP[68] bit 9	MAIN[2][31][36]
DRP[68] bit 10	MAIN[2][30][37]
DRP[68] bit 11	MAIN[2][31][37]
DRP[68] bit 12	MAIN[2][30][38]
DRP[68] bit 13	MAIN[2][31][38]
DRP[68] bit 14	MAIN[2][30][39]
DRP[68] bit 15	MAIN[2][31][39]
DRP[69] bit 0	MAIN[2][30][40]
DRP[69] bit 1	MAIN[2][31][40]
DRP[69] bit 2	MAIN[2][30][41]
DRP[69] bit 3	MAIN[2][31][41]
DRP[69] bit 4	MAIN[2][30][42]
DRP[69] bit 5	MAIN[2][31][42]
DRP[69] bit 6	MAIN[2][30][43]
DRP[69] bit 7	MAIN[2][31][43]
DRP[69] bit 8	MAIN[2][30][44]
DRP[69] bit 9	MAIN[2][31][44]
DRP[69] bit 10	MAIN[2][30][45]
DRP[69] bit 11	MAIN[2][31][45]
DRP[69] bit 12	MAIN[2][30][46]
DRP[69] bit 13	MAIN[2][31][46]
DRP[69] bit 14	MAIN[2][30][47]
DRP[69] bit 15	MAIN[2][31][47]
DRP[70] bit 0	MAIN[2][30][48]
DRP[70] bit 1	MAIN[2][31][48]
DRP[70] bit 2	MAIN[2][30][49]
DRP[70] bit 3	MAIN[2][31][49]
DRP[70] bit 4	MAIN[2][30][50]
DRP[70] bit 5	MAIN[2][31][50]
DRP[70] bit 6	MAIN[2][30][51]
DRP[70] bit 7	MAIN[2][31][51]
DRP[70] bit 8	MAIN[2][30][52]
DRP[70] bit 9	MAIN[2][31][52]
DRP[70] bit 10	MAIN[2][30][53]
DRP[70] bit 11	MAIN[2][31][53]
DRP[70] bit 12	MAIN[2][30][54]
DRP[70] bit 13	MAIN[2][31][54]
DRP[70] bit 14	MAIN[2][30][55]
DRP[70] bit 15	MAIN[2][31][55]
DRP[71] bit 0	MAIN[2][30][56]
DRP[71] bit 1	MAIN[2][31][56]
DRP[71] bit 2	MAIN[2][30][57]
DRP[71] bit 3	MAIN[2][31][57]
DRP[71] bit 4	MAIN[2][30][58]
DRP[71] bit 5	MAIN[2][31][58]
DRP[71] bit 6	MAIN[2][30][59]
DRP[71] bit 7	MAIN[2][31][59]
DRP[71] bit 8	MAIN[2][30][60]
DRP[71] bit 9	MAIN[2][31][60]
DRP[71] bit 10	MAIN[2][30][61]
DRP[71] bit 11	MAIN[2][31][61]
DRP[71] bit 12	MAIN[2][30][62]
DRP[71] bit 13	MAIN[2][31][62]
DRP[71] bit 14	MAIN[2][30][63]
DRP[71] bit 15	MAIN[2][31][63]
DRP[72] bit 0	MAIN[3][30][0]
DRP[72] bit 1	MAIN[3][31][0]
DRP[72] bit 2	MAIN[3][30][1]
DRP[72] bit 3	MAIN[3][31][1]
DRP[72] bit 4	MAIN[3][30][2]
DRP[72] bit 5	MAIN[3][31][2]
DRP[72] bit 6	MAIN[3][30][3]
DRP[72] bit 7	MAIN[3][31][3]
DRP[72] bit 8	MAIN[3][30][4]
DRP[72] bit 9	MAIN[3][31][4]
DRP[72] bit 10	MAIN[3][30][5]
DRP[72] bit 11	MAIN[3][31][5]
DRP[72] bit 12	MAIN[3][30][6]
DRP[72] bit 13	MAIN[3][31][6]
DRP[72] bit 14	MAIN[3][30][7]
DRP[72] bit 15	MAIN[3][31][7]
DRP[73] bit 0	MAIN[3][30][8]
DRP[73] bit 1	MAIN[3][31][8]
DRP[73] bit 2	MAIN[3][30][9]
DRP[73] bit 3	MAIN[3][31][9]
DRP[73] bit 4	MAIN[3][30][10]
DRP[73] bit 5	MAIN[3][31][10]
DRP[73] bit 6	MAIN[3][30][11]
DRP[73] bit 7	MAIN[3][31][11]
DRP[73] bit 8	MAIN[3][30][12]
DRP[73] bit 9	MAIN[3][31][12]
DRP[73] bit 10	MAIN[3][30][13]
DRP[73] bit 11	MAIN[3][31][13]
DRP[73] bit 12	MAIN[3][30][14]
DRP[73] bit 13	MAIN[3][31][14]
DRP[73] bit 14	MAIN[3][30][15]
DRP[73] bit 15	MAIN[3][31][15]
DRP[74] bit 0	MAIN[3][30][16]
DRP[74] bit 1	MAIN[3][31][16]
DRP[74] bit 2	MAIN[3][30][17]
DRP[74] bit 3	MAIN[3][31][17]
DRP[74] bit 4	MAIN[3][30][18]
DRP[74] bit 5	MAIN[3][31][18]
DRP[74] bit 6	MAIN[3][30][19]
DRP[74] bit 7	MAIN[3][31][19]
DRP[74] bit 8	MAIN[3][30][20]
DRP[74] bit 9	MAIN[3][31][20]
DRP[74] bit 10	MAIN[3][30][21]
DRP[74] bit 11	MAIN[3][31][21]
DRP[74] bit 12	MAIN[3][30][22]
DRP[74] bit 13	MAIN[3][31][22]
DRP[74] bit 14	MAIN[3][30][23]
DRP[74] bit 15	MAIN[3][31][23]
DRP[75] bit 0	MAIN[3][30][24]
DRP[75] bit 1	MAIN[3][31][24]
DRP[75] bit 2	MAIN[3][30][25]
DRP[75] bit 3	MAIN[3][31][25]
DRP[75] bit 4	MAIN[3][30][26]
DRP[75] bit 5	MAIN[3][31][26]
DRP[75] bit 6	MAIN[3][30][27]
DRP[75] bit 7	MAIN[3][31][27]
DRP[75] bit 8	MAIN[3][30][28]
DRP[75] bit 9	MAIN[3][31][28]
DRP[75] bit 10	MAIN[3][30][29]
DRP[75] bit 11	MAIN[3][31][29]
DRP[75] bit 12	MAIN[3][30][30]
DRP[75] bit 13	MAIN[3][31][30]
DRP[75] bit 14	MAIN[3][30][31]
DRP[75] bit 15	MAIN[3][31][31]
DRP[76] bit 0	MAIN[3][30][32]
DRP[76] bit 1	MAIN[3][31][32]
DRP[76] bit 2	MAIN[3][30][33]
DRP[76] bit 3	MAIN[3][31][33]
DRP[76] bit 4	MAIN[3][30][34]
DRP[76] bit 5	MAIN[3][31][34]
DRP[76] bit 6	MAIN[3][30][35]
DRP[76] bit 7	MAIN[3][31][35]
DRP[76] bit 8	MAIN[3][30][36]
DRP[76] bit 9	MAIN[3][31][36]
DRP[76] bit 10	MAIN[3][30][37]
DRP[76] bit 11	MAIN[3][31][37]
DRP[76] bit 12	MAIN[3][30][38]
DRP[76] bit 13	MAIN[3][31][38]
DRP[76] bit 14	MAIN[3][30][39]
DRP[76] bit 15	MAIN[3][31][39]
DRP[77] bit 0	MAIN[3][30][40]
DRP[77] bit 1	MAIN[3][31][40]
DRP[77] bit 2	MAIN[3][30][41]
DRP[77] bit 3	MAIN[3][31][41]
DRP[77] bit 4	MAIN[3][30][42]
DRP[77] bit 5	MAIN[3][31][42]
DRP[77] bit 6	MAIN[3][30][43]
DRP[77] bit 7	MAIN[3][31][43]
DRP[77] bit 8	MAIN[3][30][44]
DRP[77] bit 9	MAIN[3][31][44]
DRP[77] bit 10	MAIN[3][30][45]
DRP[77] bit 11	MAIN[3][31][45]
DRP[77] bit 12	MAIN[3][30][46]
DRP[77] bit 13	MAIN[3][31][46]
DRP[77] bit 14	MAIN[3][30][47]
DRP[77] bit 15	MAIN[3][31][47]
DRP[78] bit 0	MAIN[3][30][48]
DRP[78] bit 1	MAIN[3][31][48]
DRP[78] bit 2	MAIN[3][30][49]
DRP[78] bit 3	MAIN[3][31][49]
DRP[78] bit 4	MAIN[3][30][50]
DRP[78] bit 5	MAIN[3][31][50]
DRP[78] bit 6	MAIN[3][30][51]
DRP[78] bit 7	MAIN[3][31][51]
DRP[78] bit 8	MAIN[3][30][52]
DRP[78] bit 9	MAIN[3][31][52]
DRP[78] bit 10	MAIN[3][30][53]
DRP[78] bit 11	MAIN[3][31][53]
DRP[78] bit 12	MAIN[3][30][54]
DRP[78] bit 13	MAIN[3][31][54]
DRP[78] bit 14	MAIN[3][30][55]
DRP[78] bit 15	MAIN[3][31][55]
DRP[79] bit 0	MAIN[3][30][56]
DRP[79] bit 1	MAIN[3][31][56]
DRP[79] bit 2	MAIN[3][30][57]
DRP[79] bit 3	MAIN[3][31][57]
DRP[79] bit 4	MAIN[3][30][58]
DRP[79] bit 5	MAIN[3][31][58]
DRP[79] bit 6	MAIN[3][30][59]
DRP[79] bit 7	MAIN[3][31][59]
DRP[79] bit 8	MAIN[3][30][60]
DRP[79] bit 9	MAIN[3][31][60]
DRP[79] bit 10	MAIN[3][30][61]
DRP[79] bit 11	MAIN[3][31][61]
DRP[79] bit 12	MAIN[3][30][62]
DRP[79] bit 13	MAIN[3][31][62]
DRP[79] bit 14	MAIN[3][30][63]
DRP[79] bit 15	MAIN[3][31][63]
DRP[80] bit 0	MAIN[4][30][0]
DRP[80] bit 1	MAIN[4][31][0]
DRP[80] bit 2	MAIN[4][30][1]
DRP[80] bit 3	MAIN[4][31][1]
DRP[80] bit 4	MAIN[4][30][2]
DRP[80] bit 5	MAIN[4][31][2]
DRP[80] bit 6	MAIN[4][30][3]
DRP[80] bit 7	MAIN[4][31][3]
DRP[80] bit 8	MAIN[4][30][4]
DRP[80] bit 9	MAIN[4][31][4]
DRP[80] bit 10	MAIN[4][30][5]
DRP[80] bit 11	MAIN[4][31][5]
DRP[80] bit 12	MAIN[4][30][6]
DRP[80] bit 13	MAIN[4][31][6]
DRP[80] bit 14	MAIN[4][30][7]
DRP[80] bit 15	MAIN[4][31][7]
DRP[81] bit 0	MAIN[4][30][8]
DRP[81] bit 1	MAIN[4][31][8]
DRP[81] bit 2	MAIN[4][30][9]
DRP[81] bit 3	MAIN[4][31][9]
DRP[81] bit 4	MAIN[4][30][10]
DRP[81] bit 5	MAIN[4][31][10]
DRP[81] bit 6	MAIN[4][30][11]
DRP[81] bit 7	MAIN[4][31][11]
DRP[81] bit 8	MAIN[4][30][12]
DRP[81] bit 9	MAIN[4][31][12]
DRP[81] bit 10	MAIN[4][30][13]
DRP[81] bit 11	MAIN[4][31][13]
DRP[81] bit 12	MAIN[4][30][14]
DRP[81] bit 13	MAIN[4][31][14]
DRP[81] bit 14	MAIN[4][30][15]
DRP[81] bit 15	MAIN[4][31][15]
DRP[82] bit 0	MAIN[4][30][16]
DRP[82] bit 1	MAIN[4][31][16]
DRP[82] bit 2	MAIN[4][30][17]
DRP[82] bit 3	MAIN[4][31][17]
DRP[82] bit 4	MAIN[4][30][18]
DRP[82] bit 5	MAIN[4][31][18]
DRP[82] bit 6	MAIN[4][30][19]
DRP[82] bit 7	MAIN[4][31][19]
DRP[82] bit 8	MAIN[4][30][20]
DRP[82] bit 9	MAIN[4][31][20]
DRP[82] bit 10	MAIN[4][30][21]
DRP[82] bit 11	MAIN[4][31][21]
DRP[82] bit 12	MAIN[4][30][22]
DRP[82] bit 13	MAIN[4][31][22]
DRP[82] bit 14	MAIN[4][30][23]
DRP[82] bit 15	MAIN[4][31][23]
DRP[83] bit 0	MAIN[4][30][24]
DRP[83] bit 1	MAIN[4][31][24]
DRP[83] bit 2	MAIN[4][30][25]
DRP[83] bit 3	MAIN[4][31][25]
DRP[83] bit 4	MAIN[4][30][26]
DRP[83] bit 5	MAIN[4][31][26]
DRP[83] bit 6	MAIN[4][30][27]
DRP[83] bit 7	MAIN[4][31][27]
DRP[83] bit 8	MAIN[4][30][28]
DRP[83] bit 9	MAIN[4][31][28]
DRP[83] bit 10	MAIN[4][30][29]
DRP[83] bit 11	MAIN[4][31][29]
DRP[83] bit 12	MAIN[4][30][30]
DRP[83] bit 13	MAIN[4][31][30]
DRP[83] bit 14	MAIN[4][30][31]
DRP[83] bit 15	MAIN[4][31][31]
DRP[84] bit 0	MAIN[4][30][32]
DRP[84] bit 1	MAIN[4][31][32]
DRP[84] bit 2	MAIN[4][30][33]
DRP[84] bit 3	MAIN[4][31][33]
DRP[84] bit 4	MAIN[4][30][34]
DRP[84] bit 5	MAIN[4][31][34]
DRP[84] bit 6	MAIN[4][30][35]
DRP[84] bit 7	MAIN[4][31][35]
DRP[84] bit 8	MAIN[4][30][36]
DRP[84] bit 9	MAIN[4][31][36]
DRP[84] bit 10	MAIN[4][30][37]
DRP[84] bit 11	MAIN[4][31][37]
DRP[84] bit 12	MAIN[4][30][38]
DRP[84] bit 13	MAIN[4][31][38]
DRP[84] bit 14	MAIN[4][30][39]
DRP[84] bit 15	MAIN[4][31][39]
DRP[85] bit 0	MAIN[4][30][40]
DRP[85] bit 1	MAIN[4][31][40]
DRP[85] bit 2	MAIN[4][30][41]
DRP[85] bit 3	MAIN[4][31][41]
DRP[85] bit 4	MAIN[4][30][42]
DRP[85] bit 5	MAIN[4][31][42]
DRP[85] bit 6	MAIN[4][30][43]
DRP[85] bit 7	MAIN[4][31][43]
DRP[85] bit 8	MAIN[4][30][44]
DRP[85] bit 9	MAIN[4][31][44]
DRP[85] bit 10	MAIN[4][30][45]
DRP[85] bit 11	MAIN[4][31][45]
DRP[85] bit 12	MAIN[4][30][46]
DRP[85] bit 13	MAIN[4][31][46]
DRP[85] bit 14	MAIN[4][30][47]
DRP[85] bit 15	MAIN[4][31][47]
DRP[86] bit 0	MAIN[4][30][48]
DRP[86] bit 1	MAIN[4][31][48]
DRP[86] bit 2	MAIN[4][30][49]
DRP[86] bit 3	MAIN[4][31][49]
DRP[86] bit 4	MAIN[4][30][50]
DRP[86] bit 5	MAIN[4][31][50]
DRP[86] bit 6	MAIN[4][30][51]
DRP[86] bit 7	MAIN[4][31][51]
DRP[86] bit 8	MAIN[4][30][52]
DRP[86] bit 9	MAIN[4][31][52]
DRP[86] bit 10	MAIN[4][30][53]
DRP[86] bit 11	MAIN[4][31][53]
DRP[86] bit 12	MAIN[4][30][54]
DRP[86] bit 13	MAIN[4][31][54]
DRP[86] bit 14	MAIN[4][30][55]
DRP[86] bit 15	MAIN[4][31][55]
DRP[87] bit 0	MAIN[4][30][56]
DRP[87] bit 1	MAIN[4][31][56]
DRP[87] bit 2	MAIN[4][30][57]
DRP[87] bit 3	MAIN[4][31][57]
DRP[87] bit 4	MAIN[4][30][58]
DRP[87] bit 5	MAIN[4][31][58]
DRP[87] bit 6	MAIN[4][30][59]
DRP[87] bit 7	MAIN[4][31][59]
DRP[87] bit 8	MAIN[4][30][60]
DRP[87] bit 9	MAIN[4][31][60]
DRP[87] bit 10	MAIN[4][30][61]
DRP[87] bit 11	MAIN[4][31][61]
DRP[87] bit 12	MAIN[4][30][62]
DRP[87] bit 13	MAIN[4][31][62]
DRP[87] bit 14	MAIN[4][30][63]
DRP[87] bit 15	MAIN[4][31][63]
DRP[88] bit 0	MAIN[5][30][0]
DRP[88] bit 1	MAIN[5][31][0]
DRP[88] bit 2	MAIN[5][30][1]
DRP[88] bit 3	MAIN[5][31][1]
DRP[88] bit 4	MAIN[5][30][2]
DRP[88] bit 5	MAIN[5][31][2]
DRP[88] bit 6	MAIN[5][30][3]
DRP[88] bit 7	MAIN[5][31][3]
DRP[88] bit 8	MAIN[5][30][4]
DRP[88] bit 9	MAIN[5][31][4]
DRP[88] bit 10	MAIN[5][30][5]
DRP[88] bit 11	MAIN[5][31][5]
DRP[88] bit 12	MAIN[5][30][6]
DRP[88] bit 13	MAIN[5][31][6]
DRP[88] bit 14	MAIN[5][30][7]
DRP[88] bit 15	MAIN[5][31][7]
DRP[89] bit 0	MAIN[5][30][8]
DRP[89] bit 1	MAIN[5][31][8]
DRP[89] bit 2	MAIN[5][30][9]
DRP[89] bit 3	MAIN[5][31][9]
DRP[89] bit 4	MAIN[5][30][10]
DRP[89] bit 5	MAIN[5][31][10]
DRP[89] bit 6	MAIN[5][30][11]
DRP[89] bit 7	MAIN[5][31][11]
DRP[89] bit 8	MAIN[5][30][12]
DRP[89] bit 9	MAIN[5][31][12]
DRP[89] bit 10	MAIN[5][30][13]
DRP[89] bit 11	MAIN[5][31][13]
DRP[89] bit 12	MAIN[5][30][14]
DRP[89] bit 13	MAIN[5][31][14]
DRP[89] bit 14	MAIN[5][30][15]
DRP[89] bit 15	MAIN[5][31][15]
DRP[90] bit 0	MAIN[5][30][16]
DRP[90] bit 1	MAIN[5][31][16]
DRP[90] bit 2	MAIN[5][30][17]
DRP[90] bit 3	MAIN[5][31][17]
DRP[90] bit 4	MAIN[5][30][18]
DRP[90] bit 5	MAIN[5][31][18]
DRP[90] bit 6	MAIN[5][30][19]
DRP[90] bit 7	MAIN[5][31][19]
DRP[90] bit 8	MAIN[5][30][20]
DRP[90] bit 9	MAIN[5][31][20]
DRP[90] bit 10	MAIN[5][30][21]
DRP[90] bit 11	MAIN[5][31][21]
DRP[90] bit 12	MAIN[5][30][22]
DRP[90] bit 13	MAIN[5][31][22]
DRP[90] bit 14	MAIN[5][30][23]
DRP[90] bit 15	MAIN[5][31][23]
DRP[91] bit 0	MAIN[5][30][24]
DRP[91] bit 1	MAIN[5][31][24]
DRP[91] bit 2	MAIN[5][30][25]
DRP[91] bit 3	MAIN[5][31][25]
DRP[91] bit 4	MAIN[5][30][26]
DRP[91] bit 5	MAIN[5][31][26]
DRP[91] bit 6	MAIN[5][30][27]
DRP[91] bit 7	MAIN[5][31][27]
DRP[91] bit 8	MAIN[5][30][28]
DRP[91] bit 9	MAIN[5][31][28]
DRP[91] bit 10	MAIN[5][30][29]
DRP[91] bit 11	MAIN[5][31][29]
DRP[91] bit 12	MAIN[5][30][30]
DRP[91] bit 13	MAIN[5][31][30]
DRP[91] bit 14	MAIN[5][30][31]
DRP[91] bit 15	MAIN[5][31][31]
DRP[92] bit 0	MAIN[5][30][32]
DRP[92] bit 1	MAIN[5][31][32]
DRP[92] bit 2	MAIN[5][30][33]
DRP[92] bit 3	MAIN[5][31][33]
DRP[92] bit 4	MAIN[5][30][34]
DRP[92] bit 5	MAIN[5][31][34]
DRP[92] bit 6	MAIN[5][30][35]
DRP[92] bit 7	MAIN[5][31][35]
DRP[92] bit 8	MAIN[5][30][36]
DRP[92] bit 9	MAIN[5][31][36]
DRP[92] bit 10	MAIN[5][30][37]
DRP[92] bit 11	MAIN[5][31][37]
DRP[92] bit 12	MAIN[5][30][38]
DRP[92] bit 13	MAIN[5][31][38]
DRP[92] bit 14	MAIN[5][30][39]
DRP[92] bit 15	MAIN[5][31][39]
DRP[93] bit 0	MAIN[5][30][40]
DRP[93] bit 1	MAIN[5][31][40]
DRP[93] bit 2	MAIN[5][30][41]
DRP[93] bit 3	MAIN[5][31][41]
DRP[93] bit 4	MAIN[5][30][42]
DRP[93] bit 5	MAIN[5][31][42]
DRP[93] bit 6	MAIN[5][30][43]
DRP[93] bit 7	MAIN[5][31][43]
DRP[93] bit 8	MAIN[5][30][44]
DRP[93] bit 9	MAIN[5][31][44]
DRP[93] bit 10	MAIN[5][30][45]
DRP[93] bit 11	MAIN[5][31][45]
DRP[93] bit 12	MAIN[5][30][46]
DRP[93] bit 13	MAIN[5][31][46]
DRP[93] bit 14	MAIN[5][30][47]
DRP[93] bit 15	MAIN[5][31][47]
DRP[94] bit 0	MAIN[5][30][48]
DRP[94] bit 1	MAIN[5][31][48]
DRP[94] bit 2	MAIN[5][30][49]
DRP[94] bit 3	MAIN[5][31][49]
DRP[94] bit 4	MAIN[5][30][50]
DRP[94] bit 5	MAIN[5][31][50]
DRP[94] bit 6	MAIN[5][30][51]
DRP[94] bit 7	MAIN[5][31][51]
DRP[94] bit 8	MAIN[5][30][52]
DRP[94] bit 9	MAIN[5][31][52]
DRP[94] bit 10	MAIN[5][30][53]
DRP[94] bit 11	MAIN[5][31][53]
DRP[94] bit 12	MAIN[5][30][54]
DRP[94] bit 13	MAIN[5][31][54]
DRP[94] bit 14	MAIN[5][30][55]
DRP[94] bit 15	MAIN[5][31][55]
DRP[95] bit 0	MAIN[5][30][56]
DRP[95] bit 1	MAIN[5][31][56]
DRP[95] bit 2	MAIN[5][30][57]
DRP[95] bit 3	MAIN[5][31][57]
DRP[95] bit 4	MAIN[5][30][58]
DRP[95] bit 5	MAIN[5][31][58]
DRP[95] bit 6	MAIN[5][30][59]
DRP[95] bit 7	MAIN[5][31][59]
DRP[95] bit 8	MAIN[5][30][60]
DRP[95] bit 9	MAIN[5][31][60]
DRP[95] bit 10	MAIN[5][30][61]
DRP[95] bit 11	MAIN[5][31][61]
DRP[95] bit 12	MAIN[5][30][62]
DRP[95] bit 13	MAIN[5][31][62]
DRP[95] bit 14	MAIN[5][30][63]
DRP[95] bit 15	MAIN[5][31][63]
CLKSWING_CFG bit 0	MAIN[1][30][11]
CLKSWING_CFG bit 1	MAIN[1][31][11]
QPLLREFCLKSEL_STATIC_VAL	[enum: GTX_COMMON_PLLREFCLKSEL]
QPLLREFCLKSEL_MODE_DYNAMIC	MAIN[0][31][15]
MUX_SOUTHREFCLKOUT0	[enum: HCLK_GTX_MUX_SOUTHREFCLKOUT0]
MUX_SOUTHREFCLKOUT1	[enum: HCLK_GTX_MUX_SOUTHREFCLKOUT1]
MUX_NORTHREFCLKOUT0	[enum: HCLK_GTX_MUX_NORTHREFCLKOUT0]
MUX_NORTHREFCLKOUT1	[enum: HCLK_GTX_MUX_NORTHREFCLKOUT1]
QPLL_REFCLK_DIV	[enum: GTP_PLL_DIVSEL_REF]
AEN_BGBS bit 0	MAIN[2][30][59]
AEN_MASTER bit 0	MAIN[2][30][58]
AEN_PD bit 0	MAIN[2][31][57]
AEN_QPLL bit 0	MAIN[2][30][57]
AEN_REFCLK bit 0	MAIN[2][31][56]
AEN_RESET bit 0	MAIN[2][30][56]
AQDMUXSEL bit 0	MAIN[1][31][6]
AQDMUXSEL bit 1	MAIN[1][30][7]
AQDMUXSEL bit 2	MAIN[1][31][7]
A_BGMONITOREN bit 0	MAIN[2][31][51]
A_BGPD bit 0	MAIN[2][30][51]
A_GTREFCLKPD0 bit 0	MAIN[2][31][48]
A_GTREFCLKPD1 bit 0	MAIN[2][30][48]
A_QPLLLOCKEN bit 0	MAIN[2][30][50]
A_QPLLOUTRESET bit 0	MAIN[2][31][50]
A_QPLLPD bit 0	MAIN[2][31][49]
A_QPLLRESET bit 0	MAIN[2][30][49]
COMMON_AMUX_SEL bit 0	MAIN[1][30][18]
COMMON_AMUX_SEL bit 1	MAIN[1][31][18]
COMMON_INSTANTIATED bit 0	MAIN[2][31][63]
QPLL_AMONITOR_SEL bit 0	MAIN[0][30][56]
QPLL_AMONITOR_SEL bit 1	MAIN[0][31][56]
QPLL_CLKOUT_CFG bit 0	MAIN[0][30][57]
QPLL_CLKOUT_CFG bit 1	MAIN[0][31][57]
QPLL_CLKOUT_CFG bit 2	MAIN[0][30][58]
QPLL_CLKOUT_CFG bit 3	MAIN[0][31][58]
QPLL_COARSE_FREQ_OVRD bit 0	MAIN[0][30][45]
QPLL_COARSE_FREQ_OVRD bit 1	MAIN[0][31][45]
QPLL_COARSE_FREQ_OVRD bit 2	MAIN[0][30][46]
QPLL_COARSE_FREQ_OVRD bit 3	MAIN[0][31][46]
QPLL_COARSE_FREQ_OVRD bit 4	MAIN[0][30][47]
QPLL_COARSE_FREQ_OVRD bit 5	MAIN[0][31][47]
QPLL_COARSE_FREQ_OVRD_EN bit 0	MAIN[0][31][53]
QPLL_CP bit 0	MAIN[0][30][40]
QPLL_CP bit 1	MAIN[0][31][40]
QPLL_CP bit 2	MAIN[0][30][41]
QPLL_CP bit 3	MAIN[0][31][41]
QPLL_CP bit 4	MAIN[0][30][42]
QPLL_CP bit 5	MAIN[0][31][42]
QPLL_CP bit 6	MAIN[0][30][43]
QPLL_CP bit 7	MAIN[0][31][43]
QPLL_CP bit 8	MAIN[0][30][44]
QPLL_CP bit 9	MAIN[0][31][44]
QPLL_CP_MONITOR_EN bit 0	MAIN[0][31][54]
QPLL_DMONITOR_SEL bit 0	MAIN[0][31][55]
QPLL_FBDIV bit 0	MAIN[0][30][48]
QPLL_FBDIV bit 1	MAIN[0][31][48]
QPLL_FBDIV bit 2	MAIN[0][30][49]
QPLL_FBDIV bit 3	MAIN[0][31][49]
QPLL_FBDIV bit 4	MAIN[0][30][50]
QPLL_FBDIV bit 5	MAIN[0][31][50]
QPLL_FBDIV bit 6	MAIN[0][30][51]
QPLL_FBDIV bit 7	MAIN[0][31][51]
QPLL_FBDIV bit 8	MAIN[0][30][52]
QPLL_FBDIV bit 9	MAIN[0][31][52]
QPLL_FBDIV_MONITOR_EN bit 0	MAIN[0][30][55]
QPLL_FBDIV_RATIO bit 0	MAIN[0][30][59]
QPLL_LPF bit 0	MAIN[0][31][13]
QPLL_LPF bit 1	MAIN[0][30][14]
QPLL_LPF bit 2	MAIN[0][31][14]
QPLL_LPF bit 3	MAIN[0][30][15]
QPLL_VCTRL_MONITOR_EN bit 0	MAIN[0][30][53]
QPLL_VREG_MONITOR_EN bit 0	MAIN[0][30][54]
QPLL_RP_COMP bit 0	MAIN[2][30][62]
QPLL_VTRL_RESET bit 0	MAIN[2][30][61]
QPLL_VTRL_RESET bit 1	MAIN[2][31][61]
RCAL_CFG bit 0	MAIN[2][31][62]
RCAL_CFG bit 1	MAIN[2][30][63]
BIAS_CFG bit 0	MAIN[1][30][48]
BIAS_CFG bit 1	MAIN[1][31][48]
BIAS_CFG bit 2	MAIN[1][30][49]
BIAS_CFG bit 3	MAIN[1][31][49]
BIAS_CFG bit 4	MAIN[1][30][50]
BIAS_CFG bit 5	MAIN[1][31][50]
BIAS_CFG bit 6	MAIN[1][30][51]
BIAS_CFG bit 7	MAIN[1][31][51]
BIAS_CFG bit 8	MAIN[1][30][52]
BIAS_CFG bit 9	MAIN[1][31][52]
BIAS_CFG bit 10	MAIN[1][30][53]
BIAS_CFG bit 11	MAIN[1][31][53]
BIAS_CFG bit 12	MAIN[1][30][54]
BIAS_CFG bit 13	MAIN[1][31][54]
BIAS_CFG bit 14	MAIN[1][30][55]
BIAS_CFG bit 15	MAIN[1][31][55]
BIAS_CFG bit 16	MAIN[1][30][56]
BIAS_CFG bit 17	MAIN[1][31][56]
BIAS_CFG bit 18	MAIN[1][30][57]
BIAS_CFG bit 19	MAIN[1][31][57]
BIAS_CFG bit 20	MAIN[1][30][58]
BIAS_CFG bit 21	MAIN[1][31][58]
BIAS_CFG bit 22	MAIN[1][30][59]
BIAS_CFG bit 23	MAIN[1][31][59]
BIAS_CFG bit 24	MAIN[1][30][60]
BIAS_CFG bit 25	MAIN[1][31][60]
BIAS_CFG bit 26	MAIN[1][30][61]
BIAS_CFG bit 27	MAIN[1][31][61]
BIAS_CFG bit 28	MAIN[1][30][62]
BIAS_CFG bit 29	MAIN[1][31][62]
BIAS_CFG bit 30	MAIN[1][30][63]
BIAS_CFG bit 31	MAIN[1][31][63]
BIAS_CFG bit 32	MAIN[2][30][0]
BIAS_CFG bit 33	MAIN[2][31][0]
BIAS_CFG bit 34	MAIN[2][30][1]
BIAS_CFG bit 35	MAIN[2][31][1]
BIAS_CFG bit 36	MAIN[2][30][2]
BIAS_CFG bit 37	MAIN[2][31][2]
BIAS_CFG bit 38	MAIN[2][30][3]
BIAS_CFG bit 39	MAIN[2][31][3]
BIAS_CFG bit 40	MAIN[2][30][4]
BIAS_CFG bit 41	MAIN[2][31][4]
BIAS_CFG bit 42	MAIN[2][30][5]
BIAS_CFG bit 43	MAIN[2][31][5]
BIAS_CFG bit 44	MAIN[2][30][6]
BIAS_CFG bit 45	MAIN[2][31][6]
BIAS_CFG bit 46	MAIN[2][30][7]
BIAS_CFG bit 47	MAIN[2][31][7]
BIAS_CFG bit 48	MAIN[2][30][8]
BIAS_CFG bit 49	MAIN[2][31][8]
BIAS_CFG bit 50	MAIN[2][30][9]
BIAS_CFG bit 51	MAIN[2][31][9]
BIAS_CFG bit 52	MAIN[2][30][10]
BIAS_CFG bit 53	MAIN[2][31][10]
BIAS_CFG bit 54	MAIN[2][30][11]
BIAS_CFG bit 55	MAIN[2][31][11]
BIAS_CFG bit 56	MAIN[2][30][12]
BIAS_CFG bit 57	MAIN[2][31][12]
BIAS_CFG bit 58	MAIN[2][30][13]
BIAS_CFG bit 59	MAIN[2][31][13]
BIAS_CFG bit 60	MAIN[2][30][14]
BIAS_CFG bit 61	MAIN[2][31][14]
BIAS_CFG bit 62	MAIN[2][30][15]
BIAS_CFG bit 63	MAIN[2][31][15]
COMMON_CFG bit 0	MAIN[2][30][24]
COMMON_CFG bit 1	MAIN[2][31][24]
COMMON_CFG bit 2	MAIN[2][30][25]
COMMON_CFG bit 3	MAIN[2][31][25]
COMMON_CFG bit 4	MAIN[2][30][26]
COMMON_CFG bit 5	MAIN[2][31][26]
COMMON_CFG bit 6	MAIN[2][30][27]
COMMON_CFG bit 7	MAIN[2][31][27]
COMMON_CFG bit 8	MAIN[2][30][28]
COMMON_CFG bit 9	MAIN[2][31][28]
COMMON_CFG bit 10	MAIN[2][30][29]
COMMON_CFG bit 11	MAIN[2][31][29]
COMMON_CFG bit 12	MAIN[2][30][30]
COMMON_CFG bit 13	MAIN[2][31][30]
COMMON_CFG bit 14	MAIN[2][30][31]
COMMON_CFG bit 15	MAIN[2][31][31]
COMMON_CFG bit 16	MAIN[2][30][32]
COMMON_CFG bit 17	MAIN[2][31][32]
COMMON_CFG bit 18	MAIN[2][30][33]
COMMON_CFG bit 19	MAIN[2][31][33]
COMMON_CFG bit 20	MAIN[2][30][34]
COMMON_CFG bit 21	MAIN[2][31][34]
COMMON_CFG bit 22	MAIN[2][30][35]
COMMON_CFG bit 23	MAIN[2][31][35]
COMMON_CFG bit 24	MAIN[2][30][36]
COMMON_CFG bit 25	MAIN[2][31][36]
COMMON_CFG bit 26	MAIN[2][30][37]
COMMON_CFG bit 27	MAIN[2][31][37]
COMMON_CFG bit 28	MAIN[2][30][38]
COMMON_CFG bit 29	MAIN[2][31][38]
COMMON_CFG bit 30	MAIN[2][30][39]
COMMON_CFG bit 31	MAIN[2][31][39]
QPLL_CFG bit 0	MAIN[0][30][16]
QPLL_CFG bit 1	MAIN[0][31][16]
QPLL_CFG bit 2	MAIN[0][30][17]
QPLL_CFG bit 3	MAIN[0][31][17]
QPLL_CFG bit 4	MAIN[0][30][18]
QPLL_CFG bit 5	MAIN[0][31][18]
QPLL_CFG bit 6	MAIN[0][30][19]
QPLL_CFG bit 7	MAIN[0][31][19]
QPLL_CFG bit 8	MAIN[0][30][20]
QPLL_CFG bit 9	MAIN[0][31][20]
QPLL_CFG bit 10	MAIN[0][30][21]
QPLL_CFG bit 11	MAIN[0][31][21]
QPLL_CFG bit 12	MAIN[0][30][22]
QPLL_CFG bit 13	MAIN[0][31][22]
QPLL_CFG bit 14	MAIN[0][30][23]
QPLL_CFG bit 15	MAIN[0][31][23]
QPLL_CFG bit 16	MAIN[0][30][24]
QPLL_CFG bit 17	MAIN[0][31][24]
QPLL_CFG bit 18	MAIN[0][30][25]
QPLL_CFG bit 19	MAIN[0][31][25]
QPLL_CFG bit 20	MAIN[0][30][26]
QPLL_CFG bit 21	MAIN[0][31][26]
QPLL_CFG bit 22	MAIN[0][30][27]
QPLL_CFG bit 23	MAIN[0][31][27]
QPLL_CFG bit 24	MAIN[0][30][28]
QPLL_CFG bit 25	MAIN[0][31][28]
QPLL_CFG bit 26	MAIN[0][30][29]
QPLL_INIT_CFG bit 0	MAIN[0][30][0]
QPLL_INIT_CFG bit 1	MAIN[0][31][0]
QPLL_INIT_CFG bit 2	MAIN[0][30][1]
QPLL_INIT_CFG bit 3	MAIN[0][31][1]
QPLL_INIT_CFG bit 4	MAIN[0][30][2]
QPLL_INIT_CFG bit 5	MAIN[0][31][2]
QPLL_INIT_CFG bit 6	MAIN[0][30][3]
QPLL_INIT_CFG bit 7	MAIN[0][31][3]
QPLL_INIT_CFG bit 8	MAIN[0][30][4]
QPLL_INIT_CFG bit 9	MAIN[0][31][4]
QPLL_INIT_CFG bit 10	MAIN[0][30][5]
QPLL_INIT_CFG bit 11	MAIN[0][31][5]
QPLL_INIT_CFG bit 12	MAIN[0][30][6]
QPLL_INIT_CFG bit 13	MAIN[0][31][6]
QPLL_INIT_CFG bit 14	MAIN[0][30][7]
QPLL_INIT_CFG bit 15	MAIN[0][31][7]
QPLL_INIT_CFG bit 16	MAIN[0][30][8]
QPLL_INIT_CFG bit 17	MAIN[0][31][8]
QPLL_INIT_CFG bit 18	MAIN[0][30][9]
QPLL_INIT_CFG bit 19	MAIN[0][31][9]
QPLL_INIT_CFG bit 20	MAIN[0][30][10]
QPLL_INIT_CFG bit 21	MAIN[0][31][10]
QPLL_INIT_CFG bit 22	MAIN[0][30][11]
QPLL_INIT_CFG bit 23	MAIN[0][31][11]
QPLL_LOCK_CFG bit 0	MAIN[0][30][32]
QPLL_LOCK_CFG bit 1	MAIN[0][31][32]
QPLL_LOCK_CFG bit 2	MAIN[0][30][33]
QPLL_LOCK_CFG bit 3	MAIN[0][31][33]
QPLL_LOCK_CFG bit 4	MAIN[0][30][34]
QPLL_LOCK_CFG bit 5	MAIN[0][31][34]
QPLL_LOCK_CFG bit 6	MAIN[0][30][35]
QPLL_LOCK_CFG bit 7	MAIN[0][31][35]
QPLL_LOCK_CFG bit 8	MAIN[0][30][36]
QPLL_LOCK_CFG bit 9	MAIN[0][31][36]
QPLL_LOCK_CFG bit 10	MAIN[0][30][37]
QPLL_LOCK_CFG bit 11	MAIN[0][31][37]
QPLL_LOCK_CFG bit 12	MAIN[0][30][38]
QPLL_LOCK_CFG bit 13	MAIN[0][31][38]
QPLL_LOCK_CFG bit 14	MAIN[0][30][39]
QPLL_LOCK_CFG bit 15	MAIN[0][31][39]
RSVD_ATTR0 bit 0	MAIN[2][30][16]
RSVD_ATTR0 bit 1	MAIN[2][31][16]
RSVD_ATTR0 bit 2	MAIN[2][30][17]
RSVD_ATTR0 bit 3	MAIN[2][31][17]
RSVD_ATTR0 bit 4	MAIN[2][30][18]
RSVD_ATTR0 bit 5	MAIN[2][31][18]
RSVD_ATTR0 bit 6	MAIN[2][30][19]
RSVD_ATTR0 bit 7	MAIN[2][31][19]
RSVD_ATTR0 bit 8	MAIN[2][30][20]
RSVD_ATTR0 bit 9	MAIN[2][31][20]
RSVD_ATTR0 bit 10	MAIN[2][30][21]
RSVD_ATTR0 bit 11	MAIN[2][31][21]
RSVD_ATTR0 bit 12	MAIN[2][30][22]
RSVD_ATTR0 bit 13	MAIN[2][31][22]
RSVD_ATTR0 bit 14	MAIN[2][30][23]
RSVD_ATTR0 bit 15	MAIN[2][31][23]
RSVD_ATTR1 bit 0	MAIN[1][30][40]
RSVD_ATTR1 bit 1	MAIN[1][31][40]
RSVD_ATTR1 bit 2	MAIN[1][30][41]
RSVD_ATTR1 bit 3	MAIN[1][31][41]
RSVD_ATTR1 bit 4	MAIN[1][30][42]
RSVD_ATTR1 bit 5	MAIN[1][31][42]
RSVD_ATTR1 bit 6	MAIN[1][30][43]
RSVD_ATTR1 bit 7	MAIN[1][31][43]
RSVD_ATTR1 bit 8	MAIN[1][30][44]
RSVD_ATTR1 bit 9	MAIN[1][31][44]
RSVD_ATTR1 bit 10	MAIN[1][30][45]
RSVD_ATTR1 bit 11	MAIN[1][31][45]
RSVD_ATTR1 bit 12	MAIN[1][30][46]
RSVD_ATTR1 bit 13	MAIN[1][31][46]
RSVD_ATTR1 bit 14	MAIN[1][30][47]
RSVD_ATTR1 bit 15	MAIN[1][31][47]

virtex7 GTH_COMMON enum GTX_COMMON_PLLREFCLKSEL
GTX_COMMON.QPLLREFCLKSEL_STATIC_VAL	MAIN[0][30][13]	MAIN[0][31][12]	MAIN[0][30][12]
NONE	0	0	0
GTREFCLK0	0	0	1
GTREFCLK1	0	1	0
GTNORTHREFCLK0	0	1	1
GTNORTHREFCLK1	1	0	0
GTSOUTHREFCLK0	1	0	1
GTSOUTHREFCLK1	1	1	0
GTGREFCLK	1	1	1

virtex7 GTH_COMMON enum HCLK_GTX_MUX_SOUTHREFCLKOUT0
GTX_COMMON.MUX_SOUTHREFCLKOUT0	MAIN[1][31][17]	MAIN[1][30][17]
NONE	0	0
MGTREFCLKIN0	0	1
MGTREFCLKIN1	1	0
SOUTHREFCLKIN0	1	1

virtex7 GTH_COMMON enum HCLK_GTX_MUX_SOUTHREFCLKOUT1
GTX_COMMON.MUX_SOUTHREFCLKOUT1	MAIN[1][31][16]	MAIN[1][30][16]
NONE	0	0
MGTREFCLKIN0	0	1
MGTREFCLKIN1	1	0
SOUTHREFCLKIN1	1	1

virtex7 GTH_COMMON enum HCLK_GTX_MUX_NORTHREFCLKOUT0
GTX_COMMON.MUX_NORTHREFCLKOUT0	MAIN[1][31][13]	MAIN[1][30][13]
NONE	0	0
MGTREFCLKIN0	0	1
MGTREFCLKIN1	1	0
NORTHREFCLKIN0	1	1

virtex7 GTH_COMMON enum HCLK_GTX_MUX_NORTHREFCLKOUT1
GTX_COMMON.MUX_NORTHREFCLKOUT1	MAIN[1][31][14]	MAIN[1][30][14]
NONE	0	0
MGTREFCLKIN0	0	1
MGTREFCLKIN1	1	0
NORTHREFCLKIN1	1	1

virtex7 GTH_COMMON enum GTP_PLL_DIVSEL_REF
GTX_COMMON.QPLL_REFCLK_DIV	MAIN[0][31][31]	MAIN[0][30][31]	MAIN[0][31][30]	MAIN[0][30][30]	MAIN[0][31][29]
_1	1	0	0	0	0
_2	0	0	0	0	0
_3	0	0	0	0	1
_4	0	0	0	1	0
_5	0	0	0	1	1
_6	0	0	1	0	1
_8	0	0	1	1	0
_10	0	0	1	1	1
_12	0	1	1	0	1
_16	0	1	1	1	0
_20	0	1	1	1	1

Bel wires

virtex7 GTH_COMMON bel wires
Wire	Pins
CELL[0].IMUX_CLK[1]	GTX_COMMON.QPLLCLKSPARE[0]
CELL[0].IMUX_IMUX_DELAY[16]	GTX_COMMON.DRPDI[7]
CELL[0].IMUX_IMUX_DELAY[17]	GTX_COMMON.DRPDI[6]
CELL[0].IMUX_IMUX_DELAY[18]	GTX_COMMON.DRPDI[3]
CELL[0].IMUX_IMUX_DELAY[19]	GTX_COMMON.DRPDI[2]
CELL[0].IMUX_IMUX_DELAY[20]	GTX_COMMON.DRPDI[5]
CELL[0].IMUX_IMUX_DELAY[21]	GTX_COMMON.DRPDI[4]
CELL[0].IMUX_IMUX_DELAY[22]	GTX_COMMON.DRPDI[1]
CELL[0].IMUX_IMUX_DELAY[23]	GTX_COMMON.DRPDI[0]
CELL[0].IMUX_IMUX_DELAY[25]	GTX_COMMON.PMASCANIN[0]
CELL[0].IMUX_IMUX_DELAY[29]	GTX_COMMON.DRPWE
CELL[0].OUT_BEL[8]	GTX_COMMON.DRPDO[6]
CELL[0].OUT_BEL[9]	GTX_COMMON.DRPDO[3]
CELL[0].OUT_BEL[10]	GTX_COMMON.DRPDO[4]
CELL[0].OUT_BEL[11]	GTX_COMMON.DRPDO[1]
CELL[0].OUT_BEL[12]	GTX_COMMON.DRPDO[7]
CELL[0].OUT_BEL[13]	GTX_COMMON.DRPDO[2]
CELL[0].OUT_BEL[14]	GTX_COMMON.DRPDO[5]
CELL[0].OUT_BEL[15]	GTX_COMMON.DRPDO[0]
CELL[0].OUT_BEL[21]	GTX_COMMON.DRPRDY
CELL[1].IMUX_CLK[0]	GTX_COMMON.PMASCANCLK[1]
CELL[1].IMUX_CLK[1]	GTX_COMMON.DRPCLK
CELL[1].IMUX_IMUX_DELAY[16]	GTX_COMMON.DRPDI[15]
CELL[1].IMUX_IMUX_DELAY[17]	GTX_COMMON.DRPDI[14]
CELL[1].IMUX_IMUX_DELAY[18]	GTX_COMMON.DRPDI[11]
CELL[1].IMUX_IMUX_DELAY[19]	GTX_COMMON.DRPDI[10]
CELL[1].IMUX_IMUX_DELAY[20]	GTX_COMMON.DRPDI[13]
CELL[1].IMUX_IMUX_DELAY[21]	GTX_COMMON.DRPDI[12]
CELL[1].IMUX_IMUX_DELAY[22]	GTX_COMMON.DRPDI[9]
CELL[1].IMUX_IMUX_DELAY[23]	GTX_COMMON.DRPDI[8]
CELL[1].IMUX_IMUX_DELAY[25]	GTX_COMMON.PMASCANIN[1]
CELL[1].IMUX_IMUX_DELAY[29]	GTX_COMMON.DRPEN
CELL[1].IMUX_IMUX_DELAY[31]	GTX_COMMON.PMASCANENB
CELL[1].OUT_BEL[8]	GTX_COMMON.DRPDO[14]
CELL[1].OUT_BEL[9]	GTX_COMMON.DRPDO[11]
CELL[1].OUT_BEL[10]	GTX_COMMON.DRPDO[12]
CELL[1].OUT_BEL[11]	GTX_COMMON.DRPDO[9]
CELL[1].OUT_BEL[12]	GTX_COMMON.DRPDO[15]
CELL[1].OUT_BEL[13]	GTX_COMMON.DRPDO[10]
CELL[1].OUT_BEL[14]	GTX_COMMON.DRPDO[13]
CELL[1].OUT_BEL[15]	GTX_COMMON.DRPDO[8]
CELL[2].IMUX_CLK[0]	GTX_COMMON.GTGREFCLK
CELL[2].IMUX_CTRL[1]	GTX_COMMON.QPLLOUTRESET
CELL[2].IMUX_IMUX_DELAY[16]	GTX_COMMON.QPLLRSVD2[0]
CELL[2].IMUX_IMUX_DELAY[18]	GTX_COMMON.QPLLRSVD1[3]
CELL[2].IMUX_IMUX_DELAY[19]	GTX_COMMON.QPLLRSVD1[2]
CELL[2].IMUX_IMUX_DELAY[20]	GTX_COMMON.PMARSVD[4]
CELL[2].IMUX_IMUX_DELAY[21]	GTX_COMMON.PMARSVD[0]
CELL[2].IMUX_IMUX_DELAY[22]	GTX_COMMON.QPLLRSVD1[1]
CELL[2].IMUX_IMUX_DELAY[23]	GTX_COMMON.QPLLRSVD1[0]
CELL[2].IMUX_IMUX_DELAY[24]	GTX_COMMON.DRPADDR[0]
CELL[2].IMUX_IMUX_DELAY[25]	GTX_COMMON.DRPADDR[1]
CELL[2].IMUX_IMUX_DELAY[26]	GTX_COMMON.DRPADDR[4]
CELL[2].IMUX_IMUX_DELAY[27]	GTX_COMMON.DRPADDR[5]
CELL[2].IMUX_IMUX_DELAY[28]	GTX_COMMON.DRPADDR[2]
CELL[2].IMUX_IMUX_DELAY[29]	GTX_COMMON.DRPADDR[3]
CELL[2].IMUX_IMUX_DELAY[30]	GTX_COMMON.DRPADDR[6]
CELL[2].IMUX_IMUX_DELAY[31]	GTX_COMMON.DRPADDR[7]
CELL[2].OUT_BEL[9]	GTX_COMMON.PMASCANOUT[0]
CELL[2].OUT_BEL[10]	GTX_COMMON.QPLLREFCLKLOST
CELL[2].OUT_BEL[14]	GTX_COMMON.QPLLLOCK
CELL[2].OUT_BEL[19]	GTX_COMMON.QPLLFBCLKLOST
CELL[3].IMUX_CLK[0]	GTCLK[1].CLKTESTSIG
CELL[3].IMUX_CLK[1]	GTX_COMMON.QPLLLOCKDETCLK
CELL[3].IMUX_CTRL[0]	GTX_COMMON.QPLLRESET
CELL[3].IMUX_IMUX_DELAY[16]	GTX_COMMON.QPLLRSVD2[1]
CELL[3].IMUX_IMUX_DELAY[18]	GTX_COMMON.QPLLRSVD1[7]
CELL[3].IMUX_IMUX_DELAY[19]	GTX_COMMON.QPLLRSVD1[6]
CELL[3].IMUX_IMUX_DELAY[20]	GTX_COMMON.PMARSVD[5]
CELL[3].IMUX_IMUX_DELAY[21]	GTX_COMMON.PMARSVD[1]
CELL[3].IMUX_IMUX_DELAY[22]	GTX_COMMON.QPLLRSVD1[5]
CELL[3].IMUX_IMUX_DELAY[23]	GTX_COMMON.QPLLRSVD1[4]
CELL[3].IMUX_IMUX_DELAY[24]	GTX_COMMON.QPLLLOCKEN
CELL[3].IMUX_IMUX_DELAY[25]	GTX_COMMON.PMASCANIN[2]
CELL[3].IMUX_IMUX_DELAY[26]	GTCLK[0].CEB
CELL[3].IMUX_IMUX_DELAY[27]	GTX_COMMON.QPLLREFCLKSEL[2]
CELL[3].IMUX_IMUX_DELAY[28]	GTX_COMMON.QPLLPD
CELL[3].IMUX_IMUX_DELAY[29]	GTCLK[1].CEB
CELL[3].IMUX_IMUX_DELAY[30]	GTX_COMMON.QPLLREFCLKSEL[1]
CELL[3].IMUX_IMUX_DELAY[31]	GTX_COMMON.QPLLREFCLKSEL[0]
CELL[3].OUT_BEL[2]	GTX_COMMON.REFCLKOUTMONITOR
CELL[3].OUT_BEL[8]	GTX_COMMON.PMARSVDOUT[14]
CELL[3].OUT_BEL[9]	GTX_COMMON.PMASCANOUT[1]
CELL[3].OUT_BEL[10]	GTX_COMMON.PMASCANOUT[4]
CELL[3].OUT_BEL[17]	GTX_COMMON.QPLLDMONITOR[2]
CELL[3].OUT_BEL[18]	GTX_COMMON.PMARSVDOUT[13]
CELL[3].OUT_BEL[19]	GTX_COMMON.QPLLDMONITOR[0]
CELL[3].OUT_BEL[20]	GTX_COMMON.PMARSVDOUT[12]
CELL[3].OUT_BEL[21]	GTX_COMMON.QPLLDMONITOR[3]
CELL[3].OUT_BEL[22]	GTX_COMMON.PMARSVDOUT[15]
CELL[3].OUT_BEL[23]	GTX_COMMON.QPLLDMONITOR[1]
CELL[3].OUT_GT_MGTCLKOUT[0]	GTCLK[0].CLKOUT
CELL[3].OUT_GT_MGTCLKOUT[1]	GTCLK[1].CLKOUT
CELL[4].IMUX_CLK[0]	GTX_COMMON.PMASCANCLK[0]
CELL[4].IMUX_CLK[1]	GTCLK[0].CLKTESTSIG
CELL[4].IMUX_IMUX_DELAY[16]	GTX_COMMON.QPLLRSVD2[2]
CELL[4].IMUX_IMUX_DELAY[18]	GTX_COMMON.QPLLRSVD1[11]
CELL[4].IMUX_IMUX_DELAY[19]	GTX_COMMON.QPLLRSVD1[10]
CELL[4].IMUX_IMUX_DELAY[20]	GTX_COMMON.PMARSVD[6]
CELL[4].IMUX_IMUX_DELAY[21]	GTX_COMMON.PMARSVD[2]
CELL[4].IMUX_IMUX_DELAY[22]	GTX_COMMON.QPLLRSVD1[9]
CELL[4].IMUX_IMUX_DELAY[23]	GTX_COMMON.QPLLRSVD1[8]
CELL[4].IMUX_IMUX_DELAY[25]	GTX_COMMON.PMASCANIN[3]
CELL[4].IMUX_IMUX_DELAY[26]	GTX_COMMON.BGRCALOVRD[3]
CELL[4].IMUX_IMUX_DELAY[27]	GTX_COMMON.BGRCALOVRD[2]
CELL[4].IMUX_IMUX_DELAY[28]	GTX_COMMON.RCALENB
CELL[4].IMUX_IMUX_DELAY[29]	GTX_COMMON.BGRCALOVRD[4]
CELL[4].IMUX_IMUX_DELAY[30]	GTX_COMMON.BGRCALOVRD[1]
CELL[4].IMUX_IMUX_DELAY[31]	GTX_COMMON.BGRCALOVRD[0]
CELL[4].OUT_BEL[9]	GTX_COMMON.PMASCANOUT[2]
CELL[4].OUT_BEL[16]	GTX_COMMON.QPLLDMONITOR[7]
CELL[4].OUT_BEL[17]	GTX_COMMON.PMARSVDOUT[9]
CELL[4].OUT_BEL[18]	GTX_COMMON.QPLLDMONITOR[5]
CELL[4].OUT_BEL[19]	GTX_COMMON.PMARSVDOUT[11]
CELL[4].OUT_BEL[20]	GTX_COMMON.QPLLDMONITOR[6]
CELL[4].OUT_BEL[21]	GTX_COMMON.PMARSVDOUT[8]
CELL[4].OUT_BEL[22]	GTX_COMMON.QPLLDMONITOR[4]
CELL[4].OUT_BEL[23]	GTX_COMMON.PMARSVDOUT[10]
CELL[5].IMUX_CLK[0]	GTX_COMMON.QPLLCLKSPARE[1]
CELL[5].IMUX_IMUX_DELAY[16]	GTX_COMMON.QPLLRSVD2[3]
CELL[5].IMUX_IMUX_DELAY[17]	GTX_COMMON.QPLLRSVD2[4]
CELL[5].IMUX_IMUX_DELAY[18]	GTX_COMMON.QPLLRSVD1[15]
CELL[5].IMUX_IMUX_DELAY[19]	GTX_COMMON.QPLLRSVD1[14]
CELL[5].IMUX_IMUX_DELAY[20]	GTX_COMMON.PMARSVD[7]
CELL[5].IMUX_IMUX_DELAY[21]	GTX_COMMON.PMARSVD[3]
CELL[5].IMUX_IMUX_DELAY[22]	GTX_COMMON.QPLLRSVD1[13]
CELL[5].IMUX_IMUX_DELAY[23]	GTX_COMMON.QPLLRSVD1[12]
CELL[5].IMUX_IMUX_DELAY[25]	GTX_COMMON.PMASCANIN[4]
CELL[5].IMUX_IMUX_DELAY[26]	GTX_COMMON.BGPDB
CELL[5].IMUX_IMUX_DELAY[27]	GTX_COMMON.BGMONITORENB
CELL[5].IMUX_IMUX_DELAY[28]	GTX_COMMON.QDPMASCANRSTEN
CELL[5].IMUX_IMUX_DELAY[29]	GTX_COMMON.QDPMASCANMODEB
CELL[5].IMUX_IMUX_DELAY[30]	GTX_COMMON.BGBYPASSB
CELL[5].IMUX_IMUX_DELAY[40]	GTX_COMMON.BGRCALOVRDENB
CELL[5].OUT_BEL[9]	GTX_COMMON.PMASCANOUT[3]
CELL[5].OUT_BEL[16]	GTX_COMMON.PMARSVDOUT[4]
CELL[5].OUT_BEL[17]	GTX_COMMON.PMARSVDOUT[1]
CELL[5].OUT_BEL[18]	GTX_COMMON.PMARSVDOUT[6]
CELL[5].OUT_BEL[19]	GTX_COMMON.PMARSVDOUT[3]
CELL[5].OUT_BEL[20]	GTX_COMMON.PMARSVDOUT[5]
CELL[5].OUT_BEL[21]	GTX_COMMON.PMARSVDOUT[0]
CELL[5].OUT_BEL[22]	GTX_COMMON.PMARSVDOUT[7]
CELL[5].OUT_BEL[23]	GTX_COMMON.PMARSVDOUT[2]

Bitstream

virtex7 GTH_COMMON rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[7] bit 14	GTX_COMMON: DRP[7] bit 15	GTX_COMMON: DRP[55] bit 14	GTX_COMMON: DRP[55] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[7] bit 12	GTX_COMMON: DRP[7] bit 13	GTX_COMMON: DRP[55] bit 12	GTX_COMMON: DRP[55] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[7] bit 10	GTX_COMMON: DRP[7] bit 11	GTX_COMMON: DRP[55] bit 10	GTX_COMMON: DRP[55] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[7] bit 8	GTX_COMMON: DRP[7] bit 9	GTX_COMMON: DRP[55] bit 8	GTX_COMMON: DRP[55] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[7] bit 6	GTX_COMMON: DRP[7] bit 7	GTX_COMMON: DRP[55] bit 6 GTX_COMMON: QPLL_FBDIV_RATIO bit 0	GTX_COMMON: DRP[55] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[7] bit 4	GTX_COMMON: DRP[7] bit 5	GTX_COMMON: DRP[55] bit 4 GTX_COMMON: QPLL_CLKOUT_CFG bit 2	GTX_COMMON: DRP[55] bit 5 GTX_COMMON: QPLL_CLKOUT_CFG bit 3
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[7] bit 2	GTX_COMMON: DRP[7] bit 3	GTX_COMMON: DRP[55] bit 2 GTX_COMMON: QPLL_CLKOUT_CFG bit 0	GTX_COMMON: DRP[55] bit 3 GTX_COMMON: QPLL_CLKOUT_CFG bit 1
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[7] bit 0	GTX_COMMON: DRP[7] bit 1	GTX_COMMON: DRP[55] bit 0 GTX_COMMON: QPLL_AMONITOR_SEL bit 0	GTX_COMMON: DRP[55] bit 1 GTX_COMMON: QPLL_AMONITOR_SEL bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[6] bit 14	GTX_COMMON: DRP[6] bit 15	GTX_COMMON: DRP[54] bit 14 GTX_COMMON: QPLL_FBDIV_MONITOR_EN bit 0	GTX_COMMON: DRP[54] bit 15 GTX_COMMON: QPLL_DMONITOR_SEL bit 0
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[6] bit 12	GTX_COMMON: DRP[6] bit 13	GTX_COMMON: DRP[54] bit 12 GTX_COMMON: QPLL_VREG_MONITOR_EN bit 0	GTX_COMMON: DRP[54] bit 13 GTX_COMMON: QPLL_CP_MONITOR_EN bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[6] bit 10	GTX_COMMON: DRP[6] bit 11	GTX_COMMON: DRP[54] bit 10 GTX_COMMON: QPLL_VCTRL_MONITOR_EN bit 0	GTX_COMMON: DRP[54] bit 11 GTX_COMMON: QPLL_COARSE_FREQ_OVRD_EN bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[6] bit 8	GTX_COMMON: DRP[6] bit 9	GTX_COMMON: DRP[54] bit 8 GTX_COMMON: QPLL_FBDIV bit 8	GTX_COMMON: DRP[54] bit 9 GTX_COMMON: QPLL_FBDIV bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[6] bit 6	GTX_COMMON: DRP[6] bit 7	GTX_COMMON: DRP[54] bit 6 GTX_COMMON: QPLL_FBDIV bit 6	GTX_COMMON: DRP[54] bit 7 GTX_COMMON: QPLL_FBDIV bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[6] bit 4	GTX_COMMON: DRP[6] bit 5	GTX_COMMON: DRP[54] bit 4 GTX_COMMON: QPLL_FBDIV bit 4	GTX_COMMON: DRP[54] bit 5 GTX_COMMON: QPLL_FBDIV bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[6] bit 2	GTX_COMMON: DRP[6] bit 3	GTX_COMMON: DRP[54] bit 2 GTX_COMMON: QPLL_FBDIV bit 2	GTX_COMMON: DRP[54] bit 3 GTX_COMMON: QPLL_FBDIV bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[6] bit 0	GTX_COMMON: DRP[6] bit 1	GTX_COMMON: DRP[54] bit 0 GTX_COMMON: QPLL_FBDIV bit 0	GTX_COMMON: DRP[54] bit 1 GTX_COMMON: QPLL_FBDIV bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[5] bit 14	GTX_COMMON: DRP[5] bit 15	GTX_COMMON: DRP[53] bit 14 GTX_COMMON: QPLL_COARSE_FREQ_OVRD bit 4	GTX_COMMON: DRP[53] bit 15 GTX_COMMON: QPLL_COARSE_FREQ_OVRD bit 5
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[5] bit 12	GTX_COMMON: DRP[5] bit 13	GTX_COMMON: DRP[53] bit 12 GTX_COMMON: QPLL_COARSE_FREQ_OVRD bit 2	GTX_COMMON: DRP[53] bit 13 GTX_COMMON: QPLL_COARSE_FREQ_OVRD bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[5] bit 10	GTX_COMMON: DRP[5] bit 11	GTX_COMMON: DRP[53] bit 10 GTX_COMMON: QPLL_COARSE_FREQ_OVRD bit 0	GTX_COMMON: DRP[53] bit 11 GTX_COMMON: QPLL_COARSE_FREQ_OVRD bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[5] bit 8	GTX_COMMON: DRP[5] bit 9	GTX_COMMON: DRP[53] bit 8 GTX_COMMON: QPLL_CP bit 8	GTX_COMMON: DRP[53] bit 9 GTX_COMMON: QPLL_CP bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[5] bit 6	GTX_COMMON: DRP[5] bit 7	GTX_COMMON: DRP[53] bit 6 GTX_COMMON: QPLL_CP bit 6	GTX_COMMON: DRP[53] bit 7 GTX_COMMON: QPLL_CP bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[5] bit 4	GTX_COMMON: DRP[5] bit 5	GTX_COMMON: DRP[53] bit 4 GTX_COMMON: QPLL_CP bit 4	GTX_COMMON: DRP[53] bit 5 GTX_COMMON: QPLL_CP bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[5] bit 2	GTX_COMMON: DRP[5] bit 3	GTX_COMMON: DRP[53] bit 2 GTX_COMMON: QPLL_CP bit 2	GTX_COMMON: DRP[53] bit 3 GTX_COMMON: QPLL_CP bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[5] bit 0	GTX_COMMON: DRP[5] bit 1	GTX_COMMON: DRP[53] bit 0 GTX_COMMON: QPLL_CP bit 0	GTX_COMMON: DRP[53] bit 1 GTX_COMMON: QPLL_CP bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[4] bit 14	GTX_COMMON: DRP[4] bit 15	GTX_COMMON: DRP[52] bit 14 GTX_COMMON: QPLL_LOCK_CFG bit 14	GTX_COMMON: DRP[52] bit 15 GTX_COMMON: QPLL_LOCK_CFG bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[4] bit 12	GTX_COMMON: DRP[4] bit 13	GTX_COMMON: DRP[52] bit 12 GTX_COMMON: QPLL_LOCK_CFG bit 12	GTX_COMMON: DRP[52] bit 13 GTX_COMMON: QPLL_LOCK_CFG bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[4] bit 10	GTX_COMMON: DRP[4] bit 11	GTX_COMMON: DRP[52] bit 10 GTX_COMMON: QPLL_LOCK_CFG bit 10	GTX_COMMON: DRP[52] bit 11 GTX_COMMON: QPLL_LOCK_CFG bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[4] bit 8	GTX_COMMON: DRP[4] bit 9	GTX_COMMON: DRP[52] bit 8 GTX_COMMON: QPLL_LOCK_CFG bit 8	GTX_COMMON: DRP[52] bit 9 GTX_COMMON: QPLL_LOCK_CFG bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[4] bit 6	GTX_COMMON: DRP[4] bit 7	GTX_COMMON: DRP[52] bit 6 GTX_COMMON: QPLL_LOCK_CFG bit 6	GTX_COMMON: DRP[52] bit 7 GTX_COMMON: QPLL_LOCK_CFG bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[4] bit 4	GTX_COMMON: DRP[4] bit 5	GTX_COMMON: DRP[52] bit 4 GTX_COMMON: QPLL_LOCK_CFG bit 4	GTX_COMMON: DRP[52] bit 5 GTX_COMMON: QPLL_LOCK_CFG bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[4] bit 2	GTX_COMMON: DRP[4] bit 3	GTX_COMMON: DRP[52] bit 2 GTX_COMMON: QPLL_LOCK_CFG bit 2	GTX_COMMON: DRP[52] bit 3 GTX_COMMON: QPLL_LOCK_CFG bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[4] bit 0	GTX_COMMON: DRP[4] bit 1	GTX_COMMON: DRP[52] bit 0 GTX_COMMON: QPLL_LOCK_CFG bit 0	GTX_COMMON: DRP[52] bit 1 GTX_COMMON: QPLL_LOCK_CFG bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[3] bit 14	GTX_COMMON: DRP[3] bit 15	GTX_COMMON: DRP[51] bit 14 GTX_COMMON: QPLL_REFCLK_DIV bit 3	GTX_COMMON: DRP[51] bit 15 GTX_COMMON: QPLL_REFCLK_DIV bit 4
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[3] bit 12	GTX_COMMON: DRP[3] bit 13	GTX_COMMON: DRP[51] bit 12 GTX_COMMON: QPLL_REFCLK_DIV bit 1	GTX_COMMON: DRP[51] bit 13 GTX_COMMON: QPLL_REFCLK_DIV bit 2
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[3] bit 10	GTX_COMMON: DRP[3] bit 11	GTX_COMMON: DRP[51] bit 10 GTX_COMMON: QPLL_CFG bit 26	GTX_COMMON: DRP[51] bit 11 GTX_COMMON: QPLL_REFCLK_DIV bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[3] bit 8	GTX_COMMON: DRP[3] bit 9	GTX_COMMON: DRP[51] bit 8 GTX_COMMON: QPLL_CFG bit 24	GTX_COMMON: DRP[51] bit 9 GTX_COMMON: QPLL_CFG bit 25
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[3] bit 6	GTX_COMMON: DRP[3] bit 7	GTX_COMMON: DRP[51] bit 6 GTX_COMMON: QPLL_CFG bit 22	GTX_COMMON: DRP[51] bit 7 GTX_COMMON: QPLL_CFG bit 23
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[3] bit 4	GTX_COMMON: DRP[3] bit 5	GTX_COMMON: DRP[51] bit 4 GTX_COMMON: QPLL_CFG bit 20	GTX_COMMON: DRP[51] bit 5 GTX_COMMON: QPLL_CFG bit 21
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[3] bit 2	GTX_COMMON: DRP[3] bit 3	GTX_COMMON: DRP[51] bit 2 GTX_COMMON: QPLL_CFG bit 18	GTX_COMMON: DRP[51] bit 3 GTX_COMMON: QPLL_CFG bit 19
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[3] bit 0	GTX_COMMON: DRP[3] bit 1	GTX_COMMON: DRP[51] bit 0 GTX_COMMON: QPLL_CFG bit 16	GTX_COMMON: DRP[51] bit 1 GTX_COMMON: QPLL_CFG bit 17
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[2] bit 14	GTX_COMMON: DRP[2] bit 15	GTX_COMMON: DRP[50] bit 14 GTX_COMMON: QPLL_CFG bit 14	GTX_COMMON: DRP[50] bit 15 GTX_COMMON: QPLL_CFG bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[2] bit 12	GTX_COMMON: DRP[2] bit 13	GTX_COMMON: DRP[50] bit 12 GTX_COMMON: QPLL_CFG bit 12	GTX_COMMON: DRP[50] bit 13 GTX_COMMON: QPLL_CFG bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[2] bit 10	GTX_COMMON: DRP[2] bit 11	GTX_COMMON: DRP[50] bit 10 GTX_COMMON: QPLL_CFG bit 10	GTX_COMMON: DRP[50] bit 11 GTX_COMMON: QPLL_CFG bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[2] bit 8	GTX_COMMON: DRP[2] bit 9	GTX_COMMON: DRP[50] bit 8 GTX_COMMON: QPLL_CFG bit 8	GTX_COMMON: DRP[50] bit 9 GTX_COMMON: QPLL_CFG bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[2] bit 6	GTX_COMMON: DRP[2] bit 7	GTX_COMMON: DRP[50] bit 6 GTX_COMMON: QPLL_CFG bit 6	GTX_COMMON: DRP[50] bit 7 GTX_COMMON: QPLL_CFG bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[2] bit 4	GTX_COMMON: DRP[2] bit 5	GTX_COMMON: DRP[50] bit 4 GTX_COMMON: QPLL_CFG bit 4	GTX_COMMON: DRP[50] bit 5 GTX_COMMON: QPLL_CFG bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[2] bit 2	GTX_COMMON: DRP[2] bit 3	GTX_COMMON: DRP[50] bit 2 GTX_COMMON: QPLL_CFG bit 2	GTX_COMMON: DRP[50] bit 3 GTX_COMMON: QPLL_CFG bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[2] bit 0	GTX_COMMON: DRP[2] bit 1	GTX_COMMON: DRP[50] bit 0 GTX_COMMON: QPLL_CFG bit 0	GTX_COMMON: DRP[50] bit 1 GTX_COMMON: QPLL_CFG bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[1] bit 14	GTX_COMMON: DRP[1] bit 15	GTX_COMMON: DRP[49] bit 14 GTX_COMMON: QPLL_LPF bit 3	GTX_COMMON: DRP[49] bit 15 GTX_COMMON: QPLLREFCLKSEL_MODE_DYNAMIC
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[1] bit 12	GTX_COMMON: DRP[1] bit 13	GTX_COMMON: DRP[49] bit 12 GTX_COMMON: QPLL_LPF bit 1	GTX_COMMON: DRP[49] bit 13 GTX_COMMON: QPLL_LPF bit 2
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[1] bit 10	GTX_COMMON: DRP[1] bit 11	GTX_COMMON: DRP[49] bit 10 GTX_COMMON: QPLLREFCLKSEL_STATIC_VAL bit 2	GTX_COMMON: DRP[49] bit 11 GTX_COMMON: QPLL_LPF bit 0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[1] bit 8	GTX_COMMON: DRP[1] bit 9	GTX_COMMON: DRP[49] bit 8 GTX_COMMON: QPLLREFCLKSEL_STATIC_VAL bit 0	GTX_COMMON: DRP[49] bit 9 GTX_COMMON: QPLLREFCLKSEL_STATIC_VAL bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[1] bit 6	GTX_COMMON: DRP[1] bit 7	GTX_COMMON: DRP[49] bit 6 GTX_COMMON: QPLL_INIT_CFG bit 22	GTX_COMMON: DRP[49] bit 7 GTX_COMMON: QPLL_INIT_CFG bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[1] bit 4	GTX_COMMON: DRP[1] bit 5	GTX_COMMON: DRP[49] bit 4 GTX_COMMON: QPLL_INIT_CFG bit 20	GTX_COMMON: DRP[49] bit 5 GTX_COMMON: QPLL_INIT_CFG bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[1] bit 2	GTX_COMMON: DRP[1] bit 3	GTX_COMMON: DRP[49] bit 2 GTX_COMMON: QPLL_INIT_CFG bit 18	GTX_COMMON: DRP[49] bit 3 GTX_COMMON: QPLL_INIT_CFG bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[1] bit 0	GTX_COMMON: DRP[1] bit 1	GTX_COMMON: DRP[49] bit 0 GTX_COMMON: QPLL_INIT_CFG bit 16	GTX_COMMON: DRP[49] bit 1 GTX_COMMON: QPLL_INIT_CFG bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[0] bit 14	GTX_COMMON: DRP[0] bit 15	GTX_COMMON: DRP[48] bit 14 GTX_COMMON: QPLL_INIT_CFG bit 14	GTX_COMMON: DRP[48] bit 15 GTX_COMMON: QPLL_INIT_CFG bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[0] bit 12	GTX_COMMON: DRP[0] bit 13	GTX_COMMON: DRP[48] bit 12 GTX_COMMON: QPLL_INIT_CFG bit 12	GTX_COMMON: DRP[48] bit 13 GTX_COMMON: QPLL_INIT_CFG bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[0] bit 10	GTX_COMMON: DRP[0] bit 11	GTX_COMMON: DRP[48] bit 10 GTX_COMMON: QPLL_INIT_CFG bit 10	GTX_COMMON: DRP[48] bit 11 GTX_COMMON: QPLL_INIT_CFG bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[0] bit 8	GTX_COMMON: DRP[0] bit 9	GTX_COMMON: DRP[48] bit 8 GTX_COMMON: QPLL_INIT_CFG bit 8	GTX_COMMON: DRP[48] bit 9 GTX_COMMON: QPLL_INIT_CFG bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[0] bit 6	GTX_COMMON: DRP[0] bit 7	GTX_COMMON: DRP[48] bit 6 GTX_COMMON: QPLL_INIT_CFG bit 6	GTX_COMMON: DRP[48] bit 7 GTX_COMMON: QPLL_INIT_CFG bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[0] bit 4	GTX_COMMON: DRP[0] bit 5	GTX_COMMON: DRP[48] bit 4 GTX_COMMON: QPLL_INIT_CFG bit 4	GTX_COMMON: DRP[48] bit 5 GTX_COMMON: QPLL_INIT_CFG bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[0] bit 2	GTX_COMMON: DRP[0] bit 3	GTX_COMMON: DRP[48] bit 2 GTX_COMMON: QPLL_INIT_CFG bit 2	GTX_COMMON: DRP[48] bit 3 GTX_COMMON: QPLL_INIT_CFG bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[0] bit 0	GTX_COMMON: DRP[0] bit 1	GTX_COMMON: DRP[48] bit 0 GTX_COMMON: QPLL_INIT_CFG bit 0	GTX_COMMON: DRP[48] bit 1 GTX_COMMON: QPLL_INIT_CFG bit 1

virtex7 GTH_COMMON rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[15] bit 14	GTX_COMMON: DRP[15] bit 15	GTX_COMMON: DRP[63] bit 14 GTX_COMMON: BIAS_CFG bit 30	GTX_COMMON: DRP[63] bit 15 GTX_COMMON: BIAS_CFG bit 31
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[15] bit 12	GTX_COMMON: DRP[15] bit 13	GTX_COMMON: DRP[63] bit 12 GTX_COMMON: BIAS_CFG bit 28	GTX_COMMON: DRP[63] bit 13 GTX_COMMON: BIAS_CFG bit 29
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[15] bit 10	GTX_COMMON: DRP[15] bit 11	GTX_COMMON: DRP[63] bit 10 GTX_COMMON: BIAS_CFG bit 26	GTX_COMMON: DRP[63] bit 11 GTX_COMMON: BIAS_CFG bit 27
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[15] bit 8	GTX_COMMON: DRP[15] bit 9	GTX_COMMON: DRP[63] bit 8 GTX_COMMON: BIAS_CFG bit 24	GTX_COMMON: DRP[63] bit 9 GTX_COMMON: BIAS_CFG bit 25
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[15] bit 6	GTX_COMMON: DRP[15] bit 7	GTX_COMMON: DRP[63] bit 6 GTX_COMMON: BIAS_CFG bit 22	GTX_COMMON: DRP[63] bit 7 GTX_COMMON: BIAS_CFG bit 23
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[15] bit 4	GTX_COMMON: DRP[15] bit 5	GTX_COMMON: DRP[63] bit 4 GTX_COMMON: BIAS_CFG bit 20	GTX_COMMON: DRP[63] bit 5 GTX_COMMON: BIAS_CFG bit 21
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[15] bit 2	GTX_COMMON: DRP[15] bit 3	GTX_COMMON: DRP[63] bit 2 GTX_COMMON: BIAS_CFG bit 18	GTX_COMMON: DRP[63] bit 3 GTX_COMMON: BIAS_CFG bit 19
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[15] bit 0	GTX_COMMON: DRP[15] bit 1	GTX_COMMON: DRP[63] bit 0 GTX_COMMON: BIAS_CFG bit 16	GTX_COMMON: DRP[63] bit 1 GTX_COMMON: BIAS_CFG bit 17
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[14] bit 14	GTX_COMMON: DRP[14] bit 15	GTX_COMMON: DRP[62] bit 14 GTX_COMMON: BIAS_CFG bit 14	GTX_COMMON: DRP[62] bit 15 GTX_COMMON: BIAS_CFG bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[14] bit 12	GTX_COMMON: DRP[14] bit 13	GTX_COMMON: DRP[62] bit 12 GTX_COMMON: BIAS_CFG bit 12	GTX_COMMON: DRP[62] bit 13 GTX_COMMON: BIAS_CFG bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[14] bit 10	GTX_COMMON: DRP[14] bit 11	GTX_COMMON: DRP[62] bit 10 GTX_COMMON: BIAS_CFG bit 10	GTX_COMMON: DRP[62] bit 11 GTX_COMMON: BIAS_CFG bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[14] bit 8	GTX_COMMON: DRP[14] bit 9	GTX_COMMON: DRP[62] bit 8 GTX_COMMON: BIAS_CFG bit 8	GTX_COMMON: DRP[62] bit 9 GTX_COMMON: BIAS_CFG bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[14] bit 6	GTX_COMMON: DRP[14] bit 7	GTX_COMMON: DRP[62] bit 6 GTX_COMMON: BIAS_CFG bit 6	GTX_COMMON: DRP[62] bit 7 GTX_COMMON: BIAS_CFG bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[14] bit 4	GTX_COMMON: DRP[14] bit 5	GTX_COMMON: DRP[62] bit 4 GTX_COMMON: BIAS_CFG bit 4	GTX_COMMON: DRP[62] bit 5 GTX_COMMON: BIAS_CFG bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[14] bit 2	GTX_COMMON: DRP[14] bit 3	GTX_COMMON: DRP[62] bit 2 GTX_COMMON: BIAS_CFG bit 2	GTX_COMMON: DRP[62] bit 3 GTX_COMMON: BIAS_CFG bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[14] bit 0	GTX_COMMON: DRP[14] bit 1	GTX_COMMON: DRP[62] bit 0 GTX_COMMON: BIAS_CFG bit 0	GTX_COMMON: DRP[62] bit 1 GTX_COMMON: BIAS_CFG bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[13] bit 14	GTX_COMMON: DRP[13] bit 15	GTX_COMMON: DRP[61] bit 14 GTX_COMMON: RSVD_ATTR1 bit 14	GTX_COMMON: DRP[61] bit 15 GTX_COMMON: RSVD_ATTR1 bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[13] bit 12	GTX_COMMON: DRP[13] bit 13	GTX_COMMON: DRP[61] bit 12 GTX_COMMON: RSVD_ATTR1 bit 12	GTX_COMMON: DRP[61] bit 13 GTX_COMMON: RSVD_ATTR1 bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[13] bit 10	GTX_COMMON: DRP[13] bit 11	GTX_COMMON: DRP[61] bit 10 GTX_COMMON: RSVD_ATTR1 bit 10	GTX_COMMON: DRP[61] bit 11 GTX_COMMON: RSVD_ATTR1 bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[13] bit 8	GTX_COMMON: DRP[13] bit 9	GTX_COMMON: DRP[61] bit 8 GTX_COMMON: RSVD_ATTR1 bit 8	GTX_COMMON: DRP[61] bit 9 GTX_COMMON: RSVD_ATTR1 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[13] bit 6	GTX_COMMON: DRP[13] bit 7	GTX_COMMON: DRP[61] bit 6 GTX_COMMON: RSVD_ATTR1 bit 6	GTX_COMMON: DRP[61] bit 7 GTX_COMMON: RSVD_ATTR1 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[13] bit 4	GTX_COMMON: DRP[13] bit 5	GTX_COMMON: DRP[61] bit 4 GTX_COMMON: RSVD_ATTR1 bit 4	GTX_COMMON: DRP[61] bit 5 GTX_COMMON: RSVD_ATTR1 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[13] bit 2	GTX_COMMON: DRP[13] bit 3	GTX_COMMON: DRP[61] bit 2 GTX_COMMON: RSVD_ATTR1 bit 2	GTX_COMMON: DRP[61] bit 3 GTX_COMMON: RSVD_ATTR1 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[13] bit 0	GTX_COMMON: DRP[13] bit 1	GTX_COMMON: DRP[61] bit 0 GTX_COMMON: RSVD_ATTR1 bit 0	GTX_COMMON: DRP[61] bit 1 GTX_COMMON: RSVD_ATTR1 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[12] bit 14	GTX_COMMON: DRP[12] bit 15	GTX_COMMON: DRP[60] bit 14	GTX_COMMON: DRP[60] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[12] bit 12	GTX_COMMON: DRP[12] bit 13	GTX_COMMON: DRP[60] bit 12	GTX_COMMON: DRP[60] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[12] bit 10	GTX_COMMON: DRP[12] bit 11	GTX_COMMON: DRP[60] bit 10	GTX_COMMON: DRP[60] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[12] bit 8	GTX_COMMON: DRP[12] bit 9	GTX_COMMON: invert GTGREFCLK GTX_COMMON: DRP[60] bit 8	GTX_COMMON: DRP[60] bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[12] bit 6	GTX_COMMON: DRP[12] bit 7	GTX_COMMON: invert PMASCANCLK[0] GTX_COMMON: DRP[60] bit 6	GTX_COMMON: invert DRPCLK GTX_COMMON: DRP[60] bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[12] bit 4	GTX_COMMON: DRP[12] bit 5	GTX_COMMON: invert QPLLLOCKDETCLK GTX_COMMON: DRP[60] bit 4	GTX_COMMON: invert PMASCANCLK[1] GTX_COMMON: DRP[60] bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[12] bit 2	GTX_COMMON: DRP[12] bit 3	GTX_COMMON: invert QPLLCLKSPARE[1] GTX_COMMON: DRP[60] bit 2	GTX_COMMON: invert QPLLCLKSPARE[0] GTX_COMMON: DRP[60] bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[12] bit 0	GTX_COMMON: DRP[12] bit 1	GTCLK[1]: invert CLKTESTSIG GTX_COMMON: DRP[60] bit 0	GTCLK[0]: invert CLKTESTSIG GTX_COMMON: DRP[60] bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[11] bit 14	GTX_COMMON: DRP[11] bit 15	GTX_COMMON: DRP[59] bit 14	GTX_COMMON: DRP[59] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[11] bit 12	GTX_COMMON: DRP[11] bit 13	GTX_COMMON: DRP[59] bit 12	GTX_COMMON: DRP[59] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[11] bit 10	GTX_COMMON: DRP[11] bit 11	GTX_COMMON: DRP[59] bit 10	GTX_COMMON: DRP[59] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[11] bit 8	GTX_COMMON: DRP[11] bit 9	GTX_COMMON: DRP[59] bit 8	GTX_COMMON: DRP[59] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[11] bit 6	GTX_COMMON: DRP[11] bit 7	GTX_COMMON: DRP[59] bit 6	GTX_COMMON: DRP[59] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[11] bit 4	GTX_COMMON: DRP[11] bit 5	GTX_COMMON: DRP[59] bit 4	GTX_COMMON: DRP[59] bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[11] bit 2	GTX_COMMON: DRP[11] bit 3	GTX_COMMON: DRP[59] bit 2	GTX_COMMON: DRP[59] bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[11] bit 0	GTX_COMMON: DRP[11] bit 1	GTX_COMMON: DRP[59] bit 0	GTX_COMMON: DRP[59] bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[10] bit 14	GTX_COMMON: DRP[10] bit 15	GTX_COMMON: DRP[58] bit 14	GTX_COMMON: DRP[58] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[10] bit 12	GTX_COMMON: DRP[10] bit 13	GTX_COMMON: DRP[58] bit 12	GTX_COMMON: DRP[58] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[10] bit 10	GTX_COMMON: DRP[10] bit 11	GTX_COMMON: DRP[58] bit 10	GTX_COMMON: DRP[58] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[10] bit 8	GTX_COMMON: DRP[10] bit 9	GTX_COMMON: DRP[58] bit 8	GTX_COMMON: DRP[58] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[10] bit 6	GTX_COMMON: DRP[10] bit 7	GTX_COMMON: DRP[58] bit 6	GTX_COMMON: DRP[58] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[10] bit 4	GTX_COMMON: DRP[10] bit 5	GTX_COMMON: DRP[58] bit 4 GTX_COMMON: COMMON_AMUX_SEL bit 0	GTX_COMMON: DRP[58] bit 5 GTX_COMMON: COMMON_AMUX_SEL bit 1
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[10] bit 2	GTX_COMMON: DRP[10] bit 3	GTX_COMMON: DRP[58] bit 2 GTX_COMMON: MUX_SOUTHREFCLKOUT0 bit 0	GTX_COMMON: DRP[58] bit 3 GTX_COMMON: MUX_SOUTHREFCLKOUT0 bit 1
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[10] bit 0	GTX_COMMON: DRP[10] bit 1	GTX_COMMON: DRP[58] bit 0 GTX_COMMON: MUX_SOUTHREFCLKOUT1 bit 0	GTX_COMMON: DRP[58] bit 1 GTX_COMMON: MUX_SOUTHREFCLKOUT1 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[9] bit 14	GTX_COMMON: DRP[9] bit 15	GTX_COMMON: DRP[57] bit 14	GTX_COMMON: DRP[57] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[9] bit 12	GTX_COMMON: DRP[9] bit 13	GTX_COMMON: DRP[57] bit 12 GTX_COMMON: MUX_NORTHREFCLKOUT1 bit 0	GTX_COMMON: DRP[57] bit 13 GTX_COMMON: MUX_NORTHREFCLKOUT1 bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[9] bit 10	GTX_COMMON: DRP[9] bit 11	GTX_COMMON: DRP[57] bit 10 GTX_COMMON: MUX_NORTHREFCLKOUT0 bit 0	GTX_COMMON: DRP[57] bit 11 GTX_COMMON: MUX_NORTHREFCLKOUT0 bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[9] bit 8	GTX_COMMON: DRP[9] bit 9	GTCLK[0]: CLKRCV_TRST GTX_COMMON: DRP[57] bit 8	GTCLK[1]: CLKRCV_TRST GTX_COMMON: DRP[57] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[9] bit 6	GTX_COMMON: DRP[9] bit 7	GTX_COMMON: DRP[57] bit 6 GTX_COMMON: CLKSWING_CFG bit 0	GTX_COMMON: DRP[57] bit 7 GTX_COMMON: CLKSWING_CFG bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[9] bit 4	GTX_COMMON: DRP[9] bit 5	GTCLK[0]: CLKCM_CFG GTX_COMMON: DRP[57] bit 4	GTCLK[1]: CLKCM_CFG GTX_COMMON: DRP[57] bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[9] bit 2	GTX_COMMON: DRP[9] bit 3	GTCLK[1]: MUX_CLKOUT bit 1 GTX_COMMON: DRP[57] bit 2	GTCLK[1]: MUX_CLKOUT bit 0 GTX_COMMON: DRP[57] bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[9] bit 0	GTX_COMMON: DRP[9] bit 1	GTCLK[0]: MUX_CLKOUT bit 1 GTX_COMMON: DRP[57] bit 0	GTCLK[0]: MUX_CLKOUT bit 0 GTX_COMMON: DRP[57] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[8] bit 14	GTX_COMMON: DRP[8] bit 15	GTX_COMMON: DRP[56] bit 14 GTX_COMMON: AQDMUXSEL bit 1	GTX_COMMON: DRP[56] bit 15 GTX_COMMON: AQDMUXSEL bit 2
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[8] bit 12	GTX_COMMON: DRP[8] bit 13	GTX_COMMON: DRP[56] bit 12	GTX_COMMON: DRP[56] bit 13 GTX_COMMON: AQDMUXSEL bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[8] bit 10	GTX_COMMON: DRP[8] bit 11	GTX_COMMON: DRP[56] bit 10	GTX_COMMON: DRP[56] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[8] bit 8	GTX_COMMON: DRP[8] bit 9	GTX_COMMON: DRP[56] bit 8	GTX_COMMON: DRP[56] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[8] bit 6	GTX_COMMON: DRP[8] bit 7	GTX_COMMON: DRP[56] bit 6	GTX_COMMON: DRP[56] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[8] bit 4	GTX_COMMON: DRP[8] bit 5	GTX_COMMON: DRP[56] bit 4	GTX_COMMON: DRP[56] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[8] bit 2	GTX_COMMON: DRP[8] bit 3	GTX_COMMON: DRP[56] bit 2	GTX_COMMON: DRP[56] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[8] bit 0	GTX_COMMON: DRP[8] bit 1	GTX_COMMON: DRP[56] bit 0	GTX_COMMON: DRP[56] bit 1

virtex7 GTH_COMMON rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[23] bit 14	GTX_COMMON: DRP[23] bit 15	GTX_COMMON: DRP[71] bit 14 GTX_COMMON: RCAL_CFG bit 1	GTX_COMMON: DRP[71] bit 15 GTX_COMMON: COMMON_INSTANTIATED bit 0
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[23] bit 12	GTX_COMMON: DRP[23] bit 13	GTX_COMMON: DRP[71] bit 12 GTX_COMMON: QPLL_RP_COMP bit 0	GTX_COMMON: DRP[71] bit 13 GTX_COMMON: RCAL_CFG bit 0
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[23] bit 10	GTX_COMMON: DRP[23] bit 11	GTX_COMMON: DRP[71] bit 10 GTX_COMMON: QPLL_VTRL_RESET bit 0	GTX_COMMON: DRP[71] bit 11 GTX_COMMON: QPLL_VTRL_RESET bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[23] bit 8	GTX_COMMON: DRP[23] bit 9	GTX_COMMON: DRP[71] bit 8	GTX_COMMON: DRP[71] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[23] bit 6	GTX_COMMON: DRP[23] bit 7	GTX_COMMON: DRP[71] bit 6 GTX_COMMON: AEN_BGBS bit 0	GTX_COMMON: DRP[71] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[23] bit 4	GTX_COMMON: DRP[23] bit 5	GTX_COMMON: DRP[71] bit 4 GTX_COMMON: AEN_MASTER bit 0	GTX_COMMON: DRP[71] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[23] bit 2	GTX_COMMON: DRP[23] bit 3	GTX_COMMON: DRP[71] bit 2 GTX_COMMON: AEN_QPLL bit 0	GTX_COMMON: DRP[71] bit 3 GTX_COMMON: AEN_PD bit 0
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[23] bit 0	GTX_COMMON: DRP[23] bit 1	GTX_COMMON: DRP[71] bit 0 GTX_COMMON: AEN_RESET bit 0	GTX_COMMON: DRP[71] bit 1 GTX_COMMON: AEN_REFCLK bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[22] bit 14	GTX_COMMON: DRP[22] bit 15	GTX_COMMON: DRP[70] bit 14	GTX_COMMON: DRP[70] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[22] bit 12	GTX_COMMON: DRP[22] bit 13	GTX_COMMON: DRP[70] bit 12	GTX_COMMON: DRP[70] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[22] bit 10	GTX_COMMON: DRP[22] bit 11	GTX_COMMON: DRP[70] bit 10	GTX_COMMON: DRP[70] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[22] bit 8	GTX_COMMON: DRP[22] bit 9	GTX_COMMON: DRP[70] bit 8	GTX_COMMON: DRP[70] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[22] bit 6	GTX_COMMON: DRP[22] bit 7	GTX_COMMON: DRP[70] bit 6 GTX_COMMON: A_BGPD bit 0	GTX_COMMON: DRP[70] bit 7 GTX_COMMON: A_BGMONITOREN bit 0
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[22] bit 4	GTX_COMMON: DRP[22] bit 5	GTX_COMMON: DRP[70] bit 4 GTX_COMMON: A_QPLLLOCKEN bit 0	GTX_COMMON: DRP[70] bit 5 GTX_COMMON: A_QPLLOUTRESET bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[22] bit 2	GTX_COMMON: DRP[22] bit 3	GTX_COMMON: DRP[70] bit 2 GTX_COMMON: A_QPLLRESET bit 0	GTX_COMMON: DRP[70] bit 3 GTX_COMMON: A_QPLLPD bit 0
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[22] bit 0	GTX_COMMON: DRP[22] bit 1	GTX_COMMON: DRP[70] bit 0 GTX_COMMON: A_GTREFCLKPD1 bit 0	GTX_COMMON: DRP[70] bit 1 GTX_COMMON: A_GTREFCLKPD0 bit 0
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[21] bit 14	GTX_COMMON: DRP[21] bit 15	GTX_COMMON: DRP[69] bit 14	GTX_COMMON: DRP[69] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[21] bit 12	GTX_COMMON: DRP[21] bit 13	GTX_COMMON: DRP[69] bit 12	GTX_COMMON: DRP[69] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[21] bit 10	GTX_COMMON: DRP[21] bit 11	GTX_COMMON: DRP[69] bit 10	GTX_COMMON: DRP[69] bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[21] bit 8	GTX_COMMON: DRP[21] bit 9	GTX_COMMON: DRP[69] bit 8	GTX_COMMON: DRP[69] bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[21] bit 6	GTX_COMMON: DRP[21] bit 7	GTX_COMMON: DRP[69] bit 6	GTX_COMMON: DRP[69] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[21] bit 4	GTX_COMMON: DRP[21] bit 5	GTX_COMMON: DRP[69] bit 4	GTX_COMMON: DRP[69] bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[21] bit 2	GTX_COMMON: DRP[21] bit 3	GTX_COMMON: DRP[69] bit 2	GTX_COMMON: DRP[69] bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[21] bit 0	GTX_COMMON: DRP[21] bit 1	GTX_COMMON: DRP[69] bit 0	GTX_COMMON: DRP[69] bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[20] bit 14	GTX_COMMON: DRP[20] bit 15	GTX_COMMON: DRP[68] bit 14 GTX_COMMON: COMMON_CFG bit 30	GTX_COMMON: DRP[68] bit 15 GTX_COMMON: COMMON_CFG bit 31
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[20] bit 12	GTX_COMMON: DRP[20] bit 13	GTX_COMMON: DRP[68] bit 12 GTX_COMMON: COMMON_CFG bit 28	GTX_COMMON: DRP[68] bit 13 GTX_COMMON: COMMON_CFG bit 29
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[20] bit 10	GTX_COMMON: DRP[20] bit 11	GTX_COMMON: DRP[68] bit 10 GTX_COMMON: COMMON_CFG bit 26	GTX_COMMON: DRP[68] bit 11 GTX_COMMON: COMMON_CFG bit 27
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[20] bit 8	GTX_COMMON: DRP[20] bit 9	GTX_COMMON: DRP[68] bit 8 GTX_COMMON: COMMON_CFG bit 24	GTX_COMMON: DRP[68] bit 9 GTX_COMMON: COMMON_CFG bit 25
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[20] bit 6	GTX_COMMON: DRP[20] bit 7	GTX_COMMON: DRP[68] bit 6 GTX_COMMON: COMMON_CFG bit 22	GTX_COMMON: DRP[68] bit 7 GTX_COMMON: COMMON_CFG bit 23
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[20] bit 4	GTX_COMMON: DRP[20] bit 5	GTX_COMMON: DRP[68] bit 4 GTX_COMMON: COMMON_CFG bit 20	GTX_COMMON: DRP[68] bit 5 GTX_COMMON: COMMON_CFG bit 21
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[20] bit 2	GTX_COMMON: DRP[20] bit 3	GTX_COMMON: DRP[68] bit 2 GTX_COMMON: COMMON_CFG bit 18	GTX_COMMON: DRP[68] bit 3 GTX_COMMON: COMMON_CFG bit 19
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[20] bit 0	GTX_COMMON: DRP[20] bit 1	GTX_COMMON: DRP[68] bit 0 GTX_COMMON: COMMON_CFG bit 16	GTX_COMMON: DRP[68] bit 1 GTX_COMMON: COMMON_CFG bit 17
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[19] bit 14	GTX_COMMON: DRP[19] bit 15	GTX_COMMON: DRP[67] bit 14 GTX_COMMON: COMMON_CFG bit 14	GTX_COMMON: DRP[67] bit 15 GTX_COMMON: COMMON_CFG bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[19] bit 12	GTX_COMMON: DRP[19] bit 13	GTX_COMMON: DRP[67] bit 12 GTX_COMMON: COMMON_CFG bit 12	GTX_COMMON: DRP[67] bit 13 GTX_COMMON: COMMON_CFG bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[19] bit 10	GTX_COMMON: DRP[19] bit 11	GTX_COMMON: DRP[67] bit 10 GTX_COMMON: COMMON_CFG bit 10	GTX_COMMON: DRP[67] bit 11 GTX_COMMON: COMMON_CFG bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[19] bit 8	GTX_COMMON: DRP[19] bit 9	GTX_COMMON: DRP[67] bit 8 GTX_COMMON: COMMON_CFG bit 8	GTX_COMMON: DRP[67] bit 9 GTX_COMMON: COMMON_CFG bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[19] bit 6	GTX_COMMON: DRP[19] bit 7	GTX_COMMON: DRP[67] bit 6 GTX_COMMON: COMMON_CFG bit 6	GTX_COMMON: DRP[67] bit 7 GTX_COMMON: COMMON_CFG bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[19] bit 4	GTX_COMMON: DRP[19] bit 5	GTX_COMMON: DRP[67] bit 4 GTX_COMMON: COMMON_CFG bit 4	GTX_COMMON: DRP[67] bit 5 GTX_COMMON: COMMON_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[19] bit 2	GTX_COMMON: DRP[19] bit 3	GTX_COMMON: DRP[67] bit 2 GTX_COMMON: COMMON_CFG bit 2	GTX_COMMON: DRP[67] bit 3 GTX_COMMON: COMMON_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[19] bit 0	GTX_COMMON: DRP[19] bit 1	GTX_COMMON: DRP[67] bit 0 GTX_COMMON: COMMON_CFG bit 0	GTX_COMMON: DRP[67] bit 1 GTX_COMMON: COMMON_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[18] bit 14	GTX_COMMON: DRP[18] bit 15	GTX_COMMON: DRP[66] bit 14 GTX_COMMON: RSVD_ATTR0 bit 14	GTX_COMMON: DRP[66] bit 15 GTX_COMMON: RSVD_ATTR0 bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[18] bit 12	GTX_COMMON: DRP[18] bit 13	GTX_COMMON: DRP[66] bit 12 GTX_COMMON: RSVD_ATTR0 bit 12	GTX_COMMON: DRP[66] bit 13 GTX_COMMON: RSVD_ATTR0 bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[18] bit 10	GTX_COMMON: DRP[18] bit 11	GTX_COMMON: DRP[66] bit 10 GTX_COMMON: RSVD_ATTR0 bit 10	GTX_COMMON: DRP[66] bit 11 GTX_COMMON: RSVD_ATTR0 bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[18] bit 8	GTX_COMMON: DRP[18] bit 9	GTX_COMMON: DRP[66] bit 8 GTX_COMMON: RSVD_ATTR0 bit 8	GTX_COMMON: DRP[66] bit 9 GTX_COMMON: RSVD_ATTR0 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[18] bit 6	GTX_COMMON: DRP[18] bit 7	GTX_COMMON: DRP[66] bit 6 GTX_COMMON: RSVD_ATTR0 bit 6	GTX_COMMON: DRP[66] bit 7 GTX_COMMON: RSVD_ATTR0 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[18] bit 4	GTX_COMMON: DRP[18] bit 5	GTX_COMMON: DRP[66] bit 4 GTX_COMMON: RSVD_ATTR0 bit 4	GTX_COMMON: DRP[66] bit 5 GTX_COMMON: RSVD_ATTR0 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[18] bit 2	GTX_COMMON: DRP[18] bit 3	GTX_COMMON: DRP[66] bit 2 GTX_COMMON: RSVD_ATTR0 bit 2	GTX_COMMON: DRP[66] bit 3 GTX_COMMON: RSVD_ATTR0 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[18] bit 0	GTX_COMMON: DRP[18] bit 1	GTX_COMMON: DRP[66] bit 0 GTX_COMMON: RSVD_ATTR0 bit 0	GTX_COMMON: DRP[66] bit 1 GTX_COMMON: RSVD_ATTR0 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[17] bit 14	GTX_COMMON: DRP[17] bit 15	GTX_COMMON: DRP[65] bit 14 GTX_COMMON: BIAS_CFG bit 62	GTX_COMMON: DRP[65] bit 15 GTX_COMMON: BIAS_CFG bit 63
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[17] bit 12	GTX_COMMON: DRP[17] bit 13	GTX_COMMON: DRP[65] bit 12 GTX_COMMON: BIAS_CFG bit 60	GTX_COMMON: DRP[65] bit 13 GTX_COMMON: BIAS_CFG bit 61
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[17] bit 10	GTX_COMMON: DRP[17] bit 11	GTX_COMMON: DRP[65] bit 10 GTX_COMMON: BIAS_CFG bit 58	GTX_COMMON: DRP[65] bit 11 GTX_COMMON: BIAS_CFG bit 59
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[17] bit 8	GTX_COMMON: DRP[17] bit 9	GTX_COMMON: DRP[65] bit 8 GTX_COMMON: BIAS_CFG bit 56	GTX_COMMON: DRP[65] bit 9 GTX_COMMON: BIAS_CFG bit 57
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[17] bit 6	GTX_COMMON: DRP[17] bit 7	GTX_COMMON: DRP[65] bit 6 GTX_COMMON: BIAS_CFG bit 54	GTX_COMMON: DRP[65] bit 7 GTX_COMMON: BIAS_CFG bit 55
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[17] bit 4	GTX_COMMON: DRP[17] bit 5	GTX_COMMON: DRP[65] bit 4 GTX_COMMON: BIAS_CFG bit 52	GTX_COMMON: DRP[65] bit 5 GTX_COMMON: BIAS_CFG bit 53
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[17] bit 2	GTX_COMMON: DRP[17] bit 3	GTX_COMMON: DRP[65] bit 2 GTX_COMMON: BIAS_CFG bit 50	GTX_COMMON: DRP[65] bit 3 GTX_COMMON: BIAS_CFG bit 51
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[17] bit 0	GTX_COMMON: DRP[17] bit 1	GTX_COMMON: DRP[65] bit 0 GTX_COMMON: BIAS_CFG bit 48	GTX_COMMON: DRP[65] bit 1 GTX_COMMON: BIAS_CFG bit 49
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[16] bit 14	GTX_COMMON: DRP[16] bit 15	GTX_COMMON: DRP[64] bit 14 GTX_COMMON: BIAS_CFG bit 46	GTX_COMMON: DRP[64] bit 15 GTX_COMMON: BIAS_CFG bit 47
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[16] bit 12	GTX_COMMON: DRP[16] bit 13	GTX_COMMON: DRP[64] bit 12 GTX_COMMON: BIAS_CFG bit 44	GTX_COMMON: DRP[64] bit 13 GTX_COMMON: BIAS_CFG bit 45
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[16] bit 10	GTX_COMMON: DRP[16] bit 11	GTX_COMMON: DRP[64] bit 10 GTX_COMMON: BIAS_CFG bit 42	GTX_COMMON: DRP[64] bit 11 GTX_COMMON: BIAS_CFG bit 43
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[16] bit 8	GTX_COMMON: DRP[16] bit 9	GTX_COMMON: DRP[64] bit 8 GTX_COMMON: BIAS_CFG bit 40	GTX_COMMON: DRP[64] bit 9 GTX_COMMON: BIAS_CFG bit 41
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[16] bit 6	GTX_COMMON: DRP[16] bit 7	GTX_COMMON: DRP[64] bit 6 GTX_COMMON: BIAS_CFG bit 38	GTX_COMMON: DRP[64] bit 7 GTX_COMMON: BIAS_CFG bit 39
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[16] bit 4	GTX_COMMON: DRP[16] bit 5	GTX_COMMON: DRP[64] bit 4 GTX_COMMON: BIAS_CFG bit 36	GTX_COMMON: DRP[64] bit 5 GTX_COMMON: BIAS_CFG bit 37
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[16] bit 2	GTX_COMMON: DRP[16] bit 3	GTX_COMMON: DRP[64] bit 2 GTX_COMMON: BIAS_CFG bit 34	GTX_COMMON: DRP[64] bit 3 GTX_COMMON: BIAS_CFG bit 35
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[16] bit 0	GTX_COMMON: DRP[16] bit 1	GTX_COMMON: DRP[64] bit 0 GTX_COMMON: BIAS_CFG bit 32	GTX_COMMON: DRP[64] bit 1 GTX_COMMON: BIAS_CFG bit 33

virtex7 GTH_COMMON rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[31] bit 14	GTX_COMMON: DRP[31] bit 15	GTX_COMMON: DRP[79] bit 14	GTX_COMMON: DRP[79] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[31] bit 12	GTX_COMMON: DRP[31] bit 13	GTX_COMMON: DRP[79] bit 12	GTX_COMMON: DRP[79] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[31] bit 10	GTX_COMMON: DRP[31] bit 11	GTX_COMMON: DRP[79] bit 10	GTX_COMMON: DRP[79] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[31] bit 8	GTX_COMMON: DRP[31] bit 9	GTX_COMMON: DRP[79] bit 8	GTX_COMMON: DRP[79] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[31] bit 6	GTX_COMMON: DRP[31] bit 7	GTX_COMMON: DRP[79] bit 6	GTX_COMMON: DRP[79] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[31] bit 4	GTX_COMMON: DRP[31] bit 5	GTX_COMMON: DRP[79] bit 4	GTX_COMMON: DRP[79] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[31] bit 2	GTX_COMMON: DRP[31] bit 3	GTX_COMMON: DRP[79] bit 2	GTX_COMMON: DRP[79] bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[31] bit 0	GTX_COMMON: DRP[31] bit 1	GTX_COMMON: DRP[79] bit 0	GTX_COMMON: DRP[79] bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[30] bit 14	GTX_COMMON: DRP[30] bit 15	GTX_COMMON: DRP[78] bit 14	GTX_COMMON: DRP[78] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[30] bit 12	GTX_COMMON: DRP[30] bit 13	GTX_COMMON: DRP[78] bit 12	GTX_COMMON: DRP[78] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[30] bit 10	GTX_COMMON: DRP[30] bit 11	GTX_COMMON: DRP[78] bit 10	GTX_COMMON: DRP[78] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[30] bit 8	GTX_COMMON: DRP[30] bit 9	GTX_COMMON: DRP[78] bit 8	GTX_COMMON: DRP[78] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[30] bit 6	GTX_COMMON: DRP[30] bit 7	GTX_COMMON: DRP[78] bit 6	GTX_COMMON: DRP[78] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[30] bit 4	GTX_COMMON: DRP[30] bit 5	GTX_COMMON: DRP[78] bit 4	GTX_COMMON: DRP[78] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[30] bit 2	GTX_COMMON: DRP[30] bit 3	GTX_COMMON: DRP[78] bit 2	GTX_COMMON: DRP[78] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[30] bit 0	GTX_COMMON: DRP[30] bit 1	GTX_COMMON: DRP[78] bit 0	GTX_COMMON: DRP[78] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[29] bit 14	GTX_COMMON: DRP[29] bit 15	GTX_COMMON: DRP[77] bit 14	GTX_COMMON: DRP[77] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[29] bit 12	GTX_COMMON: DRP[29] bit 13	GTX_COMMON: DRP[77] bit 12	GTX_COMMON: DRP[77] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[29] bit 10	GTX_COMMON: DRP[29] bit 11	GTX_COMMON: DRP[77] bit 10	GTX_COMMON: DRP[77] bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[29] bit 8	GTX_COMMON: DRP[29] bit 9	GTX_COMMON: DRP[77] bit 8	GTX_COMMON: DRP[77] bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[29] bit 6	GTX_COMMON: DRP[29] bit 7	GTX_COMMON: DRP[77] bit 6	GTX_COMMON: DRP[77] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[29] bit 4	GTX_COMMON: DRP[29] bit 5	GTX_COMMON: DRP[77] bit 4	GTX_COMMON: DRP[77] bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[29] bit 2	GTX_COMMON: DRP[29] bit 3	GTX_COMMON: DRP[77] bit 2	GTX_COMMON: DRP[77] bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[29] bit 0	GTX_COMMON: DRP[29] bit 1	GTX_COMMON: DRP[77] bit 0	GTX_COMMON: DRP[77] bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[28] bit 14	GTX_COMMON: DRP[28] bit 15	GTX_COMMON: DRP[76] bit 14	GTX_COMMON: DRP[76] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[28] bit 12	GTX_COMMON: DRP[28] bit 13	GTX_COMMON: DRP[76] bit 12	GTX_COMMON: DRP[76] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[28] bit 10	GTX_COMMON: DRP[28] bit 11	GTX_COMMON: DRP[76] bit 10	GTX_COMMON: DRP[76] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[28] bit 8	GTX_COMMON: DRP[28] bit 9	GTX_COMMON: DRP[76] bit 8	GTX_COMMON: DRP[76] bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[28] bit 6	GTX_COMMON: DRP[28] bit 7	GTX_COMMON: DRP[76] bit 6	GTX_COMMON: DRP[76] bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[28] bit 4	GTX_COMMON: DRP[28] bit 5	GTX_COMMON: DRP[76] bit 4	GTX_COMMON: DRP[76] bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[28] bit 2	GTX_COMMON: DRP[28] bit 3	GTX_COMMON: DRP[76] bit 2	GTX_COMMON: DRP[76] bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[28] bit 0	GTX_COMMON: DRP[28] bit 1	GTX_COMMON: DRP[76] bit 0	GTX_COMMON: DRP[76] bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[27] bit 14	GTX_COMMON: DRP[27] bit 15	GTX_COMMON: DRP[75] bit 14	GTX_COMMON: DRP[75] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[27] bit 12	GTX_COMMON: DRP[27] bit 13	GTX_COMMON: DRP[75] bit 12	GTX_COMMON: DRP[75] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[27] bit 10	GTX_COMMON: DRP[27] bit 11	GTX_COMMON: DRP[75] bit 10	GTX_COMMON: DRP[75] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[27] bit 8	GTX_COMMON: DRP[27] bit 9	GTX_COMMON: DRP[75] bit 8	GTX_COMMON: DRP[75] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[27] bit 6	GTX_COMMON: DRP[27] bit 7	GTX_COMMON: DRP[75] bit 6	GTX_COMMON: DRP[75] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[27] bit 4	GTX_COMMON: DRP[27] bit 5	GTX_COMMON: DRP[75] bit 4	GTX_COMMON: DRP[75] bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[27] bit 2	GTX_COMMON: DRP[27] bit 3	GTX_COMMON: DRP[75] bit 2	GTX_COMMON: DRP[75] bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[27] bit 0	GTX_COMMON: DRP[27] bit 1	GTX_COMMON: DRP[75] bit 0	GTX_COMMON: DRP[75] bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[26] bit 14	GTX_COMMON: DRP[26] bit 15	GTX_COMMON: DRP[74] bit 14	GTX_COMMON: DRP[74] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[26] bit 12	GTX_COMMON: DRP[26] bit 13	GTX_COMMON: DRP[74] bit 12	GTX_COMMON: DRP[74] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[26] bit 10	GTX_COMMON: DRP[26] bit 11	GTX_COMMON: DRP[74] bit 10	GTX_COMMON: DRP[74] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[26] bit 8	GTX_COMMON: DRP[26] bit 9	GTX_COMMON: DRP[74] bit 8	GTX_COMMON: DRP[74] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[26] bit 6	GTX_COMMON: DRP[26] bit 7	GTX_COMMON: DRP[74] bit 6	GTX_COMMON: DRP[74] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[26] bit 4	GTX_COMMON: DRP[26] bit 5	GTX_COMMON: DRP[74] bit 4	GTX_COMMON: DRP[74] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[26] bit 2	GTX_COMMON: DRP[26] bit 3	GTX_COMMON: DRP[74] bit 2	GTX_COMMON: DRP[74] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[26] bit 0	GTX_COMMON: DRP[26] bit 1	GTX_COMMON: DRP[74] bit 0	GTX_COMMON: DRP[74] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[25] bit 14	GTX_COMMON: DRP[25] bit 15	GTX_COMMON: DRP[73] bit 14	GTX_COMMON: DRP[73] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[25] bit 12	GTX_COMMON: DRP[25] bit 13	GTX_COMMON: DRP[73] bit 12	GTX_COMMON: DRP[73] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[25] bit 10	GTX_COMMON: DRP[25] bit 11	GTX_COMMON: DRP[73] bit 10	GTX_COMMON: DRP[73] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[25] bit 8	GTX_COMMON: DRP[25] bit 9	GTX_COMMON: DRP[73] bit 8	GTX_COMMON: DRP[73] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[25] bit 6	GTX_COMMON: DRP[25] bit 7	GTX_COMMON: DRP[73] bit 6	GTX_COMMON: DRP[73] bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[25] bit 4	GTX_COMMON: DRP[25] bit 5	GTX_COMMON: DRP[73] bit 4	GTX_COMMON: DRP[73] bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[25] bit 2	GTX_COMMON: DRP[25] bit 3	GTX_COMMON: DRP[73] bit 2	GTX_COMMON: DRP[73] bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[25] bit 0	GTX_COMMON: DRP[25] bit 1	GTX_COMMON: DRP[73] bit 0	GTX_COMMON: DRP[73] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[24] bit 14	GTX_COMMON: DRP[24] bit 15	GTX_COMMON: DRP[72] bit 14	GTX_COMMON: DRP[72] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[24] bit 12	GTX_COMMON: DRP[24] bit 13	GTX_COMMON: DRP[72] bit 12	GTX_COMMON: DRP[72] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[24] bit 10	GTX_COMMON: DRP[24] bit 11	GTX_COMMON: DRP[72] bit 10	GTX_COMMON: DRP[72] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[24] bit 8	GTX_COMMON: DRP[24] bit 9	GTX_COMMON: DRP[72] bit 8	GTX_COMMON: DRP[72] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[24] bit 6	GTX_COMMON: DRP[24] bit 7	GTX_COMMON: DRP[72] bit 6	GTX_COMMON: DRP[72] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[24] bit 4	GTX_COMMON: DRP[24] bit 5	GTX_COMMON: DRP[72] bit 4	GTX_COMMON: DRP[72] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[24] bit 2	GTX_COMMON: DRP[24] bit 3	GTX_COMMON: DRP[72] bit 2	GTX_COMMON: DRP[72] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[24] bit 0	GTX_COMMON: DRP[24] bit 1	GTX_COMMON: DRP[72] bit 0	GTX_COMMON: DRP[72] bit 1

virtex7 GTH_COMMON rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[39] bit 14	GTX_COMMON: DRP[39] bit 15	GTX_COMMON: DRP[87] bit 14	GTX_COMMON: DRP[87] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[39] bit 12	GTX_COMMON: DRP[39] bit 13	GTX_COMMON: DRP[87] bit 12	GTX_COMMON: DRP[87] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[39] bit 10	GTX_COMMON: DRP[39] bit 11	GTX_COMMON: DRP[87] bit 10	GTX_COMMON: DRP[87] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[39] bit 8	GTX_COMMON: DRP[39] bit 9	GTX_COMMON: DRP[87] bit 8	GTX_COMMON: DRP[87] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[39] bit 6	GTX_COMMON: DRP[39] bit 7	GTX_COMMON: DRP[87] bit 6	GTX_COMMON: DRP[87] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[39] bit 4	GTX_COMMON: DRP[39] bit 5	GTX_COMMON: DRP[87] bit 4	GTX_COMMON: DRP[87] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[39] bit 2	GTX_COMMON: DRP[39] bit 3	GTX_COMMON: DRP[87] bit 2	GTX_COMMON: DRP[87] bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[39] bit 0	GTX_COMMON: DRP[39] bit 1	GTX_COMMON: DRP[87] bit 0	GTX_COMMON: DRP[87] bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[38] bit 14	GTX_COMMON: DRP[38] bit 15	GTX_COMMON: DRP[86] bit 14	GTX_COMMON: DRP[86] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[38] bit 12	GTX_COMMON: DRP[38] bit 13	GTX_COMMON: DRP[86] bit 12	GTX_COMMON: DRP[86] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[38] bit 10	GTX_COMMON: DRP[38] bit 11	GTX_COMMON: DRP[86] bit 10	GTX_COMMON: DRP[86] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[38] bit 8	GTX_COMMON: DRP[38] bit 9	GTX_COMMON: DRP[86] bit 8	GTX_COMMON: DRP[86] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[38] bit 6	GTX_COMMON: DRP[38] bit 7	GTX_COMMON: DRP[86] bit 6	GTX_COMMON: DRP[86] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[38] bit 4	GTX_COMMON: DRP[38] bit 5	GTX_COMMON: DRP[86] bit 4	GTX_COMMON: DRP[86] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[38] bit 2	GTX_COMMON: DRP[38] bit 3	GTX_COMMON: DRP[86] bit 2	GTX_COMMON: DRP[86] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[38] bit 0	GTX_COMMON: DRP[38] bit 1	GTX_COMMON: DRP[86] bit 0	GTX_COMMON: DRP[86] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[37] bit 14	GTX_COMMON: DRP[37] bit 15	GTX_COMMON: DRP[85] bit 14	GTX_COMMON: DRP[85] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[37] bit 12	GTX_COMMON: DRP[37] bit 13	GTX_COMMON: DRP[85] bit 12	GTX_COMMON: DRP[85] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[37] bit 10	GTX_COMMON: DRP[37] bit 11	GTX_COMMON: DRP[85] bit 10	GTX_COMMON: DRP[85] bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[37] bit 8	GTX_COMMON: DRP[37] bit 9	GTX_COMMON: DRP[85] bit 8	GTX_COMMON: DRP[85] bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[37] bit 6	GTX_COMMON: DRP[37] bit 7	GTX_COMMON: DRP[85] bit 6	GTX_COMMON: DRP[85] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[37] bit 4	GTX_COMMON: DRP[37] bit 5	GTX_COMMON: DRP[85] bit 4	GTX_COMMON: DRP[85] bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[37] bit 2	GTX_COMMON: DRP[37] bit 3	GTX_COMMON: DRP[85] bit 2	GTX_COMMON: DRP[85] bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[37] bit 0	GTX_COMMON: DRP[37] bit 1	GTX_COMMON: DRP[85] bit 0	GTX_COMMON: DRP[85] bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[36] bit 14	GTX_COMMON: DRP[36] bit 15	GTX_COMMON: DRP[84] bit 14	GTX_COMMON: DRP[84] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[36] bit 12	GTX_COMMON: DRP[36] bit 13	GTX_COMMON: DRP[84] bit 12	GTX_COMMON: DRP[84] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[36] bit 10	GTX_COMMON: DRP[36] bit 11	GTX_COMMON: DRP[84] bit 10	GTX_COMMON: DRP[84] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[36] bit 8	GTX_COMMON: DRP[36] bit 9	GTX_COMMON: DRP[84] bit 8	GTX_COMMON: DRP[84] bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[36] bit 6	GTX_COMMON: DRP[36] bit 7	GTX_COMMON: DRP[84] bit 6	GTX_COMMON: DRP[84] bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[36] bit 4	GTX_COMMON: DRP[36] bit 5	GTX_COMMON: DRP[84] bit 4	GTX_COMMON: DRP[84] bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[36] bit 2	GTX_COMMON: DRP[36] bit 3	GTX_COMMON: DRP[84] bit 2	GTX_COMMON: DRP[84] bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[36] bit 0	GTX_COMMON: DRP[36] bit 1	GTX_COMMON: DRP[84] bit 0	GTX_COMMON: DRP[84] bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[35] bit 14	GTX_COMMON: DRP[35] bit 15	GTX_COMMON: DRP[83] bit 14	GTX_COMMON: DRP[83] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[35] bit 12	GTX_COMMON: DRP[35] bit 13	GTX_COMMON: DRP[83] bit 12	GTX_COMMON: DRP[83] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[35] bit 10	GTX_COMMON: DRP[35] bit 11	GTX_COMMON: DRP[83] bit 10	GTX_COMMON: DRP[83] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[35] bit 8	GTX_COMMON: DRP[35] bit 9	GTX_COMMON: DRP[83] bit 8	GTX_COMMON: DRP[83] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[35] bit 6	GTX_COMMON: DRP[35] bit 7	GTX_COMMON: DRP[83] bit 6	GTX_COMMON: DRP[83] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[35] bit 4	GTX_COMMON: DRP[35] bit 5	GTX_COMMON: DRP[83] bit 4	GTX_COMMON: DRP[83] bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[35] bit 2	GTX_COMMON: DRP[35] bit 3	GTX_COMMON: DRP[83] bit 2	GTX_COMMON: DRP[83] bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[35] bit 0	GTX_COMMON: DRP[35] bit 1	GTX_COMMON: DRP[83] bit 0	GTX_COMMON: DRP[83] bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[34] bit 14	GTX_COMMON: DRP[34] bit 15	GTX_COMMON: DRP[82] bit 14	GTX_COMMON: DRP[82] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[34] bit 12	GTX_COMMON: DRP[34] bit 13	GTX_COMMON: DRP[82] bit 12	GTX_COMMON: DRP[82] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[34] bit 10	GTX_COMMON: DRP[34] bit 11	GTX_COMMON: DRP[82] bit 10	GTX_COMMON: DRP[82] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[34] bit 8	GTX_COMMON: DRP[34] bit 9	GTX_COMMON: DRP[82] bit 8	GTX_COMMON: DRP[82] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[34] bit 6	GTX_COMMON: DRP[34] bit 7	GTX_COMMON: DRP[82] bit 6	GTX_COMMON: DRP[82] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[34] bit 4	GTX_COMMON: DRP[34] bit 5	GTX_COMMON: DRP[82] bit 4	GTX_COMMON: DRP[82] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[34] bit 2	GTX_COMMON: DRP[34] bit 3	GTX_COMMON: DRP[82] bit 2	GTX_COMMON: DRP[82] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[34] bit 0	GTX_COMMON: DRP[34] bit 1	GTX_COMMON: DRP[82] bit 0	GTX_COMMON: DRP[82] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[33] bit 14	GTX_COMMON: DRP[33] bit 15	GTX_COMMON: DRP[81] bit 14	GTX_COMMON: DRP[81] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[33] bit 12	GTX_COMMON: DRP[33] bit 13	GTX_COMMON: DRP[81] bit 12	GTX_COMMON: DRP[81] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[33] bit 10	GTX_COMMON: DRP[33] bit 11	GTX_COMMON: DRP[81] bit 10	GTX_COMMON: DRP[81] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[33] bit 8	GTX_COMMON: DRP[33] bit 9	GTX_COMMON: DRP[81] bit 8	GTX_COMMON: DRP[81] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[33] bit 6	GTX_COMMON: DRP[33] bit 7	GTX_COMMON: DRP[81] bit 6	GTX_COMMON: DRP[81] bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[33] bit 4	GTX_COMMON: DRP[33] bit 5	GTX_COMMON: DRP[81] bit 4	GTX_COMMON: DRP[81] bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[33] bit 2	GTX_COMMON: DRP[33] bit 3	GTX_COMMON: DRP[81] bit 2	GTX_COMMON: DRP[81] bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[33] bit 0	GTX_COMMON: DRP[33] bit 1	GTX_COMMON: DRP[81] bit 0	GTX_COMMON: DRP[81] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[32] bit 14	GTX_COMMON: DRP[32] bit 15	GTX_COMMON: DRP[80] bit 14	GTX_COMMON: DRP[80] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[32] bit 12	GTX_COMMON: DRP[32] bit 13	GTX_COMMON: DRP[80] bit 12	GTX_COMMON: DRP[80] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[32] bit 10	GTX_COMMON: DRP[32] bit 11	GTX_COMMON: DRP[80] bit 10	GTX_COMMON: DRP[80] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[32] bit 8	GTX_COMMON: DRP[32] bit 9	GTX_COMMON: DRP[80] bit 8	GTX_COMMON: DRP[80] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[32] bit 6	GTX_COMMON: DRP[32] bit 7	GTX_COMMON: DRP[80] bit 6	GTX_COMMON: DRP[80] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[32] bit 4	GTX_COMMON: DRP[32] bit 5	GTX_COMMON: DRP[80] bit 4	GTX_COMMON: DRP[80] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[32] bit 2	GTX_COMMON: DRP[32] bit 3	GTX_COMMON: DRP[80] bit 2	GTX_COMMON: DRP[80] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[32] bit 0	GTX_COMMON: DRP[32] bit 1	GTX_COMMON: DRP[80] bit 0	GTX_COMMON: DRP[80] bit 1

virtex7 GTH_COMMON rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[47] bit 14	GTX_COMMON: DRP[47] bit 15	GTX_COMMON: DRP[95] bit 14	GTX_COMMON: DRP[95] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[47] bit 12	GTX_COMMON: DRP[47] bit 13	GTX_COMMON: DRP[95] bit 12	GTX_COMMON: DRP[95] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[47] bit 10	GTX_COMMON: DRP[47] bit 11	GTX_COMMON: DRP[95] bit 10	GTX_COMMON: DRP[95] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[47] bit 8	GTX_COMMON: DRP[47] bit 9	GTX_COMMON: DRP[95] bit 8	GTX_COMMON: DRP[95] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[47] bit 6	GTX_COMMON: DRP[47] bit 7	GTX_COMMON: DRP[95] bit 6	GTX_COMMON: DRP[95] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[47] bit 4	GTX_COMMON: DRP[47] bit 5	GTX_COMMON: DRP[95] bit 4	GTX_COMMON: DRP[95] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[47] bit 2	GTX_COMMON: DRP[47] bit 3	GTX_COMMON: DRP[95] bit 2	GTX_COMMON: DRP[95] bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[47] bit 0	GTX_COMMON: DRP[47] bit 1	GTX_COMMON: DRP[95] bit 0	GTX_COMMON: DRP[95] bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[46] bit 14	GTX_COMMON: DRP[46] bit 15	GTX_COMMON: DRP[94] bit 14	GTX_COMMON: DRP[94] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[46] bit 12	GTX_COMMON: DRP[46] bit 13	GTX_COMMON: DRP[94] bit 12	GTX_COMMON: DRP[94] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[46] bit 10	GTX_COMMON: DRP[46] bit 11	GTX_COMMON: DRP[94] bit 10	GTX_COMMON: DRP[94] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[46] bit 8	GTX_COMMON: DRP[46] bit 9	GTX_COMMON: DRP[94] bit 8	GTX_COMMON: DRP[94] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[46] bit 6	GTX_COMMON: DRP[46] bit 7	GTX_COMMON: DRP[94] bit 6	GTX_COMMON: DRP[94] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[46] bit 4	GTX_COMMON: DRP[46] bit 5	GTX_COMMON: DRP[94] bit 4	GTX_COMMON: DRP[94] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[46] bit 2	GTX_COMMON: DRP[46] bit 3	GTX_COMMON: DRP[94] bit 2	GTX_COMMON: DRP[94] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[46] bit 0	GTX_COMMON: DRP[46] bit 1	GTX_COMMON: DRP[94] bit 0	GTX_COMMON: DRP[94] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[45] bit 14	GTX_COMMON: DRP[45] bit 15	GTX_COMMON: DRP[93] bit 14	GTX_COMMON: DRP[93] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[45] bit 12	GTX_COMMON: DRP[45] bit 13	GTX_COMMON: DRP[93] bit 12	GTX_COMMON: DRP[93] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[45] bit 10	GTX_COMMON: DRP[45] bit 11	GTX_COMMON: DRP[93] bit 10	GTX_COMMON: DRP[93] bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[45] bit 8	GTX_COMMON: DRP[45] bit 9	GTX_COMMON: DRP[93] bit 8	GTX_COMMON: DRP[93] bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[45] bit 6	GTX_COMMON: DRP[45] bit 7	GTX_COMMON: DRP[93] bit 6	GTX_COMMON: DRP[93] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[45] bit 4	GTX_COMMON: DRP[45] bit 5	GTX_COMMON: DRP[93] bit 4	GTX_COMMON: DRP[93] bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[45] bit 2	GTX_COMMON: DRP[45] bit 3	GTX_COMMON: DRP[93] bit 2	GTX_COMMON: DRP[93] bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[45] bit 0	GTX_COMMON: DRP[45] bit 1	GTX_COMMON: DRP[93] bit 0	GTX_COMMON: DRP[93] bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[44] bit 14	GTX_COMMON: DRP[44] bit 15	GTX_COMMON: DRP[92] bit 14	GTX_COMMON: DRP[92] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[44] bit 12	GTX_COMMON: DRP[44] bit 13	GTX_COMMON: DRP[92] bit 12	GTX_COMMON: DRP[92] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[44] bit 10	GTX_COMMON: DRP[44] bit 11	GTX_COMMON: DRP[92] bit 10	GTX_COMMON: DRP[92] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[44] bit 8	GTX_COMMON: DRP[44] bit 9	GTX_COMMON: DRP[92] bit 8	GTX_COMMON: DRP[92] bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[44] bit 6	GTX_COMMON: DRP[44] bit 7	GTX_COMMON: DRP[92] bit 6	GTX_COMMON: DRP[92] bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[44] bit 4	GTX_COMMON: DRP[44] bit 5	GTX_COMMON: DRP[92] bit 4	GTX_COMMON: DRP[92] bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[44] bit 2	GTX_COMMON: DRP[44] bit 3	GTX_COMMON: DRP[92] bit 2	GTX_COMMON: DRP[92] bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[44] bit 0	GTX_COMMON: DRP[44] bit 1	GTX_COMMON: DRP[92] bit 0	GTX_COMMON: DRP[92] bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[43] bit 14	GTX_COMMON: DRP[43] bit 15	GTX_COMMON: DRP[91] bit 14	GTX_COMMON: DRP[91] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[43] bit 12	GTX_COMMON: DRP[43] bit 13	GTX_COMMON: DRP[91] bit 12	GTX_COMMON: DRP[91] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[43] bit 10	GTX_COMMON: DRP[43] bit 11	GTX_COMMON: DRP[91] bit 10	GTX_COMMON: DRP[91] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[43] bit 8	GTX_COMMON: DRP[43] bit 9	GTX_COMMON: DRP[91] bit 8	GTX_COMMON: DRP[91] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[43] bit 6	GTX_COMMON: DRP[43] bit 7	GTX_COMMON: DRP[91] bit 6	GTX_COMMON: DRP[91] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[43] bit 4	GTX_COMMON: DRP[43] bit 5	GTX_COMMON: DRP[91] bit 4	GTX_COMMON: DRP[91] bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[43] bit 2	GTX_COMMON: DRP[43] bit 3	GTX_COMMON: DRP[91] bit 2	GTX_COMMON: DRP[91] bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[43] bit 0	GTX_COMMON: DRP[43] bit 1	GTX_COMMON: DRP[91] bit 0	GTX_COMMON: DRP[91] bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[42] bit 14	GTX_COMMON: DRP[42] bit 15	GTX_COMMON: DRP[90] bit 14	GTX_COMMON: DRP[90] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[42] bit 12	GTX_COMMON: DRP[42] bit 13	GTX_COMMON: DRP[90] bit 12	GTX_COMMON: DRP[90] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[42] bit 10	GTX_COMMON: DRP[42] bit 11	GTX_COMMON: DRP[90] bit 10	GTX_COMMON: DRP[90] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[42] bit 8	GTX_COMMON: DRP[42] bit 9	GTX_COMMON: DRP[90] bit 8	GTX_COMMON: DRP[90] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[42] bit 6	GTX_COMMON: DRP[42] bit 7	GTX_COMMON: DRP[90] bit 6	GTX_COMMON: DRP[90] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[42] bit 4	GTX_COMMON: DRP[42] bit 5	GTX_COMMON: DRP[90] bit 4	GTX_COMMON: DRP[90] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[42] bit 2	GTX_COMMON: DRP[42] bit 3	GTX_COMMON: DRP[90] bit 2	GTX_COMMON: DRP[90] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[42] bit 0	GTX_COMMON: DRP[42] bit 1	GTX_COMMON: DRP[90] bit 0	GTX_COMMON: DRP[90] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[41] bit 14	GTX_COMMON: DRP[41] bit 15	GTX_COMMON: DRP[89] bit 14	GTX_COMMON: DRP[89] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[41] bit 12	GTX_COMMON: DRP[41] bit 13	GTX_COMMON: DRP[89] bit 12	GTX_COMMON: DRP[89] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[41] bit 10	GTX_COMMON: DRP[41] bit 11	GTX_COMMON: DRP[89] bit 10	GTX_COMMON: DRP[89] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[41] bit 8	GTX_COMMON: DRP[41] bit 9	GTX_COMMON: DRP[89] bit 8	GTX_COMMON: DRP[89] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[41] bit 6	GTX_COMMON: DRP[41] bit 7	GTX_COMMON: DRP[89] bit 6	GTX_COMMON: DRP[89] bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[41] bit 4	GTX_COMMON: DRP[41] bit 5	GTX_COMMON: DRP[89] bit 4	GTX_COMMON: DRP[89] bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[41] bit 2	GTX_COMMON: DRP[41] bit 3	GTX_COMMON: DRP[89] bit 2	GTX_COMMON: DRP[89] bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[41] bit 0	GTX_COMMON: DRP[41] bit 1	GTX_COMMON: DRP[89] bit 0	GTX_COMMON: DRP[89] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[40] bit 14	GTX_COMMON: DRP[40] bit 15	GTX_COMMON: DRP[88] bit 14	GTX_COMMON: DRP[88] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[40] bit 12	GTX_COMMON: DRP[40] bit 13	GTX_COMMON: DRP[88] bit 12	GTX_COMMON: DRP[88] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[40] bit 10	GTX_COMMON: DRP[40] bit 11	GTX_COMMON: DRP[88] bit 10	GTX_COMMON: DRP[88] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[40] bit 8	GTX_COMMON: DRP[40] bit 9	GTX_COMMON: DRP[88] bit 8	GTX_COMMON: DRP[88] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[40] bit 6	GTX_COMMON: DRP[40] bit 7	GTX_COMMON: DRP[88] bit 6	GTX_COMMON: DRP[88] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[40] bit 4	GTX_COMMON: DRP[40] bit 5	GTX_COMMON: DRP[88] bit 4	GTX_COMMON: DRP[88] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[40] bit 2	GTX_COMMON: DRP[40] bit 3	GTX_COMMON: DRP[88] bit 2	GTX_COMMON: DRP[88] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_COMMON: DRP[40] bit 0	GTX_COMMON: DRP[40] bit 1	GTX_COMMON: DRP[88] bit 0	GTX_COMMON: DRP[88] bit 1

Tile GTH_CHANNEL

Cells: 11

Bels GTX_CHANNEL

virtex7 GTH_CHANNEL bel GTX_CHANNEL pins
Pin	Direction	GTX_CHANNEL
CFGRESET	in	CELL[5].IMUX_CTRL[1]
CLKRSVD[0]	in	CELL[7].IMUX_CLK[1] invert by MAIN[0][30][23]
CLKRSVD[1]	in	CELL[8].IMUX_CLK[1] invert by MAIN[0][31][23]
CPLLLOCKDETCLK	in	CELL[2].IMUX_CLK[0] invert by MAIN[0][31][0]
CPLLLOCKEN	in	CELL[2].IMUX_IMUX_DELAY[28]
CPLLPD	in	CELL[2].IMUX_IMUX_DELAY[36]
CPLLREFCLKSEL0	in	CELL[2].IMUX_IMUX_DELAY[15]
CPLLREFCLKSEL1	in	CELL[2].IMUX_IMUX_DELAY[14]
CPLLREFCLKSEL2	in	CELL[2].IMUX_IMUX_DELAY[11]
CPLLRESET	in	CELL[3].IMUX_CTRL[0]
DMONFIFORESET	in	CELL[1].IMUX_IMUX_DELAY[46]
DMONITORCLK	in	CELL[5].IMUX_CLK[1] invert by MAIN[0][30][13]
DRPCLK	in	CELL[1].IMUX_CLK[1] invert by MAIN[0][31][1]
DRPEN	in	CELL[3].IMUX_IMUX_DELAY[44]
DRPWE	in	CELL[3].IMUX_IMUX_DELAY[28]
DRPADDR[0]	in	CELL[2].IMUX_IMUX_DELAY[39]
DRPADDR[1]	in	CELL[2].IMUX_IMUX_DELAY[38]
DRPADDR[2]	in	CELL[2].IMUX_IMUX_DELAY[35]
DRPADDR[3]	in	CELL[2].IMUX_IMUX_DELAY[34]
DRPADDR[4]	in	CELL[3].IMUX_IMUX_DELAY[39]
DRPADDR[5]	in	CELL[3].IMUX_IMUX_DELAY[38]
DRPADDR[6]	in	CELL[3].IMUX_IMUX_DELAY[35]
DRPADDR[7]	in	CELL[3].IMUX_IMUX_DELAY[34]
DRPADDR[8]	in	CELL[3].IMUX_IMUX_DELAY[2]
DRPDI[0]	in	CELL[0].IMUX_IMUX_DELAY[39]
DRPDI[1]	in	CELL[0].IMUX_IMUX_DELAY[38]
DRPDI[2]	in	CELL[0].IMUX_IMUX_DELAY[35]
DRPDI[3]	in	CELL[0].IMUX_IMUX_DELAY[34]
DRPDI[4]	in	CELL[1].IMUX_IMUX_DELAY[39]
DRPDI[5]	in	CELL[1].IMUX_IMUX_DELAY[38]
DRPDI[6]	in	CELL[1].IMUX_IMUX_DELAY[35]
DRPDI[7]	in	CELL[1].IMUX_IMUX_DELAY[34]
DRPDI[8]	in	CELL[0].IMUX_IMUX_DELAY[37]
DRPDI[9]	in	CELL[0].IMUX_IMUX_DELAY[36]
DRPDI[10]	in	CELL[0].IMUX_IMUX_DELAY[33]
DRPDI[11]	in	CELL[0].IMUX_IMUX_DELAY[32]
DRPDI[12]	in	CELL[1].IMUX_IMUX_DELAY[37]
DRPDI[13]	in	CELL[1].IMUX_IMUX_DELAY[36]
DRPDI[14]	in	CELL[1].IMUX_IMUX_DELAY[33]
DRPDI[15]	in	CELL[1].IMUX_IMUX_DELAY[32]
EYESCANMODE	in	CELL[0].IMUX_IMUX_DELAY[41]
EYESCANRESET	in	CELL[8].IMUX_IMUX_DELAY[45]
EYESCANTRIGGER	in	CELL[8].IMUX_IMUX_DELAY[31]
GTGREFCLK	in	CELL[6].IMUX_CLK[1] invert by MAIN[0][30][0]
GTRESETSEL	in	CELL[10].IMUX_CTRL[0]
GTRSVD[0]	in	CELL[3].IMUX_IMUX_DELAY[42]
GTRSVD[1]	in	CELL[4].IMUX_IMUX_DELAY[42]
GTRSVD[2]	in	CELL[5].IMUX_IMUX_DELAY[42]
GTRSVD[3]	in	CELL[6].IMUX_IMUX_DELAY[42]
GTRSVD[4]	in	CELL[7].IMUX_IMUX_DELAY[42]
GTRSVD[5]	in	CELL[8].IMUX_IMUX_DELAY[42]
GTRSVD[6]	in	CELL[9].IMUX_IMUX_DELAY[42]
GTRSVD[7]	in	CELL[10].IMUX_IMUX_DELAY[42]
GTRSVD[8]	in	CELL[3].IMUX_IMUX_DELAY[26]
GTRSVD[9]	in	CELL[4].IMUX_IMUX_DELAY[26]
GTRSVD[10]	in	CELL[5].IMUX_IMUX_DELAY[26]
GTRSVD[11]	in	CELL[6].IMUX_IMUX_DELAY[26]
GTRSVD[12]	in	CELL[7].IMUX_IMUX_DELAY[26]
GTRSVD[13]	in	CELL[8].IMUX_IMUX_DELAY[26]
GTRSVD[14]	in	CELL[9].IMUX_IMUX_DELAY[26]
GTRSVD[15]	in	CELL[10].IMUX_IMUX_DELAY[26]
GTRXRESET	in	CELL[8].IMUX_CTRL[0]
GTTXRESET	in	CELL[5].IMUX_CTRL[0]
LOOPBACK[0]	in	CELL[9].IMUX_IMUX_DELAY[43]
LOOPBACK[1]	in	CELL[9].IMUX_IMUX_DELAY[46]
LOOPBACK[2]	in	CELL[9].IMUX_IMUX_DELAY[47]
PCSRSVDIN[0]	in	CELL[3].IMUX_IMUX_DELAY[25]
PCSRSVDIN[1]	in	CELL[4].IMUX_IMUX_DELAY[25]
PCSRSVDIN[2]	in	CELL[5].IMUX_IMUX_DELAY[25]
PCSRSVDIN[3]	in	CELL[6].IMUX_IMUX_DELAY[25]
PCSRSVDIN[4]	in	CELL[7].IMUX_IMUX_DELAY[25]
PCSRSVDIN[5]	in	CELL[8].IMUX_IMUX_DELAY[25]
PCSRSVDIN[6]	in	CELL[9].IMUX_IMUX_DELAY[25]
PCSRSVDIN[7]	in	CELL[10].IMUX_IMUX_DELAY[25]
PCSRSVDIN[8]	in	CELL[3].IMUX_IMUX_DELAY[9]
PCSRSVDIN[9]	in	CELL[4].IMUX_IMUX_DELAY[9]
PCSRSVDIN[10]	in	CELL[5].IMUX_IMUX_DELAY[9]
PCSRSVDIN[11]	in	CELL[6].IMUX_IMUX_DELAY[9]
PCSRSVDIN[12]	in	CELL[7].IMUX_IMUX_DELAY[9]
PCSRSVDIN[13]	in	CELL[8].IMUX_IMUX_DELAY[9]
PCSRSVDIN[14]	in	CELL[9].IMUX_IMUX_DELAY[9]
PCSRSVDIN[15]	in	CELL[10].IMUX_IMUX_DELAY[9]
PCSRSVDIN2[0]	in	CELL[10].IMUX_IMUX_DELAY[34]
PCSRSVDIN2[1]	in	CELL[10].IMUX_IMUX_DELAY[35]
PCSRSVDIN2[2]	in	CELL[10].IMUX_IMUX_DELAY[38]
PCSRSVDIN2[3]	in	CELL[10].IMUX_IMUX_DELAY[39]
PCSRSVDIN2[4]	in	CELL[9].IMUX_IMUX_DELAY[39]
PMARSVDIN[0]	in	CELL[9].IMUX_IMUX_DELAY[5]
PMARSVDIN[1]	in	CELL[9].IMUX_IMUX_DELAY[4]
PMARSVDIN[2]	in	CELL[9].IMUX_IMUX_DELAY[1]
PMARSVDIN[3]	in	CELL[9].IMUX_IMUX_DELAY[0]
PMARSVDIN[4]	in	CELL[8].IMUX_IMUX_DELAY[0]
PMASCANCLK[0]	in	CELL[0].IMUX_CLK[0] invert by MAIN[0][30][2]
PMASCANCLK[1]	in	CELL[1].IMUX_CLK[0] invert by MAIN[0][31][2]
PMASCANCLK[2]	in	CELL[8].IMUX_CLK[0] invert by MAIN[0][30][3]
PMASCANCLK[3]	in	CELL[9].IMUX_CLK[0] invert by MAIN[0][31][3]
PMASCANCLK[4]	in	CELL[10].IMUX_CLK[0] invert by MAIN[0][30][4]
PMASCANRSTEN	in	CELL[0].IMUX_IMUX_DELAY[28]
PMASCANENB	in	CELL[9].IMUX_IMUX_DELAY[36]
PMASCANMODEB	in	CELL[0].IMUX_IMUX_DELAY[12]
PMASCANIN[0]	in	CELL[0].IMUX_IMUX_DELAY[14]
PMASCANIN[1]	in	CELL[1].IMUX_IMUX_DELAY[14]
PMASCANIN[2]	in	CELL[8].IMUX_IMUX_DELAY[20]
PMASCANIN[3]	in	CELL[9].IMUX_IMUX_DELAY[20]
PMASCANIN[4]	in	CELL[10].IMUX_IMUX_DELAY[20]
PMASCANIN[5]	in	CELL[0].IMUX_IMUX_DELAY[24]
PMASCANIN[6]	in	CELL[0].IMUX_IMUX_DELAY[9]
PMASCANIN[7]	in	CELL[7].IMUX_IMUX_DELAY[5]
RESETOVRD	in	CELL[5].IMUX_IMUX_DELAY[41]
RX8B10BEN	in	CELL[9].IMUX_IMUX_DELAY[12]
RXADAPTSELTEST[0]	in	CELL[7].IMUX_IMUX_DELAY[39]
RXADAPTSELTEST[1]	in	CELL[7].IMUX_IMUX_DELAY[6]
RXADAPTSELTEST[2]	in	CELL[7].IMUX_IMUX_DELAY[35]
RXADAPTSELTEST[3]	in	CELL[7].IMUX_IMUX_DELAY[34]
RXADAPTSELTEST[4]	in	CELL[7].IMUX_IMUX_DELAY[37]
RXADAPTSELTEST[5]	in	CELL[7].IMUX_IMUX_DELAY[36]
RXADAPTSELTEST[6]	in	CELL[7].IMUX_IMUX_DELAY[32]
RXADAPTSELTEST[7]	in	CELL[6].IMUX_IMUX_DELAY[34]
RXADAPTSELTEST[8]	in	CELL[6].IMUX_IMUX_DELAY[37]
RXADAPTSELTEST[9]	in	CELL[6].IMUX_IMUX_DELAY[36]
RXADAPTSELTEST[10]	in	CELL[6].IMUX_IMUX_DELAY[32]
RXADAPTSELTEST[11]	in	CELL[5].IMUX_IMUX_DELAY[37]
RXADAPTSELTEST[12]	in	CELL[6].IMUX_IMUX_DELAY[13]
RXADAPTSELTEST[13]	in	CELL[6].IMUX_IMUX_DELAY[44]
RXBUFRESET	in	CELL[6].IMUX_CTRL[1]
RXCDRFREQRESET	in	CELL[7].IMUX_CTRL[0]
RXCDRHOLD	in	CELL[8].IMUX_IMUX_DELAY[30]
RXCDROVRDEN	in	CELL[8].IMUX_IMUX_DELAY[14]
RXCDRRESET	in	CELL[9].IMUX_CTRL[1]
RXCDRRESETRSV	in	CELL[8].IMUX_CTRL[1]
RXCHBONDEN	in	CELL[9].IMUX_IMUX_DELAY[17]
RXCHBONDI[0]	in	CELL[9].IMUX_IMUX_DELAY[18]
RXCHBONDI[1]	in	CELL[9].IMUX_IMUX_DELAY[19]
RXCHBONDI[2]	in	CELL[9].IMUX_IMUX_DELAY[22]
RXCHBONDI[3]	in	CELL[9].IMUX_IMUX_DELAY[23]
RXCHBONDI[4]	in	CELL[10].IMUX_IMUX_DELAY[23]
RXCHBONDLEVEL[0]	in	CELL[10].IMUX_IMUX_DELAY[18]
RXCHBONDLEVEL[1]	in	CELL[10].IMUX_IMUX_DELAY[19]
RXCHBONDLEVEL[2]	in	CELL[10].IMUX_IMUX_DELAY[22]
RXCHBONDMASTER	in	CELL[9].IMUX_IMUX_DELAY[30]
RXCHBONDSLAVE	in	CELL[10].IMUX_IMUX_DELAY[30]
RXCOMMADETEN	in	CELL[9].IMUX_IMUX_DELAY[44]
RXDDIEN	in	CELL[8].IMUX_IMUX_DELAY[8]
RXDEBUGPULSE	in	CELL[7].IMUX_IMUX_DELAY[28]
RXDFEAGCHOLD	in	CELL[10].IMUX_IMUX_DELAY[29]
RXDFEAGCOVRDEN	in	CELL[10].IMUX_IMUX_DELAY[21]
RXDFEAGCTRL[0]	in	CELL[10].IMUX_IMUX_DELAY[31]
RXDFEAGCTRL[1]	in	CELL[10].IMUX_IMUX_DELAY[46]
RXDFEAGCTRL[2]	in	CELL[10].IMUX_IMUX_DELAY[10]
RXDFEAGCTRL[3]	in	CELL[10].IMUX_IMUX_DELAY[41]
RXDFEAGCTRL[4]	in	CELL[10].IMUX_IMUX_DELAY[8]
RXDFECM1EN	in	CELL[10].IMUX_IMUX_DELAY[16]
RXDFELFHOLD	in	CELL[9].IMUX_IMUX_DELAY[35]
RXDFELFOVRDEN	in	CELL[9].IMUX_IMUX_DELAY[27]
RXDFELPMRESET	in	CELL[9].IMUX_CTRL[0]
RXDFEUTHOLD	in	CELL[9].IMUX_IMUX_DELAY[3]
RXDFEUTOVRDEN	in	CELL[8].IMUX_IMUX_DELAY[35]
RXDFEVPHOLD	in	CELL[8].IMUX_IMUX_DELAY[19]
RXDFEVPOVRDEN	in	CELL[8].IMUX_IMUX_DELAY[27]
RXDFEVSEN	in	CELL[8].IMUX_IMUX_DELAY[11]
RXDFEXYDEN	in	CELL[9].IMUX_IMUX_DELAY[45]
RXDFESLIDETAP[0]	in	CELL[9].IMUX_IMUX_DELAY[8]
RXDFESLIDETAP[1]	in	CELL[9].IMUX_IMUX_DELAY[41]
RXDFESLIDETAP[2]	in	CELL[9].IMUX_IMUX_DELAY[15]
RXDFESLIDETAP[3]	in	CELL[10].IMUX_IMUX_DELAY[6]
RXDFESLIDETAP[4]	in	CELL[9].IMUX_IMUX_DELAY[6]
RXDFESLIDETAPADAPTEN	in	CELL[7].IMUX_IMUX_DELAY[11]
RXDFESLIDETAPHOLD	in	CELL[8].IMUX_IMUX_DELAY[15]
RXDFESLIDETAPID[0]	in	CELL[3].IMUX_IMUX_DELAY[41]
RXDFESLIDETAPID[1]	in	CELL[3].IMUX_IMUX_DELAY[10]
RXDFESLIDETAPID[2]	in	CELL[3].IMUX_IMUX_DELAY[27]
RXDFESLIDETAPID[3]	in	CELL[3].IMUX_IMUX_DELAY[46]
RXDFESLIDETAPID[4]	in	CELL[4].IMUX_IMUX_DELAY[46]
RXDFESLIDETAPID[5]	in	CELL[4].IMUX_IMUX_DELAY[14]
RXDFESLIDETAPINITOVRDEN	in	CELL[8].IMUX_IMUX_DELAY[43]
RXDFESLIDETAPONLYADAPTEN	in	CELL[7].IMUX_IMUX_DELAY[41]
RXDFESLIDETAPOVRDEN	in	CELL[9].IMUX_IMUX_DELAY[32]
RXDFESLIDETAPSTROBE	in	CELL[9].IMUX_IMUX_DELAY[16]
RXDFETAP2HOLD	in	CELL[10].IMUX_IMUX_DELAY[44]
RXDFETAP2OVRDEN	in	CELL[10].IMUX_IMUX_DELAY[28]
RXDFETAP3HOLD	in	CELL[10].IMUX_IMUX_DELAY[36]
RXDFETAP3OVRDEN	in	CELL[10].IMUX_IMUX_DELAY[12]
RXDFETAP4HOLD	in	CELL[9].IMUX_IMUX_DELAY[37]
RXDFETAP4OVRDEN	in	CELL[9].IMUX_IMUX_DELAY[21]
RXDFETAP5HOLD	in	CELL[9].IMUX_IMUX_DELAY[29]
RXDFETAP5OVRDEN	in	CELL[9].IMUX_IMUX_DELAY[13]
RXDFETAP6HOLD	in	CELL[1].IMUX_IMUX_DELAY[26]
RXDFETAP6OVRDEN	in	CELL[1].IMUX_IMUX_DELAY[42]
RXDFETAP7HOLD	in	CELL[1].IMUX_IMUX_DELAY[1]
RXDFETAP7OVRDEN	in	CELL[1].IMUX_IMUX_DELAY[0]
RXDLYBYPASS	in	CELL[8].IMUX_IMUX_DELAY[32]
RXDLYEN	in	CELL[6].IMUX_IMUX_DELAY[28]
RXDLYOVRDEN	in	CELL[7].IMUX_IMUX_DELAY[38]
RXDLYSRESET	in	CELL[6].IMUX_CTRL[0]
RXDLYTESTENB	in	CELL[8].IMUX_IMUX_DELAY[10]
RXELECIDLEMODE[0]	in	CELL[10].IMUX_IMUX_DELAY[0]
RXELECIDLEMODE[1]	in	CELL[10].IMUX_IMUX_DELAY[1]
RXGEARBOXSLIP	in	CELL[8].IMUX_IMUX_DELAY[2]
RXLPMEN	in	CELL[8].IMUX_IMUX_DELAY[34]
RXLPMHFHOLD	in	CELL[10].IMUX_IMUX_DELAY[43]
RXLPMHFOVRDEN	in	CELL[10].IMUX_IMUX_DELAY[27]
RXLPMLFHOLD	in	CELL[10].IMUX_IMUX_DELAY[11]
RXLPMLFKLOVRDEN	in	CELL[10].IMUX_IMUX_DELAY[3]
RXMCOMMAALIGNEN	in	CELL[9].IMUX_IMUX_DELAY[2]
RXMONITORSEL[0]	in	CELL[10].IMUX_IMUX_DELAY[45]
RXMONITORSEL[1]	in	CELL[2].IMUX_IMUX_DELAY[1]
RXOOBRESET	in	CELL[10].IMUX_CTRL[1]
RXOSHOLD	in	CELL[8].IMUX_IMUX_DELAY[29]
RXOSOVRDEN	in	CELL[8].IMUX_IMUX_DELAY[13]
RXOSCALRESET	in	CELL[2].IMUX_IMUX_DELAY[46]
RXOSINTCFG[0]	in	CELL[0].IMUX_IMUX_DELAY[4]
RXOSINTCFG[1]	in	CELL[0].IMUX_IMUX_DELAY[5]
RXOSINTCFG[2]	in	CELL[0].IMUX_IMUX_DELAY[2]
RXOSINTCFG[3]	in	CELL[0].IMUX_IMUX_DELAY[3]
RXOSINTEN	in	CELL[8].IMUX_IMUX_DELAY[41]
RXOSINTHOLD	in	CELL[4].IMUX_IMUX_DELAY[0]
RXOSINTID0[0]	in	CELL[2].IMUX_IMUX_DELAY[2]
RXOSINTID0[1]	in	CELL[2].IMUX_IMUX_DELAY[3]
RXOSINTID0[2]	in	CELL[2].IMUX_IMUX_DELAY[6]
RXOSINTID0[3]	in	CELL[2].IMUX_IMUX_DELAY[7]
RXOSINTNTRLEN	in	CELL[8].IMUX_IMUX_DELAY[16]
RXOSINTOVRDEN	in	CELL[4].IMUX_IMUX_DELAY[41]
RXOSINTSTROBE	in	CELL[4].IMUX_IMUX_DELAY[33]
RXOSINTTESTOVRDEN	in	CELL[4].IMUX_IMUX_DELAY[32]
RXOUTCLKSEL[0]	in	CELL[10].IMUX_IMUX_DELAY[4]
RXOUTCLKSEL[1]	in	CELL[10].IMUX_IMUX_DELAY[5]
RXOUTCLKSEL[2]	in	CELL[10].IMUX_IMUX_DELAY[2]
RXPCOMMAALIGNEN	in	CELL[9].IMUX_IMUX_DELAY[34]
RXPCSRESET	in	CELL[7].IMUX_IMUX_DELAY[14]
RXPD[0]	in	CELL[7].IMUX_IMUX_DELAY[3]
RXPD[1]	in	CELL[8].IMUX_IMUX_DELAY[28]
RXPHALIGN	in	CELL[9].IMUX_IMUX_DELAY[14]
RXPHALIGNEN	in	CELL[6].IMUX_IMUX_DELAY[41]
RXPHDLYPD	in	CELL[1].IMUX_IMUX_DELAY[9]
RXPHDLYRESET	in	CELL[1].IMUX_CTRL[1]
RXPHOVRDEN	in	CELL[10].IMUX_IMUX_DELAY[14]
RXPMARESET	in	CELL[7].IMUX_CTRL[1]
RXPOLARITY	in	CELL[7].IMUX_IMUX_DELAY[27]
RXPRBSCNTRESET	in	CELL[10].IMUX_IMUX_DELAY[13]
RXPRBSSEL[0]	in	CELL[8].IMUX_IMUX_DELAY[22]
RXPRBSSEL[1]	in	CELL[8].IMUX_IMUX_DELAY[38]
RXPRBSSEL[2]	in	CELL[8].IMUX_IMUX_DELAY[23]
RXQPIEN	in	CELL[9].IMUX_IMUX_DELAY[10]
RXRATE[0]	in	CELL[6].IMUX_IMUX_DELAY[15]
RXRATE[1]	in	CELL[6].IMUX_IMUX_DELAY[14]
RXRATE[2]	in	CELL[6].IMUX_IMUX_DELAY[11]
RXRATEMODE	in	CELL[7].IMUX_IMUX_DELAY[2]
RXSLIDE	in	CELL[8].IMUX_IMUX_DELAY[12]
RXSYNCALLIN	in	CELL[0].IMUX_IMUX_DELAY[13]
RXSYNCIN	in	CELL[0].IMUX_IMUX_DELAY[42]
RXSYNCMODE	in	CELL[2].IMUX_IMUX_DELAY[4]
RXSYSCLKSEL[0]	in	CELL[2].IMUX_IMUX_DELAY[45]
RXSYSCLKSEL[1]	in	CELL[2].IMUX_IMUX_DELAY[42]
RXUSERRDY	in	CELL[8].IMUX_IMUX_DELAY[44]
RXUSRCLK	in	CELL[6].IMUX_CLK[0] invert by MAIN[0][31][4]
RXUSRCLK2	in	CELL[7].IMUX_CLK[0] invert by MAIN[0][30][5]
SETERRSTATUS	in	CELL[4].IMUX_IMUX_DELAY[34]
SIGVALIDCLK	in	CELL[4].IMUX_CLK[1] invert by MAIN[0][31][13]
TSTCLK[0]	in	CELL[3].IMUX_CLK[0] invert by MAIN[0][31][6]
TSTCLK[1]	in	CELL[10].IMUX_CLK[1] invert by MAIN[0][30][7]
TSTIN[0]	in	CELL[1].IMUX_IMUX_DELAY[40]
TSTIN[1]	in	CELL[2].IMUX_IMUX_DELAY[40]
TSTIN[2]	in	CELL[3].IMUX_IMUX_DELAY[40]
TSTIN[3]	in	CELL[4].IMUX_IMUX_DELAY[40]
TSTIN[4]	in	CELL[5].IMUX_IMUX_DELAY[40]
TSTIN[5]	in	CELL[6].IMUX_IMUX_DELAY[40]
TSTIN[6]	in	CELL[7].IMUX_IMUX_DELAY[40]
TSTIN[7]	in	CELL[8].IMUX_IMUX_DELAY[40]
TSTIN[8]	in	CELL[9].IMUX_IMUX_DELAY[40]
TSTIN[9]	in	CELL[10].IMUX_IMUX_DELAY[40]
TSTIN[10]	in	CELL[1].IMUX_IMUX_DELAY[24]
TSTIN[11]	in	CELL[2].IMUX_IMUX_DELAY[24]
TSTIN[12]	in	CELL[3].IMUX_IMUX_DELAY[24]
TSTIN[13]	in	CELL[4].IMUX_IMUX_DELAY[24]
TSTIN[14]	in	CELL[5].IMUX_IMUX_DELAY[24]
TSTIN[15]	in	CELL[6].IMUX_IMUX_DELAY[24]
TSTIN[16]	in	CELL[7].IMUX_IMUX_DELAY[24]
TSTIN[17]	in	CELL[8].IMUX_IMUX_DELAY[24]
TSTIN[18]	in	CELL[9].IMUX_IMUX_DELAY[24]
TSTIN[19]	in	CELL[10].IMUX_IMUX_DELAY[24]
TSTPD[0]	in	CELL[0].IMUX_IMUX_DELAY[43]
TSTPD[1]	in	CELL[1].IMUX_IMUX_DELAY[43]
TSTPD[2]	in	CELL[2].IMUX_IMUX_DELAY[43]
TSTPD[3]	in	CELL[3].IMUX_IMUX_DELAY[43]
TSTPD[4]	in	CELL[4].IMUX_IMUX_DELAY[43]
TSTPDOVRDB	in	CELL[0].IMUX_IMUX_DELAY[27]
TX8B10BBYPASS[0]	in	CELL[7].IMUX_IMUX_DELAY[15]
TX8B10BBYPASS[1]	in	CELL[5].IMUX_IMUX_DELAY[15]
TX8B10BBYPASS[2]	in	CELL[3].IMUX_IMUX_DELAY[15]
TX8B10BBYPASS[3]	in	CELL[1].IMUX_IMUX_DELAY[15]
TX8B10BBYPASS[4]	in	CELL[7].IMUX_IMUX_DELAY[8]
TX8B10BBYPASS[5]	in	CELL[5].IMUX_IMUX_DELAY[8]
TX8B10BBYPASS[6]	in	CELL[3].IMUX_IMUX_DELAY[8]
TX8B10BBYPASS[7]	in	CELL[1].IMUX_IMUX_DELAY[8]
TX8B10BEN	in	CELL[2].IMUX_IMUX_DELAY[0]
TXBUFDIFFCTRL[0]	in	CELL[7].IMUX_IMUX_DELAY[12]
TXBUFDIFFCTRL[1]	in	CELL[7].IMUX_IMUX_DELAY[13]
TXBUFDIFFCTRL[2]	in	CELL[7].IMUX_IMUX_DELAY[10]
TXCHARDISPMODE[0]	in	CELL[6].IMUX_IMUX_DELAY[29]
TXCHARDISPMODE[1]	in	CELL[4].IMUX_IMUX_DELAY[29]
TXCHARDISPMODE[2]	in	CELL[2].IMUX_IMUX_DELAY[29]
TXCHARDISPMODE[3]	in	CELL[0].IMUX_IMUX_DELAY[29]
TXCHARDISPMODE[4]	in	CELL[6].IMUX_IMUX_DELAY[31]
TXCHARDISPMODE[5]	in	CELL[4].IMUX_IMUX_DELAY[31]
TXCHARDISPMODE[6]	in	CELL[2].IMUX_IMUX_DELAY[31]
TXCHARDISPMODE[7]	in	CELL[0].IMUX_IMUX_DELAY[31]
TXCHARDISPVAL[0]	in	CELL[6].IMUX_IMUX_DELAY[8]
TXCHARDISPVAL[1]	in	CELL[4].IMUX_IMUX_DELAY[8]
TXCHARDISPVAL[2]	in	CELL[2].IMUX_IMUX_DELAY[8]
TXCHARDISPVAL[3]	in	CELL[0].IMUX_IMUX_DELAY[8]
TXCHARDISPVAL[4]	in	CELL[6].IMUX_IMUX_DELAY[10]
TXCHARDISPVAL[5]	in	CELL[4].IMUX_IMUX_DELAY[10]
TXCHARDISPVAL[6]	in	CELL[2].IMUX_IMUX_DELAY[10]
TXCHARDISPVAL[7]	in	CELL[0].IMUX_IMUX_DELAY[10]
TXCHARISK[0]	in	CELL[7].IMUX_IMUX_DELAY[31]
TXCHARISK[1]	in	CELL[5].IMUX_IMUX_DELAY[31]
TXCHARISK[2]	in	CELL[3].IMUX_IMUX_DELAY[31]
TXCHARISK[3]	in	CELL[1].IMUX_IMUX_DELAY[31]
TXCHARISK[4]	in	CELL[7].IMUX_IMUX_DELAY[29]
TXCHARISK[5]	in	CELL[5].IMUX_IMUX_DELAY[29]
TXCHARISK[6]	in	CELL[3].IMUX_IMUX_DELAY[29]
TXCHARISK[7]	in	CELL[1].IMUX_IMUX_DELAY[29]
TXCOMINIT	in	CELL[1].IMUX_IMUX_DELAY[44]
TXCOMSAS	in	CELL[1].IMUX_IMUX_DELAY[28]
TXCOMWAKE	in	CELL[1].IMUX_IMUX_DELAY[12]
TXDATA[0]	in	CELL[7].IMUX_IMUX_DELAY[18]
TXDATA[1]	in	CELL[7].IMUX_IMUX_DELAY[19]
TXDATA[2]	in	CELL[7].IMUX_IMUX_DELAY[22]
TXDATA[3]	in	CELL[7].IMUX_IMUX_DELAY[23]
TXDATA[4]	in	CELL[6].IMUX_IMUX_DELAY[16]
TXDATA[5]	in	CELL[6].IMUX_IMUX_DELAY[17]
TXDATA[6]	in	CELL[6].IMUX_IMUX_DELAY[20]
TXDATA[7]	in	CELL[6].IMUX_IMUX_DELAY[21]
TXDATA[8]	in	CELL[5].IMUX_IMUX_DELAY[18]
TXDATA[9]	in	CELL[5].IMUX_IMUX_DELAY[19]
TXDATA[10]	in	CELL[5].IMUX_IMUX_DELAY[22]
TXDATA[11]	in	CELL[5].IMUX_IMUX_DELAY[23]
TXDATA[12]	in	CELL[4].IMUX_IMUX_DELAY[16]
TXDATA[13]	in	CELL[4].IMUX_IMUX_DELAY[17]
TXDATA[14]	in	CELL[4].IMUX_IMUX_DELAY[20]
TXDATA[15]	in	CELL[4].IMUX_IMUX_DELAY[21]
TXDATA[16]	in	CELL[3].IMUX_IMUX_DELAY[18]
TXDATA[17]	in	CELL[3].IMUX_IMUX_DELAY[19]
TXDATA[18]	in	CELL[3].IMUX_IMUX_DELAY[22]
TXDATA[19]	in	CELL[3].IMUX_IMUX_DELAY[23]
TXDATA[20]	in	CELL[2].IMUX_IMUX_DELAY[16]
TXDATA[21]	in	CELL[2].IMUX_IMUX_DELAY[17]
TXDATA[22]	in	CELL[2].IMUX_IMUX_DELAY[20]
TXDATA[23]	in	CELL[2].IMUX_IMUX_DELAY[21]
TXDATA[24]	in	CELL[1].IMUX_IMUX_DELAY[18]
TXDATA[25]	in	CELL[1].IMUX_IMUX_DELAY[19]
TXDATA[26]	in	CELL[1].IMUX_IMUX_DELAY[22]
TXDATA[27]	in	CELL[1].IMUX_IMUX_DELAY[23]
TXDATA[28]	in	CELL[0].IMUX_IMUX_DELAY[16]
TXDATA[29]	in	CELL[0].IMUX_IMUX_DELAY[17]
TXDATA[30]	in	CELL[0].IMUX_IMUX_DELAY[20]
TXDATA[31]	in	CELL[0].IMUX_IMUX_DELAY[21]
TXDATA[32]	in	CELL[7].IMUX_IMUX_DELAY[21]
TXDATA[33]	in	CELL[7].IMUX_IMUX_DELAY[20]
TXDATA[34]	in	CELL[7].IMUX_IMUX_DELAY[17]
TXDATA[35]	in	CELL[7].IMUX_IMUX_DELAY[16]
TXDATA[36]	in	CELL[6].IMUX_IMUX_DELAY[18]
TXDATA[37]	in	CELL[6].IMUX_IMUX_DELAY[19]
TXDATA[38]	in	CELL[6].IMUX_IMUX_DELAY[22]
TXDATA[39]	in	CELL[6].IMUX_IMUX_DELAY[23]
TXDATA[40]	in	CELL[5].IMUX_IMUX_DELAY[16]
TXDATA[41]	in	CELL[5].IMUX_IMUX_DELAY[17]
TXDATA[42]	in	CELL[5].IMUX_IMUX_DELAY[20]
TXDATA[43]	in	CELL[5].IMUX_IMUX_DELAY[21]
TXDATA[44]	in	CELL[4].IMUX_IMUX_DELAY[18]
TXDATA[45]	in	CELL[4].IMUX_IMUX_DELAY[19]
TXDATA[46]	in	CELL[4].IMUX_IMUX_DELAY[22]
TXDATA[47]	in	CELL[4].IMUX_IMUX_DELAY[23]
TXDATA[48]	in	CELL[3].IMUX_IMUX_DELAY[16]
TXDATA[49]	in	CELL[3].IMUX_IMUX_DELAY[17]
TXDATA[50]	in	CELL[3].IMUX_IMUX_DELAY[20]
TXDATA[51]	in	CELL[3].IMUX_IMUX_DELAY[21]
TXDATA[52]	in	CELL[2].IMUX_IMUX_DELAY[18]
TXDATA[53]	in	CELL[2].IMUX_IMUX_DELAY[19]
TXDATA[54]	in	CELL[2].IMUX_IMUX_DELAY[22]
TXDATA[55]	in	CELL[2].IMUX_IMUX_DELAY[23]
TXDATA[56]	in	CELL[1].IMUX_IMUX_DELAY[16]
TXDATA[57]	in	CELL[1].IMUX_IMUX_DELAY[17]
TXDATA[58]	in	CELL[1].IMUX_IMUX_DELAY[20]
TXDATA[59]	in	CELL[1].IMUX_IMUX_DELAY[21]
TXDATA[60]	in	CELL[0].IMUX_IMUX_DELAY[18]
TXDATA[61]	in	CELL[0].IMUX_IMUX_DELAY[19]
TXDATA[62]	in	CELL[0].IMUX_IMUX_DELAY[22]
TXDATA[63]	in	CELL[0].IMUX_IMUX_DELAY[23]
TXDEEMPH	in	CELL[5].IMUX_IMUX_DELAY[35]
TXDETECTRX	in	CELL[5].IMUX_IMUX_DELAY[39]
TXDIFFCTRL[0]	in	CELL[5].IMUX_IMUX_DELAY[7]
TXDIFFCTRL[1]	in	CELL[5].IMUX_IMUX_DELAY[6]
TXDIFFCTRL[2]	in	CELL[5].IMUX_IMUX_DELAY[3]
TXDIFFCTRL[3]	in	CELL[5].IMUX_IMUX_DELAY[2]
TXDIFFPD	in	CELL[4].IMUX_IMUX_DELAY[37]
TXDLYBYPASS	in	CELL[5].IMUX_IMUX_DELAY[44]
TXDLYEN	in	CELL[5].IMUX_IMUX_DELAY[14]
TXDLYHOLD	in	CELL[5].IMUX_IMUX_DELAY[11]
TXDLYOVRDEN	in	CELL[5].IMUX_IMUX_DELAY[12]
TXDLYSRESET	in	CELL[3].IMUX_IMUX_DELAY[45]
TXDLYTESTENB	in	CELL[5].IMUX_IMUX_DELAY[30]
TXDLYUPDOWN	in	CELL[5].IMUX_IMUX_DELAY[43]
TXELECIDLE	in	CELL[6].IMUX_IMUX_DELAY[39]
TXHEADER[0]	in	CELL[2].IMUX_IMUX_DELAY[13]
TXHEADER[1]	in	CELL[2].IMUX_IMUX_DELAY[12]
TXHEADER[2]	in	CELL[2].IMUX_IMUX_DELAY[9]
TXINHIBIT	in	CELL[2].IMUX_IMUX_DELAY[32]
TXMAINCURSOR[0]	in	CELL[3].IMUX_IMUX_DELAY[5]
TXMAINCURSOR[1]	in	CELL[3].IMUX_IMUX_DELAY[4]
TXMAINCURSOR[2]	in	CELL[3].IMUX_IMUX_DELAY[1]
TXMAINCURSOR[3]	in	CELL[3].IMUX_IMUX_DELAY[0]
TXMAINCURSOR[4]	in	CELL[4].IMUX_IMUX_DELAY[5]
TXMAINCURSOR[5]	in	CELL[7].IMUX_IMUX_DELAY[0]
TXMAINCURSOR[6]	in	CELL[7].IMUX_IMUX_DELAY[1]
TXMARGIN[0]	in	CELL[4].IMUX_IMUX_DELAY[39]
TXMARGIN[1]	in	CELL[4].IMUX_IMUX_DELAY[38]
TXMARGIN[2]	in	CELL[4].IMUX_IMUX_DELAY[35]
TXOUTCLKSEL[0]	in	CELL[8].IMUX_IMUX_DELAY[5]
TXOUTCLKSEL[1]	in	CELL[8].IMUX_IMUX_DELAY[4]
TXOUTCLKSEL[2]	in	CELL[8].IMUX_IMUX_DELAY[1]
TXPCSRESET	in	CELL[7].IMUX_IMUX_DELAY[30]
TXPD[0]	in	CELL[6].IMUX_IMUX_DELAY[38]
TXPD[1]	in	CELL[6].IMUX_IMUX_DELAY[35]
TXPDELECIDLEMODE	in	CELL[1].IMUX_IMUX_DELAY[10]
TXPHALIGN	in	CELL[2].IMUX_IMUX_DELAY[25]
TXPHALIGNEN	in	CELL[2].IMUX_IMUX_DELAY[33]
TXPHDLYPD	in	CELL[3].IMUX_IMUX_DELAY[37]
TXPHDLYRESET	in	CELL[5].IMUX_IMUX_DELAY[36]
TXPHDLYTSTCLK	in	CELL[2].IMUX_CLK[1] invert by MAIN[0][30][6]
TXPHINIT	in	CELL[5].IMUX_IMUX_DELAY[27]
TXPHOVRDEN	in	CELL[4].IMUX_IMUX_DELAY[12]
TXPIPPMEN	in	CELL[0].IMUX_IMUX_DELAY[15]
TXPIPPMOVRDEN	in	CELL[2].IMUX_IMUX_DELAY[30]
TXPIPPMPD	in	CELL[1].IMUX_IMUX_DELAY[27]
TXPIPPMSEL	in	CELL[2].IMUX_IMUX_DELAY[27]
TXPIPPMSTEPSIZE[0]	in	CELL[4].IMUX_IMUX_DELAY[27]
TXPIPPMSTEPSIZE[1]	in	CELL[8].IMUX_IMUX_DELAY[18]
TXPIPPMSTEPSIZE[2]	in	CELL[8].IMUX_IMUX_DELAY[37]
TXPIPPMSTEPSIZE[3]	in	CELL[10].IMUX_IMUX_DELAY[15]
TXPIPPMSTEPSIZE[4]	in	CELL[3].IMUX_IMUX_DELAY[12]
TXPISOPD	in	CELL[0].IMUX_IMUX_DELAY[7]
TXPMARESET	in	CELL[3].IMUX_CTRL[1]
TXPOLARITY	in	CELL[3].IMUX_IMUX_DELAY[30]
TXPOSTCURSOR[0]	in	CELL[4].IMUX_IMUX_DELAY[7]
TXPOSTCURSOR[1]	in	CELL[4].IMUX_IMUX_DELAY[6]
TXPOSTCURSOR[2]	in	CELL[4].IMUX_IMUX_DELAY[3]
TXPOSTCURSOR[3]	in	CELL[4].IMUX_IMUX_DELAY[2]
TXPOSTCURSOR[4]	in	CELL[7].IMUX_IMUX_DELAY[4]
TXPOSTCURSORINV	in	CELL[1].IMUX_IMUX_DELAY[41]
TXPRBSFORCEERR	in	CELL[4].IMUX_IMUX_DELAY[15]
TXPRBSSEL[0]	in	CELL[8].IMUX_IMUX_DELAY[3]
TXPRBSSEL[1]	in	CELL[8].IMUX_IMUX_DELAY[6]
TXPRBSSEL[2]	in	CELL[8].IMUX_IMUX_DELAY[7]
TXPRECURSOR[0]	in	CELL[6].IMUX_IMUX_DELAY[7]
TXPRECURSOR[1]	in	CELL[6].IMUX_IMUX_DELAY[6]
TXPRECURSOR[2]	in	CELL[6].IMUX_IMUX_DELAY[3]
TXPRECURSOR[3]	in	CELL[6].IMUX_IMUX_DELAY[2]
TXPRECURSOR[4]	in	CELL[7].IMUX_IMUX_DELAY[7]
TXPRECURSORINV	in	CELL[1].IMUX_IMUX_DELAY[4]
TXQPIBIASEN	in	CELL[1].IMUX_IMUX_DELAY[5]
TXQPISTRONGPDOWN	in	CELL[1].IMUX_IMUX_DELAY[13]
TXQPIWEAKPUP	in	CELL[1].IMUX_IMUX_DELAY[45]
TXRATE[0]	in	CELL[6].IMUX_IMUX_DELAY[47]
TXRATE[1]	in	CELL[6].IMUX_IMUX_DELAY[46]
TXRATE[2]	in	CELL[6].IMUX_IMUX_DELAY[43]
TXRATEMODE	in	CELL[3].IMUX_IMUX_DELAY[11]
TXSEQUENCE[0]	in	CELL[5].IMUX_IMUX_DELAY[5]
TXSEQUENCE[1]	in	CELL[5].IMUX_IMUX_DELAY[4]
TXSEQUENCE[2]	in	CELL[5].IMUX_IMUX_DELAY[1]
TXSEQUENCE[3]	in	CELL[5].IMUX_IMUX_DELAY[0]
TXSEQUENCE[4]	in	CELL[6].IMUX_IMUX_DELAY[5]
TXSEQUENCE[5]	in	CELL[6].IMUX_IMUX_DELAY[4]
TXSEQUENCE[6]	in	CELL[6].IMUX_IMUX_DELAY[1]
TXSTARTSEQ	in	CELL[3].IMUX_IMUX_DELAY[3]
TXSWING	in	CELL[5].IMUX_IMUX_DELAY[38]
TXSYSCLKSEL[0]	in	CELL[5].IMUX_IMUX_DELAY[28]
TXSYSCLKSEL[1]	in	CELL[4].IMUX_IMUX_DELAY[28]
TXUSERRDY	in	CELL[5].IMUX_IMUX_DELAY[10]
TXUSRCLK	in	CELL[4].IMUX_CLK[0] invert by MAIN[0][31][7]
TXUSRCLK2	in	CELL[5].IMUX_CLK[0] invert by MAIN[0][30][8]
TXSYNCALLIN	in	CELL[0].IMUX_IMUX_DELAY[45]
TXSYNCIN	in	CELL[0].IMUX_IMUX_DELAY[11]
TXSYNCMODE	in	CELL[1].IMUX_IMUX_DELAY[11]
SCANCLK	in	CELL[9].IMUX_CLK[1] invert by MAIN[0][31][5]
SCANENB	in	CELL[0].IMUX_IMUX_DELAY[6]
SCANMODEB	in	CELL[0].IMUX_IMUX_DELAY[46]
SCANIN[0]	in	CELL[0].IMUX_IMUX_DELAY[30]
SCANIN[1]	in	CELL[1].IMUX_IMUX_DELAY[30]
SCANIN[2]	in	CELL[8].IMUX_IMUX_DELAY[33]
SCANIN[3]	in	CELL[9].IMUX_IMUX_DELAY[33]
SCANIN[4]	in	CELL[10].IMUX_IMUX_DELAY[33]
SCANIN[5]	in	CELL[5].IMUX_IMUX_DELAY[45]
CPLLFBCLKLOST	out	CELL[1].OUT_BEL[8]
CPLLLOCK	out	CELL[1].OUT_BEL[14]
CPLLREFCLKLOST	out	CELL[1].OUT_BEL[18]
DMONITOROUT[0]	out	CELL[10].OUT_BEL[9]
DMONITOROUT[1]	out	CELL[9].OUT_BEL[9]
DMONITOROUT[2]	out	CELL[8].OUT_BEL[9]
DMONITOROUT[3]	out	CELL[7].OUT_BEL[9]
DMONITOROUT[4]	out	CELL[6].OUT_BEL[9]
DMONITOROUT[5]	out	CELL[5].OUT_BEL[9]
DMONITOROUT[6]	out	CELL[4].OUT_BEL[9]
DMONITOROUT[7]	out	CELL[3].OUT_BEL[9]
DMONITOROUT[8]	out	CELL[7].OUT_BEL[21]
DMONITOROUT[9]	out	CELL[6].OUT_BEL[21]
DMONITOROUT[10]	out	CELL[5].OUT_BEL[21]
DMONITOROUT[11]	out	CELL[4].OUT_BEL[21]
DMONITOROUT[12]	out	CELL[2].OUT_BEL[15]
DMONITOROUT[13]	out	CELL[1].OUT_BEL[21]
DMONITOROUT[14]	out	CELL[0].OUT_BEL[21]
DRPRDY	out	CELL[0].OUT_BEL[20]
DRPDO[0]	out	CELL[0].OUT_BEL[0]
DRPDO[1]	out	CELL[0].OUT_BEL[4]
DRPDO[2]	out	CELL[0].OUT_BEL[2]
DRPDO[3]	out	CELL[0].OUT_BEL[6]
DRPDO[4]	out	CELL[0].OUT_BEL[5]
DRPDO[5]	out	CELL[0].OUT_BEL[1]
DRPDO[6]	out	CELL[0].OUT_BEL[7]
DRPDO[7]	out	CELL[0].OUT_BEL[3]
DRPDO[8]	out	CELL[1].OUT_BEL[0]
DRPDO[9]	out	CELL[1].OUT_BEL[4]
DRPDO[10]	out	CELL[1].OUT_BEL[2]
DRPDO[11]	out	CELL[1].OUT_BEL[6]
DRPDO[12]	out	CELL[1].OUT_BEL[5]
DRPDO[13]	out	CELL[1].OUT_BEL[1]
DRPDO[14]	out	CELL[1].OUT_BEL[7]
DRPDO[15]	out	CELL[1].OUT_BEL[3]
EYESCANDATAERROR	out	CELL[10].OUT_BEL[20]
GTREFCLKMONITOR	out	CELL[2].OUT_BEL[23]
PCSRSVDOUT[0]	out	CELL[0].OUT_BEL[13]
PCSRSVDOUT[1]	out	CELL[1].OUT_BEL[13]
PCSRSVDOUT[2]	out	CELL[2].OUT_BEL[13]
PCSRSVDOUT[3]	out	CELL[3].OUT_BEL[13]
PCSRSVDOUT[4]	out	CELL[4].OUT_BEL[13]
PCSRSVDOUT[5]	out	CELL[5].OUT_BEL[13]
PCSRSVDOUT[6]	out	CELL[6].OUT_BEL[13]
PCSRSVDOUT[7]	out	CELL[7].OUT_BEL[13]
PCSRSVDOUT[8]	out	CELL[8].OUT_BEL[13]
PCSRSVDOUT[9]	out	CELL[9].OUT_BEL[13]
PCSRSVDOUT[10]	out	CELL[10].OUT_BEL[13]
PCSRSVDOUT[11]	out	CELL[0].OUT_BEL[9]
PCSRSVDOUT[12]	out	CELL[1].OUT_BEL[9]
PCSRSVDOUT[13]	out	CELL[2].OUT_BEL[9]
PCSRSVDOUT[14]	out	CELL[0].OUT_BEL[16]
PCSRSVDOUT[15]	out	CELL[1].OUT_BEL[16]
PHYSTATUS	out	CELL[9].OUT_BEL[10]
PMASCANOUT[0]	out	CELL[2].OUT_BEL[22]
PMASCANOUT[1]	out	CELL[2].OUT_BEL[18]
PMASCANOUT[2]	out	CELL[2].OUT_BEL[20]
PMASCANOUT[3]	out	CELL[2].OUT_BEL[16]
PMASCANOUT[4]	out	CELL[1].OUT_BEL[20]
PMASCANOUT[5]	out	CELL[9].OUT_BEL[11]
PMASCANOUT[6]	out	CELL[8].OUT_BEL[11]
PMASCANOUT[7]	out	CELL[10].OUT_BEL[21]
RSOSINTDONE	out	CELL[0].OUT_BEL[12]
RXBUFSTATUS[0]	out	CELL[10].OUT_BEL[23]
RXBUFSTATUS[1]	out	CELL[10].OUT_BEL[19]
RXBUFSTATUS[2]	out	CELL[10].OUT_BEL[17]
RXBYTEISALIGNED	out	CELL[10].OUT_BEL[18]
RXBYTEREALIGN	out	CELL[10].OUT_BEL[10]
RXCDRLOCK	out	CELL[5].OUT_BEL[17]
RXCHANBONDSEQ	out	CELL[8].OUT_BEL[10]
RXCHANISALIGNED	out	CELL[9].OUT_BEL[18]
RXCHANREALIGN	out	CELL[9].OUT_BEL[23]
RXCHARISCOMMA[0]	out	CELL[9].OUT_BEL[15]
RXCHARISCOMMA[1]	out	CELL[7].OUT_BEL[15]
RXCHARISCOMMA[2]	out	CELL[5].OUT_BEL[15]
RXCHARISCOMMA[3]	out	CELL[3].OUT_BEL[15]
RXCHARISCOMMA[4]	out	CELL[10].OUT_BEL[15]
RXCHARISCOMMA[5]	out	CELL[8].OUT_BEL[15]
RXCHARISCOMMA[6]	out	CELL[6].OUT_BEL[15]
RXCHARISCOMMA[7]	out	CELL[4].OUT_BEL[15]
RXCHARISK[0]	out	CELL[10].OUT_BEL[12]
RXCHARISK[1]	out	CELL[8].OUT_BEL[12]
RXCHARISK[2]	out	CELL[6].OUT_BEL[12]
RXCHARISK[3]	out	CELL[4].OUT_BEL[12]
RXCHARISK[4]	out	CELL[9].OUT_BEL[12]
RXCHARISK[5]	out	CELL[7].OUT_BEL[12]
RXCHARISK[6]	out	CELL[5].OUT_BEL[12]
RXCHARISK[7]	out	CELL[3].OUT_BEL[12]
RXCHBONDO[0]	out	CELL[10].OUT_BEL[16]
RXCHBONDO[1]	out	CELL[9].OUT_BEL[16]
RXCHBONDO[2]	out	CELL[8].OUT_BEL[16]
RXCHBONDO[3]	out	CELL[7].OUT_BEL[16]
RXCHBONDO[4]	out	CELL[6].OUT_BEL[16]
RXCLKCORCNT[0]	out	CELL[5].OUT_BEL[18]
RXCLKCORCNT[1]	out	CELL[5].OUT_BEL[20]
RXCOMINITDET	out	CELL[7].OUT_BEL[20]
RXCOMMADET	out	CELL[7].OUT_BEL[19]
RXCOMSASDET	out	CELL[7].OUT_BEL[18]
RXCOMWAKEDET	out	CELL[9].OUT_BEL[19]
RXDATA[0]	out	CELL[10].OUT_BEL[6]
RXDATA[1]	out	CELL[10].OUT_BEL[2]
RXDATA[2]	out	CELL[10].OUT_BEL[4]
RXDATA[3]	out	CELL[10].OUT_BEL[0]
RXDATA[4]	out	CELL[9].OUT_BEL[3]
RXDATA[5]	out	CELL[9].OUT_BEL[7]
RXDATA[6]	out	CELL[9].OUT_BEL[1]
RXDATA[7]	out	CELL[9].OUT_BEL[5]
RXDATA[8]	out	CELL[8].OUT_BEL[6]
RXDATA[9]	out	CELL[8].OUT_BEL[2]
RXDATA[10]	out	CELL[8].OUT_BEL[4]
RXDATA[11]	out	CELL[8].OUT_BEL[0]
RXDATA[12]	out	CELL[7].OUT_BEL[3]
RXDATA[13]	out	CELL[7].OUT_BEL[7]
RXDATA[14]	out	CELL[7].OUT_BEL[1]
RXDATA[15]	out	CELL[7].OUT_BEL[5]
RXDATA[16]	out	CELL[6].OUT_BEL[6]
RXDATA[17]	out	CELL[6].OUT_BEL[2]
RXDATA[18]	out	CELL[6].OUT_BEL[4]
RXDATA[19]	out	CELL[6].OUT_BEL[0]
RXDATA[20]	out	CELL[5].OUT_BEL[3]
RXDATA[21]	out	CELL[5].OUT_BEL[7]
RXDATA[22]	out	CELL[5].OUT_BEL[1]
RXDATA[23]	out	CELL[5].OUT_BEL[5]
RXDATA[24]	out	CELL[4].OUT_BEL[6]
RXDATA[25]	out	CELL[4].OUT_BEL[2]
RXDATA[26]	out	CELL[4].OUT_BEL[4]
RXDATA[27]	out	CELL[4].OUT_BEL[0]
RXDATA[28]	out	CELL[3].OUT_BEL[3]
RXDATA[29]	out	CELL[3].OUT_BEL[7]
RXDATA[30]	out	CELL[3].OUT_BEL[1]
RXDATA[31]	out	CELL[3].OUT_BEL[5]
RXDATA[32]	out	CELL[10].OUT_BEL[3]
RXDATA[33]	out	CELL[10].OUT_BEL[7]
RXDATA[34]	out	CELL[10].OUT_BEL[1]
RXDATA[35]	out	CELL[10].OUT_BEL[5]
RXDATA[36]	out	CELL[9].OUT_BEL[6]
RXDATA[37]	out	CELL[9].OUT_BEL[2]
RXDATA[38]	out	CELL[9].OUT_BEL[4]
RXDATA[39]	out	CELL[9].OUT_BEL[0]
RXDATA[40]	out	CELL[8].OUT_BEL[3]
RXDATA[41]	out	CELL[8].OUT_BEL[7]
RXDATA[42]	out	CELL[8].OUT_BEL[1]
RXDATA[43]	out	CELL[8].OUT_BEL[5]
RXDATA[44]	out	CELL[7].OUT_BEL[6]
RXDATA[45]	out	CELL[7].OUT_BEL[2]
RXDATA[46]	out	CELL[7].OUT_BEL[4]
RXDATA[47]	out	CELL[7].OUT_BEL[0]
RXDATA[48]	out	CELL[6].OUT_BEL[3]
RXDATA[49]	out	CELL[6].OUT_BEL[7]
RXDATA[50]	out	CELL[6].OUT_BEL[1]
RXDATA[51]	out	CELL[6].OUT_BEL[5]
RXDATA[52]	out	CELL[5].OUT_BEL[6]
RXDATA[53]	out	CELL[5].OUT_BEL[2]
RXDATA[54]	out	CELL[5].OUT_BEL[4]
RXDATA[55]	out	CELL[5].OUT_BEL[0]
RXDATA[56]	out	CELL[4].OUT_BEL[3]
RXDATA[57]	out	CELL[4].OUT_BEL[7]
RXDATA[58]	out	CELL[4].OUT_BEL[1]
RXDATA[59]	out	CELL[4].OUT_BEL[5]
RXDATA[60]	out	CELL[3].OUT_BEL[6]
RXDATA[61]	out	CELL[3].OUT_BEL[2]
RXDATA[62]	out	CELL[3].OUT_BEL[4]
RXDATA[63]	out	CELL[3].OUT_BEL[0]
RXDATAVALID[0]	out	CELL[5].OUT_BEL[19]
RXDATAVALID[1]	out	CELL[6].OUT_BEL[18]
RXDFESLIDETAPSTARTED	out	CELL[0].OUT_BEL[11]
RXDFESLIDETAPSTROBEDONE	out	CELL[1].OUT_BEL[11]
RXDFESLIDETAPSTROBESTARTED	out	CELL[2].OUT_BEL[11]
RXDFESTADAPTDONE	out	CELL[3].OUT_BEL[11]
RXDISPERR[0]	out	CELL[10].OUT_BEL[22]
RXDISPERR[1]	out	CELL[8].OUT_BEL[22]
RXDISPERR[2]	out	CELL[6].OUT_BEL[22]
RXDISPERR[3]	out	CELL[4].OUT_BEL[22]
RXDISPERR[4]	out	CELL[9].OUT_BEL[22]
RXDISPERR[5]	out	CELL[7].OUT_BEL[22]
RXDISPERR[6]	out	CELL[5].OUT_BEL[22]
RXDISPERR[7]	out	CELL[3].OUT_BEL[22]
RXDLYSRESETDONE	out	CELL[1].OUT_BEL[22]
RXELECIDLE	out	CELL[8].OUT_BEL[19]
RXHEADER[0]	out	CELL[6].OUT_BEL[19]
RXHEADER[1]	out	CELL[6].OUT_BEL[23]
RXHEADER[2]	out	CELL[6].OUT_BEL[17]
RXHEADER[3]	out	CELL[1].OUT_BEL[23]
RXHEADER[4]	out	CELL[0].OUT_BEL[23]
RXHEADER[5]	out	CELL[0].OUT_BEL[15]
RXHEADERVALID[0]	out	CELL[7].OUT_BEL[23]
RXHEADERVALID[1]	out	CELL[7].OUT_BEL[17]
RXMONITOROUT[0]	out	CELL[10].OUT_BEL[8]
RXMONITOROUT[1]	out	CELL[9].OUT_BEL[8]
RXMONITOROUT[2]	out	CELL[8].OUT_BEL[8]
RXMONITOROUT[3]	out	CELL[7].OUT_BEL[8]
RXMONITOROUT[4]	out	CELL[6].OUT_BEL[8]
RXMONITOROUT[5]	out	CELL[5].OUT_BEL[8]
RXMONITOROUT[6]	out	CELL[4].OUT_BEL[8]
RXNOTINTABLE[0]	out	CELL[10].OUT_BEL[14]
RXNOTINTABLE[1]	out	CELL[8].OUT_BEL[14]
RXNOTINTABLE[2]	out	CELL[6].OUT_BEL[14]
RXNOTINTABLE[3]	out	CELL[4].OUT_BEL[14]
RXNOTINTABLE[4]	out	CELL[9].OUT_BEL[14]
RXNOTINTABLE[5]	out	CELL[7].OUT_BEL[14]
RXNOTINTABLE[6]	out	CELL[5].OUT_BEL[14]
RXNOTINTABLE[7]	out	CELL[3].OUT_BEL[14]
RXOSINTSTARTED	out	CELL[4].OUT_BEL[11]
RXOSINTSTROBEDONE	out	CELL[5].OUT_BEL[11]
RXOSINTSTROBESTARTED	out	CELL[6].OUT_BEL[11]
RXOUTCLK	out	CELL[0].OUT_GT_RXOUTCLK
RXOUTCLKFABRIC	out	CELL[9].OUT_BEL[17]
RXOUTCLKPCS	out	CELL[9].OUT_BEL[21]
RXPHALIGNDONE	out	CELL[4].OUT_BEL[18]
RXPHMONITOR[0]	out	CELL[2].OUT_BEL[5]
RXPHMONITOR[1]	out	CELL[2].OUT_BEL[1]
RXPHMONITOR[2]	out	CELL[2].OUT_BEL[7]
RXPHMONITOR[3]	out	CELL[2].OUT_BEL[3]
RXPHMONITOR[4]	out	CELL[3].OUT_BEL[21]
RXPHSLIPMONITOR[0]	out	CELL[2].OUT_BEL[0]
RXPHSLIPMONITOR[1]	out	CELL[2].OUT_BEL[4]
RXPHSLIPMONITOR[2]	out	CELL[2].OUT_BEL[2]
RXPHSLIPMONITOR[3]	out	CELL[2].OUT_BEL[6]
RXPHSLIPMONITOR[4]	out	CELL[3].OUT_BEL[16]
RXPMARESETDONE	out	CELL[2].OUT_BEL[12]
RXPRBSERR	out	CELL[6].OUT_BEL[20]
RXQPISENN	out	CELL[1].OUT_BEL[17]
RXQPISENP	out	CELL[1].OUT_BEL[15]
RXRATEDONE	out	CELL[5].OUT_BEL[23]
RXRESETDONE	out	CELL[8].OUT_BEL[20]
RXSTARTOFSEQ[0]	out	CELL[8].OUT_BEL[18]
RXSTARTOFSEQ[1]	out	CELL[10].OUT_BEL[11]
RXSTATUS[0]	out	CELL[8].OUT_BEL[21]
RXSTATUS[1]	out	CELL[8].OUT_BEL[17]
RXSTATUS[2]	out	CELL[8].OUT_BEL[23]
RXSYNCDONE	out	CELL[0].OUT_BEL[14]
RXSYNCOUT	out	CELL[0].OUT_BEL[8]
RXVALID	out	CELL[9].OUT_BEL[20]
TXBUFSTATUS[0]	out	CELL[2].OUT_BEL[17]
TXBUFSTATUS[1]	out	CELL[2].OUT_BEL[21]
TXCOMFINISH	out	CELL[5].OUT_BEL[16]
TXDLYSRESETDONE	out	CELL[3].OUT_BEL[17]
TXGEARBOXREADY	out	CELL[4].OUT_BEL[23]
TXOUTCLK	out	CELL[0].OUT_GT_TXOUTCLK
TXOUTCLKFABRIC	out	CELL[3].OUT_BEL[23]
TXOUTCLKPCS	out	CELL[4].OUT_BEL[17]
TXPHALIGNDONE	out	CELL[3].OUT_BEL[18]
TXPHINITDONE	out	CELL[0].OUT_BEL[17]
TXPMARESETDONE	out	CELL[2].OUT_BEL[14]
TXQPISENN	out	CELL[3].OUT_BEL[20]
TXQPISENP	out	CELL[3].OUT_BEL[8]
TXRATEDONE	out	CELL[4].OUT_BEL[20]
TXRESETDONE	out	CELL[4].OUT_BEL[16]
TXRUNDISP[0]	out	CELL[0].OUT_BEL[10]
TXRUNDISP[1]	out	CELL[2].OUT_BEL[10]
TXRUNDISP[2]	out	CELL[4].OUT_BEL[10]
TXRUNDISP[3]	out	CELL[6].OUT_BEL[10]
TXRUNDISP[4]	out	CELL[1].OUT_BEL[10]
TXRUNDISP[5]	out	CELL[3].OUT_BEL[10]
TXRUNDISP[6]	out	CELL[5].OUT_BEL[10]
TXRUNDISP[7]	out	CELL[7].OUT_BEL[10]
TXSYNCDONE	out	CELL[0].OUT_BEL[22]
TXSYNCOUT	out	CELL[0].OUT_BEL[18]
SCANOUT[0]	out	CELL[0].OUT_BEL[19]
SCANOUT[1]	out	CELL[1].OUT_BEL[19]
SCANOUT[2]	out	CELL[2].OUT_BEL[19]
SCANOUT[3]	out	CELL[3].OUT_BEL[19]
SCANOUT[4]	out	CELL[4].OUT_BEL[19]
SCANOUT[5]	out	CELL[7].OUT_BEL[11]

virtex7 GTH_CHANNEL bel GTX_CHANNEL attribute bits
Attribute	GTX_CHANNEL
DRP[0] bit 0	MAIN[0][28][0]
DRP[0] bit 1	MAIN[0][29][0]
DRP[0] bit 2	MAIN[0][28][1]
DRP[0] bit 3	MAIN[0][29][1]
DRP[0] bit 4	MAIN[0][28][2]
DRP[0] bit 5	MAIN[0][29][2]
DRP[0] bit 6	MAIN[0][28][3]
DRP[0] bit 7	MAIN[0][29][3]
DRP[0] bit 8	MAIN[0][28][4]
DRP[0] bit 9	MAIN[0][29][4]
DRP[0] bit 10	MAIN[0][28][5]
DRP[0] bit 11	MAIN[0][29][5]
DRP[0] bit 12	MAIN[0][28][6]
DRP[0] bit 13	MAIN[0][29][6]
DRP[0] bit 14	MAIN[0][28][7]
DRP[0] bit 15	MAIN[0][29][7]
DRP[1] bit 0	MAIN[0][28][8]
DRP[1] bit 1	MAIN[0][29][8]
DRP[1] bit 2	MAIN[0][28][9]
DRP[1] bit 3	MAIN[0][29][9]
DRP[1] bit 4	MAIN[0][28][10]
DRP[1] bit 5	MAIN[0][29][10]
DRP[1] bit 6	MAIN[0][28][11]
DRP[1] bit 7	MAIN[0][29][11]
DRP[1] bit 8	MAIN[0][28][12]
DRP[1] bit 9	MAIN[0][29][12]
DRP[1] bit 10	MAIN[0][28][13]
DRP[1] bit 11	MAIN[0][29][13]
DRP[1] bit 12	MAIN[0][28][14]
DRP[1] bit 13	MAIN[0][29][14]
DRP[1] bit 14	MAIN[0][28][15]
DRP[1] bit 15	MAIN[0][29][15]
DRP[2] bit 0	MAIN[0][28][16]
DRP[2] bit 1	MAIN[0][29][16]
DRP[2] bit 2	MAIN[0][28][17]
DRP[2] bit 3	MAIN[0][29][17]
DRP[2] bit 4	MAIN[0][28][18]
DRP[2] bit 5	MAIN[0][29][18]
DRP[2] bit 6	MAIN[0][28][19]
DRP[2] bit 7	MAIN[0][29][19]
DRP[2] bit 8	MAIN[0][28][20]
DRP[2] bit 9	MAIN[0][29][20]
DRP[2] bit 10	MAIN[0][28][21]
DRP[2] bit 11	MAIN[0][29][21]
DRP[2] bit 12	MAIN[0][28][22]
DRP[2] bit 13	MAIN[0][29][22]
DRP[2] bit 14	MAIN[0][28][23]
DRP[2] bit 15	MAIN[0][29][23]
DRP[3] bit 0	MAIN[0][28][24]
DRP[3] bit 1	MAIN[0][29][24]
DRP[3] bit 2	MAIN[0][28][25]
DRP[3] bit 3	MAIN[0][29][25]
DRP[3] bit 4	MAIN[0][28][26]
DRP[3] bit 5	MAIN[0][29][26]
DRP[3] bit 6	MAIN[0][28][27]
DRP[3] bit 7	MAIN[0][29][27]
DRP[3] bit 8	MAIN[0][28][28]
DRP[3] bit 9	MAIN[0][29][28]
DRP[3] bit 10	MAIN[0][28][29]
DRP[3] bit 11	MAIN[0][29][29]
DRP[3] bit 12	MAIN[0][28][30]
DRP[3] bit 13	MAIN[0][29][30]
DRP[3] bit 14	MAIN[0][28][31]
DRP[3] bit 15	MAIN[0][29][31]
DRP[4] bit 0	MAIN[0][28][32]
DRP[4] bit 1	MAIN[0][29][32]
DRP[4] bit 2	MAIN[0][28][33]
DRP[4] bit 3	MAIN[0][29][33]
DRP[4] bit 4	MAIN[0][28][34]
DRP[4] bit 5	MAIN[0][29][34]
DRP[4] bit 6	MAIN[0][28][35]
DRP[4] bit 7	MAIN[0][29][35]
DRP[4] bit 8	MAIN[0][28][36]
DRP[4] bit 9	MAIN[0][29][36]
DRP[4] bit 10	MAIN[0][28][37]
DRP[4] bit 11	MAIN[0][29][37]
DRP[4] bit 12	MAIN[0][28][38]
DRP[4] bit 13	MAIN[0][29][38]
DRP[4] bit 14	MAIN[0][28][39]
DRP[4] bit 15	MAIN[0][29][39]
DRP[5] bit 0	MAIN[0][28][40]
DRP[5] bit 1	MAIN[0][29][40]
DRP[5] bit 2	MAIN[0][28][41]
DRP[5] bit 3	MAIN[0][29][41]
DRP[5] bit 4	MAIN[0][28][42]
DRP[5] bit 5	MAIN[0][29][42]
DRP[5] bit 6	MAIN[0][28][43]
DRP[5] bit 7	MAIN[0][29][43]
DRP[5] bit 8	MAIN[0][28][44]
DRP[5] bit 9	MAIN[0][29][44]
DRP[5] bit 10	MAIN[0][28][45]
DRP[5] bit 11	MAIN[0][29][45]
DRP[5] bit 12	MAIN[0][28][46]
DRP[5] bit 13	MAIN[0][29][46]
DRP[5] bit 14	MAIN[0][28][47]
DRP[5] bit 15	MAIN[0][29][47]
DRP[6] bit 0	MAIN[0][28][48]
DRP[6] bit 1	MAIN[0][29][48]
DRP[6] bit 2	MAIN[0][28][49]
DRP[6] bit 3	MAIN[0][29][49]
DRP[6] bit 4	MAIN[0][28][50]
DRP[6] bit 5	MAIN[0][29][50]
DRP[6] bit 6	MAIN[0][28][51]
DRP[6] bit 7	MAIN[0][29][51]
DRP[6] bit 8	MAIN[0][28][52]
DRP[6] bit 9	MAIN[0][29][52]
DRP[6] bit 10	MAIN[0][28][53]
DRP[6] bit 11	MAIN[0][29][53]
DRP[6] bit 12	MAIN[0][28][54]
DRP[6] bit 13	MAIN[0][29][54]
DRP[6] bit 14	MAIN[0][28][55]
DRP[6] bit 15	MAIN[0][29][55]
DRP[7] bit 0	MAIN[0][28][56]
DRP[7] bit 1	MAIN[0][29][56]
DRP[7] bit 2	MAIN[0][28][57]
DRP[7] bit 3	MAIN[0][29][57]
DRP[7] bit 4	MAIN[0][28][58]
DRP[7] bit 5	MAIN[0][29][58]
DRP[7] bit 6	MAIN[0][28][59]
DRP[7] bit 7	MAIN[0][29][59]
DRP[7] bit 8	MAIN[0][28][60]
DRP[7] bit 9	MAIN[0][29][60]
DRP[7] bit 10	MAIN[0][28][61]
DRP[7] bit 11	MAIN[0][29][61]
DRP[7] bit 12	MAIN[0][28][62]
DRP[7] bit 13	MAIN[0][29][62]
DRP[7] bit 14	MAIN[0][28][63]
DRP[7] bit 15	MAIN[0][29][63]
DRP[8] bit 0	MAIN[1][28][0]
DRP[8] bit 1	MAIN[1][29][0]
DRP[8] bit 2	MAIN[1][28][1]
DRP[8] bit 3	MAIN[1][29][1]
DRP[8] bit 4	MAIN[1][28][2]
DRP[8] bit 5	MAIN[1][29][2]
DRP[8] bit 6	MAIN[1][28][3]
DRP[8] bit 7	MAIN[1][29][3]
DRP[8] bit 8	MAIN[1][28][4]
DRP[8] bit 9	MAIN[1][29][4]
DRP[8] bit 10	MAIN[1][28][5]
DRP[8] bit 11	MAIN[1][29][5]
DRP[8] bit 12	MAIN[1][28][6]
DRP[8] bit 13	MAIN[1][29][6]
DRP[8] bit 14	MAIN[1][28][7]
DRP[8] bit 15	MAIN[1][29][7]
DRP[9] bit 0	MAIN[1][28][8]
DRP[9] bit 1	MAIN[1][29][8]
DRP[9] bit 2	MAIN[1][28][9]
DRP[9] bit 3	MAIN[1][29][9]
DRP[9] bit 4	MAIN[1][28][10]
DRP[9] bit 5	MAIN[1][29][10]
DRP[9] bit 6	MAIN[1][28][11]
DRP[9] bit 7	MAIN[1][29][11]
DRP[9] bit 8	MAIN[1][28][12]
DRP[9] bit 9	MAIN[1][29][12]
DRP[9] bit 10	MAIN[1][28][13]
DRP[9] bit 11	MAIN[1][29][13]
DRP[9] bit 12	MAIN[1][28][14]
DRP[9] bit 13	MAIN[1][29][14]
DRP[9] bit 14	MAIN[1][28][15]
DRP[9] bit 15	MAIN[1][29][15]
DRP[10] bit 0	MAIN[1][28][16]
DRP[10] bit 1	MAIN[1][29][16]
DRP[10] bit 2	MAIN[1][28][17]
DRP[10] bit 3	MAIN[1][29][17]
DRP[10] bit 4	MAIN[1][28][18]
DRP[10] bit 5	MAIN[1][29][18]
DRP[10] bit 6	MAIN[1][28][19]
DRP[10] bit 7	MAIN[1][29][19]
DRP[10] bit 8	MAIN[1][28][20]
DRP[10] bit 9	MAIN[1][29][20]
DRP[10] bit 10	MAIN[1][28][21]
DRP[10] bit 11	MAIN[1][29][21]
DRP[10] bit 12	MAIN[1][28][22]
DRP[10] bit 13	MAIN[1][29][22]
DRP[10] bit 14	MAIN[1][28][23]
DRP[10] bit 15	MAIN[1][29][23]
DRP[11] bit 0	MAIN[1][28][24]
DRP[11] bit 1	MAIN[1][29][24]
DRP[11] bit 2	MAIN[1][28][25]
DRP[11] bit 3	MAIN[1][29][25]
DRP[11] bit 4	MAIN[1][28][26]
DRP[11] bit 5	MAIN[1][29][26]
DRP[11] bit 6	MAIN[1][28][27]
DRP[11] bit 7	MAIN[1][29][27]
DRP[11] bit 8	MAIN[1][28][28]
DRP[11] bit 9	MAIN[1][29][28]
DRP[11] bit 10	MAIN[1][28][29]
DRP[11] bit 11	MAIN[1][29][29]
DRP[11] bit 12	MAIN[1][28][30]
DRP[11] bit 13	MAIN[1][29][30]
DRP[11] bit 14	MAIN[1][28][31]
DRP[11] bit 15	MAIN[1][29][31]
DRP[12] bit 0	MAIN[1][28][32]
DRP[12] bit 1	MAIN[1][29][32]
DRP[12] bit 2	MAIN[1][28][33]
DRP[12] bit 3	MAIN[1][29][33]
DRP[12] bit 4	MAIN[1][28][34]
DRP[12] bit 5	MAIN[1][29][34]
DRP[12] bit 6	MAIN[1][28][35]
DRP[12] bit 7	MAIN[1][29][35]
DRP[12] bit 8	MAIN[1][28][36]
DRP[12] bit 9	MAIN[1][29][36]
DRP[12] bit 10	MAIN[1][28][37]
DRP[12] bit 11	MAIN[1][29][37]
DRP[12] bit 12	MAIN[1][28][38]
DRP[12] bit 13	MAIN[1][29][38]
DRP[12] bit 14	MAIN[1][28][39]
DRP[12] bit 15	MAIN[1][29][39]
DRP[13] bit 0	MAIN[1][28][40]
DRP[13] bit 1	MAIN[1][29][40]
DRP[13] bit 2	MAIN[1][28][41]
DRP[13] bit 3	MAIN[1][29][41]
DRP[13] bit 4	MAIN[1][28][42]
DRP[13] bit 5	MAIN[1][29][42]
DRP[13] bit 6	MAIN[1][28][43]
DRP[13] bit 7	MAIN[1][29][43]
DRP[13] bit 8	MAIN[1][28][44]
DRP[13] bit 9	MAIN[1][29][44]
DRP[13] bit 10	MAIN[1][28][45]
DRP[13] bit 11	MAIN[1][29][45]
DRP[13] bit 12	MAIN[1][28][46]
DRP[13] bit 13	MAIN[1][29][46]
DRP[13] bit 14	MAIN[1][28][47]
DRP[13] bit 15	MAIN[1][29][47]
DRP[14] bit 0	MAIN[1][28][48]
DRP[14] bit 1	MAIN[1][29][48]
DRP[14] bit 2	MAIN[1][28][49]
DRP[14] bit 3	MAIN[1][29][49]
DRP[14] bit 4	MAIN[1][28][50]
DRP[14] bit 5	MAIN[1][29][50]
DRP[14] bit 6	MAIN[1][28][51]
DRP[14] bit 7	MAIN[1][29][51]
DRP[14] bit 8	MAIN[1][28][52]
DRP[14] bit 9	MAIN[1][29][52]
DRP[14] bit 10	MAIN[1][28][53]
DRP[14] bit 11	MAIN[1][29][53]
DRP[14] bit 12	MAIN[1][28][54]
DRP[14] bit 13	MAIN[1][29][54]
DRP[14] bit 14	MAIN[1][28][55]
DRP[14] bit 15	MAIN[1][29][55]
DRP[15] bit 0	MAIN[1][28][56]
DRP[15] bit 1	MAIN[1][29][56]
DRP[15] bit 2	MAIN[1][28][57]
DRP[15] bit 3	MAIN[1][29][57]
DRP[15] bit 4	MAIN[1][28][58]
DRP[15] bit 5	MAIN[1][29][58]
DRP[15] bit 6	MAIN[1][28][59]
DRP[15] bit 7	MAIN[1][29][59]
DRP[15] bit 8	MAIN[1][28][60]
DRP[15] bit 9	MAIN[1][29][60]
DRP[15] bit 10	MAIN[1][28][61]
DRP[15] bit 11	MAIN[1][29][61]
DRP[15] bit 12	MAIN[1][28][62]
DRP[15] bit 13	MAIN[1][29][62]
DRP[15] bit 14	MAIN[1][28][63]
DRP[15] bit 15	MAIN[1][29][63]
DRP[16] bit 0	MAIN[2][28][0]
DRP[16] bit 1	MAIN[2][29][0]
DRP[16] bit 2	MAIN[2][28][1]
DRP[16] bit 3	MAIN[2][29][1]
DRP[16] bit 4	MAIN[2][28][2]
DRP[16] bit 5	MAIN[2][29][2]
DRP[16] bit 6	MAIN[2][28][3]
DRP[16] bit 7	MAIN[2][29][3]
DRP[16] bit 8	MAIN[2][28][4]
DRP[16] bit 9	MAIN[2][29][4]
DRP[16] bit 10	MAIN[2][28][5]
DRP[16] bit 11	MAIN[2][29][5]
DRP[16] bit 12	MAIN[2][28][6]
DRP[16] bit 13	MAIN[2][29][6]
DRP[16] bit 14	MAIN[2][28][7]
DRP[16] bit 15	MAIN[2][29][7]
DRP[17] bit 0	MAIN[2][28][8]
DRP[17] bit 1	MAIN[2][29][8]
DRP[17] bit 2	MAIN[2][28][9]
DRP[17] bit 3	MAIN[2][29][9]
DRP[17] bit 4	MAIN[2][28][10]
DRP[17] bit 5	MAIN[2][29][10]
DRP[17] bit 6	MAIN[2][28][11]
DRP[17] bit 7	MAIN[2][29][11]
DRP[17] bit 8	MAIN[2][28][12]
DRP[17] bit 9	MAIN[2][29][12]
DRP[17] bit 10	MAIN[2][28][13]
DRP[17] bit 11	MAIN[2][29][13]
DRP[17] bit 12	MAIN[2][28][14]
DRP[17] bit 13	MAIN[2][29][14]
DRP[17] bit 14	MAIN[2][28][15]
DRP[17] bit 15	MAIN[2][29][15]
DRP[18] bit 0	MAIN[2][28][16]
DRP[18] bit 1	MAIN[2][29][16]
DRP[18] bit 2	MAIN[2][28][17]
DRP[18] bit 3	MAIN[2][29][17]
DRP[18] bit 4	MAIN[2][28][18]
DRP[18] bit 5	MAIN[2][29][18]
DRP[18] bit 6	MAIN[2][28][19]
DRP[18] bit 7	MAIN[2][29][19]
DRP[18] bit 8	MAIN[2][28][20]
DRP[18] bit 9	MAIN[2][29][20]
DRP[18] bit 10	MAIN[2][28][21]
DRP[18] bit 11	MAIN[2][29][21]
DRP[18] bit 12	MAIN[2][28][22]
DRP[18] bit 13	MAIN[2][29][22]
DRP[18] bit 14	MAIN[2][28][23]
DRP[18] bit 15	MAIN[2][29][23]
DRP[19] bit 0	MAIN[2][28][24]
DRP[19] bit 1	MAIN[2][29][24]
DRP[19] bit 2	MAIN[2][28][25]
DRP[19] bit 3	MAIN[2][29][25]
DRP[19] bit 4	MAIN[2][28][26]
DRP[19] bit 5	MAIN[2][29][26]
DRP[19] bit 6	MAIN[2][28][27]
DRP[19] bit 7	MAIN[2][29][27]
DRP[19] bit 8	MAIN[2][28][28]
DRP[19] bit 9	MAIN[2][29][28]
DRP[19] bit 10	MAIN[2][28][29]
DRP[19] bit 11	MAIN[2][29][29]
DRP[19] bit 12	MAIN[2][28][30]
DRP[19] bit 13	MAIN[2][29][30]
DRP[19] bit 14	MAIN[2][28][31]
DRP[19] bit 15	MAIN[2][29][31]
DRP[20] bit 0	MAIN[2][28][32]
DRP[20] bit 1	MAIN[2][29][32]
DRP[20] bit 2	MAIN[2][28][33]
DRP[20] bit 3	MAIN[2][29][33]
DRP[20] bit 4	MAIN[2][28][34]
DRP[20] bit 5	MAIN[2][29][34]
DRP[20] bit 6	MAIN[2][28][35]
DRP[20] bit 7	MAIN[2][29][35]
DRP[20] bit 8	MAIN[2][28][36]
DRP[20] bit 9	MAIN[2][29][36]
DRP[20] bit 10	MAIN[2][28][37]
DRP[20] bit 11	MAIN[2][29][37]
DRP[20] bit 12	MAIN[2][28][38]
DRP[20] bit 13	MAIN[2][29][38]
DRP[20] bit 14	MAIN[2][28][39]
DRP[20] bit 15	MAIN[2][29][39]
DRP[21] bit 0	MAIN[2][28][40]
DRP[21] bit 1	MAIN[2][29][40]
DRP[21] bit 2	MAIN[2][28][41]
DRP[21] bit 3	MAIN[2][29][41]
DRP[21] bit 4	MAIN[2][28][42]
DRP[21] bit 5	MAIN[2][29][42]
DRP[21] bit 6	MAIN[2][28][43]
DRP[21] bit 7	MAIN[2][29][43]
DRP[21] bit 8	MAIN[2][28][44]
DRP[21] bit 9	MAIN[2][29][44]
DRP[21] bit 10	MAIN[2][28][45]
DRP[21] bit 11	MAIN[2][29][45]
DRP[21] bit 12	MAIN[2][28][46]
DRP[21] bit 13	MAIN[2][29][46]
DRP[21] bit 14	MAIN[2][28][47]
DRP[21] bit 15	MAIN[2][29][47]
DRP[22] bit 0	MAIN[2][28][48]
DRP[22] bit 1	MAIN[2][29][48]
DRP[22] bit 2	MAIN[2][28][49]
DRP[22] bit 3	MAIN[2][29][49]
DRP[22] bit 4	MAIN[2][28][50]
DRP[22] bit 5	MAIN[2][29][50]
DRP[22] bit 6	MAIN[2][28][51]
DRP[22] bit 7	MAIN[2][29][51]
DRP[22] bit 8	MAIN[2][28][52]
DRP[22] bit 9	MAIN[2][29][52]
DRP[22] bit 10	MAIN[2][28][53]
DRP[22] bit 11	MAIN[2][29][53]
DRP[22] bit 12	MAIN[2][28][54]
DRP[22] bit 13	MAIN[2][29][54]
DRP[22] bit 14	MAIN[2][28][55]
DRP[22] bit 15	MAIN[2][29][55]
DRP[23] bit 0	MAIN[2][28][56]
DRP[23] bit 1	MAIN[2][29][56]
DRP[23] bit 2	MAIN[2][28][57]
DRP[23] bit 3	MAIN[2][29][57]
DRP[23] bit 4	MAIN[2][28][58]
DRP[23] bit 5	MAIN[2][29][58]
DRP[23] bit 6	MAIN[2][28][59]
DRP[23] bit 7	MAIN[2][29][59]
DRP[23] bit 8	MAIN[2][28][60]
DRP[23] bit 9	MAIN[2][29][60]
DRP[23] bit 10	MAIN[2][28][61]
DRP[23] bit 11	MAIN[2][29][61]
DRP[23] bit 12	MAIN[2][28][62]
DRP[23] bit 13	MAIN[2][29][62]
DRP[23] bit 14	MAIN[2][28][63]
DRP[23] bit 15	MAIN[2][29][63]
DRP[24] bit 0	MAIN[3][28][0]
DRP[24] bit 1	MAIN[3][29][0]
DRP[24] bit 2	MAIN[3][28][1]
DRP[24] bit 3	MAIN[3][29][1]
DRP[24] bit 4	MAIN[3][28][2]
DRP[24] bit 5	MAIN[3][29][2]
DRP[24] bit 6	MAIN[3][28][3]
DRP[24] bit 7	MAIN[3][29][3]
DRP[24] bit 8	MAIN[3][28][4]
DRP[24] bit 9	MAIN[3][29][4]
DRP[24] bit 10	MAIN[3][28][5]
DRP[24] bit 11	MAIN[3][29][5]
DRP[24] bit 12	MAIN[3][28][6]
DRP[24] bit 13	MAIN[3][29][6]
DRP[24] bit 14	MAIN[3][28][7]
DRP[24] bit 15	MAIN[3][29][7]
DRP[25] bit 0	MAIN[3][28][8]
DRP[25] bit 1	MAIN[3][29][8]
DRP[25] bit 2	MAIN[3][28][9]
DRP[25] bit 3	MAIN[3][29][9]
DRP[25] bit 4	MAIN[3][28][10]
DRP[25] bit 5	MAIN[3][29][10]
DRP[25] bit 6	MAIN[3][28][11]
DRP[25] bit 7	MAIN[3][29][11]
DRP[25] bit 8	MAIN[3][28][12]
DRP[25] bit 9	MAIN[3][29][12]
DRP[25] bit 10	MAIN[3][28][13]
DRP[25] bit 11	MAIN[3][29][13]
DRP[25] bit 12	MAIN[3][28][14]
DRP[25] bit 13	MAIN[3][29][14]
DRP[25] bit 14	MAIN[3][28][15]
DRP[25] bit 15	MAIN[3][29][15]
DRP[26] bit 0	MAIN[3][28][16]
DRP[26] bit 1	MAIN[3][29][16]
DRP[26] bit 2	MAIN[3][28][17]
DRP[26] bit 3	MAIN[3][29][17]
DRP[26] bit 4	MAIN[3][28][18]
DRP[26] bit 5	MAIN[3][29][18]
DRP[26] bit 6	MAIN[3][28][19]
DRP[26] bit 7	MAIN[3][29][19]
DRP[26] bit 8	MAIN[3][28][20]
DRP[26] bit 9	MAIN[3][29][20]
DRP[26] bit 10	MAIN[3][28][21]
DRP[26] bit 11	MAIN[3][29][21]
DRP[26] bit 12	MAIN[3][28][22]
DRP[26] bit 13	MAIN[3][29][22]
DRP[26] bit 14	MAIN[3][28][23]
DRP[26] bit 15	MAIN[3][29][23]
DRP[27] bit 0	MAIN[3][28][24]
DRP[27] bit 1	MAIN[3][29][24]
DRP[27] bit 2	MAIN[3][28][25]
DRP[27] bit 3	MAIN[3][29][25]
DRP[27] bit 4	MAIN[3][28][26]
DRP[27] bit 5	MAIN[3][29][26]
DRP[27] bit 6	MAIN[3][28][27]
DRP[27] bit 7	MAIN[3][29][27]
DRP[27] bit 8	MAIN[3][28][28]
DRP[27] bit 9	MAIN[3][29][28]
DRP[27] bit 10	MAIN[3][28][29]
DRP[27] bit 11	MAIN[3][29][29]
DRP[27] bit 12	MAIN[3][28][30]
DRP[27] bit 13	MAIN[3][29][30]
DRP[27] bit 14	MAIN[3][28][31]
DRP[27] bit 15	MAIN[3][29][31]
DRP[28] bit 0	MAIN[3][28][32]
DRP[28] bit 1	MAIN[3][29][32]
DRP[28] bit 2	MAIN[3][28][33]
DRP[28] bit 3	MAIN[3][29][33]
DRP[28] bit 4	MAIN[3][28][34]
DRP[28] bit 5	MAIN[3][29][34]
DRP[28] bit 6	MAIN[3][28][35]
DRP[28] bit 7	MAIN[3][29][35]
DRP[28] bit 8	MAIN[3][28][36]
DRP[28] bit 9	MAIN[3][29][36]
DRP[28] bit 10	MAIN[3][28][37]
DRP[28] bit 11	MAIN[3][29][37]
DRP[28] bit 12	MAIN[3][28][38]
DRP[28] bit 13	MAIN[3][29][38]
DRP[28] bit 14	MAIN[3][28][39]
DRP[28] bit 15	MAIN[3][29][39]
DRP[29] bit 0	MAIN[3][28][40]
DRP[29] bit 1	MAIN[3][29][40]
DRP[29] bit 2	MAIN[3][28][41]
DRP[29] bit 3	MAIN[3][29][41]
DRP[29] bit 4	MAIN[3][28][42]
DRP[29] bit 5	MAIN[3][29][42]
DRP[29] bit 6	MAIN[3][28][43]
DRP[29] bit 7	MAIN[3][29][43]
DRP[29] bit 8	MAIN[3][28][44]
DRP[29] bit 9	MAIN[3][29][44]
DRP[29] bit 10	MAIN[3][28][45]
DRP[29] bit 11	MAIN[3][29][45]
DRP[29] bit 12	MAIN[3][28][46]
DRP[29] bit 13	MAIN[3][29][46]
DRP[29] bit 14	MAIN[3][28][47]
DRP[29] bit 15	MAIN[3][29][47]
DRP[30] bit 0	MAIN[3][28][48]
DRP[30] bit 1	MAIN[3][29][48]
DRP[30] bit 2	MAIN[3][28][49]
DRP[30] bit 3	MAIN[3][29][49]
DRP[30] bit 4	MAIN[3][28][50]
DRP[30] bit 5	MAIN[3][29][50]
DRP[30] bit 6	MAIN[3][28][51]
DRP[30] bit 7	MAIN[3][29][51]
DRP[30] bit 8	MAIN[3][28][52]
DRP[30] bit 9	MAIN[3][29][52]
DRP[30] bit 10	MAIN[3][28][53]
DRP[30] bit 11	MAIN[3][29][53]
DRP[30] bit 12	MAIN[3][28][54]
DRP[30] bit 13	MAIN[3][29][54]
DRP[30] bit 14	MAIN[3][28][55]
DRP[30] bit 15	MAIN[3][29][55]
DRP[31] bit 0	MAIN[3][28][56]
DRP[31] bit 1	MAIN[3][29][56]
DRP[31] bit 2	MAIN[3][28][57]
DRP[31] bit 3	MAIN[3][29][57]
DRP[31] bit 4	MAIN[3][28][58]
DRP[31] bit 5	MAIN[3][29][58]
DRP[31] bit 6	MAIN[3][28][59]
DRP[31] bit 7	MAIN[3][29][59]
DRP[31] bit 8	MAIN[3][28][60]
DRP[31] bit 9	MAIN[3][29][60]
DRP[31] bit 10	MAIN[3][28][61]
DRP[31] bit 11	MAIN[3][29][61]
DRP[31] bit 12	MAIN[3][28][62]
DRP[31] bit 13	MAIN[3][29][62]
DRP[31] bit 14	MAIN[3][28][63]
DRP[31] bit 15	MAIN[3][29][63]
DRP[32] bit 0	MAIN[4][28][0]
DRP[32] bit 1	MAIN[4][29][0]
DRP[32] bit 2	MAIN[4][28][1]
DRP[32] bit 3	MAIN[4][29][1]
DRP[32] bit 4	MAIN[4][28][2]
DRP[32] bit 5	MAIN[4][29][2]
DRP[32] bit 6	MAIN[4][28][3]
DRP[32] bit 7	MAIN[4][29][3]
DRP[32] bit 8	MAIN[4][28][4]
DRP[32] bit 9	MAIN[4][29][4]
DRP[32] bit 10	MAIN[4][28][5]
DRP[32] bit 11	MAIN[4][29][5]
DRP[32] bit 12	MAIN[4][28][6]
DRP[32] bit 13	MAIN[4][29][6]
DRP[32] bit 14	MAIN[4][28][7]
DRP[32] bit 15	MAIN[4][29][7]
DRP[33] bit 0	MAIN[4][28][8]
DRP[33] bit 1	MAIN[4][29][8]
DRP[33] bit 2	MAIN[4][28][9]
DRP[33] bit 3	MAIN[4][29][9]
DRP[33] bit 4	MAIN[4][28][10]
DRP[33] bit 5	MAIN[4][29][10]
DRP[33] bit 6	MAIN[4][28][11]
DRP[33] bit 7	MAIN[4][29][11]
DRP[33] bit 8	MAIN[4][28][12]
DRP[33] bit 9	MAIN[4][29][12]
DRP[33] bit 10	MAIN[4][28][13]
DRP[33] bit 11	MAIN[4][29][13]
DRP[33] bit 12	MAIN[4][28][14]
DRP[33] bit 13	MAIN[4][29][14]
DRP[33] bit 14	MAIN[4][28][15]
DRP[33] bit 15	MAIN[4][29][15]
DRP[34] bit 0	MAIN[4][28][16]
DRP[34] bit 1	MAIN[4][29][16]
DRP[34] bit 2	MAIN[4][28][17]
DRP[34] bit 3	MAIN[4][29][17]
DRP[34] bit 4	MAIN[4][28][18]
DRP[34] bit 5	MAIN[4][29][18]
DRP[34] bit 6	MAIN[4][28][19]
DRP[34] bit 7	MAIN[4][29][19]
DRP[34] bit 8	MAIN[4][28][20]
DRP[34] bit 9	MAIN[4][29][20]
DRP[34] bit 10	MAIN[4][28][21]
DRP[34] bit 11	MAIN[4][29][21]
DRP[34] bit 12	MAIN[4][28][22]
DRP[34] bit 13	MAIN[4][29][22]
DRP[34] bit 14	MAIN[4][28][23]
DRP[34] bit 15	MAIN[4][29][23]
DRP[35] bit 0	MAIN[4][28][24]
DRP[35] bit 1	MAIN[4][29][24]
DRP[35] bit 2	MAIN[4][28][25]
DRP[35] bit 3	MAIN[4][29][25]
DRP[35] bit 4	MAIN[4][28][26]
DRP[35] bit 5	MAIN[4][29][26]
DRP[35] bit 6	MAIN[4][28][27]
DRP[35] bit 7	MAIN[4][29][27]
DRP[35] bit 8	MAIN[4][28][28]
DRP[35] bit 9	MAIN[4][29][28]
DRP[35] bit 10	MAIN[4][28][29]
DRP[35] bit 11	MAIN[4][29][29]
DRP[35] bit 12	MAIN[4][28][30]
DRP[35] bit 13	MAIN[4][29][30]
DRP[35] bit 14	MAIN[4][28][31]
DRP[35] bit 15	MAIN[4][29][31]
DRP[36] bit 0	MAIN[4][28][32]
DRP[36] bit 1	MAIN[4][29][32]
DRP[36] bit 2	MAIN[4][28][33]
DRP[36] bit 3	MAIN[4][29][33]
DRP[36] bit 4	MAIN[4][28][34]
DRP[36] bit 5	MAIN[4][29][34]
DRP[36] bit 6	MAIN[4][28][35]
DRP[36] bit 7	MAIN[4][29][35]
DRP[36] bit 8	MAIN[4][28][36]
DRP[36] bit 9	MAIN[4][29][36]
DRP[36] bit 10	MAIN[4][28][37]
DRP[36] bit 11	MAIN[4][29][37]
DRP[36] bit 12	MAIN[4][28][38]
DRP[36] bit 13	MAIN[4][29][38]
DRP[36] bit 14	MAIN[4][28][39]
DRP[36] bit 15	MAIN[4][29][39]
DRP[37] bit 0	MAIN[4][28][40]
DRP[37] bit 1	MAIN[4][29][40]
DRP[37] bit 2	MAIN[4][28][41]
DRP[37] bit 3	MAIN[4][29][41]
DRP[37] bit 4	MAIN[4][28][42]
DRP[37] bit 5	MAIN[4][29][42]
DRP[37] bit 6	MAIN[4][28][43]
DRP[37] bit 7	MAIN[4][29][43]
DRP[37] bit 8	MAIN[4][28][44]
DRP[37] bit 9	MAIN[4][29][44]
DRP[37] bit 10	MAIN[4][28][45]
DRP[37] bit 11	MAIN[4][29][45]
DRP[37] bit 12	MAIN[4][28][46]
DRP[37] bit 13	MAIN[4][29][46]
DRP[37] bit 14	MAIN[4][28][47]
DRP[37] bit 15	MAIN[4][29][47]
DRP[38] bit 0	MAIN[4][28][48]
DRP[38] bit 1	MAIN[4][29][48]
DRP[38] bit 2	MAIN[4][28][49]
DRP[38] bit 3	MAIN[4][29][49]
DRP[38] bit 4	MAIN[4][28][50]
DRP[38] bit 5	MAIN[4][29][50]
DRP[38] bit 6	MAIN[4][28][51]
DRP[38] bit 7	MAIN[4][29][51]
DRP[38] bit 8	MAIN[4][28][52]
DRP[38] bit 9	MAIN[4][29][52]
DRP[38] bit 10	MAIN[4][28][53]
DRP[38] bit 11	MAIN[4][29][53]
DRP[38] bit 12	MAIN[4][28][54]
DRP[38] bit 13	MAIN[4][29][54]
DRP[38] bit 14	MAIN[4][28][55]
DRP[38] bit 15	MAIN[4][29][55]
DRP[39] bit 0	MAIN[4][28][56]
DRP[39] bit 1	MAIN[4][29][56]
DRP[39] bit 2	MAIN[4][28][57]
DRP[39] bit 3	MAIN[4][29][57]
DRP[39] bit 4	MAIN[4][28][58]
DRP[39] bit 5	MAIN[4][29][58]
DRP[39] bit 6	MAIN[4][28][59]
DRP[39] bit 7	MAIN[4][29][59]
DRP[39] bit 8	MAIN[4][28][60]
DRP[39] bit 9	MAIN[4][29][60]
DRP[39] bit 10	MAIN[4][28][61]
DRP[39] bit 11	MAIN[4][29][61]
DRP[39] bit 12	MAIN[4][28][62]
DRP[39] bit 13	MAIN[4][29][62]
DRP[39] bit 14	MAIN[4][28][63]
DRP[39] bit 15	MAIN[4][29][63]
DRP[40] bit 0	MAIN[5][28][0]
DRP[40] bit 1	MAIN[5][29][0]
DRP[40] bit 2	MAIN[5][28][1]
DRP[40] bit 3	MAIN[5][29][1]
DRP[40] bit 4	MAIN[5][28][2]
DRP[40] bit 5	MAIN[5][29][2]
DRP[40] bit 6	MAIN[5][28][3]
DRP[40] bit 7	MAIN[5][29][3]
DRP[40] bit 8	MAIN[5][28][4]
DRP[40] bit 9	MAIN[5][29][4]
DRP[40] bit 10	MAIN[5][28][5]
DRP[40] bit 11	MAIN[5][29][5]
DRP[40] bit 12	MAIN[5][28][6]
DRP[40] bit 13	MAIN[5][29][6]
DRP[40] bit 14	MAIN[5][28][7]
DRP[40] bit 15	MAIN[5][29][7]
DRP[41] bit 0	MAIN[5][28][8]
DRP[41] bit 1	MAIN[5][29][8]
DRP[41] bit 2	MAIN[5][28][9]
DRP[41] bit 3	MAIN[5][29][9]
DRP[41] bit 4	MAIN[5][28][10]
DRP[41] bit 5	MAIN[5][29][10]
DRP[41] bit 6	MAIN[5][28][11]
DRP[41] bit 7	MAIN[5][29][11]
DRP[41] bit 8	MAIN[5][28][12]
DRP[41] bit 9	MAIN[5][29][12]
DRP[41] bit 10	MAIN[5][28][13]
DRP[41] bit 11	MAIN[5][29][13]
DRP[41] bit 12	MAIN[5][28][14]
DRP[41] bit 13	MAIN[5][29][14]
DRP[41] bit 14	MAIN[5][28][15]
DRP[41] bit 15	MAIN[5][29][15]
DRP[42] bit 0	MAIN[5][28][16]
DRP[42] bit 1	MAIN[5][29][16]
DRP[42] bit 2	MAIN[5][28][17]
DRP[42] bit 3	MAIN[5][29][17]
DRP[42] bit 4	MAIN[5][28][18]
DRP[42] bit 5	MAIN[5][29][18]
DRP[42] bit 6	MAIN[5][28][19]
DRP[42] bit 7	MAIN[5][29][19]
DRP[42] bit 8	MAIN[5][28][20]
DRP[42] bit 9	MAIN[5][29][20]
DRP[42] bit 10	MAIN[5][28][21]
DRP[42] bit 11	MAIN[5][29][21]
DRP[42] bit 12	MAIN[5][28][22]
DRP[42] bit 13	MAIN[5][29][22]
DRP[42] bit 14	MAIN[5][28][23]
DRP[42] bit 15	MAIN[5][29][23]
DRP[43] bit 0	MAIN[5][28][24]
DRP[43] bit 1	MAIN[5][29][24]
DRP[43] bit 2	MAIN[5][28][25]
DRP[43] bit 3	MAIN[5][29][25]
DRP[43] bit 4	MAIN[5][28][26]
DRP[43] bit 5	MAIN[5][29][26]
DRP[43] bit 6	MAIN[5][28][27]
DRP[43] bit 7	MAIN[5][29][27]
DRP[43] bit 8	MAIN[5][28][28]
DRP[43] bit 9	MAIN[5][29][28]
DRP[43] bit 10	MAIN[5][28][29]
DRP[43] bit 11	MAIN[5][29][29]
DRP[43] bit 12	MAIN[5][28][30]
DRP[43] bit 13	MAIN[5][29][30]
DRP[43] bit 14	MAIN[5][28][31]
DRP[43] bit 15	MAIN[5][29][31]
DRP[44] bit 0	MAIN[5][28][32]
DRP[44] bit 1	MAIN[5][29][32]
DRP[44] bit 2	MAIN[5][28][33]
DRP[44] bit 3	MAIN[5][29][33]
DRP[44] bit 4	MAIN[5][28][34]
DRP[44] bit 5	MAIN[5][29][34]
DRP[44] bit 6	MAIN[5][28][35]
DRP[44] bit 7	MAIN[5][29][35]
DRP[44] bit 8	MAIN[5][28][36]
DRP[44] bit 9	MAIN[5][29][36]
DRP[44] bit 10	MAIN[5][28][37]
DRP[44] bit 11	MAIN[5][29][37]
DRP[44] bit 12	MAIN[5][28][38]
DRP[44] bit 13	MAIN[5][29][38]
DRP[44] bit 14	MAIN[5][28][39]
DRP[44] bit 15	MAIN[5][29][39]
DRP[45] bit 0	MAIN[5][28][40]
DRP[45] bit 1	MAIN[5][29][40]
DRP[45] bit 2	MAIN[5][28][41]
DRP[45] bit 3	MAIN[5][29][41]
DRP[45] bit 4	MAIN[5][28][42]
DRP[45] bit 5	MAIN[5][29][42]
DRP[45] bit 6	MAIN[5][28][43]
DRP[45] bit 7	MAIN[5][29][43]
DRP[45] bit 8	MAIN[5][28][44]
DRP[45] bit 9	MAIN[5][29][44]
DRP[45] bit 10	MAIN[5][28][45]
DRP[45] bit 11	MAIN[5][29][45]
DRP[45] bit 12	MAIN[5][28][46]
DRP[45] bit 13	MAIN[5][29][46]
DRP[45] bit 14	MAIN[5][28][47]
DRP[45] bit 15	MAIN[5][29][47]
DRP[46] bit 0	MAIN[5][28][48]
DRP[46] bit 1	MAIN[5][29][48]
DRP[46] bit 2	MAIN[5][28][49]
DRP[46] bit 3	MAIN[5][29][49]
DRP[46] bit 4	MAIN[5][28][50]
DRP[46] bit 5	MAIN[5][29][50]
DRP[46] bit 6	MAIN[5][28][51]
DRP[46] bit 7	MAIN[5][29][51]
DRP[46] bit 8	MAIN[5][28][52]
DRP[46] bit 9	MAIN[5][29][52]
DRP[46] bit 10	MAIN[5][28][53]
DRP[46] bit 11	MAIN[5][29][53]
DRP[46] bit 12	MAIN[5][28][54]
DRP[46] bit 13	MAIN[5][29][54]
DRP[46] bit 14	MAIN[5][28][55]
DRP[46] bit 15	MAIN[5][29][55]
DRP[47] bit 0	MAIN[5][28][56]
DRP[47] bit 1	MAIN[5][29][56]
DRP[47] bit 2	MAIN[5][28][57]
DRP[47] bit 3	MAIN[5][29][57]
DRP[47] bit 4	MAIN[5][28][58]
DRP[47] bit 5	MAIN[5][29][58]
DRP[47] bit 6	MAIN[5][28][59]
DRP[47] bit 7	MAIN[5][29][59]
DRP[47] bit 8	MAIN[5][28][60]
DRP[47] bit 9	MAIN[5][29][60]
DRP[47] bit 10	MAIN[5][28][61]
DRP[47] bit 11	MAIN[5][29][61]
DRP[47] bit 12	MAIN[5][28][62]
DRP[47] bit 13	MAIN[5][29][62]
DRP[47] bit 14	MAIN[5][28][63]
DRP[47] bit 15	MAIN[5][29][63]
DRP[48] bit 0	MAIN[6][28][0]
DRP[48] bit 1	MAIN[6][29][0]
DRP[48] bit 2	MAIN[6][28][1]
DRP[48] bit 3	MAIN[6][29][1]
DRP[48] bit 4	MAIN[6][28][2]
DRP[48] bit 5	MAIN[6][29][2]
DRP[48] bit 6	MAIN[6][28][3]
DRP[48] bit 7	MAIN[6][29][3]
DRP[48] bit 8	MAIN[6][28][4]
DRP[48] bit 9	MAIN[6][29][4]
DRP[48] bit 10	MAIN[6][28][5]
DRP[48] bit 11	MAIN[6][29][5]
DRP[48] bit 12	MAIN[6][28][6]
DRP[48] bit 13	MAIN[6][29][6]
DRP[48] bit 14	MAIN[6][28][7]
DRP[48] bit 15	MAIN[6][29][7]
DRP[49] bit 0	MAIN[6][28][8]
DRP[49] bit 1	MAIN[6][29][8]
DRP[49] bit 2	MAIN[6][28][9]
DRP[49] bit 3	MAIN[6][29][9]
DRP[49] bit 4	MAIN[6][28][10]
DRP[49] bit 5	MAIN[6][29][10]
DRP[49] bit 6	MAIN[6][28][11]
DRP[49] bit 7	MAIN[6][29][11]
DRP[49] bit 8	MAIN[6][28][12]
DRP[49] bit 9	MAIN[6][29][12]
DRP[49] bit 10	MAIN[6][28][13]
DRP[49] bit 11	MAIN[6][29][13]
DRP[49] bit 12	MAIN[6][28][14]
DRP[49] bit 13	MAIN[6][29][14]
DRP[49] bit 14	MAIN[6][28][15]
DRP[49] bit 15	MAIN[6][29][15]
DRP[50] bit 0	MAIN[6][28][16]
DRP[50] bit 1	MAIN[6][29][16]
DRP[50] bit 2	MAIN[6][28][17]
DRP[50] bit 3	MAIN[6][29][17]
DRP[50] bit 4	MAIN[6][28][18]
DRP[50] bit 5	MAIN[6][29][18]
DRP[50] bit 6	MAIN[6][28][19]
DRP[50] bit 7	MAIN[6][29][19]
DRP[50] bit 8	MAIN[6][28][20]
DRP[50] bit 9	MAIN[6][29][20]
DRP[50] bit 10	MAIN[6][28][21]
DRP[50] bit 11	MAIN[6][29][21]
DRP[50] bit 12	MAIN[6][28][22]
DRP[50] bit 13	MAIN[6][29][22]
DRP[50] bit 14	MAIN[6][28][23]
DRP[50] bit 15	MAIN[6][29][23]
DRP[51] bit 0	MAIN[6][28][24]
DRP[51] bit 1	MAIN[6][29][24]
DRP[51] bit 2	MAIN[6][28][25]
DRP[51] bit 3	MAIN[6][29][25]
DRP[51] bit 4	MAIN[6][28][26]
DRP[51] bit 5	MAIN[6][29][26]
DRP[51] bit 6	MAIN[6][28][27]
DRP[51] bit 7	MAIN[6][29][27]
DRP[51] bit 8	MAIN[6][28][28]
DRP[51] bit 9	MAIN[6][29][28]
DRP[51] bit 10	MAIN[6][28][29]
DRP[51] bit 11	MAIN[6][29][29]
DRP[51] bit 12	MAIN[6][28][30]
DRP[51] bit 13	MAIN[6][29][30]
DRP[51] bit 14	MAIN[6][28][31]
DRP[51] bit 15	MAIN[6][29][31]
DRP[52] bit 0	MAIN[6][28][32]
DRP[52] bit 1	MAIN[6][29][32]
DRP[52] bit 2	MAIN[6][28][33]
DRP[52] bit 3	MAIN[6][29][33]
DRP[52] bit 4	MAIN[6][28][34]
DRP[52] bit 5	MAIN[6][29][34]
DRP[52] bit 6	MAIN[6][28][35]
DRP[52] bit 7	MAIN[6][29][35]
DRP[52] bit 8	MAIN[6][28][36]
DRP[52] bit 9	MAIN[6][29][36]
DRP[52] bit 10	MAIN[6][28][37]
DRP[52] bit 11	MAIN[6][29][37]
DRP[52] bit 12	MAIN[6][28][38]
DRP[52] bit 13	MAIN[6][29][38]
DRP[52] bit 14	MAIN[6][28][39]
DRP[52] bit 15	MAIN[6][29][39]
DRP[53] bit 0	MAIN[6][28][40]
DRP[53] bit 1	MAIN[6][29][40]
DRP[53] bit 2	MAIN[6][28][41]
DRP[53] bit 3	MAIN[6][29][41]
DRP[53] bit 4	MAIN[6][28][42]
DRP[53] bit 5	MAIN[6][29][42]
DRP[53] bit 6	MAIN[6][28][43]
DRP[53] bit 7	MAIN[6][29][43]
DRP[53] bit 8	MAIN[6][28][44]
DRP[53] bit 9	MAIN[6][29][44]
DRP[53] bit 10	MAIN[6][28][45]
DRP[53] bit 11	MAIN[6][29][45]
DRP[53] bit 12	MAIN[6][28][46]
DRP[53] bit 13	MAIN[6][29][46]
DRP[53] bit 14	MAIN[6][28][47]
DRP[53] bit 15	MAIN[6][29][47]
DRP[54] bit 0	MAIN[6][28][48]
DRP[54] bit 1	MAIN[6][29][48]
DRP[54] bit 2	MAIN[6][28][49]
DRP[54] bit 3	MAIN[6][29][49]
DRP[54] bit 4	MAIN[6][28][50]
DRP[54] bit 5	MAIN[6][29][50]
DRP[54] bit 6	MAIN[6][28][51]
DRP[54] bit 7	MAIN[6][29][51]
DRP[54] bit 8	MAIN[6][28][52]
DRP[54] bit 9	MAIN[6][29][52]
DRP[54] bit 10	MAIN[6][28][53]
DRP[54] bit 11	MAIN[6][29][53]
DRP[54] bit 12	MAIN[6][28][54]
DRP[54] bit 13	MAIN[6][29][54]
DRP[54] bit 14	MAIN[6][28][55]
DRP[54] bit 15	MAIN[6][29][55]
DRP[55] bit 0	MAIN[6][28][56]
DRP[55] bit 1	MAIN[6][29][56]
DRP[55] bit 2	MAIN[6][28][57]
DRP[55] bit 3	MAIN[6][29][57]
DRP[55] bit 4	MAIN[6][28][58]
DRP[55] bit 5	MAIN[6][29][58]
DRP[55] bit 6	MAIN[6][28][59]
DRP[55] bit 7	MAIN[6][29][59]
DRP[55] bit 8	MAIN[6][28][60]
DRP[55] bit 9	MAIN[6][29][60]
DRP[55] bit 10	MAIN[6][28][61]
DRP[55] bit 11	MAIN[6][29][61]
DRP[55] bit 12	MAIN[6][28][62]
DRP[55] bit 13	MAIN[6][29][62]
DRP[55] bit 14	MAIN[6][28][63]
DRP[55] bit 15	MAIN[6][29][63]
DRP[56] bit 0	MAIN[7][28][0]
DRP[56] bit 1	MAIN[7][29][0]
DRP[56] bit 2	MAIN[7][28][1]
DRP[56] bit 3	MAIN[7][29][1]
DRP[56] bit 4	MAIN[7][28][2]
DRP[56] bit 5	MAIN[7][29][2]
DRP[56] bit 6	MAIN[7][28][3]
DRP[56] bit 7	MAIN[7][29][3]
DRP[56] bit 8	MAIN[7][28][4]
DRP[56] bit 9	MAIN[7][29][4]
DRP[56] bit 10	MAIN[7][28][5]
DRP[56] bit 11	MAIN[7][29][5]
DRP[56] bit 12	MAIN[7][28][6]
DRP[56] bit 13	MAIN[7][29][6]
DRP[56] bit 14	MAIN[7][28][7]
DRP[56] bit 15	MAIN[7][29][7]
DRP[57] bit 0	MAIN[7][28][8]
DRP[57] bit 1	MAIN[7][29][8]
DRP[57] bit 2	MAIN[7][28][9]
DRP[57] bit 3	MAIN[7][29][9]
DRP[57] bit 4	MAIN[7][28][10]
DRP[57] bit 5	MAIN[7][29][10]
DRP[57] bit 6	MAIN[7][28][11]
DRP[57] bit 7	MAIN[7][29][11]
DRP[57] bit 8	MAIN[7][28][12]
DRP[57] bit 9	MAIN[7][29][12]
DRP[57] bit 10	MAIN[7][28][13]
DRP[57] bit 11	MAIN[7][29][13]
DRP[57] bit 12	MAIN[7][28][14]
DRP[57] bit 13	MAIN[7][29][14]
DRP[57] bit 14	MAIN[7][28][15]
DRP[57] bit 15	MAIN[7][29][15]
DRP[58] bit 0	MAIN[7][28][16]
DRP[58] bit 1	MAIN[7][29][16]
DRP[58] bit 2	MAIN[7][28][17]
DRP[58] bit 3	MAIN[7][29][17]
DRP[58] bit 4	MAIN[7][28][18]
DRP[58] bit 5	MAIN[7][29][18]
DRP[58] bit 6	MAIN[7][28][19]
DRP[58] bit 7	MAIN[7][29][19]
DRP[58] bit 8	MAIN[7][28][20]
DRP[58] bit 9	MAIN[7][29][20]
DRP[58] bit 10	MAIN[7][28][21]
DRP[58] bit 11	MAIN[7][29][21]
DRP[58] bit 12	MAIN[7][28][22]
DRP[58] bit 13	MAIN[7][29][22]
DRP[58] bit 14	MAIN[7][28][23]
DRP[58] bit 15	MAIN[7][29][23]
DRP[59] bit 0	MAIN[7][28][24]
DRP[59] bit 1	MAIN[7][29][24]
DRP[59] bit 2	MAIN[7][28][25]
DRP[59] bit 3	MAIN[7][29][25]
DRP[59] bit 4	MAIN[7][28][26]
DRP[59] bit 5	MAIN[7][29][26]
DRP[59] bit 6	MAIN[7][28][27]
DRP[59] bit 7	MAIN[7][29][27]
DRP[59] bit 8	MAIN[7][28][28]
DRP[59] bit 9	MAIN[7][29][28]
DRP[59] bit 10	MAIN[7][28][29]
DRP[59] bit 11	MAIN[7][29][29]
DRP[59] bit 12	MAIN[7][28][30]
DRP[59] bit 13	MAIN[7][29][30]
DRP[59] bit 14	MAIN[7][28][31]
DRP[59] bit 15	MAIN[7][29][31]
DRP[60] bit 0	MAIN[7][28][32]
DRP[60] bit 1	MAIN[7][29][32]
DRP[60] bit 2	MAIN[7][28][33]
DRP[60] bit 3	MAIN[7][29][33]
DRP[60] bit 4	MAIN[7][28][34]
DRP[60] bit 5	MAIN[7][29][34]
DRP[60] bit 6	MAIN[7][28][35]
DRP[60] bit 7	MAIN[7][29][35]
DRP[60] bit 8	MAIN[7][28][36]
DRP[60] bit 9	MAIN[7][29][36]
DRP[60] bit 10	MAIN[7][28][37]
DRP[60] bit 11	MAIN[7][29][37]
DRP[60] bit 12	MAIN[7][28][38]
DRP[60] bit 13	MAIN[7][29][38]
DRP[60] bit 14	MAIN[7][28][39]
DRP[60] bit 15	MAIN[7][29][39]
DRP[61] bit 0	MAIN[7][28][40]
DRP[61] bit 1	MAIN[7][29][40]
DRP[61] bit 2	MAIN[7][28][41]
DRP[61] bit 3	MAIN[7][29][41]
DRP[61] bit 4	MAIN[7][28][42]
DRP[61] bit 5	MAIN[7][29][42]
DRP[61] bit 6	MAIN[7][28][43]
DRP[61] bit 7	MAIN[7][29][43]
DRP[61] bit 8	MAIN[7][28][44]
DRP[61] bit 9	MAIN[7][29][44]
DRP[61] bit 10	MAIN[7][28][45]
DRP[61] bit 11	MAIN[7][29][45]
DRP[61] bit 12	MAIN[7][28][46]
DRP[61] bit 13	MAIN[7][29][46]
DRP[61] bit 14	MAIN[7][28][47]
DRP[61] bit 15	MAIN[7][29][47]
DRP[62] bit 0	MAIN[7][28][48]
DRP[62] bit 1	MAIN[7][29][48]
DRP[62] bit 2	MAIN[7][28][49]
DRP[62] bit 3	MAIN[7][29][49]
DRP[62] bit 4	MAIN[7][28][50]
DRP[62] bit 5	MAIN[7][29][50]
DRP[62] bit 6	MAIN[7][28][51]
DRP[62] bit 7	MAIN[7][29][51]
DRP[62] bit 8	MAIN[7][28][52]
DRP[62] bit 9	MAIN[7][29][52]
DRP[62] bit 10	MAIN[7][28][53]
DRP[62] bit 11	MAIN[7][29][53]
DRP[62] bit 12	MAIN[7][28][54]
DRP[62] bit 13	MAIN[7][29][54]
DRP[62] bit 14	MAIN[7][28][55]
DRP[62] bit 15	MAIN[7][29][55]
DRP[63] bit 0	MAIN[7][28][56]
DRP[63] bit 1	MAIN[7][29][56]
DRP[63] bit 2	MAIN[7][28][57]
DRP[63] bit 3	MAIN[7][29][57]
DRP[63] bit 4	MAIN[7][28][58]
DRP[63] bit 5	MAIN[7][29][58]
DRP[63] bit 6	MAIN[7][28][59]
DRP[63] bit 7	MAIN[7][29][59]
DRP[63] bit 8	MAIN[7][28][60]
DRP[63] bit 9	MAIN[7][29][60]
DRP[63] bit 10	MAIN[7][28][61]
DRP[63] bit 11	MAIN[7][29][61]
DRP[63] bit 12	MAIN[7][28][62]
DRP[63] bit 13	MAIN[7][29][62]
DRP[63] bit 14	MAIN[7][28][63]
DRP[63] bit 15	MAIN[7][29][63]
DRP[64] bit 0	MAIN[8][28][0]
DRP[64] bit 1	MAIN[8][29][0]
DRP[64] bit 2	MAIN[8][28][1]
DRP[64] bit 3	MAIN[8][29][1]
DRP[64] bit 4	MAIN[8][28][2]
DRP[64] bit 5	MAIN[8][29][2]
DRP[64] bit 6	MAIN[8][28][3]
DRP[64] bit 7	MAIN[8][29][3]
DRP[64] bit 8	MAIN[8][28][4]
DRP[64] bit 9	MAIN[8][29][4]
DRP[64] bit 10	MAIN[8][28][5]
DRP[64] bit 11	MAIN[8][29][5]
DRP[64] bit 12	MAIN[8][28][6]
DRP[64] bit 13	MAIN[8][29][6]
DRP[64] bit 14	MAIN[8][28][7]
DRP[64] bit 15	MAIN[8][29][7]
DRP[65] bit 0	MAIN[8][28][8]
DRP[65] bit 1	MAIN[8][29][8]
DRP[65] bit 2	MAIN[8][28][9]
DRP[65] bit 3	MAIN[8][29][9]
DRP[65] bit 4	MAIN[8][28][10]
DRP[65] bit 5	MAIN[8][29][10]
DRP[65] bit 6	MAIN[8][28][11]
DRP[65] bit 7	MAIN[8][29][11]
DRP[65] bit 8	MAIN[8][28][12]
DRP[65] bit 9	MAIN[8][29][12]
DRP[65] bit 10	MAIN[8][28][13]
DRP[65] bit 11	MAIN[8][29][13]
DRP[65] bit 12	MAIN[8][28][14]
DRP[65] bit 13	MAIN[8][29][14]
DRP[65] bit 14	MAIN[8][28][15]
DRP[65] bit 15	MAIN[8][29][15]
DRP[66] bit 0	MAIN[8][28][16]
DRP[66] bit 1	MAIN[8][29][16]
DRP[66] bit 2	MAIN[8][28][17]
DRP[66] bit 3	MAIN[8][29][17]
DRP[66] bit 4	MAIN[8][28][18]
DRP[66] bit 5	MAIN[8][29][18]
DRP[66] bit 6	MAIN[8][28][19]
DRP[66] bit 7	MAIN[8][29][19]
DRP[66] bit 8	MAIN[8][28][20]
DRP[66] bit 9	MAIN[8][29][20]
DRP[66] bit 10	MAIN[8][28][21]
DRP[66] bit 11	MAIN[8][29][21]
DRP[66] bit 12	MAIN[8][28][22]
DRP[66] bit 13	MAIN[8][29][22]
DRP[66] bit 14	MAIN[8][28][23]
DRP[66] bit 15	MAIN[8][29][23]
DRP[67] bit 0	MAIN[8][28][24]
DRP[67] bit 1	MAIN[8][29][24]
DRP[67] bit 2	MAIN[8][28][25]
DRP[67] bit 3	MAIN[8][29][25]
DRP[67] bit 4	MAIN[8][28][26]
DRP[67] bit 5	MAIN[8][29][26]
DRP[67] bit 6	MAIN[8][28][27]
DRP[67] bit 7	MAIN[8][29][27]
DRP[67] bit 8	MAIN[8][28][28]
DRP[67] bit 9	MAIN[8][29][28]
DRP[67] bit 10	MAIN[8][28][29]
DRP[67] bit 11	MAIN[8][29][29]
DRP[67] bit 12	MAIN[8][28][30]
DRP[67] bit 13	MAIN[8][29][30]
DRP[67] bit 14	MAIN[8][28][31]
DRP[67] bit 15	MAIN[8][29][31]
DRP[68] bit 0	MAIN[8][28][32]
DRP[68] bit 1	MAIN[8][29][32]
DRP[68] bit 2	MAIN[8][28][33]
DRP[68] bit 3	MAIN[8][29][33]
DRP[68] bit 4	MAIN[8][28][34]
DRP[68] bit 5	MAIN[8][29][34]
DRP[68] bit 6	MAIN[8][28][35]
DRP[68] bit 7	MAIN[8][29][35]
DRP[68] bit 8	MAIN[8][28][36]
DRP[68] bit 9	MAIN[8][29][36]
DRP[68] bit 10	MAIN[8][28][37]
DRP[68] bit 11	MAIN[8][29][37]
DRP[68] bit 12	MAIN[8][28][38]
DRP[68] bit 13	MAIN[8][29][38]
DRP[68] bit 14	MAIN[8][28][39]
DRP[68] bit 15	MAIN[8][29][39]
DRP[69] bit 0	MAIN[8][28][40]
DRP[69] bit 1	MAIN[8][29][40]
DRP[69] bit 2	MAIN[8][28][41]
DRP[69] bit 3	MAIN[8][29][41]
DRP[69] bit 4	MAIN[8][28][42]
DRP[69] bit 5	MAIN[8][29][42]
DRP[69] bit 6	MAIN[8][28][43]
DRP[69] bit 7	MAIN[8][29][43]
DRP[69] bit 8	MAIN[8][28][44]
DRP[69] bit 9	MAIN[8][29][44]
DRP[69] bit 10	MAIN[8][28][45]
DRP[69] bit 11	MAIN[8][29][45]
DRP[69] bit 12	MAIN[8][28][46]
DRP[69] bit 13	MAIN[8][29][46]
DRP[69] bit 14	MAIN[8][28][47]
DRP[69] bit 15	MAIN[8][29][47]
DRP[70] bit 0	MAIN[8][28][48]
DRP[70] bit 1	MAIN[8][29][48]
DRP[70] bit 2	MAIN[8][28][49]
DRP[70] bit 3	MAIN[8][29][49]
DRP[70] bit 4	MAIN[8][28][50]
DRP[70] bit 5	MAIN[8][29][50]
DRP[70] bit 6	MAIN[8][28][51]
DRP[70] bit 7	MAIN[8][29][51]
DRP[70] bit 8	MAIN[8][28][52]
DRP[70] bit 9	MAIN[8][29][52]
DRP[70] bit 10	MAIN[8][28][53]
DRP[70] bit 11	MAIN[8][29][53]
DRP[70] bit 12	MAIN[8][28][54]
DRP[70] bit 13	MAIN[8][29][54]
DRP[70] bit 14	MAIN[8][28][55]
DRP[70] bit 15	MAIN[8][29][55]
DRP[71] bit 0	MAIN[8][28][56]
DRP[71] bit 1	MAIN[8][29][56]
DRP[71] bit 2	MAIN[8][28][57]
DRP[71] bit 3	MAIN[8][29][57]
DRP[71] bit 4	MAIN[8][28][58]
DRP[71] bit 5	MAIN[8][29][58]
DRP[71] bit 6	MAIN[8][28][59]
DRP[71] bit 7	MAIN[8][29][59]
DRP[71] bit 8	MAIN[8][28][60]
DRP[71] bit 9	MAIN[8][29][60]
DRP[71] bit 10	MAIN[8][28][61]
DRP[71] bit 11	MAIN[8][29][61]
DRP[71] bit 12	MAIN[8][28][62]
DRP[71] bit 13	MAIN[8][29][62]
DRP[71] bit 14	MAIN[8][28][63]
DRP[71] bit 15	MAIN[8][29][63]
DRP[72] bit 0	MAIN[9][28][0]
DRP[72] bit 1	MAIN[9][29][0]
DRP[72] bit 2	MAIN[9][28][1]
DRP[72] bit 3	MAIN[9][29][1]
DRP[72] bit 4	MAIN[9][28][2]
DRP[72] bit 5	MAIN[9][29][2]
DRP[72] bit 6	MAIN[9][28][3]
DRP[72] bit 7	MAIN[9][29][3]
DRP[72] bit 8	MAIN[9][28][4]
DRP[72] bit 9	MAIN[9][29][4]
DRP[72] bit 10	MAIN[9][28][5]
DRP[72] bit 11	MAIN[9][29][5]
DRP[72] bit 12	MAIN[9][28][6]
DRP[72] bit 13	MAIN[9][29][6]
DRP[72] bit 14	MAIN[9][28][7]
DRP[72] bit 15	MAIN[9][29][7]
DRP[73] bit 0	MAIN[9][28][8]
DRP[73] bit 1	MAIN[9][29][8]
DRP[73] bit 2	MAIN[9][28][9]
DRP[73] bit 3	MAIN[9][29][9]
DRP[73] bit 4	MAIN[9][28][10]
DRP[73] bit 5	MAIN[9][29][10]
DRP[73] bit 6	MAIN[9][28][11]
DRP[73] bit 7	MAIN[9][29][11]
DRP[73] bit 8	MAIN[9][28][12]
DRP[73] bit 9	MAIN[9][29][12]
DRP[73] bit 10	MAIN[9][28][13]
DRP[73] bit 11	MAIN[9][29][13]
DRP[73] bit 12	MAIN[9][28][14]
DRP[73] bit 13	MAIN[9][29][14]
DRP[73] bit 14	MAIN[9][28][15]
DRP[73] bit 15	MAIN[9][29][15]
DRP[74] bit 0	MAIN[9][28][16]
DRP[74] bit 1	MAIN[9][29][16]
DRP[74] bit 2	MAIN[9][28][17]
DRP[74] bit 3	MAIN[9][29][17]
DRP[74] bit 4	MAIN[9][28][18]
DRP[74] bit 5	MAIN[9][29][18]
DRP[74] bit 6	MAIN[9][28][19]
DRP[74] bit 7	MAIN[9][29][19]
DRP[74] bit 8	MAIN[9][28][20]
DRP[74] bit 9	MAIN[9][29][20]
DRP[74] bit 10	MAIN[9][28][21]
DRP[74] bit 11	MAIN[9][29][21]
DRP[74] bit 12	MAIN[9][28][22]
DRP[74] bit 13	MAIN[9][29][22]
DRP[74] bit 14	MAIN[9][28][23]
DRP[74] bit 15	MAIN[9][29][23]
DRP[75] bit 0	MAIN[9][28][24]
DRP[75] bit 1	MAIN[9][29][24]
DRP[75] bit 2	MAIN[9][28][25]
DRP[75] bit 3	MAIN[9][29][25]
DRP[75] bit 4	MAIN[9][28][26]
DRP[75] bit 5	MAIN[9][29][26]
DRP[75] bit 6	MAIN[9][28][27]
DRP[75] bit 7	MAIN[9][29][27]
DRP[75] bit 8	MAIN[9][28][28]
DRP[75] bit 9	MAIN[9][29][28]
DRP[75] bit 10	MAIN[9][28][29]
DRP[75] bit 11	MAIN[9][29][29]
DRP[75] bit 12	MAIN[9][28][30]
DRP[75] bit 13	MAIN[9][29][30]
DRP[75] bit 14	MAIN[9][28][31]
DRP[75] bit 15	MAIN[9][29][31]
DRP[76] bit 0	MAIN[9][28][32]
DRP[76] bit 1	MAIN[9][29][32]
DRP[76] bit 2	MAIN[9][28][33]
DRP[76] bit 3	MAIN[9][29][33]
DRP[76] bit 4	MAIN[9][28][34]
DRP[76] bit 5	MAIN[9][29][34]
DRP[76] bit 6	MAIN[9][28][35]
DRP[76] bit 7	MAIN[9][29][35]
DRP[76] bit 8	MAIN[9][28][36]
DRP[76] bit 9	MAIN[9][29][36]
DRP[76] bit 10	MAIN[9][28][37]
DRP[76] bit 11	MAIN[9][29][37]
DRP[76] bit 12	MAIN[9][28][38]
DRP[76] bit 13	MAIN[9][29][38]
DRP[76] bit 14	MAIN[9][28][39]
DRP[76] bit 15	MAIN[9][29][39]
DRP[77] bit 0	MAIN[9][28][40]
DRP[77] bit 1	MAIN[9][29][40]
DRP[77] bit 2	MAIN[9][28][41]
DRP[77] bit 3	MAIN[9][29][41]
DRP[77] bit 4	MAIN[9][28][42]
DRP[77] bit 5	MAIN[9][29][42]
DRP[77] bit 6	MAIN[9][28][43]
DRP[77] bit 7	MAIN[9][29][43]
DRP[77] bit 8	MAIN[9][28][44]
DRP[77] bit 9	MAIN[9][29][44]
DRP[77] bit 10	MAIN[9][28][45]
DRP[77] bit 11	MAIN[9][29][45]
DRP[77] bit 12	MAIN[9][28][46]
DRP[77] bit 13	MAIN[9][29][46]
DRP[77] bit 14	MAIN[9][28][47]
DRP[77] bit 15	MAIN[9][29][47]
DRP[78] bit 0	MAIN[9][28][48]
DRP[78] bit 1	MAIN[9][29][48]
DRP[78] bit 2	MAIN[9][28][49]
DRP[78] bit 3	MAIN[9][29][49]
DRP[78] bit 4	MAIN[9][28][50]
DRP[78] bit 5	MAIN[9][29][50]
DRP[78] bit 6	MAIN[9][28][51]
DRP[78] bit 7	MAIN[9][29][51]
DRP[78] bit 8	MAIN[9][28][52]
DRP[78] bit 9	MAIN[9][29][52]
DRP[78] bit 10	MAIN[9][28][53]
DRP[78] bit 11	MAIN[9][29][53]
DRP[78] bit 12	MAIN[9][28][54]
DRP[78] bit 13	MAIN[9][29][54]
DRP[78] bit 14	MAIN[9][28][55]
DRP[78] bit 15	MAIN[9][29][55]
DRP[79] bit 0	MAIN[9][28][56]
DRP[79] bit 1	MAIN[9][29][56]
DRP[79] bit 2	MAIN[9][28][57]
DRP[79] bit 3	MAIN[9][29][57]
DRP[79] bit 4	MAIN[9][28][58]
DRP[79] bit 5	MAIN[9][29][58]
DRP[79] bit 6	MAIN[9][28][59]
DRP[79] bit 7	MAIN[9][29][59]
DRP[79] bit 8	MAIN[9][28][60]
DRP[79] bit 9	MAIN[9][29][60]
DRP[79] bit 10	MAIN[9][28][61]
DRP[79] bit 11	MAIN[9][29][61]
DRP[79] bit 12	MAIN[9][28][62]
DRP[79] bit 13	MAIN[9][29][62]
DRP[79] bit 14	MAIN[9][28][63]
DRP[79] bit 15	MAIN[9][29][63]
DRP[80] bit 0	MAIN[10][28][0]
DRP[80] bit 1	MAIN[10][29][0]
DRP[80] bit 2	MAIN[10][28][1]
DRP[80] bit 3	MAIN[10][29][1]
DRP[80] bit 4	MAIN[10][28][2]
DRP[80] bit 5	MAIN[10][29][2]
DRP[80] bit 6	MAIN[10][28][3]
DRP[80] bit 7	MAIN[10][29][3]
DRP[80] bit 8	MAIN[10][28][4]
DRP[80] bit 9	MAIN[10][29][4]
DRP[80] bit 10	MAIN[10][28][5]
DRP[80] bit 11	MAIN[10][29][5]
DRP[80] bit 12	MAIN[10][28][6]
DRP[80] bit 13	MAIN[10][29][6]
DRP[80] bit 14	MAIN[10][28][7]
DRP[80] bit 15	MAIN[10][29][7]
DRP[81] bit 0	MAIN[10][28][8]
DRP[81] bit 1	MAIN[10][29][8]
DRP[81] bit 2	MAIN[10][28][9]
DRP[81] bit 3	MAIN[10][29][9]
DRP[81] bit 4	MAIN[10][28][10]
DRP[81] bit 5	MAIN[10][29][10]
DRP[81] bit 6	MAIN[10][28][11]
DRP[81] bit 7	MAIN[10][29][11]
DRP[81] bit 8	MAIN[10][28][12]
DRP[81] bit 9	MAIN[10][29][12]
DRP[81] bit 10	MAIN[10][28][13]
DRP[81] bit 11	MAIN[10][29][13]
DRP[81] bit 12	MAIN[10][28][14]
DRP[81] bit 13	MAIN[10][29][14]
DRP[81] bit 14	MAIN[10][28][15]
DRP[81] bit 15	MAIN[10][29][15]
DRP[82] bit 0	MAIN[10][28][16]
DRP[82] bit 1	MAIN[10][29][16]
DRP[82] bit 2	MAIN[10][28][17]
DRP[82] bit 3	MAIN[10][29][17]
DRP[82] bit 4	MAIN[10][28][18]
DRP[82] bit 5	MAIN[10][29][18]
DRP[82] bit 6	MAIN[10][28][19]
DRP[82] bit 7	MAIN[10][29][19]
DRP[82] bit 8	MAIN[10][28][20]
DRP[82] bit 9	MAIN[10][29][20]
DRP[82] bit 10	MAIN[10][28][21]
DRP[82] bit 11	MAIN[10][29][21]
DRP[82] bit 12	MAIN[10][28][22]
DRP[82] bit 13	MAIN[10][29][22]
DRP[82] bit 14	MAIN[10][28][23]
DRP[82] bit 15	MAIN[10][29][23]
DRP[83] bit 0	MAIN[10][28][24]
DRP[83] bit 1	MAIN[10][29][24]
DRP[83] bit 2	MAIN[10][28][25]
DRP[83] bit 3	MAIN[10][29][25]
DRP[83] bit 4	MAIN[10][28][26]
DRP[83] bit 5	MAIN[10][29][26]
DRP[83] bit 6	MAIN[10][28][27]
DRP[83] bit 7	MAIN[10][29][27]
DRP[83] bit 8	MAIN[10][28][28]
DRP[83] bit 9	MAIN[10][29][28]
DRP[83] bit 10	MAIN[10][28][29]
DRP[83] bit 11	MAIN[10][29][29]
DRP[83] bit 12	MAIN[10][28][30]
DRP[83] bit 13	MAIN[10][29][30]
DRP[83] bit 14	MAIN[10][28][31]
DRP[83] bit 15	MAIN[10][29][31]
DRP[84] bit 0	MAIN[10][28][32]
DRP[84] bit 1	MAIN[10][29][32]
DRP[84] bit 2	MAIN[10][28][33]
DRP[84] bit 3	MAIN[10][29][33]
DRP[84] bit 4	MAIN[10][28][34]
DRP[84] bit 5	MAIN[10][29][34]
DRP[84] bit 6	MAIN[10][28][35]
DRP[84] bit 7	MAIN[10][29][35]
DRP[84] bit 8	MAIN[10][28][36]
DRP[84] bit 9	MAIN[10][29][36]
DRP[84] bit 10	MAIN[10][28][37]
DRP[84] bit 11	MAIN[10][29][37]
DRP[84] bit 12	MAIN[10][28][38]
DRP[84] bit 13	MAIN[10][29][38]
DRP[84] bit 14	MAIN[10][28][39]
DRP[84] bit 15	MAIN[10][29][39]
DRP[85] bit 0	MAIN[10][28][40]
DRP[85] bit 1	MAIN[10][29][40]
DRP[85] bit 2	MAIN[10][28][41]
DRP[85] bit 3	MAIN[10][29][41]
DRP[85] bit 4	MAIN[10][28][42]
DRP[85] bit 5	MAIN[10][29][42]
DRP[85] bit 6	MAIN[10][28][43]
DRP[85] bit 7	MAIN[10][29][43]
DRP[85] bit 8	MAIN[10][28][44]
DRP[85] bit 9	MAIN[10][29][44]
DRP[85] bit 10	MAIN[10][28][45]
DRP[85] bit 11	MAIN[10][29][45]
DRP[85] bit 12	MAIN[10][28][46]
DRP[85] bit 13	MAIN[10][29][46]
DRP[85] bit 14	MAIN[10][28][47]
DRP[85] bit 15	MAIN[10][29][47]
DRP[86] bit 0	MAIN[10][28][48]
DRP[86] bit 1	MAIN[10][29][48]
DRP[86] bit 2	MAIN[10][28][49]
DRP[86] bit 3	MAIN[10][29][49]
DRP[86] bit 4	MAIN[10][28][50]
DRP[86] bit 5	MAIN[10][29][50]
DRP[86] bit 6	MAIN[10][28][51]
DRP[86] bit 7	MAIN[10][29][51]
DRP[86] bit 8	MAIN[10][28][52]
DRP[86] bit 9	MAIN[10][29][52]
DRP[86] bit 10	MAIN[10][28][53]
DRP[86] bit 11	MAIN[10][29][53]
DRP[86] bit 12	MAIN[10][28][54]
DRP[86] bit 13	MAIN[10][29][54]
DRP[86] bit 14	MAIN[10][28][55]
DRP[86] bit 15	MAIN[10][29][55]
DRP[87] bit 0	MAIN[10][28][56]
DRP[87] bit 1	MAIN[10][29][56]
DRP[87] bit 2	MAIN[10][28][57]
DRP[87] bit 3	MAIN[10][29][57]
DRP[87] bit 4	MAIN[10][28][58]
DRP[87] bit 5	MAIN[10][29][58]
DRP[87] bit 6	MAIN[10][28][59]
DRP[87] bit 7	MAIN[10][29][59]
DRP[87] bit 8	MAIN[10][28][60]
DRP[87] bit 9	MAIN[10][29][60]
DRP[87] bit 10	MAIN[10][28][61]
DRP[87] bit 11	MAIN[10][29][61]
DRP[87] bit 12	MAIN[10][28][62]
DRP[87] bit 13	MAIN[10][29][62]
DRP[87] bit 14	MAIN[10][28][63]
DRP[87] bit 15	MAIN[10][29][63]
DRP[88] bit 0	MAIN[0][30][0]
DRP[88] bit 1	MAIN[0][31][0]
DRP[88] bit 2	MAIN[0][30][1]
DRP[88] bit 3	MAIN[0][31][1]
DRP[88] bit 4	MAIN[0][30][2]
DRP[88] bit 5	MAIN[0][31][2]
DRP[88] bit 6	MAIN[0][30][3]
DRP[88] bit 7	MAIN[0][31][3]
DRP[88] bit 8	MAIN[0][30][4]
DRP[88] bit 9	MAIN[0][31][4]
DRP[88] bit 10	MAIN[0][30][5]
DRP[88] bit 11	MAIN[0][31][5]
DRP[88] bit 12	MAIN[0][30][6]
DRP[88] bit 13	MAIN[0][31][6]
DRP[88] bit 14	MAIN[0][30][7]
DRP[88] bit 15	MAIN[0][31][7]
DRP[89] bit 0	MAIN[0][30][8]
DRP[89] bit 1	MAIN[0][31][8]
DRP[89] bit 2	MAIN[0][30][9]
DRP[89] bit 3	MAIN[0][31][9]
DRP[89] bit 4	MAIN[0][30][10]
DRP[89] bit 5	MAIN[0][31][10]
DRP[89] bit 6	MAIN[0][30][11]
DRP[89] bit 7	MAIN[0][31][11]
DRP[89] bit 8	MAIN[0][30][12]
DRP[89] bit 9	MAIN[0][31][12]
DRP[89] bit 10	MAIN[0][30][13]
DRP[89] bit 11	MAIN[0][31][13]
DRP[89] bit 12	MAIN[0][30][14]
DRP[89] bit 13	MAIN[0][31][14]
DRP[89] bit 14	MAIN[0][30][15]
DRP[89] bit 15	MAIN[0][31][15]
DRP[90] bit 0	MAIN[0][30][16]
DRP[90] bit 1	MAIN[0][31][16]
DRP[90] bit 2	MAIN[0][30][17]
DRP[90] bit 3	MAIN[0][31][17]
DRP[90] bit 4	MAIN[0][30][18]
DRP[90] bit 5	MAIN[0][31][18]
DRP[90] bit 6	MAIN[0][30][19]
DRP[90] bit 7	MAIN[0][31][19]
DRP[90] bit 8	MAIN[0][30][20]
DRP[90] bit 9	MAIN[0][31][20]
DRP[90] bit 10	MAIN[0][30][21]
DRP[90] bit 11	MAIN[0][31][21]
DRP[90] bit 12	MAIN[0][30][22]
DRP[90] bit 13	MAIN[0][31][22]
DRP[90] bit 14	MAIN[0][30][23]
DRP[90] bit 15	MAIN[0][31][23]
DRP[91] bit 0	MAIN[0][30][24]
DRP[91] bit 1	MAIN[0][31][24]
DRP[91] bit 2	MAIN[0][30][25]
DRP[91] bit 3	MAIN[0][31][25]
DRP[91] bit 4	MAIN[0][30][26]
DRP[91] bit 5	MAIN[0][31][26]
DRP[91] bit 6	MAIN[0][30][27]
DRP[91] bit 7	MAIN[0][31][27]
DRP[91] bit 8	MAIN[0][30][28]
DRP[91] bit 9	MAIN[0][31][28]
DRP[91] bit 10	MAIN[0][30][29]
DRP[91] bit 11	MAIN[0][31][29]
DRP[91] bit 12	MAIN[0][30][30]
DRP[91] bit 13	MAIN[0][31][30]
DRP[91] bit 14	MAIN[0][30][31]
DRP[91] bit 15	MAIN[0][31][31]
DRP[92] bit 0	MAIN[0][30][32]
DRP[92] bit 1	MAIN[0][31][32]
DRP[92] bit 2	MAIN[0][30][33]
DRP[92] bit 3	MAIN[0][31][33]
DRP[92] bit 4	MAIN[0][30][34]
DRP[92] bit 5	MAIN[0][31][34]
DRP[92] bit 6	MAIN[0][30][35]
DRP[92] bit 7	MAIN[0][31][35]
DRP[92] bit 8	MAIN[0][30][36]
DRP[92] bit 9	MAIN[0][31][36]
DRP[92] bit 10	MAIN[0][30][37]
DRP[92] bit 11	MAIN[0][31][37]
DRP[92] bit 12	MAIN[0][30][38]
DRP[92] bit 13	MAIN[0][31][38]
DRP[92] bit 14	MAIN[0][30][39]
DRP[92] bit 15	MAIN[0][31][39]
DRP[93] bit 0	MAIN[0][30][40]
DRP[93] bit 1	MAIN[0][31][40]
DRP[93] bit 2	MAIN[0][30][41]
DRP[93] bit 3	MAIN[0][31][41]
DRP[93] bit 4	MAIN[0][30][42]
DRP[93] bit 5	MAIN[0][31][42]
DRP[93] bit 6	MAIN[0][30][43]
DRP[93] bit 7	MAIN[0][31][43]
DRP[93] bit 8	MAIN[0][30][44]
DRP[93] bit 9	MAIN[0][31][44]
DRP[93] bit 10	MAIN[0][30][45]
DRP[93] bit 11	MAIN[0][31][45]
DRP[93] bit 12	MAIN[0][30][46]
DRP[93] bit 13	MAIN[0][31][46]
DRP[93] bit 14	MAIN[0][30][47]
DRP[93] bit 15	MAIN[0][31][47]
DRP[94] bit 0	MAIN[0][30][48]
DRP[94] bit 1	MAIN[0][31][48]
DRP[94] bit 2	MAIN[0][30][49]
DRP[94] bit 3	MAIN[0][31][49]
DRP[94] bit 4	MAIN[0][30][50]
DRP[94] bit 5	MAIN[0][31][50]
DRP[94] bit 6	MAIN[0][30][51]
DRP[94] bit 7	MAIN[0][31][51]
DRP[94] bit 8	MAIN[0][30][52]
DRP[94] bit 9	MAIN[0][31][52]
DRP[94] bit 10	MAIN[0][30][53]
DRP[94] bit 11	MAIN[0][31][53]
DRP[94] bit 12	MAIN[0][30][54]
DRP[94] bit 13	MAIN[0][31][54]
DRP[94] bit 14	MAIN[0][30][55]
DRP[94] bit 15	MAIN[0][31][55]
DRP[95] bit 0	MAIN[0][30][56]
DRP[95] bit 1	MAIN[0][31][56]
DRP[95] bit 2	MAIN[0][30][57]
DRP[95] bit 3	MAIN[0][31][57]
DRP[95] bit 4	MAIN[0][30][58]
DRP[95] bit 5	MAIN[0][31][58]
DRP[95] bit 6	MAIN[0][30][59]
DRP[95] bit 7	MAIN[0][31][59]
DRP[95] bit 8	MAIN[0][30][60]
DRP[95] bit 9	MAIN[0][31][60]
DRP[95] bit 10	MAIN[0][30][61]
DRP[95] bit 11	MAIN[0][31][61]
DRP[95] bit 12	MAIN[0][30][62]
DRP[95] bit 13	MAIN[0][31][62]
DRP[95] bit 14	MAIN[0][30][63]
DRP[95] bit 15	MAIN[0][31][63]
DRP[96] bit 0	MAIN[1][30][0]
DRP[96] bit 1	MAIN[1][31][0]
DRP[96] bit 2	MAIN[1][30][1]
DRP[96] bit 3	MAIN[1][31][1]
DRP[96] bit 4	MAIN[1][30][2]
DRP[96] bit 5	MAIN[1][31][2]
DRP[96] bit 6	MAIN[1][30][3]
DRP[96] bit 7	MAIN[1][31][3]
DRP[96] bit 8	MAIN[1][30][4]
DRP[96] bit 9	MAIN[1][31][4]
DRP[96] bit 10	MAIN[1][30][5]
DRP[96] bit 11	MAIN[1][31][5]
DRP[96] bit 12	MAIN[1][30][6]
DRP[96] bit 13	MAIN[1][31][6]
DRP[96] bit 14	MAIN[1][30][7]
DRP[96] bit 15	MAIN[1][31][7]
DRP[97] bit 0	MAIN[1][30][8]
DRP[97] bit 1	MAIN[1][31][8]
DRP[97] bit 2	MAIN[1][30][9]
DRP[97] bit 3	MAIN[1][31][9]
DRP[97] bit 4	MAIN[1][30][10]
DRP[97] bit 5	MAIN[1][31][10]
DRP[97] bit 6	MAIN[1][30][11]
DRP[97] bit 7	MAIN[1][31][11]
DRP[97] bit 8	MAIN[1][30][12]
DRP[97] bit 9	MAIN[1][31][12]
DRP[97] bit 10	MAIN[1][30][13]
DRP[97] bit 11	MAIN[1][31][13]
DRP[97] bit 12	MAIN[1][30][14]
DRP[97] bit 13	MAIN[1][31][14]
DRP[97] bit 14	MAIN[1][30][15]
DRP[97] bit 15	MAIN[1][31][15]
DRP[98] bit 0	MAIN[1][30][16]
DRP[98] bit 1	MAIN[1][31][16]
DRP[98] bit 2	MAIN[1][30][17]
DRP[98] bit 3	MAIN[1][31][17]
DRP[98] bit 4	MAIN[1][30][18]
DRP[98] bit 5	MAIN[1][31][18]
DRP[98] bit 6	MAIN[1][30][19]
DRP[98] bit 7	MAIN[1][31][19]
DRP[98] bit 8	MAIN[1][30][20]
DRP[98] bit 9	MAIN[1][31][20]
DRP[98] bit 10	MAIN[1][30][21]
DRP[98] bit 11	MAIN[1][31][21]
DRP[98] bit 12	MAIN[1][30][22]
DRP[98] bit 13	MAIN[1][31][22]
DRP[98] bit 14	MAIN[1][30][23]
DRP[98] bit 15	MAIN[1][31][23]
DRP[99] bit 0	MAIN[1][30][24]
DRP[99] bit 1	MAIN[1][31][24]
DRP[99] bit 2	MAIN[1][30][25]
DRP[99] bit 3	MAIN[1][31][25]
DRP[99] bit 4	MAIN[1][30][26]
DRP[99] bit 5	MAIN[1][31][26]
DRP[99] bit 6	MAIN[1][30][27]
DRP[99] bit 7	MAIN[1][31][27]
DRP[99] bit 8	MAIN[1][30][28]
DRP[99] bit 9	MAIN[1][31][28]
DRP[99] bit 10	MAIN[1][30][29]
DRP[99] bit 11	MAIN[1][31][29]
DRP[99] bit 12	MAIN[1][30][30]
DRP[99] bit 13	MAIN[1][31][30]
DRP[99] bit 14	MAIN[1][30][31]
DRP[99] bit 15	MAIN[1][31][31]
DRP[100] bit 0	MAIN[1][30][32]
DRP[100] bit 1	MAIN[1][31][32]
DRP[100] bit 2	MAIN[1][30][33]
DRP[100] bit 3	MAIN[1][31][33]
DRP[100] bit 4	MAIN[1][30][34]
DRP[100] bit 5	MAIN[1][31][34]
DRP[100] bit 6	MAIN[1][30][35]
DRP[100] bit 7	MAIN[1][31][35]
DRP[100] bit 8	MAIN[1][30][36]
DRP[100] bit 9	MAIN[1][31][36]
DRP[100] bit 10	MAIN[1][30][37]
DRP[100] bit 11	MAIN[1][31][37]
DRP[100] bit 12	MAIN[1][30][38]
DRP[100] bit 13	MAIN[1][31][38]
DRP[100] bit 14	MAIN[1][30][39]
DRP[100] bit 15	MAIN[1][31][39]
DRP[101] bit 0	MAIN[1][30][40]
DRP[101] bit 1	MAIN[1][31][40]
DRP[101] bit 2	MAIN[1][30][41]
DRP[101] bit 3	MAIN[1][31][41]
DRP[101] bit 4	MAIN[1][30][42]
DRP[101] bit 5	MAIN[1][31][42]
DRP[101] bit 6	MAIN[1][30][43]
DRP[101] bit 7	MAIN[1][31][43]
DRP[101] bit 8	MAIN[1][30][44]
DRP[101] bit 9	MAIN[1][31][44]
DRP[101] bit 10	MAIN[1][30][45]
DRP[101] bit 11	MAIN[1][31][45]
DRP[101] bit 12	MAIN[1][30][46]
DRP[101] bit 13	MAIN[1][31][46]
DRP[101] bit 14	MAIN[1][30][47]
DRP[101] bit 15	MAIN[1][31][47]
DRP[102] bit 0	MAIN[1][30][48]
DRP[102] bit 1	MAIN[1][31][48]
DRP[102] bit 2	MAIN[1][30][49]
DRP[102] bit 3	MAIN[1][31][49]
DRP[102] bit 4	MAIN[1][30][50]
DRP[102] bit 5	MAIN[1][31][50]
DRP[102] bit 6	MAIN[1][30][51]
DRP[102] bit 7	MAIN[1][31][51]
DRP[102] bit 8	MAIN[1][30][52]
DRP[102] bit 9	MAIN[1][31][52]
DRP[102] bit 10	MAIN[1][30][53]
DRP[102] bit 11	MAIN[1][31][53]
DRP[102] bit 12	MAIN[1][30][54]
DRP[102] bit 13	MAIN[1][31][54]
DRP[102] bit 14	MAIN[1][30][55]
DRP[102] bit 15	MAIN[1][31][55]
DRP[103] bit 0	MAIN[1][30][56]
DRP[103] bit 1	MAIN[1][31][56]
DRP[103] bit 2	MAIN[1][30][57]
DRP[103] bit 3	MAIN[1][31][57]
DRP[103] bit 4	MAIN[1][30][58]
DRP[103] bit 5	MAIN[1][31][58]
DRP[103] bit 6	MAIN[1][30][59]
DRP[103] bit 7	MAIN[1][31][59]
DRP[103] bit 8	MAIN[1][30][60]
DRP[103] bit 9	MAIN[1][31][60]
DRP[103] bit 10	MAIN[1][30][61]
DRP[103] bit 11	MAIN[1][31][61]
DRP[103] bit 12	MAIN[1][30][62]
DRP[103] bit 13	MAIN[1][31][62]
DRP[103] bit 14	MAIN[1][30][63]
DRP[103] bit 15	MAIN[1][31][63]
DRP[104] bit 0	MAIN[2][30][0]
DRP[104] bit 1	MAIN[2][31][0]
DRP[104] bit 2	MAIN[2][30][1]
DRP[104] bit 3	MAIN[2][31][1]
DRP[104] bit 4	MAIN[2][30][2]
DRP[104] bit 5	MAIN[2][31][2]
DRP[104] bit 6	MAIN[2][30][3]
DRP[104] bit 7	MAIN[2][31][3]
DRP[104] bit 8	MAIN[2][30][4]
DRP[104] bit 9	MAIN[2][31][4]
DRP[104] bit 10	MAIN[2][30][5]
DRP[104] bit 11	MAIN[2][31][5]
DRP[104] bit 12	MAIN[2][30][6]
DRP[104] bit 13	MAIN[2][31][6]
DRP[104] bit 14	MAIN[2][30][7]
DRP[104] bit 15	MAIN[2][31][7]
DRP[105] bit 0	MAIN[2][30][8]
DRP[105] bit 1	MAIN[2][31][8]
DRP[105] bit 2	MAIN[2][30][9]
DRP[105] bit 3	MAIN[2][31][9]
DRP[105] bit 4	MAIN[2][30][10]
DRP[105] bit 5	MAIN[2][31][10]
DRP[105] bit 6	MAIN[2][30][11]
DRP[105] bit 7	MAIN[2][31][11]
DRP[105] bit 8	MAIN[2][30][12]
DRP[105] bit 9	MAIN[2][31][12]
DRP[105] bit 10	MAIN[2][30][13]
DRP[105] bit 11	MAIN[2][31][13]
DRP[105] bit 12	MAIN[2][30][14]
DRP[105] bit 13	MAIN[2][31][14]
DRP[105] bit 14	MAIN[2][30][15]
DRP[105] bit 15	MAIN[2][31][15]
DRP[106] bit 0	MAIN[2][30][16]
DRP[106] bit 1	MAIN[2][31][16]
DRP[106] bit 2	MAIN[2][30][17]
DRP[106] bit 3	MAIN[2][31][17]
DRP[106] bit 4	MAIN[2][30][18]
DRP[106] bit 5	MAIN[2][31][18]
DRP[106] bit 6	MAIN[2][30][19]
DRP[106] bit 7	MAIN[2][31][19]
DRP[106] bit 8	MAIN[2][30][20]
DRP[106] bit 9	MAIN[2][31][20]
DRP[106] bit 10	MAIN[2][30][21]
DRP[106] bit 11	MAIN[2][31][21]
DRP[106] bit 12	MAIN[2][30][22]
DRP[106] bit 13	MAIN[2][31][22]
DRP[106] bit 14	MAIN[2][30][23]
DRP[106] bit 15	MAIN[2][31][23]
DRP[107] bit 0	MAIN[2][30][24]
DRP[107] bit 1	MAIN[2][31][24]
DRP[107] bit 2	MAIN[2][30][25]
DRP[107] bit 3	MAIN[2][31][25]
DRP[107] bit 4	MAIN[2][30][26]
DRP[107] bit 5	MAIN[2][31][26]
DRP[107] bit 6	MAIN[2][30][27]
DRP[107] bit 7	MAIN[2][31][27]
DRP[107] bit 8	MAIN[2][30][28]
DRP[107] bit 9	MAIN[2][31][28]
DRP[107] bit 10	MAIN[2][30][29]
DRP[107] bit 11	MAIN[2][31][29]
DRP[107] bit 12	MAIN[2][30][30]
DRP[107] bit 13	MAIN[2][31][30]
DRP[107] bit 14	MAIN[2][30][31]
DRP[107] bit 15	MAIN[2][31][31]
DRP[108] bit 0	MAIN[2][30][32]
DRP[108] bit 1	MAIN[2][31][32]
DRP[108] bit 2	MAIN[2][30][33]
DRP[108] bit 3	MAIN[2][31][33]
DRP[108] bit 4	MAIN[2][30][34]
DRP[108] bit 5	MAIN[2][31][34]
DRP[108] bit 6	MAIN[2][30][35]
DRP[108] bit 7	MAIN[2][31][35]
DRP[108] bit 8	MAIN[2][30][36]
DRP[108] bit 9	MAIN[2][31][36]
DRP[108] bit 10	MAIN[2][30][37]
DRP[108] bit 11	MAIN[2][31][37]
DRP[108] bit 12	MAIN[2][30][38]
DRP[108] bit 13	MAIN[2][31][38]
DRP[108] bit 14	MAIN[2][30][39]
DRP[108] bit 15	MAIN[2][31][39]
DRP[109] bit 0	MAIN[2][30][40]
DRP[109] bit 1	MAIN[2][31][40]
DRP[109] bit 2	MAIN[2][30][41]
DRP[109] bit 3	MAIN[2][31][41]
DRP[109] bit 4	MAIN[2][30][42]
DRP[109] bit 5	MAIN[2][31][42]
DRP[109] bit 6	MAIN[2][30][43]
DRP[109] bit 7	MAIN[2][31][43]
DRP[109] bit 8	MAIN[2][30][44]
DRP[109] bit 9	MAIN[2][31][44]
DRP[109] bit 10	MAIN[2][30][45]
DRP[109] bit 11	MAIN[2][31][45]
DRP[109] bit 12	MAIN[2][30][46]
DRP[109] bit 13	MAIN[2][31][46]
DRP[109] bit 14	MAIN[2][30][47]
DRP[109] bit 15	MAIN[2][31][47]
DRP[110] bit 0	MAIN[2][30][48]
DRP[110] bit 1	MAIN[2][31][48]
DRP[110] bit 2	MAIN[2][30][49]
DRP[110] bit 3	MAIN[2][31][49]
DRP[110] bit 4	MAIN[2][30][50]
DRP[110] bit 5	MAIN[2][31][50]
DRP[110] bit 6	MAIN[2][30][51]
DRP[110] bit 7	MAIN[2][31][51]
DRP[110] bit 8	MAIN[2][30][52]
DRP[110] bit 9	MAIN[2][31][52]
DRP[110] bit 10	MAIN[2][30][53]
DRP[110] bit 11	MAIN[2][31][53]
DRP[110] bit 12	MAIN[2][30][54]
DRP[110] bit 13	MAIN[2][31][54]
DRP[110] bit 14	MAIN[2][30][55]
DRP[110] bit 15	MAIN[2][31][55]
DRP[111] bit 0	MAIN[2][30][56]
DRP[111] bit 1	MAIN[2][31][56]
DRP[111] bit 2	MAIN[2][30][57]
DRP[111] bit 3	MAIN[2][31][57]
DRP[111] bit 4	MAIN[2][30][58]
DRP[111] bit 5	MAIN[2][31][58]
DRP[111] bit 6	MAIN[2][30][59]
DRP[111] bit 7	MAIN[2][31][59]
DRP[111] bit 8	MAIN[2][30][60]
DRP[111] bit 9	MAIN[2][31][60]
DRP[111] bit 10	MAIN[2][30][61]
DRP[111] bit 11	MAIN[2][31][61]
DRP[111] bit 12	MAIN[2][30][62]
DRP[111] bit 13	MAIN[2][31][62]
DRP[111] bit 14	MAIN[2][30][63]
DRP[111] bit 15	MAIN[2][31][63]
DRP[112] bit 0	MAIN[3][30][0]
DRP[112] bit 1	MAIN[3][31][0]
DRP[112] bit 2	MAIN[3][30][1]
DRP[112] bit 3	MAIN[3][31][1]
DRP[112] bit 4	MAIN[3][30][2]
DRP[112] bit 5	MAIN[3][31][2]
DRP[112] bit 6	MAIN[3][30][3]
DRP[112] bit 7	MAIN[3][31][3]
DRP[112] bit 8	MAIN[3][30][4]
DRP[112] bit 9	MAIN[3][31][4]
DRP[112] bit 10	MAIN[3][30][5]
DRP[112] bit 11	MAIN[3][31][5]
DRP[112] bit 12	MAIN[3][30][6]
DRP[112] bit 13	MAIN[3][31][6]
DRP[112] bit 14	MAIN[3][30][7]
DRP[112] bit 15	MAIN[3][31][7]
DRP[113] bit 0	MAIN[3][30][8]
DRP[113] bit 1	MAIN[3][31][8]
DRP[113] bit 2	MAIN[3][30][9]
DRP[113] bit 3	MAIN[3][31][9]
DRP[113] bit 4	MAIN[3][30][10]
DRP[113] bit 5	MAIN[3][31][10]
DRP[113] bit 6	MAIN[3][30][11]
DRP[113] bit 7	MAIN[3][31][11]
DRP[113] bit 8	MAIN[3][30][12]
DRP[113] bit 9	MAIN[3][31][12]
DRP[113] bit 10	MAIN[3][30][13]
DRP[113] bit 11	MAIN[3][31][13]
DRP[113] bit 12	MAIN[3][30][14]
DRP[113] bit 13	MAIN[3][31][14]
DRP[113] bit 14	MAIN[3][30][15]
DRP[113] bit 15	MAIN[3][31][15]
DRP[114] bit 0	MAIN[3][30][16]
DRP[114] bit 1	MAIN[3][31][16]
DRP[114] bit 2	MAIN[3][30][17]
DRP[114] bit 3	MAIN[3][31][17]
DRP[114] bit 4	MAIN[3][30][18]
DRP[114] bit 5	MAIN[3][31][18]
DRP[114] bit 6	MAIN[3][30][19]
DRP[114] bit 7	MAIN[3][31][19]
DRP[114] bit 8	MAIN[3][30][20]
DRP[114] bit 9	MAIN[3][31][20]
DRP[114] bit 10	MAIN[3][30][21]
DRP[114] bit 11	MAIN[3][31][21]
DRP[114] bit 12	MAIN[3][30][22]
DRP[114] bit 13	MAIN[3][31][22]
DRP[114] bit 14	MAIN[3][30][23]
DRP[114] bit 15	MAIN[3][31][23]
DRP[115] bit 0	MAIN[3][30][24]
DRP[115] bit 1	MAIN[3][31][24]
DRP[115] bit 2	MAIN[3][30][25]
DRP[115] bit 3	MAIN[3][31][25]
DRP[115] bit 4	MAIN[3][30][26]
DRP[115] bit 5	MAIN[3][31][26]
DRP[115] bit 6	MAIN[3][30][27]
DRP[115] bit 7	MAIN[3][31][27]
DRP[115] bit 8	MAIN[3][30][28]
DRP[115] bit 9	MAIN[3][31][28]
DRP[115] bit 10	MAIN[3][30][29]
DRP[115] bit 11	MAIN[3][31][29]
DRP[115] bit 12	MAIN[3][30][30]
DRP[115] bit 13	MAIN[3][31][30]
DRP[115] bit 14	MAIN[3][30][31]
DRP[115] bit 15	MAIN[3][31][31]
DRP[116] bit 0	MAIN[3][30][32]
DRP[116] bit 1	MAIN[3][31][32]
DRP[116] bit 2	MAIN[3][30][33]
DRP[116] bit 3	MAIN[3][31][33]
DRP[116] bit 4	MAIN[3][30][34]
DRP[116] bit 5	MAIN[3][31][34]
DRP[116] bit 6	MAIN[3][30][35]
DRP[116] bit 7	MAIN[3][31][35]
DRP[116] bit 8	MAIN[3][30][36]
DRP[116] bit 9	MAIN[3][31][36]
DRP[116] bit 10	MAIN[3][30][37]
DRP[116] bit 11	MAIN[3][31][37]
DRP[116] bit 12	MAIN[3][30][38]
DRP[116] bit 13	MAIN[3][31][38]
DRP[116] bit 14	MAIN[3][30][39]
DRP[116] bit 15	MAIN[3][31][39]
DRP[117] bit 0	MAIN[3][30][40]
DRP[117] bit 1	MAIN[3][31][40]
DRP[117] bit 2	MAIN[3][30][41]
DRP[117] bit 3	MAIN[3][31][41]
DRP[117] bit 4	MAIN[3][30][42]
DRP[117] bit 5	MAIN[3][31][42]
DRP[117] bit 6	MAIN[3][30][43]
DRP[117] bit 7	MAIN[3][31][43]
DRP[117] bit 8	MAIN[3][30][44]
DRP[117] bit 9	MAIN[3][31][44]
DRP[117] bit 10	MAIN[3][30][45]
DRP[117] bit 11	MAIN[3][31][45]
DRP[117] bit 12	MAIN[3][30][46]
DRP[117] bit 13	MAIN[3][31][46]
DRP[117] bit 14	MAIN[3][30][47]
DRP[117] bit 15	MAIN[3][31][47]
DRP[118] bit 0	MAIN[3][30][48]
DRP[118] bit 1	MAIN[3][31][48]
DRP[118] bit 2	MAIN[3][30][49]
DRP[118] bit 3	MAIN[3][31][49]
DRP[118] bit 4	MAIN[3][30][50]
DRP[118] bit 5	MAIN[3][31][50]
DRP[118] bit 6	MAIN[3][30][51]
DRP[118] bit 7	MAIN[3][31][51]
DRP[118] bit 8	MAIN[3][30][52]
DRP[118] bit 9	MAIN[3][31][52]
DRP[118] bit 10	MAIN[3][30][53]
DRP[118] bit 11	MAIN[3][31][53]
DRP[118] bit 12	MAIN[3][30][54]
DRP[118] bit 13	MAIN[3][31][54]
DRP[118] bit 14	MAIN[3][30][55]
DRP[118] bit 15	MAIN[3][31][55]
DRP[119] bit 0	MAIN[3][30][56]
DRP[119] bit 1	MAIN[3][31][56]
DRP[119] bit 2	MAIN[3][30][57]
DRP[119] bit 3	MAIN[3][31][57]
DRP[119] bit 4	MAIN[3][30][58]
DRP[119] bit 5	MAIN[3][31][58]
DRP[119] bit 6	MAIN[3][30][59]
DRP[119] bit 7	MAIN[3][31][59]
DRP[119] bit 8	MAIN[3][30][60]
DRP[119] bit 9	MAIN[3][31][60]
DRP[119] bit 10	MAIN[3][30][61]
DRP[119] bit 11	MAIN[3][31][61]
DRP[119] bit 12	MAIN[3][30][62]
DRP[119] bit 13	MAIN[3][31][62]
DRP[119] bit 14	MAIN[3][30][63]
DRP[119] bit 15	MAIN[3][31][63]
DRP[120] bit 0	MAIN[4][30][0]
DRP[120] bit 1	MAIN[4][31][0]
DRP[120] bit 2	MAIN[4][30][1]
DRP[120] bit 3	MAIN[4][31][1]
DRP[120] bit 4	MAIN[4][30][2]
DRP[120] bit 5	MAIN[4][31][2]
DRP[120] bit 6	MAIN[4][30][3]
DRP[120] bit 7	MAIN[4][31][3]
DRP[120] bit 8	MAIN[4][30][4]
DRP[120] bit 9	MAIN[4][31][4]
DRP[120] bit 10	MAIN[4][30][5]
DRP[120] bit 11	MAIN[4][31][5]
DRP[120] bit 12	MAIN[4][30][6]
DRP[120] bit 13	MAIN[4][31][6]
DRP[120] bit 14	MAIN[4][30][7]
DRP[120] bit 15	MAIN[4][31][7]
DRP[121] bit 0	MAIN[4][30][8]
DRP[121] bit 1	MAIN[4][31][8]
DRP[121] bit 2	MAIN[4][30][9]
DRP[121] bit 3	MAIN[4][31][9]
DRP[121] bit 4	MAIN[4][30][10]
DRP[121] bit 5	MAIN[4][31][10]
DRP[121] bit 6	MAIN[4][30][11]
DRP[121] bit 7	MAIN[4][31][11]
DRP[121] bit 8	MAIN[4][30][12]
DRP[121] bit 9	MAIN[4][31][12]
DRP[121] bit 10	MAIN[4][30][13]
DRP[121] bit 11	MAIN[4][31][13]
DRP[121] bit 12	MAIN[4][30][14]
DRP[121] bit 13	MAIN[4][31][14]
DRP[121] bit 14	MAIN[4][30][15]
DRP[121] bit 15	MAIN[4][31][15]
DRP[122] bit 0	MAIN[4][30][16]
DRP[122] bit 1	MAIN[4][31][16]
DRP[122] bit 2	MAIN[4][30][17]
DRP[122] bit 3	MAIN[4][31][17]
DRP[122] bit 4	MAIN[4][30][18]
DRP[122] bit 5	MAIN[4][31][18]
DRP[122] bit 6	MAIN[4][30][19]
DRP[122] bit 7	MAIN[4][31][19]
DRP[122] bit 8	MAIN[4][30][20]
DRP[122] bit 9	MAIN[4][31][20]
DRP[122] bit 10	MAIN[4][30][21]
DRP[122] bit 11	MAIN[4][31][21]
DRP[122] bit 12	MAIN[4][30][22]
DRP[122] bit 13	MAIN[4][31][22]
DRP[122] bit 14	MAIN[4][30][23]
DRP[122] bit 15	MAIN[4][31][23]
DRP[123] bit 0	MAIN[4][30][24]
DRP[123] bit 1	MAIN[4][31][24]
DRP[123] bit 2	MAIN[4][30][25]
DRP[123] bit 3	MAIN[4][31][25]
DRP[123] bit 4	MAIN[4][30][26]
DRP[123] bit 5	MAIN[4][31][26]
DRP[123] bit 6	MAIN[4][30][27]
DRP[123] bit 7	MAIN[4][31][27]
DRP[123] bit 8	MAIN[4][30][28]
DRP[123] bit 9	MAIN[4][31][28]
DRP[123] bit 10	MAIN[4][30][29]
DRP[123] bit 11	MAIN[4][31][29]
DRP[123] bit 12	MAIN[4][30][30]
DRP[123] bit 13	MAIN[4][31][30]
DRP[123] bit 14	MAIN[4][30][31]
DRP[123] bit 15	MAIN[4][31][31]
DRP[124] bit 0	MAIN[4][30][32]
DRP[124] bit 1	MAIN[4][31][32]
DRP[124] bit 2	MAIN[4][30][33]
DRP[124] bit 3	MAIN[4][31][33]
DRP[124] bit 4	MAIN[4][30][34]
DRP[124] bit 5	MAIN[4][31][34]
DRP[124] bit 6	MAIN[4][30][35]
DRP[124] bit 7	MAIN[4][31][35]
DRP[124] bit 8	MAIN[4][30][36]
DRP[124] bit 9	MAIN[4][31][36]
DRP[124] bit 10	MAIN[4][30][37]
DRP[124] bit 11	MAIN[4][31][37]
DRP[124] bit 12	MAIN[4][30][38]
DRP[124] bit 13	MAIN[4][31][38]
DRP[124] bit 14	MAIN[4][30][39]
DRP[124] bit 15	MAIN[4][31][39]
DRP[125] bit 0	MAIN[4][30][40]
DRP[125] bit 1	MAIN[4][31][40]
DRP[125] bit 2	MAIN[4][30][41]
DRP[125] bit 3	MAIN[4][31][41]
DRP[125] bit 4	MAIN[4][30][42]
DRP[125] bit 5	MAIN[4][31][42]
DRP[125] bit 6	MAIN[4][30][43]
DRP[125] bit 7	MAIN[4][31][43]
DRP[125] bit 8	MAIN[4][30][44]
DRP[125] bit 9	MAIN[4][31][44]
DRP[125] bit 10	MAIN[4][30][45]
DRP[125] bit 11	MAIN[4][31][45]
DRP[125] bit 12	MAIN[4][30][46]
DRP[125] bit 13	MAIN[4][31][46]
DRP[125] bit 14	MAIN[4][30][47]
DRP[125] bit 15	MAIN[4][31][47]
DRP[126] bit 0	MAIN[4][30][48]
DRP[126] bit 1	MAIN[4][31][48]
DRP[126] bit 2	MAIN[4][30][49]
DRP[126] bit 3	MAIN[4][31][49]
DRP[126] bit 4	MAIN[4][30][50]
DRP[126] bit 5	MAIN[4][31][50]
DRP[126] bit 6	MAIN[4][30][51]
DRP[126] bit 7	MAIN[4][31][51]
DRP[126] bit 8	MAIN[4][30][52]
DRP[126] bit 9	MAIN[4][31][52]
DRP[126] bit 10	MAIN[4][30][53]
DRP[126] bit 11	MAIN[4][31][53]
DRP[126] bit 12	MAIN[4][30][54]
DRP[126] bit 13	MAIN[4][31][54]
DRP[126] bit 14	MAIN[4][30][55]
DRP[126] bit 15	MAIN[4][31][55]
DRP[127] bit 0	MAIN[4][30][56]
DRP[127] bit 1	MAIN[4][31][56]
DRP[127] bit 2	MAIN[4][30][57]
DRP[127] bit 3	MAIN[4][31][57]
DRP[127] bit 4	MAIN[4][30][58]
DRP[127] bit 5	MAIN[4][31][58]
DRP[127] bit 6	MAIN[4][30][59]
DRP[127] bit 7	MAIN[4][31][59]
DRP[127] bit 8	MAIN[4][30][60]
DRP[127] bit 9	MAIN[4][31][60]
DRP[127] bit 10	MAIN[4][30][61]
DRP[127] bit 11	MAIN[4][31][61]
DRP[127] bit 12	MAIN[4][30][62]
DRP[127] bit 13	MAIN[4][31][62]
DRP[127] bit 14	MAIN[4][30][63]
DRP[127] bit 15	MAIN[4][31][63]
DRP[128] bit 0	MAIN[5][30][0]
DRP[128] bit 1	MAIN[5][31][0]
DRP[128] bit 2	MAIN[5][30][1]
DRP[128] bit 3	MAIN[5][31][1]
DRP[128] bit 4	MAIN[5][30][2]
DRP[128] bit 5	MAIN[5][31][2]
DRP[128] bit 6	MAIN[5][30][3]
DRP[128] bit 7	MAIN[5][31][3]
DRP[128] bit 8	MAIN[5][30][4]
DRP[128] bit 9	MAIN[5][31][4]
DRP[128] bit 10	MAIN[5][30][5]
DRP[128] bit 11	MAIN[5][31][5]
DRP[128] bit 12	MAIN[5][30][6]
DRP[128] bit 13	MAIN[5][31][6]
DRP[128] bit 14	MAIN[5][30][7]
DRP[128] bit 15	MAIN[5][31][7]
DRP[129] bit 0	MAIN[5][30][8]
DRP[129] bit 1	MAIN[5][31][8]
DRP[129] bit 2	MAIN[5][30][9]
DRP[129] bit 3	MAIN[5][31][9]
DRP[129] bit 4	MAIN[5][30][10]
DRP[129] bit 5	MAIN[5][31][10]
DRP[129] bit 6	MAIN[5][30][11]
DRP[129] bit 7	MAIN[5][31][11]
DRP[129] bit 8	MAIN[5][30][12]
DRP[129] bit 9	MAIN[5][31][12]
DRP[129] bit 10	MAIN[5][30][13]
DRP[129] bit 11	MAIN[5][31][13]
DRP[129] bit 12	MAIN[5][30][14]
DRP[129] bit 13	MAIN[5][31][14]
DRP[129] bit 14	MAIN[5][30][15]
DRP[129] bit 15	MAIN[5][31][15]
DRP[130] bit 0	MAIN[5][30][16]
DRP[130] bit 1	MAIN[5][31][16]
DRP[130] bit 2	MAIN[5][30][17]
DRP[130] bit 3	MAIN[5][31][17]
DRP[130] bit 4	MAIN[5][30][18]
DRP[130] bit 5	MAIN[5][31][18]
DRP[130] bit 6	MAIN[5][30][19]
DRP[130] bit 7	MAIN[5][31][19]
DRP[130] bit 8	MAIN[5][30][20]
DRP[130] bit 9	MAIN[5][31][20]
DRP[130] bit 10	MAIN[5][30][21]
DRP[130] bit 11	MAIN[5][31][21]
DRP[130] bit 12	MAIN[5][30][22]
DRP[130] bit 13	MAIN[5][31][22]
DRP[130] bit 14	MAIN[5][30][23]
DRP[130] bit 15	MAIN[5][31][23]
DRP[131] bit 0	MAIN[5][30][24]
DRP[131] bit 1	MAIN[5][31][24]
DRP[131] bit 2	MAIN[5][30][25]
DRP[131] bit 3	MAIN[5][31][25]
DRP[131] bit 4	MAIN[5][30][26]
DRP[131] bit 5	MAIN[5][31][26]
DRP[131] bit 6	MAIN[5][30][27]
DRP[131] bit 7	MAIN[5][31][27]
DRP[131] bit 8	MAIN[5][30][28]
DRP[131] bit 9	MAIN[5][31][28]
DRP[131] bit 10	MAIN[5][30][29]
DRP[131] bit 11	MAIN[5][31][29]
DRP[131] bit 12	MAIN[5][30][30]
DRP[131] bit 13	MAIN[5][31][30]
DRP[131] bit 14	MAIN[5][30][31]
DRP[131] bit 15	MAIN[5][31][31]
DRP[132] bit 0	MAIN[5][30][32]
DRP[132] bit 1	MAIN[5][31][32]
DRP[132] bit 2	MAIN[5][30][33]
DRP[132] bit 3	MAIN[5][31][33]
DRP[132] bit 4	MAIN[5][30][34]
DRP[132] bit 5	MAIN[5][31][34]
DRP[132] bit 6	MAIN[5][30][35]
DRP[132] bit 7	MAIN[5][31][35]
DRP[132] bit 8	MAIN[5][30][36]
DRP[132] bit 9	MAIN[5][31][36]
DRP[132] bit 10	MAIN[5][30][37]
DRP[132] bit 11	MAIN[5][31][37]
DRP[132] bit 12	MAIN[5][30][38]
DRP[132] bit 13	MAIN[5][31][38]
DRP[132] bit 14	MAIN[5][30][39]
DRP[132] bit 15	MAIN[5][31][39]
DRP[133] bit 0	MAIN[5][30][40]
DRP[133] bit 1	MAIN[5][31][40]
DRP[133] bit 2	MAIN[5][30][41]
DRP[133] bit 3	MAIN[5][31][41]
DRP[133] bit 4	MAIN[5][30][42]
DRP[133] bit 5	MAIN[5][31][42]
DRP[133] bit 6	MAIN[5][30][43]
DRP[133] bit 7	MAIN[5][31][43]
DRP[133] bit 8	MAIN[5][30][44]
DRP[133] bit 9	MAIN[5][31][44]
DRP[133] bit 10	MAIN[5][30][45]
DRP[133] bit 11	MAIN[5][31][45]
DRP[133] bit 12	MAIN[5][30][46]
DRP[133] bit 13	MAIN[5][31][46]
DRP[133] bit 14	MAIN[5][30][47]
DRP[133] bit 15	MAIN[5][31][47]
DRP[134] bit 0	MAIN[5][30][48]
DRP[134] bit 1	MAIN[5][31][48]
DRP[134] bit 2	MAIN[5][30][49]
DRP[134] bit 3	MAIN[5][31][49]
DRP[134] bit 4	MAIN[5][30][50]
DRP[134] bit 5	MAIN[5][31][50]
DRP[134] bit 6	MAIN[5][30][51]
DRP[134] bit 7	MAIN[5][31][51]
DRP[134] bit 8	MAIN[5][30][52]
DRP[134] bit 9	MAIN[5][31][52]
DRP[134] bit 10	MAIN[5][30][53]
DRP[134] bit 11	MAIN[5][31][53]
DRP[134] bit 12	MAIN[5][30][54]
DRP[134] bit 13	MAIN[5][31][54]
DRP[134] bit 14	MAIN[5][30][55]
DRP[134] bit 15	MAIN[5][31][55]
DRP[135] bit 0	MAIN[5][30][56]
DRP[135] bit 1	MAIN[5][31][56]
DRP[135] bit 2	MAIN[5][30][57]
DRP[135] bit 3	MAIN[5][31][57]
DRP[135] bit 4	MAIN[5][30][58]
DRP[135] bit 5	MAIN[5][31][58]
DRP[135] bit 6	MAIN[5][30][59]
DRP[135] bit 7	MAIN[5][31][59]
DRP[135] bit 8	MAIN[5][30][60]
DRP[135] bit 9	MAIN[5][31][60]
DRP[135] bit 10	MAIN[5][30][61]
DRP[135] bit 11	MAIN[5][31][61]
DRP[135] bit 12	MAIN[5][30][62]
DRP[135] bit 13	MAIN[5][31][62]
DRP[135] bit 14	MAIN[5][30][63]
DRP[135] bit 15	MAIN[5][31][63]
DRP[136] bit 0	MAIN[6][30][0]
DRP[136] bit 1	MAIN[6][31][0]
DRP[136] bit 2	MAIN[6][30][1]
DRP[136] bit 3	MAIN[6][31][1]
DRP[136] bit 4	MAIN[6][30][2]
DRP[136] bit 5	MAIN[6][31][2]
DRP[136] bit 6	MAIN[6][30][3]
DRP[136] bit 7	MAIN[6][31][3]
DRP[136] bit 8	MAIN[6][30][4]
DRP[136] bit 9	MAIN[6][31][4]
DRP[136] bit 10	MAIN[6][30][5]
DRP[136] bit 11	MAIN[6][31][5]
DRP[136] bit 12	MAIN[6][30][6]
DRP[136] bit 13	MAIN[6][31][6]
DRP[136] bit 14	MAIN[6][30][7]
DRP[136] bit 15	MAIN[6][31][7]
DRP[137] bit 0	MAIN[6][30][8]
DRP[137] bit 1	MAIN[6][31][8]
DRP[137] bit 2	MAIN[6][30][9]
DRP[137] bit 3	MAIN[6][31][9]
DRP[137] bit 4	MAIN[6][30][10]
DRP[137] bit 5	MAIN[6][31][10]
DRP[137] bit 6	MAIN[6][30][11]
DRP[137] bit 7	MAIN[6][31][11]
DRP[137] bit 8	MAIN[6][30][12]
DRP[137] bit 9	MAIN[6][31][12]
DRP[137] bit 10	MAIN[6][30][13]
DRP[137] bit 11	MAIN[6][31][13]
DRP[137] bit 12	MAIN[6][30][14]
DRP[137] bit 13	MAIN[6][31][14]
DRP[137] bit 14	MAIN[6][30][15]
DRP[137] bit 15	MAIN[6][31][15]
DRP[138] bit 0	MAIN[6][30][16]
DRP[138] bit 1	MAIN[6][31][16]
DRP[138] bit 2	MAIN[6][30][17]
DRP[138] bit 3	MAIN[6][31][17]
DRP[138] bit 4	MAIN[6][30][18]
DRP[138] bit 5	MAIN[6][31][18]
DRP[138] bit 6	MAIN[6][30][19]
DRP[138] bit 7	MAIN[6][31][19]
DRP[138] bit 8	MAIN[6][30][20]
DRP[138] bit 9	MAIN[6][31][20]
DRP[138] bit 10	MAIN[6][30][21]
DRP[138] bit 11	MAIN[6][31][21]
DRP[138] bit 12	MAIN[6][30][22]
DRP[138] bit 13	MAIN[6][31][22]
DRP[138] bit 14	MAIN[6][30][23]
DRP[138] bit 15	MAIN[6][31][23]
DRP[139] bit 0	MAIN[6][30][24]
DRP[139] bit 1	MAIN[6][31][24]
DRP[139] bit 2	MAIN[6][30][25]
DRP[139] bit 3	MAIN[6][31][25]
DRP[139] bit 4	MAIN[6][30][26]
DRP[139] bit 5	MAIN[6][31][26]
DRP[139] bit 6	MAIN[6][30][27]
DRP[139] bit 7	MAIN[6][31][27]
DRP[139] bit 8	MAIN[6][30][28]
DRP[139] bit 9	MAIN[6][31][28]
DRP[139] bit 10	MAIN[6][30][29]
DRP[139] bit 11	MAIN[6][31][29]
DRP[139] bit 12	MAIN[6][30][30]
DRP[139] bit 13	MAIN[6][31][30]
DRP[139] bit 14	MAIN[6][30][31]
DRP[139] bit 15	MAIN[6][31][31]
DRP[140] bit 0	MAIN[6][30][32]
DRP[140] bit 1	MAIN[6][31][32]
DRP[140] bit 2	MAIN[6][30][33]
DRP[140] bit 3	MAIN[6][31][33]
DRP[140] bit 4	MAIN[6][30][34]
DRP[140] bit 5	MAIN[6][31][34]
DRP[140] bit 6	MAIN[6][30][35]
DRP[140] bit 7	MAIN[6][31][35]
DRP[140] bit 8	MAIN[6][30][36]
DRP[140] bit 9	MAIN[6][31][36]
DRP[140] bit 10	MAIN[6][30][37]
DRP[140] bit 11	MAIN[6][31][37]
DRP[140] bit 12	MAIN[6][30][38]
DRP[140] bit 13	MAIN[6][31][38]
DRP[140] bit 14	MAIN[6][30][39]
DRP[140] bit 15	MAIN[6][31][39]
DRP[141] bit 0	MAIN[6][30][40]
DRP[141] bit 1	MAIN[6][31][40]
DRP[141] bit 2	MAIN[6][30][41]
DRP[141] bit 3	MAIN[6][31][41]
DRP[141] bit 4	MAIN[6][30][42]
DRP[141] bit 5	MAIN[6][31][42]
DRP[141] bit 6	MAIN[6][30][43]
DRP[141] bit 7	MAIN[6][31][43]
DRP[141] bit 8	MAIN[6][30][44]
DRP[141] bit 9	MAIN[6][31][44]
DRP[141] bit 10	MAIN[6][30][45]
DRP[141] bit 11	MAIN[6][31][45]
DRP[141] bit 12	MAIN[6][30][46]
DRP[141] bit 13	MAIN[6][31][46]
DRP[141] bit 14	MAIN[6][30][47]
DRP[141] bit 15	MAIN[6][31][47]
DRP[142] bit 0	MAIN[6][30][48]
DRP[142] bit 1	MAIN[6][31][48]
DRP[142] bit 2	MAIN[6][30][49]
DRP[142] bit 3	MAIN[6][31][49]
DRP[142] bit 4	MAIN[6][30][50]
DRP[142] bit 5	MAIN[6][31][50]
DRP[142] bit 6	MAIN[6][30][51]
DRP[142] bit 7	MAIN[6][31][51]
DRP[142] bit 8	MAIN[6][30][52]
DRP[142] bit 9	MAIN[6][31][52]
DRP[142] bit 10	MAIN[6][30][53]
DRP[142] bit 11	MAIN[6][31][53]
DRP[142] bit 12	MAIN[6][30][54]
DRP[142] bit 13	MAIN[6][31][54]
DRP[142] bit 14	MAIN[6][30][55]
DRP[142] bit 15	MAIN[6][31][55]
DRP[143] bit 0	MAIN[6][30][56]
DRP[143] bit 1	MAIN[6][31][56]
DRP[143] bit 2	MAIN[6][30][57]
DRP[143] bit 3	MAIN[6][31][57]
DRP[143] bit 4	MAIN[6][30][58]
DRP[143] bit 5	MAIN[6][31][58]
DRP[143] bit 6	MAIN[6][30][59]
DRP[143] bit 7	MAIN[6][31][59]
DRP[143] bit 8	MAIN[6][30][60]
DRP[143] bit 9	MAIN[6][31][60]
DRP[143] bit 10	MAIN[6][30][61]
DRP[143] bit 11	MAIN[6][31][61]
DRP[143] bit 12	MAIN[6][30][62]
DRP[143] bit 13	MAIN[6][31][62]
DRP[143] bit 14	MAIN[6][30][63]
DRP[143] bit 15	MAIN[6][31][63]
DRP[144] bit 0	MAIN[7][30][0]
DRP[144] bit 1	MAIN[7][31][0]
DRP[144] bit 2	MAIN[7][30][1]
DRP[144] bit 3	MAIN[7][31][1]
DRP[144] bit 4	MAIN[7][30][2]
DRP[144] bit 5	MAIN[7][31][2]
DRP[144] bit 6	MAIN[7][30][3]
DRP[144] bit 7	MAIN[7][31][3]
DRP[144] bit 8	MAIN[7][30][4]
DRP[144] bit 9	MAIN[7][31][4]
DRP[144] bit 10	MAIN[7][30][5]
DRP[144] bit 11	MAIN[7][31][5]
DRP[144] bit 12	MAIN[7][30][6]
DRP[144] bit 13	MAIN[7][31][6]
DRP[144] bit 14	MAIN[7][30][7]
DRP[144] bit 15	MAIN[7][31][7]
DRP[145] bit 0	MAIN[7][30][8]
DRP[145] bit 1	MAIN[7][31][8]
DRP[145] bit 2	MAIN[7][30][9]
DRP[145] bit 3	MAIN[7][31][9]
DRP[145] bit 4	MAIN[7][30][10]
DRP[145] bit 5	MAIN[7][31][10]
DRP[145] bit 6	MAIN[7][30][11]
DRP[145] bit 7	MAIN[7][31][11]
DRP[145] bit 8	MAIN[7][30][12]
DRP[145] bit 9	MAIN[7][31][12]
DRP[145] bit 10	MAIN[7][30][13]
DRP[145] bit 11	MAIN[7][31][13]
DRP[145] bit 12	MAIN[7][30][14]
DRP[145] bit 13	MAIN[7][31][14]
DRP[145] bit 14	MAIN[7][30][15]
DRP[145] bit 15	MAIN[7][31][15]
DRP[146] bit 0	MAIN[7][30][16]
DRP[146] bit 1	MAIN[7][31][16]
DRP[146] bit 2	MAIN[7][30][17]
DRP[146] bit 3	MAIN[7][31][17]
DRP[146] bit 4	MAIN[7][30][18]
DRP[146] bit 5	MAIN[7][31][18]
DRP[146] bit 6	MAIN[7][30][19]
DRP[146] bit 7	MAIN[7][31][19]
DRP[146] bit 8	MAIN[7][30][20]
DRP[146] bit 9	MAIN[7][31][20]
DRP[146] bit 10	MAIN[7][30][21]
DRP[146] bit 11	MAIN[7][31][21]
DRP[146] bit 12	MAIN[7][30][22]
DRP[146] bit 13	MAIN[7][31][22]
DRP[146] bit 14	MAIN[7][30][23]
DRP[146] bit 15	MAIN[7][31][23]
DRP[147] bit 0	MAIN[7][30][24]
DRP[147] bit 1	MAIN[7][31][24]
DRP[147] bit 2	MAIN[7][30][25]
DRP[147] bit 3	MAIN[7][31][25]
DRP[147] bit 4	MAIN[7][30][26]
DRP[147] bit 5	MAIN[7][31][26]
DRP[147] bit 6	MAIN[7][30][27]
DRP[147] bit 7	MAIN[7][31][27]
DRP[147] bit 8	MAIN[7][30][28]
DRP[147] bit 9	MAIN[7][31][28]
DRP[147] bit 10	MAIN[7][30][29]
DRP[147] bit 11	MAIN[7][31][29]
DRP[147] bit 12	MAIN[7][30][30]
DRP[147] bit 13	MAIN[7][31][30]
DRP[147] bit 14	MAIN[7][30][31]
DRP[147] bit 15	MAIN[7][31][31]
DRP[148] bit 0	MAIN[7][30][32]
DRP[148] bit 1	MAIN[7][31][32]
DRP[148] bit 2	MAIN[7][30][33]
DRP[148] bit 3	MAIN[7][31][33]
DRP[148] bit 4	MAIN[7][30][34]
DRP[148] bit 5	MAIN[7][31][34]
DRP[148] bit 6	MAIN[7][30][35]
DRP[148] bit 7	MAIN[7][31][35]
DRP[148] bit 8	MAIN[7][30][36]
DRP[148] bit 9	MAIN[7][31][36]
DRP[148] bit 10	MAIN[7][30][37]
DRP[148] bit 11	MAIN[7][31][37]
DRP[148] bit 12	MAIN[7][30][38]
DRP[148] bit 13	MAIN[7][31][38]
DRP[148] bit 14	MAIN[7][30][39]
DRP[148] bit 15	MAIN[7][31][39]
DRP[149] bit 0	MAIN[7][30][40]
DRP[149] bit 1	MAIN[7][31][40]
DRP[149] bit 2	MAIN[7][30][41]
DRP[149] bit 3	MAIN[7][31][41]
DRP[149] bit 4	MAIN[7][30][42]
DRP[149] bit 5	MAIN[7][31][42]
DRP[149] bit 6	MAIN[7][30][43]
DRP[149] bit 7	MAIN[7][31][43]
DRP[149] bit 8	MAIN[7][30][44]
DRP[149] bit 9	MAIN[7][31][44]
DRP[149] bit 10	MAIN[7][30][45]
DRP[149] bit 11	MAIN[7][31][45]
DRP[149] bit 12	MAIN[7][30][46]
DRP[149] bit 13	MAIN[7][31][46]
DRP[149] bit 14	MAIN[7][30][47]
DRP[149] bit 15	MAIN[7][31][47]
DRP[150] bit 0	MAIN[7][30][48]
DRP[150] bit 1	MAIN[7][31][48]
DRP[150] bit 2	MAIN[7][30][49]
DRP[150] bit 3	MAIN[7][31][49]
DRP[150] bit 4	MAIN[7][30][50]
DRP[150] bit 5	MAIN[7][31][50]
DRP[150] bit 6	MAIN[7][30][51]
DRP[150] bit 7	MAIN[7][31][51]
DRP[150] bit 8	MAIN[7][30][52]
DRP[150] bit 9	MAIN[7][31][52]
DRP[150] bit 10	MAIN[7][30][53]
DRP[150] bit 11	MAIN[7][31][53]
DRP[150] bit 12	MAIN[7][30][54]
DRP[150] bit 13	MAIN[7][31][54]
DRP[150] bit 14	MAIN[7][30][55]
DRP[150] bit 15	MAIN[7][31][55]
DRP[151] bit 0	MAIN[7][30][56]
DRP[151] bit 1	MAIN[7][31][56]
DRP[151] bit 2	MAIN[7][30][57]
DRP[151] bit 3	MAIN[7][31][57]
DRP[151] bit 4	MAIN[7][30][58]
DRP[151] bit 5	MAIN[7][31][58]
DRP[151] bit 6	MAIN[7][30][59]
DRP[151] bit 7	MAIN[7][31][59]
DRP[151] bit 8	MAIN[7][30][60]
DRP[151] bit 9	MAIN[7][31][60]
DRP[151] bit 10	MAIN[7][30][61]
DRP[151] bit 11	MAIN[7][31][61]
DRP[151] bit 12	MAIN[7][30][62]
DRP[151] bit 13	MAIN[7][31][62]
DRP[151] bit 14	MAIN[7][30][63]
DRP[151] bit 15	MAIN[7][31][63]
DRP[152] bit 0	MAIN[8][30][0]
DRP[152] bit 1	MAIN[8][31][0]
DRP[152] bit 2	MAIN[8][30][1]
DRP[152] bit 3	MAIN[8][31][1]
DRP[152] bit 4	MAIN[8][30][2]
DRP[152] bit 5	MAIN[8][31][2]
DRP[152] bit 6	MAIN[8][30][3]
DRP[152] bit 7	MAIN[8][31][3]
DRP[152] bit 8	MAIN[8][30][4]
DRP[152] bit 9	MAIN[8][31][4]
DRP[152] bit 10	MAIN[8][30][5]
DRP[152] bit 11	MAIN[8][31][5]
DRP[152] bit 12	MAIN[8][30][6]
DRP[152] bit 13	MAIN[8][31][6]
DRP[152] bit 14	MAIN[8][30][7]
DRP[152] bit 15	MAIN[8][31][7]
DRP[153] bit 0	MAIN[8][30][8]
DRP[153] bit 1	MAIN[8][31][8]
DRP[153] bit 2	MAIN[8][30][9]
DRP[153] bit 3	MAIN[8][31][9]
DRP[153] bit 4	MAIN[8][30][10]
DRP[153] bit 5	MAIN[8][31][10]
DRP[153] bit 6	MAIN[8][30][11]
DRP[153] bit 7	MAIN[8][31][11]
DRP[153] bit 8	MAIN[8][30][12]
DRP[153] bit 9	MAIN[8][31][12]
DRP[153] bit 10	MAIN[8][30][13]
DRP[153] bit 11	MAIN[8][31][13]
DRP[153] bit 12	MAIN[8][30][14]
DRP[153] bit 13	MAIN[8][31][14]
DRP[153] bit 14	MAIN[8][30][15]
DRP[153] bit 15	MAIN[8][31][15]
DRP[154] bit 0	MAIN[8][30][16]
DRP[154] bit 1	MAIN[8][31][16]
DRP[154] bit 2	MAIN[8][30][17]
DRP[154] bit 3	MAIN[8][31][17]
DRP[154] bit 4	MAIN[8][30][18]
DRP[154] bit 5	MAIN[8][31][18]
DRP[154] bit 6	MAIN[8][30][19]
DRP[154] bit 7	MAIN[8][31][19]
DRP[154] bit 8	MAIN[8][30][20]
DRP[154] bit 9	MAIN[8][31][20]
DRP[154] bit 10	MAIN[8][30][21]
DRP[154] bit 11	MAIN[8][31][21]
DRP[154] bit 12	MAIN[8][30][22]
DRP[154] bit 13	MAIN[8][31][22]
DRP[154] bit 14	MAIN[8][30][23]
DRP[154] bit 15	MAIN[8][31][23]
DRP[155] bit 0	MAIN[8][30][24]
DRP[155] bit 1	MAIN[8][31][24]
DRP[155] bit 2	MAIN[8][30][25]
DRP[155] bit 3	MAIN[8][31][25]
DRP[155] bit 4	MAIN[8][30][26]
DRP[155] bit 5	MAIN[8][31][26]
DRP[155] bit 6	MAIN[8][30][27]
DRP[155] bit 7	MAIN[8][31][27]
DRP[155] bit 8	MAIN[8][30][28]
DRP[155] bit 9	MAIN[8][31][28]
DRP[155] bit 10	MAIN[8][30][29]
DRP[155] bit 11	MAIN[8][31][29]
DRP[155] bit 12	MAIN[8][30][30]
DRP[155] bit 13	MAIN[8][31][30]
DRP[155] bit 14	MAIN[8][30][31]
DRP[155] bit 15	MAIN[8][31][31]
DRP[156] bit 0	MAIN[8][30][32]
DRP[156] bit 1	MAIN[8][31][32]
DRP[156] bit 2	MAIN[8][30][33]
DRP[156] bit 3	MAIN[8][31][33]
DRP[156] bit 4	MAIN[8][30][34]
DRP[156] bit 5	MAIN[8][31][34]
DRP[156] bit 6	MAIN[8][30][35]
DRP[156] bit 7	MAIN[8][31][35]
DRP[156] bit 8	MAIN[8][30][36]
DRP[156] bit 9	MAIN[8][31][36]
DRP[156] bit 10	MAIN[8][30][37]
DRP[156] bit 11	MAIN[8][31][37]
DRP[156] bit 12	MAIN[8][30][38]
DRP[156] bit 13	MAIN[8][31][38]
DRP[156] bit 14	MAIN[8][30][39]
DRP[156] bit 15	MAIN[8][31][39]
DRP[157] bit 0	MAIN[8][30][40]
DRP[157] bit 1	MAIN[8][31][40]
DRP[157] bit 2	MAIN[8][30][41]
DRP[157] bit 3	MAIN[8][31][41]
DRP[157] bit 4	MAIN[8][30][42]
DRP[157] bit 5	MAIN[8][31][42]
DRP[157] bit 6	MAIN[8][30][43]
DRP[157] bit 7	MAIN[8][31][43]
DRP[157] bit 8	MAIN[8][30][44]
DRP[157] bit 9	MAIN[8][31][44]
DRP[157] bit 10	MAIN[8][30][45]
DRP[157] bit 11	MAIN[8][31][45]
DRP[157] bit 12	MAIN[8][30][46]
DRP[157] bit 13	MAIN[8][31][46]
DRP[157] bit 14	MAIN[8][30][47]
DRP[157] bit 15	MAIN[8][31][47]
DRP[158] bit 0	MAIN[8][30][48]
DRP[158] bit 1	MAIN[8][31][48]
DRP[158] bit 2	MAIN[8][30][49]
DRP[158] bit 3	MAIN[8][31][49]
DRP[158] bit 4	MAIN[8][30][50]
DRP[158] bit 5	MAIN[8][31][50]
DRP[158] bit 6	MAIN[8][30][51]
DRP[158] bit 7	MAIN[8][31][51]
DRP[158] bit 8	MAIN[8][30][52]
DRP[158] bit 9	MAIN[8][31][52]
DRP[158] bit 10	MAIN[8][30][53]
DRP[158] bit 11	MAIN[8][31][53]
DRP[158] bit 12	MAIN[8][30][54]
DRP[158] bit 13	MAIN[8][31][54]
DRP[158] bit 14	MAIN[8][30][55]
DRP[158] bit 15	MAIN[8][31][55]
DRP[159] bit 0	MAIN[8][30][56]
DRP[159] bit 1	MAIN[8][31][56]
DRP[159] bit 2	MAIN[8][30][57]
DRP[159] bit 3	MAIN[8][31][57]
DRP[159] bit 4	MAIN[8][30][58]
DRP[159] bit 5	MAIN[8][31][58]
DRP[159] bit 6	MAIN[8][30][59]
DRP[159] bit 7	MAIN[8][31][59]
DRP[159] bit 8	MAIN[8][30][60]
DRP[159] bit 9	MAIN[8][31][60]
DRP[159] bit 10	MAIN[8][30][61]
DRP[159] bit 11	MAIN[8][31][61]
DRP[159] bit 12	MAIN[8][30][62]
DRP[159] bit 13	MAIN[8][31][62]
DRP[159] bit 14	MAIN[8][30][63]
DRP[159] bit 15	MAIN[8][31][63]
DRP[160] bit 0	MAIN[9][30][0]
DRP[160] bit 1	MAIN[9][31][0]
DRP[160] bit 2	MAIN[9][30][1]
DRP[160] bit 3	MAIN[9][31][1]
DRP[160] bit 4	MAIN[9][30][2]
DRP[160] bit 5	MAIN[9][31][2]
DRP[160] bit 6	MAIN[9][30][3]
DRP[160] bit 7	MAIN[9][31][3]
DRP[160] bit 8	MAIN[9][30][4]
DRP[160] bit 9	MAIN[9][31][4]
DRP[160] bit 10	MAIN[9][30][5]
DRP[160] bit 11	MAIN[9][31][5]
DRP[160] bit 12	MAIN[9][30][6]
DRP[160] bit 13	MAIN[9][31][6]
DRP[160] bit 14	MAIN[9][30][7]
DRP[160] bit 15	MAIN[9][31][7]
DRP[161] bit 0	MAIN[9][30][8]
DRP[161] bit 1	MAIN[9][31][8]
DRP[161] bit 2	MAIN[9][30][9]
DRP[161] bit 3	MAIN[9][31][9]
DRP[161] bit 4	MAIN[9][30][10]
DRP[161] bit 5	MAIN[9][31][10]
DRP[161] bit 6	MAIN[9][30][11]
DRP[161] bit 7	MAIN[9][31][11]
DRP[161] bit 8	MAIN[9][30][12]
DRP[161] bit 9	MAIN[9][31][12]
DRP[161] bit 10	MAIN[9][30][13]
DRP[161] bit 11	MAIN[9][31][13]
DRP[161] bit 12	MAIN[9][30][14]
DRP[161] bit 13	MAIN[9][31][14]
DRP[161] bit 14	MAIN[9][30][15]
DRP[161] bit 15	MAIN[9][31][15]
DRP[162] bit 0	MAIN[9][30][16]
DRP[162] bit 1	MAIN[9][31][16]
DRP[162] bit 2	MAIN[9][30][17]
DRP[162] bit 3	MAIN[9][31][17]
DRP[162] bit 4	MAIN[9][30][18]
DRP[162] bit 5	MAIN[9][31][18]
DRP[162] bit 6	MAIN[9][30][19]
DRP[162] bit 7	MAIN[9][31][19]
DRP[162] bit 8	MAIN[9][30][20]
DRP[162] bit 9	MAIN[9][31][20]
DRP[162] bit 10	MAIN[9][30][21]
DRP[162] bit 11	MAIN[9][31][21]
DRP[162] bit 12	MAIN[9][30][22]
DRP[162] bit 13	MAIN[9][31][22]
DRP[162] bit 14	MAIN[9][30][23]
DRP[162] bit 15	MAIN[9][31][23]
DRP[163] bit 0	MAIN[9][30][24]
DRP[163] bit 1	MAIN[9][31][24]
DRP[163] bit 2	MAIN[9][30][25]
DRP[163] bit 3	MAIN[9][31][25]
DRP[163] bit 4	MAIN[9][30][26]
DRP[163] bit 5	MAIN[9][31][26]
DRP[163] bit 6	MAIN[9][30][27]
DRP[163] bit 7	MAIN[9][31][27]
DRP[163] bit 8	MAIN[9][30][28]
DRP[163] bit 9	MAIN[9][31][28]
DRP[163] bit 10	MAIN[9][30][29]
DRP[163] bit 11	MAIN[9][31][29]
DRP[163] bit 12	MAIN[9][30][30]
DRP[163] bit 13	MAIN[9][31][30]
DRP[163] bit 14	MAIN[9][30][31]
DRP[163] bit 15	MAIN[9][31][31]
DRP[164] bit 0	MAIN[9][30][32]
DRP[164] bit 1	MAIN[9][31][32]
DRP[164] bit 2	MAIN[9][30][33]
DRP[164] bit 3	MAIN[9][31][33]
DRP[164] bit 4	MAIN[9][30][34]
DRP[164] bit 5	MAIN[9][31][34]
DRP[164] bit 6	MAIN[9][30][35]
DRP[164] bit 7	MAIN[9][31][35]
DRP[164] bit 8	MAIN[9][30][36]
DRP[164] bit 9	MAIN[9][31][36]
DRP[164] bit 10	MAIN[9][30][37]
DRP[164] bit 11	MAIN[9][31][37]
DRP[164] bit 12	MAIN[9][30][38]
DRP[164] bit 13	MAIN[9][31][38]
DRP[164] bit 14	MAIN[9][30][39]
DRP[164] bit 15	MAIN[9][31][39]
DRP[165] bit 0	MAIN[9][30][40]
DRP[165] bit 1	MAIN[9][31][40]
DRP[165] bit 2	MAIN[9][30][41]
DRP[165] bit 3	MAIN[9][31][41]
DRP[165] bit 4	MAIN[9][30][42]
DRP[165] bit 5	MAIN[9][31][42]
DRP[165] bit 6	MAIN[9][30][43]
DRP[165] bit 7	MAIN[9][31][43]
DRP[165] bit 8	MAIN[9][30][44]
DRP[165] bit 9	MAIN[9][31][44]
DRP[165] bit 10	MAIN[9][30][45]
DRP[165] bit 11	MAIN[9][31][45]
DRP[165] bit 12	MAIN[9][30][46]
DRP[165] bit 13	MAIN[9][31][46]
DRP[165] bit 14	MAIN[9][30][47]
DRP[165] bit 15	MAIN[9][31][47]
DRP[166] bit 0	MAIN[9][30][48]
DRP[166] bit 1	MAIN[9][31][48]
DRP[166] bit 2	MAIN[9][30][49]
DRP[166] bit 3	MAIN[9][31][49]
DRP[166] bit 4	MAIN[9][30][50]
DRP[166] bit 5	MAIN[9][31][50]
DRP[166] bit 6	MAIN[9][30][51]
DRP[166] bit 7	MAIN[9][31][51]
DRP[166] bit 8	MAIN[9][30][52]
DRP[166] bit 9	MAIN[9][31][52]
DRP[166] bit 10	MAIN[9][30][53]
DRP[166] bit 11	MAIN[9][31][53]
DRP[166] bit 12	MAIN[9][30][54]
DRP[166] bit 13	MAIN[9][31][54]
DRP[166] bit 14	MAIN[9][30][55]
DRP[166] bit 15	MAIN[9][31][55]
DRP[167] bit 0	MAIN[9][30][56]
DRP[167] bit 1	MAIN[9][31][56]
DRP[167] bit 2	MAIN[9][30][57]
DRP[167] bit 3	MAIN[9][31][57]
DRP[167] bit 4	MAIN[9][30][58]
DRP[167] bit 5	MAIN[9][31][58]
DRP[167] bit 6	MAIN[9][30][59]
DRP[167] bit 7	MAIN[9][31][59]
DRP[167] bit 8	MAIN[9][30][60]
DRP[167] bit 9	MAIN[9][31][60]
DRP[167] bit 10	MAIN[9][30][61]
DRP[167] bit 11	MAIN[9][31][61]
DRP[167] bit 12	MAIN[9][30][62]
DRP[167] bit 13	MAIN[9][31][62]
DRP[167] bit 14	MAIN[9][30][63]
DRP[167] bit 15	MAIN[9][31][63]
DRP[168] bit 0	MAIN[10][30][0]
DRP[168] bit 1	MAIN[10][31][0]
DRP[168] bit 2	MAIN[10][30][1]
DRP[168] bit 3	MAIN[10][31][1]
DRP[168] bit 4	MAIN[10][30][2]
DRP[168] bit 5	MAIN[10][31][2]
DRP[168] bit 6	MAIN[10][30][3]
DRP[168] bit 7	MAIN[10][31][3]
DRP[168] bit 8	MAIN[10][30][4]
DRP[168] bit 9	MAIN[10][31][4]
DRP[168] bit 10	MAIN[10][30][5]
DRP[168] bit 11	MAIN[10][31][5]
DRP[168] bit 12	MAIN[10][30][6]
DRP[168] bit 13	MAIN[10][31][6]
DRP[168] bit 14	MAIN[10][30][7]
DRP[168] bit 15	MAIN[10][31][7]
DRP[169] bit 0	MAIN[10][30][8]
DRP[169] bit 1	MAIN[10][31][8]
DRP[169] bit 2	MAIN[10][30][9]
DRP[169] bit 3	MAIN[10][31][9]
DRP[169] bit 4	MAIN[10][30][10]
DRP[169] bit 5	MAIN[10][31][10]
DRP[169] bit 6	MAIN[10][30][11]
DRP[169] bit 7	MAIN[10][31][11]
DRP[169] bit 8	MAIN[10][30][12]
DRP[169] bit 9	MAIN[10][31][12]
DRP[169] bit 10	MAIN[10][30][13]
DRP[169] bit 11	MAIN[10][31][13]
DRP[169] bit 12	MAIN[10][30][14]
DRP[169] bit 13	MAIN[10][31][14]
DRP[169] bit 14	MAIN[10][30][15]
DRP[169] bit 15	MAIN[10][31][15]
DRP[170] bit 0	MAIN[10][30][16]
DRP[170] bit 1	MAIN[10][31][16]
DRP[170] bit 2	MAIN[10][30][17]
DRP[170] bit 3	MAIN[10][31][17]
DRP[170] bit 4	MAIN[10][30][18]
DRP[170] bit 5	MAIN[10][31][18]
DRP[170] bit 6	MAIN[10][30][19]
DRP[170] bit 7	MAIN[10][31][19]
DRP[170] bit 8	MAIN[10][30][20]
DRP[170] bit 9	MAIN[10][31][20]
DRP[170] bit 10	MAIN[10][30][21]
DRP[170] bit 11	MAIN[10][31][21]
DRP[170] bit 12	MAIN[10][30][22]
DRP[170] bit 13	MAIN[10][31][22]
DRP[170] bit 14	MAIN[10][30][23]
DRP[170] bit 15	MAIN[10][31][23]
DRP[171] bit 0	MAIN[10][30][24]
DRP[171] bit 1	MAIN[10][31][24]
DRP[171] bit 2	MAIN[10][30][25]
DRP[171] bit 3	MAIN[10][31][25]
DRP[171] bit 4	MAIN[10][30][26]
DRP[171] bit 5	MAIN[10][31][26]
DRP[171] bit 6	MAIN[10][30][27]
DRP[171] bit 7	MAIN[10][31][27]
DRP[171] bit 8	MAIN[10][30][28]
DRP[171] bit 9	MAIN[10][31][28]
DRP[171] bit 10	MAIN[10][30][29]
DRP[171] bit 11	MAIN[10][31][29]
DRP[171] bit 12	MAIN[10][30][30]
DRP[171] bit 13	MAIN[10][31][30]
DRP[171] bit 14	MAIN[10][30][31]
DRP[171] bit 15	MAIN[10][31][31]
DRP[172] bit 0	MAIN[10][30][32]
DRP[172] bit 1	MAIN[10][31][32]
DRP[172] bit 2	MAIN[10][30][33]
DRP[172] bit 3	MAIN[10][31][33]
DRP[172] bit 4	MAIN[10][30][34]
DRP[172] bit 5	MAIN[10][31][34]
DRP[172] bit 6	MAIN[10][30][35]
DRP[172] bit 7	MAIN[10][31][35]
DRP[172] bit 8	MAIN[10][30][36]
DRP[172] bit 9	MAIN[10][31][36]
DRP[172] bit 10	MAIN[10][30][37]
DRP[172] bit 11	MAIN[10][31][37]
DRP[172] bit 12	MAIN[10][30][38]
DRP[172] bit 13	MAIN[10][31][38]
DRP[172] bit 14	MAIN[10][30][39]
DRP[172] bit 15	MAIN[10][31][39]
DRP[173] bit 0	MAIN[10][30][40]
DRP[173] bit 1	MAIN[10][31][40]
DRP[173] bit 2	MAIN[10][30][41]
DRP[173] bit 3	MAIN[10][31][41]
DRP[173] bit 4	MAIN[10][30][42]
DRP[173] bit 5	MAIN[10][31][42]
DRP[173] bit 6	MAIN[10][30][43]
DRP[173] bit 7	MAIN[10][31][43]
DRP[173] bit 8	MAIN[10][30][44]
DRP[173] bit 9	MAIN[10][31][44]
DRP[173] bit 10	MAIN[10][30][45]
DRP[173] bit 11	MAIN[10][31][45]
DRP[173] bit 12	MAIN[10][30][46]
DRP[173] bit 13	MAIN[10][31][46]
DRP[173] bit 14	MAIN[10][30][47]
DRP[173] bit 15	MAIN[10][31][47]
DRP[174] bit 0	MAIN[10][30][48]
DRP[174] bit 1	MAIN[10][31][48]
DRP[174] bit 2	MAIN[10][30][49]
DRP[174] bit 3	MAIN[10][31][49]
DRP[174] bit 4	MAIN[10][30][50]
DRP[174] bit 5	MAIN[10][31][50]
DRP[174] bit 6	MAIN[10][30][51]
DRP[174] bit 7	MAIN[10][31][51]
DRP[174] bit 8	MAIN[10][30][52]
DRP[174] bit 9	MAIN[10][31][52]
DRP[174] bit 10	MAIN[10][30][53]
DRP[174] bit 11	MAIN[10][31][53]
DRP[174] bit 12	MAIN[10][30][54]
DRP[174] bit 13	MAIN[10][31][54]
DRP[174] bit 14	MAIN[10][30][55]
DRP[174] bit 15	MAIN[10][31][55]
DRP[175] bit 0	MAIN[10][30][56]
DRP[175] bit 1	MAIN[10][31][56]
DRP[175] bit 2	MAIN[10][30][57]
DRP[175] bit 3	MAIN[10][31][57]
DRP[175] bit 4	MAIN[10][30][58]
DRP[175] bit 5	MAIN[10][31][58]
DRP[175] bit 6	MAIN[10][30][59]
DRP[175] bit 7	MAIN[10][31][59]
DRP[175] bit 8	MAIN[10][30][60]
DRP[175] bit 9	MAIN[10][31][60]
DRP[175] bit 10	MAIN[10][30][61]
DRP[175] bit 11	MAIN[10][31][61]
DRP[175] bit 12	MAIN[10][30][62]
DRP[175] bit 13	MAIN[10][31][62]
DRP[175] bit 14	MAIN[10][30][63]
DRP[175] bit 15	MAIN[10][31][63]
CPLLREFCLKSEL_STATIC_VAL	[enum: GTX_COMMON_PLLREFCLKSEL]
CPLLREFCLKSEL_MODE_DYNAMIC	MAIN[0][31][54]
ALIGN_COMMA_DOUBLE	MAIN[8][28][10]
ALIGN_MCOMMA_DET	MAIN[8][28][11]
ALIGN_PCOMMA_DET	MAIN[8][29][11]
CHAN_BOND_KEEP_ALIGN	MAIN[9][29][55]
CHAN_BOND_SEQ_2_USE	MAIN[10][29][5]
CLK_COR_INSERT_IDLE_FLAG	MAIN[9][28][15]
CLK_COR_KEEP_IDLE	MAIN[9][29][14]
CLK_COR_PRECEDENCE	MAIN[9][28][14]
CLK_COR_SEQ_2_USE	MAIN[9][28][7]
CLK_CORRECT_USE	MAIN[8][28][39]
DEC_MCOMMA_DETECT	MAIN[7][29][46]
DEC_PCOMMA_DETECT	MAIN[7][28][47]
DEC_VALID_COMMA_ONLY	MAIN[7][28][46]
ES_ERRDET_EN	MAIN[7][29][44]
ES_EYE_SCAN_EN	MAIN[7][28][44]
FTS_LANE_DESKEW_EN	MAIN[10][29][13]
GEN_RXUSRCLK	MAIN[0][28][1]
GEN_TXUSRCLK	MAIN[0][29][1]
PCS_PCIE_EN	MAIN[3][28][24]
RXBUF_EN	MAIN[8][31][40]
RXBUF_RESET_ON_CB_CHANGE	MAIN[8][31][42]
RXBUF_RESET_ON_COMMAALIGN	MAIN[8][31][41]
RXBUF_RESET_ON_EIDLE	MAIN[8][30][43]
RXBUF_RESET_ON_RATE_CHANGE	MAIN[8][30][42]
RXBUF_THRESH_OVRD	MAIN[8][30][41]
RX_DEFER_RESET_BUF_EN	MAIN[8][30][40]
RX_DISPERR_SEQ_MATCH	MAIN[7][29][47]
RXGEARBOX_EN	MAIN[9][29][31]
SHOW_REALIGN_COMMA	MAIN[8][29][10]
TXBUF_EN	MAIN[3][28][39]
TXBUF_RESET_ON_RATE_CHANGE	MAIN[3][29][39]
TXGEARBOX_EN	MAIN[3][29][34]
TX_LOOPBACK_DRIVE_HIZ	MAIN[3][29][10]
ALIGN_COMMA_WORD	[enum: GT11_ALIGN_COMMA_WORD]
CBCC_DATA_SOURCE_SEL	[enum: GTP_CHANNEL_CBCC_DATA_SOURCE_SEL]
CHAN_BOND_SEQ_LEN	[enum: GTP_SEQ_LEN]
CLK_COR_SEQ_LEN	[enum: GTP_SEQ_LEN]
CPLL_FBDIV	[enum: GTP_PLL_DIVSEL_REF]
CPLL_FBDIV_45	[enum: GTX_PLL_DIVSEL45_FB]
CPLL_REFCLK_DIV	[enum: GTP_PLL_DIVSEL_REF]
RXBUF_ADDR_MODE	[enum: GTX_RX_FIFO_ADDR_MODE]
RXOUT_DIV	[enum: GTP_CHANNEL_CLKOUT_DIV]
RX_DATA_WIDTH	[enum: GTX_CHANNEL_DATA_WIDTH]
RX_XCLK_SEL	[enum: GTP_RX_XCLK_SEL]
RXPLL_SEL	[enum: GTX_CHANNEL_PLL_SEL]
RXSIPO_DIV_45	[enum: GTX_PLL_DIVSEL45_FB]
RXSLIDE_MODE	[enum: GTX_RX_SLIDE_MODE]
SATA_CPLL_CFG	[enum: GTP_CHANNEL_SATA_PLL_CFG]
TX_DATA_WIDTH	[enum: GTX_CHANNEL_DATA_WIDTH]
TX_DRIVE_MODE	[enum: GTP_CHANNEL_TX_DRIVE_MODE]
TXOUT_DIV	[enum: GTP_CHANNEL_CLKOUT_DIV]
TX_XCLK_SEL	[enum: GTP_TX_XCLK_SEL]
TXPISO_DIV_45	[enum: GTX_PLL_DIVSEL45_FB]
TXPLL_SEL	[enum: GTX_CHANNEL_PLL_SEL]
TXPI_PPMCLK_SEL	[enum: GTP_CHANNEL_TXPI_PPMCLK_SEL]
RXOOB_CLK_CFG	[enum: GTP_CHANNEL_RXOOB_CLK_CFG]
CHAN_BOND_MAX_SKEW bit 0	MAIN[10][28][30]
CHAN_BOND_MAX_SKEW bit 1	MAIN[10][29][30]
CHAN_BOND_MAX_SKEW bit 2	MAIN[10][28][31]
CHAN_BOND_MAX_SKEW bit 3	MAIN[10][29][31]
CLK_COR_MAX_LAT bit 0	MAIN[8][28][45]
CLK_COR_MAX_LAT bit 1	MAIN[8][29][45]
CLK_COR_MAX_LAT bit 2	MAIN[8][28][46]
CLK_COR_MAX_LAT bit 3	MAIN[8][29][46]
CLK_COR_MAX_LAT bit 4	MAIN[8][28][47]
CLK_COR_MAX_LAT bit 5	MAIN[8][29][47]
CLK_COR_MIN_LAT bit 0	MAIN[8][28][53]
CLK_COR_MIN_LAT bit 1	MAIN[8][29][53]
CLK_COR_MIN_LAT bit 2	MAIN[8][28][54]
CLK_COR_MIN_LAT bit 3	MAIN[8][29][54]
CLK_COR_MIN_LAT bit 4	MAIN[8][28][55]
CLK_COR_MIN_LAT bit 5	MAIN[8][29][55]
RX_CLK25_DIV bit 0	MAIN[2][28][11]
RX_CLK25_DIV bit 1	MAIN[2][29][11]
RX_CLK25_DIV bit 2	MAIN[2][28][12]
RX_CLK25_DIV bit 3	MAIN[2][29][12]
RX_CLK25_DIV bit 4	MAIN[2][28][13]
RX_SIG_VALID_DLY bit 0	MAIN[8][28][12]
RX_SIG_VALID_DLY bit 1	MAIN[8][29][12]
RX_SIG_VALID_DLY bit 2	MAIN[8][28][13]
RX_SIG_VALID_DLY bit 3	MAIN[8][29][13]
RX_SIG_VALID_DLY bit 4	MAIN[8][28][14]
SAS_MAX_COM bit 0	MAIN[2][28][43]
SAS_MAX_COM bit 1	MAIN[2][29][43]
SAS_MAX_COM bit 2	MAIN[2][28][44]
SAS_MAX_COM bit 3	MAIN[2][29][44]
SAS_MAX_COM bit 4	MAIN[2][28][45]
SAS_MAX_COM bit 5	MAIN[2][29][45]
SAS_MAX_COM bit 6	MAIN[2][28][46]
SAS_MIN_COM bit 0	MAIN[2][29][28]
SAS_MIN_COM bit 1	MAIN[2][28][29]
SAS_MIN_COM bit 2	MAIN[2][29][29]
SAS_MIN_COM bit 3	MAIN[2][28][30]
SAS_MIN_COM bit 4	MAIN[2][29][30]
SAS_MIN_COM bit 5	MAIN[2][28][31]
SATA_MAX_BURST bit 0	MAIN[2][28][40]
SATA_MAX_BURST bit 1	MAIN[2][29][40]
SATA_MAX_BURST bit 2	MAIN[2][28][41]
SATA_MAX_BURST bit 3	MAIN[2][29][41]
SATA_MAX_BURST bit 4	MAIN[2][28][42]
SATA_MAX_BURST bit 5	MAIN[2][29][42]
SATA_MAX_INIT bit 0	MAIN[2][28][48]
SATA_MAX_INIT bit 1	MAIN[2][29][48]
SATA_MAX_INIT bit 2	MAIN[2][28][49]
SATA_MAX_INIT bit 3	MAIN[2][29][49]
SATA_MAX_INIT bit 4	MAIN[2][28][50]
SATA_MAX_INIT bit 5	MAIN[2][29][50]
SATA_MAX_WAKE bit 0	MAIN[2][28][51]
SATA_MAX_WAKE bit 1	MAIN[2][29][51]
SATA_MAX_WAKE bit 2	MAIN[2][28][52]
SATA_MAX_WAKE bit 3	MAIN[2][29][52]
SATA_MAX_WAKE bit 4	MAIN[2][28][53]
SATA_MAX_WAKE bit 5	MAIN[2][29][53]
SATA_MIN_BURST bit 0	MAIN[2][29][25]
SATA_MIN_BURST bit 1	MAIN[2][28][26]
SATA_MIN_BURST bit 2	MAIN[2][29][26]
SATA_MIN_BURST bit 3	MAIN[2][28][27]
SATA_MIN_BURST bit 4	MAIN[2][29][27]
SATA_MIN_BURST bit 5	MAIN[2][28][28]
SATA_MIN_INIT bit 0	MAIN[2][28][32]
SATA_MIN_INIT bit 1	MAIN[2][29][32]
SATA_MIN_INIT bit 2	MAIN[2][28][33]
SATA_MIN_INIT bit 3	MAIN[2][29][33]
SATA_MIN_INIT bit 4	MAIN[2][28][34]
SATA_MIN_INIT bit 5	MAIN[2][29][34]
SATA_MIN_WAKE bit 0	MAIN[2][28][35]
SATA_MIN_WAKE bit 1	MAIN[2][29][35]
SATA_MIN_WAKE bit 2	MAIN[2][28][36]
SATA_MIN_WAKE bit 3	MAIN[2][29][36]
SATA_MIN_WAKE bit 4	MAIN[2][28][37]
SATA_MIN_WAKE bit 5	MAIN[2][29][37]
TX_CLK25_DIV bit 0	MAIN[2][30][16]
TX_CLK25_DIV bit 1	MAIN[2][31][16]
TX_CLK25_DIV bit 2	MAIN[2][30][17]
TX_CLK25_DIV bit 3	MAIN[2][31][17]
TX_CLK25_DIV bit 4	MAIN[2][30][18]
CLK_COR_REPEAT_WAIT bit 0	MAIN[8][28][61]
CLK_COR_REPEAT_WAIT bit 1	MAIN[8][29][61]
CLK_COR_REPEAT_WAIT bit 2	MAIN[8][28][62]
CLK_COR_REPEAT_WAIT bit 3	MAIN[8][29][62]
CLK_COR_REPEAT_WAIT bit 4	MAIN[8][28][63]
RXBUF_THRESH_OVFLW bit 0	MAIN[8][30][36]
RXBUF_THRESH_OVFLW bit 1	MAIN[8][31][36]
RXBUF_THRESH_OVFLW bit 2	MAIN[8][30][37]
RXBUF_THRESH_OVFLW bit 3	MAIN[8][31][37]
RXBUF_THRESH_OVFLW bit 4	MAIN[8][30][38]
RXBUF_THRESH_OVFLW bit 5	MAIN[8][31][38]
RXBUF_THRESH_UNDFLW bit 0	MAIN[8][30][32]
RXBUF_THRESH_UNDFLW bit 1	MAIN[8][31][32]
RXBUF_THRESH_UNDFLW bit 2	MAIN[8][30][33]
RXBUF_THRESH_UNDFLW bit 3	MAIN[8][31][33]
RXBUF_THRESH_UNDFLW bit 4	MAIN[8][30][34]
RXBUF_THRESH_UNDFLW bit 5	MAIN[8][31][34]
RXSLIDE_AUTO_WAIT bit 0	MAIN[8][28][8]
RXSLIDE_AUTO_WAIT bit 1	MAIN[8][29][8]
RXSLIDE_AUTO_WAIT bit 2	MAIN[8][28][9]
RXSLIDE_AUTO_WAIT bit 3	MAIN[8][29][9]
RX_INT_DATAWIDTH bit 0	MAIN[2][28][15]
TXOUTCLKPCS_SEL bit 0	MAIN[0][30][12]
TX_INT_DATAWIDTH bit 0	MAIN[2][30][26]
ACJTAG_DEBUG_MODE bit 0	MAIN[0][28][7]
ACJTAG_MODE bit 0	MAIN[0][29][6]
ACJTAG_RESET bit 0	MAIN[0][29][7]
AEN_CPLL bit 0	MAIN[1][28][25]
AEN_LOOPBACK bit 0	MAIN[1][28][26]
AEN_MASTER bit 0	MAIN[1][28][27]
AEN_PD_AND_EIDLE bit 0	MAIN[1][28][28]
AEN_POLARITY bit 0	MAIN[1][28][29]
AEN_PRBS bit 0	MAIN[1][29][29]
AEN_QPI bit 0	MAIN[1][28][30]
AEN_RESET bit 0	MAIN[1][29][30]
AEN_RXCDR bit 0	MAIN[1][29][24]
AEN_RXDFE bit 0	MAIN[1][29][25]
AEN_RXDFELPM bit 0	MAIN[1][29][26]
AEN_RXOUTCLK_SEL bit 0	MAIN[1][28][31]
AEN_RXPHDLY bit 0	MAIN[1][28][34]
AEN_RXSYSCLK_SEL bit 0	MAIN[1][29][31]
AEN_TXOUTCLK_SEL bit 0	MAIN[1][28][33]
AEN_TXPHDLY bit 0	MAIN[1][28][32]
AEN_TXSYSCLK_SEL bit 0	MAIN[1][29][33]
AEN_TX_DRIVE_MODE bit 0	MAIN[1][29][32]
AEN_TXPI_PPM bit 0	MAIN[7][30][52]
ALIGN_COMMA_ENABLE bit 0	MAIN[7][28][48]
ALIGN_COMMA_ENABLE bit 1	MAIN[7][29][48]
ALIGN_COMMA_ENABLE bit 2	MAIN[7][28][49]
ALIGN_COMMA_ENABLE bit 3	MAIN[7][29][49]
ALIGN_COMMA_ENABLE bit 4	MAIN[7][28][50]
ALIGN_COMMA_ENABLE bit 5	MAIN[7][29][50]
ALIGN_COMMA_ENABLE bit 6	MAIN[7][28][51]
ALIGN_COMMA_ENABLE bit 7	MAIN[7][29][51]
ALIGN_COMMA_ENABLE bit 8	MAIN[7][28][52]
ALIGN_COMMA_ENABLE bit 9	MAIN[7][29][52]
ALIGN_MCOMMA_VALUE bit 0	MAIN[7][28][56]
ALIGN_MCOMMA_VALUE bit 1	MAIN[7][29][56]
ALIGN_MCOMMA_VALUE bit 2	MAIN[7][28][57]
ALIGN_MCOMMA_VALUE bit 3	MAIN[7][29][57]
ALIGN_MCOMMA_VALUE bit 4	MAIN[7][28][58]
ALIGN_MCOMMA_VALUE bit 5	MAIN[7][29][58]
ALIGN_MCOMMA_VALUE bit 6	MAIN[7][28][59]
ALIGN_MCOMMA_VALUE bit 7	MAIN[7][29][59]
ALIGN_MCOMMA_VALUE bit 8	MAIN[7][28][60]
ALIGN_MCOMMA_VALUE bit 9	MAIN[7][29][60]
ALIGN_PCOMMA_VALUE bit 0	MAIN[8][28][0]
ALIGN_PCOMMA_VALUE bit 1	MAIN[8][29][0]
ALIGN_PCOMMA_VALUE bit 2	MAIN[8][28][1]
ALIGN_PCOMMA_VALUE bit 3	MAIN[8][29][1]
ALIGN_PCOMMA_VALUE bit 4	MAIN[8][28][2]
ALIGN_PCOMMA_VALUE bit 5	MAIN[8][29][2]
ALIGN_PCOMMA_VALUE bit 6	MAIN[8][28][3]
ALIGN_PCOMMA_VALUE bit 7	MAIN[8][29][3]
ALIGN_PCOMMA_VALUE bit 8	MAIN[8][28][4]
ALIGN_PCOMMA_VALUE bit 9	MAIN[8][29][4]
A_CFGRESET bit 0	MAIN[0][29][18]
A_CPLLLOCKEN bit 0	MAIN[0][28][19]
A_CPLLPD bit 0	MAIN[0][29][19]
A_CPLLRESET bit 0	MAIN[0][28][20]
A_EYESCANMODE bit 0	MAIN[0][29][33]
A_EYESCANRESET bit 0	MAIN[0][28][33]
A_GTRESETSEL bit 0	MAIN[0][29][43]
A_GTRXRESET bit 0	MAIN[0][28][32]
A_GTTXRESET bit 0	MAIN[0][29][32]
A_LOOPBACK bit 0	MAIN[0][28][34]
A_LOOPBACK bit 1	MAIN[0][29][34]
A_LOOPBACK bit 2	MAIN[0][28][35]
A_RXADAPTSELTEST bit 0	MAIN[2][30][40]
A_RXADAPTSELTEST bit 1	MAIN[2][31][40]
A_RXADAPTSELTEST bit 2	MAIN[2][30][41]
A_RXADAPTSELTEST bit 3	MAIN[2][31][41]
A_RXADAPTSELTEST bit 4	MAIN[2][30][42]
A_RXADAPTSELTEST bit 5	MAIN[2][31][42]
A_RXADAPTSELTEST bit 6	MAIN[2][30][43]
A_RXADAPTSELTEST bit 7	MAIN[2][31][43]
A_RXADAPTSELTEST bit 8	MAIN[2][30][44]
A_RXADAPTSELTEST bit 9	MAIN[2][31][44]
A_RXADAPTSELTEST bit 10	MAIN[2][30][45]
A_RXADAPTSELTEST bit 11	MAIN[2][31][45]
A_RXADAPTSELTEST bit 12	MAIN[2][30][46]
A_RXADAPTSELTEST bit 13	MAIN[2][31][46]
A_RXBUFRESET bit 0	MAIN[0][29][41]
A_RXCDRFREQRESET bit 0	MAIN[0][29][16]
A_RXCDRHOLD bit 0	MAIN[0][28][17]
A_RXCDROVRDEN bit 0	MAIN[1][29][17]
A_RXCDRRESET bit 0	MAIN[0][29][17]
A_RXCDRRESETRSV bit 0	MAIN[0][28][18]
A_RXDFEAGCHOLD bit 0	MAIN[0][29][20]
A_RXDFEAGCOVRDEN bit 0	MAIN[0][28][21]
A_RXDFECM1EN bit 0	MAIN[0][29][31]
A_RXDFELFHOLD bit 0	MAIN[0][29][25]
A_RXDFELFOVRDEN bit 0	MAIN[0][28][26]
A_RXDFELPMRESET bit 0	MAIN[0][29][27]
A_RXDFEUTHOLD bit 0	MAIN[0][28][28]
A_RXDFEUTOVRDEN bit 0	MAIN[0][29][28]
A_RXDFEVPHOLD bit 0	MAIN[0][28][29]
A_RXDFEVPOVRDEN bit 0	MAIN[0][29][29]
A_RXDFEVSEN bit 0	MAIN[1][28][18]
A_RXDFEXYDEN bit 0	MAIN[0][28][31]
A_RXDFETAP2HOLD bit 0	MAIN[0][29][21]
A_RXDFETAP2OVRDEN bit 0	MAIN[0][28][22]
A_RXDFETAP3HOLD bit 0	MAIN[0][29][22]
A_RXDFETAP3OVRDEN bit 0	MAIN[0][28][23]
A_RXDFETAP4HOLD bit 0	MAIN[0][29][23]
A_RXDFETAP4OVRDEN bit 0	MAIN[0][28][24]
A_RXDFETAP5HOLD bit 0	MAIN[0][29][24]
A_RXDFETAP5OVRDEN bit 0	MAIN[0][28][25]
A_RXDFETAP6HOLD bit 0	MAIN[2][31][47]
A_RXDFETAP6OVRDEN bit 0	MAIN[2][30][47]
A_RXDFETAP7HOLD bit 0	MAIN[2][31][55]
A_RXDFETAP7OVRDEN bit 0	MAIN[2][30][55]
A_RXDFEAGCTRL bit 0	MAIN[2][31][50]
A_RXDFEAGCTRL bit 1	MAIN[2][30][51]
A_RXDFEAGCTRL bit 2	MAIN[2][31][51]
A_RXDFEAGCTRL bit 3	MAIN[2][30][52]
A_RXDFEAGCTRL bit 4	MAIN[2][31][52]
A_RXDFESLIDETAP bit 0	MAIN[2][30][48]
A_RXDFESLIDETAP bit 1	MAIN[2][31][48]
A_RXDFESLIDETAP bit 2	MAIN[2][30][49]
A_RXDFESLIDETAP bit 3	MAIN[2][31][49]
A_RXDFESLIDETAP bit 4	MAIN[2][30][50]
A_RXDFESLIDETAPADAPTEN bit 0	MAIN[1][29][1]
A_RXDFESLIDETAPHOLD bit 0	MAIN[1][28][2]
A_RXDFESLIDETAPID bit 0	MAIN[1][28][19]
A_RXDFESLIDETAPID bit 1	MAIN[1][29][19]
A_RXDFESLIDETAPID bit 2	MAIN[1][28][20]
A_RXDFESLIDETAPID bit 3	MAIN[1][29][20]
A_RXDFESLIDETAPID bit 4	MAIN[1][28][21]
A_RXDFESLIDETAPID bit 5	MAIN[1][29][21]
A_RXDFESLIDETAPINITOVRDEN bit 0	MAIN[2][30][35]
A_RXDFESLIDETAPONLYADAPTEN bit 0	MAIN[1][28][1]
A_RXDFESLIDETAPOVRDEN bit 0	MAIN[0][28][30]
A_RXDFESLIDETAPSTROBE bit 0	MAIN[0][29][30]
A_RXDLYBYPASS bit 0	MAIN[0][28][38]
A_RXDLYEN bit 0	MAIN[0][29][39]
A_RXDLYOVRDEN bit 0	MAIN[0][29][38]
A_RXDLYSRESET bit 0	MAIN[0][28][41]
A_RXLPMEN bit 0	MAIN[0][28][43]
A_RXLPMHFHOLD bit 0	MAIN[0][29][35]
A_RXLPMHFOVRDEN bit 0	MAIN[0][28][36]
A_RXLPMLFHOLD bit 0	MAIN[0][29][36]
A_RXLPMLFKLOVRDEN bit 0	MAIN[0][28][37]
A_RXMONITORSEL bit 0	MAIN[1][29][16]
A_RXMONITORSEL bit 1	MAIN[1][28][17]
A_RXOOBRESET bit 0	MAIN[0][28][44]
A_RXOSHOLD bit 0	MAIN[0][29][26]
A_RXOSOVRDEN bit 0	MAIN[0][28][27]
A_RXOSCALRESET bit 0	MAIN[1][29][18]
A_RXOSINTCFG bit 0	MAIN[1][28][22]
A_RXOSINTCFG bit 1	MAIN[1][29][22]
A_RXOSINTCFG bit 2	MAIN[1][28][23]
A_RXOSINTCFG bit 3	MAIN[1][29][23]
A_RXOSINTEN bit 0	MAIN[2][31][34]
A_RXOSINTHOLD bit 0	MAIN[2][31][32]
A_RXOSINTID0 bit 0	MAIN[2][30][53]
A_RXOSINTID0 bit 1	MAIN[2][31][53]
A_RXOSINTID0 bit 2	MAIN[2][30][54]
A_RXOSINTID0 bit 3	MAIN[2][31][54]
A_RXOSINTNTRLEN bit 0	MAIN[2][30][34]
A_RXOSINTOVRDEN bit 0	MAIN[2][31][33]
A_RXOSINTSTROBE bit 0	MAIN[2][30][33]
A_RXOSINTTESTOVRDEN bit 0	MAIN[2][30][32]
A_RXOUTCLKSEL bit 0	MAIN[0][29][44]
A_RXOUTCLKSEL bit 1	MAIN[0][28][45]
A_RXOUTCLKSEL bit 2	MAIN[0][29][45]
A_RXPCSRESET bit 0	MAIN[0][29][49]
A_RXPD bit 0	MAIN[0][28][47]
A_RXPD bit 1	MAIN[0][29][47]
A_RXPHALIGN bit 0	MAIN[0][29][42]
A_RXPHALIGNEN bit 0	MAIN[0][28][42]
A_RXPHDLYPD bit 0	MAIN[0][29][40]
A_RXPHDLYRESET bit 0	MAIN[0][28][39]
A_RXPHOVRDEN bit 0	MAIN[0][28][40]
A_RXPMARESET bit 0	MAIN[0][28][46]
A_RXPOLARITY bit 0	MAIN[0][29][46]
A_RXPRBSCNTRESET bit 0	MAIN[0][29][37]
A_RXPRBSSEL bit 0	MAIN[0][28][48]
A_RXPRBSSEL bit 1	MAIN[0][29][48]
A_RXPRBSSEL bit 2	MAIN[0][28][49]
A_RXSYSCLKSEL bit 0	MAIN[0][28][50]
A_RXSYSCLKSEL bit 1	MAIN[0][29][50]
A_SPARE bit 0	MAIN[0][29][63]
A_TXBUFDIFFCTRL bit 0	MAIN[1][28][11]
A_TXBUFDIFFCTRL bit 1	MAIN[1][29][11]
A_TXBUFDIFFCTRL bit 2	MAIN[1][28][12]
A_TXDEEMPH bit 0	MAIN[0][28][56]
A_TXDIFFCTRL bit 0	MAIN[0][29][56]
A_TXDIFFCTRL bit 1	MAIN[0][28][57]
A_TXDIFFCTRL bit 2	MAIN[0][29][57]
A_TXDIFFCTRL bit 3	MAIN[0][28][58]
A_TXDLYBYPASS bit 0	MAIN[0][28][51]
A_TXDLYEN bit 0	MAIN[0][29][54]
A_TXDLYOVRDEN bit 0	MAIN[0][29][51]
A_TXDLYSRESET bit 0	MAIN[0][28][54]
A_TXELECIDLE bit 0	MAIN[0][29][58]
A_TXINHIBIT bit 0	MAIN[0][28][16]
A_TXMAINCURSOR bit 0	MAIN[0][28][60]
A_TXMAINCURSOR bit 1	MAIN[0][29][60]
A_TXMAINCURSOR bit 2	MAIN[0][28][61]
A_TXMAINCURSOR bit 3	MAIN[0][29][61]
A_TXMAINCURSOR bit 4	MAIN[0][28][62]
A_TXMAINCURSOR bit 5	MAIN[0][29][62]
A_TXMAINCURSOR bit 6	MAIN[0][28][63]
A_TXMARGIN bit 0	MAIN[1][28][5]
A_TXMARGIN bit 1	MAIN[1][29][5]
A_TXMARGIN bit 2	MAIN[1][28][6]
A_TXOUTCLKSEL bit 0	MAIN[1][29][6]
A_TXOUTCLKSEL bit 1	MAIN[1][28][7]
A_TXOUTCLKSEL bit 2	MAIN[1][29][7]
A_TXPCSRESET bit 0	MAIN[1][29][13]
A_TXPD bit 0	MAIN[1][29][12]
A_TXPD bit 1	MAIN[1][28][13]
A_TXPHALIGN bit 0	MAIN[0][29][55]
A_TXPHALIGNEN bit 0	MAIN[0][28][55]
A_TXPHDLYPD bit 0	MAIN[0][29][53]
A_TXPHDLYRESET bit 0	MAIN[0][28][52]
A_TXPHINIT bit 0	MAIN[0][29][52]
A_TXPHOVRDEN bit 0	MAIN[0][28][53]
A_TXPIPPMOVRDEN bit 0	MAIN[7][31][51]
A_TXPIPPMPD bit 0	MAIN[7][31][55]
A_TXPIPPMSEL bit 0	MAIN[7][31][52]
A_TXPMARESET bit 0	MAIN[1][28][8]
A_TXPOLARITY bit 0	MAIN[1][29][8]
A_TXPOSTCURSOR bit 0	MAIN[3][28][5]
A_TXPOSTCURSOR bit 1	MAIN[3][29][5]
A_TXPOSTCURSOR bit 2	MAIN[3][28][6]
A_TXPOSTCURSOR bit 3	MAIN[3][29][6]
A_TXPOSTCURSOR bit 4	MAIN[3][28][7]
A_TXPOSTCURSORINV bit 0	MAIN[0][28][59]
A_TXPRBSFORCEERR bit 0	MAIN[1][28][9]
A_TXPRBSSEL bit 0	MAIN[1][29][9]
A_TXPRBSSEL bit 1	MAIN[1][28][10]
A_TXPRBSSEL bit 2	MAIN[1][29][10]
A_TXPRECURSOR bit 0	MAIN[1][29][2]
A_TXPRECURSOR bit 1	MAIN[1][28][3]
A_TXPRECURSOR bit 2	MAIN[1][29][3]
A_TXPRECURSOR bit 3	MAIN[1][28][4]
A_TXPRECURSOR bit 4	MAIN[1][29][4]
A_TXPRECURSORINV bit 0	MAIN[0][29][59]
A_TXSWING bit 0	MAIN[1][28][14]
A_TXSYSCLKSEL bit 0	MAIN[1][29][14]
A_TXSYSCLKSEL bit 1	MAIN[1][28][15]
A_TXQPIBIASEN bit 0	MAIN[10][30][46]
CFOK_CFG2 bit 0	MAIN[7][30][11]
CFOK_CFG2 bit 1	MAIN[7][31][11]
CFOK_CFG2 bit 2	MAIN[7][30][12]
CFOK_CFG2 bit 3	MAIN[7][31][12]
CFOK_CFG2 bit 4	MAIN[7][30][13]
CFOK_CFG2 bit 5	MAIN[7][31][13]
CFOK_CFG3 bit 0	MAIN[6][30][29]
CFOK_CFG3 bit 1	MAIN[6][31][29]
CFOK_CFG3 bit 2	MAIN[6][30][30]
CFOK_CFG3 bit 3	MAIN[6][31][30]
CFOK_CFG3 bit 4	MAIN[6][30][31]
CFOK_CFG3 bit 5	MAIN[6][31][31]
CHAN_BOND_SEQ_1_1 bit 0	MAIN[9][28][32]
CHAN_BOND_SEQ_1_1 bit 1	MAIN[9][29][32]
CHAN_BOND_SEQ_1_1 bit 2	MAIN[9][28][33]
CHAN_BOND_SEQ_1_1 bit 3	MAIN[9][29][33]
CHAN_BOND_SEQ_1_1 bit 4	MAIN[9][28][34]
CHAN_BOND_SEQ_1_1 bit 5	MAIN[9][29][34]
CHAN_BOND_SEQ_1_1 bit 6	MAIN[9][28][35]
CHAN_BOND_SEQ_1_1 bit 7	MAIN[9][29][35]
CHAN_BOND_SEQ_1_1 bit 8	MAIN[9][28][36]
CHAN_BOND_SEQ_1_1 bit 9	MAIN[9][29][36]
CHAN_BOND_SEQ_1_2 bit 0	MAIN[9][28][40]
CHAN_BOND_SEQ_1_2 bit 1	MAIN[9][29][40]
CHAN_BOND_SEQ_1_2 bit 2	MAIN[9][28][41]
CHAN_BOND_SEQ_1_2 bit 3	MAIN[9][29][41]
CHAN_BOND_SEQ_1_2 bit 4	MAIN[9][28][42]
CHAN_BOND_SEQ_1_2 bit 5	MAIN[9][29][42]
CHAN_BOND_SEQ_1_2 bit 6	MAIN[9][28][43]
CHAN_BOND_SEQ_1_2 bit 7	MAIN[9][29][43]
CHAN_BOND_SEQ_1_2 bit 8	MAIN[9][28][44]
CHAN_BOND_SEQ_1_2 bit 9	MAIN[9][29][44]
CHAN_BOND_SEQ_1_3 bit 0	MAIN[9][28][48]
CHAN_BOND_SEQ_1_3 bit 1	MAIN[9][29][48]
CHAN_BOND_SEQ_1_3 bit 2	MAIN[9][28][49]
CHAN_BOND_SEQ_1_3 bit 3	MAIN[9][29][49]
CHAN_BOND_SEQ_1_3 bit 4	MAIN[9][28][50]
CHAN_BOND_SEQ_1_3 bit 5	MAIN[9][29][50]
CHAN_BOND_SEQ_1_3 bit 6	MAIN[9][28][51]
CHAN_BOND_SEQ_1_3 bit 7	MAIN[9][29][51]
CHAN_BOND_SEQ_1_3 bit 8	MAIN[9][28][52]
CHAN_BOND_SEQ_1_3 bit 9	MAIN[9][29][52]
CHAN_BOND_SEQ_1_4 bit 0	MAIN[9][28][56]
CHAN_BOND_SEQ_1_4 bit 1	MAIN[9][29][56]
CHAN_BOND_SEQ_1_4 bit 2	MAIN[9][28][57]
CHAN_BOND_SEQ_1_4 bit 3	MAIN[9][29][57]
CHAN_BOND_SEQ_1_4 bit 4	MAIN[9][28][58]
CHAN_BOND_SEQ_1_4 bit 5	MAIN[9][29][58]
CHAN_BOND_SEQ_1_4 bit 6	MAIN[9][28][59]
CHAN_BOND_SEQ_1_4 bit 7	MAIN[9][29][59]
CHAN_BOND_SEQ_1_4 bit 8	MAIN[9][28][60]
CHAN_BOND_SEQ_1_4 bit 9	MAIN[9][29][60]
CHAN_BOND_SEQ_1_ENABLE bit 0	MAIN[9][28][38]
CHAN_BOND_SEQ_1_ENABLE bit 1	MAIN[9][29][38]
CHAN_BOND_SEQ_1_ENABLE bit 2	MAIN[9][28][39]
CHAN_BOND_SEQ_1_ENABLE bit 3	MAIN[9][29][39]
CHAN_BOND_SEQ_2_1 bit 0	MAIN[10][28][0]
CHAN_BOND_SEQ_2_1 bit 1	MAIN[10][29][0]
CHAN_BOND_SEQ_2_1 bit 2	MAIN[10][28][1]
CHAN_BOND_SEQ_2_1 bit 3	MAIN[10][29][1]
CHAN_BOND_SEQ_2_1 bit 4	MAIN[10][28][2]
CHAN_BOND_SEQ_2_1 bit 5	MAIN[10][29][2]
CHAN_BOND_SEQ_2_1 bit 6	MAIN[10][28][3]
CHAN_BOND_SEQ_2_1 bit 7	MAIN[10][29][3]
CHAN_BOND_SEQ_2_1 bit 8	MAIN[10][28][4]
CHAN_BOND_SEQ_2_1 bit 9	MAIN[10][29][4]
CHAN_BOND_SEQ_2_2 bit 0	MAIN[10][28][8]
CHAN_BOND_SEQ_2_2 bit 1	MAIN[10][29][8]
CHAN_BOND_SEQ_2_2 bit 2	MAIN[10][28][9]
CHAN_BOND_SEQ_2_2 bit 3	MAIN[10][29][9]
CHAN_BOND_SEQ_2_2 bit 4	MAIN[10][28][10]
CHAN_BOND_SEQ_2_2 bit 5	MAIN[10][29][10]
CHAN_BOND_SEQ_2_2 bit 6	MAIN[10][28][11]
CHAN_BOND_SEQ_2_2 bit 7	MAIN[10][29][11]
CHAN_BOND_SEQ_2_2 bit 8	MAIN[10][28][12]
CHAN_BOND_SEQ_2_2 bit 9	MAIN[10][29][12]
CHAN_BOND_SEQ_2_3 bit 0	MAIN[10][28][16]
CHAN_BOND_SEQ_2_3 bit 1	MAIN[10][29][16]
CHAN_BOND_SEQ_2_3 bit 2	MAIN[10][28][17]
CHAN_BOND_SEQ_2_3 bit 3	MAIN[10][29][17]
CHAN_BOND_SEQ_2_3 bit 4	MAIN[10][28][18]
CHAN_BOND_SEQ_2_3 bit 5	MAIN[10][29][18]
CHAN_BOND_SEQ_2_3 bit 6	MAIN[10][28][19]
CHAN_BOND_SEQ_2_3 bit 7	MAIN[10][29][19]
CHAN_BOND_SEQ_2_3 bit 8	MAIN[10][28][20]
CHAN_BOND_SEQ_2_3 bit 9	MAIN[10][29][20]
CHAN_BOND_SEQ_2_4 bit 0	MAIN[10][28][24]
CHAN_BOND_SEQ_2_4 bit 1	MAIN[10][29][24]
CHAN_BOND_SEQ_2_4 bit 2	MAIN[10][28][25]
CHAN_BOND_SEQ_2_4 bit 3	MAIN[10][29][25]
CHAN_BOND_SEQ_2_4 bit 4	MAIN[10][28][26]
CHAN_BOND_SEQ_2_4 bit 5	MAIN[10][29][26]
CHAN_BOND_SEQ_2_4 bit 6	MAIN[10][28][27]
CHAN_BOND_SEQ_2_4 bit 7	MAIN[10][29][27]
CHAN_BOND_SEQ_2_4 bit 8	MAIN[10][28][28]
CHAN_BOND_SEQ_2_4 bit 9	MAIN[10][29][28]
CHAN_BOND_SEQ_2_ENABLE bit 0	MAIN[10][28][6]
CHAN_BOND_SEQ_2_ENABLE bit 1	MAIN[10][29][6]
CHAN_BOND_SEQ_2_ENABLE bit 2	MAIN[10][28][7]
CHAN_BOND_SEQ_2_ENABLE bit 3	MAIN[10][29][7]
CLK_COR_SEQ_1_1 bit 0	MAIN[8][28][32]
CLK_COR_SEQ_1_1 bit 1	MAIN[8][29][32]
CLK_COR_SEQ_1_1 bit 2	MAIN[8][28][33]
CLK_COR_SEQ_1_1 bit 3	MAIN[8][29][33]
CLK_COR_SEQ_1_1 bit 4	MAIN[8][28][34]
CLK_COR_SEQ_1_1 bit 5	MAIN[8][29][34]
CLK_COR_SEQ_1_1 bit 6	MAIN[8][28][35]
CLK_COR_SEQ_1_1 bit 7	MAIN[8][29][35]
CLK_COR_SEQ_1_1 bit 8	MAIN[8][28][36]
CLK_COR_SEQ_1_1 bit 9	MAIN[8][29][36]
CLK_COR_SEQ_1_2 bit 0	MAIN[8][28][40]
CLK_COR_SEQ_1_2 bit 1	MAIN[8][29][40]
CLK_COR_SEQ_1_2 bit 2	MAIN[8][28][41]
CLK_COR_SEQ_1_2 bit 3	MAIN[8][29][41]
CLK_COR_SEQ_1_2 bit 4	MAIN[8][28][42]
CLK_COR_SEQ_1_2 bit 5	MAIN[8][29][42]
CLK_COR_SEQ_1_2 bit 6	MAIN[8][28][43]
CLK_COR_SEQ_1_2 bit 7	MAIN[8][29][43]
CLK_COR_SEQ_1_2 bit 8	MAIN[8][28][44]
CLK_COR_SEQ_1_2 bit 9	MAIN[8][29][44]
CLK_COR_SEQ_1_3 bit 0	MAIN[8][28][48]
CLK_COR_SEQ_1_3 bit 1	MAIN[8][29][48]
CLK_COR_SEQ_1_3 bit 2	MAIN[8][28][49]
CLK_COR_SEQ_1_3 bit 3	MAIN[8][29][49]
CLK_COR_SEQ_1_3 bit 4	MAIN[8][28][50]
CLK_COR_SEQ_1_3 bit 5	MAIN[8][29][50]
CLK_COR_SEQ_1_3 bit 6	MAIN[8][28][51]
CLK_COR_SEQ_1_3 bit 7	MAIN[8][29][51]
CLK_COR_SEQ_1_3 bit 8	MAIN[8][28][52]
CLK_COR_SEQ_1_3 bit 9	MAIN[8][29][52]
CLK_COR_SEQ_1_4 bit 0	MAIN[8][28][56]
CLK_COR_SEQ_1_4 bit 1	MAIN[8][29][56]
CLK_COR_SEQ_1_4 bit 2	MAIN[8][28][57]
CLK_COR_SEQ_1_4 bit 3	MAIN[8][29][57]
CLK_COR_SEQ_1_4 bit 4	MAIN[8][28][58]
CLK_COR_SEQ_1_4 bit 5	MAIN[8][29][58]
CLK_COR_SEQ_1_4 bit 6	MAIN[8][28][59]
CLK_COR_SEQ_1_4 bit 7	MAIN[8][29][59]
CLK_COR_SEQ_1_4 bit 8	MAIN[8][28][60]
CLK_COR_SEQ_1_4 bit 9	MAIN[8][29][60]
CLK_COR_SEQ_1_ENABLE bit 0	MAIN[8][28][37]
CLK_COR_SEQ_1_ENABLE bit 1	MAIN[8][29][37]
CLK_COR_SEQ_1_ENABLE bit 2	MAIN[8][28][38]
CLK_COR_SEQ_1_ENABLE bit 3	MAIN[8][29][38]
CLK_COR_SEQ_2_1 bit 0	MAIN[9][28][0]
CLK_COR_SEQ_2_1 bit 1	MAIN[9][29][0]
CLK_COR_SEQ_2_1 bit 2	MAIN[9][28][1]
CLK_COR_SEQ_2_1 bit 3	MAIN[9][29][1]
CLK_COR_SEQ_2_1 bit 4	MAIN[9][28][2]
CLK_COR_SEQ_2_1 bit 5	MAIN[9][29][2]
CLK_COR_SEQ_2_1 bit 6	MAIN[9][28][3]
CLK_COR_SEQ_2_1 bit 7	MAIN[9][29][3]
CLK_COR_SEQ_2_1 bit 8	MAIN[9][28][4]
CLK_COR_SEQ_2_1 bit 9	MAIN[9][29][4]
CLK_COR_SEQ_2_2 bit 0	MAIN[9][28][8]
CLK_COR_SEQ_2_2 bit 1	MAIN[9][29][8]
CLK_COR_SEQ_2_2 bit 2	MAIN[9][28][9]
CLK_COR_SEQ_2_2 bit 3	MAIN[9][29][9]
CLK_COR_SEQ_2_2 bit 4	MAIN[9][28][10]
CLK_COR_SEQ_2_2 bit 5	MAIN[9][29][10]
CLK_COR_SEQ_2_2 bit 6	MAIN[9][28][11]
CLK_COR_SEQ_2_2 bit 7	MAIN[9][29][11]
CLK_COR_SEQ_2_2 bit 8	MAIN[9][28][12]
CLK_COR_SEQ_2_2 bit 9	MAIN[9][29][12]
CLK_COR_SEQ_2_3 bit 0	MAIN[9][28][16]
CLK_COR_SEQ_2_3 bit 1	MAIN[9][29][16]
CLK_COR_SEQ_2_3 bit 2	MAIN[9][28][17]
CLK_COR_SEQ_2_3 bit 3	MAIN[9][29][17]
CLK_COR_SEQ_2_3 bit 4	MAIN[9][28][18]
CLK_COR_SEQ_2_3 bit 5	MAIN[9][29][18]
CLK_COR_SEQ_2_3 bit 6	MAIN[9][28][19]
CLK_COR_SEQ_2_3 bit 7	MAIN[9][29][19]
CLK_COR_SEQ_2_3 bit 8	MAIN[9][28][20]
CLK_COR_SEQ_2_3 bit 9	MAIN[9][29][20]
CLK_COR_SEQ_2_4 bit 0	MAIN[9][28][24]
CLK_COR_SEQ_2_4 bit 1	MAIN[9][29][24]
CLK_COR_SEQ_2_4 bit 2	MAIN[9][28][25]
CLK_COR_SEQ_2_4 bit 3	MAIN[9][29][25]
CLK_COR_SEQ_2_4 bit 4	MAIN[9][28][26]
CLK_COR_SEQ_2_4 bit 5	MAIN[9][29][26]
CLK_COR_SEQ_2_4 bit 6	MAIN[9][28][27]
CLK_COR_SEQ_2_4 bit 7	MAIN[9][29][27]
CLK_COR_SEQ_2_4 bit 8	MAIN[9][28][28]
CLK_COR_SEQ_2_4 bit 9	MAIN[9][29][28]
CLK_COR_SEQ_2_ENABLE bit 0	MAIN[9][28][5]
CLK_COR_SEQ_2_ENABLE bit 1	MAIN[9][29][5]
CLK_COR_SEQ_2_ENABLE bit 2	MAIN[9][28][6]
CLK_COR_SEQ_2_ENABLE bit 3	MAIN[9][29][6]
CPLL_PCD_2UI_CFG bit 0	MAIN[0][31][16]
ES_CLK_PHASE_SEL bit 0	MAIN[7][31][15]
ES_CONTROL bit 0	MAIN[7][28][40]
ES_CONTROL bit 1	MAIN[7][29][40]
ES_CONTROL bit 2	MAIN[7][28][41]
ES_CONTROL bit 3	MAIN[7][29][41]
ES_CONTROL bit 4	MAIN[7][28][42]
ES_CONTROL bit 5	MAIN[7][29][42]
ES_PMA_CFG bit 0	MAIN[9][30][48]
ES_PMA_CFG bit 1	MAIN[9][31][48]
ES_PMA_CFG bit 2	MAIN[9][30][49]
ES_PMA_CFG bit 3	MAIN[9][31][49]
ES_PMA_CFG bit 4	MAIN[9][30][50]
ES_PMA_CFG bit 5	MAIN[9][31][50]
ES_PMA_CFG bit 6	MAIN[9][30][51]
ES_PMA_CFG bit 7	MAIN[9][31][51]
ES_PMA_CFG bit 8	MAIN[9][30][52]
ES_PMA_CFG bit 9	MAIN[9][31][52]
ES_PRESCALE bit 0	MAIN[7][29][29]
ES_PRESCALE bit 1	MAIN[7][28][30]
ES_PRESCALE bit 2	MAIN[7][29][30]
ES_PRESCALE bit 3	MAIN[7][28][31]
ES_PRESCALE bit 4	MAIN[7][29][31]
ES_VERT_OFFSET bit 0	MAIN[7][28][24]
ES_VERT_OFFSET bit 1	MAIN[7][29][24]
ES_VERT_OFFSET bit 2	MAIN[7][28][25]
ES_VERT_OFFSET bit 3	MAIN[7][29][25]
ES_VERT_OFFSET bit 4	MAIN[7][28][26]
ES_VERT_OFFSET bit 5	MAIN[7][29][26]
ES_VERT_OFFSET bit 6	MAIN[7][28][27]
ES_VERT_OFFSET bit 7	MAIN[7][29][27]
ES_VERT_OFFSET bit 8	MAIN[7][28][28]
FTS_DESKEW_SEQ_ENABLE bit 0	MAIN[10][28][22]
FTS_DESKEW_SEQ_ENABLE bit 1	MAIN[10][29][22]
FTS_DESKEW_SEQ_ENABLE bit 2	MAIN[10][28][23]
FTS_DESKEW_SEQ_ENABLE bit 3	MAIN[10][29][23]
FTS_LANE_DESKEW_CFG bit 0	MAIN[10][28][14]
FTS_LANE_DESKEW_CFG bit 1	MAIN[10][29][14]
FTS_LANE_DESKEW_CFG bit 2	MAIN[10][28][15]
FTS_LANE_DESKEW_CFG bit 3	MAIN[10][29][15]
GEARBOX_MODE bit 0	MAIN[3][28][32]
GEARBOX_MODE bit 1	MAIN[3][29][32]
GEARBOX_MODE bit 2	MAIN[3][28][33]
GT_INSTANTIATED bit 0	MAIN[0][28][0]
LOOPBACK_CFG bit 0	MAIN[0][30][20]
OUTREFCLK_SEL_INV bit 0	MAIN[2][28][21]
OUTREFCLK_SEL_INV bit 1	MAIN[2][29][21]
PMA_POWER_SAVE bit 0	MAIN[5][30][32]
PMA_POWER_SAVE bit 1	MAIN[5][31][32]
PMA_POWER_SAVE bit 2	MAIN[5][30][33]
PMA_POWER_SAVE bit 3	MAIN[5][31][33]
PMA_POWER_SAVE bit 4	MAIN[5][30][34]
PMA_POWER_SAVE bit 5	MAIN[5][31][34]
PMA_POWER_SAVE bit 6	MAIN[5][30][35]
PMA_POWER_SAVE bit 7	MAIN[5][31][35]
PMA_POWER_SAVE bit 8	MAIN[5][30][36]
PMA_POWER_SAVE bit 9	MAIN[5][31][36]
PMA_RSV3 bit 0	MAIN[4][30][32]
PMA_RSV3 bit 1	MAIN[4][31][32]
RESET_POWERSAVE_DISABLE bit 0	MAIN[5][30][37]
RXBUFRESET_TIME bit 0	MAIN[1][28][40]
RXBUFRESET_TIME bit 1	MAIN[1][29][40]
RXBUFRESET_TIME bit 2	MAIN[1][28][41]
RXBUFRESET_TIME bit 3	MAIN[1][29][41]
RXBUFRESET_TIME bit 4	MAIN[1][28][42]
RXBUF_EIDLE_HI_CNT bit 0	MAIN[8][30][46]
RXBUF_EIDLE_HI_CNT bit 1	MAIN[8][31][46]
RXBUF_EIDLE_HI_CNT bit 2	MAIN[8][30][47]
RXBUF_EIDLE_HI_CNT bit 3	MAIN[8][31][47]
RXBUF_EIDLE_LO_CNT bit 0	MAIN[8][30][44]
RXBUF_EIDLE_LO_CNT bit 1	MAIN[8][31][44]
RXBUF_EIDLE_LO_CNT bit 2	MAIN[8][30][45]
RXBUF_EIDLE_LO_CNT bit 3	MAIN[8][31][45]
RXCDRFREQRESET_TIME bit 0	MAIN[1][29][42]
RXCDRFREQRESET_TIME bit 1	MAIN[1][28][43]
RXCDRFREQRESET_TIME bit 2	MAIN[1][29][43]
RXCDRFREQRESET_TIME bit 3	MAIN[1][28][44]
RXCDRFREQRESET_TIME bit 4	MAIN[1][29][44]
RXCDRPHRESET_TIME bit 0	MAIN[1][28][45]
RXCDRPHRESET_TIME bit 1	MAIN[1][29][45]
RXCDRPHRESET_TIME bit 2	MAIN[1][28][46]
RXCDRPHRESET_TIME bit 3	MAIN[1][29][46]
RXCDRPHRESET_TIME bit 4	MAIN[1][28][47]
RXCDRRESET_TIME bit 0	MAIN[2][28][0]
RXCDRRESET_TIME bit 1	MAIN[2][29][0]
RXCDRRESET_TIME bit 2	MAIN[2][28][1]
RXCDRRESET_TIME bit 3	MAIN[2][29][1]
RXCDRRESET_TIME bit 4	MAIN[2][28][2]
RXCDRRESET_TIME bit 5	MAIN[2][29][2]
RXCDRRESET_TIME bit 6	MAIN[2][28][3]
RXCDR_FR_RESET_ON_EIDLE bit 0	MAIN[9][30][62]
RXCDR_HOLD_DURING_EIDLE bit 0	MAIN[9][31][61]
RXCDR_LOCK_CFG bit 0	MAIN[9][30][56]
RXCDR_LOCK_CFG bit 1	MAIN[9][31][56]
RXCDR_LOCK_CFG bit 2	MAIN[9][30][57]
RXCDR_LOCK_CFG bit 3	MAIN[9][31][57]
RXCDR_LOCK_CFG bit 4	MAIN[9][30][58]
RXCDR_LOCK_CFG bit 5	MAIN[9][31][58]
RXCDR_PCIERESET_WAIT_TIME bit 0	MAIN[9][30][59]
RXCDR_PCIERESET_WAIT_TIME bit 1	MAIN[9][31][59]
RXCDR_PCIERESET_WAIT_TIME bit 2	MAIN[9][30][60]
RXCDR_PCIERESET_WAIT_TIME bit 3	MAIN[9][31][60]
RXCDR_PCIERESET_WAIT_TIME bit 4	MAIN[9][30][61]
RXCDR_PH_RESET_ON_EIDLE bit 0	MAIN[9][31][62]
RXDFELPMRESET_TIME bit 0	MAIN[1][29][36]
RXDFELPMRESET_TIME bit 1	MAIN[1][28][37]
RXDFELPMRESET_TIME bit 2	MAIN[1][29][37]
RXDFELPMRESET_TIME bit 3	MAIN[1][28][38]
RXDFELPMRESET_TIME bit 4	MAIN[1][29][38]
RXDFELPMRESET_TIME bit 5	MAIN[1][28][39]
RXDFELPMRESET_TIME bit 6	MAIN[1][29][39]
RXISCANRESET_TIME bit 0	MAIN[1][28][61]
RXISCANRESET_TIME bit 1	MAIN[1][29][61]
RXISCANRESET_TIME bit 2	MAIN[1][28][62]
RXISCANRESET_TIME bit 3	MAIN[1][29][62]
RXISCANRESET_TIME bit 4	MAIN[1][28][63]
RXLPM_HF_CFG bit 0	MAIN[5][28][16]
RXLPM_HF_CFG bit 1	MAIN[5][29][16]
RXLPM_HF_CFG bit 2	MAIN[5][28][17]
RXLPM_HF_CFG bit 3	MAIN[5][29][17]
RXLPM_HF_CFG bit 4	MAIN[5][28][18]
RXLPM_HF_CFG bit 5	MAIN[5][29][18]
RXLPM_HF_CFG bit 6	MAIN[5][28][19]
RXLPM_HF_CFG bit 7	MAIN[5][29][19]
RXLPM_HF_CFG bit 8	MAIN[5][28][20]
RXLPM_HF_CFG bit 9	MAIN[5][29][20]
RXLPM_HF_CFG bit 10	MAIN[5][28][21]
RXLPM_HF_CFG bit 11	MAIN[5][29][21]
RXLPM_HF_CFG bit 12	MAIN[5][28][22]
RXLPM_HF_CFG bit 13	MAIN[5][29][22]
RXOOB_CFG bit 0	MAIN[2][28][16]
RXOOB_CFG bit 1	MAIN[2][29][16]
RXOOB_CFG bit 2	MAIN[2][28][17]
RXOOB_CFG bit 3	MAIN[2][29][17]
RXOOB_CFG bit 4	MAIN[2][28][18]
RXOOB_CFG bit 5	MAIN[2][29][18]
RXOOB_CFG bit 6	MAIN[2][28][19]
RXOSCALRESET_TIME bit 0	MAIN[2][28][59]
RXOSCALRESET_TIME bit 1	MAIN[2][29][59]
RXOSCALRESET_TIME bit 2	MAIN[2][28][60]
RXOSCALRESET_TIME bit 3	MAIN[2][29][60]
RXOSCALRESET_TIME bit 4	MAIN[2][28][61]
RXOSCALRESET_TIMEOUT bit 0	MAIN[2][29][61]
RXOSCALRESET_TIMEOUT bit 1	MAIN[2][28][62]
RXOSCALRESET_TIMEOUT bit 2	MAIN[2][29][62]
RXOSCALRESET_TIMEOUT bit 3	MAIN[2][28][63]
RXOSCALRESET_TIMEOUT bit 4	MAIN[2][29][63]
RXPI_CFG0 bit 0	MAIN[0][30][38]
RXPI_CFG0 bit 1	MAIN[0][31][38]
RXPI_CFG1 bit 0	MAIN[0][31][45]
RXPI_CFG1 bit 1	MAIN[0][30][46]
RXPI_CFG2 bit 0	MAIN[0][31][46]
RXPI_CFG2 bit 1	MAIN[0][30][47]
RXPI_CFG3 bit 0	MAIN[0][30][39]
RXPI_CFG3 bit 1	MAIN[0][31][39]
RXPI_CFG4 bit 0	MAIN[1][30][15]
RXPI_CFG5 bit 0	MAIN[1][31][15]
RXPI_CFG6 bit 0	MAIN[1][30][40]
RXPI_CFG6 bit 1	MAIN[1][31][40]
RXPI_CFG6 bit 2	MAIN[1][30][41]
RXSYNC_MULTILANE bit 0	MAIN[2][28][5]
RXSYNC_OVRD bit 0	MAIN[2][29][7]
RXSYNC_SKIP_DA bit 0	MAIN[2][28][6]
RXPCSRESET_TIME bit 0	MAIN[1][29][53]
RXPCSRESET_TIME bit 1	MAIN[1][28][54]
RXPCSRESET_TIME bit 2	MAIN[1][29][54]
RXPCSRESET_TIME bit 3	MAIN[1][28][55]
RXPCSRESET_TIME bit 4	MAIN[1][29][55]
RXPH_MONITOR_SEL bit 0	MAIN[10][28][60]
RXPH_MONITOR_SEL bit 1	MAIN[10][29][60]
RXPH_MONITOR_SEL bit 2	MAIN[10][28][61]
RXPH_MONITOR_SEL bit 3	MAIN[10][29][61]
RXPH_MONITOR_SEL bit 4	MAIN[10][28][62]
RXPMARESET_TIME bit 0	MAIN[1][28][51]
RXPMARESET_TIME bit 1	MAIN[1][29][51]
RXPMARESET_TIME bit 2	MAIN[1][28][52]
RXPMARESET_TIME bit 3	MAIN[1][29][52]
RXPMARESET_TIME bit 4	MAIN[1][28][53]
RXPRBS_ERR_LOOPBACK bit 0	MAIN[2][28][8]
RX_BUFFER_CFG bit 0	MAIN[8][30][24]
RX_BUFFER_CFG bit 1	MAIN[8][31][24]
RX_BUFFER_CFG bit 2	MAIN[8][30][25]
RX_BUFFER_CFG bit 3	MAIN[8][31][25]
RX_BUFFER_CFG bit 4	MAIN[8][30][26]
RX_BUFFER_CFG bit 5	MAIN[8][31][26]
RX_CLKMUX_PD bit 0	MAIN[2][30][0]
RX_CM_SEL bit 0	MAIN[2][28][10]
RX_CM_SEL bit 1	MAIN[2][29][10]
RX_DDI_SEL bit 0	MAIN[10][28][56]
RX_DDI_SEL bit 1	MAIN[10][29][56]
RX_DDI_SEL bit 2	MAIN[10][28][57]
RX_DDI_SEL bit 3	MAIN[10][29][57]
RX_DDI_SEL bit 4	MAIN[10][28][58]
RX_DDI_SEL bit 5	MAIN[10][29][58]
RXLPM_LF_CFG_GTH bit 0	MAIN[5][28][24]
RXLPM_LF_CFG_GTH bit 1	MAIN[5][29][24]
RXLPM_LF_CFG_GTH bit 2	MAIN[5][28][25]
RXLPM_LF_CFG_GTH bit 3	MAIN[5][29][25]
RXLPM_LF_CFG_GTH bit 4	MAIN[5][28][26]
RXLPM_LF_CFG_GTH bit 5	MAIN[5][29][26]
RXLPM_LF_CFG_GTH bit 6	MAIN[5][28][27]
RXLPM_LF_CFG_GTH bit 7	MAIN[5][29][27]
RXLPM_LF_CFG_GTH bit 8	MAIN[5][28][28]
RXLPM_LF_CFG_GTH bit 9	MAIN[5][29][28]
RXLPM_LF_CFG_GTH bit 10	MAIN[5][28][29]
RXLPM_LF_CFG_GTH bit 11	MAIN[5][29][29]
RXLPM_LF_CFG_GTH bit 12	MAIN[5][28][30]
RXLPM_LF_CFG_GTH bit 13	MAIN[5][29][30]
RXLPM_LF_CFG_GTH bit 14	MAIN[5][28][31]
RXLPM_LF_CFG_GTH bit 15	MAIN[5][29][31]
RXLPM_LF_CFG_GTH bit 16	MAIN[5][28][23]
RXLPM_LF_CFG_GTH bit 17	MAIN[5][29][23]
RX_BIAS_CFG_GTH bit 0	MAIN[1][30][48]
RX_BIAS_CFG_GTH bit 1	MAIN[1][31][48]
RX_BIAS_CFG_GTH bit 2	MAIN[1][30][49]
RX_BIAS_CFG_GTH bit 3	MAIN[1][31][49]
RX_BIAS_CFG_GTH bit 4	MAIN[1][30][50]
RX_BIAS_CFG_GTH bit 5	MAIN[1][31][50]
RX_BIAS_CFG_GTH bit 6	MAIN[1][30][51]
RX_BIAS_CFG_GTH bit 7	MAIN[1][31][51]
RX_BIAS_CFG_GTH bit 8	MAIN[1][30][52]
RX_BIAS_CFG_GTH bit 9	MAIN[1][31][52]
RX_BIAS_CFG_GTH bit 10	MAIN[1][30][53]
RX_BIAS_CFG_GTH bit 11	MAIN[1][31][53]
RX_BIAS_CFG_GTH bit 12	MAIN[1][30][54]
RX_BIAS_CFG_GTH bit 13	MAIN[1][31][54]
RX_BIAS_CFG_GTH bit 14	MAIN[1][30][55]
RX_BIAS_CFG_GTH bit 15	MAIN[1][31][55]
RX_BIAS_CFG_GTH bit 16	MAIN[1][30][56]
RX_BIAS_CFG_GTH bit 17	MAIN[1][31][56]
RX_BIAS_CFG_GTH bit 18	MAIN[1][30][57]
RX_BIAS_CFG_GTH bit 19	MAIN[1][31][57]
RX_BIAS_CFG_GTH bit 20	MAIN[1][30][58]
RX_BIAS_CFG_GTH bit 21	MAIN[1][31][58]
RX_BIAS_CFG_GTH bit 22	MAIN[1][30][59]
RX_BIAS_CFG_GTH bit 23	MAIN[1][31][59]
RX_CM_TRIM_GTH bit 0	MAIN[4][30][48]
RX_CM_TRIM_GTH bit 1	MAIN[4][31][48]
RX_CM_TRIM_GTH bit 2	MAIN[4][30][49]
RX_CM_TRIM_GTH bit 3	MAIN[4][31][49]
RX_DEBUG_CFG_GTH bit 0	MAIN[9][30][40]
RX_DEBUG_CFG_GTH bit 1	MAIN[9][31][40]
RX_DEBUG_CFG_GTH bit 2	MAIN[9][30][41]
RX_DEBUG_CFG_GTH bit 3	MAIN[9][31][41]
RX_DEBUG_CFG_GTH bit 4	MAIN[9][30][42]
RX_DEBUG_CFG_GTH bit 5	MAIN[9][31][42]
RX_DEBUG_CFG_GTH bit 6	MAIN[9][30][43]
RX_DEBUG_CFG_GTH bit 7	MAIN[9][31][43]
RX_DEBUG_CFG_GTH bit 8	MAIN[9][30][44]
RX_DEBUG_CFG_GTH bit 9	MAIN[9][31][44]
RX_DEBUG_CFG_GTH bit 10	MAIN[9][30][45]
RX_DEBUG_CFG_GTH bit 11	MAIN[9][31][45]
RX_DEBUG_CFG_GTH bit 12	MAIN[9][30][46]
RX_DEBUG_CFG_GTH bit 13	MAIN[9][31][46]
RX_DFE_KL_CFG_GTH bit 0	MAIN[3][30][16]
RX_DFE_KL_CFG_GTH bit 1	MAIN[3][31][16]
RX_DFE_KL_CFG_GTH bit 2	MAIN[3][30][17]
RX_DFE_KL_CFG_GTH bit 3	MAIN[3][31][17]
RX_DFE_KL_CFG_GTH bit 4	MAIN[3][30][18]
RX_DFE_KL_CFG_GTH bit 5	MAIN[3][31][18]
RX_DFE_KL_CFG_GTH bit 6	MAIN[3][30][19]
RX_DFE_KL_CFG_GTH bit 7	MAIN[3][31][19]
RX_DFE_KL_CFG_GTH bit 8	MAIN[3][30][20]
RX_DFE_KL_CFG_GTH bit 9	MAIN[3][31][20]
RX_DFE_KL_CFG_GTH bit 10	MAIN[3][30][21]
RX_DFE_KL_CFG_GTH bit 11	MAIN[3][31][21]
RX_DFE_KL_CFG_GTH bit 12	MAIN[3][30][22]
RX_DFE_KL_CFG_GTH bit 13	MAIN[3][31][22]
RX_DFE_KL_CFG_GTH bit 14	MAIN[3][30][23]
RX_DFE_KL_CFG_GTH bit 15	MAIN[3][31][23]
RX_DFE_KL_CFG_GTH bit 16	MAIN[3][30][24]
RX_DFE_KL_CFG_GTH bit 17	MAIN[3][31][24]
RX_DFE_KL_CFG_GTH bit 18	MAIN[3][30][25]
RX_DFE_KL_CFG_GTH bit 19	MAIN[3][31][25]
RX_DFE_KL_CFG_GTH bit 20	MAIN[3][30][26]
RX_DFE_KL_CFG_GTH bit 21	MAIN[3][31][26]
RX_DFE_KL_CFG_GTH bit 22	MAIN[3][30][27]
RX_DFE_KL_CFG_GTH bit 23	MAIN[3][31][27]
RX_DFE_KL_CFG_GTH bit 24	MAIN[3][30][28]
RX_DFE_KL_CFG_GTH bit 25	MAIN[3][31][28]
RX_DFE_KL_CFG_GTH bit 26	MAIN[3][30][29]
RX_DFE_KL_CFG_GTH bit 27	MAIN[3][31][29]
RX_DFE_KL_CFG_GTH bit 28	MAIN[3][30][30]
RX_DFE_KL_CFG_GTH bit 29	MAIN[3][31][30]
RX_DFE_KL_CFG_GTH bit 30	MAIN[3][30][31]
RX_DFE_KL_CFG_GTH bit 31	MAIN[3][31][31]
RX_DFE_KL_CFG_GTH bit 32	MAIN[3][30][32]
TERM_RCAL_CFG_GTH bit 0	MAIN[2][30][8]
TERM_RCAL_CFG_GTH bit 1	MAIN[2][31][8]
TERM_RCAL_CFG_GTH bit 2	MAIN[2][30][9]
TERM_RCAL_CFG_GTH bit 3	MAIN[2][31][9]
TERM_RCAL_CFG_GTH bit 4	MAIN[2][30][10]
TERM_RCAL_CFG_GTH bit 5	MAIN[2][31][10]
TERM_RCAL_CFG_GTH bit 6	MAIN[2][30][11]
TERM_RCAL_CFG_GTH bit 7	MAIN[2][31][11]
TERM_RCAL_CFG_GTH bit 8	MAIN[2][30][12]
TERM_RCAL_CFG_GTH bit 9	MAIN[2][31][12]
TERM_RCAL_CFG_GTH bit 10	MAIN[2][30][13]
TERM_RCAL_CFG_GTH bit 11	MAIN[2][31][13]
TERM_RCAL_CFG_GTH bit 12	MAIN[2][30][14]
TERM_RCAL_CFG_GTH bit 13	MAIN[2][31][14]
TERM_RCAL_CFG_GTH bit 14	MAIN[2][30][15]
TERM_RCAL_OVRD_GTH bit 0	MAIN[2][31][22]
TERM_RCAL_OVRD_GTH bit 1	MAIN[2][30][23]
TERM_RCAL_OVRD_GTH bit 2	MAIN[2][31][23]
TX_DEEMPH0_GTH bit 0	MAIN[4][30][16]
TX_DEEMPH0_GTH bit 1	MAIN[4][31][16]
TX_DEEMPH0_GTH bit 2	MAIN[4][30][17]
TX_DEEMPH0_GTH bit 3	MAIN[4][31][17]
TX_DEEMPH0_GTH bit 4	MAIN[4][30][18]
TX_DEEMPH0_GTH bit 5	MAIN[4][31][18]
TX_DEEMPH1_GTH bit 0	MAIN[4][30][20]
TX_DEEMPH1_GTH bit 1	MAIN[4][31][20]
TX_DEEMPH1_GTH bit 2	MAIN[4][30][21]
TX_DEEMPH1_GTH bit 3	MAIN[4][31][21]
TX_DEEMPH1_GTH bit 4	MAIN[4][30][22]
TX_DEEMPH1_GTH bit 5	MAIN[4][31][22]
RX_DFE_LPM_HOLD_DURING_EIDLE bit 0	MAIN[3][28][55]
RX_DFE_UT_CFG bit 0	MAIN[4][28][40]
RX_DFE_UT_CFG bit 1	MAIN[4][29][40]
RX_DFE_UT_CFG bit 2	MAIN[4][28][41]
RX_DFE_UT_CFG bit 3	MAIN[4][29][41]
RX_DFE_UT_CFG bit 4	MAIN[4][28][42]
RX_DFE_UT_CFG bit 5	MAIN[4][29][42]
RX_DFE_UT_CFG bit 6	MAIN[4][28][43]
RX_DFE_UT_CFG bit 7	MAIN[4][29][43]
RX_DFE_UT_CFG bit 8	MAIN[4][28][44]
RX_DFE_UT_CFG bit 9	MAIN[4][29][44]
RX_DFE_UT_CFG bit 10	MAIN[4][28][45]
RX_DFE_UT_CFG bit 11	MAIN[4][29][45]
RX_DFE_UT_CFG bit 12	MAIN[4][28][46]
RX_DFE_UT_CFG bit 13	MAIN[4][29][46]
RX_DFE_UT_CFG bit 14	MAIN[4][28][47]
RX_DFE_UT_CFG bit 15	MAIN[4][29][47]
RX_DFE_UT_CFG bit 16	MAIN[4][29][39]
RX_DFE_VP_CFG bit 0	MAIN[4][28][48]
RX_DFE_VP_CFG bit 1	MAIN[4][29][48]
RX_DFE_VP_CFG bit 2	MAIN[4][28][49]
RX_DFE_VP_CFG bit 3	MAIN[4][29][49]
RX_DFE_VP_CFG bit 4	MAIN[4][28][50]
RX_DFE_VP_CFG bit 5	MAIN[4][29][50]
RX_DFE_VP_CFG bit 6	MAIN[4][28][51]
RX_DFE_VP_CFG bit 7	MAIN[4][29][51]
RX_DFE_VP_CFG bit 8	MAIN[4][28][52]
RX_DFE_VP_CFG bit 9	MAIN[4][29][52]
RX_DFE_VP_CFG bit 10	MAIN[4][28][53]
RX_DFE_VP_CFG bit 11	MAIN[4][29][53]
RX_DFE_VP_CFG bit 12	MAIN[4][28][54]
RX_DFE_VP_CFG bit 13	MAIN[4][29][54]
RX_DFE_VP_CFG bit 14	MAIN[4][28][55]
RX_DFE_VP_CFG bit 15	MAIN[4][29][55]
RX_DFE_VP_CFG bit 16	MAIN[4][28][56]
RX_DFE_VS_CFG bit 0	MAIN[4][28][58]
RX_DFE_VS_CFG bit 1	MAIN[4][29][58]
RX_DFE_VS_CFG bit 2	MAIN[4][28][59]
RX_DFE_VS_CFG bit 3	MAIN[4][29][59]
RX_DFE_VS_CFG bit 4	MAIN[4][28][60]
RX_DFE_VS_CFG bit 5	MAIN[4][29][60]
RX_DFE_VS_CFG bit 6	MAIN[4][28][61]
RX_DFE_VS_CFG bit 7	MAIN[4][29][61]
RX_DFE_VS_CFG bit 8	MAIN[4][28][62]
RX_DFE_H2_CFG bit 0	MAIN[3][28][56]
RX_DFE_H2_CFG bit 1	MAIN[3][29][56]
RX_DFE_H2_CFG bit 2	MAIN[3][28][57]
RX_DFE_H2_CFG bit 3	MAIN[3][29][57]
RX_DFE_H2_CFG bit 4	MAIN[3][28][58]
RX_DFE_H2_CFG bit 5	MAIN[3][29][58]
RX_DFE_H2_CFG bit 6	MAIN[3][28][59]
RX_DFE_H2_CFG bit 7	MAIN[3][29][59]
RX_DFE_H2_CFG bit 8	MAIN[3][28][60]
RX_DFE_H2_CFG bit 9	MAIN[3][29][60]
RX_DFE_H2_CFG bit 10	MAIN[3][28][61]
RX_DFE_H2_CFG bit 11	MAIN[3][29][61]
RX_DFE_H3_CFG bit 0	MAIN[4][28][0]
RX_DFE_H3_CFG bit 1	MAIN[4][29][0]
RX_DFE_H3_CFG bit 2	MAIN[4][28][1]
RX_DFE_H3_CFG bit 3	MAIN[4][29][1]
RX_DFE_H3_CFG bit 4	MAIN[4][28][2]
RX_DFE_H3_CFG bit 5	MAIN[4][29][2]
RX_DFE_H3_CFG bit 6	MAIN[4][28][3]
RX_DFE_H3_CFG bit 7	MAIN[4][29][3]
RX_DFE_H3_CFG bit 8	MAIN[4][28][4]
RX_DFE_H3_CFG bit 9	MAIN[4][29][4]
RX_DFE_H3_CFG bit 10	MAIN[4][28][5]
RX_DFE_H3_CFG bit 11	MAIN[4][29][5]
RX_DFE_H4_CFG bit 0	MAIN[4][28][8]
RX_DFE_H4_CFG bit 1	MAIN[4][29][8]
RX_DFE_H4_CFG bit 2	MAIN[4][28][9]
RX_DFE_H4_CFG bit 3	MAIN[4][29][9]
RX_DFE_H4_CFG bit 4	MAIN[4][28][10]
RX_DFE_H4_CFG bit 5	MAIN[4][29][10]
RX_DFE_H4_CFG bit 6	MAIN[4][28][11]
RX_DFE_H4_CFG bit 7	MAIN[4][29][11]
RX_DFE_H4_CFG bit 8	MAIN[4][28][12]
RX_DFE_H4_CFG bit 9	MAIN[4][29][12]
RX_DFE_H4_CFG bit 10	MAIN[4][28][13]
RX_DFE_H5_CFG bit 0	MAIN[4][28][16]
RX_DFE_H5_CFG bit 1	MAIN[4][29][16]
RX_DFE_H5_CFG bit 2	MAIN[4][28][17]
RX_DFE_H5_CFG bit 3	MAIN[4][29][17]
RX_DFE_H5_CFG bit 4	MAIN[4][28][18]
RX_DFE_H5_CFG bit 5	MAIN[4][29][18]
RX_DFE_H5_CFG bit 6	MAIN[4][28][19]
RX_DFE_H5_CFG bit 7	MAIN[4][29][19]
RX_DFE_H5_CFG bit 8	MAIN[4][28][20]
RX_DFE_H5_CFG bit 9	MAIN[4][29][20]
RX_DFE_H5_CFG bit 10	MAIN[4][28][21]
RX_DFE_H6_CFG bit 0	MAIN[6][30][32]
RX_DFE_H6_CFG bit 1	MAIN[6][31][32]
RX_DFE_H6_CFG bit 2	MAIN[6][30][33]
RX_DFE_H6_CFG bit 3	MAIN[6][31][33]
RX_DFE_H6_CFG bit 4	MAIN[6][30][34]
RX_DFE_H6_CFG bit 5	MAIN[6][31][34]
RX_DFE_H6_CFG bit 6	MAIN[6][30][35]
RX_DFE_H6_CFG bit 7	MAIN[6][31][35]
RX_DFE_H6_CFG bit 8	MAIN[6][30][36]
RX_DFE_H6_CFG bit 9	MAIN[6][31][36]
RX_DFE_H6_CFG bit 10	MAIN[6][30][37]
RX_DFE_H7_CFG bit 0	MAIN[6][30][40]
RX_DFE_H7_CFG bit 1	MAIN[6][31][40]
RX_DFE_H7_CFG bit 2	MAIN[6][30][41]
RX_DFE_H7_CFG bit 3	MAIN[6][31][41]
RX_DFE_H7_CFG bit 4	MAIN[6][30][42]
RX_DFE_H7_CFG bit 5	MAIN[6][31][42]
RX_DFE_H7_CFG bit 6	MAIN[6][30][43]
RX_DFE_H7_CFG bit 7	MAIN[6][31][43]
RX_DFE_H7_CFG bit 8	MAIN[6][30][44]
RX_DFE_H7_CFG bit 9	MAIN[6][31][44]
RX_DFE_H7_CFG bit 10	MAIN[6][30][45]
RX_DFELPM_CFG0 bit 0	MAIN[5][30][8]
RX_DFELPM_CFG0 bit 1	MAIN[5][31][8]
RX_DFELPM_CFG0 bit 2	MAIN[5][30][9]
RX_DFELPM_CFG0 bit 3	MAIN[5][31][9]
RX_DFELPM_CFG1 bit 0	MAIN[5][30][10]
RX_DFELPM_KLKH_AGC_STUP_EN bit 0	MAIN[5][31][6]
RX_DFE_AGC_CFG0 bit 0	MAIN[3][30][34]
RX_DFE_AGC_CFG0 bit 1	MAIN[3][31][34]
RX_DFE_AGC_CFG1 bit 0	MAIN[3][30][35]
RX_DFE_AGC_CFG1 bit 1	MAIN[3][31][35]
RX_DFE_AGC_CFG1 bit 2	MAIN[3][30][36]
RX_DFE_AGC_CFG2 bit 0	MAIN[3][31][36]
RX_DFE_AGC_CFG2 bit 1	MAIN[3][30][37]
RX_DFE_AGC_CFG2 bit 2	MAIN[3][31][37]
RX_DFE_AGC_CFG2 bit 3	MAIN[3][30][38]
RX_DFE_AGC_OVRDEN bit 0	MAIN[5][31][10]
RX_DFE_KL_LPM_KH_CFG0 bit 0	MAIN[4][30][50]
RX_DFE_KL_LPM_KH_CFG0 bit 1	MAIN[4][31][50]
RX_DFE_KL_LPM_KH_CFG1 bit 0	MAIN[4][30][51]
RX_DFE_KL_LPM_KH_CFG1 bit 1	MAIN[4][31][51]
RX_DFE_KL_LPM_KH_CFG1 bit 2	MAIN[4][30][52]
RX_DFE_KL_LPM_KH_CFG2 bit 0	MAIN[4][31][52]
RX_DFE_KL_LPM_KH_CFG2 bit 1	MAIN[4][30][53]
RX_DFE_KL_LPM_KH_CFG2 bit 2	MAIN[4][31][53]
RX_DFE_KL_LPM_KH_CFG2 bit 3	MAIN[4][30][54]
RX_DFE_KL_LPM_KH_OVRDEN bit 0	MAIN[5][31][11]
RX_DFE_KL_LPM_KL_CFG0 bit 0	MAIN[4][31][54]
RX_DFE_KL_LPM_KL_CFG0 bit 1	MAIN[4][30][55]
RX_DFE_KL_LPM_KL_CFG1 bit 0	MAIN[4][31][37]
RX_DFE_KL_LPM_KL_CFG1 bit 1	MAIN[4][30][38]
RX_DFE_KL_LPM_KL_CFG1 bit 2	MAIN[4][31][38]
RX_DFE_KL_LPM_KL_CFG2 bit 0	MAIN[4][30][34]
RX_DFE_KL_LPM_KL_CFG2 bit 1	MAIN[4][31][34]
RX_DFE_KL_LPM_KL_CFG2 bit 2	MAIN[4][30][35]
RX_DFE_KL_LPM_KL_CFG2 bit 3	MAIN[4][31][35]
RX_DFE_KL_LPM_KL_OVRDEN bit 0	MAIN[5][30][11]
RX_OS_CFG bit 0	MAIN[4][28][32]
RX_OS_CFG bit 1	MAIN[4][29][32]
RX_OS_CFG bit 2	MAIN[4][28][33]
RX_OS_CFG bit 3	MAIN[4][29][33]
RX_OS_CFG bit 4	MAIN[4][28][34]
RX_OS_CFG bit 5	MAIN[4][29][34]
RX_OS_CFG bit 6	MAIN[4][28][35]
RX_OS_CFG bit 7	MAIN[4][29][35]
RX_OS_CFG bit 8	MAIN[4][28][36]
RX_OS_CFG bit 9	MAIN[4][29][36]
RX_OS_CFG bit 10	MAIN[4][28][37]
RX_OS_CFG bit 11	MAIN[4][29][37]
RX_OS_CFG bit 12	MAIN[4][28][38]
SATA_BURST_SEQ_LEN bit 0	MAIN[2][28][22]
SATA_BURST_SEQ_LEN bit 1	MAIN[2][29][22]
SATA_BURST_SEQ_LEN bit 2	MAIN[2][28][23]
SATA_BURST_SEQ_LEN bit 3	MAIN[2][29][23]
SATA_BURST_VAL bit 0	MAIN[2][29][19]
SATA_BURST_VAL bit 1	MAIN[2][28][20]
SATA_BURST_VAL bit 2	MAIN[2][29][20]
SATA_EIDLE_VAL bit 0	MAIN[2][28][24]
SATA_EIDLE_VAL bit 1	MAIN[2][29][24]
SATA_EIDLE_VAL bit 2	MAIN[2][28][25]
SP_REFCLK_CFG bit 0	MAIN[0][31][14]
SP_REFCLK_CFG bit 1	MAIN[0][30][15]
SP_REFCLK_CFG bit 2	MAIN[0][31][15]
TXPCSRESET_TIME bit 0	MAIN[1][29][58]
TXPCSRESET_TIME bit 1	MAIN[1][28][59]
TXPCSRESET_TIME bit 2	MAIN[1][29][59]
TXPCSRESET_TIME bit 3	MAIN[1][28][60]
TXPCSRESET_TIME bit 4	MAIN[1][29][60]
TXPH_MONITOR_SEL bit 0	MAIN[1][30][44]
TXPH_MONITOR_SEL bit 1	MAIN[1][31][44]
TXPH_MONITOR_SEL bit 2	MAIN[1][30][45]
TXPH_MONITOR_SEL bit 3	MAIN[1][31][45]
TXPH_MONITOR_SEL bit 4	MAIN[1][30][46]
TXPMARESET_TIME bit 0	MAIN[1][28][56]
TXPMARESET_TIME bit 1	MAIN[1][29][56]
TXPMARESET_TIME bit 2	MAIN[1][28][57]
TXPMARESET_TIME bit 3	MAIN[1][29][57]
TXPMARESET_TIME bit 4	MAIN[1][28][58]
TX_CLKMUX_PD bit 0	MAIN[2][31][0]
TX_EIDLE_ASSERT_DELAY bit 0	MAIN[3][28][11]
TX_EIDLE_ASSERT_DELAY bit 1	MAIN[3][29][11]
TX_EIDLE_ASSERT_DELAY bit 2	MAIN[3][28][12]
TX_EIDLE_DEASSERT_DELAY bit 0	MAIN[3][29][12]
TX_EIDLE_DEASSERT_DELAY bit 1	MAIN[3][28][13]
TX_EIDLE_DEASSERT_DELAY bit 2	MAIN[3][29][13]
TX_MAINCURSOR_SEL bit 0	MAIN[4][31][33]
TX_MARGIN_FULL_0 bit 0	MAIN[3][30][40]
TX_MARGIN_FULL_0 bit 1	MAIN[3][31][40]
TX_MARGIN_FULL_0 bit 2	MAIN[3][30][41]
TX_MARGIN_FULL_0 bit 3	MAIN[3][31][41]
TX_MARGIN_FULL_0 bit 4	MAIN[3][30][42]
TX_MARGIN_FULL_0 bit 5	MAIN[3][31][42]
TX_MARGIN_FULL_0 bit 6	MAIN[3][30][43]
TX_MARGIN_FULL_1 bit 0	MAIN[3][30][44]
TX_MARGIN_FULL_1 bit 1	MAIN[3][31][44]
TX_MARGIN_FULL_1 bit 2	MAIN[3][30][45]
TX_MARGIN_FULL_1 bit 3	MAIN[3][31][45]
TX_MARGIN_FULL_1 bit 4	MAIN[3][30][46]
TX_MARGIN_FULL_1 bit 5	MAIN[3][31][46]
TX_MARGIN_FULL_1 bit 6	MAIN[3][30][47]
TX_MARGIN_FULL_2 bit 0	MAIN[3][30][48]
TX_MARGIN_FULL_2 bit 1	MAIN[3][31][48]
TX_MARGIN_FULL_2 bit 2	MAIN[3][30][49]
TX_MARGIN_FULL_2 bit 3	MAIN[3][31][49]
TX_MARGIN_FULL_2 bit 4	MAIN[3][30][50]
TX_MARGIN_FULL_2 bit 5	MAIN[3][31][50]
TX_MARGIN_FULL_2 bit 6	MAIN[3][30][51]
TX_MARGIN_FULL_3 bit 0	MAIN[3][30][52]
TX_MARGIN_FULL_3 bit 1	MAIN[3][31][52]
TX_MARGIN_FULL_3 bit 2	MAIN[3][30][53]
TX_MARGIN_FULL_3 bit 3	MAIN[3][31][53]
TX_MARGIN_FULL_3 bit 4	MAIN[3][30][54]
TX_MARGIN_FULL_3 bit 5	MAIN[3][31][54]
TX_MARGIN_FULL_3 bit 6	MAIN[3][30][55]
TX_MARGIN_FULL_4 bit 0	MAIN[3][30][56]
TX_MARGIN_FULL_4 bit 1	MAIN[3][31][56]
TX_MARGIN_FULL_4 bit 2	MAIN[3][30][57]
TX_MARGIN_FULL_4 bit 3	MAIN[3][31][57]
TX_MARGIN_FULL_4 bit 4	MAIN[3][30][58]
TX_MARGIN_FULL_4 bit 5	MAIN[3][31][58]
TX_MARGIN_FULL_4 bit 6	MAIN[3][30][59]
TX_MARGIN_LOW_0 bit 0	MAIN[3][30][60]
TX_MARGIN_LOW_0 bit 1	MAIN[3][31][60]
TX_MARGIN_LOW_0 bit 2	MAIN[3][30][61]
TX_MARGIN_LOW_0 bit 3	MAIN[3][31][61]
TX_MARGIN_LOW_0 bit 4	MAIN[3][30][62]
TX_MARGIN_LOW_0 bit 5	MAIN[3][31][62]
TX_MARGIN_LOW_0 bit 6	MAIN[3][30][63]
TX_MARGIN_LOW_1 bit 0	MAIN[4][30][0]
TX_MARGIN_LOW_1 bit 1	MAIN[4][31][0]
TX_MARGIN_LOW_1 bit 2	MAIN[4][30][1]
TX_MARGIN_LOW_1 bit 3	MAIN[4][31][1]
TX_MARGIN_LOW_1 bit 4	MAIN[4][30][2]
TX_MARGIN_LOW_1 bit 5	MAIN[4][31][2]
TX_MARGIN_LOW_1 bit 6	MAIN[4][30][3]
TX_MARGIN_LOW_2 bit 0	MAIN[4][30][4]
TX_MARGIN_LOW_2 bit 1	MAIN[4][31][4]
TX_MARGIN_LOW_2 bit 2	MAIN[4][30][5]
TX_MARGIN_LOW_2 bit 3	MAIN[4][31][5]
TX_MARGIN_LOW_2 bit 4	MAIN[4][30][6]
TX_MARGIN_LOW_2 bit 5	MAIN[4][31][6]
TX_MARGIN_LOW_2 bit 6	MAIN[4][30][7]
TX_MARGIN_LOW_3 bit 0	MAIN[4][30][8]
TX_MARGIN_LOW_3 bit 1	MAIN[4][31][8]
TX_MARGIN_LOW_3 bit 2	MAIN[4][30][9]
TX_MARGIN_LOW_3 bit 3	MAIN[4][31][9]
TX_MARGIN_LOW_3 bit 4	MAIN[4][30][10]
TX_MARGIN_LOW_3 bit 5	MAIN[4][31][10]
TX_MARGIN_LOW_3 bit 6	MAIN[4][30][11]
TX_MARGIN_LOW_4 bit 0	MAIN[4][30][12]
TX_MARGIN_LOW_4 bit 1	MAIN[4][31][12]
TX_MARGIN_LOW_4 bit 2	MAIN[4][30][13]
TX_MARGIN_LOW_4 bit 3	MAIN[4][31][13]
TX_MARGIN_LOW_4 bit 4	MAIN[4][30][14]
TX_MARGIN_LOW_4 bit 5	MAIN[4][31][14]
TX_MARGIN_LOW_4 bit 6	MAIN[4][30][15]
TX_QPI_STATUS_EN bit 0	MAIN[2][31][31]
TX_RXDETECT_REF bit 0	MAIN[4][30][36]
TX_RXDETECT_REF bit 1	MAIN[4][31][36]
TX_RXDETECT_REF bit 2	MAIN[4][30][37]
UCODEER_CLR bit 0	MAIN[0][29][0]
TXOOB_CFG bit 0	MAIN[0][31][20]
TXPI_CFG0 bit 0	MAIN[0][30][40]
TXPI_CFG0 bit 1	MAIN[0][31][40]
TXPI_CFG1 bit 0	MAIN[0][30][41]
TXPI_CFG1 bit 1	MAIN[0][31][41]
TXPI_CFG2 bit 0	MAIN[0][30][42]
TXPI_CFG2 bit 1	MAIN[0][31][42]
TXPI_CFG3 bit 0	MAIN[0][30][43]
TXPI_CFG4 bit 0	MAIN[0][31][43]
TXPI_CFG5 bit 0	MAIN[0][30][44]
TXPI_CFG5 bit 1	MAIN[0][31][44]
TXPI_CFG5 bit 2	MAIN[0][30][45]
TXPI_GREY_SEL bit 0	MAIN[7][31][50]
TXPI_INVSTROBE_SEL bit 0	MAIN[7][30][50]
TXPI_PPM_CFG bit 0	MAIN[7][30][40]
TXPI_PPM_CFG bit 1	MAIN[7][31][40]
TXPI_PPM_CFG bit 2	MAIN[7][30][41]
TXPI_PPM_CFG bit 3	MAIN[7][31][41]
TXPI_PPM_CFG bit 4	MAIN[7][30][42]
TXPI_PPM_CFG bit 5	MAIN[7][31][42]
TXPI_PPM_CFG bit 6	MAIN[7][30][43]
TXPI_PPM_CFG bit 7	MAIN[7][31][43]
TXPI_SYNFREQ_PPM bit 0	MAIN[7][30][48]
TXPI_SYNFREQ_PPM bit 1	MAIN[7][31][48]
TXPI_SYNFREQ_PPM bit 2	MAIN[7][30][49]
TXSYNC_MULTILANE bit 0	MAIN[2][29][5]
TXSYNC_OVRD bit 0	MAIN[2][28][7]
TXSYNC_SKIP_DA bit 0	MAIN[2][29][6]
USE_PCS_CLK_PHASE_SEL bit 0	MAIN[7][30][15]
AMONITOR_CFG bit 0	MAIN[5][30][40]
AMONITOR_CFG bit 1	MAIN[5][31][40]
AMONITOR_CFG bit 2	MAIN[5][30][41]
AMONITOR_CFG bit 3	MAIN[5][31][41]
AMONITOR_CFG bit 4	MAIN[5][30][42]
AMONITOR_CFG bit 5	MAIN[5][31][42]
AMONITOR_CFG bit 6	MAIN[5][30][43]
AMONITOR_CFG bit 7	MAIN[5][31][43]
AMONITOR_CFG bit 8	MAIN[5][30][44]
AMONITOR_CFG bit 9	MAIN[5][31][44]
AMONITOR_CFG bit 10	MAIN[5][30][45]
AMONITOR_CFG bit 11	MAIN[5][31][45]
AMONITOR_CFG bit 12	MAIN[5][30][46]
AMONITOR_CFG bit 13	MAIN[5][31][46]
AMONITOR_CFG bit 14	MAIN[5][30][47]
AMONITOR_CFG bit 15	MAIN[5][31][47]
CPLL_INIT_CFG bit 0	MAIN[0][30][24]
CPLL_INIT_CFG bit 1	MAIN[0][31][24]
CPLL_INIT_CFG bit 2	MAIN[0][30][25]
CPLL_INIT_CFG bit 3	MAIN[0][31][25]
CPLL_INIT_CFG bit 4	MAIN[0][30][26]
CPLL_INIT_CFG bit 5	MAIN[0][31][26]
CPLL_INIT_CFG bit 6	MAIN[0][30][27]
CPLL_INIT_CFG bit 7	MAIN[0][31][27]
CPLL_INIT_CFG bit 8	MAIN[0][30][28]
CPLL_INIT_CFG bit 9	MAIN[0][31][28]
CPLL_INIT_CFG bit 10	MAIN[0][30][29]
CPLL_INIT_CFG bit 11	MAIN[0][31][29]
CPLL_INIT_CFG bit 12	MAIN[0][30][30]
CPLL_INIT_CFG bit 13	MAIN[0][31][30]
CPLL_INIT_CFG bit 14	MAIN[0][30][31]
CPLL_INIT_CFG bit 15	MAIN[0][31][31]
CPLL_INIT_CFG bit 16	MAIN[0][30][32]
CPLL_INIT_CFG bit 17	MAIN[0][31][32]
CPLL_INIT_CFG bit 18	MAIN[0][30][33]
CPLL_INIT_CFG bit 19	MAIN[0][31][33]
CPLL_INIT_CFG bit 20	MAIN[0][30][34]
CPLL_INIT_CFG bit 21	MAIN[0][31][34]
CPLL_INIT_CFG bit 22	MAIN[0][30][35]
CPLL_INIT_CFG bit 23	MAIN[0][31][35]
CPLL_LOCK_CFG bit 0	MAIN[0][30][56]
CPLL_LOCK_CFG bit 1	MAIN[0][31][56]
CPLL_LOCK_CFG bit 2	MAIN[0][30][57]
CPLL_LOCK_CFG bit 3	MAIN[0][31][57]
CPLL_LOCK_CFG bit 4	MAIN[0][30][58]
CPLL_LOCK_CFG bit 5	MAIN[0][31][58]
CPLL_LOCK_CFG bit 6	MAIN[0][30][59]
CPLL_LOCK_CFG bit 7	MAIN[0][31][59]
CPLL_LOCK_CFG bit 8	MAIN[0][30][60]
CPLL_LOCK_CFG bit 9	MAIN[0][31][60]
CPLL_LOCK_CFG bit 10	MAIN[0][30][61]
CPLL_LOCK_CFG bit 11	MAIN[0][31][61]
CPLL_LOCK_CFG bit 12	MAIN[0][30][62]
CPLL_LOCK_CFG bit 13	MAIN[0][31][62]
CPLL_LOCK_CFG bit 14	MAIN[0][30][63]
CPLL_LOCK_CFG bit 15	MAIN[0][31][63]
DMONITOR_CFG bit 0	MAIN[5][30][48]
DMONITOR_CFG bit 1	MAIN[5][31][48]
DMONITOR_CFG bit 2	MAIN[5][30][49]
DMONITOR_CFG bit 3	MAIN[5][31][49]
DMONITOR_CFG bit 4	MAIN[5][30][50]
DMONITOR_CFG bit 5	MAIN[5][31][50]
DMONITOR_CFG bit 6	MAIN[5][30][51]
DMONITOR_CFG bit 7	MAIN[5][31][51]
DMONITOR_CFG bit 8	MAIN[5][30][52]
DMONITOR_CFG bit 9	MAIN[5][31][52]
DMONITOR_CFG bit 10	MAIN[5][30][53]
DMONITOR_CFG bit 11	MAIN[5][31][53]
DMONITOR_CFG bit 12	MAIN[5][30][54]
DMONITOR_CFG bit 13	MAIN[5][31][54]
DMONITOR_CFG bit 14	MAIN[5][30][55]
DMONITOR_CFG bit 15	MAIN[5][31][55]
DMONITOR_CFG bit 16	MAIN[5][30][56]
DMONITOR_CFG bit 17	MAIN[5][31][56]
DMONITOR_CFG bit 18	MAIN[5][30][57]
DMONITOR_CFG bit 19	MAIN[5][31][57]
DMONITOR_CFG bit 20	MAIN[5][30][58]
DMONITOR_CFG bit 21	MAIN[5][31][58]
DMONITOR_CFG bit 22	MAIN[5][30][59]
DMONITOR_CFG bit 23	MAIN[5][31][59]
ES_HORZ_OFFSET bit 0	MAIN[7][28][32]
ES_HORZ_OFFSET bit 1	MAIN[7][29][32]
ES_HORZ_OFFSET bit 2	MAIN[7][28][33]
ES_HORZ_OFFSET bit 3	MAIN[7][29][33]
ES_HORZ_OFFSET bit 4	MAIN[7][28][34]
ES_HORZ_OFFSET bit 5	MAIN[7][29][34]
ES_HORZ_OFFSET bit 6	MAIN[7][28][35]
ES_HORZ_OFFSET bit 7	MAIN[7][29][35]
ES_HORZ_OFFSET bit 8	MAIN[7][28][36]
ES_HORZ_OFFSET bit 9	MAIN[7][29][36]
ES_HORZ_OFFSET bit 10	MAIN[7][28][37]
ES_HORZ_OFFSET bit 11	MAIN[7][29][37]
ES_QUALIFIER bit 0	MAIN[5][28][32]
ES_QUALIFIER bit 1	MAIN[5][29][32]
ES_QUALIFIER bit 2	MAIN[5][28][33]
ES_QUALIFIER bit 3	MAIN[5][29][33]
ES_QUALIFIER bit 4	MAIN[5][28][34]
ES_QUALIFIER bit 5	MAIN[5][29][34]
ES_QUALIFIER bit 6	MAIN[5][28][35]
ES_QUALIFIER bit 7	MAIN[5][29][35]
ES_QUALIFIER bit 8	MAIN[5][28][36]
ES_QUALIFIER bit 9	MAIN[5][29][36]
ES_QUALIFIER bit 10	MAIN[5][28][37]
ES_QUALIFIER bit 11	MAIN[5][29][37]
ES_QUALIFIER bit 12	MAIN[5][28][38]
ES_QUALIFIER bit 13	MAIN[5][29][38]
ES_QUALIFIER bit 14	MAIN[5][28][39]
ES_QUALIFIER bit 15	MAIN[5][29][39]
ES_QUALIFIER bit 16	MAIN[5][28][40]
ES_QUALIFIER bit 17	MAIN[5][29][40]
ES_QUALIFIER bit 18	MAIN[5][28][41]
ES_QUALIFIER bit 19	MAIN[5][29][41]
ES_QUALIFIER bit 20	MAIN[5][28][42]
ES_QUALIFIER bit 21	MAIN[5][29][42]
ES_QUALIFIER bit 22	MAIN[5][28][43]
ES_QUALIFIER bit 23	MAIN[5][29][43]
ES_QUALIFIER bit 24	MAIN[5][28][44]
ES_QUALIFIER bit 25	MAIN[5][29][44]
ES_QUALIFIER bit 26	MAIN[5][28][45]
ES_QUALIFIER bit 27	MAIN[5][29][45]
ES_QUALIFIER bit 28	MAIN[5][28][46]
ES_QUALIFIER bit 29	MAIN[5][29][46]
ES_QUALIFIER bit 30	MAIN[5][28][47]
ES_QUALIFIER bit 31	MAIN[5][29][47]
ES_QUALIFIER bit 32	MAIN[5][28][48]
ES_QUALIFIER bit 33	MAIN[5][29][48]
ES_QUALIFIER bit 34	MAIN[5][28][49]
ES_QUALIFIER bit 35	MAIN[5][29][49]
ES_QUALIFIER bit 36	MAIN[5][28][50]
ES_QUALIFIER bit 37	MAIN[5][29][50]
ES_QUALIFIER bit 38	MAIN[5][28][51]
ES_QUALIFIER bit 39	MAIN[5][29][51]
ES_QUALIFIER bit 40	MAIN[5][28][52]
ES_QUALIFIER bit 41	MAIN[5][29][52]
ES_QUALIFIER bit 42	MAIN[5][28][53]
ES_QUALIFIER bit 43	MAIN[5][29][53]
ES_QUALIFIER bit 44	MAIN[5][28][54]
ES_QUALIFIER bit 45	MAIN[5][29][54]
ES_QUALIFIER bit 46	MAIN[5][28][55]
ES_QUALIFIER bit 47	MAIN[5][29][55]
ES_QUALIFIER bit 48	MAIN[5][28][56]
ES_QUALIFIER bit 49	MAIN[5][29][56]
ES_QUALIFIER bit 50	MAIN[5][28][57]
ES_QUALIFIER bit 51	MAIN[5][29][57]
ES_QUALIFIER bit 52	MAIN[5][28][58]
ES_QUALIFIER bit 53	MAIN[5][29][58]
ES_QUALIFIER bit 54	MAIN[5][28][59]
ES_QUALIFIER bit 55	MAIN[5][29][59]
ES_QUALIFIER bit 56	MAIN[5][28][60]
ES_QUALIFIER bit 57	MAIN[5][29][60]
ES_QUALIFIER bit 58	MAIN[5][28][61]
ES_QUALIFIER bit 59	MAIN[5][29][61]
ES_QUALIFIER bit 60	MAIN[5][28][62]
ES_QUALIFIER bit 61	MAIN[5][29][62]
ES_QUALIFIER bit 62	MAIN[5][28][63]
ES_QUALIFIER bit 63	MAIN[5][29][63]
ES_QUALIFIER bit 64	MAIN[6][28][0]
ES_QUALIFIER bit 65	MAIN[6][29][0]
ES_QUALIFIER bit 66	MAIN[6][28][1]
ES_QUALIFIER bit 67	MAIN[6][29][1]
ES_QUALIFIER bit 68	MAIN[6][28][2]
ES_QUALIFIER bit 69	MAIN[6][29][2]
ES_QUALIFIER bit 70	MAIN[6][28][3]
ES_QUALIFIER bit 71	MAIN[6][29][3]
ES_QUALIFIER bit 72	MAIN[6][28][4]
ES_QUALIFIER bit 73	MAIN[6][29][4]
ES_QUALIFIER bit 74	MAIN[6][28][5]
ES_QUALIFIER bit 75	MAIN[6][29][5]
ES_QUALIFIER bit 76	MAIN[6][28][6]
ES_QUALIFIER bit 77	MAIN[6][29][6]
ES_QUALIFIER bit 78	MAIN[6][28][7]
ES_QUALIFIER bit 79	MAIN[6][29][7]
ES_QUAL_MASK bit 0	MAIN[6][28][8]
ES_QUAL_MASK bit 1	MAIN[6][29][8]
ES_QUAL_MASK bit 2	MAIN[6][28][9]
ES_QUAL_MASK bit 3	MAIN[6][29][9]
ES_QUAL_MASK bit 4	MAIN[6][28][10]
ES_QUAL_MASK bit 5	MAIN[6][29][10]
ES_QUAL_MASK bit 6	MAIN[6][28][11]
ES_QUAL_MASK bit 7	MAIN[6][29][11]
ES_QUAL_MASK bit 8	MAIN[6][28][12]
ES_QUAL_MASK bit 9	MAIN[6][29][12]
ES_QUAL_MASK bit 10	MAIN[6][28][13]
ES_QUAL_MASK bit 11	MAIN[6][29][13]
ES_QUAL_MASK bit 12	MAIN[6][28][14]
ES_QUAL_MASK bit 13	MAIN[6][29][14]
ES_QUAL_MASK bit 14	MAIN[6][28][15]
ES_QUAL_MASK bit 15	MAIN[6][29][15]
ES_QUAL_MASK bit 16	MAIN[6][28][16]
ES_QUAL_MASK bit 17	MAIN[6][29][16]
ES_QUAL_MASK bit 18	MAIN[6][28][17]
ES_QUAL_MASK bit 19	MAIN[6][29][17]
ES_QUAL_MASK bit 20	MAIN[6][28][18]
ES_QUAL_MASK bit 21	MAIN[6][29][18]
ES_QUAL_MASK bit 22	MAIN[6][28][19]
ES_QUAL_MASK bit 23	MAIN[6][29][19]
ES_QUAL_MASK bit 24	MAIN[6][28][20]
ES_QUAL_MASK bit 25	MAIN[6][29][20]
ES_QUAL_MASK bit 26	MAIN[6][28][21]
ES_QUAL_MASK bit 27	MAIN[6][29][21]
ES_QUAL_MASK bit 28	MAIN[6][28][22]
ES_QUAL_MASK bit 29	MAIN[6][29][22]
ES_QUAL_MASK bit 30	MAIN[6][28][23]
ES_QUAL_MASK bit 31	MAIN[6][29][23]
ES_QUAL_MASK bit 32	MAIN[6][28][24]
ES_QUAL_MASK bit 33	MAIN[6][29][24]
ES_QUAL_MASK bit 34	MAIN[6][28][25]
ES_QUAL_MASK bit 35	MAIN[6][29][25]
ES_QUAL_MASK bit 36	MAIN[6][28][26]
ES_QUAL_MASK bit 37	MAIN[6][29][26]
ES_QUAL_MASK bit 38	MAIN[6][28][27]
ES_QUAL_MASK bit 39	MAIN[6][29][27]
ES_QUAL_MASK bit 40	MAIN[6][28][28]
ES_QUAL_MASK bit 41	MAIN[6][29][28]
ES_QUAL_MASK bit 42	MAIN[6][28][29]
ES_QUAL_MASK bit 43	MAIN[6][29][29]
ES_QUAL_MASK bit 44	MAIN[6][28][30]
ES_QUAL_MASK bit 45	MAIN[6][29][30]
ES_QUAL_MASK bit 46	MAIN[6][28][31]
ES_QUAL_MASK bit 47	MAIN[6][29][31]
ES_QUAL_MASK bit 48	MAIN[6][28][32]
ES_QUAL_MASK bit 49	MAIN[6][29][32]
ES_QUAL_MASK bit 50	MAIN[6][28][33]
ES_QUAL_MASK bit 51	MAIN[6][29][33]
ES_QUAL_MASK bit 52	MAIN[6][28][34]
ES_QUAL_MASK bit 53	MAIN[6][29][34]
ES_QUAL_MASK bit 54	MAIN[6][28][35]
ES_QUAL_MASK bit 55	MAIN[6][29][35]
ES_QUAL_MASK bit 56	MAIN[6][28][36]
ES_QUAL_MASK bit 57	MAIN[6][29][36]
ES_QUAL_MASK bit 58	MAIN[6][28][37]
ES_QUAL_MASK bit 59	MAIN[6][29][37]
ES_QUAL_MASK bit 60	MAIN[6][28][38]
ES_QUAL_MASK bit 61	MAIN[6][29][38]
ES_QUAL_MASK bit 62	MAIN[6][28][39]
ES_QUAL_MASK bit 63	MAIN[6][29][39]
ES_QUAL_MASK bit 64	MAIN[6][28][40]
ES_QUAL_MASK bit 65	MAIN[6][29][40]
ES_QUAL_MASK bit 66	MAIN[6][28][41]
ES_QUAL_MASK bit 67	MAIN[6][29][41]
ES_QUAL_MASK bit 68	MAIN[6][28][42]
ES_QUAL_MASK bit 69	MAIN[6][29][42]
ES_QUAL_MASK bit 70	MAIN[6][28][43]
ES_QUAL_MASK bit 71	MAIN[6][29][43]
ES_QUAL_MASK bit 72	MAIN[6][28][44]
ES_QUAL_MASK bit 73	MAIN[6][29][44]
ES_QUAL_MASK bit 74	MAIN[6][28][45]
ES_QUAL_MASK bit 75	MAIN[6][29][45]
ES_QUAL_MASK bit 76	MAIN[6][28][46]
ES_QUAL_MASK bit 77	MAIN[6][29][46]
ES_QUAL_MASK bit 78	MAIN[6][28][47]
ES_QUAL_MASK bit 79	MAIN[6][29][47]
ES_SDATA_MASK bit 0	MAIN[6][28][48]
ES_SDATA_MASK bit 1	MAIN[6][29][48]
ES_SDATA_MASK bit 2	MAIN[6][28][49]
ES_SDATA_MASK bit 3	MAIN[6][29][49]
ES_SDATA_MASK bit 4	MAIN[6][28][50]
ES_SDATA_MASK bit 5	MAIN[6][29][50]
ES_SDATA_MASK bit 6	MAIN[6][28][51]
ES_SDATA_MASK bit 7	MAIN[6][29][51]
ES_SDATA_MASK bit 8	MAIN[6][28][52]
ES_SDATA_MASK bit 9	MAIN[6][29][52]
ES_SDATA_MASK bit 10	MAIN[6][28][53]
ES_SDATA_MASK bit 11	MAIN[6][29][53]
ES_SDATA_MASK bit 12	MAIN[6][28][54]
ES_SDATA_MASK bit 13	MAIN[6][29][54]
ES_SDATA_MASK bit 14	MAIN[6][28][55]
ES_SDATA_MASK bit 15	MAIN[6][29][55]
ES_SDATA_MASK bit 16	MAIN[6][28][56]
ES_SDATA_MASK bit 17	MAIN[6][29][56]
ES_SDATA_MASK bit 18	MAIN[6][28][57]
ES_SDATA_MASK bit 19	MAIN[6][29][57]
ES_SDATA_MASK bit 20	MAIN[6][28][58]
ES_SDATA_MASK bit 21	MAIN[6][29][58]
ES_SDATA_MASK bit 22	MAIN[6][28][59]
ES_SDATA_MASK bit 23	MAIN[6][29][59]
ES_SDATA_MASK bit 24	MAIN[6][28][60]
ES_SDATA_MASK bit 25	MAIN[6][29][60]
ES_SDATA_MASK bit 26	MAIN[6][28][61]
ES_SDATA_MASK bit 27	MAIN[6][29][61]
ES_SDATA_MASK bit 28	MAIN[6][28][62]
ES_SDATA_MASK bit 29	MAIN[6][29][62]
ES_SDATA_MASK bit 30	MAIN[6][28][63]
ES_SDATA_MASK bit 31	MAIN[6][29][63]
ES_SDATA_MASK bit 32	MAIN[7][28][0]
ES_SDATA_MASK bit 33	MAIN[7][29][0]
ES_SDATA_MASK bit 34	MAIN[7][28][1]
ES_SDATA_MASK bit 35	MAIN[7][29][1]
ES_SDATA_MASK bit 36	MAIN[7][28][2]
ES_SDATA_MASK bit 37	MAIN[7][29][2]
ES_SDATA_MASK bit 38	MAIN[7][28][3]
ES_SDATA_MASK bit 39	MAIN[7][29][3]
ES_SDATA_MASK bit 40	MAIN[7][28][4]
ES_SDATA_MASK bit 41	MAIN[7][29][4]
ES_SDATA_MASK bit 42	MAIN[7][28][5]
ES_SDATA_MASK bit 43	MAIN[7][29][5]
ES_SDATA_MASK bit 44	MAIN[7][28][6]
ES_SDATA_MASK bit 45	MAIN[7][29][6]
ES_SDATA_MASK bit 46	MAIN[7][28][7]
ES_SDATA_MASK bit 47	MAIN[7][29][7]
ES_SDATA_MASK bit 48	MAIN[7][28][8]
ES_SDATA_MASK bit 49	MAIN[7][29][8]
ES_SDATA_MASK bit 50	MAIN[7][28][9]
ES_SDATA_MASK bit 51	MAIN[7][29][9]
ES_SDATA_MASK bit 52	MAIN[7][28][10]
ES_SDATA_MASK bit 53	MAIN[7][29][10]
ES_SDATA_MASK bit 54	MAIN[7][28][11]
ES_SDATA_MASK bit 55	MAIN[7][29][11]
ES_SDATA_MASK bit 56	MAIN[7][28][12]
ES_SDATA_MASK bit 57	MAIN[7][29][12]
ES_SDATA_MASK bit 58	MAIN[7][28][13]
ES_SDATA_MASK bit 59	MAIN[7][29][13]
ES_SDATA_MASK bit 60	MAIN[7][28][14]
ES_SDATA_MASK bit 61	MAIN[7][29][14]
ES_SDATA_MASK bit 62	MAIN[7][28][15]
ES_SDATA_MASK bit 63	MAIN[7][29][15]
ES_SDATA_MASK bit 64	MAIN[7][28][16]
ES_SDATA_MASK bit 65	MAIN[7][29][16]
ES_SDATA_MASK bit 66	MAIN[7][28][17]
ES_SDATA_MASK bit 67	MAIN[7][29][17]
ES_SDATA_MASK bit 68	MAIN[7][28][18]
ES_SDATA_MASK bit 69	MAIN[7][29][18]
ES_SDATA_MASK bit 70	MAIN[7][28][19]
ES_SDATA_MASK bit 71	MAIN[7][29][19]
ES_SDATA_MASK bit 72	MAIN[7][28][20]
ES_SDATA_MASK bit 73	MAIN[7][29][20]
ES_SDATA_MASK bit 74	MAIN[7][28][21]
ES_SDATA_MASK bit 75	MAIN[7][29][21]
ES_SDATA_MASK bit 76	MAIN[7][28][22]
ES_SDATA_MASK bit 77	MAIN[7][29][22]
ES_SDATA_MASK bit 78	MAIN[7][28][23]
ES_SDATA_MASK bit 79	MAIN[7][29][23]
PCS_RSVD_ATTR bit 0	MAIN[2][30][56]
PCS_RSVD_ATTR bit 1	MAIN[2][31][56]
PCS_RSVD_ATTR bit 2	MAIN[2][30][57]
PCS_RSVD_ATTR bit 3	MAIN[2][31][57]
PCS_RSVD_ATTR bit 4	MAIN[2][30][58]
PCS_RSVD_ATTR bit 5	MAIN[2][31][58]
PCS_RSVD_ATTR bit 6	MAIN[2][30][59]
PCS_RSVD_ATTR bit 7	MAIN[2][31][59]
PCS_RSVD_ATTR bit 8	MAIN[2][30][60]
PCS_RSVD_ATTR bit 9	MAIN[2][31][60]
PCS_RSVD_ATTR bit 10	MAIN[2][30][61]
PCS_RSVD_ATTR bit 11	MAIN[2][31][61]
PCS_RSVD_ATTR bit 12	MAIN[2][30][62]
PCS_RSVD_ATTR bit 13	MAIN[2][31][62]
PCS_RSVD_ATTR bit 14	MAIN[2][30][63]
PCS_RSVD_ATTR bit 15	MAIN[2][31][63]
PCS_RSVD_ATTR bit 16	MAIN[3][30][0]
PCS_RSVD_ATTR bit 17	MAIN[3][31][0]
PCS_RSVD_ATTR bit 18	MAIN[3][30][1]
PCS_RSVD_ATTR bit 19	MAIN[3][31][1]
PCS_RSVD_ATTR bit 20	MAIN[3][30][2]
PCS_RSVD_ATTR bit 21	MAIN[3][31][2]
PCS_RSVD_ATTR bit 22	MAIN[3][30][3]
PCS_RSVD_ATTR bit 23	MAIN[3][31][3]
PCS_RSVD_ATTR bit 24	MAIN[3][30][4]
PCS_RSVD_ATTR bit 25	MAIN[3][31][4]
PCS_RSVD_ATTR bit 26	MAIN[3][30][5]
PCS_RSVD_ATTR bit 27	MAIN[3][31][5]
PCS_RSVD_ATTR bit 28	MAIN[3][30][6]
PCS_RSVD_ATTR bit 29	MAIN[3][31][6]
PCS_RSVD_ATTR bit 30	MAIN[3][30][7]
PCS_RSVD_ATTR bit 31	MAIN[3][31][7]
PCS_RSVD_ATTR bit 32	MAIN[3][30][8]
PCS_RSVD_ATTR bit 33	MAIN[3][31][8]
PCS_RSVD_ATTR bit 34	MAIN[3][30][9]
PCS_RSVD_ATTR bit 35	MAIN[3][31][9]
PCS_RSVD_ATTR bit 36	MAIN[3][30][10]
PCS_RSVD_ATTR bit 37	MAIN[3][31][10]
PCS_RSVD_ATTR bit 38	MAIN[3][30][11]
PCS_RSVD_ATTR bit 39	MAIN[3][31][11]
PCS_RSVD_ATTR bit 40	MAIN[3][30][12]
PCS_RSVD_ATTR bit 41	MAIN[3][31][12]
PCS_RSVD_ATTR bit 42	MAIN[3][30][13]
PCS_RSVD_ATTR bit 43	MAIN[3][31][13]
PCS_RSVD_ATTR bit 44	MAIN[3][30][14]
PCS_RSVD_ATTR bit 45	MAIN[3][31][14]
PCS_RSVD_ATTR bit 46	MAIN[3][30][15]
PCS_RSVD_ATTR bit 47	MAIN[3][31][15]
PD_TRANS_TIME_FROM_P2 bit 0	MAIN[3][29][24]
PD_TRANS_TIME_FROM_P2 bit 1	MAIN[3][28][25]
PD_TRANS_TIME_FROM_P2 bit 2	MAIN[3][29][25]
PD_TRANS_TIME_FROM_P2 bit 3	MAIN[3][28][26]
PD_TRANS_TIME_FROM_P2 bit 4	MAIN[3][29][26]
PD_TRANS_TIME_FROM_P2 bit 5	MAIN[3][28][27]
PD_TRANS_TIME_FROM_P2 bit 6	MAIN[3][29][27]
PD_TRANS_TIME_FROM_P2 bit 7	MAIN[3][28][28]
PD_TRANS_TIME_FROM_P2 bit 8	MAIN[3][29][28]
PD_TRANS_TIME_FROM_P2 bit 9	MAIN[3][28][29]
PD_TRANS_TIME_FROM_P2 bit 10	MAIN[3][29][29]
PD_TRANS_TIME_FROM_P2 bit 11	MAIN[3][28][30]
PD_TRANS_TIME_NONE_P2 bit 0	MAIN[3][28][16]
PD_TRANS_TIME_NONE_P2 bit 1	MAIN[3][29][16]
PD_TRANS_TIME_NONE_P2 bit 2	MAIN[3][28][17]
PD_TRANS_TIME_NONE_P2 bit 3	MAIN[3][29][17]
PD_TRANS_TIME_NONE_P2 bit 4	MAIN[3][28][18]
PD_TRANS_TIME_NONE_P2 bit 5	MAIN[3][29][18]
PD_TRANS_TIME_NONE_P2 bit 6	MAIN[3][28][19]
PD_TRANS_TIME_NONE_P2 bit 7	MAIN[3][29][19]
PD_TRANS_TIME_TO_P2 bit 0	MAIN[3][28][20]
PD_TRANS_TIME_TO_P2 bit 1	MAIN[3][29][20]
PD_TRANS_TIME_TO_P2 bit 2	MAIN[3][28][21]
PD_TRANS_TIME_TO_P2 bit 3	MAIN[3][29][21]
PD_TRANS_TIME_TO_P2 bit 4	MAIN[3][28][22]
PD_TRANS_TIME_TO_P2 bit 5	MAIN[3][29][22]
PD_TRANS_TIME_TO_P2 bit 6	MAIN[3][28][23]
PD_TRANS_TIME_TO_P2 bit 7	MAIN[3][29][23]
RXDLY_CFG bit 0	MAIN[10][28][40]
RXDLY_CFG bit 1	MAIN[10][29][40]
RXDLY_CFG bit 2	MAIN[10][28][41]
RXDLY_CFG bit 3	MAIN[10][29][41]
RXDLY_CFG bit 4	MAIN[10][28][42]
RXDLY_CFG bit 5	MAIN[10][29][42]
RXDLY_CFG bit 6	MAIN[10][28][43]
RXDLY_CFG bit 7	MAIN[10][29][43]
RXDLY_CFG bit 8	MAIN[10][28][44]
RXDLY_CFG bit 9	MAIN[10][29][44]
RXDLY_CFG bit 10	MAIN[10][28][45]
RXDLY_CFG bit 11	MAIN[10][29][45]
RXDLY_CFG bit 12	MAIN[10][28][46]
RXDLY_CFG bit 13	MAIN[10][29][46]
RXDLY_CFG bit 14	MAIN[10][28][47]
RXDLY_CFG bit 15	MAIN[10][29][47]
RXDLY_LCFG bit 0	MAIN[9][30][0]
RXDLY_LCFG bit 1	MAIN[9][31][0]
RXDLY_LCFG bit 2	MAIN[9][30][1]
RXDLY_LCFG bit 3	MAIN[9][31][1]
RXDLY_LCFG bit 4	MAIN[9][30][2]
RXDLY_LCFG bit 5	MAIN[9][31][2]
RXDLY_LCFG bit 6	MAIN[9][30][3]
RXDLY_LCFG bit 7	MAIN[9][31][3]
RXDLY_LCFG bit 8	MAIN[9][30][4]
RXDLY_TAP_CFG bit 0	MAIN[10][28][32]
RXDLY_TAP_CFG bit 1	MAIN[10][29][32]
RXDLY_TAP_CFG bit 2	MAIN[10][28][33]
RXDLY_TAP_CFG bit 3	MAIN[10][29][33]
RXDLY_TAP_CFG bit 4	MAIN[10][28][34]
RXDLY_TAP_CFG bit 5	MAIN[10][29][34]
RXDLY_TAP_CFG bit 6	MAIN[10][28][35]
RXDLY_TAP_CFG bit 7	MAIN[10][29][35]
RXDLY_TAP_CFG bit 8	MAIN[10][28][36]
RXDLY_TAP_CFG bit 9	MAIN[10][29][36]
RXDLY_TAP_CFG bit 10	MAIN[10][28][37]
RXDLY_TAP_CFG bit 11	MAIN[10][29][37]
RXDLY_TAP_CFG bit 12	MAIN[10][28][38]
RXDLY_TAP_CFG bit 13	MAIN[10][29][38]
RXDLY_TAP_CFG bit 14	MAIN[10][28][39]
RXDLY_TAP_CFG bit 15	MAIN[10][29][39]
RXPHDLY_CFG bit 0	MAIN[9][30][24]
RXPHDLY_CFG bit 1	MAIN[9][31][24]
RXPHDLY_CFG bit 2	MAIN[9][30][25]
RXPHDLY_CFG bit 3	MAIN[9][31][25]
RXPHDLY_CFG bit 4	MAIN[9][30][26]
RXPHDLY_CFG bit 5	MAIN[9][31][26]
RXPHDLY_CFG bit 6	MAIN[9][30][27]
RXPHDLY_CFG bit 7	MAIN[9][31][27]
RXPHDLY_CFG bit 8	MAIN[9][30][28]
RXPHDLY_CFG bit 9	MAIN[9][31][28]
RXPHDLY_CFG bit 10	MAIN[9][30][29]
RXPHDLY_CFG bit 11	MAIN[9][31][29]
RXPHDLY_CFG bit 12	MAIN[9][30][30]
RXPHDLY_CFG bit 13	MAIN[9][31][30]
RXPHDLY_CFG bit 14	MAIN[9][30][31]
RXPHDLY_CFG bit 15	MAIN[9][31][31]
RXPHDLY_CFG bit 16	MAIN[9][30][32]
RXPHDLY_CFG bit 17	MAIN[9][31][32]
RXPHDLY_CFG bit 18	MAIN[9][30][33]
RXPHDLY_CFG bit 19	MAIN[9][31][33]
RXPHDLY_CFG bit 20	MAIN[9][30][34]
RXPHDLY_CFG bit 21	MAIN[9][31][34]
RXPHDLY_CFG bit 22	MAIN[9][30][35]
RXPHDLY_CFG bit 23	MAIN[9][31][35]
RXPH_CFG bit 0	MAIN[9][30][8]
RXPH_CFG bit 1	MAIN[9][31][8]
RXPH_CFG bit 2	MAIN[9][30][9]
RXPH_CFG bit 3	MAIN[9][31][9]
RXPH_CFG bit 4	MAIN[9][30][10]
RXPH_CFG bit 5	MAIN[9][31][10]
RXPH_CFG bit 6	MAIN[9][30][11]
RXPH_CFG bit 7	MAIN[9][31][11]
RXPH_CFG bit 8	MAIN[9][30][12]
RXPH_CFG bit 9	MAIN[9][31][12]
RXPH_CFG bit 10	MAIN[9][30][13]
RXPH_CFG bit 11	MAIN[9][31][13]
RXPH_CFG bit 12	MAIN[9][30][14]
RXPH_CFG bit 13	MAIN[9][31][14]
RXPH_CFG bit 14	MAIN[9][30][15]
RXPH_CFG bit 15	MAIN[9][31][15]
RXPH_CFG bit 16	MAIN[9][30][16]
RXPH_CFG bit 17	MAIN[9][31][16]
RXPH_CFG bit 18	MAIN[9][30][17]
RXPH_CFG bit 19	MAIN[9][31][17]
RXPH_CFG bit 20	MAIN[9][30][18]
RXPH_CFG bit 21	MAIN[9][31][18]
RXPH_CFG bit 22	MAIN[9][30][19]
RXPH_CFG bit 23	MAIN[9][31][19]
RX_DFE_GAIN_CFG bit 0	MAIN[3][28][40]
RX_DFE_GAIN_CFG bit 1	MAIN[3][29][40]
RX_DFE_GAIN_CFG bit 2	MAIN[3][28][41]
RX_DFE_GAIN_CFG bit 3	MAIN[3][29][41]
RX_DFE_GAIN_CFG bit 4	MAIN[3][28][42]
RX_DFE_GAIN_CFG bit 5	MAIN[3][29][42]
RX_DFE_GAIN_CFG bit 6	MAIN[3][28][43]
RX_DFE_GAIN_CFG bit 7	MAIN[3][29][43]
RX_DFE_GAIN_CFG bit 8	MAIN[3][28][44]
RX_DFE_GAIN_CFG bit 9	MAIN[3][29][44]
RX_DFE_GAIN_CFG bit 10	MAIN[3][28][45]
RX_DFE_GAIN_CFG bit 11	MAIN[3][29][45]
RX_DFE_GAIN_CFG bit 12	MAIN[3][28][46]
RX_DFE_GAIN_CFG bit 13	MAIN[3][29][46]
RX_DFE_GAIN_CFG bit 14	MAIN[3][28][47]
RX_DFE_GAIN_CFG bit 15	MAIN[3][29][47]
RX_DFE_GAIN_CFG bit 16	MAIN[3][28][48]
RX_DFE_GAIN_CFG bit 17	MAIN[3][29][48]
RX_DFE_GAIN_CFG bit 18	MAIN[3][28][49]
RX_DFE_GAIN_CFG bit 19	MAIN[3][29][49]
RX_DFE_GAIN_CFG bit 20	MAIN[3][28][50]
RX_DFE_GAIN_CFG bit 21	MAIN[3][29][50]
RX_DFE_GAIN_CFG bit 22	MAIN[3][28][51]
RX_DFE_LPM_CFG bit 0	MAIN[5][28][8]
RX_DFE_LPM_CFG bit 1	MAIN[5][29][8]
RX_DFE_LPM_CFG bit 2	MAIN[5][28][9]
RX_DFE_LPM_CFG bit 3	MAIN[5][29][9]
RX_DFE_LPM_CFG bit 4	MAIN[5][28][10]
RX_DFE_LPM_CFG bit 5	MAIN[5][29][10]
RX_DFE_LPM_CFG bit 6	MAIN[5][28][11]
RX_DFE_LPM_CFG bit 7	MAIN[5][29][11]
RX_DFE_LPM_CFG bit 8	MAIN[5][28][12]
RX_DFE_LPM_CFG bit 9	MAIN[5][29][12]
RX_DFE_LPM_CFG bit 10	MAIN[5][28][13]
RX_DFE_LPM_CFG bit 11	MAIN[5][29][13]
RX_DFE_LPM_CFG bit 12	MAIN[5][28][14]
RX_DFE_LPM_CFG bit 13	MAIN[5][29][14]
RX_DFE_LPM_CFG bit 14	MAIN[5][28][15]
RX_DFE_LPM_CFG bit 15	MAIN[5][29][15]
TRANS_TIME_RATE bit 0	MAIN[3][28][0]
TRANS_TIME_RATE bit 1	MAIN[3][29][0]
TRANS_TIME_RATE bit 2	MAIN[3][28][1]
TRANS_TIME_RATE bit 3	MAIN[3][29][1]
TRANS_TIME_RATE bit 4	MAIN[3][28][2]
TRANS_TIME_RATE bit 5	MAIN[3][29][2]
TRANS_TIME_RATE bit 6	MAIN[3][28][3]
TRANS_TIME_RATE bit 7	MAIN[3][29][3]
TST_RSV bit 0	MAIN[7][30][56]
TST_RSV bit 1	MAIN[7][31][56]
TST_RSV bit 2	MAIN[7][30][57]
TST_RSV bit 3	MAIN[7][31][57]
TST_RSV bit 4	MAIN[7][30][58]
TST_RSV bit 5	MAIN[7][31][58]
TST_RSV bit 6	MAIN[7][30][59]
TST_RSV bit 7	MAIN[7][31][59]
TST_RSV bit 8	MAIN[7][30][60]
TST_RSV bit 9	MAIN[7][31][60]
TST_RSV bit 10	MAIN[7][30][61]
TST_RSV bit 11	MAIN[7][31][61]
TST_RSV bit 12	MAIN[7][30][62]
TST_RSV bit 13	MAIN[7][31][62]
TST_RSV bit 14	MAIN[7][30][63]
TST_RSV bit 15	MAIN[7][31][63]
TST_RSV bit 16	MAIN[8][30][0]
TST_RSV bit 17	MAIN[8][31][0]
TST_RSV bit 18	MAIN[8][30][1]
TST_RSV bit 19	MAIN[8][31][1]
TST_RSV bit 20	MAIN[8][30][2]
TST_RSV bit 21	MAIN[8][31][2]
TST_RSV bit 22	MAIN[8][30][3]
TST_RSV bit 23	MAIN[8][31][3]
TST_RSV bit 24	MAIN[8][30][4]
TST_RSV bit 25	MAIN[8][31][4]
TST_RSV bit 26	MAIN[8][30][5]
TST_RSV bit 27	MAIN[8][31][5]
TST_RSV bit 28	MAIN[8][30][6]
TST_RSV bit 29	MAIN[8][31][6]
TST_RSV bit 30	MAIN[8][30][7]
TST_RSV bit 31	MAIN[8][31][7]
TXDLY_CFG bit 0	MAIN[1][30][16]
TXDLY_CFG bit 1	MAIN[1][31][16]
TXDLY_CFG bit 2	MAIN[1][30][17]
TXDLY_CFG bit 3	MAIN[1][31][17]
TXDLY_CFG bit 4	MAIN[1][30][18]
TXDLY_CFG bit 5	MAIN[1][31][18]
TXDLY_CFG bit 6	MAIN[1][30][19]
TXDLY_CFG bit 7	MAIN[1][31][19]
TXDLY_CFG bit 8	MAIN[1][30][20]
TXDLY_CFG bit 9	MAIN[1][31][20]
TXDLY_CFG bit 10	MAIN[1][30][21]
TXDLY_CFG bit 11	MAIN[1][31][21]
TXDLY_CFG bit 12	MAIN[1][30][22]
TXDLY_CFG bit 13	MAIN[1][31][22]
TXDLY_CFG bit 14	MAIN[1][30][23]
TXDLY_CFG bit 15	MAIN[1][31][23]
TXDLY_LCFG bit 0	MAIN[8][30][56]
TXDLY_LCFG bit 1	MAIN[8][31][56]
TXDLY_LCFG bit 2	MAIN[8][30][57]
TXDLY_LCFG bit 3	MAIN[8][31][57]
TXDLY_LCFG bit 4	MAIN[8][30][58]
TXDLY_LCFG bit 5	MAIN[8][31][58]
TXDLY_LCFG bit 6	MAIN[8][30][59]
TXDLY_LCFG bit 7	MAIN[8][31][59]
TXDLY_LCFG bit 8	MAIN[8][30][60]
TXDLY_TAP_CFG bit 0	MAIN[1][30][24]
TXDLY_TAP_CFG bit 1	MAIN[1][31][24]
TXDLY_TAP_CFG bit 2	MAIN[1][30][25]
TXDLY_TAP_CFG bit 3	MAIN[1][31][25]
TXDLY_TAP_CFG bit 4	MAIN[1][30][26]
TXDLY_TAP_CFG bit 5	MAIN[1][31][26]
TXDLY_TAP_CFG bit 6	MAIN[1][30][27]
TXDLY_TAP_CFG bit 7	MAIN[1][31][27]
TXDLY_TAP_CFG bit 8	MAIN[1][30][28]
TXDLY_TAP_CFG bit 9	MAIN[1][31][28]
TXDLY_TAP_CFG bit 10	MAIN[1][30][29]
TXDLY_TAP_CFG bit 11	MAIN[1][31][29]
TXDLY_TAP_CFG bit 12	MAIN[1][30][30]
TXDLY_TAP_CFG bit 13	MAIN[1][31][30]
TXDLY_TAP_CFG bit 14	MAIN[1][30][31]
TXDLY_TAP_CFG bit 15	MAIN[1][31][31]
TXPHDLY_CFG bit 0	MAIN[1][30][0]
TXPHDLY_CFG bit 1	MAIN[1][31][0]
TXPHDLY_CFG bit 2	MAIN[1][30][1]
TXPHDLY_CFG bit 3	MAIN[1][31][1]
TXPHDLY_CFG bit 4	MAIN[1][30][2]
TXPHDLY_CFG bit 5	MAIN[1][31][2]
TXPHDLY_CFG bit 6	MAIN[1][30][3]
TXPHDLY_CFG bit 7	MAIN[1][31][3]
TXPHDLY_CFG bit 8	MAIN[1][30][4]
TXPHDLY_CFG bit 9	MAIN[1][31][4]
TXPHDLY_CFG bit 10	MAIN[1][30][5]
TXPHDLY_CFG bit 11	MAIN[1][31][5]
TXPHDLY_CFG bit 12	MAIN[1][30][6]
TXPHDLY_CFG bit 13	MAIN[1][31][6]
TXPHDLY_CFG bit 14	MAIN[1][30][7]
TXPHDLY_CFG bit 15	MAIN[1][31][7]
TXPHDLY_CFG bit 16	MAIN[1][30][8]
TXPHDLY_CFG bit 17	MAIN[1][31][8]
TXPHDLY_CFG bit 18	MAIN[1][30][9]
TXPHDLY_CFG bit 19	MAIN[1][31][9]
TXPHDLY_CFG bit 20	MAIN[1][30][10]
TXPHDLY_CFG bit 21	MAIN[1][31][10]
TXPHDLY_CFG bit 22	MAIN[1][30][11]
TXPHDLY_CFG bit 23	MAIN[1][31][11]
TXPH_CFG bit 0	MAIN[1][30][32]
TXPH_CFG bit 1	MAIN[1][31][32]
TXPH_CFG bit 2	MAIN[1][30][33]
TXPH_CFG bit 3	MAIN[1][31][33]
TXPH_CFG bit 4	MAIN[1][30][34]
TXPH_CFG bit 5	MAIN[1][31][34]
TXPH_CFG bit 6	MAIN[1][30][35]
TXPH_CFG bit 7	MAIN[1][31][35]
TXPH_CFG bit 8	MAIN[1][30][36]
TXPH_CFG bit 9	MAIN[1][31][36]
TXPH_CFG bit 10	MAIN[1][30][37]
TXPH_CFG bit 11	MAIN[1][31][37]
TXPH_CFG bit 12	MAIN[1][30][38]
TXPH_CFG bit 13	MAIN[1][31][38]
TXPH_CFG bit 14	MAIN[1][30][39]
TXPH_CFG bit 15	MAIN[1][31][39]
TX_RXDETECT_CFG bit 0	MAIN[4][30][40]
TX_RXDETECT_CFG bit 1	MAIN[4][31][40]
TX_RXDETECT_CFG bit 2	MAIN[4][30][41]
TX_RXDETECT_CFG bit 3	MAIN[4][31][41]
TX_RXDETECT_CFG bit 4	MAIN[4][30][42]
TX_RXDETECT_CFG bit 5	MAIN[4][31][42]
TX_RXDETECT_CFG bit 6	MAIN[4][30][43]
TX_RXDETECT_CFG bit 7	MAIN[4][31][43]
TX_RXDETECT_CFG bit 8	MAIN[4][30][44]
TX_RXDETECT_CFG bit 9	MAIN[4][31][44]
TX_RXDETECT_CFG bit 10	MAIN[4][30][45]
TX_RXDETECT_CFG bit 11	MAIN[4][31][45]
TX_RXDETECT_CFG bit 12	MAIN[4][30][46]
TX_RXDETECT_CFG bit 13	MAIN[4][31][46]
PMA_RSV bit 0	MAIN[8][30][8]
PMA_RSV bit 1	MAIN[8][31][8]
PMA_RSV bit 2	MAIN[8][30][9]
PMA_RSV bit 3	MAIN[8][31][9]
PMA_RSV bit 4	MAIN[8][30][10]
PMA_RSV bit 5	MAIN[8][31][10]
PMA_RSV bit 6	MAIN[8][30][11]
PMA_RSV bit 7	MAIN[8][31][11]
PMA_RSV bit 8	MAIN[8][30][12]
PMA_RSV bit 9	MAIN[8][31][12]
PMA_RSV bit 10	MAIN[8][30][13]
PMA_RSV bit 11	MAIN[8][31][13]
PMA_RSV bit 12	MAIN[8][30][14]
PMA_RSV bit 13	MAIN[8][31][14]
PMA_RSV bit 14	MAIN[8][30][15]
PMA_RSV bit 15	MAIN[8][31][15]
PMA_RSV bit 16	MAIN[8][30][16]
PMA_RSV bit 17	MAIN[8][31][16]
PMA_RSV bit 18	MAIN[8][30][17]
PMA_RSV bit 19	MAIN[8][31][17]
PMA_RSV bit 20	MAIN[8][30][18]
PMA_RSV bit 21	MAIN[8][31][18]
PMA_RSV bit 22	MAIN[8][30][19]
PMA_RSV bit 23	MAIN[8][31][19]
PMA_RSV bit 24	MAIN[8][30][20]
PMA_RSV bit 25	MAIN[8][31][20]
PMA_RSV bit 26	MAIN[8][30][21]
PMA_RSV bit 27	MAIN[8][31][21]
PMA_RSV bit 28	MAIN[8][30][22]
PMA_RSV bit 29	MAIN[8][31][22]
PMA_RSV bit 30	MAIN[8][30][23]
PMA_RSV bit 31	MAIN[8][31][23]
CPLL_CFG_GTH bit 0	MAIN[4][30][56]
CPLL_CFG_GTH bit 1	MAIN[4][31][56]
CPLL_CFG_GTH bit 2	MAIN[4][30][57]
CPLL_CFG_GTH bit 3	MAIN[4][31][57]
CPLL_CFG_GTH bit 4	MAIN[4][30][58]
CPLL_CFG_GTH bit 5	MAIN[4][31][58]
CPLL_CFG_GTH bit 6	MAIN[4][30][59]
CPLL_CFG_GTH bit 7	MAIN[4][31][59]
CPLL_CFG_GTH bit 8	MAIN[4][30][60]
CPLL_CFG_GTH bit 9	MAIN[4][31][60]
CPLL_CFG_GTH bit 10	MAIN[4][30][61]
CPLL_CFG_GTH bit 11	MAIN[4][31][61]
CPLL_CFG_GTH bit 12	MAIN[4][30][62]
CPLL_CFG_GTH bit 13	MAIN[4][31][62]
CPLL_CFG_GTH bit 14	MAIN[4][30][63]
CPLL_CFG_GTH bit 15	MAIN[4][31][63]
CPLL_CFG_GTH bit 16	MAIN[5][30][0]
CPLL_CFG_GTH bit 17	MAIN[5][31][0]
CPLL_CFG_GTH bit 18	MAIN[5][30][1]
CPLL_CFG_GTH bit 19	MAIN[5][31][1]
CPLL_CFG_GTH bit 20	MAIN[5][30][2]
CPLL_CFG_GTH bit 21	MAIN[5][31][2]
CPLL_CFG_GTH bit 22	MAIN[5][30][3]
CPLL_CFG_GTH bit 23	MAIN[5][31][3]
CPLL_CFG_GTH bit 24	MAIN[5][30][4]
CPLL_CFG_GTH bit 25	MAIN[5][31][4]
CPLL_CFG_GTH bit 26	MAIN[5][30][5]
CPLL_CFG_GTH bit 27	MAIN[5][31][5]
CPLL_CFG_GTH bit 28	MAIN[5][30][6]
RXCDR_CFG_GTH bit 0	MAIN[10][30][0]
RXCDR_CFG_GTH bit 1	MAIN[10][31][0]
RXCDR_CFG_GTH bit 2	MAIN[10][30][1]
RXCDR_CFG_GTH bit 3	MAIN[10][31][1]
RXCDR_CFG_GTH bit 4	MAIN[10][30][2]
RXCDR_CFG_GTH bit 5	MAIN[10][31][2]
RXCDR_CFG_GTH bit 6	MAIN[10][30][3]
RXCDR_CFG_GTH bit 7	MAIN[10][31][3]
RXCDR_CFG_GTH bit 8	MAIN[10][30][4]
RXCDR_CFG_GTH bit 9	MAIN[10][31][4]
RXCDR_CFG_GTH bit 10	MAIN[10][30][5]
RXCDR_CFG_GTH bit 11	MAIN[10][31][5]
RXCDR_CFG_GTH bit 12	MAIN[10][30][6]
RXCDR_CFG_GTH bit 13	MAIN[10][31][6]
RXCDR_CFG_GTH bit 14	MAIN[10][30][7]
RXCDR_CFG_GTH bit 15	MAIN[10][31][7]
RXCDR_CFG_GTH bit 16	MAIN[10][30][8]
RXCDR_CFG_GTH bit 17	MAIN[10][31][8]
RXCDR_CFG_GTH bit 18	MAIN[10][30][9]
RXCDR_CFG_GTH bit 19	MAIN[10][31][9]
RXCDR_CFG_GTH bit 20	MAIN[10][30][10]
RXCDR_CFG_GTH bit 21	MAIN[10][31][10]
RXCDR_CFG_GTH bit 22	MAIN[10][30][11]
RXCDR_CFG_GTH bit 23	MAIN[10][31][11]
RXCDR_CFG_GTH bit 24	MAIN[10][30][12]
RXCDR_CFG_GTH bit 25	MAIN[10][31][12]
RXCDR_CFG_GTH bit 26	MAIN[10][30][13]
RXCDR_CFG_GTH bit 27	MAIN[10][31][13]
RXCDR_CFG_GTH bit 28	MAIN[10][30][14]
RXCDR_CFG_GTH bit 29	MAIN[10][31][14]
RXCDR_CFG_GTH bit 30	MAIN[10][30][15]
RXCDR_CFG_GTH bit 31	MAIN[10][31][15]
RXCDR_CFG_GTH bit 32	MAIN[10][30][16]
RXCDR_CFG_GTH bit 33	MAIN[10][31][16]
RXCDR_CFG_GTH bit 34	MAIN[10][30][17]
RXCDR_CFG_GTH bit 35	MAIN[10][31][17]
RXCDR_CFG_GTH bit 36	MAIN[10][30][18]
RXCDR_CFG_GTH bit 37	MAIN[10][31][18]
RXCDR_CFG_GTH bit 38	MAIN[10][30][19]
RXCDR_CFG_GTH bit 39	MAIN[10][31][19]
RXCDR_CFG_GTH bit 40	MAIN[10][30][20]
RXCDR_CFG_GTH bit 41	MAIN[10][31][20]
RXCDR_CFG_GTH bit 42	MAIN[10][30][21]
RXCDR_CFG_GTH bit 43	MAIN[10][31][21]
RXCDR_CFG_GTH bit 44	MAIN[10][30][22]
RXCDR_CFG_GTH bit 45	MAIN[10][31][22]
RXCDR_CFG_GTH bit 46	MAIN[10][30][23]
RXCDR_CFG_GTH bit 47	MAIN[10][31][23]
RXCDR_CFG_GTH bit 48	MAIN[10][30][24]
RXCDR_CFG_GTH bit 49	MAIN[10][31][24]
RXCDR_CFG_GTH bit 50	MAIN[10][30][25]
RXCDR_CFG_GTH bit 51	MAIN[10][31][25]
RXCDR_CFG_GTH bit 52	MAIN[10][30][26]
RXCDR_CFG_GTH bit 53	MAIN[10][31][26]
RXCDR_CFG_GTH bit 54	MAIN[10][30][27]
RXCDR_CFG_GTH bit 55	MAIN[10][31][27]
RXCDR_CFG_GTH bit 56	MAIN[10][30][28]
RXCDR_CFG_GTH bit 57	MAIN[10][31][28]
RXCDR_CFG_GTH bit 58	MAIN[10][30][29]
RXCDR_CFG_GTH bit 59	MAIN[10][31][29]
RXCDR_CFG_GTH bit 60	MAIN[10][30][30]
RXCDR_CFG_GTH bit 61	MAIN[10][31][30]
RXCDR_CFG_GTH bit 62	MAIN[10][30][31]
RXCDR_CFG_GTH bit 63	MAIN[10][31][31]
RXCDR_CFG_GTH bit 64	MAIN[10][30][32]
RXCDR_CFG_GTH bit 65	MAIN[10][31][32]
RXCDR_CFG_GTH bit 66	MAIN[10][30][33]
RXCDR_CFG_GTH bit 67	MAIN[10][31][33]
RXCDR_CFG_GTH bit 68	MAIN[10][30][34]
RXCDR_CFG_GTH bit 69	MAIN[10][31][34]
RXCDR_CFG_GTH bit 70	MAIN[10][30][35]
RXCDR_CFG_GTH bit 71	MAIN[10][31][35]
RXCDR_CFG_GTH bit 72	MAIN[10][30][36]
RXCDR_CFG_GTH bit 73	MAIN[10][31][36]
RXCDR_CFG_GTH bit 74	MAIN[10][30][37]
RXCDR_CFG_GTH bit 75	MAIN[10][31][37]
RXCDR_CFG_GTH bit 76	MAIN[10][30][38]
RXCDR_CFG_GTH bit 77	MAIN[10][31][38]
RXCDR_CFG_GTH bit 78	MAIN[10][30][39]
RXCDR_CFG_GTH bit 79	MAIN[10][31][39]
RXCDR_CFG_GTH bit 80	MAIN[10][30][40]
RXCDR_CFG_GTH bit 81	MAIN[10][31][40]
RXCDR_CFG_GTH bit 82	MAIN[10][30][41]
PMA_RSV2_GTH bit 0	MAIN[5][30][16]
PMA_RSV2_GTH bit 1	MAIN[5][31][16]
PMA_RSV2_GTH bit 2	MAIN[5][30][17]
PMA_RSV2_GTH bit 3	MAIN[5][31][17]
PMA_RSV2_GTH bit 4	MAIN[5][30][18]
PMA_RSV2_GTH bit 5	MAIN[5][31][18]
PMA_RSV2_GTH bit 6	MAIN[5][30][19]
PMA_RSV2_GTH bit 7	MAIN[5][31][19]
PMA_RSV2_GTH bit 8	MAIN[5][30][20]
PMA_RSV2_GTH bit 9	MAIN[5][31][20]
PMA_RSV2_GTH bit 10	MAIN[5][30][21]
PMA_RSV2_GTH bit 11	MAIN[5][31][21]
PMA_RSV2_GTH bit 12	MAIN[5][30][22]
PMA_RSV2_GTH bit 13	MAIN[5][31][22]
PMA_RSV2_GTH bit 14	MAIN[5][30][23]
PMA_RSV2_GTH bit 15	MAIN[5][31][23]
PMA_RSV2_GTH bit 16	MAIN[5][30][24]
PMA_RSV2_GTH bit 17	MAIN[5][31][24]
PMA_RSV2_GTH bit 18	MAIN[5][30][25]
PMA_RSV2_GTH bit 19	MAIN[5][31][25]
PMA_RSV2_GTH bit 20	MAIN[5][30][26]
PMA_RSV2_GTH bit 21	MAIN[5][31][26]
PMA_RSV2_GTH bit 22	MAIN[5][30][27]
PMA_RSV2_GTH bit 23	MAIN[5][31][27]
PMA_RSV2_GTH bit 24	MAIN[5][30][28]
PMA_RSV2_GTH bit 25	MAIN[5][31][28]
PMA_RSV2_GTH bit 26	MAIN[5][30][29]
PMA_RSV2_GTH bit 27	MAIN[5][31][29]
PMA_RSV2_GTH bit 28	MAIN[5][30][30]
PMA_RSV2_GTH bit 29	MAIN[5][31][30]
PMA_RSV2_GTH bit 30	MAIN[5][30][31]
PMA_RSV2_GTH bit 31	MAIN[5][31][31]
PMA_RSV4_GTH bit 0	MAIN[7][30][32]
PMA_RSV4_GTH bit 1	MAIN[7][31][32]
PMA_RSV4_GTH bit 2	MAIN[7][30][33]
PMA_RSV4_GTH bit 3	MAIN[7][31][33]
PMA_RSV4_GTH bit 4	MAIN[7][30][34]
PMA_RSV4_GTH bit 5	MAIN[7][31][34]
PMA_RSV4_GTH bit 6	MAIN[7][30][35]
PMA_RSV4_GTH bit 7	MAIN[7][31][35]
PMA_RSV4_GTH bit 8	MAIN[7][30][36]
PMA_RSV4_GTH bit 9	MAIN[7][31][36]
PMA_RSV4_GTH bit 10	MAIN[7][30][37]
PMA_RSV4_GTH bit 11	MAIN[7][31][37]
PMA_RSV4_GTH bit 12	MAIN[7][30][38]
PMA_RSV4_GTH bit 13	MAIN[7][31][38]
PMA_RSV4_GTH bit 14	MAIN[7][30][39]
PMA_RSV5 bit 0	MAIN[2][30][28]
PMA_RSV5 bit 1	MAIN[2][31][28]
PMA_RSV5 bit 2	MAIN[2][30][29]
PMA_RSV5 bit 3	MAIN[2][31][29]
ADAPT_CFG0 bit 0	MAIN[7][30][16]
ADAPT_CFG0 bit 1	MAIN[7][31][16]
ADAPT_CFG0 bit 2	MAIN[7][30][17]
ADAPT_CFG0 bit 3	MAIN[7][31][17]
ADAPT_CFG0 bit 4	MAIN[7][30][18]
ADAPT_CFG0 bit 5	MAIN[7][31][18]
ADAPT_CFG0 bit 6	MAIN[7][30][19]
ADAPT_CFG0 bit 7	MAIN[7][31][19]
ADAPT_CFG0 bit 8	MAIN[7][30][20]
ADAPT_CFG0 bit 9	MAIN[7][31][20]
ADAPT_CFG0 bit 10	MAIN[7][30][21]
ADAPT_CFG0 bit 11	MAIN[7][31][21]
ADAPT_CFG0 bit 12	MAIN[7][30][22]
ADAPT_CFG0 bit 13	MAIN[7][31][22]
ADAPT_CFG0 bit 14	MAIN[7][30][23]
ADAPT_CFG0 bit 15	MAIN[7][31][23]
ADAPT_CFG0 bit 16	MAIN[7][30][24]
ADAPT_CFG0 bit 17	MAIN[7][31][24]
ADAPT_CFG0 bit 18	MAIN[7][30][25]
ADAPT_CFG0 bit 19	MAIN[7][31][25]
CFOK_CFG bit 0	MAIN[6][30][8]
CFOK_CFG bit 1	MAIN[6][31][8]
CFOK_CFG bit 2	MAIN[6][30][9]
CFOK_CFG bit 3	MAIN[6][31][9]
CFOK_CFG bit 4	MAIN[6][30][10]
CFOK_CFG bit 5	MAIN[6][31][10]
CFOK_CFG bit 6	MAIN[6][30][11]
CFOK_CFG bit 7	MAIN[6][31][11]
CFOK_CFG bit 8	MAIN[6][30][12]
CFOK_CFG bit 9	MAIN[6][31][12]
CFOK_CFG bit 10	MAIN[6][30][13]
CFOK_CFG bit 11	MAIN[6][31][13]
CFOK_CFG bit 12	MAIN[6][30][14]
CFOK_CFG bit 13	MAIN[6][31][14]
CFOK_CFG bit 14	MAIN[6][30][15]
CFOK_CFG bit 15	MAIN[6][31][15]
CFOK_CFG bit 16	MAIN[6][30][16]
CFOK_CFG bit 17	MAIN[6][31][16]
CFOK_CFG bit 18	MAIN[6][30][17]
CFOK_CFG bit 19	MAIN[6][31][17]
CFOK_CFG bit 20	MAIN[6][30][18]
CFOK_CFG bit 21	MAIN[6][31][18]
CFOK_CFG bit 22	MAIN[6][30][19]
CFOK_CFG bit 23	MAIN[6][31][19]
CFOK_CFG bit 24	MAIN[6][30][20]
CFOK_CFG bit 25	MAIN[6][31][20]
CFOK_CFG bit 26	MAIN[6][30][21]
CFOK_CFG bit 27	MAIN[6][31][21]
CFOK_CFG bit 28	MAIN[6][30][22]
CFOK_CFG bit 29	MAIN[6][31][22]
CFOK_CFG bit 30	MAIN[6][30][23]
CFOK_CFG bit 31	MAIN[6][31][23]
CFOK_CFG bit 32	MAIN[6][30][24]
CFOK_CFG bit 33	MAIN[6][31][24]
CFOK_CFG bit 34	MAIN[6][30][25]
CFOK_CFG bit 35	MAIN[6][31][25]
CFOK_CFG bit 36	MAIN[6][30][26]
CFOK_CFG bit 37	MAIN[6][31][26]
CFOK_CFG bit 38	MAIN[6][30][27]
CFOK_CFG bit 39	MAIN[6][31][27]
CFOK_CFG bit 40	MAIN[6][30][28]
CFOK_CFG bit 41	MAIN[6][31][28]
RX_DFE_ST_CFG bit 0	MAIN[6][30][48]
RX_DFE_ST_CFG bit 1	MAIN[6][31][48]
RX_DFE_ST_CFG bit 2	MAIN[6][30][49]
RX_DFE_ST_CFG bit 3	MAIN[6][31][49]
RX_DFE_ST_CFG bit 4	MAIN[6][30][50]
RX_DFE_ST_CFG bit 5	MAIN[6][31][50]
RX_DFE_ST_CFG bit 6	MAIN[6][30][51]
RX_DFE_ST_CFG bit 7	MAIN[6][31][51]
RX_DFE_ST_CFG bit 8	MAIN[6][30][52]
RX_DFE_ST_CFG bit 9	MAIN[6][31][52]
RX_DFE_ST_CFG bit 10	MAIN[6][30][53]
RX_DFE_ST_CFG bit 11	MAIN[6][31][53]
RX_DFE_ST_CFG bit 12	MAIN[6][30][54]
RX_DFE_ST_CFG bit 13	MAIN[6][31][54]
RX_DFE_ST_CFG bit 14	MAIN[6][30][55]
RX_DFE_ST_CFG bit 15	MAIN[6][31][55]
RX_DFE_ST_CFG bit 16	MAIN[6][30][56]
RX_DFE_ST_CFG bit 17	MAIN[6][31][56]
RX_DFE_ST_CFG bit 18	MAIN[6][30][57]
RX_DFE_ST_CFG bit 19	MAIN[6][31][57]
RX_DFE_ST_CFG bit 20	MAIN[6][30][58]
RX_DFE_ST_CFG bit 21	MAIN[6][31][58]
RX_DFE_ST_CFG bit 22	MAIN[6][30][59]
RX_DFE_ST_CFG bit 23	MAIN[6][31][59]
RX_DFE_ST_CFG bit 24	MAIN[6][30][60]
RX_DFE_ST_CFG bit 25	MAIN[6][31][60]
RX_DFE_ST_CFG bit 26	MAIN[6][30][61]
RX_DFE_ST_CFG bit 27	MAIN[6][31][61]
RX_DFE_ST_CFG bit 28	MAIN[6][30][62]
RX_DFE_ST_CFG bit 29	MAIN[6][31][62]
RX_DFE_ST_CFG bit 30	MAIN[6][30][63]
RX_DFE_ST_CFG bit 31	MAIN[6][31][63]
RX_DFE_ST_CFG bit 32	MAIN[7][30][0]
RX_DFE_ST_CFG bit 33	MAIN[7][31][0]
RX_DFE_ST_CFG bit 34	MAIN[7][30][1]
RX_DFE_ST_CFG bit 35	MAIN[7][31][1]
RX_DFE_ST_CFG bit 36	MAIN[7][30][2]
RX_DFE_ST_CFG bit 37	MAIN[7][31][2]
RX_DFE_ST_CFG bit 38	MAIN[7][30][3]
RX_DFE_ST_CFG bit 39	MAIN[7][31][3]
RX_DFE_ST_CFG bit 40	MAIN[7][30][4]
RX_DFE_ST_CFG bit 41	MAIN[7][31][4]
RX_DFE_ST_CFG bit 42	MAIN[7][30][5]
RX_DFE_ST_CFG bit 43	MAIN[7][31][5]
RX_DFE_ST_CFG bit 44	MAIN[7][30][6]
RX_DFE_ST_CFG bit 45	MAIN[7][31][6]
RX_DFE_ST_CFG bit 46	MAIN[7][30][7]
RX_DFE_ST_CFG bit 47	MAIN[7][31][7]
RX_DFE_ST_CFG bit 48	MAIN[7][30][8]
RX_DFE_ST_CFG bit 49	MAIN[7][31][8]
RX_DFE_ST_CFG bit 50	MAIN[7][30][9]
RX_DFE_ST_CFG bit 51	MAIN[7][31][9]
RX_DFE_ST_CFG bit 52	MAIN[7][30][10]
RX_DFE_ST_CFG bit 53	MAIN[7][31][10]
TX_RXDETECT_PRECHARGE_TIME bit 0	MAIN[4][30][24]
TX_RXDETECT_PRECHARGE_TIME bit 1	MAIN[4][31][24]
TX_RXDETECT_PRECHARGE_TIME bit 2	MAIN[4][30][25]
TX_RXDETECT_PRECHARGE_TIME bit 3	MAIN[4][31][25]
TX_RXDETECT_PRECHARGE_TIME bit 4	MAIN[4][30][26]
TX_RXDETECT_PRECHARGE_TIME bit 5	MAIN[4][31][26]
TX_RXDETECT_PRECHARGE_TIME bit 6	MAIN[4][30][27]
TX_RXDETECT_PRECHARGE_TIME bit 7	MAIN[4][31][27]
TX_RXDETECT_PRECHARGE_TIME bit 8	MAIN[4][30][28]
TX_RXDETECT_PRECHARGE_TIME bit 9	MAIN[4][31][28]
TX_RXDETECT_PRECHARGE_TIME bit 10	MAIN[4][30][29]
TX_RXDETECT_PRECHARGE_TIME bit 11	MAIN[4][31][29]
TX_RXDETECT_PRECHARGE_TIME bit 12	MAIN[4][30][30]
TX_RXDETECT_PRECHARGE_TIME bit 13	MAIN[4][31][30]
TX_RXDETECT_PRECHARGE_TIME bit 14	MAIN[4][30][31]
TX_RXDETECT_PRECHARGE_TIME bit 15	MAIN[4][31][31]
TX_RXDETECT_PRECHARGE_TIME bit 16	MAIN[4][31][39]

virtex7 GTH_CHANNEL enum GTX_COMMON_PLLREFCLKSEL
GTX_CHANNEL.CPLLREFCLKSEL_STATIC_VAL	MAIN[0][31][10]	MAIN[0][30][10]	MAIN[0][31][9]
NONE	0	0	0
GTREFCLK0	0	0	1
GTREFCLK1	0	1	0
GTNORTHREFCLK0	0	1	1
GTNORTHREFCLK1	1	0	0
GTSOUTHREFCLK0	1	0	1
GTSOUTHREFCLK1	1	1	0
GTGREFCLK	1	1	1

virtex7 GTH_CHANNEL enum GT11_ALIGN_COMMA_WORD
GTX_CHANNEL.ALIGN_COMMA_WORD	MAIN[8][29][15]	MAIN[8][28][15]	MAIN[8][29][14]
_1	0	0	1
_2	0	1	0
_4	1	0	0

virtex7 GTH_CHANNEL enum GTP_CHANNEL_CBCC_DATA_SOURCE_SEL
GTX_CHANNEL.CBCC_DATA_SOURCE_SEL	MAIN[10][29][21]
DECODED	1
ENCODED	0

virtex7 GTH_CHANNEL enum GTP_SEQ_LEN
GTX_CHANNEL.CHAN_BOND_SEQ_LEN	MAIN[9][29][47]	MAIN[9][28][47]
GTX_CHANNEL.CLK_COR_SEQ_LEN	MAIN[9][29][13]	MAIN[9][28][13]
_1	0	0
_2	0	1
_3	1	0
_4	1	1

virtex7 GTH_CHANNEL enum GTP_PLL_DIVSEL_REF
GTX_CHANNEL.CPLL_FBDIV	MAIN[0][30][50]	MAIN[0][31][49]	MAIN[0][30][49]	MAIN[0][31][48]	MAIN[0][30][48]
GTX_CHANNEL.CPLL_REFCLK_DIV	MAIN[0][30][54]	MAIN[0][31][53]	MAIN[0][30][53]	MAIN[0][31][52]	MAIN[0][30][52]
_1	1	0	0	0	0
_2	0	0	0	0	0
_3	0	0	0	0	1
_4	0	0	0	1	0
_5	0	0	0	1	1
_6	0	0	1	0	1
_8	0	0	1	1	0
_10	0	0	1	1	1
_12	0	1	1	0	1
_16	0	1	1	1	0
_20	0	1	1	1	1

virtex7 GTH_CHANNEL enum GTX_PLL_DIVSEL45_FB
GTX_CHANNEL.CPLL_FBDIV_45	MAIN[0][31][51]
GTX_CHANNEL.RXSIPO_DIV_45	MAIN[6][31][1]
GTX_CHANNEL.TXPISO_DIV_45	MAIN[2][30][1]
_4	0
_5	1

virtex7 GTH_CHANNEL enum GTX_RX_FIFO_ADDR_MODE
GTX_CHANNEL.RXBUF_ADDR_MODE	MAIN[8][31][43]
FULL	0
FAST	1

virtex7 GTH_CHANNEL enum GTP_CHANNEL_CLKOUT_DIV
GTX_CHANNEL.RXOUT_DIV	MAIN[6][30][1]	MAIN[6][31][0]	MAIN[6][30][0]
GTX_CHANNEL.TXOUT_DIV	MAIN[6][30][3]	MAIN[6][31][2]	MAIN[6][30][2]
_1	0	0	0
_2	0	0	1
_4	0	1	0
_8	0	1	1
_16	1	0	0

virtex7 GTH_CHANNEL enum GTX_CHANNEL_DATA_WIDTH
GTX_CHANNEL.RX_DATA_WIDTH	MAIN[2][29][14]	MAIN[2][28][14]	MAIN[2][29][13]
GTX_CHANNEL.TX_DATA_WIDTH	MAIN[2][30][25]	MAIN[2][31][24]	MAIN[2][30][24]
_16	0	1	0
_20	0	1	1
_32	1	0	0
_40	1	0	1
_64	1	1	0
_80	1	1	1

virtex7 GTH_CHANNEL enum GTP_RX_XCLK_SEL
GTX_CHANNEL.RX_XCLK_SEL	MAIN[0][30][11]
RXUSR	1
RXREC	0

virtex7 GTH_CHANNEL enum GTX_CHANNEL_PLL_SEL
GTX_CHANNEL.RXPLL_SEL	MAIN[3][29][55]
GTX_CHANNEL.TXPLL_SEL	MAIN[0][31][12]
CPLL	0
QPLL	1

virtex7 GTH_CHANNEL enum GTX_RX_SLIDE_MODE
GTX_CHANNEL.RXSLIDE_MODE	MAIN[8][29][7]	MAIN[8][28][7]
NONE	0	0
AUTO	0	1
PCS	1	0
PMA	1	1

virtex7 GTH_CHANNEL enum GTP_CHANNEL_SATA_PLL_CFG
GTX_CHANNEL.SATA_CPLL_CFG	MAIN[0][31][55]	MAIN[0][30][55]
VCO_750MHZ	1	0
VCO_1500MHZ	0	1
VCO_3000MHZ	0	0

virtex7 GTH_CHANNEL enum GTP_CHANNEL_TX_DRIVE_MODE
GTX_CHANNEL.TX_DRIVE_MODE	MAIN[3][29][8]	MAIN[3][28][8]
DIRECT	0	0
PIPE	0	1
PIPEGEN3	1	0

virtex7 GTH_CHANNEL enum GTP_TX_XCLK_SEL
GTX_CHANNEL.TX_XCLK_SEL	MAIN[0][31][11]
TXUSR	1
TXOUT	0

virtex7 GTH_CHANNEL enum GTP_CHANNEL_TXPI_PPMCLK_SEL
GTX_CHANNEL.TXPI_PPMCLK_SEL	MAIN[7][31][49]
TXUSRCLK	0
TXUSRCLK2	1

virtex7 GTH_CHANNEL enum GTP_CHANNEL_RXOOB_CLK_CFG
GTX_CHANNEL.RXOOB_CLK_CFG	MAIN[2][31][1]
PMA	0
FABRIC	1

Bel wires

virtex7 GTH_CHANNEL bel wires
Wire	Pins
CELL[0].IMUX_CLK[0]	GTX_CHANNEL.PMASCANCLK[0]
CELL[0].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.RXOSINTCFG[2]
CELL[0].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.RXOSINTCFG[3]
CELL[0].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.RXOSINTCFG[0]
CELL[0].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.RXOSINTCFG[1]
CELL[0].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.SCANENB
CELL[0].IMUX_IMUX_DELAY[7]	GTX_CHANNEL.TXPISOPD
CELL[0].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.TXCHARDISPVAL[3]
CELL[0].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PMASCANIN[6]
CELL[0].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.TXCHARDISPVAL[7]
CELL[0].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.TXSYNCIN
CELL[0].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.PMASCANMODEB
CELL[0].IMUX_IMUX_DELAY[13]	GTX_CHANNEL.RXSYNCALLIN
CELL[0].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.PMASCANIN[0]
CELL[0].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.TXPIPPMEN
CELL[0].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.TXDATA[28]
CELL[0].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.TXDATA[29]
CELL[0].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXDATA[60]
CELL[0].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.TXDATA[61]
CELL[0].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.TXDATA[30]
CELL[0].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.TXDATA[31]
CELL[0].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.TXDATA[62]
CELL[0].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.TXDATA[63]
CELL[0].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.PMASCANIN[5]
CELL[0].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.TSTPDOVRDB
CELL[0].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.PMASCANRSTEN
CELL[0].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.TXCHARDISPMODE[3]
CELL[0].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.SCANIN[0]
CELL[0].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.TXCHARDISPMODE[7]
CELL[0].IMUX_IMUX_DELAY[32]	GTX_CHANNEL.DRPDI[11]
CELL[0].IMUX_IMUX_DELAY[33]	GTX_CHANNEL.DRPDI[10]
CELL[0].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.DRPDI[3]
CELL[0].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.DRPDI[2]
CELL[0].IMUX_IMUX_DELAY[36]	GTX_CHANNEL.DRPDI[9]
CELL[0].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.DRPDI[8]
CELL[0].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.DRPDI[1]
CELL[0].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.DRPDI[0]
CELL[0].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.EYESCANMODE
CELL[0].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.RXSYNCIN
CELL[0].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.TSTPD[0]
CELL[0].IMUX_IMUX_DELAY[45]	GTX_CHANNEL.TXSYNCALLIN
CELL[0].IMUX_IMUX_DELAY[46]	GTX_CHANNEL.SCANMODEB
CELL[0].OUT_BEL[0]	GTX_CHANNEL.DRPDO[0]
CELL[0].OUT_BEL[1]	GTX_CHANNEL.DRPDO[5]
CELL[0].OUT_BEL[2]	GTX_CHANNEL.DRPDO[2]
CELL[0].OUT_BEL[3]	GTX_CHANNEL.DRPDO[7]
CELL[0].OUT_BEL[4]	GTX_CHANNEL.DRPDO[1]
CELL[0].OUT_BEL[5]	GTX_CHANNEL.DRPDO[4]
CELL[0].OUT_BEL[6]	GTX_CHANNEL.DRPDO[3]
CELL[0].OUT_BEL[7]	GTX_CHANNEL.DRPDO[6]
CELL[0].OUT_BEL[8]	GTX_CHANNEL.RXSYNCOUT
CELL[0].OUT_BEL[9]	GTX_CHANNEL.PCSRSVDOUT[11]
CELL[0].OUT_BEL[10]	GTX_CHANNEL.TXRUNDISP[0]
CELL[0].OUT_BEL[11]	GTX_CHANNEL.RXDFESLIDETAPSTARTED
CELL[0].OUT_BEL[12]	GTX_CHANNEL.RSOSINTDONE
CELL[0].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[0]
CELL[0].OUT_BEL[14]	GTX_CHANNEL.RXSYNCDONE
CELL[0].OUT_BEL[15]	GTX_CHANNEL.RXHEADER[5]
CELL[0].OUT_BEL[16]	GTX_CHANNEL.PCSRSVDOUT[14]
CELL[0].OUT_BEL[17]	GTX_CHANNEL.TXPHINITDONE
CELL[0].OUT_BEL[18]	GTX_CHANNEL.TXSYNCOUT
CELL[0].OUT_BEL[19]	GTX_CHANNEL.SCANOUT[0]
CELL[0].OUT_BEL[20]	GTX_CHANNEL.DRPRDY
CELL[0].OUT_BEL[21]	GTX_CHANNEL.DMONITOROUT[14]
CELL[0].OUT_BEL[22]	GTX_CHANNEL.TXSYNCDONE
CELL[0].OUT_BEL[23]	GTX_CHANNEL.RXHEADER[4]
CELL[0].OUT_GT_RXOUTCLK	GTX_CHANNEL.RXOUTCLK
CELL[0].OUT_GT_TXOUTCLK	GTX_CHANNEL.TXOUTCLK
CELL[1].IMUX_CLK[0]	GTX_CHANNEL.PMASCANCLK[1]
CELL[1].IMUX_CLK[1]	GTX_CHANNEL.DRPCLK
CELL[1].IMUX_CTRL[1]	GTX_CHANNEL.RXPHDLYRESET
CELL[1].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.RXDFETAP7OVRDEN
CELL[1].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.RXDFETAP7HOLD
CELL[1].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.TXPRECURSORINV
CELL[1].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.TXQPIBIASEN
CELL[1].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.TX8B10BBYPASS[7]
CELL[1].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.RXPHDLYPD
CELL[1].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.TXPDELECIDLEMODE
CELL[1].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.TXSYNCMODE
CELL[1].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.TXCOMWAKE
CELL[1].IMUX_IMUX_DELAY[13]	GTX_CHANNEL.TXQPISTRONGPDOWN
CELL[1].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.PMASCANIN[1]
CELL[1].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.TX8B10BBYPASS[3]
CELL[1].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.TXDATA[56]
CELL[1].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.TXDATA[57]
CELL[1].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXDATA[24]
CELL[1].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.TXDATA[25]
CELL[1].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.TXDATA[58]
CELL[1].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.TXDATA[59]
CELL[1].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.TXDATA[26]
CELL[1].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.TXDATA[27]
CELL[1].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[10]
CELL[1].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.RXDFETAP6HOLD
CELL[1].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.TXPIPPMPD
CELL[1].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.TXCOMSAS
CELL[1].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.TXCHARISK[7]
CELL[1].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.SCANIN[1]
CELL[1].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.TXCHARISK[3]
CELL[1].IMUX_IMUX_DELAY[32]	GTX_CHANNEL.DRPDI[15]
CELL[1].IMUX_IMUX_DELAY[33]	GTX_CHANNEL.DRPDI[14]
CELL[1].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.DRPDI[7]
CELL[1].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.DRPDI[6]
CELL[1].IMUX_IMUX_DELAY[36]	GTX_CHANNEL.DRPDI[13]
CELL[1].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.DRPDI[12]
CELL[1].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.DRPDI[5]
CELL[1].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.DRPDI[4]
CELL[1].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[0]
CELL[1].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.TXPOSTCURSORINV
CELL[1].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.RXDFETAP6OVRDEN
CELL[1].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.TSTPD[1]
CELL[1].IMUX_IMUX_DELAY[44]	GTX_CHANNEL.TXCOMINIT
CELL[1].IMUX_IMUX_DELAY[45]	GTX_CHANNEL.TXQPIWEAKPUP
CELL[1].IMUX_IMUX_DELAY[46]	GTX_CHANNEL.DMONFIFORESET
CELL[1].OUT_BEL[0]	GTX_CHANNEL.DRPDO[8]
CELL[1].OUT_BEL[1]	GTX_CHANNEL.DRPDO[13]
CELL[1].OUT_BEL[2]	GTX_CHANNEL.DRPDO[10]
CELL[1].OUT_BEL[3]	GTX_CHANNEL.DRPDO[15]
CELL[1].OUT_BEL[4]	GTX_CHANNEL.DRPDO[9]
CELL[1].OUT_BEL[5]	GTX_CHANNEL.DRPDO[12]
CELL[1].OUT_BEL[6]	GTX_CHANNEL.DRPDO[11]
CELL[1].OUT_BEL[7]	GTX_CHANNEL.DRPDO[14]
CELL[1].OUT_BEL[8]	GTX_CHANNEL.CPLLFBCLKLOST
CELL[1].OUT_BEL[9]	GTX_CHANNEL.PCSRSVDOUT[12]
CELL[1].OUT_BEL[10]	GTX_CHANNEL.TXRUNDISP[4]
CELL[1].OUT_BEL[11]	GTX_CHANNEL.RXDFESLIDETAPSTROBEDONE
CELL[1].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[1]
CELL[1].OUT_BEL[14]	GTX_CHANNEL.CPLLLOCK
CELL[1].OUT_BEL[15]	GTX_CHANNEL.RXQPISENP
CELL[1].OUT_BEL[16]	GTX_CHANNEL.PCSRSVDOUT[15]
CELL[1].OUT_BEL[17]	GTX_CHANNEL.RXQPISENN
CELL[1].OUT_BEL[18]	GTX_CHANNEL.CPLLREFCLKLOST
CELL[1].OUT_BEL[19]	GTX_CHANNEL.SCANOUT[1]
CELL[1].OUT_BEL[20]	GTX_CHANNEL.PMASCANOUT[4]
CELL[1].OUT_BEL[21]	GTX_CHANNEL.DMONITOROUT[13]
CELL[1].OUT_BEL[22]	GTX_CHANNEL.RXDLYSRESETDONE
CELL[1].OUT_BEL[23]	GTX_CHANNEL.RXHEADER[3]
CELL[2].IMUX_CLK[0]	GTX_CHANNEL.CPLLLOCKDETCLK
CELL[2].IMUX_CLK[1]	GTX_CHANNEL.TXPHDLYTSTCLK
CELL[2].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.TX8B10BEN
CELL[2].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.RXMONITORSEL[1]
CELL[2].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.RXOSINTID0[0]
CELL[2].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.RXOSINTID0[1]
CELL[2].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.RXSYNCMODE
CELL[2].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.RXOSINTID0[2]
CELL[2].IMUX_IMUX_DELAY[7]	GTX_CHANNEL.RXOSINTID0[3]
CELL[2].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.TXCHARDISPVAL[2]
CELL[2].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.TXHEADER[2]
CELL[2].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.TXCHARDISPVAL[6]
CELL[2].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.CPLLREFCLKSEL2
CELL[2].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.TXHEADER[1]
CELL[2].IMUX_IMUX_DELAY[13]	GTX_CHANNEL.TXHEADER[0]
CELL[2].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.CPLLREFCLKSEL1
CELL[2].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.CPLLREFCLKSEL0
CELL[2].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.TXDATA[20]
CELL[2].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.TXDATA[21]
CELL[2].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXDATA[52]
CELL[2].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.TXDATA[53]
CELL[2].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.TXDATA[22]
CELL[2].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.TXDATA[23]
CELL[2].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.TXDATA[54]
CELL[2].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.TXDATA[55]
CELL[2].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[11]
CELL[2].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.TXPHALIGN
CELL[2].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.TXPIPPMSEL
CELL[2].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.CPLLLOCKEN
CELL[2].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.TXCHARDISPMODE[2]
CELL[2].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.TXPIPPMOVRDEN
CELL[2].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.TXCHARDISPMODE[6]
CELL[2].IMUX_IMUX_DELAY[32]	GTX_CHANNEL.TXINHIBIT
CELL[2].IMUX_IMUX_DELAY[33]	GTX_CHANNEL.TXPHALIGNEN
CELL[2].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.DRPADDR[3]
CELL[2].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.DRPADDR[2]
CELL[2].IMUX_IMUX_DELAY[36]	GTX_CHANNEL.CPLLPD
CELL[2].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.DRPADDR[1]
CELL[2].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.DRPADDR[0]
CELL[2].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[1]
CELL[2].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.RXSYSCLKSEL[1]
CELL[2].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.TSTPD[2]
CELL[2].IMUX_IMUX_DELAY[45]	GTX_CHANNEL.RXSYSCLKSEL[0]
CELL[2].IMUX_IMUX_DELAY[46]	GTX_CHANNEL.RXOSCALRESET
CELL[2].OUT_BEL[0]	GTX_CHANNEL.RXPHSLIPMONITOR[0]
CELL[2].OUT_BEL[1]	GTX_CHANNEL.RXPHMONITOR[1]
CELL[2].OUT_BEL[2]	GTX_CHANNEL.RXPHSLIPMONITOR[2]
CELL[2].OUT_BEL[3]	GTX_CHANNEL.RXPHMONITOR[3]
CELL[2].OUT_BEL[4]	GTX_CHANNEL.RXPHSLIPMONITOR[1]
CELL[2].OUT_BEL[5]	GTX_CHANNEL.RXPHMONITOR[0]
CELL[2].OUT_BEL[6]	GTX_CHANNEL.RXPHSLIPMONITOR[3]
CELL[2].OUT_BEL[7]	GTX_CHANNEL.RXPHMONITOR[2]
CELL[2].OUT_BEL[9]	GTX_CHANNEL.PCSRSVDOUT[13]
CELL[2].OUT_BEL[10]	GTX_CHANNEL.TXRUNDISP[1]
CELL[2].OUT_BEL[11]	GTX_CHANNEL.RXDFESLIDETAPSTROBESTARTED
CELL[2].OUT_BEL[12]	GTX_CHANNEL.RXPMARESETDONE
CELL[2].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[2]
CELL[2].OUT_BEL[14]	GTX_CHANNEL.TXPMARESETDONE
CELL[2].OUT_BEL[15]	GTX_CHANNEL.DMONITOROUT[12]
CELL[2].OUT_BEL[16]	GTX_CHANNEL.PMASCANOUT[3]
CELL[2].OUT_BEL[17]	GTX_CHANNEL.TXBUFSTATUS[0]
CELL[2].OUT_BEL[18]	GTX_CHANNEL.PMASCANOUT[1]
CELL[2].OUT_BEL[19]	GTX_CHANNEL.SCANOUT[2]
CELL[2].OUT_BEL[20]	GTX_CHANNEL.PMASCANOUT[2]
CELL[2].OUT_BEL[21]	GTX_CHANNEL.TXBUFSTATUS[1]
CELL[2].OUT_BEL[22]	GTX_CHANNEL.PMASCANOUT[0]
CELL[2].OUT_BEL[23]	GTX_CHANNEL.GTREFCLKMONITOR
CELL[3].IMUX_CLK[0]	GTX_CHANNEL.TSTCLK[0]
CELL[3].IMUX_CTRL[0]	GTX_CHANNEL.CPLLRESET
CELL[3].IMUX_CTRL[1]	GTX_CHANNEL.TXPMARESET
CELL[3].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.TXMAINCURSOR[3]
CELL[3].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.TXMAINCURSOR[2]
CELL[3].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.DRPADDR[8]
CELL[3].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.TXSTARTSEQ
CELL[3].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.TXMAINCURSOR[1]
CELL[3].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.TXMAINCURSOR[0]
CELL[3].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.TX8B10BBYPASS[6]
CELL[3].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PCSRSVDIN[8]
CELL[3].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.RXDFESLIDETAPID[1]
CELL[3].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.TXRATEMODE
CELL[3].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.TXPIPPMSTEPSIZE[4]
CELL[3].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.TX8B10BBYPASS[2]
CELL[3].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.TXDATA[48]
CELL[3].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.TXDATA[49]
CELL[3].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXDATA[16]
CELL[3].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.TXDATA[17]
CELL[3].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.TXDATA[50]
CELL[3].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.TXDATA[51]
CELL[3].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.TXDATA[18]
CELL[3].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.TXDATA[19]
CELL[3].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[12]
CELL[3].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.PCSRSVDIN[0]
CELL[3].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.GTRSVD[8]
CELL[3].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.RXDFESLIDETAPID[2]
CELL[3].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.DRPWE
CELL[3].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.TXCHARISK[6]
CELL[3].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.TXPOLARITY
CELL[3].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.TXCHARISK[2]
CELL[3].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.DRPADDR[7]
CELL[3].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.DRPADDR[6]
CELL[3].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.TXPHDLYPD
CELL[3].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.DRPADDR[5]
CELL[3].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.DRPADDR[4]
CELL[3].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[2]
CELL[3].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.RXDFESLIDETAPID[0]
CELL[3].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.GTRSVD[0]
CELL[3].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.TSTPD[3]
CELL[3].IMUX_IMUX_DELAY[44]	GTX_CHANNEL.DRPEN
CELL[3].IMUX_IMUX_DELAY[45]	GTX_CHANNEL.TXDLYSRESET
CELL[3].IMUX_IMUX_DELAY[46]	GTX_CHANNEL.RXDFESLIDETAPID[3]
CELL[3].OUT_BEL[0]	GTX_CHANNEL.RXDATA[63]
CELL[3].OUT_BEL[1]	GTX_CHANNEL.RXDATA[30]
CELL[3].OUT_BEL[2]	GTX_CHANNEL.RXDATA[61]
CELL[3].OUT_BEL[3]	GTX_CHANNEL.RXDATA[28]
CELL[3].OUT_BEL[4]	GTX_CHANNEL.RXDATA[62]
CELL[3].OUT_BEL[5]	GTX_CHANNEL.RXDATA[31]
CELL[3].OUT_BEL[6]	GTX_CHANNEL.RXDATA[60]
CELL[3].OUT_BEL[7]	GTX_CHANNEL.RXDATA[29]
CELL[3].OUT_BEL[8]	GTX_CHANNEL.TXQPISENP
CELL[3].OUT_BEL[9]	GTX_CHANNEL.DMONITOROUT[7]
CELL[3].OUT_BEL[10]	GTX_CHANNEL.TXRUNDISP[5]
CELL[3].OUT_BEL[11]	GTX_CHANNEL.RXDFESTADAPTDONE
CELL[3].OUT_BEL[12]	GTX_CHANNEL.RXCHARISK[7]
CELL[3].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[3]
CELL[3].OUT_BEL[14]	GTX_CHANNEL.RXNOTINTABLE[7]
CELL[3].OUT_BEL[15]	GTX_CHANNEL.RXCHARISCOMMA[3]
CELL[3].OUT_BEL[16]	GTX_CHANNEL.RXPHSLIPMONITOR[4]
CELL[3].OUT_BEL[17]	GTX_CHANNEL.TXDLYSRESETDONE
CELL[3].OUT_BEL[18]	GTX_CHANNEL.TXPHALIGNDONE
CELL[3].OUT_BEL[19]	GTX_CHANNEL.SCANOUT[3]
CELL[3].OUT_BEL[20]	GTX_CHANNEL.TXQPISENN
CELL[3].OUT_BEL[21]	GTX_CHANNEL.RXPHMONITOR[4]
CELL[3].OUT_BEL[22]	GTX_CHANNEL.RXDISPERR[7]
CELL[3].OUT_BEL[23]	GTX_CHANNEL.TXOUTCLKFABRIC
CELL[4].IMUX_CLK[0]	GTX_CHANNEL.TXUSRCLK
CELL[4].IMUX_CLK[1]	GTX_CHANNEL.SIGVALIDCLK
CELL[4].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.RXOSINTHOLD
CELL[4].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.TXPOSTCURSOR[3]
CELL[4].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.TXPOSTCURSOR[2]
CELL[4].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.TXMAINCURSOR[4]
CELL[4].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.TXPOSTCURSOR[1]
CELL[4].IMUX_IMUX_DELAY[7]	GTX_CHANNEL.TXPOSTCURSOR[0]
CELL[4].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.TXCHARDISPVAL[1]
CELL[4].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PCSRSVDIN[9]
CELL[4].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.TXCHARDISPVAL[5]
CELL[4].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.TXPHOVRDEN
CELL[4].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.RXDFESLIDETAPID[5]
CELL[4].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.TXPRBSFORCEERR
CELL[4].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.TXDATA[12]
CELL[4].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.TXDATA[13]
CELL[4].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXDATA[44]
CELL[4].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.TXDATA[45]
CELL[4].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.TXDATA[14]
CELL[4].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.TXDATA[15]
CELL[4].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.TXDATA[46]
CELL[4].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.TXDATA[47]
CELL[4].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[13]
CELL[4].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.PCSRSVDIN[1]
CELL[4].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.GTRSVD[9]
CELL[4].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.TXPIPPMSTEPSIZE[0]
CELL[4].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.TXSYSCLKSEL[1]
CELL[4].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.TXCHARDISPMODE[1]
CELL[4].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.TXCHARDISPMODE[5]
CELL[4].IMUX_IMUX_DELAY[32]	GTX_CHANNEL.RXOSINTTESTOVRDEN
CELL[4].IMUX_IMUX_DELAY[33]	GTX_CHANNEL.RXOSINTSTROBE
CELL[4].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.SETERRSTATUS
CELL[4].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.TXMARGIN[2]
CELL[4].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.TXDIFFPD
CELL[4].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.TXMARGIN[1]
CELL[4].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.TXMARGIN[0]
CELL[4].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[3]
CELL[4].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.RXOSINTOVRDEN
CELL[4].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.GTRSVD[1]
CELL[4].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.TSTPD[4]
CELL[4].IMUX_IMUX_DELAY[46]	GTX_CHANNEL.RXDFESLIDETAPID[4]
CELL[4].OUT_BEL[0]	GTX_CHANNEL.RXDATA[27]
CELL[4].OUT_BEL[1]	GTX_CHANNEL.RXDATA[58]
CELL[4].OUT_BEL[2]	GTX_CHANNEL.RXDATA[25]
CELL[4].OUT_BEL[3]	GTX_CHANNEL.RXDATA[56]
CELL[4].OUT_BEL[4]	GTX_CHANNEL.RXDATA[26]
CELL[4].OUT_BEL[5]	GTX_CHANNEL.RXDATA[59]
CELL[4].OUT_BEL[6]	GTX_CHANNEL.RXDATA[24]
CELL[4].OUT_BEL[7]	GTX_CHANNEL.RXDATA[57]
CELL[4].OUT_BEL[8]	GTX_CHANNEL.RXMONITOROUT[6]
CELL[4].OUT_BEL[9]	GTX_CHANNEL.DMONITOROUT[6]
CELL[4].OUT_BEL[10]	GTX_CHANNEL.TXRUNDISP[2]
CELL[4].OUT_BEL[11]	GTX_CHANNEL.RXOSINTSTARTED
CELL[4].OUT_BEL[12]	GTX_CHANNEL.RXCHARISK[3]
CELL[4].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[4]
CELL[4].OUT_BEL[14]	GTX_CHANNEL.RXNOTINTABLE[3]
CELL[4].OUT_BEL[15]	GTX_CHANNEL.RXCHARISCOMMA[7]
CELL[4].OUT_BEL[16]	GTX_CHANNEL.TXRESETDONE
CELL[4].OUT_BEL[17]	GTX_CHANNEL.TXOUTCLKPCS
CELL[4].OUT_BEL[18]	GTX_CHANNEL.RXPHALIGNDONE
CELL[4].OUT_BEL[19]	GTX_CHANNEL.SCANOUT[4]
CELL[4].OUT_BEL[20]	GTX_CHANNEL.TXRATEDONE
CELL[4].OUT_BEL[21]	GTX_CHANNEL.DMONITOROUT[11]
CELL[4].OUT_BEL[22]	GTX_CHANNEL.RXDISPERR[3]
CELL[4].OUT_BEL[23]	GTX_CHANNEL.TXGEARBOXREADY
CELL[5].IMUX_CLK[0]	GTX_CHANNEL.TXUSRCLK2
CELL[5].IMUX_CLK[1]	GTX_CHANNEL.DMONITORCLK
CELL[5].IMUX_CTRL[0]	GTX_CHANNEL.GTTXRESET
CELL[5].IMUX_CTRL[1]	GTX_CHANNEL.CFGRESET
CELL[5].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.TXSEQUENCE[3]
CELL[5].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.TXSEQUENCE[2]
CELL[5].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.TXDIFFCTRL[3]
CELL[5].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.TXDIFFCTRL[2]
CELL[5].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.TXSEQUENCE[1]
CELL[5].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.TXSEQUENCE[0]
CELL[5].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.TXDIFFCTRL[1]
CELL[5].IMUX_IMUX_DELAY[7]	GTX_CHANNEL.TXDIFFCTRL[0]
CELL[5].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.TX8B10BBYPASS[5]
CELL[5].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PCSRSVDIN[10]
CELL[5].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.TXUSERRDY
CELL[5].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.TXDLYHOLD
CELL[5].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.TXDLYOVRDEN
CELL[5].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.TXDLYEN
CELL[5].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.TX8B10BBYPASS[1]
CELL[5].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.TXDATA[40]
CELL[5].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.TXDATA[41]
CELL[5].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXDATA[8]
CELL[5].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.TXDATA[9]
CELL[5].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.TXDATA[42]
CELL[5].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.TXDATA[43]
CELL[5].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.TXDATA[10]
CELL[5].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.TXDATA[11]
CELL[5].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[14]
CELL[5].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.PCSRSVDIN[2]
CELL[5].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.GTRSVD[10]
CELL[5].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.TXPHINIT
CELL[5].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.TXSYSCLKSEL[0]
CELL[5].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.TXCHARISK[5]
CELL[5].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.TXDLYTESTENB
CELL[5].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.TXCHARISK[1]
CELL[5].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.TXDEEMPH
CELL[5].IMUX_IMUX_DELAY[36]	GTX_CHANNEL.TXPHDLYRESET
CELL[5].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.RXADAPTSELTEST[11]
CELL[5].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.TXSWING
CELL[5].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.TXDETECTRX
CELL[5].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[4]
CELL[5].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.RESETOVRD
CELL[5].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.GTRSVD[2]
CELL[5].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.TXDLYUPDOWN
CELL[5].IMUX_IMUX_DELAY[44]	GTX_CHANNEL.TXDLYBYPASS
CELL[5].IMUX_IMUX_DELAY[45]	GTX_CHANNEL.SCANIN[5]
CELL[5].OUT_BEL[0]	GTX_CHANNEL.RXDATA[55]
CELL[5].OUT_BEL[1]	GTX_CHANNEL.RXDATA[22]
CELL[5].OUT_BEL[2]	GTX_CHANNEL.RXDATA[53]
CELL[5].OUT_BEL[3]	GTX_CHANNEL.RXDATA[20]
CELL[5].OUT_BEL[4]	GTX_CHANNEL.RXDATA[54]
CELL[5].OUT_BEL[5]	GTX_CHANNEL.RXDATA[23]
CELL[5].OUT_BEL[6]	GTX_CHANNEL.RXDATA[52]
CELL[5].OUT_BEL[7]	GTX_CHANNEL.RXDATA[21]
CELL[5].OUT_BEL[8]	GTX_CHANNEL.RXMONITOROUT[5]
CELL[5].OUT_BEL[9]	GTX_CHANNEL.DMONITOROUT[5]
CELL[5].OUT_BEL[10]	GTX_CHANNEL.TXRUNDISP[6]
CELL[5].OUT_BEL[11]	GTX_CHANNEL.RXOSINTSTROBEDONE
CELL[5].OUT_BEL[12]	GTX_CHANNEL.RXCHARISK[6]
CELL[5].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[5]
CELL[5].OUT_BEL[14]	GTX_CHANNEL.RXNOTINTABLE[6]
CELL[5].OUT_BEL[15]	GTX_CHANNEL.RXCHARISCOMMA[2]
CELL[5].OUT_BEL[16]	GTX_CHANNEL.TXCOMFINISH
CELL[5].OUT_BEL[17]	GTX_CHANNEL.RXCDRLOCK
CELL[5].OUT_BEL[18]	GTX_CHANNEL.RXCLKCORCNT[0]
CELL[5].OUT_BEL[19]	GTX_CHANNEL.RXDATAVALID[0]
CELL[5].OUT_BEL[20]	GTX_CHANNEL.RXCLKCORCNT[1]
CELL[5].OUT_BEL[21]	GTX_CHANNEL.DMONITOROUT[10]
CELL[5].OUT_BEL[22]	GTX_CHANNEL.RXDISPERR[6]
CELL[5].OUT_BEL[23]	GTX_CHANNEL.RXRATEDONE
CELL[6].IMUX_CLK[0]	GTX_CHANNEL.RXUSRCLK
CELL[6].IMUX_CLK[1]	GTX_CHANNEL.GTGREFCLK
CELL[6].IMUX_CTRL[0]	GTX_CHANNEL.RXDLYSRESET
CELL[6].IMUX_CTRL[1]	GTX_CHANNEL.RXBUFRESET
CELL[6].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.TXSEQUENCE[6]
CELL[6].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.TXPRECURSOR[3]
CELL[6].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.TXPRECURSOR[2]
CELL[6].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.TXSEQUENCE[5]
CELL[6].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.TXSEQUENCE[4]
CELL[6].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.TXPRECURSOR[1]
CELL[6].IMUX_IMUX_DELAY[7]	GTX_CHANNEL.TXPRECURSOR[0]
CELL[6].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.TXCHARDISPVAL[0]
CELL[6].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PCSRSVDIN[11]
CELL[6].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.TXCHARDISPVAL[4]
CELL[6].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.RXRATE[2]
CELL[6].IMUX_IMUX_DELAY[13]	GTX_CHANNEL.RXADAPTSELTEST[12]
CELL[6].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.RXRATE[1]
CELL[6].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.RXRATE[0]
CELL[6].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.TXDATA[4]
CELL[6].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.TXDATA[5]
CELL[6].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXDATA[36]
CELL[6].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.TXDATA[37]
CELL[6].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.TXDATA[6]
CELL[6].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.TXDATA[7]
CELL[6].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.TXDATA[38]
CELL[6].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.TXDATA[39]
CELL[6].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[15]
CELL[6].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.PCSRSVDIN[3]
CELL[6].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.GTRSVD[11]
CELL[6].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.RXDLYEN
CELL[6].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.TXCHARDISPMODE[0]
CELL[6].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.TXCHARDISPMODE[4]
CELL[6].IMUX_IMUX_DELAY[32]	GTX_CHANNEL.RXADAPTSELTEST[10]
CELL[6].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.RXADAPTSELTEST[7]
CELL[6].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.TXPD[1]
CELL[6].IMUX_IMUX_DELAY[36]	GTX_CHANNEL.RXADAPTSELTEST[9]
CELL[6].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.RXADAPTSELTEST[8]
CELL[6].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.TXPD[0]
CELL[6].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.TXELECIDLE
CELL[6].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[5]
CELL[6].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.RXPHALIGNEN
CELL[6].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.GTRSVD[3]
CELL[6].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.TXRATE[2]
CELL[6].IMUX_IMUX_DELAY[44]	GTX_CHANNEL.RXADAPTSELTEST[13]
CELL[6].IMUX_IMUX_DELAY[46]	GTX_CHANNEL.TXRATE[1]
CELL[6].IMUX_IMUX_DELAY[47]	GTX_CHANNEL.TXRATE[0]
CELL[6].OUT_BEL[0]	GTX_CHANNEL.RXDATA[19]
CELL[6].OUT_BEL[1]	GTX_CHANNEL.RXDATA[50]
CELL[6].OUT_BEL[2]	GTX_CHANNEL.RXDATA[17]
CELL[6].OUT_BEL[3]	GTX_CHANNEL.RXDATA[48]
CELL[6].OUT_BEL[4]	GTX_CHANNEL.RXDATA[18]
CELL[6].OUT_BEL[5]	GTX_CHANNEL.RXDATA[51]
CELL[6].OUT_BEL[6]	GTX_CHANNEL.RXDATA[16]
CELL[6].OUT_BEL[7]	GTX_CHANNEL.RXDATA[49]
CELL[6].OUT_BEL[8]	GTX_CHANNEL.RXMONITOROUT[4]
CELL[6].OUT_BEL[9]	GTX_CHANNEL.DMONITOROUT[4]
CELL[6].OUT_BEL[10]	GTX_CHANNEL.TXRUNDISP[3]
CELL[6].OUT_BEL[11]	GTX_CHANNEL.RXOSINTSTROBESTARTED
CELL[6].OUT_BEL[12]	GTX_CHANNEL.RXCHARISK[2]
CELL[6].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[6]
CELL[6].OUT_BEL[14]	GTX_CHANNEL.RXNOTINTABLE[2]
CELL[6].OUT_BEL[15]	GTX_CHANNEL.RXCHARISCOMMA[6]
CELL[6].OUT_BEL[16]	GTX_CHANNEL.RXCHBONDO[4]
CELL[6].OUT_BEL[17]	GTX_CHANNEL.RXHEADER[2]
CELL[6].OUT_BEL[18]	GTX_CHANNEL.RXDATAVALID[1]
CELL[6].OUT_BEL[19]	GTX_CHANNEL.RXHEADER[0]
CELL[6].OUT_BEL[20]	GTX_CHANNEL.RXPRBSERR
CELL[6].OUT_BEL[21]	GTX_CHANNEL.DMONITOROUT[9]
CELL[6].OUT_BEL[22]	GTX_CHANNEL.RXDISPERR[2]
CELL[6].OUT_BEL[23]	GTX_CHANNEL.RXHEADER[1]
CELL[7].IMUX_CLK[0]	GTX_CHANNEL.RXUSRCLK2
CELL[7].IMUX_CLK[1]	GTX_CHANNEL.CLKRSVD[0]
CELL[7].IMUX_CTRL[0]	GTX_CHANNEL.RXCDRFREQRESET
CELL[7].IMUX_CTRL[1]	GTX_CHANNEL.RXPMARESET
CELL[7].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.TXMAINCURSOR[5]
CELL[7].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.TXMAINCURSOR[6]
CELL[7].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.RXRATEMODE
CELL[7].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.RXPD[0]
CELL[7].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.TXPOSTCURSOR[4]
CELL[7].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.PMASCANIN[7]
CELL[7].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.RXADAPTSELTEST[1]
CELL[7].IMUX_IMUX_DELAY[7]	GTX_CHANNEL.TXPRECURSOR[4]
CELL[7].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.TX8B10BBYPASS[4]
CELL[7].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PCSRSVDIN[12]
CELL[7].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.TXBUFDIFFCTRL[2]
CELL[7].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.RXDFESLIDETAPADAPTEN
CELL[7].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.TXBUFDIFFCTRL[0]
CELL[7].IMUX_IMUX_DELAY[13]	GTX_CHANNEL.TXBUFDIFFCTRL[1]
CELL[7].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.RXPCSRESET
CELL[7].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.TX8B10BBYPASS[0]
CELL[7].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.TXDATA[35]
CELL[7].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.TXDATA[34]
CELL[7].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXDATA[0]
CELL[7].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.TXDATA[1]
CELL[7].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.TXDATA[33]
CELL[7].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.TXDATA[32]
CELL[7].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.TXDATA[2]
CELL[7].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.TXDATA[3]
CELL[7].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[16]
CELL[7].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.PCSRSVDIN[4]
CELL[7].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.GTRSVD[12]
CELL[7].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.RXPOLARITY
CELL[7].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.RXDEBUGPULSE
CELL[7].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.TXCHARISK[4]
CELL[7].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.TXPCSRESET
CELL[7].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.TXCHARISK[0]
CELL[7].IMUX_IMUX_DELAY[32]	GTX_CHANNEL.RXADAPTSELTEST[6]
CELL[7].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.RXADAPTSELTEST[3]
CELL[7].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.RXADAPTSELTEST[2]
CELL[7].IMUX_IMUX_DELAY[36]	GTX_CHANNEL.RXADAPTSELTEST[5]
CELL[7].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.RXADAPTSELTEST[4]
CELL[7].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.RXDLYOVRDEN
CELL[7].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.RXADAPTSELTEST[0]
CELL[7].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[6]
CELL[7].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.RXDFESLIDETAPONLYADAPTEN
CELL[7].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.GTRSVD[4]
CELL[7].OUT_BEL[0]	GTX_CHANNEL.RXDATA[47]
CELL[7].OUT_BEL[1]	GTX_CHANNEL.RXDATA[14]
CELL[7].OUT_BEL[2]	GTX_CHANNEL.RXDATA[45]
CELL[7].OUT_BEL[3]	GTX_CHANNEL.RXDATA[12]
CELL[7].OUT_BEL[4]	GTX_CHANNEL.RXDATA[46]
CELL[7].OUT_BEL[5]	GTX_CHANNEL.RXDATA[15]
CELL[7].OUT_BEL[6]	GTX_CHANNEL.RXDATA[44]
CELL[7].OUT_BEL[7]	GTX_CHANNEL.RXDATA[13]
CELL[7].OUT_BEL[8]	GTX_CHANNEL.RXMONITOROUT[3]
CELL[7].OUT_BEL[9]	GTX_CHANNEL.DMONITOROUT[3]
CELL[7].OUT_BEL[10]	GTX_CHANNEL.TXRUNDISP[7]
CELL[7].OUT_BEL[11]	GTX_CHANNEL.SCANOUT[5]
CELL[7].OUT_BEL[12]	GTX_CHANNEL.RXCHARISK[5]
CELL[7].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[7]
CELL[7].OUT_BEL[14]	GTX_CHANNEL.RXNOTINTABLE[5]
CELL[7].OUT_BEL[15]	GTX_CHANNEL.RXCHARISCOMMA[1]
CELL[7].OUT_BEL[16]	GTX_CHANNEL.RXCHBONDO[3]
CELL[7].OUT_BEL[17]	GTX_CHANNEL.RXHEADERVALID[1]
CELL[7].OUT_BEL[18]	GTX_CHANNEL.RXCOMSASDET
CELL[7].OUT_BEL[19]	GTX_CHANNEL.RXCOMMADET
CELL[7].OUT_BEL[20]	GTX_CHANNEL.RXCOMINITDET
CELL[7].OUT_BEL[21]	GTX_CHANNEL.DMONITOROUT[8]
CELL[7].OUT_BEL[22]	GTX_CHANNEL.RXDISPERR[5]
CELL[7].OUT_BEL[23]	GTX_CHANNEL.RXHEADERVALID[0]
CELL[8].IMUX_CLK[0]	GTX_CHANNEL.PMASCANCLK[2]
CELL[8].IMUX_CLK[1]	GTX_CHANNEL.CLKRSVD[1]
CELL[8].IMUX_CTRL[0]	GTX_CHANNEL.GTRXRESET
CELL[8].IMUX_CTRL[1]	GTX_CHANNEL.RXCDRRESETRSV
CELL[8].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.PMARSVDIN[4]
CELL[8].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.TXOUTCLKSEL[2]
CELL[8].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.RXGEARBOXSLIP
CELL[8].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.TXPRBSSEL[0]
CELL[8].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.TXOUTCLKSEL[1]
CELL[8].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.TXOUTCLKSEL[0]
CELL[8].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.TXPRBSSEL[1]
CELL[8].IMUX_IMUX_DELAY[7]	GTX_CHANNEL.TXPRBSSEL[2]
CELL[8].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.RXDDIEN
CELL[8].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PCSRSVDIN[13]
CELL[8].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.RXDLYTESTENB
CELL[8].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.RXDFEVSEN
CELL[8].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.RXSLIDE
CELL[8].IMUX_IMUX_DELAY[13]	GTX_CHANNEL.RXOSOVRDEN
CELL[8].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.RXCDROVRDEN
CELL[8].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.RXDFESLIDETAPHOLD
CELL[8].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.RXOSINTNTRLEN
CELL[8].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.TXPIPPMSTEPSIZE[1]
CELL[8].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.RXDFEVPHOLD
CELL[8].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.PMASCANIN[2]
CELL[8].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.RXPRBSSEL[0]
CELL[8].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.RXPRBSSEL[2]
CELL[8].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[17]
CELL[8].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.PCSRSVDIN[5]
CELL[8].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.GTRSVD[13]
CELL[8].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.RXDFEVPOVRDEN
CELL[8].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.RXPD[1]
CELL[8].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.RXOSHOLD
CELL[8].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.RXCDRHOLD
CELL[8].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.EYESCANTRIGGER
CELL[8].IMUX_IMUX_DELAY[32]	GTX_CHANNEL.RXDLYBYPASS
CELL[8].IMUX_IMUX_DELAY[33]	GTX_CHANNEL.SCANIN[2]
CELL[8].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.RXLPMEN
CELL[8].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.RXDFEUTOVRDEN
CELL[8].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.TXPIPPMSTEPSIZE[2]
CELL[8].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.RXPRBSSEL[1]
CELL[8].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[7]
CELL[8].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.RXOSINTEN
CELL[8].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.GTRSVD[5]
CELL[8].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.RXDFESLIDETAPINITOVRDEN
CELL[8].IMUX_IMUX_DELAY[44]	GTX_CHANNEL.RXUSERRDY
CELL[8].IMUX_IMUX_DELAY[45]	GTX_CHANNEL.EYESCANRESET
CELL[8].OUT_BEL[0]	GTX_CHANNEL.RXDATA[11]
CELL[8].OUT_BEL[1]	GTX_CHANNEL.RXDATA[42]
CELL[8].OUT_BEL[2]	GTX_CHANNEL.RXDATA[9]
CELL[8].OUT_BEL[3]	GTX_CHANNEL.RXDATA[40]
CELL[8].OUT_BEL[4]	GTX_CHANNEL.RXDATA[10]
CELL[8].OUT_BEL[5]	GTX_CHANNEL.RXDATA[43]
CELL[8].OUT_BEL[6]	GTX_CHANNEL.RXDATA[8]
CELL[8].OUT_BEL[7]	GTX_CHANNEL.RXDATA[41]
CELL[8].OUT_BEL[8]	GTX_CHANNEL.RXMONITOROUT[2]
CELL[8].OUT_BEL[9]	GTX_CHANNEL.DMONITOROUT[2]
CELL[8].OUT_BEL[10]	GTX_CHANNEL.RXCHANBONDSEQ
CELL[8].OUT_BEL[11]	GTX_CHANNEL.PMASCANOUT[6]
CELL[8].OUT_BEL[12]	GTX_CHANNEL.RXCHARISK[1]
CELL[8].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[8]
CELL[8].OUT_BEL[14]	GTX_CHANNEL.RXNOTINTABLE[1]
CELL[8].OUT_BEL[15]	GTX_CHANNEL.RXCHARISCOMMA[5]
CELL[8].OUT_BEL[16]	GTX_CHANNEL.RXCHBONDO[2]
CELL[8].OUT_BEL[17]	GTX_CHANNEL.RXSTATUS[1]
CELL[8].OUT_BEL[18]	GTX_CHANNEL.RXSTARTOFSEQ[0]
CELL[8].OUT_BEL[19]	GTX_CHANNEL.RXELECIDLE
CELL[8].OUT_BEL[20]	GTX_CHANNEL.RXRESETDONE
CELL[8].OUT_BEL[21]	GTX_CHANNEL.RXSTATUS[0]
CELL[8].OUT_BEL[22]	GTX_CHANNEL.RXDISPERR[1]
CELL[8].OUT_BEL[23]	GTX_CHANNEL.RXSTATUS[2]
CELL[9].IMUX_CLK[0]	GTX_CHANNEL.PMASCANCLK[3]
CELL[9].IMUX_CLK[1]	GTX_CHANNEL.SCANCLK
CELL[9].IMUX_CTRL[0]	GTX_CHANNEL.RXDFELPMRESET
CELL[9].IMUX_CTRL[1]	GTX_CHANNEL.RXCDRRESET
CELL[9].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.PMARSVDIN[3]
CELL[9].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.PMARSVDIN[2]
CELL[9].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.RXMCOMMAALIGNEN
CELL[9].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.RXDFEUTHOLD
CELL[9].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.PMARSVDIN[1]
CELL[9].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.PMARSVDIN[0]
CELL[9].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.RXDFESLIDETAP[4]
CELL[9].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.RXDFESLIDETAP[0]
CELL[9].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PCSRSVDIN[14]
CELL[9].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.RXQPIEN
CELL[9].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.RX8B10BEN
CELL[9].IMUX_IMUX_DELAY[13]	GTX_CHANNEL.RXDFETAP5OVRDEN
CELL[9].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.RXPHALIGN
CELL[9].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.RXDFESLIDETAP[2]
CELL[9].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.RXDFESLIDETAPSTROBE
CELL[9].IMUX_IMUX_DELAY[17]	GTX_CHANNEL.RXCHBONDEN
CELL[9].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.RXCHBONDI[0]
CELL[9].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.RXCHBONDI[1]
CELL[9].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.PMASCANIN[3]
CELL[9].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.RXDFETAP4OVRDEN
CELL[9].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.RXCHBONDI[2]
CELL[9].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.RXCHBONDI[3]
CELL[9].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[18]
CELL[9].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.PCSRSVDIN[6]
CELL[9].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.GTRSVD[14]
CELL[9].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.RXDFELFOVRDEN
CELL[9].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.RXDFETAP5HOLD
CELL[9].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.RXCHBONDMASTER
CELL[9].IMUX_IMUX_DELAY[32]	GTX_CHANNEL.RXDFESLIDETAPOVRDEN
CELL[9].IMUX_IMUX_DELAY[33]	GTX_CHANNEL.SCANIN[3]
CELL[9].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.RXPCOMMAALIGNEN
CELL[9].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.RXDFELFHOLD
CELL[9].IMUX_IMUX_DELAY[36]	GTX_CHANNEL.PMASCANENB
CELL[9].IMUX_IMUX_DELAY[37]	GTX_CHANNEL.RXDFETAP4HOLD
CELL[9].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.PCSRSVDIN2[4]
CELL[9].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[8]
CELL[9].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.RXDFESLIDETAP[1]
CELL[9].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.GTRSVD[6]
CELL[9].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.LOOPBACK[0]
CELL[9].IMUX_IMUX_DELAY[44]	GTX_CHANNEL.RXCOMMADETEN
CELL[9].IMUX_IMUX_DELAY[45]	GTX_CHANNEL.RXDFEXYDEN
CELL[9].IMUX_IMUX_DELAY[46]	GTX_CHANNEL.LOOPBACK[1]
CELL[9].IMUX_IMUX_DELAY[47]	GTX_CHANNEL.LOOPBACK[2]
CELL[9].OUT_BEL[0]	GTX_CHANNEL.RXDATA[39]
CELL[9].OUT_BEL[1]	GTX_CHANNEL.RXDATA[6]
CELL[9].OUT_BEL[2]	GTX_CHANNEL.RXDATA[37]
CELL[9].OUT_BEL[3]	GTX_CHANNEL.RXDATA[4]
CELL[9].OUT_BEL[4]	GTX_CHANNEL.RXDATA[38]
CELL[9].OUT_BEL[5]	GTX_CHANNEL.RXDATA[7]
CELL[9].OUT_BEL[6]	GTX_CHANNEL.RXDATA[36]
CELL[9].OUT_BEL[7]	GTX_CHANNEL.RXDATA[5]
CELL[9].OUT_BEL[8]	GTX_CHANNEL.RXMONITOROUT[1]
CELL[9].OUT_BEL[9]	GTX_CHANNEL.DMONITOROUT[1]
CELL[9].OUT_BEL[10]	GTX_CHANNEL.PHYSTATUS
CELL[9].OUT_BEL[11]	GTX_CHANNEL.PMASCANOUT[5]
CELL[9].OUT_BEL[12]	GTX_CHANNEL.RXCHARISK[4]
CELL[9].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[9]
CELL[9].OUT_BEL[14]	GTX_CHANNEL.RXNOTINTABLE[4]
CELL[9].OUT_BEL[15]	GTX_CHANNEL.RXCHARISCOMMA[0]
CELL[9].OUT_BEL[16]	GTX_CHANNEL.RXCHBONDO[1]
CELL[9].OUT_BEL[17]	GTX_CHANNEL.RXOUTCLKFABRIC
CELL[9].OUT_BEL[18]	GTX_CHANNEL.RXCHANISALIGNED
CELL[9].OUT_BEL[19]	GTX_CHANNEL.RXCOMWAKEDET
CELL[9].OUT_BEL[20]	GTX_CHANNEL.RXVALID
CELL[9].OUT_BEL[21]	GTX_CHANNEL.RXOUTCLKPCS
CELL[9].OUT_BEL[22]	GTX_CHANNEL.RXDISPERR[4]
CELL[9].OUT_BEL[23]	GTX_CHANNEL.RXCHANREALIGN
CELL[10].IMUX_CLK[0]	GTX_CHANNEL.PMASCANCLK[4]
CELL[10].IMUX_CLK[1]	GTX_CHANNEL.TSTCLK[1]
CELL[10].IMUX_CTRL[0]	GTX_CHANNEL.GTRESETSEL
CELL[10].IMUX_CTRL[1]	GTX_CHANNEL.RXOOBRESET
CELL[10].IMUX_IMUX_DELAY[0]	GTX_CHANNEL.RXELECIDLEMODE[0]
CELL[10].IMUX_IMUX_DELAY[1]	GTX_CHANNEL.RXELECIDLEMODE[1]
CELL[10].IMUX_IMUX_DELAY[2]	GTX_CHANNEL.RXOUTCLKSEL[2]
CELL[10].IMUX_IMUX_DELAY[3]	GTX_CHANNEL.RXLPMLFKLOVRDEN
CELL[10].IMUX_IMUX_DELAY[4]	GTX_CHANNEL.RXOUTCLKSEL[0]
CELL[10].IMUX_IMUX_DELAY[5]	GTX_CHANNEL.RXOUTCLKSEL[1]
CELL[10].IMUX_IMUX_DELAY[6]	GTX_CHANNEL.RXDFESLIDETAP[3]
CELL[10].IMUX_IMUX_DELAY[8]	GTX_CHANNEL.RXDFEAGCTRL[4]
CELL[10].IMUX_IMUX_DELAY[9]	GTX_CHANNEL.PCSRSVDIN[15]
CELL[10].IMUX_IMUX_DELAY[10]	GTX_CHANNEL.RXDFEAGCTRL[2]
CELL[10].IMUX_IMUX_DELAY[11]	GTX_CHANNEL.RXLPMLFHOLD
CELL[10].IMUX_IMUX_DELAY[12]	GTX_CHANNEL.RXDFETAP3OVRDEN
CELL[10].IMUX_IMUX_DELAY[13]	GTX_CHANNEL.RXPRBSCNTRESET
CELL[10].IMUX_IMUX_DELAY[14]	GTX_CHANNEL.RXPHOVRDEN
CELL[10].IMUX_IMUX_DELAY[15]	GTX_CHANNEL.TXPIPPMSTEPSIZE[3]
CELL[10].IMUX_IMUX_DELAY[16]	GTX_CHANNEL.RXDFECM1EN
CELL[10].IMUX_IMUX_DELAY[18]	GTX_CHANNEL.RXCHBONDLEVEL[0]
CELL[10].IMUX_IMUX_DELAY[19]	GTX_CHANNEL.RXCHBONDLEVEL[1]
CELL[10].IMUX_IMUX_DELAY[20]	GTX_CHANNEL.PMASCANIN[4]
CELL[10].IMUX_IMUX_DELAY[21]	GTX_CHANNEL.RXDFEAGCOVRDEN
CELL[10].IMUX_IMUX_DELAY[22]	GTX_CHANNEL.RXCHBONDLEVEL[2]
CELL[10].IMUX_IMUX_DELAY[23]	GTX_CHANNEL.RXCHBONDI[4]
CELL[10].IMUX_IMUX_DELAY[24]	GTX_CHANNEL.TSTIN[19]
CELL[10].IMUX_IMUX_DELAY[25]	GTX_CHANNEL.PCSRSVDIN[7]
CELL[10].IMUX_IMUX_DELAY[26]	GTX_CHANNEL.GTRSVD[15]
CELL[10].IMUX_IMUX_DELAY[27]	GTX_CHANNEL.RXLPMHFOVRDEN
CELL[10].IMUX_IMUX_DELAY[28]	GTX_CHANNEL.RXDFETAP2OVRDEN
CELL[10].IMUX_IMUX_DELAY[29]	GTX_CHANNEL.RXDFEAGCHOLD
CELL[10].IMUX_IMUX_DELAY[30]	GTX_CHANNEL.RXCHBONDSLAVE
CELL[10].IMUX_IMUX_DELAY[31]	GTX_CHANNEL.RXDFEAGCTRL[0]
CELL[10].IMUX_IMUX_DELAY[33]	GTX_CHANNEL.SCANIN[4]
CELL[10].IMUX_IMUX_DELAY[34]	GTX_CHANNEL.PCSRSVDIN2[0]
CELL[10].IMUX_IMUX_DELAY[35]	GTX_CHANNEL.PCSRSVDIN2[1]
CELL[10].IMUX_IMUX_DELAY[36]	GTX_CHANNEL.RXDFETAP3HOLD
CELL[10].IMUX_IMUX_DELAY[38]	GTX_CHANNEL.PCSRSVDIN2[2]
CELL[10].IMUX_IMUX_DELAY[39]	GTX_CHANNEL.PCSRSVDIN2[3]
CELL[10].IMUX_IMUX_DELAY[40]	GTX_CHANNEL.TSTIN[9]
CELL[10].IMUX_IMUX_DELAY[41]	GTX_CHANNEL.RXDFEAGCTRL[3]
CELL[10].IMUX_IMUX_DELAY[42]	GTX_CHANNEL.GTRSVD[7]
CELL[10].IMUX_IMUX_DELAY[43]	GTX_CHANNEL.RXLPMHFHOLD
CELL[10].IMUX_IMUX_DELAY[44]	GTX_CHANNEL.RXDFETAP2HOLD
CELL[10].IMUX_IMUX_DELAY[45]	GTX_CHANNEL.RXMONITORSEL[0]
CELL[10].IMUX_IMUX_DELAY[46]	GTX_CHANNEL.RXDFEAGCTRL[1]
CELL[10].OUT_BEL[0]	GTX_CHANNEL.RXDATA[3]
CELL[10].OUT_BEL[1]	GTX_CHANNEL.RXDATA[34]
CELL[10].OUT_BEL[2]	GTX_CHANNEL.RXDATA[1]
CELL[10].OUT_BEL[3]	GTX_CHANNEL.RXDATA[32]
CELL[10].OUT_BEL[4]	GTX_CHANNEL.RXDATA[2]
CELL[10].OUT_BEL[5]	GTX_CHANNEL.RXDATA[35]
CELL[10].OUT_BEL[6]	GTX_CHANNEL.RXDATA[0]
CELL[10].OUT_BEL[7]	GTX_CHANNEL.RXDATA[33]
CELL[10].OUT_BEL[8]	GTX_CHANNEL.RXMONITOROUT[0]
CELL[10].OUT_BEL[9]	GTX_CHANNEL.DMONITOROUT[0]
CELL[10].OUT_BEL[10]	GTX_CHANNEL.RXBYTEREALIGN
CELL[10].OUT_BEL[11]	GTX_CHANNEL.RXSTARTOFSEQ[1]
CELL[10].OUT_BEL[12]	GTX_CHANNEL.RXCHARISK[0]
CELL[10].OUT_BEL[13]	GTX_CHANNEL.PCSRSVDOUT[10]
CELL[10].OUT_BEL[14]	GTX_CHANNEL.RXNOTINTABLE[0]
CELL[10].OUT_BEL[15]	GTX_CHANNEL.RXCHARISCOMMA[4]
CELL[10].OUT_BEL[16]	GTX_CHANNEL.RXCHBONDO[0]
CELL[10].OUT_BEL[17]	GTX_CHANNEL.RXBUFSTATUS[2]
CELL[10].OUT_BEL[18]	GTX_CHANNEL.RXBYTEISALIGNED
CELL[10].OUT_BEL[19]	GTX_CHANNEL.RXBUFSTATUS[1]
CELL[10].OUT_BEL[20]	GTX_CHANNEL.EYESCANDATAERROR
CELL[10].OUT_BEL[21]	GTX_CHANNEL.PMASCANOUT[7]
CELL[10].OUT_BEL[22]	GTX_CHANNEL.RXDISPERR[0]
CELL[10].OUT_BEL[23]	GTX_CHANNEL.RXBUFSTATUS[0]

Bitstream

virtex7 GTH_CHANNEL rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[7] bit 14 GTX_CHANNEL: A_TXMAINCURSOR bit 6	GTX_CHANNEL: DRP[7] bit 15 GTX_CHANNEL: A_SPARE bit 0	GTX_CHANNEL: DRP[95] bit 14 GTX_CHANNEL: CPLL_LOCK_CFG bit 14	GTX_CHANNEL: DRP[95] bit 15 GTX_CHANNEL: CPLL_LOCK_CFG bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[7] bit 12 GTX_CHANNEL: A_TXMAINCURSOR bit 4	GTX_CHANNEL: DRP[7] bit 13 GTX_CHANNEL: A_TXMAINCURSOR bit 5	GTX_CHANNEL: DRP[95] bit 12 GTX_CHANNEL: CPLL_LOCK_CFG bit 12	GTX_CHANNEL: DRP[95] bit 13 GTX_CHANNEL: CPLL_LOCK_CFG bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[7] bit 10 GTX_CHANNEL: A_TXMAINCURSOR bit 2	GTX_CHANNEL: DRP[7] bit 11 GTX_CHANNEL: A_TXMAINCURSOR bit 3	GTX_CHANNEL: DRP[95] bit 10 GTX_CHANNEL: CPLL_LOCK_CFG bit 10	GTX_CHANNEL: DRP[95] bit 11 GTX_CHANNEL: CPLL_LOCK_CFG bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[7] bit 8 GTX_CHANNEL: A_TXMAINCURSOR bit 0	GTX_CHANNEL: DRP[7] bit 9 GTX_CHANNEL: A_TXMAINCURSOR bit 1	GTX_CHANNEL: DRP[95] bit 8 GTX_CHANNEL: CPLL_LOCK_CFG bit 8	GTX_CHANNEL: DRP[95] bit 9 GTX_CHANNEL: CPLL_LOCK_CFG bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[7] bit 6 GTX_CHANNEL: A_TXPOSTCURSORINV bit 0	GTX_CHANNEL: DRP[7] bit 7 GTX_CHANNEL: A_TXPRECURSORINV bit 0	GTX_CHANNEL: DRP[95] bit 6 GTX_CHANNEL: CPLL_LOCK_CFG bit 6	GTX_CHANNEL: DRP[95] bit 7 GTX_CHANNEL: CPLL_LOCK_CFG bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[7] bit 4 GTX_CHANNEL: A_TXDIFFCTRL bit 3	GTX_CHANNEL: DRP[7] bit 5 GTX_CHANNEL: A_TXELECIDLE bit 0	GTX_CHANNEL: DRP[95] bit 4 GTX_CHANNEL: CPLL_LOCK_CFG bit 4	GTX_CHANNEL: DRP[95] bit 5 GTX_CHANNEL: CPLL_LOCK_CFG bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[7] bit 2 GTX_CHANNEL: A_TXDIFFCTRL bit 1	GTX_CHANNEL: DRP[7] bit 3 GTX_CHANNEL: A_TXDIFFCTRL bit 2	GTX_CHANNEL: DRP[95] bit 2 GTX_CHANNEL: CPLL_LOCK_CFG bit 2	GTX_CHANNEL: DRP[95] bit 3 GTX_CHANNEL: CPLL_LOCK_CFG bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[7] bit 0 GTX_CHANNEL: A_TXDEEMPH bit 0	GTX_CHANNEL: DRP[7] bit 1 GTX_CHANNEL: A_TXDIFFCTRL bit 0	GTX_CHANNEL: DRP[95] bit 0 GTX_CHANNEL: CPLL_LOCK_CFG bit 0	GTX_CHANNEL: DRP[95] bit 1 GTX_CHANNEL: CPLL_LOCK_CFG bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[6] bit 14 GTX_CHANNEL: A_TXPHALIGNEN bit 0	GTX_CHANNEL: DRP[6] bit 15 GTX_CHANNEL: A_TXPHALIGN bit 0	GTX_CHANNEL: DRP[94] bit 14 GTX_CHANNEL: SATA_CPLL_CFG bit 0	GTX_CHANNEL: DRP[94] bit 15 GTX_CHANNEL: SATA_CPLL_CFG bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[6] bit 12 GTX_CHANNEL: A_TXDLYSRESET bit 0	GTX_CHANNEL: DRP[6] bit 13 GTX_CHANNEL: A_TXDLYEN bit 0	GTX_CHANNEL: DRP[94] bit 12 GTX_CHANNEL: CPLL_REFCLK_DIV bit 4	GTX_CHANNEL: DRP[94] bit 13 GTX_CHANNEL: CPLLREFCLKSEL_MODE_DYNAMIC
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[6] bit 10 GTX_CHANNEL: A_TXPHOVRDEN bit 0	GTX_CHANNEL: DRP[6] bit 11 GTX_CHANNEL: A_TXPHDLYPD bit 0	GTX_CHANNEL: DRP[94] bit 10 GTX_CHANNEL: CPLL_REFCLK_DIV bit 2	GTX_CHANNEL: DRP[94] bit 11 GTX_CHANNEL: CPLL_REFCLK_DIV bit 3
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[6] bit 8 GTX_CHANNEL: A_TXPHDLYRESET bit 0	GTX_CHANNEL: DRP[6] bit 9 GTX_CHANNEL: A_TXPHINIT bit 0	GTX_CHANNEL: DRP[94] bit 8 GTX_CHANNEL: CPLL_REFCLK_DIV bit 0	GTX_CHANNEL: DRP[94] bit 9 GTX_CHANNEL: CPLL_REFCLK_DIV bit 1
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[6] bit 6 GTX_CHANNEL: A_TXDLYBYPASS bit 0	GTX_CHANNEL: DRP[6] bit 7 GTX_CHANNEL: A_TXDLYOVRDEN bit 0	GTX_CHANNEL: DRP[94] bit 6	GTX_CHANNEL: DRP[94] bit 7 GTX_CHANNEL: CPLL_FBDIV_45 bit 0
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[6] bit 4 GTX_CHANNEL: A_RXSYSCLKSEL bit 0	GTX_CHANNEL: DRP[6] bit 5 GTX_CHANNEL: A_RXSYSCLKSEL bit 1	GTX_CHANNEL: DRP[94] bit 4 GTX_CHANNEL: CPLL_FBDIV bit 4	GTX_CHANNEL: DRP[94] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[6] bit 2 GTX_CHANNEL: A_RXPRBSSEL bit 2	GTX_CHANNEL: DRP[6] bit 3 GTX_CHANNEL: A_RXPCSRESET bit 0	GTX_CHANNEL: DRP[94] bit 2 GTX_CHANNEL: CPLL_FBDIV bit 2	GTX_CHANNEL: DRP[94] bit 3 GTX_CHANNEL: CPLL_FBDIV bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[6] bit 0 GTX_CHANNEL: A_RXPRBSSEL bit 0	GTX_CHANNEL: DRP[6] bit 1 GTX_CHANNEL: A_RXPRBSSEL bit 1	GTX_CHANNEL: DRP[94] bit 0 GTX_CHANNEL: CPLL_FBDIV bit 0	GTX_CHANNEL: DRP[94] bit 1 GTX_CHANNEL: CPLL_FBDIV bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[5] bit 14 GTX_CHANNEL: A_RXPD bit 0	GTX_CHANNEL: DRP[5] bit 15 GTX_CHANNEL: A_RXPD bit 1	GTX_CHANNEL: DRP[93] bit 14 GTX_CHANNEL: RXPI_CFG2 bit 1	GTX_CHANNEL: DRP[93] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[5] bit 12 GTX_CHANNEL: A_RXPMARESET bit 0	GTX_CHANNEL: DRP[5] bit 13 GTX_CHANNEL: A_RXPOLARITY bit 0	GTX_CHANNEL: DRP[93] bit 12 GTX_CHANNEL: RXPI_CFG1 bit 1	GTX_CHANNEL: DRP[93] bit 13 GTX_CHANNEL: RXPI_CFG2 bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[5] bit 10 GTX_CHANNEL: A_RXOUTCLKSEL bit 1	GTX_CHANNEL: DRP[5] bit 11 GTX_CHANNEL: A_RXOUTCLKSEL bit 2	GTX_CHANNEL: DRP[93] bit 10 GTX_CHANNEL: TXPI_CFG5 bit 2	GTX_CHANNEL: DRP[93] bit 11 GTX_CHANNEL: RXPI_CFG1 bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[5] bit 8 GTX_CHANNEL: A_RXOOBRESET bit 0	GTX_CHANNEL: DRP[5] bit 9 GTX_CHANNEL: A_RXOUTCLKSEL bit 0	GTX_CHANNEL: DRP[93] bit 8 GTX_CHANNEL: TXPI_CFG5 bit 0	GTX_CHANNEL: DRP[93] bit 9 GTX_CHANNEL: TXPI_CFG5 bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[5] bit 6 GTX_CHANNEL: A_RXLPMEN bit 0	GTX_CHANNEL: DRP[5] bit 7 GTX_CHANNEL: A_GTRESETSEL bit 0	GTX_CHANNEL: DRP[93] bit 6 GTX_CHANNEL: TXPI_CFG3 bit 0	GTX_CHANNEL: DRP[93] bit 7 GTX_CHANNEL: TXPI_CFG4 bit 0
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[5] bit 4 GTX_CHANNEL: A_RXPHALIGNEN bit 0	GTX_CHANNEL: DRP[5] bit 5 GTX_CHANNEL: A_RXPHALIGN bit 0	GTX_CHANNEL: DRP[93] bit 4 GTX_CHANNEL: TXPI_CFG2 bit 0	GTX_CHANNEL: DRP[93] bit 5 GTX_CHANNEL: TXPI_CFG2 bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[5] bit 2 GTX_CHANNEL: A_RXDLYSRESET bit 0	GTX_CHANNEL: DRP[5] bit 3 GTX_CHANNEL: A_RXBUFRESET bit 0	GTX_CHANNEL: DRP[93] bit 2 GTX_CHANNEL: TXPI_CFG1 bit 0	GTX_CHANNEL: DRP[93] bit 3 GTX_CHANNEL: TXPI_CFG1 bit 1
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[5] bit 0 GTX_CHANNEL: A_RXPHOVRDEN bit 0	GTX_CHANNEL: DRP[5] bit 1 GTX_CHANNEL: A_RXPHDLYPD bit 0	GTX_CHANNEL: DRP[93] bit 0 GTX_CHANNEL: TXPI_CFG0 bit 0	GTX_CHANNEL: DRP[93] bit 1 GTX_CHANNEL: TXPI_CFG0 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[4] bit 14 GTX_CHANNEL: A_RXPHDLYRESET bit 0	GTX_CHANNEL: DRP[4] bit 15 GTX_CHANNEL: A_RXDLYEN bit 0	GTX_CHANNEL: DRP[92] bit 14 GTX_CHANNEL: RXPI_CFG3 bit 0	GTX_CHANNEL: DRP[92] bit 15 GTX_CHANNEL: RXPI_CFG3 bit 1
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[4] bit 12 GTX_CHANNEL: A_RXDLYBYPASS bit 0	GTX_CHANNEL: DRP[4] bit 13 GTX_CHANNEL: A_RXDLYOVRDEN bit 0	GTX_CHANNEL: DRP[92] bit 12 GTX_CHANNEL: RXPI_CFG0 bit 0	GTX_CHANNEL: DRP[92] bit 13 GTX_CHANNEL: RXPI_CFG0 bit 1
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[4] bit 10 GTX_CHANNEL: A_RXLPMLFKLOVRDEN bit 0	GTX_CHANNEL: DRP[4] bit 11 GTX_CHANNEL: A_RXPRBSCNTRESET bit 0	GTX_CHANNEL: DRP[92] bit 10	GTX_CHANNEL: DRP[92] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[4] bit 8 GTX_CHANNEL: A_RXLPMHFOVRDEN bit 0	GTX_CHANNEL: DRP[4] bit 9 GTX_CHANNEL: A_RXLPMLFHOLD bit 0	GTX_CHANNEL: DRP[92] bit 8	GTX_CHANNEL: DRP[92] bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[4] bit 6 GTX_CHANNEL: A_LOOPBACK bit 2	GTX_CHANNEL: DRP[4] bit 7 GTX_CHANNEL: A_RXLPMHFHOLD bit 0	GTX_CHANNEL: DRP[92] bit 6 GTX_CHANNEL: CPLL_INIT_CFG bit 22	GTX_CHANNEL: DRP[92] bit 7 GTX_CHANNEL: CPLL_INIT_CFG bit 23
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[4] bit 4 GTX_CHANNEL: A_LOOPBACK bit 0	GTX_CHANNEL: DRP[4] bit 5 GTX_CHANNEL: A_LOOPBACK bit 1	GTX_CHANNEL: DRP[92] bit 4 GTX_CHANNEL: CPLL_INIT_CFG bit 20	GTX_CHANNEL: DRP[92] bit 5 GTX_CHANNEL: CPLL_INIT_CFG bit 21
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[4] bit 2 GTX_CHANNEL: A_EYESCANRESET bit 0	GTX_CHANNEL: DRP[4] bit 3 GTX_CHANNEL: A_EYESCANMODE bit 0	GTX_CHANNEL: DRP[92] bit 2 GTX_CHANNEL: CPLL_INIT_CFG bit 18	GTX_CHANNEL: DRP[92] bit 3 GTX_CHANNEL: CPLL_INIT_CFG bit 19
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[4] bit 0 GTX_CHANNEL: A_GTRXRESET bit 0	GTX_CHANNEL: DRP[4] bit 1 GTX_CHANNEL: A_GTTXRESET bit 0	GTX_CHANNEL: DRP[92] bit 0 GTX_CHANNEL: CPLL_INIT_CFG bit 16	GTX_CHANNEL: DRP[92] bit 1 GTX_CHANNEL: CPLL_INIT_CFG bit 17
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[3] bit 14 GTX_CHANNEL: A_RXDFEXYDEN bit 0	GTX_CHANNEL: DRP[3] bit 15 GTX_CHANNEL: A_RXDFECM1EN bit 0	GTX_CHANNEL: DRP[91] bit 14 GTX_CHANNEL: CPLL_INIT_CFG bit 14	GTX_CHANNEL: DRP[91] bit 15 GTX_CHANNEL: CPLL_INIT_CFG bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[3] bit 12 GTX_CHANNEL: A_RXDFESLIDETAPOVRDEN bit 0	GTX_CHANNEL: DRP[3] bit 13 GTX_CHANNEL: A_RXDFESLIDETAPSTROBE bit 0	GTX_CHANNEL: DRP[91] bit 12 GTX_CHANNEL: CPLL_INIT_CFG bit 12	GTX_CHANNEL: DRP[91] bit 13 GTX_CHANNEL: CPLL_INIT_CFG bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[3] bit 10 GTX_CHANNEL: A_RXDFEVPHOLD bit 0	GTX_CHANNEL: DRP[3] bit 11 GTX_CHANNEL: A_RXDFEVPOVRDEN bit 0	GTX_CHANNEL: DRP[91] bit 10 GTX_CHANNEL: CPLL_INIT_CFG bit 10	GTX_CHANNEL: DRP[91] bit 11 GTX_CHANNEL: CPLL_INIT_CFG bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[3] bit 8 GTX_CHANNEL: A_RXDFEUTHOLD bit 0	GTX_CHANNEL: DRP[3] bit 9 GTX_CHANNEL: A_RXDFEUTOVRDEN bit 0	GTX_CHANNEL: DRP[91] bit 8 GTX_CHANNEL: CPLL_INIT_CFG bit 8	GTX_CHANNEL: DRP[91] bit 9 GTX_CHANNEL: CPLL_INIT_CFG bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[3] bit 6 GTX_CHANNEL: A_RXOSOVRDEN bit 0	GTX_CHANNEL: DRP[3] bit 7 GTX_CHANNEL: A_RXDFELPMRESET bit 0	GTX_CHANNEL: DRP[91] bit 6 GTX_CHANNEL: CPLL_INIT_CFG bit 6	GTX_CHANNEL: DRP[91] bit 7 GTX_CHANNEL: CPLL_INIT_CFG bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[3] bit 4 GTX_CHANNEL: A_RXDFELFOVRDEN bit 0	GTX_CHANNEL: DRP[3] bit 5 GTX_CHANNEL: A_RXOSHOLD bit 0	GTX_CHANNEL: DRP[91] bit 4 GTX_CHANNEL: CPLL_INIT_CFG bit 4	GTX_CHANNEL: DRP[91] bit 5 GTX_CHANNEL: CPLL_INIT_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[3] bit 2 GTX_CHANNEL: A_RXDFETAP5OVRDEN bit 0	GTX_CHANNEL: DRP[3] bit 3 GTX_CHANNEL: A_RXDFELFHOLD bit 0	GTX_CHANNEL: DRP[91] bit 2 GTX_CHANNEL: CPLL_INIT_CFG bit 2	GTX_CHANNEL: DRP[91] bit 3 GTX_CHANNEL: CPLL_INIT_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[3] bit 0 GTX_CHANNEL: A_RXDFETAP4OVRDEN bit 0	GTX_CHANNEL: DRP[3] bit 1 GTX_CHANNEL: A_RXDFETAP5HOLD bit 0	GTX_CHANNEL: DRP[91] bit 0 GTX_CHANNEL: CPLL_INIT_CFG bit 0	GTX_CHANNEL: DRP[91] bit 1 GTX_CHANNEL: CPLL_INIT_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[2] bit 14 GTX_CHANNEL: A_RXDFETAP3OVRDEN bit 0	GTX_CHANNEL: DRP[2] bit 15 GTX_CHANNEL: A_RXDFETAP4HOLD bit 0	GTX_CHANNEL: invert CLKRSVD[0] GTX_CHANNEL: DRP[90] bit 14	GTX_CHANNEL: invert CLKRSVD[1] GTX_CHANNEL: DRP[90] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[2] bit 12 GTX_CHANNEL: A_RXDFETAP2OVRDEN bit 0	GTX_CHANNEL: DRP[2] bit 13 GTX_CHANNEL: A_RXDFETAP3HOLD bit 0	GTX_CHANNEL: DRP[90] bit 12	GTX_CHANNEL: DRP[90] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[2] bit 10 GTX_CHANNEL: A_RXDFEAGCOVRDEN bit 0	GTX_CHANNEL: DRP[2] bit 11 GTX_CHANNEL: A_RXDFETAP2HOLD bit 0	GTX_CHANNEL: DRP[90] bit 10	GTX_CHANNEL: DRP[90] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[2] bit 8 GTX_CHANNEL: A_CPLLRESET bit 0	GTX_CHANNEL: DRP[2] bit 9 GTX_CHANNEL: A_RXDFEAGCHOLD bit 0	GTX_CHANNEL: DRP[90] bit 8 GTX_CHANNEL: LOOPBACK_CFG bit 0	GTX_CHANNEL: DRP[90] bit 9 GTX_CHANNEL: TXOOB_CFG bit 0
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[2] bit 6 GTX_CHANNEL: A_CPLLLOCKEN bit 0	GTX_CHANNEL: DRP[2] bit 7 GTX_CHANNEL: A_CPLLPD bit 0	GTX_CHANNEL: DRP[90] bit 6	GTX_CHANNEL: DRP[90] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[2] bit 4 GTX_CHANNEL: A_RXCDRRESETRSV bit 0	GTX_CHANNEL: DRP[2] bit 5 GTX_CHANNEL: A_CFGRESET bit 0	GTX_CHANNEL: DRP[90] bit 4	GTX_CHANNEL: DRP[90] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[2] bit 2 GTX_CHANNEL: A_RXCDRHOLD bit 0	GTX_CHANNEL: DRP[2] bit 3 GTX_CHANNEL: A_RXCDRRESET bit 0	GTX_CHANNEL: DRP[90] bit 2	GTX_CHANNEL: DRP[90] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[2] bit 0 GTX_CHANNEL: A_TXINHIBIT bit 0	GTX_CHANNEL: DRP[2] bit 1 GTX_CHANNEL: A_RXCDRFREQRESET bit 0	GTX_CHANNEL: DRP[90] bit 0	GTX_CHANNEL: DRP[90] bit 1 GTX_CHANNEL: CPLL_PCD_2UI_CFG bit 0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[1] bit 14	GTX_CHANNEL: DRP[1] bit 15	GTX_CHANNEL: DRP[89] bit 14 GTX_CHANNEL: SP_REFCLK_CFG bit 1	GTX_CHANNEL: DRP[89] bit 15 GTX_CHANNEL: SP_REFCLK_CFG bit 2
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[1] bit 12	GTX_CHANNEL: DRP[1] bit 13	GTX_CHANNEL: DRP[89] bit 12	GTX_CHANNEL: DRP[89] bit 13 GTX_CHANNEL: SP_REFCLK_CFG bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[1] bit 10	GTX_CHANNEL: DRP[1] bit 11	GTX_CHANNEL: invert DMONITORCLK GTX_CHANNEL: DRP[89] bit 10	GTX_CHANNEL: invert SIGVALIDCLK GTX_CHANNEL: DRP[89] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[1] bit 8	GTX_CHANNEL: DRP[1] bit 9	GTX_CHANNEL: DRP[89] bit 8 GTX_CHANNEL: TXOUTCLKPCS_SEL bit 0	GTX_CHANNEL: DRP[89] bit 9 GTX_CHANNEL: TXPLL_SEL bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[1] bit 6	GTX_CHANNEL: DRP[1] bit 7	GTX_CHANNEL: DRP[89] bit 6 GTX_CHANNEL: RX_XCLK_SEL bit 0	GTX_CHANNEL: DRP[89] bit 7 GTX_CHANNEL: TX_XCLK_SEL bit 0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[1] bit 4	GTX_CHANNEL: DRP[1] bit 5	GTX_CHANNEL: DRP[89] bit 4 GTX_CHANNEL: CPLLREFCLKSEL_STATIC_VAL bit 1	GTX_CHANNEL: DRP[89] bit 5 GTX_CHANNEL: CPLLREFCLKSEL_STATIC_VAL bit 2
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[1] bit 2	GTX_CHANNEL: DRP[1] bit 3	GTX_CHANNEL: DRP[89] bit 2	GTX_CHANNEL: DRP[89] bit 3 GTX_CHANNEL: CPLLREFCLKSEL_STATIC_VAL bit 0
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[1] bit 0	GTX_CHANNEL: DRP[1] bit 1	GTX_CHANNEL: invert TXUSRCLK2 GTX_CHANNEL: DRP[89] bit 0	GTX_CHANNEL: DRP[89] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[0] bit 14 GTX_CHANNEL: ACJTAG_DEBUG_MODE bit 0	GTX_CHANNEL: DRP[0] bit 15 GTX_CHANNEL: ACJTAG_RESET bit 0	GTX_CHANNEL: invert TSTCLK[1] GTX_CHANNEL: DRP[88] bit 14	GTX_CHANNEL: invert TXUSRCLK GTX_CHANNEL: DRP[88] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[0] bit 12	GTX_CHANNEL: DRP[0] bit 13 GTX_CHANNEL: ACJTAG_MODE bit 0	GTX_CHANNEL: invert TXPHDLYTSTCLK GTX_CHANNEL: DRP[88] bit 12	GTX_CHANNEL: invert TSTCLK[0] GTX_CHANNEL: DRP[88] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[0] bit 10	GTX_CHANNEL: DRP[0] bit 11	GTX_CHANNEL: invert RXUSRCLK2 GTX_CHANNEL: DRP[88] bit 10	GTX_CHANNEL: invert SCANCLK GTX_CHANNEL: DRP[88] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[0] bit 8	GTX_CHANNEL: DRP[0] bit 9	GTX_CHANNEL: invert PMASCANCLK[4] GTX_CHANNEL: DRP[88] bit 8	GTX_CHANNEL: invert RXUSRCLK GTX_CHANNEL: DRP[88] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[0] bit 6	GTX_CHANNEL: DRP[0] bit 7	GTX_CHANNEL: invert PMASCANCLK[2] GTX_CHANNEL: DRP[88] bit 6	GTX_CHANNEL: invert PMASCANCLK[3] GTX_CHANNEL: DRP[88] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[0] bit 4	GTX_CHANNEL: DRP[0] bit 5	GTX_CHANNEL: invert PMASCANCLK[0] GTX_CHANNEL: DRP[88] bit 4	GTX_CHANNEL: invert PMASCANCLK[1] GTX_CHANNEL: DRP[88] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[0] bit 2 GTX_CHANNEL: GEN_RXUSRCLK	GTX_CHANNEL: DRP[0] bit 3 GTX_CHANNEL: GEN_TXUSRCLK	GTX_CHANNEL: DRP[88] bit 2	GTX_CHANNEL: invert DRPCLK GTX_CHANNEL: DRP[88] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[0] bit 0 GTX_CHANNEL: GT_INSTANTIATED bit 0	GTX_CHANNEL: DRP[0] bit 1 GTX_CHANNEL: UCODEER_CLR bit 0	GTX_CHANNEL: invert GTGREFCLK GTX_CHANNEL: DRP[88] bit 0	GTX_CHANNEL: invert CPLLLOCKDETCLK GTX_CHANNEL: DRP[88] bit 1

virtex7 GTH_CHANNEL rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[15] bit 14 GTX_CHANNEL: RXISCANRESET_TIME bit 4	GTX_CHANNEL: DRP[15] bit 15	GTX_CHANNEL: DRP[103] bit 14	GTX_CHANNEL: DRP[103] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[15] bit 12 GTX_CHANNEL: RXISCANRESET_TIME bit 2	GTX_CHANNEL: DRP[15] bit 13 GTX_CHANNEL: RXISCANRESET_TIME bit 3	GTX_CHANNEL: DRP[103] bit 12	GTX_CHANNEL: DRP[103] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[15] bit 10 GTX_CHANNEL: RXISCANRESET_TIME bit 0	GTX_CHANNEL: DRP[15] bit 11 GTX_CHANNEL: RXISCANRESET_TIME bit 1	GTX_CHANNEL: DRP[103] bit 10	GTX_CHANNEL: DRP[103] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[15] bit 8 GTX_CHANNEL: TXPCSRESET_TIME bit 3	GTX_CHANNEL: DRP[15] bit 9 GTX_CHANNEL: TXPCSRESET_TIME bit 4	GTX_CHANNEL: DRP[103] bit 8	GTX_CHANNEL: DRP[103] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[15] bit 6 GTX_CHANNEL: TXPCSRESET_TIME bit 1	GTX_CHANNEL: DRP[15] bit 7 GTX_CHANNEL: TXPCSRESET_TIME bit 2	GTX_CHANNEL: DRP[103] bit 6 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 22	GTX_CHANNEL: DRP[103] bit 7 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 23
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[15] bit 4 GTX_CHANNEL: TXPMARESET_TIME bit 4	GTX_CHANNEL: DRP[15] bit 5 GTX_CHANNEL: TXPCSRESET_TIME bit 0	GTX_CHANNEL: DRP[103] bit 4 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 20	GTX_CHANNEL: DRP[103] bit 5 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 21
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[15] bit 2 GTX_CHANNEL: TXPMARESET_TIME bit 2	GTX_CHANNEL: DRP[15] bit 3 GTX_CHANNEL: TXPMARESET_TIME bit 3	GTX_CHANNEL: DRP[103] bit 2 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 18	GTX_CHANNEL: DRP[103] bit 3 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 19
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[15] bit 0 GTX_CHANNEL: TXPMARESET_TIME bit 0	GTX_CHANNEL: DRP[15] bit 1 GTX_CHANNEL: TXPMARESET_TIME bit 1	GTX_CHANNEL: DRP[103] bit 0 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 16	GTX_CHANNEL: DRP[103] bit 1 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 17
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[14] bit 14 GTX_CHANNEL: RXPCSRESET_TIME bit 3	GTX_CHANNEL: DRP[14] bit 15 GTX_CHANNEL: RXPCSRESET_TIME bit 4	GTX_CHANNEL: DRP[102] bit 14 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 14	GTX_CHANNEL: DRP[102] bit 15 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[14] bit 12 GTX_CHANNEL: RXPCSRESET_TIME bit 1	GTX_CHANNEL: DRP[14] bit 13 GTX_CHANNEL: RXPCSRESET_TIME bit 2	GTX_CHANNEL: DRP[102] bit 12 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 12	GTX_CHANNEL: DRP[102] bit 13 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[14] bit 10 GTX_CHANNEL: RXPMARESET_TIME bit 4	GTX_CHANNEL: DRP[14] bit 11 GTX_CHANNEL: RXPCSRESET_TIME bit 0	GTX_CHANNEL: DRP[102] bit 10 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 10	GTX_CHANNEL: DRP[102] bit 11 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[14] bit 8 GTX_CHANNEL: RXPMARESET_TIME bit 2	GTX_CHANNEL: DRP[14] bit 9 GTX_CHANNEL: RXPMARESET_TIME bit 3	GTX_CHANNEL: DRP[102] bit 8 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 8	GTX_CHANNEL: DRP[102] bit 9 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[14] bit 6 GTX_CHANNEL: RXPMARESET_TIME bit 0	GTX_CHANNEL: DRP[14] bit 7 GTX_CHANNEL: RXPMARESET_TIME bit 1	GTX_CHANNEL: DRP[102] bit 6 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 6	GTX_CHANNEL: DRP[102] bit 7 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[14] bit 4	GTX_CHANNEL: DRP[14] bit 5	GTX_CHANNEL: DRP[102] bit 4 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 4	GTX_CHANNEL: DRP[102] bit 5 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[14] bit 2	GTX_CHANNEL: DRP[14] bit 3	GTX_CHANNEL: DRP[102] bit 2 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 2	GTX_CHANNEL: DRP[102] bit 3 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[14] bit 0	GTX_CHANNEL: DRP[14] bit 1	GTX_CHANNEL: DRP[102] bit 0 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 0	GTX_CHANNEL: DRP[102] bit 1 GTX_CHANNEL: RX_BIAS_CFG_GTH bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[13] bit 14 GTX_CHANNEL: RXCDRPHRESET_TIME bit 4	GTX_CHANNEL: DRP[13] bit 15	GTX_CHANNEL: DRP[101] bit 14	GTX_CHANNEL: DRP[101] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[13] bit 12 GTX_CHANNEL: RXCDRPHRESET_TIME bit 2	GTX_CHANNEL: DRP[13] bit 13 GTX_CHANNEL: RXCDRPHRESET_TIME bit 3	GTX_CHANNEL: DRP[101] bit 12 GTX_CHANNEL: TXPH_MONITOR_SEL bit 4	GTX_CHANNEL: DRP[101] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[13] bit 10 GTX_CHANNEL: RXCDRPHRESET_TIME bit 0	GTX_CHANNEL: DRP[13] bit 11 GTX_CHANNEL: RXCDRPHRESET_TIME bit 1	GTX_CHANNEL: DRP[101] bit 10 GTX_CHANNEL: TXPH_MONITOR_SEL bit 2	GTX_CHANNEL: DRP[101] bit 11 GTX_CHANNEL: TXPH_MONITOR_SEL bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[13] bit 8 GTX_CHANNEL: RXCDRFREQRESET_TIME bit 3	GTX_CHANNEL: DRP[13] bit 9 GTX_CHANNEL: RXCDRFREQRESET_TIME bit 4	GTX_CHANNEL: DRP[101] bit 8 GTX_CHANNEL: TXPH_MONITOR_SEL bit 0	GTX_CHANNEL: DRP[101] bit 9 GTX_CHANNEL: TXPH_MONITOR_SEL bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[13] bit 6 GTX_CHANNEL: RXCDRFREQRESET_TIME bit 1	GTX_CHANNEL: DRP[13] bit 7 GTX_CHANNEL: RXCDRFREQRESET_TIME bit 2	GTX_CHANNEL: DRP[101] bit 6	GTX_CHANNEL: DRP[101] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[13] bit 4 GTX_CHANNEL: RXBUFRESET_TIME bit 4	GTX_CHANNEL: DRP[13] bit 5 GTX_CHANNEL: RXCDRFREQRESET_TIME bit 0	GTX_CHANNEL: DRP[101] bit 4	GTX_CHANNEL: DRP[101] bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[13] bit 2 GTX_CHANNEL: RXBUFRESET_TIME bit 2	GTX_CHANNEL: DRP[13] bit 3 GTX_CHANNEL: RXBUFRESET_TIME bit 3	GTX_CHANNEL: DRP[101] bit 2 GTX_CHANNEL: RXPI_CFG6 bit 2	GTX_CHANNEL: DRP[101] bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[13] bit 0 GTX_CHANNEL: RXBUFRESET_TIME bit 0	GTX_CHANNEL: DRP[13] bit 1 GTX_CHANNEL: RXBUFRESET_TIME bit 1	GTX_CHANNEL: DRP[101] bit 0 GTX_CHANNEL: RXPI_CFG6 bit 0	GTX_CHANNEL: DRP[101] bit 1 GTX_CHANNEL: RXPI_CFG6 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[12] bit 14 GTX_CHANNEL: RXDFELPMRESET_TIME bit 5	GTX_CHANNEL: DRP[12] bit 15 GTX_CHANNEL: RXDFELPMRESET_TIME bit 6	GTX_CHANNEL: DRP[100] bit 14 GTX_CHANNEL: TXPH_CFG bit 14	GTX_CHANNEL: DRP[100] bit 15 GTX_CHANNEL: TXPH_CFG bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[12] bit 12 GTX_CHANNEL: RXDFELPMRESET_TIME bit 3	GTX_CHANNEL: DRP[12] bit 13 GTX_CHANNEL: RXDFELPMRESET_TIME bit 4	GTX_CHANNEL: DRP[100] bit 12 GTX_CHANNEL: TXPH_CFG bit 12	GTX_CHANNEL: DRP[100] bit 13 GTX_CHANNEL: TXPH_CFG bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[12] bit 10 GTX_CHANNEL: RXDFELPMRESET_TIME bit 1	GTX_CHANNEL: DRP[12] bit 11 GTX_CHANNEL: RXDFELPMRESET_TIME bit 2	GTX_CHANNEL: DRP[100] bit 10 GTX_CHANNEL: TXPH_CFG bit 10	GTX_CHANNEL: DRP[100] bit 11 GTX_CHANNEL: TXPH_CFG bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[12] bit 8	GTX_CHANNEL: DRP[12] bit 9 GTX_CHANNEL: RXDFELPMRESET_TIME bit 0	GTX_CHANNEL: DRP[100] bit 8 GTX_CHANNEL: TXPH_CFG bit 8	GTX_CHANNEL: DRP[100] bit 9 GTX_CHANNEL: TXPH_CFG bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[12] bit 6	GTX_CHANNEL: DRP[12] bit 7	GTX_CHANNEL: DRP[100] bit 6 GTX_CHANNEL: TXPH_CFG bit 6	GTX_CHANNEL: DRP[100] bit 7 GTX_CHANNEL: TXPH_CFG bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[12] bit 4 GTX_CHANNEL: AEN_RXPHDLY bit 0	GTX_CHANNEL: DRP[12] bit 5	GTX_CHANNEL: DRP[100] bit 4 GTX_CHANNEL: TXPH_CFG bit 4	GTX_CHANNEL: DRP[100] bit 5 GTX_CHANNEL: TXPH_CFG bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[12] bit 2 GTX_CHANNEL: AEN_TXOUTCLK_SEL bit 0	GTX_CHANNEL: DRP[12] bit 3 GTX_CHANNEL: AEN_TXSYSCLK_SEL bit 0	GTX_CHANNEL: DRP[100] bit 2 GTX_CHANNEL: TXPH_CFG bit 2	GTX_CHANNEL: DRP[100] bit 3 GTX_CHANNEL: TXPH_CFG bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[12] bit 0 GTX_CHANNEL: AEN_TXPHDLY bit 0	GTX_CHANNEL: DRP[12] bit 1 GTX_CHANNEL: AEN_TX_DRIVE_MODE bit 0	GTX_CHANNEL: DRP[100] bit 0 GTX_CHANNEL: TXPH_CFG bit 0	GTX_CHANNEL: DRP[100] bit 1 GTX_CHANNEL: TXPH_CFG bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[11] bit 14 GTX_CHANNEL: AEN_RXOUTCLK_SEL bit 0	GTX_CHANNEL: DRP[11] bit 15 GTX_CHANNEL: AEN_RXSYSCLK_SEL bit 0	GTX_CHANNEL: DRP[99] bit 14 GTX_CHANNEL: TXDLY_TAP_CFG bit 14	GTX_CHANNEL: DRP[99] bit 15 GTX_CHANNEL: TXDLY_TAP_CFG bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[11] bit 12 GTX_CHANNEL: AEN_QPI bit 0	GTX_CHANNEL: DRP[11] bit 13 GTX_CHANNEL: AEN_RESET bit 0	GTX_CHANNEL: DRP[99] bit 12 GTX_CHANNEL: TXDLY_TAP_CFG bit 12	GTX_CHANNEL: DRP[99] bit 13 GTX_CHANNEL: TXDLY_TAP_CFG bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[11] bit 10 GTX_CHANNEL: AEN_POLARITY bit 0	GTX_CHANNEL: DRP[11] bit 11 GTX_CHANNEL: AEN_PRBS bit 0	GTX_CHANNEL: DRP[99] bit 10 GTX_CHANNEL: TXDLY_TAP_CFG bit 10	GTX_CHANNEL: DRP[99] bit 11 GTX_CHANNEL: TXDLY_TAP_CFG bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[11] bit 8 GTX_CHANNEL: AEN_PD_AND_EIDLE bit 0	GTX_CHANNEL: DRP[11] bit 9	GTX_CHANNEL: DRP[99] bit 8 GTX_CHANNEL: TXDLY_TAP_CFG bit 8	GTX_CHANNEL: DRP[99] bit 9 GTX_CHANNEL: TXDLY_TAP_CFG bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[11] bit 6 GTX_CHANNEL: AEN_MASTER bit 0	GTX_CHANNEL: DRP[11] bit 7	GTX_CHANNEL: DRP[99] bit 6 GTX_CHANNEL: TXDLY_TAP_CFG bit 6	GTX_CHANNEL: DRP[99] bit 7 GTX_CHANNEL: TXDLY_TAP_CFG bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[11] bit 4 GTX_CHANNEL: AEN_LOOPBACK bit 0	GTX_CHANNEL: DRP[11] bit 5 GTX_CHANNEL: AEN_RXDFELPM bit 0	GTX_CHANNEL: DRP[99] bit 4 GTX_CHANNEL: TXDLY_TAP_CFG bit 4	GTX_CHANNEL: DRP[99] bit 5 GTX_CHANNEL: TXDLY_TAP_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[11] bit 2 GTX_CHANNEL: AEN_CPLL bit 0	GTX_CHANNEL: DRP[11] bit 3 GTX_CHANNEL: AEN_RXDFE bit 0	GTX_CHANNEL: DRP[99] bit 2 GTX_CHANNEL: TXDLY_TAP_CFG bit 2	GTX_CHANNEL: DRP[99] bit 3 GTX_CHANNEL: TXDLY_TAP_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[11] bit 0	GTX_CHANNEL: DRP[11] bit 1 GTX_CHANNEL: AEN_RXCDR bit 0	GTX_CHANNEL: DRP[99] bit 0 GTX_CHANNEL: TXDLY_TAP_CFG bit 0	GTX_CHANNEL: DRP[99] bit 1 GTX_CHANNEL: TXDLY_TAP_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[10] bit 14 GTX_CHANNEL: A_RXOSINTCFG bit 2	GTX_CHANNEL: DRP[10] bit 15 GTX_CHANNEL: A_RXOSINTCFG bit 3	GTX_CHANNEL: DRP[98] bit 14 GTX_CHANNEL: TXDLY_CFG bit 14	GTX_CHANNEL: DRP[98] bit 15 GTX_CHANNEL: TXDLY_CFG bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[10] bit 12 GTX_CHANNEL: A_RXOSINTCFG bit 0	GTX_CHANNEL: DRP[10] bit 13 GTX_CHANNEL: A_RXOSINTCFG bit 1	GTX_CHANNEL: DRP[98] bit 12 GTX_CHANNEL: TXDLY_CFG bit 12	GTX_CHANNEL: DRP[98] bit 13 GTX_CHANNEL: TXDLY_CFG bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[10] bit 10 GTX_CHANNEL: A_RXDFESLIDETAPID bit 4	GTX_CHANNEL: DRP[10] bit 11 GTX_CHANNEL: A_RXDFESLIDETAPID bit 5	GTX_CHANNEL: DRP[98] bit 10 GTX_CHANNEL: TXDLY_CFG bit 10	GTX_CHANNEL: DRP[98] bit 11 GTX_CHANNEL: TXDLY_CFG bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[10] bit 8 GTX_CHANNEL: A_RXDFESLIDETAPID bit 2	GTX_CHANNEL: DRP[10] bit 9 GTX_CHANNEL: A_RXDFESLIDETAPID bit 3	GTX_CHANNEL: DRP[98] bit 8 GTX_CHANNEL: TXDLY_CFG bit 8	GTX_CHANNEL: DRP[98] bit 9 GTX_CHANNEL: TXDLY_CFG bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[10] bit 6 GTX_CHANNEL: A_RXDFESLIDETAPID bit 0	GTX_CHANNEL: DRP[10] bit 7 GTX_CHANNEL: A_RXDFESLIDETAPID bit 1	GTX_CHANNEL: DRP[98] bit 6 GTX_CHANNEL: TXDLY_CFG bit 6	GTX_CHANNEL: DRP[98] bit 7 GTX_CHANNEL: TXDLY_CFG bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[10] bit 4 GTX_CHANNEL: A_RXDFEVSEN bit 0	GTX_CHANNEL: DRP[10] bit 5 GTX_CHANNEL: A_RXOSCALRESET bit 0	GTX_CHANNEL: DRP[98] bit 4 GTX_CHANNEL: TXDLY_CFG bit 4	GTX_CHANNEL: DRP[98] bit 5 GTX_CHANNEL: TXDLY_CFG bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[10] bit 2 GTX_CHANNEL: A_RXMONITORSEL bit 1	GTX_CHANNEL: DRP[10] bit 3 GTX_CHANNEL: A_RXCDROVRDEN bit 0	GTX_CHANNEL: DRP[98] bit 2 GTX_CHANNEL: TXDLY_CFG bit 2	GTX_CHANNEL: DRP[98] bit 3 GTX_CHANNEL: TXDLY_CFG bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[10] bit 0	GTX_CHANNEL: DRP[10] bit 1 GTX_CHANNEL: A_RXMONITORSEL bit 0	GTX_CHANNEL: DRP[98] bit 0 GTX_CHANNEL: TXDLY_CFG bit 0	GTX_CHANNEL: DRP[98] bit 1 GTX_CHANNEL: TXDLY_CFG bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[9] bit 14 GTX_CHANNEL: A_TXSYSCLKSEL bit 1	GTX_CHANNEL: DRP[9] bit 15	GTX_CHANNEL: DRP[97] bit 14 GTX_CHANNEL: RXPI_CFG4 bit 0	GTX_CHANNEL: DRP[97] bit 15 GTX_CHANNEL: RXPI_CFG5 bit 0
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[9] bit 12 GTX_CHANNEL: A_TXSWING bit 0	GTX_CHANNEL: DRP[9] bit 13 GTX_CHANNEL: A_TXSYSCLKSEL bit 0	GTX_CHANNEL: DRP[97] bit 12	GTX_CHANNEL: DRP[97] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[9] bit 10 GTX_CHANNEL: A_TXPD bit 1	GTX_CHANNEL: DRP[9] bit 11 GTX_CHANNEL: A_TXPCSRESET bit 0	GTX_CHANNEL: DRP[97] bit 10	GTX_CHANNEL: DRP[97] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[9] bit 8 GTX_CHANNEL: A_TXBUFDIFFCTRL bit 2	GTX_CHANNEL: DRP[9] bit 9 GTX_CHANNEL: A_TXPD bit 0	GTX_CHANNEL: DRP[97] bit 8	GTX_CHANNEL: DRP[97] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[9] bit 6 GTX_CHANNEL: A_TXBUFDIFFCTRL bit 0	GTX_CHANNEL: DRP[9] bit 7 GTX_CHANNEL: A_TXBUFDIFFCTRL bit 1	GTX_CHANNEL: DRP[97] bit 6 GTX_CHANNEL: TXPHDLY_CFG bit 22	GTX_CHANNEL: DRP[97] bit 7 GTX_CHANNEL: TXPHDLY_CFG bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[9] bit 4 GTX_CHANNEL: A_TXPRBSSEL bit 1	GTX_CHANNEL: DRP[9] bit 5 GTX_CHANNEL: A_TXPRBSSEL bit 2	GTX_CHANNEL: DRP[97] bit 4 GTX_CHANNEL: TXPHDLY_CFG bit 20	GTX_CHANNEL: DRP[97] bit 5 GTX_CHANNEL: TXPHDLY_CFG bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[9] bit 2 GTX_CHANNEL: A_TXPRBSFORCEERR bit 0	GTX_CHANNEL: DRP[9] bit 3 GTX_CHANNEL: A_TXPRBSSEL bit 0	GTX_CHANNEL: DRP[97] bit 2 GTX_CHANNEL: TXPHDLY_CFG bit 18	GTX_CHANNEL: DRP[97] bit 3 GTX_CHANNEL: TXPHDLY_CFG bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[9] bit 0 GTX_CHANNEL: A_TXPMARESET bit 0	GTX_CHANNEL: DRP[9] bit 1 GTX_CHANNEL: A_TXPOLARITY bit 0	GTX_CHANNEL: DRP[97] bit 0 GTX_CHANNEL: TXPHDLY_CFG bit 16	GTX_CHANNEL: DRP[97] bit 1 GTX_CHANNEL: TXPHDLY_CFG bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[8] bit 14 GTX_CHANNEL: A_TXOUTCLKSEL bit 1	GTX_CHANNEL: DRP[8] bit 15 GTX_CHANNEL: A_TXOUTCLKSEL bit 2	GTX_CHANNEL: DRP[96] bit 14 GTX_CHANNEL: TXPHDLY_CFG bit 14	GTX_CHANNEL: DRP[96] bit 15 GTX_CHANNEL: TXPHDLY_CFG bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[8] bit 12 GTX_CHANNEL: A_TXMARGIN bit 2	GTX_CHANNEL: DRP[8] bit 13 GTX_CHANNEL: A_TXOUTCLKSEL bit 0	GTX_CHANNEL: DRP[96] bit 12 GTX_CHANNEL: TXPHDLY_CFG bit 12	GTX_CHANNEL: DRP[96] bit 13 GTX_CHANNEL: TXPHDLY_CFG bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[8] bit 10 GTX_CHANNEL: A_TXMARGIN bit 0	GTX_CHANNEL: DRP[8] bit 11 GTX_CHANNEL: A_TXMARGIN bit 1	GTX_CHANNEL: DRP[96] bit 10 GTX_CHANNEL: TXPHDLY_CFG bit 10	GTX_CHANNEL: DRP[96] bit 11 GTX_CHANNEL: TXPHDLY_CFG bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[8] bit 8 GTX_CHANNEL: A_TXPRECURSOR bit 3	GTX_CHANNEL: DRP[8] bit 9 GTX_CHANNEL: A_TXPRECURSOR bit 4	GTX_CHANNEL: DRP[96] bit 8 GTX_CHANNEL: TXPHDLY_CFG bit 8	GTX_CHANNEL: DRP[96] bit 9 GTX_CHANNEL: TXPHDLY_CFG bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[8] bit 6 GTX_CHANNEL: A_TXPRECURSOR bit 1	GTX_CHANNEL: DRP[8] bit 7 GTX_CHANNEL: A_TXPRECURSOR bit 2	GTX_CHANNEL: DRP[96] bit 6 GTX_CHANNEL: TXPHDLY_CFG bit 6	GTX_CHANNEL: DRP[96] bit 7 GTX_CHANNEL: TXPHDLY_CFG bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[8] bit 4 GTX_CHANNEL: A_RXDFESLIDETAPHOLD bit 0	GTX_CHANNEL: DRP[8] bit 5 GTX_CHANNEL: A_TXPRECURSOR bit 0	GTX_CHANNEL: DRP[96] bit 4 GTX_CHANNEL: TXPHDLY_CFG bit 4	GTX_CHANNEL: DRP[96] bit 5 GTX_CHANNEL: TXPHDLY_CFG bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[8] bit 2 GTX_CHANNEL: A_RXDFESLIDETAPONLYADAPTEN bit 0	GTX_CHANNEL: DRP[8] bit 3 GTX_CHANNEL: A_RXDFESLIDETAPADAPTEN bit 0	GTX_CHANNEL: DRP[96] bit 2 GTX_CHANNEL: TXPHDLY_CFG bit 2	GTX_CHANNEL: DRP[96] bit 3 GTX_CHANNEL: TXPHDLY_CFG bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[8] bit 0	GTX_CHANNEL: DRP[8] bit 1	GTX_CHANNEL: DRP[96] bit 0 GTX_CHANNEL: TXPHDLY_CFG bit 0	GTX_CHANNEL: DRP[96] bit 1 GTX_CHANNEL: TXPHDLY_CFG bit 1

virtex7 GTH_CHANNEL rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[23] bit 14 GTX_CHANNEL: RXOSCALRESET_TIMEOUT bit 3	GTX_CHANNEL: DRP[23] bit 15 GTX_CHANNEL: RXOSCALRESET_TIMEOUT bit 4	GTX_CHANNEL: DRP[111] bit 14 GTX_CHANNEL: PCS_RSVD_ATTR bit 14	GTX_CHANNEL: DRP[111] bit 15 GTX_CHANNEL: PCS_RSVD_ATTR bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[23] bit 12 GTX_CHANNEL: RXOSCALRESET_TIMEOUT bit 1	GTX_CHANNEL: DRP[23] bit 13 GTX_CHANNEL: RXOSCALRESET_TIMEOUT bit 2	GTX_CHANNEL: DRP[111] bit 12 GTX_CHANNEL: PCS_RSVD_ATTR bit 12	GTX_CHANNEL: DRP[111] bit 13 GTX_CHANNEL: PCS_RSVD_ATTR bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[23] bit 10 GTX_CHANNEL: RXOSCALRESET_TIME bit 4	GTX_CHANNEL: DRP[23] bit 11 GTX_CHANNEL: RXOSCALRESET_TIMEOUT bit 0	GTX_CHANNEL: DRP[111] bit 10 GTX_CHANNEL: PCS_RSVD_ATTR bit 10	GTX_CHANNEL: DRP[111] bit 11 GTX_CHANNEL: PCS_RSVD_ATTR bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[23] bit 8 GTX_CHANNEL: RXOSCALRESET_TIME bit 2	GTX_CHANNEL: DRP[23] bit 9 GTX_CHANNEL: RXOSCALRESET_TIME bit 3	GTX_CHANNEL: DRP[111] bit 8 GTX_CHANNEL: PCS_RSVD_ATTR bit 8	GTX_CHANNEL: DRP[111] bit 9 GTX_CHANNEL: PCS_RSVD_ATTR bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[23] bit 6 GTX_CHANNEL: RXOSCALRESET_TIME bit 0	GTX_CHANNEL: DRP[23] bit 7 GTX_CHANNEL: RXOSCALRESET_TIME bit 1	GTX_CHANNEL: DRP[111] bit 6 GTX_CHANNEL: PCS_RSVD_ATTR bit 6	GTX_CHANNEL: DRP[111] bit 7 GTX_CHANNEL: PCS_RSVD_ATTR bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[23] bit 4	GTX_CHANNEL: DRP[23] bit 5	GTX_CHANNEL: DRP[111] bit 4 GTX_CHANNEL: PCS_RSVD_ATTR bit 4	GTX_CHANNEL: DRP[111] bit 5 GTX_CHANNEL: PCS_RSVD_ATTR bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[23] bit 2	GTX_CHANNEL: DRP[23] bit 3	GTX_CHANNEL: DRP[111] bit 2 GTX_CHANNEL: PCS_RSVD_ATTR bit 2	GTX_CHANNEL: DRP[111] bit 3 GTX_CHANNEL: PCS_RSVD_ATTR bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[23] bit 0	GTX_CHANNEL: DRP[23] bit 1	GTX_CHANNEL: DRP[111] bit 0 GTX_CHANNEL: PCS_RSVD_ATTR bit 0	GTX_CHANNEL: DRP[111] bit 1 GTX_CHANNEL: PCS_RSVD_ATTR bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[22] bit 14	GTX_CHANNEL: DRP[22] bit 15	GTX_CHANNEL: DRP[110] bit 14 GTX_CHANNEL: A_RXDFETAP7OVRDEN bit 0	GTX_CHANNEL: DRP[110] bit 15 GTX_CHANNEL: A_RXDFETAP7HOLD bit 0
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[22] bit 12	GTX_CHANNEL: DRP[22] bit 13	GTX_CHANNEL: DRP[110] bit 12 GTX_CHANNEL: A_RXOSINTID0 bit 2	GTX_CHANNEL: DRP[110] bit 13 GTX_CHANNEL: A_RXOSINTID0 bit 3
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[22] bit 10 GTX_CHANNEL: SATA_MAX_WAKE bit 4	GTX_CHANNEL: DRP[22] bit 11 GTX_CHANNEL: SATA_MAX_WAKE bit 5	GTX_CHANNEL: DRP[110] bit 10 GTX_CHANNEL: A_RXOSINTID0 bit 0	GTX_CHANNEL: DRP[110] bit 11 GTX_CHANNEL: A_RXOSINTID0 bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[22] bit 8 GTX_CHANNEL: SATA_MAX_WAKE bit 2	GTX_CHANNEL: DRP[22] bit 9 GTX_CHANNEL: SATA_MAX_WAKE bit 3	GTX_CHANNEL: DRP[110] bit 8 GTX_CHANNEL: A_RXDFEAGCTRL bit 3	GTX_CHANNEL: DRP[110] bit 9 GTX_CHANNEL: A_RXDFEAGCTRL bit 4
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[22] bit 6 GTX_CHANNEL: SATA_MAX_WAKE bit 0	GTX_CHANNEL: DRP[22] bit 7 GTX_CHANNEL: SATA_MAX_WAKE bit 1	GTX_CHANNEL: DRP[110] bit 6 GTX_CHANNEL: A_RXDFEAGCTRL bit 1	GTX_CHANNEL: DRP[110] bit 7 GTX_CHANNEL: A_RXDFEAGCTRL bit 2
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[22] bit 4 GTX_CHANNEL: SATA_MAX_INIT bit 4	GTX_CHANNEL: DRP[22] bit 5 GTX_CHANNEL: SATA_MAX_INIT bit 5	GTX_CHANNEL: DRP[110] bit 4 GTX_CHANNEL: A_RXDFESLIDETAP bit 4	GTX_CHANNEL: DRP[110] bit 5 GTX_CHANNEL: A_RXDFEAGCTRL bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[22] bit 2 GTX_CHANNEL: SATA_MAX_INIT bit 2	GTX_CHANNEL: DRP[22] bit 3 GTX_CHANNEL: SATA_MAX_INIT bit 3	GTX_CHANNEL: DRP[110] bit 2 GTX_CHANNEL: A_RXDFESLIDETAP bit 2	GTX_CHANNEL: DRP[110] bit 3 GTX_CHANNEL: A_RXDFESLIDETAP bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[22] bit 0 GTX_CHANNEL: SATA_MAX_INIT bit 0	GTX_CHANNEL: DRP[22] bit 1 GTX_CHANNEL: SATA_MAX_INIT bit 1	GTX_CHANNEL: DRP[110] bit 0 GTX_CHANNEL: A_RXDFESLIDETAP bit 0	GTX_CHANNEL: DRP[110] bit 1 GTX_CHANNEL: A_RXDFESLIDETAP bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[21] bit 14	GTX_CHANNEL: DRP[21] bit 15	GTX_CHANNEL: DRP[109] bit 14 GTX_CHANNEL: A_RXDFETAP6OVRDEN bit 0	GTX_CHANNEL: DRP[109] bit 15 GTX_CHANNEL: A_RXDFETAP6HOLD bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[21] bit 12 GTX_CHANNEL: SAS_MAX_COM bit 6	GTX_CHANNEL: DRP[21] bit 13	GTX_CHANNEL: DRP[109] bit 12 GTX_CHANNEL: A_RXADAPTSELTEST bit 12	GTX_CHANNEL: DRP[109] bit 13 GTX_CHANNEL: A_RXADAPTSELTEST bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[21] bit 10 GTX_CHANNEL: SAS_MAX_COM bit 4	GTX_CHANNEL: DRP[21] bit 11 GTX_CHANNEL: SAS_MAX_COM bit 5	GTX_CHANNEL: DRP[109] bit 10 GTX_CHANNEL: A_RXADAPTSELTEST bit 10	GTX_CHANNEL: DRP[109] bit 11 GTX_CHANNEL: A_RXADAPTSELTEST bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[21] bit 8 GTX_CHANNEL: SAS_MAX_COM bit 2	GTX_CHANNEL: DRP[21] bit 9 GTX_CHANNEL: SAS_MAX_COM bit 3	GTX_CHANNEL: DRP[109] bit 8 GTX_CHANNEL: A_RXADAPTSELTEST bit 8	GTX_CHANNEL: DRP[109] bit 9 GTX_CHANNEL: A_RXADAPTSELTEST bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[21] bit 6 GTX_CHANNEL: SAS_MAX_COM bit 0	GTX_CHANNEL: DRP[21] bit 7 GTX_CHANNEL: SAS_MAX_COM bit 1	GTX_CHANNEL: DRP[109] bit 6 GTX_CHANNEL: A_RXADAPTSELTEST bit 6	GTX_CHANNEL: DRP[109] bit 7 GTX_CHANNEL: A_RXADAPTSELTEST bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[21] bit 4 GTX_CHANNEL: SATA_MAX_BURST bit 4	GTX_CHANNEL: DRP[21] bit 5 GTX_CHANNEL: SATA_MAX_BURST bit 5	GTX_CHANNEL: DRP[109] bit 4 GTX_CHANNEL: A_RXADAPTSELTEST bit 4	GTX_CHANNEL: DRP[109] bit 5 GTX_CHANNEL: A_RXADAPTSELTEST bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[21] bit 2 GTX_CHANNEL: SATA_MAX_BURST bit 2	GTX_CHANNEL: DRP[21] bit 3 GTX_CHANNEL: SATA_MAX_BURST bit 3	GTX_CHANNEL: DRP[109] bit 2 GTX_CHANNEL: A_RXADAPTSELTEST bit 2	GTX_CHANNEL: DRP[109] bit 3 GTX_CHANNEL: A_RXADAPTSELTEST bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[21] bit 0 GTX_CHANNEL: SATA_MAX_BURST bit 0	GTX_CHANNEL: DRP[21] bit 1 GTX_CHANNEL: SATA_MAX_BURST bit 1	GTX_CHANNEL: DRP[109] bit 0 GTX_CHANNEL: A_RXADAPTSELTEST bit 0	GTX_CHANNEL: DRP[109] bit 1 GTX_CHANNEL: A_RXADAPTSELTEST bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[20] bit 14	GTX_CHANNEL: DRP[20] bit 15	GTX_CHANNEL: DRP[108] bit 14	GTX_CHANNEL: DRP[108] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[20] bit 12	GTX_CHANNEL: DRP[20] bit 13	GTX_CHANNEL: DRP[108] bit 12	GTX_CHANNEL: DRP[108] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[20] bit 10 GTX_CHANNEL: SATA_MIN_WAKE bit 4	GTX_CHANNEL: DRP[20] bit 11 GTX_CHANNEL: SATA_MIN_WAKE bit 5	GTX_CHANNEL: DRP[108] bit 10	GTX_CHANNEL: DRP[108] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[20] bit 8 GTX_CHANNEL: SATA_MIN_WAKE bit 2	GTX_CHANNEL: DRP[20] bit 9 GTX_CHANNEL: SATA_MIN_WAKE bit 3	GTX_CHANNEL: DRP[108] bit 8	GTX_CHANNEL: DRP[108] bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[20] bit 6 GTX_CHANNEL: SATA_MIN_WAKE bit 0	GTX_CHANNEL: DRP[20] bit 7 GTX_CHANNEL: SATA_MIN_WAKE bit 1	GTX_CHANNEL: DRP[108] bit 6 GTX_CHANNEL: A_RXDFESLIDETAPINITOVRDEN bit 0	GTX_CHANNEL: DRP[108] bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[20] bit 4 GTX_CHANNEL: SATA_MIN_INIT bit 4	GTX_CHANNEL: DRP[20] bit 5 GTX_CHANNEL: SATA_MIN_INIT bit 5	GTX_CHANNEL: DRP[108] bit 4 GTX_CHANNEL: A_RXOSINTNTRLEN bit 0	GTX_CHANNEL: DRP[108] bit 5 GTX_CHANNEL: A_RXOSINTEN bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[20] bit 2 GTX_CHANNEL: SATA_MIN_INIT bit 2	GTX_CHANNEL: DRP[20] bit 3 GTX_CHANNEL: SATA_MIN_INIT bit 3	GTX_CHANNEL: DRP[108] bit 2 GTX_CHANNEL: A_RXOSINTSTROBE bit 0	GTX_CHANNEL: DRP[108] bit 3 GTX_CHANNEL: A_RXOSINTOVRDEN bit 0
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[20] bit 0 GTX_CHANNEL: SATA_MIN_INIT bit 0	GTX_CHANNEL: DRP[20] bit 1 GTX_CHANNEL: SATA_MIN_INIT bit 1	GTX_CHANNEL: DRP[108] bit 0 GTX_CHANNEL: A_RXOSINTTESTOVRDEN bit 0	GTX_CHANNEL: DRP[108] bit 1 GTX_CHANNEL: A_RXOSINTHOLD bit 0
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[19] bit 14 GTX_CHANNEL: SAS_MIN_COM bit 5	GTX_CHANNEL: DRP[19] bit 15	GTX_CHANNEL: DRP[107] bit 14	GTX_CHANNEL: DRP[107] bit 15 GTX_CHANNEL: TX_QPI_STATUS_EN bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[19] bit 12 GTX_CHANNEL: SAS_MIN_COM bit 3	GTX_CHANNEL: DRP[19] bit 13 GTX_CHANNEL: SAS_MIN_COM bit 4	GTX_CHANNEL: DRP[107] bit 12	GTX_CHANNEL: DRP[107] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[19] bit 10 GTX_CHANNEL: SAS_MIN_COM bit 1	GTX_CHANNEL: DRP[19] bit 11 GTX_CHANNEL: SAS_MIN_COM bit 2	GTX_CHANNEL: DRP[107] bit 10 GTX_CHANNEL: PMA_RSV5 bit 2	GTX_CHANNEL: DRP[107] bit 11 GTX_CHANNEL: PMA_RSV5 bit 3
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[19] bit 8 GTX_CHANNEL: SATA_MIN_BURST bit 5	GTX_CHANNEL: DRP[19] bit 9 GTX_CHANNEL: SAS_MIN_COM bit 0	GTX_CHANNEL: DRP[107] bit 8 GTX_CHANNEL: PMA_RSV5 bit 0	GTX_CHANNEL: DRP[107] bit 9 GTX_CHANNEL: PMA_RSV5 bit 1
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[19] bit 6 GTX_CHANNEL: SATA_MIN_BURST bit 3	GTX_CHANNEL: DRP[19] bit 7 GTX_CHANNEL: SATA_MIN_BURST bit 4	GTX_CHANNEL: DRP[107] bit 6	GTX_CHANNEL: DRP[107] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[19] bit 4 GTX_CHANNEL: SATA_MIN_BURST bit 1	GTX_CHANNEL: DRP[19] bit 5 GTX_CHANNEL: SATA_MIN_BURST bit 2	GTX_CHANNEL: DRP[107] bit 4 GTX_CHANNEL: TX_INT_DATAWIDTH bit 0	GTX_CHANNEL: DRP[107] bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[19] bit 2 GTX_CHANNEL: SATA_EIDLE_VAL bit 2	GTX_CHANNEL: DRP[19] bit 3 GTX_CHANNEL: SATA_MIN_BURST bit 0	GTX_CHANNEL: DRP[107] bit 2 GTX_CHANNEL: TX_DATA_WIDTH bit 2	GTX_CHANNEL: DRP[107] bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[19] bit 0 GTX_CHANNEL: SATA_EIDLE_VAL bit 0	GTX_CHANNEL: DRP[19] bit 1 GTX_CHANNEL: SATA_EIDLE_VAL bit 1	GTX_CHANNEL: DRP[107] bit 0 GTX_CHANNEL: TX_DATA_WIDTH bit 0	GTX_CHANNEL: DRP[107] bit 1 GTX_CHANNEL: TX_DATA_WIDTH bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[18] bit 14 GTX_CHANNEL: SATA_BURST_SEQ_LEN bit 2	GTX_CHANNEL: DRP[18] bit 15 GTX_CHANNEL: SATA_BURST_SEQ_LEN bit 3	GTX_CHANNEL: DRP[106] bit 14 GTX_CHANNEL: TERM_RCAL_OVRD_GTH bit 1	GTX_CHANNEL: DRP[106] bit 15 GTX_CHANNEL: TERM_RCAL_OVRD_GTH bit 2
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[18] bit 12 GTX_CHANNEL: SATA_BURST_SEQ_LEN bit 0	GTX_CHANNEL: DRP[18] bit 13 GTX_CHANNEL: SATA_BURST_SEQ_LEN bit 1	GTX_CHANNEL: DRP[106] bit 12	GTX_CHANNEL: DRP[106] bit 13 GTX_CHANNEL: TERM_RCAL_OVRD_GTH bit 0
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[18] bit 10 GTX_CHANNEL: OUTREFCLK_SEL_INV bit 0	GTX_CHANNEL: DRP[18] bit 11 GTX_CHANNEL: OUTREFCLK_SEL_INV bit 1	GTX_CHANNEL: DRP[106] bit 10	GTX_CHANNEL: DRP[106] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[18] bit 8 GTX_CHANNEL: SATA_BURST_VAL bit 1	GTX_CHANNEL: DRP[18] bit 9 GTX_CHANNEL: SATA_BURST_VAL bit 2	GTX_CHANNEL: DRP[106] bit 8	GTX_CHANNEL: DRP[106] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[18] bit 6 GTX_CHANNEL: RXOOB_CFG bit 6	GTX_CHANNEL: DRP[18] bit 7 GTX_CHANNEL: SATA_BURST_VAL bit 0	GTX_CHANNEL: DRP[106] bit 6	GTX_CHANNEL: DRP[106] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[18] bit 4 GTX_CHANNEL: RXOOB_CFG bit 4	GTX_CHANNEL: DRP[18] bit 5 GTX_CHANNEL: RXOOB_CFG bit 5	GTX_CHANNEL: DRP[106] bit 4 GTX_CHANNEL: TX_CLK25_DIV bit 4	GTX_CHANNEL: DRP[106] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[18] bit 2 GTX_CHANNEL: RXOOB_CFG bit 2	GTX_CHANNEL: DRP[18] bit 3 GTX_CHANNEL: RXOOB_CFG bit 3	GTX_CHANNEL: DRP[106] bit 2 GTX_CHANNEL: TX_CLK25_DIV bit 2	GTX_CHANNEL: DRP[106] bit 3 GTX_CHANNEL: TX_CLK25_DIV bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[18] bit 0 GTX_CHANNEL: RXOOB_CFG bit 0	GTX_CHANNEL: DRP[18] bit 1 GTX_CHANNEL: RXOOB_CFG bit 1	GTX_CHANNEL: DRP[106] bit 0 GTX_CHANNEL: TX_CLK25_DIV bit 0	GTX_CHANNEL: DRP[106] bit 1 GTX_CHANNEL: TX_CLK25_DIV bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[17] bit 14 GTX_CHANNEL: RX_INT_DATAWIDTH bit 0	GTX_CHANNEL: DRP[17] bit 15	GTX_CHANNEL: DRP[105] bit 14 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 14	GTX_CHANNEL: DRP[105] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[17] bit 12 GTX_CHANNEL: RX_DATA_WIDTH bit 1	GTX_CHANNEL: DRP[17] bit 13 GTX_CHANNEL: RX_DATA_WIDTH bit 2	GTX_CHANNEL: DRP[105] bit 12 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 12	GTX_CHANNEL: DRP[105] bit 13 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[17] bit 10 GTX_CHANNEL: RX_CLK25_DIV bit 4	GTX_CHANNEL: DRP[17] bit 11 GTX_CHANNEL: RX_DATA_WIDTH bit 0	GTX_CHANNEL: DRP[105] bit 10 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 10	GTX_CHANNEL: DRP[105] bit 11 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[17] bit 8 GTX_CHANNEL: RX_CLK25_DIV bit 2	GTX_CHANNEL: DRP[17] bit 9 GTX_CHANNEL: RX_CLK25_DIV bit 3	GTX_CHANNEL: DRP[105] bit 8 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 8	GTX_CHANNEL: DRP[105] bit 9 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[17] bit 6 GTX_CHANNEL: RX_CLK25_DIV bit 0	GTX_CHANNEL: DRP[17] bit 7 GTX_CHANNEL: RX_CLK25_DIV bit 1	GTX_CHANNEL: DRP[105] bit 6 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 6	GTX_CHANNEL: DRP[105] bit 7 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[17] bit 4 GTX_CHANNEL: RX_CM_SEL bit 0	GTX_CHANNEL: DRP[17] bit 5 GTX_CHANNEL: RX_CM_SEL bit 1	GTX_CHANNEL: DRP[105] bit 4 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 4	GTX_CHANNEL: DRP[105] bit 5 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[17] bit 2	GTX_CHANNEL: DRP[17] bit 3	GTX_CHANNEL: DRP[105] bit 2 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 2	GTX_CHANNEL: DRP[105] bit 3 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[17] bit 0 GTX_CHANNEL: RXPRBS_ERR_LOOPBACK bit 0	GTX_CHANNEL: DRP[17] bit 1	GTX_CHANNEL: DRP[105] bit 0 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 0	GTX_CHANNEL: DRP[105] bit 1 GTX_CHANNEL: TERM_RCAL_CFG_GTH bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[16] bit 14 GTX_CHANNEL: TXSYNC_OVRD bit 0	GTX_CHANNEL: DRP[16] bit 15 GTX_CHANNEL: RXSYNC_OVRD bit 0	GTX_CHANNEL: DRP[104] bit 14	GTX_CHANNEL: DRP[104] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[16] bit 12 GTX_CHANNEL: RXSYNC_SKIP_DA bit 0	GTX_CHANNEL: DRP[16] bit 13 GTX_CHANNEL: TXSYNC_SKIP_DA bit 0	GTX_CHANNEL: DRP[104] bit 12	GTX_CHANNEL: DRP[104] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[16] bit 10 GTX_CHANNEL: RXSYNC_MULTILANE bit 0	GTX_CHANNEL: DRP[16] bit 11 GTX_CHANNEL: TXSYNC_MULTILANE bit 0	GTX_CHANNEL: DRP[104] bit 10	GTX_CHANNEL: DRP[104] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[16] bit 8	GTX_CHANNEL: DRP[16] bit 9	GTX_CHANNEL: DRP[104] bit 8	GTX_CHANNEL: DRP[104] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[16] bit 6 GTX_CHANNEL: RXCDRRESET_TIME bit 6	GTX_CHANNEL: DRP[16] bit 7	GTX_CHANNEL: DRP[104] bit 6	GTX_CHANNEL: DRP[104] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[16] bit 4 GTX_CHANNEL: RXCDRRESET_TIME bit 4	GTX_CHANNEL: DRP[16] bit 5 GTX_CHANNEL: RXCDRRESET_TIME bit 5	GTX_CHANNEL: DRP[104] bit 4	GTX_CHANNEL: DRP[104] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[16] bit 2 GTX_CHANNEL: RXCDRRESET_TIME bit 2	GTX_CHANNEL: DRP[16] bit 3 GTX_CHANNEL: RXCDRRESET_TIME bit 3	GTX_CHANNEL: DRP[104] bit 2 GTX_CHANNEL: TXPISO_DIV_45 bit 0	GTX_CHANNEL: DRP[104] bit 3 GTX_CHANNEL: RXOOB_CLK_CFG bit 0
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[16] bit 0 GTX_CHANNEL: RXCDRRESET_TIME bit 0	GTX_CHANNEL: DRP[16] bit 1 GTX_CHANNEL: RXCDRRESET_TIME bit 1	GTX_CHANNEL: DRP[104] bit 0 GTX_CHANNEL: RX_CLKMUX_PD bit 0	GTX_CHANNEL: DRP[104] bit 1 GTX_CHANNEL: TX_CLKMUX_PD bit 0

virtex7 GTH_CHANNEL rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[31] bit 14	GTX_CHANNEL: DRP[31] bit 15	GTX_CHANNEL: DRP[119] bit 14 GTX_CHANNEL: TX_MARGIN_LOW_0 bit 6	GTX_CHANNEL: DRP[119] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[31] bit 12	GTX_CHANNEL: DRP[31] bit 13	GTX_CHANNEL: DRP[119] bit 12 GTX_CHANNEL: TX_MARGIN_LOW_0 bit 4	GTX_CHANNEL: DRP[119] bit 13 GTX_CHANNEL: TX_MARGIN_LOW_0 bit 5
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[31] bit 10 GTX_CHANNEL: RX_DFE_H2_CFG bit 10	GTX_CHANNEL: DRP[31] bit 11 GTX_CHANNEL: RX_DFE_H2_CFG bit 11	GTX_CHANNEL: DRP[119] bit 10 GTX_CHANNEL: TX_MARGIN_LOW_0 bit 2	GTX_CHANNEL: DRP[119] bit 11 GTX_CHANNEL: TX_MARGIN_LOW_0 bit 3
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[31] bit 8 GTX_CHANNEL: RX_DFE_H2_CFG bit 8	GTX_CHANNEL: DRP[31] bit 9 GTX_CHANNEL: RX_DFE_H2_CFG bit 9	GTX_CHANNEL: DRP[119] bit 8 GTX_CHANNEL: TX_MARGIN_LOW_0 bit 0	GTX_CHANNEL: DRP[119] bit 9 GTX_CHANNEL: TX_MARGIN_LOW_0 bit 1
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[31] bit 6 GTX_CHANNEL: RX_DFE_H2_CFG bit 6	GTX_CHANNEL: DRP[31] bit 7 GTX_CHANNEL: RX_DFE_H2_CFG bit 7	GTX_CHANNEL: DRP[119] bit 6 GTX_CHANNEL: TX_MARGIN_FULL_4 bit 6	GTX_CHANNEL: DRP[119] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[31] bit 4 GTX_CHANNEL: RX_DFE_H2_CFG bit 4	GTX_CHANNEL: DRP[31] bit 5 GTX_CHANNEL: RX_DFE_H2_CFG bit 5	GTX_CHANNEL: DRP[119] bit 4 GTX_CHANNEL: TX_MARGIN_FULL_4 bit 4	GTX_CHANNEL: DRP[119] bit 5 GTX_CHANNEL: TX_MARGIN_FULL_4 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[31] bit 2 GTX_CHANNEL: RX_DFE_H2_CFG bit 2	GTX_CHANNEL: DRP[31] bit 3 GTX_CHANNEL: RX_DFE_H2_CFG bit 3	GTX_CHANNEL: DRP[119] bit 2 GTX_CHANNEL: TX_MARGIN_FULL_4 bit 2	GTX_CHANNEL: DRP[119] bit 3 GTX_CHANNEL: TX_MARGIN_FULL_4 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[31] bit 0 GTX_CHANNEL: RX_DFE_H2_CFG bit 0	GTX_CHANNEL: DRP[31] bit 1 GTX_CHANNEL: RX_DFE_H2_CFG bit 1	GTX_CHANNEL: DRP[119] bit 0 GTX_CHANNEL: TX_MARGIN_FULL_4 bit 0	GTX_CHANNEL: DRP[119] bit 1 GTX_CHANNEL: TX_MARGIN_FULL_4 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[30] bit 14 GTX_CHANNEL: RX_DFE_LPM_HOLD_DURING_EIDLE bit 0	GTX_CHANNEL: DRP[30] bit 15 GTX_CHANNEL: RXPLL_SEL bit 0	GTX_CHANNEL: DRP[118] bit 14 GTX_CHANNEL: TX_MARGIN_FULL_3 bit 6	GTX_CHANNEL: DRP[118] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[30] bit 12	GTX_CHANNEL: DRP[30] bit 13	GTX_CHANNEL: DRP[118] bit 12 GTX_CHANNEL: TX_MARGIN_FULL_3 bit 4	GTX_CHANNEL: DRP[118] bit 13 GTX_CHANNEL: TX_MARGIN_FULL_3 bit 5
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[30] bit 10	GTX_CHANNEL: DRP[30] bit 11	GTX_CHANNEL: DRP[118] bit 10 GTX_CHANNEL: TX_MARGIN_FULL_3 bit 2	GTX_CHANNEL: DRP[118] bit 11 GTX_CHANNEL: TX_MARGIN_FULL_3 bit 3
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[30] bit 8	GTX_CHANNEL: DRP[30] bit 9	GTX_CHANNEL: DRP[118] bit 8 GTX_CHANNEL: TX_MARGIN_FULL_3 bit 0	GTX_CHANNEL: DRP[118] bit 9 GTX_CHANNEL: TX_MARGIN_FULL_3 bit 1
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[30] bit 6 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 22	GTX_CHANNEL: DRP[30] bit 7	GTX_CHANNEL: DRP[118] bit 6 GTX_CHANNEL: TX_MARGIN_FULL_2 bit 6	GTX_CHANNEL: DRP[118] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[30] bit 4 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 20	GTX_CHANNEL: DRP[30] bit 5 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 21	GTX_CHANNEL: DRP[118] bit 4 GTX_CHANNEL: TX_MARGIN_FULL_2 bit 4	GTX_CHANNEL: DRP[118] bit 5 GTX_CHANNEL: TX_MARGIN_FULL_2 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[30] bit 2 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 18	GTX_CHANNEL: DRP[30] bit 3 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 19	GTX_CHANNEL: DRP[118] bit 2 GTX_CHANNEL: TX_MARGIN_FULL_2 bit 2	GTX_CHANNEL: DRP[118] bit 3 GTX_CHANNEL: TX_MARGIN_FULL_2 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[30] bit 0 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 16	GTX_CHANNEL: DRP[30] bit 1 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 17	GTX_CHANNEL: DRP[118] bit 0 GTX_CHANNEL: TX_MARGIN_FULL_2 bit 0	GTX_CHANNEL: DRP[118] bit 1 GTX_CHANNEL: TX_MARGIN_FULL_2 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[29] bit 14 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 14	GTX_CHANNEL: DRP[29] bit 15 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 15	GTX_CHANNEL: DRP[117] bit 14 GTX_CHANNEL: TX_MARGIN_FULL_1 bit 6	GTX_CHANNEL: DRP[117] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[29] bit 12 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 12	GTX_CHANNEL: DRP[29] bit 13 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 13	GTX_CHANNEL: DRP[117] bit 12 GTX_CHANNEL: TX_MARGIN_FULL_1 bit 4	GTX_CHANNEL: DRP[117] bit 13 GTX_CHANNEL: TX_MARGIN_FULL_1 bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[29] bit 10 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 10	GTX_CHANNEL: DRP[29] bit 11 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 11	GTX_CHANNEL: DRP[117] bit 10 GTX_CHANNEL: TX_MARGIN_FULL_1 bit 2	GTX_CHANNEL: DRP[117] bit 11 GTX_CHANNEL: TX_MARGIN_FULL_1 bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[29] bit 8 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 8	GTX_CHANNEL: DRP[29] bit 9 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 9	GTX_CHANNEL: DRP[117] bit 8 GTX_CHANNEL: TX_MARGIN_FULL_1 bit 0	GTX_CHANNEL: DRP[117] bit 9 GTX_CHANNEL: TX_MARGIN_FULL_1 bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[29] bit 6 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 6	GTX_CHANNEL: DRP[29] bit 7 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 7	GTX_CHANNEL: DRP[117] bit 6 GTX_CHANNEL: TX_MARGIN_FULL_0 bit 6	GTX_CHANNEL: DRP[117] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[29] bit 4 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 4	GTX_CHANNEL: DRP[29] bit 5 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 5	GTX_CHANNEL: DRP[117] bit 4 GTX_CHANNEL: TX_MARGIN_FULL_0 bit 4	GTX_CHANNEL: DRP[117] bit 5 GTX_CHANNEL: TX_MARGIN_FULL_0 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[29] bit 2 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 2	GTX_CHANNEL: DRP[29] bit 3 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 3	GTX_CHANNEL: DRP[117] bit 2 GTX_CHANNEL: TX_MARGIN_FULL_0 bit 2	GTX_CHANNEL: DRP[117] bit 3 GTX_CHANNEL: TX_MARGIN_FULL_0 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[29] bit 0 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 0	GTX_CHANNEL: DRP[29] bit 1 GTX_CHANNEL: RX_DFE_GAIN_CFG bit 1	GTX_CHANNEL: DRP[117] bit 0 GTX_CHANNEL: TX_MARGIN_FULL_0 bit 0	GTX_CHANNEL: DRP[117] bit 1 GTX_CHANNEL: TX_MARGIN_FULL_0 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[28] bit 14 GTX_CHANNEL: TXBUF_EN	GTX_CHANNEL: DRP[28] bit 15 GTX_CHANNEL: TXBUF_RESET_ON_RATE_CHANGE	GTX_CHANNEL: DRP[116] bit 14	GTX_CHANNEL: DRP[116] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[28] bit 12	GTX_CHANNEL: DRP[28] bit 13	GTX_CHANNEL: DRP[116] bit 12 GTX_CHANNEL: RX_DFE_AGC_CFG2 bit 3	GTX_CHANNEL: DRP[116] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[28] bit 10	GTX_CHANNEL: DRP[28] bit 11	GTX_CHANNEL: DRP[116] bit 10 GTX_CHANNEL: RX_DFE_AGC_CFG2 bit 1	GTX_CHANNEL: DRP[116] bit 11 GTX_CHANNEL: RX_DFE_AGC_CFG2 bit 2
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[28] bit 8	GTX_CHANNEL: DRP[28] bit 9	GTX_CHANNEL: DRP[116] bit 8 GTX_CHANNEL: RX_DFE_AGC_CFG1 bit 2	GTX_CHANNEL: DRP[116] bit 9 GTX_CHANNEL: RX_DFE_AGC_CFG2 bit 0
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[28] bit 6	GTX_CHANNEL: DRP[28] bit 7	GTX_CHANNEL: DRP[116] bit 6 GTX_CHANNEL: RX_DFE_AGC_CFG1 bit 0	GTX_CHANNEL: DRP[116] bit 7 GTX_CHANNEL: RX_DFE_AGC_CFG1 bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[28] bit 4	GTX_CHANNEL: DRP[28] bit 5 GTX_CHANNEL: TXGEARBOX_EN	GTX_CHANNEL: DRP[116] bit 4 GTX_CHANNEL: RX_DFE_AGC_CFG0 bit 0	GTX_CHANNEL: DRP[116] bit 5 GTX_CHANNEL: RX_DFE_AGC_CFG0 bit 1
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[28] bit 2 GTX_CHANNEL: GEARBOX_MODE bit 2	GTX_CHANNEL: DRP[28] bit 3	GTX_CHANNEL: DRP[116] bit 2	GTX_CHANNEL: DRP[116] bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[28] bit 0 GTX_CHANNEL: GEARBOX_MODE bit 0	GTX_CHANNEL: DRP[28] bit 1 GTX_CHANNEL: GEARBOX_MODE bit 1	GTX_CHANNEL: DRP[116] bit 0 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 32	GTX_CHANNEL: DRP[116] bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[27] bit 14	GTX_CHANNEL: DRP[27] bit 15	GTX_CHANNEL: DRP[115] bit 14 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 30	GTX_CHANNEL: DRP[115] bit 15 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 31
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[27] bit 12 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 11	GTX_CHANNEL: DRP[27] bit 13	GTX_CHANNEL: DRP[115] bit 12 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 28	GTX_CHANNEL: DRP[115] bit 13 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 29
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[27] bit 10 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 9	GTX_CHANNEL: DRP[27] bit 11 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 10	GTX_CHANNEL: DRP[115] bit 10 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 26	GTX_CHANNEL: DRP[115] bit 11 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 27
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[27] bit 8 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 7	GTX_CHANNEL: DRP[27] bit 9 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 8	GTX_CHANNEL: DRP[115] bit 8 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 24	GTX_CHANNEL: DRP[115] bit 9 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 25
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[27] bit 6 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 5	GTX_CHANNEL: DRP[27] bit 7 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 6	GTX_CHANNEL: DRP[115] bit 6 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 22	GTX_CHANNEL: DRP[115] bit 7 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 23
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[27] bit 4 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 3	GTX_CHANNEL: DRP[27] bit 5 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 4	GTX_CHANNEL: DRP[115] bit 4 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 20	GTX_CHANNEL: DRP[115] bit 5 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 21
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[27] bit 2 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 1	GTX_CHANNEL: DRP[27] bit 3 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 2	GTX_CHANNEL: DRP[115] bit 2 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 18	GTX_CHANNEL: DRP[115] bit 3 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 19
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[27] bit 0 GTX_CHANNEL: PCS_PCIE_EN	GTX_CHANNEL: DRP[27] bit 1 GTX_CHANNEL: PD_TRANS_TIME_FROM_P2 bit 0	GTX_CHANNEL: DRP[115] bit 0 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 16	GTX_CHANNEL: DRP[115] bit 1 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 17
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[26] bit 14 GTX_CHANNEL: PD_TRANS_TIME_TO_P2 bit 6	GTX_CHANNEL: DRP[26] bit 15 GTX_CHANNEL: PD_TRANS_TIME_TO_P2 bit 7	GTX_CHANNEL: DRP[114] bit 14 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 14	GTX_CHANNEL: DRP[114] bit 15 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[26] bit 12 GTX_CHANNEL: PD_TRANS_TIME_TO_P2 bit 4	GTX_CHANNEL: DRP[26] bit 13 GTX_CHANNEL: PD_TRANS_TIME_TO_P2 bit 5	GTX_CHANNEL: DRP[114] bit 12 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 12	GTX_CHANNEL: DRP[114] bit 13 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[26] bit 10 GTX_CHANNEL: PD_TRANS_TIME_TO_P2 bit 2	GTX_CHANNEL: DRP[26] bit 11 GTX_CHANNEL: PD_TRANS_TIME_TO_P2 bit 3	GTX_CHANNEL: DRP[114] bit 10 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 10	GTX_CHANNEL: DRP[114] bit 11 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[26] bit 8 GTX_CHANNEL: PD_TRANS_TIME_TO_P2 bit 0	GTX_CHANNEL: DRP[26] bit 9 GTX_CHANNEL: PD_TRANS_TIME_TO_P2 bit 1	GTX_CHANNEL: DRP[114] bit 8 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 8	GTX_CHANNEL: DRP[114] bit 9 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[26] bit 6 GTX_CHANNEL: PD_TRANS_TIME_NONE_P2 bit 6	GTX_CHANNEL: DRP[26] bit 7 GTX_CHANNEL: PD_TRANS_TIME_NONE_P2 bit 7	GTX_CHANNEL: DRP[114] bit 6 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 6	GTX_CHANNEL: DRP[114] bit 7 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[26] bit 4 GTX_CHANNEL: PD_TRANS_TIME_NONE_P2 bit 4	GTX_CHANNEL: DRP[26] bit 5 GTX_CHANNEL: PD_TRANS_TIME_NONE_P2 bit 5	GTX_CHANNEL: DRP[114] bit 4 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 4	GTX_CHANNEL: DRP[114] bit 5 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[26] bit 2 GTX_CHANNEL: PD_TRANS_TIME_NONE_P2 bit 2	GTX_CHANNEL: DRP[26] bit 3 GTX_CHANNEL: PD_TRANS_TIME_NONE_P2 bit 3	GTX_CHANNEL: DRP[114] bit 2 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 2	GTX_CHANNEL: DRP[114] bit 3 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[26] bit 0 GTX_CHANNEL: PD_TRANS_TIME_NONE_P2 bit 0	GTX_CHANNEL: DRP[26] bit 1 GTX_CHANNEL: PD_TRANS_TIME_NONE_P2 bit 1	GTX_CHANNEL: DRP[114] bit 0 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 0	GTX_CHANNEL: DRP[114] bit 1 GTX_CHANNEL: RX_DFE_KL_CFG_GTH bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[25] bit 14	GTX_CHANNEL: DRP[25] bit 15	GTX_CHANNEL: DRP[113] bit 14 GTX_CHANNEL: PCS_RSVD_ATTR bit 46	GTX_CHANNEL: DRP[113] bit 15 GTX_CHANNEL: PCS_RSVD_ATTR bit 47
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[25] bit 12	GTX_CHANNEL: DRP[25] bit 13	GTX_CHANNEL: DRP[113] bit 12 GTX_CHANNEL: PCS_RSVD_ATTR bit 44	GTX_CHANNEL: DRP[113] bit 13 GTX_CHANNEL: PCS_RSVD_ATTR bit 45
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[25] bit 10 GTX_CHANNEL: TX_EIDLE_DEASSERT_DELAY bit 1	GTX_CHANNEL: DRP[25] bit 11 GTX_CHANNEL: TX_EIDLE_DEASSERT_DELAY bit 2	GTX_CHANNEL: DRP[113] bit 10 GTX_CHANNEL: PCS_RSVD_ATTR bit 42	GTX_CHANNEL: DRP[113] bit 11 GTX_CHANNEL: PCS_RSVD_ATTR bit 43
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[25] bit 8 GTX_CHANNEL: TX_EIDLE_ASSERT_DELAY bit 2	GTX_CHANNEL: DRP[25] bit 9 GTX_CHANNEL: TX_EIDLE_DEASSERT_DELAY bit 0	GTX_CHANNEL: DRP[113] bit 8 GTX_CHANNEL: PCS_RSVD_ATTR bit 40	GTX_CHANNEL: DRP[113] bit 9 GTX_CHANNEL: PCS_RSVD_ATTR bit 41
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[25] bit 6 GTX_CHANNEL: TX_EIDLE_ASSERT_DELAY bit 0	GTX_CHANNEL: DRP[25] bit 7 GTX_CHANNEL: TX_EIDLE_ASSERT_DELAY bit 1	GTX_CHANNEL: DRP[113] bit 6 GTX_CHANNEL: PCS_RSVD_ATTR bit 38	GTX_CHANNEL: DRP[113] bit 7 GTX_CHANNEL: PCS_RSVD_ATTR bit 39
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[25] bit 4	GTX_CHANNEL: DRP[25] bit 5 GTX_CHANNEL: TX_LOOPBACK_DRIVE_HIZ	GTX_CHANNEL: DRP[113] bit 4 GTX_CHANNEL: PCS_RSVD_ATTR bit 36	GTX_CHANNEL: DRP[113] bit 5 GTX_CHANNEL: PCS_RSVD_ATTR bit 37
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[25] bit 2	GTX_CHANNEL: DRP[25] bit 3	GTX_CHANNEL: DRP[113] bit 2 GTX_CHANNEL: PCS_RSVD_ATTR bit 34	GTX_CHANNEL: DRP[113] bit 3 GTX_CHANNEL: PCS_RSVD_ATTR bit 35
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[25] bit 0 GTX_CHANNEL: TX_DRIVE_MODE bit 0	GTX_CHANNEL: DRP[25] bit 1 GTX_CHANNEL: TX_DRIVE_MODE bit 1	GTX_CHANNEL: DRP[113] bit 0 GTX_CHANNEL: PCS_RSVD_ATTR bit 32	GTX_CHANNEL: DRP[113] bit 1 GTX_CHANNEL: PCS_RSVD_ATTR bit 33
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[24] bit 14 GTX_CHANNEL: A_TXPOSTCURSOR bit 4	GTX_CHANNEL: DRP[24] bit 15	GTX_CHANNEL: DRP[112] bit 14 GTX_CHANNEL: PCS_RSVD_ATTR bit 30	GTX_CHANNEL: DRP[112] bit 15 GTX_CHANNEL: PCS_RSVD_ATTR bit 31
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[24] bit 12 GTX_CHANNEL: A_TXPOSTCURSOR bit 2	GTX_CHANNEL: DRP[24] bit 13 GTX_CHANNEL: A_TXPOSTCURSOR bit 3	GTX_CHANNEL: DRP[112] bit 12 GTX_CHANNEL: PCS_RSVD_ATTR bit 28	GTX_CHANNEL: DRP[112] bit 13 GTX_CHANNEL: PCS_RSVD_ATTR bit 29
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[24] bit 10 GTX_CHANNEL: A_TXPOSTCURSOR bit 0	GTX_CHANNEL: DRP[24] bit 11 GTX_CHANNEL: A_TXPOSTCURSOR bit 1	GTX_CHANNEL: DRP[112] bit 10 GTX_CHANNEL: PCS_RSVD_ATTR bit 26	GTX_CHANNEL: DRP[112] bit 11 GTX_CHANNEL: PCS_RSVD_ATTR bit 27
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[24] bit 8	GTX_CHANNEL: DRP[24] bit 9	GTX_CHANNEL: DRP[112] bit 8 GTX_CHANNEL: PCS_RSVD_ATTR bit 24	GTX_CHANNEL: DRP[112] bit 9 GTX_CHANNEL: PCS_RSVD_ATTR bit 25
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[24] bit 6 GTX_CHANNEL: TRANS_TIME_RATE bit 6	GTX_CHANNEL: DRP[24] bit 7 GTX_CHANNEL: TRANS_TIME_RATE bit 7	GTX_CHANNEL: DRP[112] bit 6 GTX_CHANNEL: PCS_RSVD_ATTR bit 22	GTX_CHANNEL: DRP[112] bit 7 GTX_CHANNEL: PCS_RSVD_ATTR bit 23
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[24] bit 4 GTX_CHANNEL: TRANS_TIME_RATE bit 4	GTX_CHANNEL: DRP[24] bit 5 GTX_CHANNEL: TRANS_TIME_RATE bit 5	GTX_CHANNEL: DRP[112] bit 4 GTX_CHANNEL: PCS_RSVD_ATTR bit 20	GTX_CHANNEL: DRP[112] bit 5 GTX_CHANNEL: PCS_RSVD_ATTR bit 21
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[24] bit 2 GTX_CHANNEL: TRANS_TIME_RATE bit 2	GTX_CHANNEL: DRP[24] bit 3 GTX_CHANNEL: TRANS_TIME_RATE bit 3	GTX_CHANNEL: DRP[112] bit 2 GTX_CHANNEL: PCS_RSVD_ATTR bit 18	GTX_CHANNEL: DRP[112] bit 3 GTX_CHANNEL: PCS_RSVD_ATTR bit 19
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[24] bit 0 GTX_CHANNEL: TRANS_TIME_RATE bit 0	GTX_CHANNEL: DRP[24] bit 1 GTX_CHANNEL: TRANS_TIME_RATE bit 1	GTX_CHANNEL: DRP[112] bit 0 GTX_CHANNEL: PCS_RSVD_ATTR bit 16	GTX_CHANNEL: DRP[112] bit 1 GTX_CHANNEL: PCS_RSVD_ATTR bit 17

virtex7 GTH_CHANNEL rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[39] bit 14	GTX_CHANNEL: DRP[39] bit 15	GTX_CHANNEL: DRP[127] bit 14 GTX_CHANNEL: CPLL_CFG_GTH bit 14	GTX_CHANNEL: DRP[127] bit 15 GTX_CHANNEL: CPLL_CFG_GTH bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[39] bit 12 GTX_CHANNEL: RX_DFE_VS_CFG bit 8	GTX_CHANNEL: DRP[39] bit 13	GTX_CHANNEL: DRP[127] bit 12 GTX_CHANNEL: CPLL_CFG_GTH bit 12	GTX_CHANNEL: DRP[127] bit 13 GTX_CHANNEL: CPLL_CFG_GTH bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[39] bit 10 GTX_CHANNEL: RX_DFE_VS_CFG bit 6	GTX_CHANNEL: DRP[39] bit 11 GTX_CHANNEL: RX_DFE_VS_CFG bit 7	GTX_CHANNEL: DRP[127] bit 10 GTX_CHANNEL: CPLL_CFG_GTH bit 10	GTX_CHANNEL: DRP[127] bit 11 GTX_CHANNEL: CPLL_CFG_GTH bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[39] bit 8 GTX_CHANNEL: RX_DFE_VS_CFG bit 4	GTX_CHANNEL: DRP[39] bit 9 GTX_CHANNEL: RX_DFE_VS_CFG bit 5	GTX_CHANNEL: DRP[127] bit 8 GTX_CHANNEL: CPLL_CFG_GTH bit 8	GTX_CHANNEL: DRP[127] bit 9 GTX_CHANNEL: CPLL_CFG_GTH bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[39] bit 6 GTX_CHANNEL: RX_DFE_VS_CFG bit 2	GTX_CHANNEL: DRP[39] bit 7 GTX_CHANNEL: RX_DFE_VS_CFG bit 3	GTX_CHANNEL: DRP[127] bit 6 GTX_CHANNEL: CPLL_CFG_GTH bit 6	GTX_CHANNEL: DRP[127] bit 7 GTX_CHANNEL: CPLL_CFG_GTH bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[39] bit 4 GTX_CHANNEL: RX_DFE_VS_CFG bit 0	GTX_CHANNEL: DRP[39] bit 5 GTX_CHANNEL: RX_DFE_VS_CFG bit 1	GTX_CHANNEL: DRP[127] bit 4 GTX_CHANNEL: CPLL_CFG_GTH bit 4	GTX_CHANNEL: DRP[127] bit 5 GTX_CHANNEL: CPLL_CFG_GTH bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[39] bit 2	GTX_CHANNEL: DRP[39] bit 3	GTX_CHANNEL: DRP[127] bit 2 GTX_CHANNEL: CPLL_CFG_GTH bit 2	GTX_CHANNEL: DRP[127] bit 3 GTX_CHANNEL: CPLL_CFG_GTH bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[39] bit 0 GTX_CHANNEL: RX_DFE_VP_CFG bit 16	GTX_CHANNEL: DRP[39] bit 1	GTX_CHANNEL: DRP[127] bit 0 GTX_CHANNEL: CPLL_CFG_GTH bit 0	GTX_CHANNEL: DRP[127] bit 1 GTX_CHANNEL: CPLL_CFG_GTH bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[38] bit 14 GTX_CHANNEL: RX_DFE_VP_CFG bit 14	GTX_CHANNEL: DRP[38] bit 15 GTX_CHANNEL: RX_DFE_VP_CFG bit 15	GTX_CHANNEL: DRP[126] bit 14 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG0 bit 1	GTX_CHANNEL: DRP[126] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[38] bit 12 GTX_CHANNEL: RX_DFE_VP_CFG bit 12	GTX_CHANNEL: DRP[38] bit 13 GTX_CHANNEL: RX_DFE_VP_CFG bit 13	GTX_CHANNEL: DRP[126] bit 12 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG2 bit 3	GTX_CHANNEL: DRP[126] bit 13 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG0 bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[38] bit 10 GTX_CHANNEL: RX_DFE_VP_CFG bit 10	GTX_CHANNEL: DRP[38] bit 11 GTX_CHANNEL: RX_DFE_VP_CFG bit 11	GTX_CHANNEL: DRP[126] bit 10 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG2 bit 1	GTX_CHANNEL: DRP[126] bit 11 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG2 bit 2
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[38] bit 8 GTX_CHANNEL: RX_DFE_VP_CFG bit 8	GTX_CHANNEL: DRP[38] bit 9 GTX_CHANNEL: RX_DFE_VP_CFG bit 9	GTX_CHANNEL: DRP[126] bit 8 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG1 bit 2	GTX_CHANNEL: DRP[126] bit 9 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG2 bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[38] bit 6 GTX_CHANNEL: RX_DFE_VP_CFG bit 6	GTX_CHANNEL: DRP[38] bit 7 GTX_CHANNEL: RX_DFE_VP_CFG bit 7	GTX_CHANNEL: DRP[126] bit 6 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG1 bit 0	GTX_CHANNEL: DRP[126] bit 7 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG1 bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[38] bit 4 GTX_CHANNEL: RX_DFE_VP_CFG bit 4	GTX_CHANNEL: DRP[38] bit 5 GTX_CHANNEL: RX_DFE_VP_CFG bit 5	GTX_CHANNEL: DRP[126] bit 4 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG0 bit 0	GTX_CHANNEL: DRP[126] bit 5 GTX_CHANNEL: RX_DFE_KL_LPM_KH_CFG0 bit 1
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[38] bit 2 GTX_CHANNEL: RX_DFE_VP_CFG bit 2	GTX_CHANNEL: DRP[38] bit 3 GTX_CHANNEL: RX_DFE_VP_CFG bit 3	GTX_CHANNEL: DRP[126] bit 2 GTX_CHANNEL: RX_CM_TRIM_GTH bit 2	GTX_CHANNEL: DRP[126] bit 3 GTX_CHANNEL: RX_CM_TRIM_GTH bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[38] bit 0 GTX_CHANNEL: RX_DFE_VP_CFG bit 0	GTX_CHANNEL: DRP[38] bit 1 GTX_CHANNEL: RX_DFE_VP_CFG bit 1	GTX_CHANNEL: DRP[126] bit 0 GTX_CHANNEL: RX_CM_TRIM_GTH bit 0	GTX_CHANNEL: DRP[126] bit 1 GTX_CHANNEL: RX_CM_TRIM_GTH bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[37] bit 14 GTX_CHANNEL: RX_DFE_UT_CFG bit 14	GTX_CHANNEL: DRP[37] bit 15 GTX_CHANNEL: RX_DFE_UT_CFG bit 15	GTX_CHANNEL: DRP[125] bit 14	GTX_CHANNEL: DRP[125] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[37] bit 12 GTX_CHANNEL: RX_DFE_UT_CFG bit 12	GTX_CHANNEL: DRP[37] bit 13 GTX_CHANNEL: RX_DFE_UT_CFG bit 13	GTX_CHANNEL: DRP[125] bit 12 GTX_CHANNEL: TX_RXDETECT_CFG bit 12	GTX_CHANNEL: DRP[125] bit 13 GTX_CHANNEL: TX_RXDETECT_CFG bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[37] bit 10 GTX_CHANNEL: RX_DFE_UT_CFG bit 10	GTX_CHANNEL: DRP[37] bit 11 GTX_CHANNEL: RX_DFE_UT_CFG bit 11	GTX_CHANNEL: DRP[125] bit 10 GTX_CHANNEL: TX_RXDETECT_CFG bit 10	GTX_CHANNEL: DRP[125] bit 11 GTX_CHANNEL: TX_RXDETECT_CFG bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[37] bit 8 GTX_CHANNEL: RX_DFE_UT_CFG bit 8	GTX_CHANNEL: DRP[37] bit 9 GTX_CHANNEL: RX_DFE_UT_CFG bit 9	GTX_CHANNEL: DRP[125] bit 8 GTX_CHANNEL: TX_RXDETECT_CFG bit 8	GTX_CHANNEL: DRP[125] bit 9 GTX_CHANNEL: TX_RXDETECT_CFG bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[37] bit 6 GTX_CHANNEL: RX_DFE_UT_CFG bit 6	GTX_CHANNEL: DRP[37] bit 7 GTX_CHANNEL: RX_DFE_UT_CFG bit 7	GTX_CHANNEL: DRP[125] bit 6 GTX_CHANNEL: TX_RXDETECT_CFG bit 6	GTX_CHANNEL: DRP[125] bit 7 GTX_CHANNEL: TX_RXDETECT_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[37] bit 4 GTX_CHANNEL: RX_DFE_UT_CFG bit 4	GTX_CHANNEL: DRP[37] bit 5 GTX_CHANNEL: RX_DFE_UT_CFG bit 5	GTX_CHANNEL: DRP[125] bit 4 GTX_CHANNEL: TX_RXDETECT_CFG bit 4	GTX_CHANNEL: DRP[125] bit 5 GTX_CHANNEL: TX_RXDETECT_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[37] bit 2 GTX_CHANNEL: RX_DFE_UT_CFG bit 2	GTX_CHANNEL: DRP[37] bit 3 GTX_CHANNEL: RX_DFE_UT_CFG bit 3	GTX_CHANNEL: DRP[125] bit 2 GTX_CHANNEL: TX_RXDETECT_CFG bit 2	GTX_CHANNEL: DRP[125] bit 3 GTX_CHANNEL: TX_RXDETECT_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[37] bit 0 GTX_CHANNEL: RX_DFE_UT_CFG bit 0	GTX_CHANNEL: DRP[37] bit 1 GTX_CHANNEL: RX_DFE_UT_CFG bit 1	GTX_CHANNEL: DRP[125] bit 0 GTX_CHANNEL: TX_RXDETECT_CFG bit 0	GTX_CHANNEL: DRP[125] bit 1 GTX_CHANNEL: TX_RXDETECT_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[36] bit 14	GTX_CHANNEL: DRP[36] bit 15 GTX_CHANNEL: RX_DFE_UT_CFG bit 16	GTX_CHANNEL: DRP[124] bit 14	GTX_CHANNEL: DRP[124] bit 15 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 16
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[36] bit 12 GTX_CHANNEL: RX_OS_CFG bit 12	GTX_CHANNEL: DRP[36] bit 13	GTX_CHANNEL: DRP[124] bit 12 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG1 bit 1	GTX_CHANNEL: DRP[124] bit 13 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG1 bit 2
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[36] bit 10 GTX_CHANNEL: RX_OS_CFG bit 10	GTX_CHANNEL: DRP[36] bit 11 GTX_CHANNEL: RX_OS_CFG bit 11	GTX_CHANNEL: DRP[124] bit 10 GTX_CHANNEL: TX_RXDETECT_REF bit 2	GTX_CHANNEL: DRP[124] bit 11 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG1 bit 0
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[36] bit 8 GTX_CHANNEL: RX_OS_CFG bit 8	GTX_CHANNEL: DRP[36] bit 9 GTX_CHANNEL: RX_OS_CFG bit 9	GTX_CHANNEL: DRP[124] bit 8 GTX_CHANNEL: TX_RXDETECT_REF bit 0	GTX_CHANNEL: DRP[124] bit 9 GTX_CHANNEL: TX_RXDETECT_REF bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[36] bit 6 GTX_CHANNEL: RX_OS_CFG bit 6	GTX_CHANNEL: DRP[36] bit 7 GTX_CHANNEL: RX_OS_CFG bit 7	GTX_CHANNEL: DRP[124] bit 6 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG2 bit 2	GTX_CHANNEL: DRP[124] bit 7 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG2 bit 3
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[36] bit 4 GTX_CHANNEL: RX_OS_CFG bit 4	GTX_CHANNEL: DRP[36] bit 5 GTX_CHANNEL: RX_OS_CFG bit 5	GTX_CHANNEL: DRP[124] bit 4 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG2 bit 0	GTX_CHANNEL: DRP[124] bit 5 GTX_CHANNEL: RX_DFE_KL_LPM_KL_CFG2 bit 1
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[36] bit 2 GTX_CHANNEL: RX_OS_CFG bit 2	GTX_CHANNEL: DRP[36] bit 3 GTX_CHANNEL: RX_OS_CFG bit 3	GTX_CHANNEL: DRP[124] bit 2	GTX_CHANNEL: DRP[124] bit 3 GTX_CHANNEL: TX_MAINCURSOR_SEL bit 0
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[36] bit 0 GTX_CHANNEL: RX_OS_CFG bit 0	GTX_CHANNEL: DRP[36] bit 1 GTX_CHANNEL: RX_OS_CFG bit 1	GTX_CHANNEL: DRP[124] bit 0 GTX_CHANNEL: PMA_RSV3 bit 0	GTX_CHANNEL: DRP[124] bit 1 GTX_CHANNEL: PMA_RSV3 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[35] bit 14	GTX_CHANNEL: DRP[35] bit 15	GTX_CHANNEL: DRP[123] bit 14 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 14	GTX_CHANNEL: DRP[123] bit 15 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[35] bit 12	GTX_CHANNEL: DRP[35] bit 13	GTX_CHANNEL: DRP[123] bit 12 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 12	GTX_CHANNEL: DRP[123] bit 13 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[35] bit 10	GTX_CHANNEL: DRP[35] bit 11	GTX_CHANNEL: DRP[123] bit 10 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 10	GTX_CHANNEL: DRP[123] bit 11 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[35] bit 8	GTX_CHANNEL: DRP[35] bit 9	GTX_CHANNEL: DRP[123] bit 8 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 8	GTX_CHANNEL: DRP[123] bit 9 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[35] bit 6	GTX_CHANNEL: DRP[35] bit 7	GTX_CHANNEL: DRP[123] bit 6 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 6	GTX_CHANNEL: DRP[123] bit 7 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[35] bit 4	GTX_CHANNEL: DRP[35] bit 5	GTX_CHANNEL: DRP[123] bit 4 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 4	GTX_CHANNEL: DRP[123] bit 5 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[35] bit 2	GTX_CHANNEL: DRP[35] bit 3	GTX_CHANNEL: DRP[123] bit 2 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 2	GTX_CHANNEL: DRP[123] bit 3 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[35] bit 0	GTX_CHANNEL: DRP[35] bit 1	GTX_CHANNEL: DRP[123] bit 0 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 0	GTX_CHANNEL: DRP[123] bit 1 GTX_CHANNEL: TX_RXDETECT_PRECHARGE_TIME bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[34] bit 14	GTX_CHANNEL: DRP[34] bit 15	GTX_CHANNEL: DRP[122] bit 14	GTX_CHANNEL: DRP[122] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[34] bit 12	GTX_CHANNEL: DRP[34] bit 13	GTX_CHANNEL: DRP[122] bit 12 GTX_CHANNEL: TX_DEEMPH1_GTH bit 4	GTX_CHANNEL: DRP[122] bit 13 GTX_CHANNEL: TX_DEEMPH1_GTH bit 5
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[34] bit 10 GTX_CHANNEL: RX_DFE_H5_CFG bit 10	GTX_CHANNEL: DRP[34] bit 11	GTX_CHANNEL: DRP[122] bit 10 GTX_CHANNEL: TX_DEEMPH1_GTH bit 2	GTX_CHANNEL: DRP[122] bit 11 GTX_CHANNEL: TX_DEEMPH1_GTH bit 3
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[34] bit 8 GTX_CHANNEL: RX_DFE_H5_CFG bit 8	GTX_CHANNEL: DRP[34] bit 9 GTX_CHANNEL: RX_DFE_H5_CFG bit 9	GTX_CHANNEL: DRP[122] bit 8 GTX_CHANNEL: TX_DEEMPH1_GTH bit 0	GTX_CHANNEL: DRP[122] bit 9 GTX_CHANNEL: TX_DEEMPH1_GTH bit 1
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[34] bit 6 GTX_CHANNEL: RX_DFE_H5_CFG bit 6	GTX_CHANNEL: DRP[34] bit 7 GTX_CHANNEL: RX_DFE_H5_CFG bit 7	GTX_CHANNEL: DRP[122] bit 6	GTX_CHANNEL: DRP[122] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[34] bit 4 GTX_CHANNEL: RX_DFE_H5_CFG bit 4	GTX_CHANNEL: DRP[34] bit 5 GTX_CHANNEL: RX_DFE_H5_CFG bit 5	GTX_CHANNEL: DRP[122] bit 4 GTX_CHANNEL: TX_DEEMPH0_GTH bit 4	GTX_CHANNEL: DRP[122] bit 5 GTX_CHANNEL: TX_DEEMPH0_GTH bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[34] bit 2 GTX_CHANNEL: RX_DFE_H5_CFG bit 2	GTX_CHANNEL: DRP[34] bit 3 GTX_CHANNEL: RX_DFE_H5_CFG bit 3	GTX_CHANNEL: DRP[122] bit 2 GTX_CHANNEL: TX_DEEMPH0_GTH bit 2	GTX_CHANNEL: DRP[122] bit 3 GTX_CHANNEL: TX_DEEMPH0_GTH bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[34] bit 0 GTX_CHANNEL: RX_DFE_H5_CFG bit 0	GTX_CHANNEL: DRP[34] bit 1 GTX_CHANNEL: RX_DFE_H5_CFG bit 1	GTX_CHANNEL: DRP[122] bit 0 GTX_CHANNEL: TX_DEEMPH0_GTH bit 0	GTX_CHANNEL: DRP[122] bit 1 GTX_CHANNEL: TX_DEEMPH0_GTH bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[33] bit 14	GTX_CHANNEL: DRP[33] bit 15	GTX_CHANNEL: DRP[121] bit 14 GTX_CHANNEL: TX_MARGIN_LOW_4 bit 6	GTX_CHANNEL: DRP[121] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[33] bit 12	GTX_CHANNEL: DRP[33] bit 13	GTX_CHANNEL: DRP[121] bit 12 GTX_CHANNEL: TX_MARGIN_LOW_4 bit 4	GTX_CHANNEL: DRP[121] bit 13 GTX_CHANNEL: TX_MARGIN_LOW_4 bit 5
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[33] bit 10 GTX_CHANNEL: RX_DFE_H4_CFG bit 10	GTX_CHANNEL: DRP[33] bit 11	GTX_CHANNEL: DRP[121] bit 10 GTX_CHANNEL: TX_MARGIN_LOW_4 bit 2	GTX_CHANNEL: DRP[121] bit 11 GTX_CHANNEL: TX_MARGIN_LOW_4 bit 3
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[33] bit 8 GTX_CHANNEL: RX_DFE_H4_CFG bit 8	GTX_CHANNEL: DRP[33] bit 9 GTX_CHANNEL: RX_DFE_H4_CFG bit 9	GTX_CHANNEL: DRP[121] bit 8 GTX_CHANNEL: TX_MARGIN_LOW_4 bit 0	GTX_CHANNEL: DRP[121] bit 9 GTX_CHANNEL: TX_MARGIN_LOW_4 bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[33] bit 6 GTX_CHANNEL: RX_DFE_H4_CFG bit 6	GTX_CHANNEL: DRP[33] bit 7 GTX_CHANNEL: RX_DFE_H4_CFG bit 7	GTX_CHANNEL: DRP[121] bit 6 GTX_CHANNEL: TX_MARGIN_LOW_3 bit 6	GTX_CHANNEL: DRP[121] bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[33] bit 4 GTX_CHANNEL: RX_DFE_H4_CFG bit 4	GTX_CHANNEL: DRP[33] bit 5 GTX_CHANNEL: RX_DFE_H4_CFG bit 5	GTX_CHANNEL: DRP[121] bit 4 GTX_CHANNEL: TX_MARGIN_LOW_3 bit 4	GTX_CHANNEL: DRP[121] bit 5 GTX_CHANNEL: TX_MARGIN_LOW_3 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[33] bit 2 GTX_CHANNEL: RX_DFE_H4_CFG bit 2	GTX_CHANNEL: DRP[33] bit 3 GTX_CHANNEL: RX_DFE_H4_CFG bit 3	GTX_CHANNEL: DRP[121] bit 2 GTX_CHANNEL: TX_MARGIN_LOW_3 bit 2	GTX_CHANNEL: DRP[121] bit 3 GTX_CHANNEL: TX_MARGIN_LOW_3 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[33] bit 0 GTX_CHANNEL: RX_DFE_H4_CFG bit 0	GTX_CHANNEL: DRP[33] bit 1 GTX_CHANNEL: RX_DFE_H4_CFG bit 1	GTX_CHANNEL: DRP[121] bit 0 GTX_CHANNEL: TX_MARGIN_LOW_3 bit 0	GTX_CHANNEL: DRP[121] bit 1 GTX_CHANNEL: TX_MARGIN_LOW_3 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[32] bit 14	GTX_CHANNEL: DRP[32] bit 15	GTX_CHANNEL: DRP[120] bit 14 GTX_CHANNEL: TX_MARGIN_LOW_2 bit 6	GTX_CHANNEL: DRP[120] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[32] bit 12	GTX_CHANNEL: DRP[32] bit 13	GTX_CHANNEL: DRP[120] bit 12 GTX_CHANNEL: TX_MARGIN_LOW_2 bit 4	GTX_CHANNEL: DRP[120] bit 13 GTX_CHANNEL: TX_MARGIN_LOW_2 bit 5
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[32] bit 10 GTX_CHANNEL: RX_DFE_H3_CFG bit 10	GTX_CHANNEL: DRP[32] bit 11 GTX_CHANNEL: RX_DFE_H3_CFG bit 11	GTX_CHANNEL: DRP[120] bit 10 GTX_CHANNEL: TX_MARGIN_LOW_2 bit 2	GTX_CHANNEL: DRP[120] bit 11 GTX_CHANNEL: TX_MARGIN_LOW_2 bit 3
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[32] bit 8 GTX_CHANNEL: RX_DFE_H3_CFG bit 8	GTX_CHANNEL: DRP[32] bit 9 GTX_CHANNEL: RX_DFE_H3_CFG bit 9	GTX_CHANNEL: DRP[120] bit 8 GTX_CHANNEL: TX_MARGIN_LOW_2 bit 0	GTX_CHANNEL: DRP[120] bit 9 GTX_CHANNEL: TX_MARGIN_LOW_2 bit 1
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[32] bit 6 GTX_CHANNEL: RX_DFE_H3_CFG bit 6	GTX_CHANNEL: DRP[32] bit 7 GTX_CHANNEL: RX_DFE_H3_CFG bit 7	GTX_CHANNEL: DRP[120] bit 6 GTX_CHANNEL: TX_MARGIN_LOW_1 bit 6	GTX_CHANNEL: DRP[120] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[32] bit 4 GTX_CHANNEL: RX_DFE_H3_CFG bit 4	GTX_CHANNEL: DRP[32] bit 5 GTX_CHANNEL: RX_DFE_H3_CFG bit 5	GTX_CHANNEL: DRP[120] bit 4 GTX_CHANNEL: TX_MARGIN_LOW_1 bit 4	GTX_CHANNEL: DRP[120] bit 5 GTX_CHANNEL: TX_MARGIN_LOW_1 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[32] bit 2 GTX_CHANNEL: RX_DFE_H3_CFG bit 2	GTX_CHANNEL: DRP[32] bit 3 GTX_CHANNEL: RX_DFE_H3_CFG bit 3	GTX_CHANNEL: DRP[120] bit 2 GTX_CHANNEL: TX_MARGIN_LOW_1 bit 2	GTX_CHANNEL: DRP[120] bit 3 GTX_CHANNEL: TX_MARGIN_LOW_1 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[32] bit 0 GTX_CHANNEL: RX_DFE_H3_CFG bit 0	GTX_CHANNEL: DRP[32] bit 1 GTX_CHANNEL: RX_DFE_H3_CFG bit 1	GTX_CHANNEL: DRP[120] bit 0 GTX_CHANNEL: TX_MARGIN_LOW_1 bit 0	GTX_CHANNEL: DRP[120] bit 1 GTX_CHANNEL: TX_MARGIN_LOW_1 bit 1

virtex7 GTH_CHANNEL rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[47] bit 14 GTX_CHANNEL: ES_QUALIFIER bit 62	GTX_CHANNEL: DRP[47] bit 15 GTX_CHANNEL: ES_QUALIFIER bit 63	GTX_CHANNEL: DRP[135] bit 14	GTX_CHANNEL: DRP[135] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[47] bit 12 GTX_CHANNEL: ES_QUALIFIER bit 60	GTX_CHANNEL: DRP[47] bit 13 GTX_CHANNEL: ES_QUALIFIER bit 61	GTX_CHANNEL: DRP[135] bit 12	GTX_CHANNEL: DRP[135] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[47] bit 10 GTX_CHANNEL: ES_QUALIFIER bit 58	GTX_CHANNEL: DRP[47] bit 11 GTX_CHANNEL: ES_QUALIFIER bit 59	GTX_CHANNEL: DRP[135] bit 10	GTX_CHANNEL: DRP[135] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[47] bit 8 GTX_CHANNEL: ES_QUALIFIER bit 56	GTX_CHANNEL: DRP[47] bit 9 GTX_CHANNEL: ES_QUALIFIER bit 57	GTX_CHANNEL: DRP[135] bit 8	GTX_CHANNEL: DRP[135] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[47] bit 6 GTX_CHANNEL: ES_QUALIFIER bit 54	GTX_CHANNEL: DRP[47] bit 7 GTX_CHANNEL: ES_QUALIFIER bit 55	GTX_CHANNEL: DRP[135] bit 6 GTX_CHANNEL: DMONITOR_CFG bit 22	GTX_CHANNEL: DRP[135] bit 7 GTX_CHANNEL: DMONITOR_CFG bit 23
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[47] bit 4 GTX_CHANNEL: ES_QUALIFIER bit 52	GTX_CHANNEL: DRP[47] bit 5 GTX_CHANNEL: ES_QUALIFIER bit 53	GTX_CHANNEL: DRP[135] bit 4 GTX_CHANNEL: DMONITOR_CFG bit 20	GTX_CHANNEL: DRP[135] bit 5 GTX_CHANNEL: DMONITOR_CFG bit 21
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[47] bit 2 GTX_CHANNEL: ES_QUALIFIER bit 50	GTX_CHANNEL: DRP[47] bit 3 GTX_CHANNEL: ES_QUALIFIER bit 51	GTX_CHANNEL: DRP[135] bit 2 GTX_CHANNEL: DMONITOR_CFG bit 18	GTX_CHANNEL: DRP[135] bit 3 GTX_CHANNEL: DMONITOR_CFG bit 19
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[47] bit 0 GTX_CHANNEL: ES_QUALIFIER bit 48	GTX_CHANNEL: DRP[47] bit 1 GTX_CHANNEL: ES_QUALIFIER bit 49	GTX_CHANNEL: DRP[135] bit 0 GTX_CHANNEL: DMONITOR_CFG bit 16	GTX_CHANNEL: DRP[135] bit 1 GTX_CHANNEL: DMONITOR_CFG bit 17
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[46] bit 14 GTX_CHANNEL: ES_QUALIFIER bit 46	GTX_CHANNEL: DRP[46] bit 15 GTX_CHANNEL: ES_QUALIFIER bit 47	GTX_CHANNEL: DRP[134] bit 14 GTX_CHANNEL: DMONITOR_CFG bit 14	GTX_CHANNEL: DRP[134] bit 15 GTX_CHANNEL: DMONITOR_CFG bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[46] bit 12 GTX_CHANNEL: ES_QUALIFIER bit 44	GTX_CHANNEL: DRP[46] bit 13 GTX_CHANNEL: ES_QUALIFIER bit 45	GTX_CHANNEL: DRP[134] bit 12 GTX_CHANNEL: DMONITOR_CFG bit 12	GTX_CHANNEL: DRP[134] bit 13 GTX_CHANNEL: DMONITOR_CFG bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[46] bit 10 GTX_CHANNEL: ES_QUALIFIER bit 42	GTX_CHANNEL: DRP[46] bit 11 GTX_CHANNEL: ES_QUALIFIER bit 43	GTX_CHANNEL: DRP[134] bit 10 GTX_CHANNEL: DMONITOR_CFG bit 10	GTX_CHANNEL: DRP[134] bit 11 GTX_CHANNEL: DMONITOR_CFG bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[46] bit 8 GTX_CHANNEL: ES_QUALIFIER bit 40	GTX_CHANNEL: DRP[46] bit 9 GTX_CHANNEL: ES_QUALIFIER bit 41	GTX_CHANNEL: DRP[134] bit 8 GTX_CHANNEL: DMONITOR_CFG bit 8	GTX_CHANNEL: DRP[134] bit 9 GTX_CHANNEL: DMONITOR_CFG bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[46] bit 6 GTX_CHANNEL: ES_QUALIFIER bit 38	GTX_CHANNEL: DRP[46] bit 7 GTX_CHANNEL: ES_QUALIFIER bit 39	GTX_CHANNEL: DRP[134] bit 6 GTX_CHANNEL: DMONITOR_CFG bit 6	GTX_CHANNEL: DRP[134] bit 7 GTX_CHANNEL: DMONITOR_CFG bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[46] bit 4 GTX_CHANNEL: ES_QUALIFIER bit 36	GTX_CHANNEL: DRP[46] bit 5 GTX_CHANNEL: ES_QUALIFIER bit 37	GTX_CHANNEL: DRP[134] bit 4 GTX_CHANNEL: DMONITOR_CFG bit 4	GTX_CHANNEL: DRP[134] bit 5 GTX_CHANNEL: DMONITOR_CFG bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[46] bit 2 GTX_CHANNEL: ES_QUALIFIER bit 34	GTX_CHANNEL: DRP[46] bit 3 GTX_CHANNEL: ES_QUALIFIER bit 35	GTX_CHANNEL: DRP[134] bit 2 GTX_CHANNEL: DMONITOR_CFG bit 2	GTX_CHANNEL: DRP[134] bit 3 GTX_CHANNEL: DMONITOR_CFG bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[46] bit 0 GTX_CHANNEL: ES_QUALIFIER bit 32	GTX_CHANNEL: DRP[46] bit 1 GTX_CHANNEL: ES_QUALIFIER bit 33	GTX_CHANNEL: DRP[134] bit 0 GTX_CHANNEL: DMONITOR_CFG bit 0	GTX_CHANNEL: DRP[134] bit 1 GTX_CHANNEL: DMONITOR_CFG bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[45] bit 14 GTX_CHANNEL: ES_QUALIFIER bit 30	GTX_CHANNEL: DRP[45] bit 15 GTX_CHANNEL: ES_QUALIFIER bit 31	GTX_CHANNEL: DRP[133] bit 14 GTX_CHANNEL: AMONITOR_CFG bit 14	GTX_CHANNEL: DRP[133] bit 15 GTX_CHANNEL: AMONITOR_CFG bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[45] bit 12 GTX_CHANNEL: ES_QUALIFIER bit 28	GTX_CHANNEL: DRP[45] bit 13 GTX_CHANNEL: ES_QUALIFIER bit 29	GTX_CHANNEL: DRP[133] bit 12 GTX_CHANNEL: AMONITOR_CFG bit 12	GTX_CHANNEL: DRP[133] bit 13 GTX_CHANNEL: AMONITOR_CFG bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[45] bit 10 GTX_CHANNEL: ES_QUALIFIER bit 26	GTX_CHANNEL: DRP[45] bit 11 GTX_CHANNEL: ES_QUALIFIER bit 27	GTX_CHANNEL: DRP[133] bit 10 GTX_CHANNEL: AMONITOR_CFG bit 10	GTX_CHANNEL: DRP[133] bit 11 GTX_CHANNEL: AMONITOR_CFG bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[45] bit 8 GTX_CHANNEL: ES_QUALIFIER bit 24	GTX_CHANNEL: DRP[45] bit 9 GTX_CHANNEL: ES_QUALIFIER bit 25	GTX_CHANNEL: DRP[133] bit 8 GTX_CHANNEL: AMONITOR_CFG bit 8	GTX_CHANNEL: DRP[133] bit 9 GTX_CHANNEL: AMONITOR_CFG bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[45] bit 6 GTX_CHANNEL: ES_QUALIFIER bit 22	GTX_CHANNEL: DRP[45] bit 7 GTX_CHANNEL: ES_QUALIFIER bit 23	GTX_CHANNEL: DRP[133] bit 6 GTX_CHANNEL: AMONITOR_CFG bit 6	GTX_CHANNEL: DRP[133] bit 7 GTX_CHANNEL: AMONITOR_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[45] bit 4 GTX_CHANNEL: ES_QUALIFIER bit 20	GTX_CHANNEL: DRP[45] bit 5 GTX_CHANNEL: ES_QUALIFIER bit 21	GTX_CHANNEL: DRP[133] bit 4 GTX_CHANNEL: AMONITOR_CFG bit 4	GTX_CHANNEL: DRP[133] bit 5 GTX_CHANNEL: AMONITOR_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[45] bit 2 GTX_CHANNEL: ES_QUALIFIER bit 18	GTX_CHANNEL: DRP[45] bit 3 GTX_CHANNEL: ES_QUALIFIER bit 19	GTX_CHANNEL: DRP[133] bit 2 GTX_CHANNEL: AMONITOR_CFG bit 2	GTX_CHANNEL: DRP[133] bit 3 GTX_CHANNEL: AMONITOR_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[45] bit 0 GTX_CHANNEL: ES_QUALIFIER bit 16	GTX_CHANNEL: DRP[45] bit 1 GTX_CHANNEL: ES_QUALIFIER bit 17	GTX_CHANNEL: DRP[133] bit 0 GTX_CHANNEL: AMONITOR_CFG bit 0	GTX_CHANNEL: DRP[133] bit 1 GTX_CHANNEL: AMONITOR_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[44] bit 14 GTX_CHANNEL: ES_QUALIFIER bit 14	GTX_CHANNEL: DRP[44] bit 15 GTX_CHANNEL: ES_QUALIFIER bit 15	GTX_CHANNEL: DRP[132] bit 14	GTX_CHANNEL: DRP[132] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[44] bit 12 GTX_CHANNEL: ES_QUALIFIER bit 12	GTX_CHANNEL: DRP[44] bit 13 GTX_CHANNEL: ES_QUALIFIER bit 13	GTX_CHANNEL: DRP[132] bit 12	GTX_CHANNEL: DRP[132] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[44] bit 10 GTX_CHANNEL: ES_QUALIFIER bit 10	GTX_CHANNEL: DRP[44] bit 11 GTX_CHANNEL: ES_QUALIFIER bit 11	GTX_CHANNEL: DRP[132] bit 10 GTX_CHANNEL: RESET_POWERSAVE_DISABLE bit 0	GTX_CHANNEL: DRP[132] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[44] bit 8 GTX_CHANNEL: ES_QUALIFIER bit 8	GTX_CHANNEL: DRP[44] bit 9 GTX_CHANNEL: ES_QUALIFIER bit 9	GTX_CHANNEL: DRP[132] bit 8 GTX_CHANNEL: PMA_POWER_SAVE bit 8	GTX_CHANNEL: DRP[132] bit 9 GTX_CHANNEL: PMA_POWER_SAVE bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[44] bit 6 GTX_CHANNEL: ES_QUALIFIER bit 6	GTX_CHANNEL: DRP[44] bit 7 GTX_CHANNEL: ES_QUALIFIER bit 7	GTX_CHANNEL: DRP[132] bit 6 GTX_CHANNEL: PMA_POWER_SAVE bit 6	GTX_CHANNEL: DRP[132] bit 7 GTX_CHANNEL: PMA_POWER_SAVE bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[44] bit 4 GTX_CHANNEL: ES_QUALIFIER bit 4	GTX_CHANNEL: DRP[44] bit 5 GTX_CHANNEL: ES_QUALIFIER bit 5	GTX_CHANNEL: DRP[132] bit 4 GTX_CHANNEL: PMA_POWER_SAVE bit 4	GTX_CHANNEL: DRP[132] bit 5 GTX_CHANNEL: PMA_POWER_SAVE bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[44] bit 2 GTX_CHANNEL: ES_QUALIFIER bit 2	GTX_CHANNEL: DRP[44] bit 3 GTX_CHANNEL: ES_QUALIFIER bit 3	GTX_CHANNEL: DRP[132] bit 2 GTX_CHANNEL: PMA_POWER_SAVE bit 2	GTX_CHANNEL: DRP[132] bit 3 GTX_CHANNEL: PMA_POWER_SAVE bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[44] bit 0 GTX_CHANNEL: ES_QUALIFIER bit 0	GTX_CHANNEL: DRP[44] bit 1 GTX_CHANNEL: ES_QUALIFIER bit 1	GTX_CHANNEL: DRP[132] bit 0 GTX_CHANNEL: PMA_POWER_SAVE bit 0	GTX_CHANNEL: DRP[132] bit 1 GTX_CHANNEL: PMA_POWER_SAVE bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[43] bit 14 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 14	GTX_CHANNEL: DRP[43] bit 15 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 15	GTX_CHANNEL: DRP[131] bit 14 GTX_CHANNEL: PMA_RSV2_GTH bit 30	GTX_CHANNEL: DRP[131] bit 15 GTX_CHANNEL: PMA_RSV2_GTH bit 31
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[43] bit 12 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 12	GTX_CHANNEL: DRP[43] bit 13 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 13	GTX_CHANNEL: DRP[131] bit 12 GTX_CHANNEL: PMA_RSV2_GTH bit 28	GTX_CHANNEL: DRP[131] bit 13 GTX_CHANNEL: PMA_RSV2_GTH bit 29
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[43] bit 10 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 10	GTX_CHANNEL: DRP[43] bit 11 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 11	GTX_CHANNEL: DRP[131] bit 10 GTX_CHANNEL: PMA_RSV2_GTH bit 26	GTX_CHANNEL: DRP[131] bit 11 GTX_CHANNEL: PMA_RSV2_GTH bit 27
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[43] bit 8 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 8	GTX_CHANNEL: DRP[43] bit 9 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 9	GTX_CHANNEL: DRP[131] bit 8 GTX_CHANNEL: PMA_RSV2_GTH bit 24	GTX_CHANNEL: DRP[131] bit 9 GTX_CHANNEL: PMA_RSV2_GTH bit 25
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[43] bit 6 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 6	GTX_CHANNEL: DRP[43] bit 7 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 7	GTX_CHANNEL: DRP[131] bit 6 GTX_CHANNEL: PMA_RSV2_GTH bit 22	GTX_CHANNEL: DRP[131] bit 7 GTX_CHANNEL: PMA_RSV2_GTH bit 23
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[43] bit 4 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 4	GTX_CHANNEL: DRP[43] bit 5 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 5	GTX_CHANNEL: DRP[131] bit 4 GTX_CHANNEL: PMA_RSV2_GTH bit 20	GTX_CHANNEL: DRP[131] bit 5 GTX_CHANNEL: PMA_RSV2_GTH bit 21
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[43] bit 2 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 2	GTX_CHANNEL: DRP[43] bit 3 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 3	GTX_CHANNEL: DRP[131] bit 2 GTX_CHANNEL: PMA_RSV2_GTH bit 18	GTX_CHANNEL: DRP[131] bit 3 GTX_CHANNEL: PMA_RSV2_GTH bit 19
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[43] bit 0 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 0	GTX_CHANNEL: DRP[43] bit 1 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 1	GTX_CHANNEL: DRP[131] bit 0 GTX_CHANNEL: PMA_RSV2_GTH bit 16	GTX_CHANNEL: DRP[131] bit 1 GTX_CHANNEL: PMA_RSV2_GTH bit 17
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[42] bit 14 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 16	GTX_CHANNEL: DRP[42] bit 15 GTX_CHANNEL: RXLPM_LF_CFG_GTH bit 17	GTX_CHANNEL: DRP[130] bit 14 GTX_CHANNEL: PMA_RSV2_GTH bit 14	GTX_CHANNEL: DRP[130] bit 15 GTX_CHANNEL: PMA_RSV2_GTH bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[42] bit 12 GTX_CHANNEL: RXLPM_HF_CFG bit 12	GTX_CHANNEL: DRP[42] bit 13 GTX_CHANNEL: RXLPM_HF_CFG bit 13	GTX_CHANNEL: DRP[130] bit 12 GTX_CHANNEL: PMA_RSV2_GTH bit 12	GTX_CHANNEL: DRP[130] bit 13 GTX_CHANNEL: PMA_RSV2_GTH bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[42] bit 10 GTX_CHANNEL: RXLPM_HF_CFG bit 10	GTX_CHANNEL: DRP[42] bit 11 GTX_CHANNEL: RXLPM_HF_CFG bit 11	GTX_CHANNEL: DRP[130] bit 10 GTX_CHANNEL: PMA_RSV2_GTH bit 10	GTX_CHANNEL: DRP[130] bit 11 GTX_CHANNEL: PMA_RSV2_GTH bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[42] bit 8 GTX_CHANNEL: RXLPM_HF_CFG bit 8	GTX_CHANNEL: DRP[42] bit 9 GTX_CHANNEL: RXLPM_HF_CFG bit 9	GTX_CHANNEL: DRP[130] bit 8 GTX_CHANNEL: PMA_RSV2_GTH bit 8	GTX_CHANNEL: DRP[130] bit 9 GTX_CHANNEL: PMA_RSV2_GTH bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[42] bit 6 GTX_CHANNEL: RXLPM_HF_CFG bit 6	GTX_CHANNEL: DRP[42] bit 7 GTX_CHANNEL: RXLPM_HF_CFG bit 7	GTX_CHANNEL: DRP[130] bit 6 GTX_CHANNEL: PMA_RSV2_GTH bit 6	GTX_CHANNEL: DRP[130] bit 7 GTX_CHANNEL: PMA_RSV2_GTH bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[42] bit 4 GTX_CHANNEL: RXLPM_HF_CFG bit 4	GTX_CHANNEL: DRP[42] bit 5 GTX_CHANNEL: RXLPM_HF_CFG bit 5	GTX_CHANNEL: DRP[130] bit 4 GTX_CHANNEL: PMA_RSV2_GTH bit 4	GTX_CHANNEL: DRP[130] bit 5 GTX_CHANNEL: PMA_RSV2_GTH bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[42] bit 2 GTX_CHANNEL: RXLPM_HF_CFG bit 2	GTX_CHANNEL: DRP[42] bit 3 GTX_CHANNEL: RXLPM_HF_CFG bit 3	GTX_CHANNEL: DRP[130] bit 2 GTX_CHANNEL: PMA_RSV2_GTH bit 2	GTX_CHANNEL: DRP[130] bit 3 GTX_CHANNEL: PMA_RSV2_GTH bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[42] bit 0 GTX_CHANNEL: RXLPM_HF_CFG bit 0	GTX_CHANNEL: DRP[42] bit 1 GTX_CHANNEL: RXLPM_HF_CFG bit 1	GTX_CHANNEL: DRP[130] bit 0 GTX_CHANNEL: PMA_RSV2_GTH bit 0	GTX_CHANNEL: DRP[130] bit 1 GTX_CHANNEL: PMA_RSV2_GTH bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[41] bit 14 GTX_CHANNEL: RX_DFE_LPM_CFG bit 14	GTX_CHANNEL: DRP[41] bit 15 GTX_CHANNEL: RX_DFE_LPM_CFG bit 15	GTX_CHANNEL: DRP[129] bit 14	GTX_CHANNEL: DRP[129] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[41] bit 12 GTX_CHANNEL: RX_DFE_LPM_CFG bit 12	GTX_CHANNEL: DRP[41] bit 13 GTX_CHANNEL: RX_DFE_LPM_CFG bit 13	GTX_CHANNEL: DRP[129] bit 12	GTX_CHANNEL: DRP[129] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[41] bit 10 GTX_CHANNEL: RX_DFE_LPM_CFG bit 10	GTX_CHANNEL: DRP[41] bit 11 GTX_CHANNEL: RX_DFE_LPM_CFG bit 11	GTX_CHANNEL: DRP[129] bit 10	GTX_CHANNEL: DRP[129] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[41] bit 8 GTX_CHANNEL: RX_DFE_LPM_CFG bit 8	GTX_CHANNEL: DRP[41] bit 9 GTX_CHANNEL: RX_DFE_LPM_CFG bit 9	GTX_CHANNEL: DRP[129] bit 8	GTX_CHANNEL: DRP[129] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[41] bit 6 GTX_CHANNEL: RX_DFE_LPM_CFG bit 6	GTX_CHANNEL: DRP[41] bit 7 GTX_CHANNEL: RX_DFE_LPM_CFG bit 7	GTX_CHANNEL: DRP[129] bit 6 GTX_CHANNEL: RX_DFE_KL_LPM_KL_OVRDEN bit 0	GTX_CHANNEL: DRP[129] bit 7 GTX_CHANNEL: RX_DFE_KL_LPM_KH_OVRDEN bit 0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[41] bit 4 GTX_CHANNEL: RX_DFE_LPM_CFG bit 4	GTX_CHANNEL: DRP[41] bit 5 GTX_CHANNEL: RX_DFE_LPM_CFG bit 5	GTX_CHANNEL: DRP[129] bit 4 GTX_CHANNEL: RX_DFELPM_CFG1 bit 0	GTX_CHANNEL: DRP[129] bit 5 GTX_CHANNEL: RX_DFE_AGC_OVRDEN bit 0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[41] bit 2 GTX_CHANNEL: RX_DFE_LPM_CFG bit 2	GTX_CHANNEL: DRP[41] bit 3 GTX_CHANNEL: RX_DFE_LPM_CFG bit 3	GTX_CHANNEL: DRP[129] bit 2 GTX_CHANNEL: RX_DFELPM_CFG0 bit 2	GTX_CHANNEL: DRP[129] bit 3 GTX_CHANNEL: RX_DFELPM_CFG0 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[41] bit 0 GTX_CHANNEL: RX_DFE_LPM_CFG bit 0	GTX_CHANNEL: DRP[41] bit 1 GTX_CHANNEL: RX_DFE_LPM_CFG bit 1	GTX_CHANNEL: DRP[129] bit 0 GTX_CHANNEL: RX_DFELPM_CFG0 bit 0	GTX_CHANNEL: DRP[129] bit 1 GTX_CHANNEL: RX_DFELPM_CFG0 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[40] bit 14	GTX_CHANNEL: DRP[40] bit 15	GTX_CHANNEL: DRP[128] bit 14	GTX_CHANNEL: DRP[128] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[40] bit 12	GTX_CHANNEL: DRP[40] bit 13	GTX_CHANNEL: DRP[128] bit 12 GTX_CHANNEL: CPLL_CFG_GTH bit 28	GTX_CHANNEL: DRP[128] bit 13 GTX_CHANNEL: RX_DFELPM_KLKH_AGC_STUP_EN bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[40] bit 10	GTX_CHANNEL: DRP[40] bit 11	GTX_CHANNEL: DRP[128] bit 10 GTX_CHANNEL: CPLL_CFG_GTH bit 26	GTX_CHANNEL: DRP[128] bit 11 GTX_CHANNEL: CPLL_CFG_GTH bit 27
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[40] bit 8	GTX_CHANNEL: DRP[40] bit 9	GTX_CHANNEL: DRP[128] bit 8 GTX_CHANNEL: CPLL_CFG_GTH bit 24	GTX_CHANNEL: DRP[128] bit 9 GTX_CHANNEL: CPLL_CFG_GTH bit 25
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[40] bit 6	GTX_CHANNEL: DRP[40] bit 7	GTX_CHANNEL: DRP[128] bit 6 GTX_CHANNEL: CPLL_CFG_GTH bit 22	GTX_CHANNEL: DRP[128] bit 7 GTX_CHANNEL: CPLL_CFG_GTH bit 23
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[40] bit 4	GTX_CHANNEL: DRP[40] bit 5	GTX_CHANNEL: DRP[128] bit 4 GTX_CHANNEL: CPLL_CFG_GTH bit 20	GTX_CHANNEL: DRP[128] bit 5 GTX_CHANNEL: CPLL_CFG_GTH bit 21
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[40] bit 2	GTX_CHANNEL: DRP[40] bit 3	GTX_CHANNEL: DRP[128] bit 2 GTX_CHANNEL: CPLL_CFG_GTH bit 18	GTX_CHANNEL: DRP[128] bit 3 GTX_CHANNEL: CPLL_CFG_GTH bit 19
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[40] bit 0	GTX_CHANNEL: DRP[40] bit 1	GTX_CHANNEL: DRP[128] bit 0 GTX_CHANNEL: CPLL_CFG_GTH bit 16	GTX_CHANNEL: DRP[128] bit 1 GTX_CHANNEL: CPLL_CFG_GTH bit 17

virtex7 GTH_CHANNEL rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[55] bit 14 GTX_CHANNEL: ES_SDATA_MASK bit 30	GTX_CHANNEL: DRP[55] bit 15 GTX_CHANNEL: ES_SDATA_MASK bit 31	GTX_CHANNEL: DRP[143] bit 14 GTX_CHANNEL: RX_DFE_ST_CFG bit 30	GTX_CHANNEL: DRP[143] bit 15 GTX_CHANNEL: RX_DFE_ST_CFG bit 31
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[55] bit 12 GTX_CHANNEL: ES_SDATA_MASK bit 28	GTX_CHANNEL: DRP[55] bit 13 GTX_CHANNEL: ES_SDATA_MASK bit 29	GTX_CHANNEL: DRP[143] bit 12 GTX_CHANNEL: RX_DFE_ST_CFG bit 28	GTX_CHANNEL: DRP[143] bit 13 GTX_CHANNEL: RX_DFE_ST_CFG bit 29
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[55] bit 10 GTX_CHANNEL: ES_SDATA_MASK bit 26	GTX_CHANNEL: DRP[55] bit 11 GTX_CHANNEL: ES_SDATA_MASK bit 27	GTX_CHANNEL: DRP[143] bit 10 GTX_CHANNEL: RX_DFE_ST_CFG bit 26	GTX_CHANNEL: DRP[143] bit 11 GTX_CHANNEL: RX_DFE_ST_CFG bit 27
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[55] bit 8 GTX_CHANNEL: ES_SDATA_MASK bit 24	GTX_CHANNEL: DRP[55] bit 9 GTX_CHANNEL: ES_SDATA_MASK bit 25	GTX_CHANNEL: DRP[143] bit 8 GTX_CHANNEL: RX_DFE_ST_CFG bit 24	GTX_CHANNEL: DRP[143] bit 9 GTX_CHANNEL: RX_DFE_ST_CFG bit 25
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[55] bit 6 GTX_CHANNEL: ES_SDATA_MASK bit 22	GTX_CHANNEL: DRP[55] bit 7 GTX_CHANNEL: ES_SDATA_MASK bit 23	GTX_CHANNEL: DRP[143] bit 6 GTX_CHANNEL: RX_DFE_ST_CFG bit 22	GTX_CHANNEL: DRP[143] bit 7 GTX_CHANNEL: RX_DFE_ST_CFG bit 23
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[55] bit 4 GTX_CHANNEL: ES_SDATA_MASK bit 20	GTX_CHANNEL: DRP[55] bit 5 GTX_CHANNEL: ES_SDATA_MASK bit 21	GTX_CHANNEL: DRP[143] bit 4 GTX_CHANNEL: RX_DFE_ST_CFG bit 20	GTX_CHANNEL: DRP[143] bit 5 GTX_CHANNEL: RX_DFE_ST_CFG bit 21
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[55] bit 2 GTX_CHANNEL: ES_SDATA_MASK bit 18	GTX_CHANNEL: DRP[55] bit 3 GTX_CHANNEL: ES_SDATA_MASK bit 19	GTX_CHANNEL: DRP[143] bit 2 GTX_CHANNEL: RX_DFE_ST_CFG bit 18	GTX_CHANNEL: DRP[143] bit 3 GTX_CHANNEL: RX_DFE_ST_CFG bit 19
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[55] bit 0 GTX_CHANNEL: ES_SDATA_MASK bit 16	GTX_CHANNEL: DRP[55] bit 1 GTX_CHANNEL: ES_SDATA_MASK bit 17	GTX_CHANNEL: DRP[143] bit 0 GTX_CHANNEL: RX_DFE_ST_CFG bit 16	GTX_CHANNEL: DRP[143] bit 1 GTX_CHANNEL: RX_DFE_ST_CFG bit 17
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[54] bit 14 GTX_CHANNEL: ES_SDATA_MASK bit 14	GTX_CHANNEL: DRP[54] bit 15 GTX_CHANNEL: ES_SDATA_MASK bit 15	GTX_CHANNEL: DRP[142] bit 14 GTX_CHANNEL: RX_DFE_ST_CFG bit 14	GTX_CHANNEL: DRP[142] bit 15 GTX_CHANNEL: RX_DFE_ST_CFG bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[54] bit 12 GTX_CHANNEL: ES_SDATA_MASK bit 12	GTX_CHANNEL: DRP[54] bit 13 GTX_CHANNEL: ES_SDATA_MASK bit 13	GTX_CHANNEL: DRP[142] bit 12 GTX_CHANNEL: RX_DFE_ST_CFG bit 12	GTX_CHANNEL: DRP[142] bit 13 GTX_CHANNEL: RX_DFE_ST_CFG bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[54] bit 10 GTX_CHANNEL: ES_SDATA_MASK bit 10	GTX_CHANNEL: DRP[54] bit 11 GTX_CHANNEL: ES_SDATA_MASK bit 11	GTX_CHANNEL: DRP[142] bit 10 GTX_CHANNEL: RX_DFE_ST_CFG bit 10	GTX_CHANNEL: DRP[142] bit 11 GTX_CHANNEL: RX_DFE_ST_CFG bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[54] bit 8 GTX_CHANNEL: ES_SDATA_MASK bit 8	GTX_CHANNEL: DRP[54] bit 9 GTX_CHANNEL: ES_SDATA_MASK bit 9	GTX_CHANNEL: DRP[142] bit 8 GTX_CHANNEL: RX_DFE_ST_CFG bit 8	GTX_CHANNEL: DRP[142] bit 9 GTX_CHANNEL: RX_DFE_ST_CFG bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[54] bit 6 GTX_CHANNEL: ES_SDATA_MASK bit 6	GTX_CHANNEL: DRP[54] bit 7 GTX_CHANNEL: ES_SDATA_MASK bit 7	GTX_CHANNEL: DRP[142] bit 6 GTX_CHANNEL: RX_DFE_ST_CFG bit 6	GTX_CHANNEL: DRP[142] bit 7 GTX_CHANNEL: RX_DFE_ST_CFG bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[54] bit 4 GTX_CHANNEL: ES_SDATA_MASK bit 4	GTX_CHANNEL: DRP[54] bit 5 GTX_CHANNEL: ES_SDATA_MASK bit 5	GTX_CHANNEL: DRP[142] bit 4 GTX_CHANNEL: RX_DFE_ST_CFG bit 4	GTX_CHANNEL: DRP[142] bit 5 GTX_CHANNEL: RX_DFE_ST_CFG bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[54] bit 2 GTX_CHANNEL: ES_SDATA_MASK bit 2	GTX_CHANNEL: DRP[54] bit 3 GTX_CHANNEL: ES_SDATA_MASK bit 3	GTX_CHANNEL: DRP[142] bit 2 GTX_CHANNEL: RX_DFE_ST_CFG bit 2	GTX_CHANNEL: DRP[142] bit 3 GTX_CHANNEL: RX_DFE_ST_CFG bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[54] bit 0 GTX_CHANNEL: ES_SDATA_MASK bit 0	GTX_CHANNEL: DRP[54] bit 1 GTX_CHANNEL: ES_SDATA_MASK bit 1	GTX_CHANNEL: DRP[142] bit 0 GTX_CHANNEL: RX_DFE_ST_CFG bit 0	GTX_CHANNEL: DRP[142] bit 1 GTX_CHANNEL: RX_DFE_ST_CFG bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[53] bit 14 GTX_CHANNEL: ES_QUAL_MASK bit 78	GTX_CHANNEL: DRP[53] bit 15 GTX_CHANNEL: ES_QUAL_MASK bit 79	GTX_CHANNEL: DRP[141] bit 14	GTX_CHANNEL: DRP[141] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[53] bit 12 GTX_CHANNEL: ES_QUAL_MASK bit 76	GTX_CHANNEL: DRP[53] bit 13 GTX_CHANNEL: ES_QUAL_MASK bit 77	GTX_CHANNEL: DRP[141] bit 12	GTX_CHANNEL: DRP[141] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[53] bit 10 GTX_CHANNEL: ES_QUAL_MASK bit 74	GTX_CHANNEL: DRP[53] bit 11 GTX_CHANNEL: ES_QUAL_MASK bit 75	GTX_CHANNEL: DRP[141] bit 10 GTX_CHANNEL: RX_DFE_H7_CFG bit 10	GTX_CHANNEL: DRP[141] bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[53] bit 8 GTX_CHANNEL: ES_QUAL_MASK bit 72	GTX_CHANNEL: DRP[53] bit 9 GTX_CHANNEL: ES_QUAL_MASK bit 73	GTX_CHANNEL: DRP[141] bit 8 GTX_CHANNEL: RX_DFE_H7_CFG bit 8	GTX_CHANNEL: DRP[141] bit 9 GTX_CHANNEL: RX_DFE_H7_CFG bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[53] bit 6 GTX_CHANNEL: ES_QUAL_MASK bit 70	GTX_CHANNEL: DRP[53] bit 7 GTX_CHANNEL: ES_QUAL_MASK bit 71	GTX_CHANNEL: DRP[141] bit 6 GTX_CHANNEL: RX_DFE_H7_CFG bit 6	GTX_CHANNEL: DRP[141] bit 7 GTX_CHANNEL: RX_DFE_H7_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[53] bit 4 GTX_CHANNEL: ES_QUAL_MASK bit 68	GTX_CHANNEL: DRP[53] bit 5 GTX_CHANNEL: ES_QUAL_MASK bit 69	GTX_CHANNEL: DRP[141] bit 4 GTX_CHANNEL: RX_DFE_H7_CFG bit 4	GTX_CHANNEL: DRP[141] bit 5 GTX_CHANNEL: RX_DFE_H7_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[53] bit 2 GTX_CHANNEL: ES_QUAL_MASK bit 66	GTX_CHANNEL: DRP[53] bit 3 GTX_CHANNEL: ES_QUAL_MASK bit 67	GTX_CHANNEL: DRP[141] bit 2 GTX_CHANNEL: RX_DFE_H7_CFG bit 2	GTX_CHANNEL: DRP[141] bit 3 GTX_CHANNEL: RX_DFE_H7_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[53] bit 0 GTX_CHANNEL: ES_QUAL_MASK bit 64	GTX_CHANNEL: DRP[53] bit 1 GTX_CHANNEL: ES_QUAL_MASK bit 65	GTX_CHANNEL: DRP[141] bit 0 GTX_CHANNEL: RX_DFE_H7_CFG bit 0	GTX_CHANNEL: DRP[141] bit 1 GTX_CHANNEL: RX_DFE_H7_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[52] bit 14 GTX_CHANNEL: ES_QUAL_MASK bit 62	GTX_CHANNEL: DRP[52] bit 15 GTX_CHANNEL: ES_QUAL_MASK bit 63	GTX_CHANNEL: DRP[140] bit 14	GTX_CHANNEL: DRP[140] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[52] bit 12 GTX_CHANNEL: ES_QUAL_MASK bit 60	GTX_CHANNEL: DRP[52] bit 13 GTX_CHANNEL: ES_QUAL_MASK bit 61	GTX_CHANNEL: DRP[140] bit 12	GTX_CHANNEL: DRP[140] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[52] bit 10 GTX_CHANNEL: ES_QUAL_MASK bit 58	GTX_CHANNEL: DRP[52] bit 11 GTX_CHANNEL: ES_QUAL_MASK bit 59	GTX_CHANNEL: DRP[140] bit 10 GTX_CHANNEL: RX_DFE_H6_CFG bit 10	GTX_CHANNEL: DRP[140] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[52] bit 8 GTX_CHANNEL: ES_QUAL_MASK bit 56	GTX_CHANNEL: DRP[52] bit 9 GTX_CHANNEL: ES_QUAL_MASK bit 57	GTX_CHANNEL: DRP[140] bit 8 GTX_CHANNEL: RX_DFE_H6_CFG bit 8	GTX_CHANNEL: DRP[140] bit 9 GTX_CHANNEL: RX_DFE_H6_CFG bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[52] bit 6 GTX_CHANNEL: ES_QUAL_MASK bit 54	GTX_CHANNEL: DRP[52] bit 7 GTX_CHANNEL: ES_QUAL_MASK bit 55	GTX_CHANNEL: DRP[140] bit 6 GTX_CHANNEL: RX_DFE_H6_CFG bit 6	GTX_CHANNEL: DRP[140] bit 7 GTX_CHANNEL: RX_DFE_H6_CFG bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[52] bit 4 GTX_CHANNEL: ES_QUAL_MASK bit 52	GTX_CHANNEL: DRP[52] bit 5 GTX_CHANNEL: ES_QUAL_MASK bit 53	GTX_CHANNEL: DRP[140] bit 4 GTX_CHANNEL: RX_DFE_H6_CFG bit 4	GTX_CHANNEL: DRP[140] bit 5 GTX_CHANNEL: RX_DFE_H6_CFG bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[52] bit 2 GTX_CHANNEL: ES_QUAL_MASK bit 50	GTX_CHANNEL: DRP[52] bit 3 GTX_CHANNEL: ES_QUAL_MASK bit 51	GTX_CHANNEL: DRP[140] bit 2 GTX_CHANNEL: RX_DFE_H6_CFG bit 2	GTX_CHANNEL: DRP[140] bit 3 GTX_CHANNEL: RX_DFE_H6_CFG bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[52] bit 0 GTX_CHANNEL: ES_QUAL_MASK bit 48	GTX_CHANNEL: DRP[52] bit 1 GTX_CHANNEL: ES_QUAL_MASK bit 49	GTX_CHANNEL: DRP[140] bit 0 GTX_CHANNEL: RX_DFE_H6_CFG bit 0	GTX_CHANNEL: DRP[140] bit 1 GTX_CHANNEL: RX_DFE_H6_CFG bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[51] bit 14 GTX_CHANNEL: ES_QUAL_MASK bit 46	GTX_CHANNEL: DRP[51] bit 15 GTX_CHANNEL: ES_QUAL_MASK bit 47	GTX_CHANNEL: DRP[139] bit 14 GTX_CHANNEL: CFOK_CFG3 bit 4	GTX_CHANNEL: DRP[139] bit 15 GTX_CHANNEL: CFOK_CFG3 bit 5
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[51] bit 12 GTX_CHANNEL: ES_QUAL_MASK bit 44	GTX_CHANNEL: DRP[51] bit 13 GTX_CHANNEL: ES_QUAL_MASK bit 45	GTX_CHANNEL: DRP[139] bit 12 GTX_CHANNEL: CFOK_CFG3 bit 2	GTX_CHANNEL: DRP[139] bit 13 GTX_CHANNEL: CFOK_CFG3 bit 3
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[51] bit 10 GTX_CHANNEL: ES_QUAL_MASK bit 42	GTX_CHANNEL: DRP[51] bit 11 GTX_CHANNEL: ES_QUAL_MASK bit 43	GTX_CHANNEL: DRP[139] bit 10 GTX_CHANNEL: CFOK_CFG3 bit 0	GTX_CHANNEL: DRP[139] bit 11 GTX_CHANNEL: CFOK_CFG3 bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[51] bit 8 GTX_CHANNEL: ES_QUAL_MASK bit 40	GTX_CHANNEL: DRP[51] bit 9 GTX_CHANNEL: ES_QUAL_MASK bit 41	GTX_CHANNEL: DRP[139] bit 8 GTX_CHANNEL: CFOK_CFG bit 40	GTX_CHANNEL: DRP[139] bit 9 GTX_CHANNEL: CFOK_CFG bit 41
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[51] bit 6 GTX_CHANNEL: ES_QUAL_MASK bit 38	GTX_CHANNEL: DRP[51] bit 7 GTX_CHANNEL: ES_QUAL_MASK bit 39	GTX_CHANNEL: DRP[139] bit 6 GTX_CHANNEL: CFOK_CFG bit 38	GTX_CHANNEL: DRP[139] bit 7 GTX_CHANNEL: CFOK_CFG bit 39
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[51] bit 4 GTX_CHANNEL: ES_QUAL_MASK bit 36	GTX_CHANNEL: DRP[51] bit 5 GTX_CHANNEL: ES_QUAL_MASK bit 37	GTX_CHANNEL: DRP[139] bit 4 GTX_CHANNEL: CFOK_CFG bit 36	GTX_CHANNEL: DRP[139] bit 5 GTX_CHANNEL: CFOK_CFG bit 37
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[51] bit 2 GTX_CHANNEL: ES_QUAL_MASK bit 34	GTX_CHANNEL: DRP[51] bit 3 GTX_CHANNEL: ES_QUAL_MASK bit 35	GTX_CHANNEL: DRP[139] bit 2 GTX_CHANNEL: CFOK_CFG bit 34	GTX_CHANNEL: DRP[139] bit 3 GTX_CHANNEL: CFOK_CFG bit 35
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[51] bit 0 GTX_CHANNEL: ES_QUAL_MASK bit 32	GTX_CHANNEL: DRP[51] bit 1 GTX_CHANNEL: ES_QUAL_MASK bit 33	GTX_CHANNEL: DRP[139] bit 0 GTX_CHANNEL: CFOK_CFG bit 32	GTX_CHANNEL: DRP[139] bit 1 GTX_CHANNEL: CFOK_CFG bit 33
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[50] bit 14 GTX_CHANNEL: ES_QUAL_MASK bit 30	GTX_CHANNEL: DRP[50] bit 15 GTX_CHANNEL: ES_QUAL_MASK bit 31	GTX_CHANNEL: DRP[138] bit 14 GTX_CHANNEL: CFOK_CFG bit 30	GTX_CHANNEL: DRP[138] bit 15 GTX_CHANNEL: CFOK_CFG bit 31
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[50] bit 12 GTX_CHANNEL: ES_QUAL_MASK bit 28	GTX_CHANNEL: DRP[50] bit 13 GTX_CHANNEL: ES_QUAL_MASK bit 29	GTX_CHANNEL: DRP[138] bit 12 GTX_CHANNEL: CFOK_CFG bit 28	GTX_CHANNEL: DRP[138] bit 13 GTX_CHANNEL: CFOK_CFG bit 29
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[50] bit 10 GTX_CHANNEL: ES_QUAL_MASK bit 26	GTX_CHANNEL: DRP[50] bit 11 GTX_CHANNEL: ES_QUAL_MASK bit 27	GTX_CHANNEL: DRP[138] bit 10 GTX_CHANNEL: CFOK_CFG bit 26	GTX_CHANNEL: DRP[138] bit 11 GTX_CHANNEL: CFOK_CFG bit 27
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[50] bit 8 GTX_CHANNEL: ES_QUAL_MASK bit 24	GTX_CHANNEL: DRP[50] bit 9 GTX_CHANNEL: ES_QUAL_MASK bit 25	GTX_CHANNEL: DRP[138] bit 8 GTX_CHANNEL: CFOK_CFG bit 24	GTX_CHANNEL: DRP[138] bit 9 GTX_CHANNEL: CFOK_CFG bit 25
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[50] bit 6 GTX_CHANNEL: ES_QUAL_MASK bit 22	GTX_CHANNEL: DRP[50] bit 7 GTX_CHANNEL: ES_QUAL_MASK bit 23	GTX_CHANNEL: DRP[138] bit 6 GTX_CHANNEL: CFOK_CFG bit 22	GTX_CHANNEL: DRP[138] bit 7 GTX_CHANNEL: CFOK_CFG bit 23
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[50] bit 4 GTX_CHANNEL: ES_QUAL_MASK bit 20	GTX_CHANNEL: DRP[50] bit 5 GTX_CHANNEL: ES_QUAL_MASK bit 21	GTX_CHANNEL: DRP[138] bit 4 GTX_CHANNEL: CFOK_CFG bit 20	GTX_CHANNEL: DRP[138] bit 5 GTX_CHANNEL: CFOK_CFG bit 21
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[50] bit 2 GTX_CHANNEL: ES_QUAL_MASK bit 18	GTX_CHANNEL: DRP[50] bit 3 GTX_CHANNEL: ES_QUAL_MASK bit 19	GTX_CHANNEL: DRP[138] bit 2 GTX_CHANNEL: CFOK_CFG bit 18	GTX_CHANNEL: DRP[138] bit 3 GTX_CHANNEL: CFOK_CFG bit 19
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[50] bit 0 GTX_CHANNEL: ES_QUAL_MASK bit 16	GTX_CHANNEL: DRP[50] bit 1 GTX_CHANNEL: ES_QUAL_MASK bit 17	GTX_CHANNEL: DRP[138] bit 0 GTX_CHANNEL: CFOK_CFG bit 16	GTX_CHANNEL: DRP[138] bit 1 GTX_CHANNEL: CFOK_CFG bit 17
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[49] bit 14 GTX_CHANNEL: ES_QUAL_MASK bit 14	GTX_CHANNEL: DRP[49] bit 15 GTX_CHANNEL: ES_QUAL_MASK bit 15	GTX_CHANNEL: DRP[137] bit 14 GTX_CHANNEL: CFOK_CFG bit 14	GTX_CHANNEL: DRP[137] bit 15 GTX_CHANNEL: CFOK_CFG bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[49] bit 12 GTX_CHANNEL: ES_QUAL_MASK bit 12	GTX_CHANNEL: DRP[49] bit 13 GTX_CHANNEL: ES_QUAL_MASK bit 13	GTX_CHANNEL: DRP[137] bit 12 GTX_CHANNEL: CFOK_CFG bit 12	GTX_CHANNEL: DRP[137] bit 13 GTX_CHANNEL: CFOK_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[49] bit 10 GTX_CHANNEL: ES_QUAL_MASK bit 10	GTX_CHANNEL: DRP[49] bit 11 GTX_CHANNEL: ES_QUAL_MASK bit 11	GTX_CHANNEL: DRP[137] bit 10 GTX_CHANNEL: CFOK_CFG bit 10	GTX_CHANNEL: DRP[137] bit 11 GTX_CHANNEL: CFOK_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[49] bit 8 GTX_CHANNEL: ES_QUAL_MASK bit 8	GTX_CHANNEL: DRP[49] bit 9 GTX_CHANNEL: ES_QUAL_MASK bit 9	GTX_CHANNEL: DRP[137] bit 8 GTX_CHANNEL: CFOK_CFG bit 8	GTX_CHANNEL: DRP[137] bit 9 GTX_CHANNEL: CFOK_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[49] bit 6 GTX_CHANNEL: ES_QUAL_MASK bit 6	GTX_CHANNEL: DRP[49] bit 7 GTX_CHANNEL: ES_QUAL_MASK bit 7	GTX_CHANNEL: DRP[137] bit 6 GTX_CHANNEL: CFOK_CFG bit 6	GTX_CHANNEL: DRP[137] bit 7 GTX_CHANNEL: CFOK_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[49] bit 4 GTX_CHANNEL: ES_QUAL_MASK bit 4	GTX_CHANNEL: DRP[49] bit 5 GTX_CHANNEL: ES_QUAL_MASK bit 5	GTX_CHANNEL: DRP[137] bit 4 GTX_CHANNEL: CFOK_CFG bit 4	GTX_CHANNEL: DRP[137] bit 5 GTX_CHANNEL: CFOK_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[49] bit 2 GTX_CHANNEL: ES_QUAL_MASK bit 2	GTX_CHANNEL: DRP[49] bit 3 GTX_CHANNEL: ES_QUAL_MASK bit 3	GTX_CHANNEL: DRP[137] bit 2 GTX_CHANNEL: CFOK_CFG bit 2	GTX_CHANNEL: DRP[137] bit 3 GTX_CHANNEL: CFOK_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[49] bit 0 GTX_CHANNEL: ES_QUAL_MASK bit 0	GTX_CHANNEL: DRP[49] bit 1 GTX_CHANNEL: ES_QUAL_MASK bit 1	GTX_CHANNEL: DRP[137] bit 0 GTX_CHANNEL: CFOK_CFG bit 0	GTX_CHANNEL: DRP[137] bit 1 GTX_CHANNEL: CFOK_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[48] bit 14 GTX_CHANNEL: ES_QUALIFIER bit 78	GTX_CHANNEL: DRP[48] bit 15 GTX_CHANNEL: ES_QUALIFIER bit 79	GTX_CHANNEL: DRP[136] bit 14	GTX_CHANNEL: DRP[136] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[48] bit 12 GTX_CHANNEL: ES_QUALIFIER bit 76	GTX_CHANNEL: DRP[48] bit 13 GTX_CHANNEL: ES_QUALIFIER bit 77	GTX_CHANNEL: DRP[136] bit 12	GTX_CHANNEL: DRP[136] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[48] bit 10 GTX_CHANNEL: ES_QUALIFIER bit 74	GTX_CHANNEL: DRP[48] bit 11 GTX_CHANNEL: ES_QUALIFIER bit 75	GTX_CHANNEL: DRP[136] bit 10	GTX_CHANNEL: DRP[136] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[48] bit 8 GTX_CHANNEL: ES_QUALIFIER bit 72	GTX_CHANNEL: DRP[48] bit 9 GTX_CHANNEL: ES_QUALIFIER bit 73	GTX_CHANNEL: DRP[136] bit 8	GTX_CHANNEL: DRP[136] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[48] bit 6 GTX_CHANNEL: ES_QUALIFIER bit 70	GTX_CHANNEL: DRP[48] bit 7 GTX_CHANNEL: ES_QUALIFIER bit 71	GTX_CHANNEL: DRP[136] bit 6 GTX_CHANNEL: TXOUT_DIV bit 2	GTX_CHANNEL: DRP[136] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[48] bit 4 GTX_CHANNEL: ES_QUALIFIER bit 68	GTX_CHANNEL: DRP[48] bit 5 GTX_CHANNEL: ES_QUALIFIER bit 69	GTX_CHANNEL: DRP[136] bit 4 GTX_CHANNEL: TXOUT_DIV bit 0	GTX_CHANNEL: DRP[136] bit 5 GTX_CHANNEL: TXOUT_DIV bit 1
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[48] bit 2 GTX_CHANNEL: ES_QUALIFIER bit 66	GTX_CHANNEL: DRP[48] bit 3 GTX_CHANNEL: ES_QUALIFIER bit 67	GTX_CHANNEL: DRP[136] bit 2 GTX_CHANNEL: RXOUT_DIV bit 2	GTX_CHANNEL: DRP[136] bit 3 GTX_CHANNEL: RXSIPO_DIV_45 bit 0
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[48] bit 0 GTX_CHANNEL: ES_QUALIFIER bit 64	GTX_CHANNEL: DRP[48] bit 1 GTX_CHANNEL: ES_QUALIFIER bit 65	GTX_CHANNEL: DRP[136] bit 0 GTX_CHANNEL: RXOUT_DIV bit 0	GTX_CHANNEL: DRP[136] bit 1 GTX_CHANNEL: RXOUT_DIV bit 1

virtex7 GTH_CHANNEL rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[63] bit 14	GTX_CHANNEL: DRP[63] bit 15	GTX_CHANNEL: DRP[151] bit 14 GTX_CHANNEL: TST_RSV bit 14	GTX_CHANNEL: DRP[151] bit 15 GTX_CHANNEL: TST_RSV bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[63] bit 12	GTX_CHANNEL: DRP[63] bit 13	GTX_CHANNEL: DRP[151] bit 12 GTX_CHANNEL: TST_RSV bit 12	GTX_CHANNEL: DRP[151] bit 13 GTX_CHANNEL: TST_RSV bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[63] bit 10	GTX_CHANNEL: DRP[63] bit 11	GTX_CHANNEL: DRP[151] bit 10 GTX_CHANNEL: TST_RSV bit 10	GTX_CHANNEL: DRP[151] bit 11 GTX_CHANNEL: TST_RSV bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[63] bit 8 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 8	GTX_CHANNEL: DRP[63] bit 9 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 9	GTX_CHANNEL: DRP[151] bit 8 GTX_CHANNEL: TST_RSV bit 8	GTX_CHANNEL: DRP[151] bit 9 GTX_CHANNEL: TST_RSV bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[63] bit 6 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 6	GTX_CHANNEL: DRP[63] bit 7 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 7	GTX_CHANNEL: DRP[151] bit 6 GTX_CHANNEL: TST_RSV bit 6	GTX_CHANNEL: DRP[151] bit 7 GTX_CHANNEL: TST_RSV bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[63] bit 4 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 4	GTX_CHANNEL: DRP[63] bit 5 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 5	GTX_CHANNEL: DRP[151] bit 4 GTX_CHANNEL: TST_RSV bit 4	GTX_CHANNEL: DRP[151] bit 5 GTX_CHANNEL: TST_RSV bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[63] bit 2 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 2	GTX_CHANNEL: DRP[63] bit 3 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 3	GTX_CHANNEL: DRP[151] bit 2 GTX_CHANNEL: TST_RSV bit 2	GTX_CHANNEL: DRP[151] bit 3 GTX_CHANNEL: TST_RSV bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[63] bit 0 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 0	GTX_CHANNEL: DRP[63] bit 1 GTX_CHANNEL: ALIGN_MCOMMA_VALUE bit 1	GTX_CHANNEL: DRP[151] bit 0 GTX_CHANNEL: TST_RSV bit 0	GTX_CHANNEL: DRP[151] bit 1 GTX_CHANNEL: TST_RSV bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[62] bit 14	GTX_CHANNEL: DRP[62] bit 15	GTX_CHANNEL: DRP[150] bit 14	GTX_CHANNEL: DRP[150] bit 15 GTX_CHANNEL: A_TXPIPPMPD bit 0
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[62] bit 12	GTX_CHANNEL: DRP[62] bit 13	GTX_CHANNEL: DRP[150] bit 12	GTX_CHANNEL: DRP[150] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[62] bit 10	GTX_CHANNEL: DRP[62] bit 11	GTX_CHANNEL: DRP[150] bit 10	GTX_CHANNEL: DRP[150] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[62] bit 8 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 8	GTX_CHANNEL: DRP[62] bit 9 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 9	GTX_CHANNEL: DRP[150] bit 8 GTX_CHANNEL: AEN_TXPI_PPM bit 0	GTX_CHANNEL: DRP[150] bit 9 GTX_CHANNEL: A_TXPIPPMSEL bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[62] bit 6 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 6	GTX_CHANNEL: DRP[62] bit 7 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 7	GTX_CHANNEL: DRP[150] bit 6	GTX_CHANNEL: DRP[150] bit 7 GTX_CHANNEL: A_TXPIPPMOVRDEN bit 0
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[62] bit 4 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 4	GTX_CHANNEL: DRP[62] bit 5 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 5	GTX_CHANNEL: DRP[150] bit 4 GTX_CHANNEL: TXPI_INVSTROBE_SEL bit 0	GTX_CHANNEL: DRP[150] bit 5 GTX_CHANNEL: TXPI_GREY_SEL bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[62] bit 2 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 2	GTX_CHANNEL: DRP[62] bit 3 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 3	GTX_CHANNEL: DRP[150] bit 2 GTX_CHANNEL: TXPI_SYNFREQ_PPM bit 2	GTX_CHANNEL: DRP[150] bit 3 GTX_CHANNEL: TXPI_PPMCLK_SEL bit 0
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[62] bit 0 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 0	GTX_CHANNEL: DRP[62] bit 1 GTX_CHANNEL: ALIGN_COMMA_ENABLE bit 1	GTX_CHANNEL: DRP[150] bit 0 GTX_CHANNEL: TXPI_SYNFREQ_PPM bit 0	GTX_CHANNEL: DRP[150] bit 1 GTX_CHANNEL: TXPI_SYNFREQ_PPM bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[61] bit 14 GTX_CHANNEL: DEC_PCOMMA_DETECT	GTX_CHANNEL: DRP[61] bit 15 GTX_CHANNEL: RX_DISPERR_SEQ_MATCH	GTX_CHANNEL: DRP[149] bit 14	GTX_CHANNEL: DRP[149] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[61] bit 12 GTX_CHANNEL: DEC_VALID_COMMA_ONLY	GTX_CHANNEL: DRP[61] bit 13 GTX_CHANNEL: DEC_MCOMMA_DETECT	GTX_CHANNEL: DRP[149] bit 12	GTX_CHANNEL: DRP[149] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[61] bit 10	GTX_CHANNEL: DRP[61] bit 11	GTX_CHANNEL: DRP[149] bit 10	GTX_CHANNEL: DRP[149] bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[61] bit 8 GTX_CHANNEL: ES_EYE_SCAN_EN	GTX_CHANNEL: DRP[61] bit 9 GTX_CHANNEL: ES_ERRDET_EN	GTX_CHANNEL: DRP[149] bit 8	GTX_CHANNEL: DRP[149] bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[61] bit 6	GTX_CHANNEL: DRP[61] bit 7	GTX_CHANNEL: DRP[149] bit 6 GTX_CHANNEL: TXPI_PPM_CFG bit 6	GTX_CHANNEL: DRP[149] bit 7 GTX_CHANNEL: TXPI_PPM_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[61] bit 4 GTX_CHANNEL: ES_CONTROL bit 4	GTX_CHANNEL: DRP[61] bit 5 GTX_CHANNEL: ES_CONTROL bit 5	GTX_CHANNEL: DRP[149] bit 4 GTX_CHANNEL: TXPI_PPM_CFG bit 4	GTX_CHANNEL: DRP[149] bit 5 GTX_CHANNEL: TXPI_PPM_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[61] bit 2 GTX_CHANNEL: ES_CONTROL bit 2	GTX_CHANNEL: DRP[61] bit 3 GTX_CHANNEL: ES_CONTROL bit 3	GTX_CHANNEL: DRP[149] bit 2 GTX_CHANNEL: TXPI_PPM_CFG bit 2	GTX_CHANNEL: DRP[149] bit 3 GTX_CHANNEL: TXPI_PPM_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[61] bit 0 GTX_CHANNEL: ES_CONTROL bit 0	GTX_CHANNEL: DRP[61] bit 1 GTX_CHANNEL: ES_CONTROL bit 1	GTX_CHANNEL: DRP[149] bit 0 GTX_CHANNEL: TXPI_PPM_CFG bit 0	GTX_CHANNEL: DRP[149] bit 1 GTX_CHANNEL: TXPI_PPM_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[60] bit 14	GTX_CHANNEL: DRP[60] bit 15	GTX_CHANNEL: DRP[148] bit 14 GTX_CHANNEL: PMA_RSV4_GTH bit 14	GTX_CHANNEL: DRP[148] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[60] bit 12	GTX_CHANNEL: DRP[60] bit 13	GTX_CHANNEL: DRP[148] bit 12 GTX_CHANNEL: PMA_RSV4_GTH bit 12	GTX_CHANNEL: DRP[148] bit 13 GTX_CHANNEL: PMA_RSV4_GTH bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[60] bit 10 GTX_CHANNEL: ES_HORZ_OFFSET bit 10	GTX_CHANNEL: DRP[60] bit 11 GTX_CHANNEL: ES_HORZ_OFFSET bit 11	GTX_CHANNEL: DRP[148] bit 10 GTX_CHANNEL: PMA_RSV4_GTH bit 10	GTX_CHANNEL: DRP[148] bit 11 GTX_CHANNEL: PMA_RSV4_GTH bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[60] bit 8 GTX_CHANNEL: ES_HORZ_OFFSET bit 8	GTX_CHANNEL: DRP[60] bit 9 GTX_CHANNEL: ES_HORZ_OFFSET bit 9	GTX_CHANNEL: DRP[148] bit 8 GTX_CHANNEL: PMA_RSV4_GTH bit 8	GTX_CHANNEL: DRP[148] bit 9 GTX_CHANNEL: PMA_RSV4_GTH bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[60] bit 6 GTX_CHANNEL: ES_HORZ_OFFSET bit 6	GTX_CHANNEL: DRP[60] bit 7 GTX_CHANNEL: ES_HORZ_OFFSET bit 7	GTX_CHANNEL: DRP[148] bit 6 GTX_CHANNEL: PMA_RSV4_GTH bit 6	GTX_CHANNEL: DRP[148] bit 7 GTX_CHANNEL: PMA_RSV4_GTH bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[60] bit 4 GTX_CHANNEL: ES_HORZ_OFFSET bit 4	GTX_CHANNEL: DRP[60] bit 5 GTX_CHANNEL: ES_HORZ_OFFSET bit 5	GTX_CHANNEL: DRP[148] bit 4 GTX_CHANNEL: PMA_RSV4_GTH bit 4	GTX_CHANNEL: DRP[148] bit 5 GTX_CHANNEL: PMA_RSV4_GTH bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[60] bit 2 GTX_CHANNEL: ES_HORZ_OFFSET bit 2	GTX_CHANNEL: DRP[60] bit 3 GTX_CHANNEL: ES_HORZ_OFFSET bit 3	GTX_CHANNEL: DRP[148] bit 2 GTX_CHANNEL: PMA_RSV4_GTH bit 2	GTX_CHANNEL: DRP[148] bit 3 GTX_CHANNEL: PMA_RSV4_GTH bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[60] bit 0 GTX_CHANNEL: ES_HORZ_OFFSET bit 0	GTX_CHANNEL: DRP[60] bit 1 GTX_CHANNEL: ES_HORZ_OFFSET bit 1	GTX_CHANNEL: DRP[148] bit 0 GTX_CHANNEL: PMA_RSV4_GTH bit 0	GTX_CHANNEL: DRP[148] bit 1 GTX_CHANNEL: PMA_RSV4_GTH bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[59] bit 14 GTX_CHANNEL: ES_PRESCALE bit 3	GTX_CHANNEL: DRP[59] bit 15 GTX_CHANNEL: ES_PRESCALE bit 4	GTX_CHANNEL: DRP[147] bit 14	GTX_CHANNEL: DRP[147] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[59] bit 12 GTX_CHANNEL: ES_PRESCALE bit 1	GTX_CHANNEL: DRP[59] bit 13 GTX_CHANNEL: ES_PRESCALE bit 2	GTX_CHANNEL: DRP[147] bit 12	GTX_CHANNEL: DRP[147] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[59] bit 10	GTX_CHANNEL: DRP[59] bit 11 GTX_CHANNEL: ES_PRESCALE bit 0	GTX_CHANNEL: DRP[147] bit 10	GTX_CHANNEL: DRP[147] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[59] bit 8 GTX_CHANNEL: ES_VERT_OFFSET bit 8	GTX_CHANNEL: DRP[59] bit 9	GTX_CHANNEL: DRP[147] bit 8	GTX_CHANNEL: DRP[147] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[59] bit 6 GTX_CHANNEL: ES_VERT_OFFSET bit 6	GTX_CHANNEL: DRP[59] bit 7 GTX_CHANNEL: ES_VERT_OFFSET bit 7	GTX_CHANNEL: DRP[147] bit 6	GTX_CHANNEL: DRP[147] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[59] bit 4 GTX_CHANNEL: ES_VERT_OFFSET bit 4	GTX_CHANNEL: DRP[59] bit 5 GTX_CHANNEL: ES_VERT_OFFSET bit 5	GTX_CHANNEL: DRP[147] bit 4	GTX_CHANNEL: DRP[147] bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[59] bit 2 GTX_CHANNEL: ES_VERT_OFFSET bit 2	GTX_CHANNEL: DRP[59] bit 3 GTX_CHANNEL: ES_VERT_OFFSET bit 3	GTX_CHANNEL: DRP[147] bit 2 GTX_CHANNEL: ADAPT_CFG0 bit 18	GTX_CHANNEL: DRP[147] bit 3 GTX_CHANNEL: ADAPT_CFG0 bit 19
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[59] bit 0 GTX_CHANNEL: ES_VERT_OFFSET bit 0	GTX_CHANNEL: DRP[59] bit 1 GTX_CHANNEL: ES_VERT_OFFSET bit 1	GTX_CHANNEL: DRP[147] bit 0 GTX_CHANNEL: ADAPT_CFG0 bit 16	GTX_CHANNEL: DRP[147] bit 1 GTX_CHANNEL: ADAPT_CFG0 bit 17
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[58] bit 14 GTX_CHANNEL: ES_SDATA_MASK bit 78	GTX_CHANNEL: DRP[58] bit 15 GTX_CHANNEL: ES_SDATA_MASK bit 79	GTX_CHANNEL: DRP[146] bit 14 GTX_CHANNEL: ADAPT_CFG0 bit 14	GTX_CHANNEL: DRP[146] bit 15 GTX_CHANNEL: ADAPT_CFG0 bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[58] bit 12 GTX_CHANNEL: ES_SDATA_MASK bit 76	GTX_CHANNEL: DRP[58] bit 13 GTX_CHANNEL: ES_SDATA_MASK bit 77	GTX_CHANNEL: DRP[146] bit 12 GTX_CHANNEL: ADAPT_CFG0 bit 12	GTX_CHANNEL: DRP[146] bit 13 GTX_CHANNEL: ADAPT_CFG0 bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[58] bit 10 GTX_CHANNEL: ES_SDATA_MASK bit 74	GTX_CHANNEL: DRP[58] bit 11 GTX_CHANNEL: ES_SDATA_MASK bit 75	GTX_CHANNEL: DRP[146] bit 10 GTX_CHANNEL: ADAPT_CFG0 bit 10	GTX_CHANNEL: DRP[146] bit 11 GTX_CHANNEL: ADAPT_CFG0 bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[58] bit 8 GTX_CHANNEL: ES_SDATA_MASK bit 72	GTX_CHANNEL: DRP[58] bit 9 GTX_CHANNEL: ES_SDATA_MASK bit 73	GTX_CHANNEL: DRP[146] bit 8 GTX_CHANNEL: ADAPT_CFG0 bit 8	GTX_CHANNEL: DRP[146] bit 9 GTX_CHANNEL: ADAPT_CFG0 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[58] bit 6 GTX_CHANNEL: ES_SDATA_MASK bit 70	GTX_CHANNEL: DRP[58] bit 7 GTX_CHANNEL: ES_SDATA_MASK bit 71	GTX_CHANNEL: DRP[146] bit 6 GTX_CHANNEL: ADAPT_CFG0 bit 6	GTX_CHANNEL: DRP[146] bit 7 GTX_CHANNEL: ADAPT_CFG0 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[58] bit 4 GTX_CHANNEL: ES_SDATA_MASK bit 68	GTX_CHANNEL: DRP[58] bit 5 GTX_CHANNEL: ES_SDATA_MASK bit 69	GTX_CHANNEL: DRP[146] bit 4 GTX_CHANNEL: ADAPT_CFG0 bit 4	GTX_CHANNEL: DRP[146] bit 5 GTX_CHANNEL: ADAPT_CFG0 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[58] bit 2 GTX_CHANNEL: ES_SDATA_MASK bit 66	GTX_CHANNEL: DRP[58] bit 3 GTX_CHANNEL: ES_SDATA_MASK bit 67	GTX_CHANNEL: DRP[146] bit 2 GTX_CHANNEL: ADAPT_CFG0 bit 2	GTX_CHANNEL: DRP[146] bit 3 GTX_CHANNEL: ADAPT_CFG0 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[58] bit 0 GTX_CHANNEL: ES_SDATA_MASK bit 64	GTX_CHANNEL: DRP[58] bit 1 GTX_CHANNEL: ES_SDATA_MASK bit 65	GTX_CHANNEL: DRP[146] bit 0 GTX_CHANNEL: ADAPT_CFG0 bit 0	GTX_CHANNEL: DRP[146] bit 1 GTX_CHANNEL: ADAPT_CFG0 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[57] bit 14 GTX_CHANNEL: ES_SDATA_MASK bit 62	GTX_CHANNEL: DRP[57] bit 15 GTX_CHANNEL: ES_SDATA_MASK bit 63	GTX_CHANNEL: DRP[145] bit 14 GTX_CHANNEL: USE_PCS_CLK_PHASE_SEL bit 0	GTX_CHANNEL: DRP[145] bit 15 GTX_CHANNEL: ES_CLK_PHASE_SEL bit 0
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[57] bit 12 GTX_CHANNEL: ES_SDATA_MASK bit 60	GTX_CHANNEL: DRP[57] bit 13 GTX_CHANNEL: ES_SDATA_MASK bit 61	GTX_CHANNEL: DRP[145] bit 12	GTX_CHANNEL: DRP[145] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[57] bit 10 GTX_CHANNEL: ES_SDATA_MASK bit 58	GTX_CHANNEL: DRP[57] bit 11 GTX_CHANNEL: ES_SDATA_MASK bit 59	GTX_CHANNEL: DRP[145] bit 10 GTX_CHANNEL: CFOK_CFG2 bit 4	GTX_CHANNEL: DRP[145] bit 11 GTX_CHANNEL: CFOK_CFG2 bit 5
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[57] bit 8 GTX_CHANNEL: ES_SDATA_MASK bit 56	GTX_CHANNEL: DRP[57] bit 9 GTX_CHANNEL: ES_SDATA_MASK bit 57	GTX_CHANNEL: DRP[145] bit 8 GTX_CHANNEL: CFOK_CFG2 bit 2	GTX_CHANNEL: DRP[145] bit 9 GTX_CHANNEL: CFOK_CFG2 bit 3
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[57] bit 6 GTX_CHANNEL: ES_SDATA_MASK bit 54	GTX_CHANNEL: DRP[57] bit 7 GTX_CHANNEL: ES_SDATA_MASK bit 55	GTX_CHANNEL: DRP[145] bit 6 GTX_CHANNEL: CFOK_CFG2 bit 0	GTX_CHANNEL: DRP[145] bit 7 GTX_CHANNEL: CFOK_CFG2 bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[57] bit 4 GTX_CHANNEL: ES_SDATA_MASK bit 52	GTX_CHANNEL: DRP[57] bit 5 GTX_CHANNEL: ES_SDATA_MASK bit 53	GTX_CHANNEL: DRP[145] bit 4 GTX_CHANNEL: RX_DFE_ST_CFG bit 52	GTX_CHANNEL: DRP[145] bit 5 GTX_CHANNEL: RX_DFE_ST_CFG bit 53
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[57] bit 2 GTX_CHANNEL: ES_SDATA_MASK bit 50	GTX_CHANNEL: DRP[57] bit 3 GTX_CHANNEL: ES_SDATA_MASK bit 51	GTX_CHANNEL: DRP[145] bit 2 GTX_CHANNEL: RX_DFE_ST_CFG bit 50	GTX_CHANNEL: DRP[145] bit 3 GTX_CHANNEL: RX_DFE_ST_CFG bit 51
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[57] bit 0 GTX_CHANNEL: ES_SDATA_MASK bit 48	GTX_CHANNEL: DRP[57] bit 1 GTX_CHANNEL: ES_SDATA_MASK bit 49	GTX_CHANNEL: DRP[145] bit 0 GTX_CHANNEL: RX_DFE_ST_CFG bit 48	GTX_CHANNEL: DRP[145] bit 1 GTX_CHANNEL: RX_DFE_ST_CFG bit 49
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[56] bit 14 GTX_CHANNEL: ES_SDATA_MASK bit 46	GTX_CHANNEL: DRP[56] bit 15 GTX_CHANNEL: ES_SDATA_MASK bit 47	GTX_CHANNEL: DRP[144] bit 14 GTX_CHANNEL: RX_DFE_ST_CFG bit 46	GTX_CHANNEL: DRP[144] bit 15 GTX_CHANNEL: RX_DFE_ST_CFG bit 47
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[56] bit 12 GTX_CHANNEL: ES_SDATA_MASK bit 44	GTX_CHANNEL: DRP[56] bit 13 GTX_CHANNEL: ES_SDATA_MASK bit 45	GTX_CHANNEL: DRP[144] bit 12 GTX_CHANNEL: RX_DFE_ST_CFG bit 44	GTX_CHANNEL: DRP[144] bit 13 GTX_CHANNEL: RX_DFE_ST_CFG bit 45
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[56] bit 10 GTX_CHANNEL: ES_SDATA_MASK bit 42	GTX_CHANNEL: DRP[56] bit 11 GTX_CHANNEL: ES_SDATA_MASK bit 43	GTX_CHANNEL: DRP[144] bit 10 GTX_CHANNEL: RX_DFE_ST_CFG bit 42	GTX_CHANNEL: DRP[144] bit 11 GTX_CHANNEL: RX_DFE_ST_CFG bit 43
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[56] bit 8 GTX_CHANNEL: ES_SDATA_MASK bit 40	GTX_CHANNEL: DRP[56] bit 9 GTX_CHANNEL: ES_SDATA_MASK bit 41	GTX_CHANNEL: DRP[144] bit 8 GTX_CHANNEL: RX_DFE_ST_CFG bit 40	GTX_CHANNEL: DRP[144] bit 9 GTX_CHANNEL: RX_DFE_ST_CFG bit 41
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[56] bit 6 GTX_CHANNEL: ES_SDATA_MASK bit 38	GTX_CHANNEL: DRP[56] bit 7 GTX_CHANNEL: ES_SDATA_MASK bit 39	GTX_CHANNEL: DRP[144] bit 6 GTX_CHANNEL: RX_DFE_ST_CFG bit 38	GTX_CHANNEL: DRP[144] bit 7 GTX_CHANNEL: RX_DFE_ST_CFG bit 39
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[56] bit 4 GTX_CHANNEL: ES_SDATA_MASK bit 36	GTX_CHANNEL: DRP[56] bit 5 GTX_CHANNEL: ES_SDATA_MASK bit 37	GTX_CHANNEL: DRP[144] bit 4 GTX_CHANNEL: RX_DFE_ST_CFG bit 36	GTX_CHANNEL: DRP[144] bit 5 GTX_CHANNEL: RX_DFE_ST_CFG bit 37
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[56] bit 2 GTX_CHANNEL: ES_SDATA_MASK bit 34	GTX_CHANNEL: DRP[56] bit 3 GTX_CHANNEL: ES_SDATA_MASK bit 35	GTX_CHANNEL: DRP[144] bit 2 GTX_CHANNEL: RX_DFE_ST_CFG bit 34	GTX_CHANNEL: DRP[144] bit 3 GTX_CHANNEL: RX_DFE_ST_CFG bit 35
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[56] bit 0 GTX_CHANNEL: ES_SDATA_MASK bit 32	GTX_CHANNEL: DRP[56] bit 1 GTX_CHANNEL: ES_SDATA_MASK bit 33	GTX_CHANNEL: DRP[144] bit 0 GTX_CHANNEL: RX_DFE_ST_CFG bit 32	GTX_CHANNEL: DRP[144] bit 1 GTX_CHANNEL: RX_DFE_ST_CFG bit 33

virtex7 GTH_CHANNEL rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[71] bit 14 GTX_CHANNEL: CLK_COR_REPEAT_WAIT bit 4	GTX_CHANNEL: DRP[71] bit 15	GTX_CHANNEL: DRP[159] bit 14	GTX_CHANNEL: DRP[159] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[71] bit 12 GTX_CHANNEL: CLK_COR_REPEAT_WAIT bit 2	GTX_CHANNEL: DRP[71] bit 13 GTX_CHANNEL: CLK_COR_REPEAT_WAIT bit 3	GTX_CHANNEL: DRP[159] bit 12	GTX_CHANNEL: DRP[159] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[71] bit 10 GTX_CHANNEL: CLK_COR_REPEAT_WAIT bit 0	GTX_CHANNEL: DRP[71] bit 11 GTX_CHANNEL: CLK_COR_REPEAT_WAIT bit 1	GTX_CHANNEL: DRP[159] bit 10	GTX_CHANNEL: DRP[159] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[71] bit 8 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 8	GTX_CHANNEL: DRP[71] bit 9 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 9	GTX_CHANNEL: DRP[159] bit 8 GTX_CHANNEL: TXDLY_LCFG bit 8	GTX_CHANNEL: DRP[159] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[71] bit 6 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 6	GTX_CHANNEL: DRP[71] bit 7 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 7	GTX_CHANNEL: DRP[159] bit 6 GTX_CHANNEL: TXDLY_LCFG bit 6	GTX_CHANNEL: DRP[159] bit 7 GTX_CHANNEL: TXDLY_LCFG bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[71] bit 4 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 4	GTX_CHANNEL: DRP[71] bit 5 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 5	GTX_CHANNEL: DRP[159] bit 4 GTX_CHANNEL: TXDLY_LCFG bit 4	GTX_CHANNEL: DRP[159] bit 5 GTX_CHANNEL: TXDLY_LCFG bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[71] bit 2 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 2	GTX_CHANNEL: DRP[71] bit 3 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 3	GTX_CHANNEL: DRP[159] bit 2 GTX_CHANNEL: TXDLY_LCFG bit 2	GTX_CHANNEL: DRP[159] bit 3 GTX_CHANNEL: TXDLY_LCFG bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[71] bit 0 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 0	GTX_CHANNEL: DRP[71] bit 1 GTX_CHANNEL: CLK_COR_SEQ_1_4 bit 1	GTX_CHANNEL: DRP[159] bit 0 GTX_CHANNEL: TXDLY_LCFG bit 0	GTX_CHANNEL: DRP[159] bit 1 GTX_CHANNEL: TXDLY_LCFG bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[70] bit 14 GTX_CHANNEL: CLK_COR_MIN_LAT bit 4	GTX_CHANNEL: DRP[70] bit 15 GTX_CHANNEL: CLK_COR_MIN_LAT bit 5	GTX_CHANNEL: DRP[158] bit 14	GTX_CHANNEL: DRP[158] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[70] bit 12 GTX_CHANNEL: CLK_COR_MIN_LAT bit 2	GTX_CHANNEL: DRP[70] bit 13 GTX_CHANNEL: CLK_COR_MIN_LAT bit 3	GTX_CHANNEL: DRP[158] bit 12	GTX_CHANNEL: DRP[158] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[70] bit 10 GTX_CHANNEL: CLK_COR_MIN_LAT bit 0	GTX_CHANNEL: DRP[70] bit 11 GTX_CHANNEL: CLK_COR_MIN_LAT bit 1	GTX_CHANNEL: DRP[158] bit 10	GTX_CHANNEL: DRP[158] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[70] bit 8 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 8	GTX_CHANNEL: DRP[70] bit 9 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 9	GTX_CHANNEL: DRP[158] bit 8	GTX_CHANNEL: DRP[158] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[70] bit 6 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 6	GTX_CHANNEL: DRP[70] bit 7 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 7	GTX_CHANNEL: DRP[158] bit 6	GTX_CHANNEL: DRP[158] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[70] bit 4 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 4	GTX_CHANNEL: DRP[70] bit 5 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 5	GTX_CHANNEL: DRP[158] bit 4	GTX_CHANNEL: DRP[158] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[70] bit 2 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 2	GTX_CHANNEL: DRP[70] bit 3 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 3	GTX_CHANNEL: DRP[158] bit 2	GTX_CHANNEL: DRP[158] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[70] bit 0 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 0	GTX_CHANNEL: DRP[70] bit 1 GTX_CHANNEL: CLK_COR_SEQ_1_3 bit 1	GTX_CHANNEL: DRP[158] bit 0	GTX_CHANNEL: DRP[158] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[69] bit 14 GTX_CHANNEL: CLK_COR_MAX_LAT bit 4	GTX_CHANNEL: DRP[69] bit 15 GTX_CHANNEL: CLK_COR_MAX_LAT bit 5	GTX_CHANNEL: DRP[157] bit 14 GTX_CHANNEL: RXBUF_EIDLE_HI_CNT bit 2	GTX_CHANNEL: DRP[157] bit 15 GTX_CHANNEL: RXBUF_EIDLE_HI_CNT bit 3
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[69] bit 12 GTX_CHANNEL: CLK_COR_MAX_LAT bit 2	GTX_CHANNEL: DRP[69] bit 13 GTX_CHANNEL: CLK_COR_MAX_LAT bit 3	GTX_CHANNEL: DRP[157] bit 12 GTX_CHANNEL: RXBUF_EIDLE_HI_CNT bit 0	GTX_CHANNEL: DRP[157] bit 13 GTX_CHANNEL: RXBUF_EIDLE_HI_CNT bit 1
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[69] bit 10 GTX_CHANNEL: CLK_COR_MAX_LAT bit 0	GTX_CHANNEL: DRP[69] bit 11 GTX_CHANNEL: CLK_COR_MAX_LAT bit 1	GTX_CHANNEL: DRP[157] bit 10 GTX_CHANNEL: RXBUF_EIDLE_LO_CNT bit 2	GTX_CHANNEL: DRP[157] bit 11 GTX_CHANNEL: RXBUF_EIDLE_LO_CNT bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[69] bit 8 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 8	GTX_CHANNEL: DRP[69] bit 9 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 9	GTX_CHANNEL: DRP[157] bit 8 GTX_CHANNEL: RXBUF_EIDLE_LO_CNT bit 0	GTX_CHANNEL: DRP[157] bit 9 GTX_CHANNEL: RXBUF_EIDLE_LO_CNT bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[69] bit 6 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 6	GTX_CHANNEL: DRP[69] bit 7 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 7	GTX_CHANNEL: DRP[157] bit 6 GTX_CHANNEL: RXBUF_RESET_ON_EIDLE	GTX_CHANNEL: DRP[157] bit 7 GTX_CHANNEL: RXBUF_ADDR_MODE bit 0
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[69] bit 4 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 4	GTX_CHANNEL: DRP[69] bit 5 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 5	GTX_CHANNEL: DRP[157] bit 4 GTX_CHANNEL: RXBUF_RESET_ON_RATE_CHANGE	GTX_CHANNEL: DRP[157] bit 5 GTX_CHANNEL: RXBUF_RESET_ON_CB_CHANGE
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[69] bit 2 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 2	GTX_CHANNEL: DRP[69] bit 3 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 3	GTX_CHANNEL: DRP[157] bit 2 GTX_CHANNEL: RXBUF_THRESH_OVRD	GTX_CHANNEL: DRP[157] bit 3 GTX_CHANNEL: RXBUF_RESET_ON_COMMAALIGN
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[69] bit 0 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 0	GTX_CHANNEL: DRP[69] bit 1 GTX_CHANNEL: CLK_COR_SEQ_1_2 bit 1	GTX_CHANNEL: DRP[157] bit 0 GTX_CHANNEL: RX_DEFER_RESET_BUF_EN	GTX_CHANNEL: DRP[157] bit 1 GTX_CHANNEL: RXBUF_EN
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[68] bit 14 GTX_CHANNEL: CLK_CORRECT_USE	GTX_CHANNEL: DRP[68] bit 15	GTX_CHANNEL: DRP[156] bit 14	GTX_CHANNEL: DRP[156] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[68] bit 12 GTX_CHANNEL: CLK_COR_SEQ_1_ENABLE bit 2	GTX_CHANNEL: DRP[68] bit 13 GTX_CHANNEL: CLK_COR_SEQ_1_ENABLE bit 3	GTX_CHANNEL: DRP[156] bit 12 GTX_CHANNEL: RXBUF_THRESH_OVFLW bit 4	GTX_CHANNEL: DRP[156] bit 13 GTX_CHANNEL: RXBUF_THRESH_OVFLW bit 5
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[68] bit 10 GTX_CHANNEL: CLK_COR_SEQ_1_ENABLE bit 0	GTX_CHANNEL: DRP[68] bit 11 GTX_CHANNEL: CLK_COR_SEQ_1_ENABLE bit 1	GTX_CHANNEL: DRP[156] bit 10 GTX_CHANNEL: RXBUF_THRESH_OVFLW bit 2	GTX_CHANNEL: DRP[156] bit 11 GTX_CHANNEL: RXBUF_THRESH_OVFLW bit 3
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[68] bit 8 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 8	GTX_CHANNEL: DRP[68] bit 9 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 9	GTX_CHANNEL: DRP[156] bit 8 GTX_CHANNEL: RXBUF_THRESH_OVFLW bit 0	GTX_CHANNEL: DRP[156] bit 9 GTX_CHANNEL: RXBUF_THRESH_OVFLW bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[68] bit 6 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 6	GTX_CHANNEL: DRP[68] bit 7 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 7	GTX_CHANNEL: DRP[156] bit 6	GTX_CHANNEL: DRP[156] bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[68] bit 4 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 4	GTX_CHANNEL: DRP[68] bit 5 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 5	GTX_CHANNEL: DRP[156] bit 4 GTX_CHANNEL: RXBUF_THRESH_UNDFLW bit 4	GTX_CHANNEL: DRP[156] bit 5 GTX_CHANNEL: RXBUF_THRESH_UNDFLW bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[68] bit 2 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 2	GTX_CHANNEL: DRP[68] bit 3 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 3	GTX_CHANNEL: DRP[156] bit 2 GTX_CHANNEL: RXBUF_THRESH_UNDFLW bit 2	GTX_CHANNEL: DRP[156] bit 3 GTX_CHANNEL: RXBUF_THRESH_UNDFLW bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[68] bit 0 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 0	GTX_CHANNEL: DRP[68] bit 1 GTX_CHANNEL: CLK_COR_SEQ_1_1 bit 1	GTX_CHANNEL: DRP[156] bit 0 GTX_CHANNEL: RXBUF_THRESH_UNDFLW bit 0	GTX_CHANNEL: DRP[156] bit 1 GTX_CHANNEL: RXBUF_THRESH_UNDFLW bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[67] bit 14	GTX_CHANNEL: DRP[67] bit 15	GTX_CHANNEL: DRP[155] bit 14	GTX_CHANNEL: DRP[155] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[67] bit 12	GTX_CHANNEL: DRP[67] bit 13	GTX_CHANNEL: DRP[155] bit 12	GTX_CHANNEL: DRP[155] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[67] bit 10	GTX_CHANNEL: DRP[67] bit 11	GTX_CHANNEL: DRP[155] bit 10	GTX_CHANNEL: DRP[155] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[67] bit 8	GTX_CHANNEL: DRP[67] bit 9	GTX_CHANNEL: DRP[155] bit 8	GTX_CHANNEL: DRP[155] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[67] bit 6	GTX_CHANNEL: DRP[67] bit 7	GTX_CHANNEL: DRP[155] bit 6	GTX_CHANNEL: DRP[155] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[67] bit 4	GTX_CHANNEL: DRP[67] bit 5	GTX_CHANNEL: DRP[155] bit 4 GTX_CHANNEL: RX_BUFFER_CFG bit 4	GTX_CHANNEL: DRP[155] bit 5 GTX_CHANNEL: RX_BUFFER_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[67] bit 2	GTX_CHANNEL: DRP[67] bit 3	GTX_CHANNEL: DRP[155] bit 2 GTX_CHANNEL: RX_BUFFER_CFG bit 2	GTX_CHANNEL: DRP[155] bit 3 GTX_CHANNEL: RX_BUFFER_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[67] bit 0	GTX_CHANNEL: DRP[67] bit 1	GTX_CHANNEL: DRP[155] bit 0 GTX_CHANNEL: RX_BUFFER_CFG bit 0	GTX_CHANNEL: DRP[155] bit 1 GTX_CHANNEL: RX_BUFFER_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[66] bit 14	GTX_CHANNEL: DRP[66] bit 15	GTX_CHANNEL: DRP[154] bit 14 GTX_CHANNEL: PMA_RSV bit 30	GTX_CHANNEL: DRP[154] bit 15 GTX_CHANNEL: PMA_RSV bit 31
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[66] bit 12	GTX_CHANNEL: DRP[66] bit 13	GTX_CHANNEL: DRP[154] bit 12 GTX_CHANNEL: PMA_RSV bit 28	GTX_CHANNEL: DRP[154] bit 13 GTX_CHANNEL: PMA_RSV bit 29
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[66] bit 10	GTX_CHANNEL: DRP[66] bit 11	GTX_CHANNEL: DRP[154] bit 10 GTX_CHANNEL: PMA_RSV bit 26	GTX_CHANNEL: DRP[154] bit 11 GTX_CHANNEL: PMA_RSV bit 27
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[66] bit 8	GTX_CHANNEL: DRP[66] bit 9	GTX_CHANNEL: DRP[154] bit 8 GTX_CHANNEL: PMA_RSV bit 24	GTX_CHANNEL: DRP[154] bit 9 GTX_CHANNEL: PMA_RSV bit 25
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[66] bit 6	GTX_CHANNEL: DRP[66] bit 7	GTX_CHANNEL: DRP[154] bit 6 GTX_CHANNEL: PMA_RSV bit 22	GTX_CHANNEL: DRP[154] bit 7 GTX_CHANNEL: PMA_RSV bit 23
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[66] bit 4	GTX_CHANNEL: DRP[66] bit 5	GTX_CHANNEL: DRP[154] bit 4 GTX_CHANNEL: PMA_RSV bit 20	GTX_CHANNEL: DRP[154] bit 5 GTX_CHANNEL: PMA_RSV bit 21
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[66] bit 2	GTX_CHANNEL: DRP[66] bit 3	GTX_CHANNEL: DRP[154] bit 2 GTX_CHANNEL: PMA_RSV bit 18	GTX_CHANNEL: DRP[154] bit 3 GTX_CHANNEL: PMA_RSV bit 19
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[66] bit 0	GTX_CHANNEL: DRP[66] bit 1	GTX_CHANNEL: DRP[154] bit 0 GTX_CHANNEL: PMA_RSV bit 16	GTX_CHANNEL: DRP[154] bit 1 GTX_CHANNEL: PMA_RSV bit 17
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[65] bit 14 GTX_CHANNEL: ALIGN_COMMA_WORD bit 1	GTX_CHANNEL: DRP[65] bit 15 GTX_CHANNEL: ALIGN_COMMA_WORD bit 2	GTX_CHANNEL: DRP[153] bit 14 GTX_CHANNEL: PMA_RSV bit 14	GTX_CHANNEL: DRP[153] bit 15 GTX_CHANNEL: PMA_RSV bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[65] bit 12 GTX_CHANNEL: RX_SIG_VALID_DLY bit 4	GTX_CHANNEL: DRP[65] bit 13 GTX_CHANNEL: ALIGN_COMMA_WORD bit 0	GTX_CHANNEL: DRP[153] bit 12 GTX_CHANNEL: PMA_RSV bit 12	GTX_CHANNEL: DRP[153] bit 13 GTX_CHANNEL: PMA_RSV bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[65] bit 10 GTX_CHANNEL: RX_SIG_VALID_DLY bit 2	GTX_CHANNEL: DRP[65] bit 11 GTX_CHANNEL: RX_SIG_VALID_DLY bit 3	GTX_CHANNEL: DRP[153] bit 10 GTX_CHANNEL: PMA_RSV bit 10	GTX_CHANNEL: DRP[153] bit 11 GTX_CHANNEL: PMA_RSV bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[65] bit 8 GTX_CHANNEL: RX_SIG_VALID_DLY bit 0	GTX_CHANNEL: DRP[65] bit 9 GTX_CHANNEL: RX_SIG_VALID_DLY bit 1	GTX_CHANNEL: DRP[153] bit 8 GTX_CHANNEL: PMA_RSV bit 8	GTX_CHANNEL: DRP[153] bit 9 GTX_CHANNEL: PMA_RSV bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[65] bit 6 GTX_CHANNEL: ALIGN_MCOMMA_DET	GTX_CHANNEL: DRP[65] bit 7 GTX_CHANNEL: ALIGN_PCOMMA_DET	GTX_CHANNEL: DRP[153] bit 6 GTX_CHANNEL: PMA_RSV bit 6	GTX_CHANNEL: DRP[153] bit 7 GTX_CHANNEL: PMA_RSV bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[65] bit 4 GTX_CHANNEL: ALIGN_COMMA_DOUBLE	GTX_CHANNEL: DRP[65] bit 5 GTX_CHANNEL: SHOW_REALIGN_COMMA	GTX_CHANNEL: DRP[153] bit 4 GTX_CHANNEL: PMA_RSV bit 4	GTX_CHANNEL: DRP[153] bit 5 GTX_CHANNEL: PMA_RSV bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[65] bit 2 GTX_CHANNEL: RXSLIDE_AUTO_WAIT bit 2	GTX_CHANNEL: DRP[65] bit 3 GTX_CHANNEL: RXSLIDE_AUTO_WAIT bit 3	GTX_CHANNEL: DRP[153] bit 2 GTX_CHANNEL: PMA_RSV bit 2	GTX_CHANNEL: DRP[153] bit 3 GTX_CHANNEL: PMA_RSV bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[65] bit 0 GTX_CHANNEL: RXSLIDE_AUTO_WAIT bit 0	GTX_CHANNEL: DRP[65] bit 1 GTX_CHANNEL: RXSLIDE_AUTO_WAIT bit 1	GTX_CHANNEL: DRP[153] bit 0 GTX_CHANNEL: PMA_RSV bit 0	GTX_CHANNEL: DRP[153] bit 1 GTX_CHANNEL: PMA_RSV bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[64] bit 14 GTX_CHANNEL: RXSLIDE_MODE bit 0	GTX_CHANNEL: DRP[64] bit 15 GTX_CHANNEL: RXSLIDE_MODE bit 1	GTX_CHANNEL: DRP[152] bit 14 GTX_CHANNEL: TST_RSV bit 30	GTX_CHANNEL: DRP[152] bit 15 GTX_CHANNEL: TST_RSV bit 31
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[64] bit 12	GTX_CHANNEL: DRP[64] bit 13	GTX_CHANNEL: DRP[152] bit 12 GTX_CHANNEL: TST_RSV bit 28	GTX_CHANNEL: DRP[152] bit 13 GTX_CHANNEL: TST_RSV bit 29
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[64] bit 10	GTX_CHANNEL: DRP[64] bit 11	GTX_CHANNEL: DRP[152] bit 10 GTX_CHANNEL: TST_RSV bit 26	GTX_CHANNEL: DRP[152] bit 11 GTX_CHANNEL: TST_RSV bit 27
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[64] bit 8 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 8	GTX_CHANNEL: DRP[64] bit 9 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 9	GTX_CHANNEL: DRP[152] bit 8 GTX_CHANNEL: TST_RSV bit 24	GTX_CHANNEL: DRP[152] bit 9 GTX_CHANNEL: TST_RSV bit 25
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[64] bit 6 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 6	GTX_CHANNEL: DRP[64] bit 7 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 7	GTX_CHANNEL: DRP[152] bit 6 GTX_CHANNEL: TST_RSV bit 22	GTX_CHANNEL: DRP[152] bit 7 GTX_CHANNEL: TST_RSV bit 23
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[64] bit 4 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 4	GTX_CHANNEL: DRP[64] bit 5 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 5	GTX_CHANNEL: DRP[152] bit 4 GTX_CHANNEL: TST_RSV bit 20	GTX_CHANNEL: DRP[152] bit 5 GTX_CHANNEL: TST_RSV bit 21
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[64] bit 2 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 2	GTX_CHANNEL: DRP[64] bit 3 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 3	GTX_CHANNEL: DRP[152] bit 2 GTX_CHANNEL: TST_RSV bit 18	GTX_CHANNEL: DRP[152] bit 3 GTX_CHANNEL: TST_RSV bit 19
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[64] bit 0 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 0	GTX_CHANNEL: DRP[64] bit 1 GTX_CHANNEL: ALIGN_PCOMMA_VALUE bit 1	GTX_CHANNEL: DRP[152] bit 0 GTX_CHANNEL: TST_RSV bit 16	GTX_CHANNEL: DRP[152] bit 1 GTX_CHANNEL: TST_RSV bit 17

virtex7 GTH_CHANNEL rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[79] bit 14	GTX_CHANNEL: DRP[79] bit 15	GTX_CHANNEL: DRP[167] bit 14	GTX_CHANNEL: DRP[167] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[79] bit 12	GTX_CHANNEL: DRP[79] bit 13	GTX_CHANNEL: DRP[167] bit 12 GTX_CHANNEL: RXCDR_FR_RESET_ON_EIDLE bit 0	GTX_CHANNEL: DRP[167] bit 13 GTX_CHANNEL: RXCDR_PH_RESET_ON_EIDLE bit 0
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[79] bit 10	GTX_CHANNEL: DRP[79] bit 11	GTX_CHANNEL: DRP[167] bit 10 GTX_CHANNEL: RXCDR_PCIERESET_WAIT_TIME bit 4	GTX_CHANNEL: DRP[167] bit 11 GTX_CHANNEL: RXCDR_HOLD_DURING_EIDLE bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[79] bit 8 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 8	GTX_CHANNEL: DRP[79] bit 9 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 9	GTX_CHANNEL: DRP[167] bit 8 GTX_CHANNEL: RXCDR_PCIERESET_WAIT_TIME bit 2	GTX_CHANNEL: DRP[167] bit 9 GTX_CHANNEL: RXCDR_PCIERESET_WAIT_TIME bit 3
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[79] bit 6 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 6	GTX_CHANNEL: DRP[79] bit 7 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 7	GTX_CHANNEL: DRP[167] bit 6 GTX_CHANNEL: RXCDR_PCIERESET_WAIT_TIME bit 0	GTX_CHANNEL: DRP[167] bit 7 GTX_CHANNEL: RXCDR_PCIERESET_WAIT_TIME bit 1
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[79] bit 4 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 4	GTX_CHANNEL: DRP[79] bit 5 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 5	GTX_CHANNEL: DRP[167] bit 4 GTX_CHANNEL: RXCDR_LOCK_CFG bit 4	GTX_CHANNEL: DRP[167] bit 5 GTX_CHANNEL: RXCDR_LOCK_CFG bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[79] bit 2 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 2	GTX_CHANNEL: DRP[79] bit 3 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 3	GTX_CHANNEL: DRP[167] bit 2 GTX_CHANNEL: RXCDR_LOCK_CFG bit 2	GTX_CHANNEL: DRP[167] bit 3 GTX_CHANNEL: RXCDR_LOCK_CFG bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[79] bit 0 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 0	GTX_CHANNEL: DRP[79] bit 1 GTX_CHANNEL: CHAN_BOND_SEQ_1_4 bit 1	GTX_CHANNEL: DRP[167] bit 0 GTX_CHANNEL: RXCDR_LOCK_CFG bit 0	GTX_CHANNEL: DRP[167] bit 1 GTX_CHANNEL: RXCDR_LOCK_CFG bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[78] bit 14	GTX_CHANNEL: DRP[78] bit 15 GTX_CHANNEL: CHAN_BOND_KEEP_ALIGN	GTX_CHANNEL: DRP[166] bit 14	GTX_CHANNEL: DRP[166] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[78] bit 12	GTX_CHANNEL: DRP[78] bit 13	GTX_CHANNEL: DRP[166] bit 12	GTX_CHANNEL: DRP[166] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[78] bit 10	GTX_CHANNEL: DRP[78] bit 11	GTX_CHANNEL: DRP[166] bit 10	GTX_CHANNEL: DRP[166] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[78] bit 8 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 8	GTX_CHANNEL: DRP[78] bit 9 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 9	GTX_CHANNEL: DRP[166] bit 8 GTX_CHANNEL: ES_PMA_CFG bit 8	GTX_CHANNEL: DRP[166] bit 9 GTX_CHANNEL: ES_PMA_CFG bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[78] bit 6 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 6	GTX_CHANNEL: DRP[78] bit 7 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 7	GTX_CHANNEL: DRP[166] bit 6 GTX_CHANNEL: ES_PMA_CFG bit 6	GTX_CHANNEL: DRP[166] bit 7 GTX_CHANNEL: ES_PMA_CFG bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[78] bit 4 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 4	GTX_CHANNEL: DRP[78] bit 5 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 5	GTX_CHANNEL: DRP[166] bit 4 GTX_CHANNEL: ES_PMA_CFG bit 4	GTX_CHANNEL: DRP[166] bit 5 GTX_CHANNEL: ES_PMA_CFG bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[78] bit 2 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 2	GTX_CHANNEL: DRP[78] bit 3 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 3	GTX_CHANNEL: DRP[166] bit 2 GTX_CHANNEL: ES_PMA_CFG bit 2	GTX_CHANNEL: DRP[166] bit 3 GTX_CHANNEL: ES_PMA_CFG bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[78] bit 0 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 0	GTX_CHANNEL: DRP[78] bit 1 GTX_CHANNEL: CHAN_BOND_SEQ_1_3 bit 1	GTX_CHANNEL: DRP[166] bit 0 GTX_CHANNEL: ES_PMA_CFG bit 0	GTX_CHANNEL: DRP[166] bit 1 GTX_CHANNEL: ES_PMA_CFG bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[77] bit 14 GTX_CHANNEL: CHAN_BOND_SEQ_LEN bit 0	GTX_CHANNEL: DRP[77] bit 15 GTX_CHANNEL: CHAN_BOND_SEQ_LEN bit 1	GTX_CHANNEL: DRP[165] bit 14	GTX_CHANNEL: DRP[165] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[77] bit 12	GTX_CHANNEL: DRP[77] bit 13	GTX_CHANNEL: DRP[165] bit 12 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 12	GTX_CHANNEL: DRP[165] bit 13 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[77] bit 10	GTX_CHANNEL: DRP[77] bit 11	GTX_CHANNEL: DRP[165] bit 10 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 10	GTX_CHANNEL: DRP[165] bit 11 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[77] bit 8 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 8	GTX_CHANNEL: DRP[77] bit 9 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 9	GTX_CHANNEL: DRP[165] bit 8 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 8	GTX_CHANNEL: DRP[165] bit 9 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[77] bit 6 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 6	GTX_CHANNEL: DRP[77] bit 7 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 7	GTX_CHANNEL: DRP[165] bit 6 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 6	GTX_CHANNEL: DRP[165] bit 7 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[77] bit 4 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 4	GTX_CHANNEL: DRP[77] bit 5 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 5	GTX_CHANNEL: DRP[165] bit 4 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 4	GTX_CHANNEL: DRP[165] bit 5 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[77] bit 2 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 2	GTX_CHANNEL: DRP[77] bit 3 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 3	GTX_CHANNEL: DRP[165] bit 2 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 2	GTX_CHANNEL: DRP[165] bit 3 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[77] bit 0 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 0	GTX_CHANNEL: DRP[77] bit 1 GTX_CHANNEL: CHAN_BOND_SEQ_1_2 bit 1	GTX_CHANNEL: DRP[165] bit 0 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 0	GTX_CHANNEL: DRP[165] bit 1 GTX_CHANNEL: RX_DEBUG_CFG_GTH bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[76] bit 14 GTX_CHANNEL: CHAN_BOND_SEQ_1_ENABLE bit 2	GTX_CHANNEL: DRP[76] bit 15 GTX_CHANNEL: CHAN_BOND_SEQ_1_ENABLE bit 3	GTX_CHANNEL: DRP[164] bit 14	GTX_CHANNEL: DRP[164] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[76] bit 12 GTX_CHANNEL: CHAN_BOND_SEQ_1_ENABLE bit 0	GTX_CHANNEL: DRP[76] bit 13 GTX_CHANNEL: CHAN_BOND_SEQ_1_ENABLE bit 1	GTX_CHANNEL: DRP[164] bit 12	GTX_CHANNEL: DRP[164] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[76] bit 10	GTX_CHANNEL: DRP[76] bit 11	GTX_CHANNEL: DRP[164] bit 10	GTX_CHANNEL: DRP[164] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[76] bit 8 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 8	GTX_CHANNEL: DRP[76] bit 9 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 9	GTX_CHANNEL: DRP[164] bit 8	GTX_CHANNEL: DRP[164] bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[76] bit 6 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 6	GTX_CHANNEL: DRP[76] bit 7 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 7	GTX_CHANNEL: DRP[164] bit 6 GTX_CHANNEL: RXPHDLY_CFG bit 22	GTX_CHANNEL: DRP[164] bit 7 GTX_CHANNEL: RXPHDLY_CFG bit 23
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[76] bit 4 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 4	GTX_CHANNEL: DRP[76] bit 5 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 5	GTX_CHANNEL: DRP[164] bit 4 GTX_CHANNEL: RXPHDLY_CFG bit 20	GTX_CHANNEL: DRP[164] bit 5 GTX_CHANNEL: RXPHDLY_CFG bit 21
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[76] bit 2 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 2	GTX_CHANNEL: DRP[76] bit 3 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 3	GTX_CHANNEL: DRP[164] bit 2 GTX_CHANNEL: RXPHDLY_CFG bit 18	GTX_CHANNEL: DRP[164] bit 3 GTX_CHANNEL: RXPHDLY_CFG bit 19
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[76] bit 0 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 0	GTX_CHANNEL: DRP[76] bit 1 GTX_CHANNEL: CHAN_BOND_SEQ_1_1 bit 1	GTX_CHANNEL: DRP[164] bit 0 GTX_CHANNEL: RXPHDLY_CFG bit 16	GTX_CHANNEL: DRP[164] bit 1 GTX_CHANNEL: RXPHDLY_CFG bit 17
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[75] bit 14	GTX_CHANNEL: DRP[75] bit 15 GTX_CHANNEL: RXGEARBOX_EN	GTX_CHANNEL: DRP[163] bit 14 GTX_CHANNEL: RXPHDLY_CFG bit 14	GTX_CHANNEL: DRP[163] bit 15 GTX_CHANNEL: RXPHDLY_CFG bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[75] bit 12	GTX_CHANNEL: DRP[75] bit 13	GTX_CHANNEL: DRP[163] bit 12 GTX_CHANNEL: RXPHDLY_CFG bit 12	GTX_CHANNEL: DRP[163] bit 13 GTX_CHANNEL: RXPHDLY_CFG bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[75] bit 10	GTX_CHANNEL: DRP[75] bit 11	GTX_CHANNEL: DRP[163] bit 10 GTX_CHANNEL: RXPHDLY_CFG bit 10	GTX_CHANNEL: DRP[163] bit 11 GTX_CHANNEL: RXPHDLY_CFG bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[75] bit 8 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 8	GTX_CHANNEL: DRP[75] bit 9 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 9	GTX_CHANNEL: DRP[163] bit 8 GTX_CHANNEL: RXPHDLY_CFG bit 8	GTX_CHANNEL: DRP[163] bit 9 GTX_CHANNEL: RXPHDLY_CFG bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[75] bit 6 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 6	GTX_CHANNEL: DRP[75] bit 7 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 7	GTX_CHANNEL: DRP[163] bit 6 GTX_CHANNEL: RXPHDLY_CFG bit 6	GTX_CHANNEL: DRP[163] bit 7 GTX_CHANNEL: RXPHDLY_CFG bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[75] bit 4 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 4	GTX_CHANNEL: DRP[75] bit 5 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 5	GTX_CHANNEL: DRP[163] bit 4 GTX_CHANNEL: RXPHDLY_CFG bit 4	GTX_CHANNEL: DRP[163] bit 5 GTX_CHANNEL: RXPHDLY_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[75] bit 2 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 2	GTX_CHANNEL: DRP[75] bit 3 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 3	GTX_CHANNEL: DRP[163] bit 2 GTX_CHANNEL: RXPHDLY_CFG bit 2	GTX_CHANNEL: DRP[163] bit 3 GTX_CHANNEL: RXPHDLY_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[75] bit 0 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 0	GTX_CHANNEL: DRP[75] bit 1 GTX_CHANNEL: CLK_COR_SEQ_2_4 bit 1	GTX_CHANNEL: DRP[163] bit 0 GTX_CHANNEL: RXPHDLY_CFG bit 0	GTX_CHANNEL: DRP[163] bit 1 GTX_CHANNEL: RXPHDLY_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[74] bit 14	GTX_CHANNEL: DRP[74] bit 15	GTX_CHANNEL: DRP[162] bit 14	GTX_CHANNEL: DRP[162] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[74] bit 12	GTX_CHANNEL: DRP[74] bit 13	GTX_CHANNEL: DRP[162] bit 12	GTX_CHANNEL: DRP[162] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[74] bit 10	GTX_CHANNEL: DRP[74] bit 11	GTX_CHANNEL: DRP[162] bit 10	GTX_CHANNEL: DRP[162] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[74] bit 8 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 8	GTX_CHANNEL: DRP[74] bit 9 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 9	GTX_CHANNEL: DRP[162] bit 8	GTX_CHANNEL: DRP[162] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[74] bit 6 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 6	GTX_CHANNEL: DRP[74] bit 7 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 7	GTX_CHANNEL: DRP[162] bit 6 GTX_CHANNEL: RXPH_CFG bit 22	GTX_CHANNEL: DRP[162] bit 7 GTX_CHANNEL: RXPH_CFG bit 23
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[74] bit 4 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 4	GTX_CHANNEL: DRP[74] bit 5 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 5	GTX_CHANNEL: DRP[162] bit 4 GTX_CHANNEL: RXPH_CFG bit 20	GTX_CHANNEL: DRP[162] bit 5 GTX_CHANNEL: RXPH_CFG bit 21
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[74] bit 2 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 2	GTX_CHANNEL: DRP[74] bit 3 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 3	GTX_CHANNEL: DRP[162] bit 2 GTX_CHANNEL: RXPH_CFG bit 18	GTX_CHANNEL: DRP[162] bit 3 GTX_CHANNEL: RXPH_CFG bit 19
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[74] bit 0 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 0	GTX_CHANNEL: DRP[74] bit 1 GTX_CHANNEL: CLK_COR_SEQ_2_3 bit 1	GTX_CHANNEL: DRP[162] bit 0 GTX_CHANNEL: RXPH_CFG bit 16	GTX_CHANNEL: DRP[162] bit 1 GTX_CHANNEL: RXPH_CFG bit 17
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[73] bit 14 GTX_CHANNEL: CLK_COR_INSERT_IDLE_FLAG	GTX_CHANNEL: DRP[73] bit 15	GTX_CHANNEL: DRP[161] bit 14 GTX_CHANNEL: RXPH_CFG bit 14	GTX_CHANNEL: DRP[161] bit 15 GTX_CHANNEL: RXPH_CFG bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[73] bit 12 GTX_CHANNEL: CLK_COR_PRECEDENCE	GTX_CHANNEL: DRP[73] bit 13 GTX_CHANNEL: CLK_COR_KEEP_IDLE	GTX_CHANNEL: DRP[161] bit 12 GTX_CHANNEL: RXPH_CFG bit 12	GTX_CHANNEL: DRP[161] bit 13 GTX_CHANNEL: RXPH_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[73] bit 10 GTX_CHANNEL: CLK_COR_SEQ_LEN bit 0	GTX_CHANNEL: DRP[73] bit 11 GTX_CHANNEL: CLK_COR_SEQ_LEN bit 1	GTX_CHANNEL: DRP[161] bit 10 GTX_CHANNEL: RXPH_CFG bit 10	GTX_CHANNEL: DRP[161] bit 11 GTX_CHANNEL: RXPH_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[73] bit 8 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 8	GTX_CHANNEL: DRP[73] bit 9 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 9	GTX_CHANNEL: DRP[161] bit 8 GTX_CHANNEL: RXPH_CFG bit 8	GTX_CHANNEL: DRP[161] bit 9 GTX_CHANNEL: RXPH_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[73] bit 6 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 6	GTX_CHANNEL: DRP[73] bit 7 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 7	GTX_CHANNEL: DRP[161] bit 6 GTX_CHANNEL: RXPH_CFG bit 6	GTX_CHANNEL: DRP[161] bit 7 GTX_CHANNEL: RXPH_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[73] bit 4 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 4	GTX_CHANNEL: DRP[73] bit 5 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 5	GTX_CHANNEL: DRP[161] bit 4 GTX_CHANNEL: RXPH_CFG bit 4	GTX_CHANNEL: DRP[161] bit 5 GTX_CHANNEL: RXPH_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[73] bit 2 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 2	GTX_CHANNEL: DRP[73] bit 3 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 3	GTX_CHANNEL: DRP[161] bit 2 GTX_CHANNEL: RXPH_CFG bit 2	GTX_CHANNEL: DRP[161] bit 3 GTX_CHANNEL: RXPH_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[73] bit 0 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 0	GTX_CHANNEL: DRP[73] bit 1 GTX_CHANNEL: CLK_COR_SEQ_2_2 bit 1	GTX_CHANNEL: DRP[161] bit 0 GTX_CHANNEL: RXPH_CFG bit 0	GTX_CHANNEL: DRP[161] bit 1 GTX_CHANNEL: RXPH_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[72] bit 14 GTX_CHANNEL: CLK_COR_SEQ_2_USE	GTX_CHANNEL: DRP[72] bit 15	GTX_CHANNEL: DRP[160] bit 14	GTX_CHANNEL: DRP[160] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[72] bit 12 GTX_CHANNEL: CLK_COR_SEQ_2_ENABLE bit 2	GTX_CHANNEL: DRP[72] bit 13 GTX_CHANNEL: CLK_COR_SEQ_2_ENABLE bit 3	GTX_CHANNEL: DRP[160] bit 12	GTX_CHANNEL: DRP[160] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[72] bit 10 GTX_CHANNEL: CLK_COR_SEQ_2_ENABLE bit 0	GTX_CHANNEL: DRP[72] bit 11 GTX_CHANNEL: CLK_COR_SEQ_2_ENABLE bit 1	GTX_CHANNEL: DRP[160] bit 10	GTX_CHANNEL: DRP[160] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[72] bit 8 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 8	GTX_CHANNEL: DRP[72] bit 9 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 9	GTX_CHANNEL: DRP[160] bit 8 GTX_CHANNEL: RXDLY_LCFG bit 8	GTX_CHANNEL: DRP[160] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[72] bit 6 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 6	GTX_CHANNEL: DRP[72] bit 7 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 7	GTX_CHANNEL: DRP[160] bit 6 GTX_CHANNEL: RXDLY_LCFG bit 6	GTX_CHANNEL: DRP[160] bit 7 GTX_CHANNEL: RXDLY_LCFG bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[72] bit 4 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 4	GTX_CHANNEL: DRP[72] bit 5 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 5	GTX_CHANNEL: DRP[160] bit 4 GTX_CHANNEL: RXDLY_LCFG bit 4	GTX_CHANNEL: DRP[160] bit 5 GTX_CHANNEL: RXDLY_LCFG bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[72] bit 2 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 2	GTX_CHANNEL: DRP[72] bit 3 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 3	GTX_CHANNEL: DRP[160] bit 2 GTX_CHANNEL: RXDLY_LCFG bit 2	GTX_CHANNEL: DRP[160] bit 3 GTX_CHANNEL: RXDLY_LCFG bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[72] bit 0 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 0	GTX_CHANNEL: DRP[72] bit 1 GTX_CHANNEL: CLK_COR_SEQ_2_1 bit 1	GTX_CHANNEL: DRP[160] bit 0 GTX_CHANNEL: RXDLY_LCFG bit 0	GTX_CHANNEL: DRP[160] bit 1 GTX_CHANNEL: RXDLY_LCFG bit 1

virtex7 GTH_CHANNEL rect MAIN[10]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[87] bit 14	GTX_CHANNEL: DRP[87] bit 15	GTX_CHANNEL: DRP[175] bit 14	GTX_CHANNEL: DRP[175] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[87] bit 12 GTX_CHANNEL: RXPH_MONITOR_SEL bit 4	GTX_CHANNEL: DRP[87] bit 13	GTX_CHANNEL: DRP[175] bit 12	GTX_CHANNEL: DRP[175] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[87] bit 10 GTX_CHANNEL: RXPH_MONITOR_SEL bit 2	GTX_CHANNEL: DRP[87] bit 11 GTX_CHANNEL: RXPH_MONITOR_SEL bit 3	GTX_CHANNEL: DRP[175] bit 10	GTX_CHANNEL: DRP[175] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[87] bit 8 GTX_CHANNEL: RXPH_MONITOR_SEL bit 0	GTX_CHANNEL: DRP[87] bit 9 GTX_CHANNEL: RXPH_MONITOR_SEL bit 1	GTX_CHANNEL: DRP[175] bit 8	GTX_CHANNEL: DRP[175] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[87] bit 6	GTX_CHANNEL: DRP[87] bit 7	GTX_CHANNEL: DRP[175] bit 6	GTX_CHANNEL: DRP[175] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[87] bit 4 GTX_CHANNEL: RX_DDI_SEL bit 4	GTX_CHANNEL: DRP[87] bit 5 GTX_CHANNEL: RX_DDI_SEL bit 5	GTX_CHANNEL: DRP[175] bit 4	GTX_CHANNEL: DRP[175] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[87] bit 2 GTX_CHANNEL: RX_DDI_SEL bit 2	GTX_CHANNEL: DRP[87] bit 3 GTX_CHANNEL: RX_DDI_SEL bit 3	GTX_CHANNEL: DRP[175] bit 2	GTX_CHANNEL: DRP[175] bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[87] bit 0 GTX_CHANNEL: RX_DDI_SEL bit 0	GTX_CHANNEL: DRP[87] bit 1 GTX_CHANNEL: RX_DDI_SEL bit 1	GTX_CHANNEL: DRP[175] bit 0	GTX_CHANNEL: DRP[175] bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[86] bit 14	GTX_CHANNEL: DRP[86] bit 15	GTX_CHANNEL: DRP[174] bit 14	GTX_CHANNEL: DRP[174] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[86] bit 12	GTX_CHANNEL: DRP[86] bit 13	GTX_CHANNEL: DRP[174] bit 12	GTX_CHANNEL: DRP[174] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[86] bit 10	GTX_CHANNEL: DRP[86] bit 11	GTX_CHANNEL: DRP[174] bit 10	GTX_CHANNEL: DRP[174] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[86] bit 8	GTX_CHANNEL: DRP[86] bit 9	GTX_CHANNEL: DRP[174] bit 8	GTX_CHANNEL: DRP[174] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[86] bit 6	GTX_CHANNEL: DRP[86] bit 7	GTX_CHANNEL: DRP[174] bit 6	GTX_CHANNEL: DRP[174] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[86] bit 4	GTX_CHANNEL: DRP[86] bit 5	GTX_CHANNEL: DRP[174] bit 4	GTX_CHANNEL: DRP[174] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[86] bit 2	GTX_CHANNEL: DRP[86] bit 3	GTX_CHANNEL: DRP[174] bit 2	GTX_CHANNEL: DRP[174] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[86] bit 0	GTX_CHANNEL: DRP[86] bit 1	GTX_CHANNEL: DRP[174] bit 0	GTX_CHANNEL: DRP[174] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[85] bit 14 GTX_CHANNEL: RXDLY_CFG bit 14	GTX_CHANNEL: DRP[85] bit 15 GTX_CHANNEL: RXDLY_CFG bit 15	GTX_CHANNEL: DRP[173] bit 14	GTX_CHANNEL: DRP[173] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[85] bit 12 GTX_CHANNEL: RXDLY_CFG bit 12	GTX_CHANNEL: DRP[85] bit 13 GTX_CHANNEL: RXDLY_CFG bit 13	GTX_CHANNEL: DRP[173] bit 12 GTX_CHANNEL: A_TXQPIBIASEN bit 0	GTX_CHANNEL: DRP[173] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[85] bit 10 GTX_CHANNEL: RXDLY_CFG bit 10	GTX_CHANNEL: DRP[85] bit 11 GTX_CHANNEL: RXDLY_CFG bit 11	GTX_CHANNEL: DRP[173] bit 10	GTX_CHANNEL: DRP[173] bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[85] bit 8 GTX_CHANNEL: RXDLY_CFG bit 8	GTX_CHANNEL: DRP[85] bit 9 GTX_CHANNEL: RXDLY_CFG bit 9	GTX_CHANNEL: DRP[173] bit 8	GTX_CHANNEL: DRP[173] bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[85] bit 6 GTX_CHANNEL: RXDLY_CFG bit 6	GTX_CHANNEL: DRP[85] bit 7 GTX_CHANNEL: RXDLY_CFG bit 7	GTX_CHANNEL: DRP[173] bit 6	GTX_CHANNEL: DRP[173] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[85] bit 4 GTX_CHANNEL: RXDLY_CFG bit 4	GTX_CHANNEL: DRP[85] bit 5 GTX_CHANNEL: RXDLY_CFG bit 5	GTX_CHANNEL: DRP[173] bit 4	GTX_CHANNEL: DRP[173] bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[85] bit 2 GTX_CHANNEL: RXDLY_CFG bit 2	GTX_CHANNEL: DRP[85] bit 3 GTX_CHANNEL: RXDLY_CFG bit 3	GTX_CHANNEL: DRP[173] bit 2 GTX_CHANNEL: RXCDR_CFG_GTH bit 82	GTX_CHANNEL: DRP[173] bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[85] bit 0 GTX_CHANNEL: RXDLY_CFG bit 0	GTX_CHANNEL: DRP[85] bit 1 GTX_CHANNEL: RXDLY_CFG bit 1	GTX_CHANNEL: DRP[173] bit 0 GTX_CHANNEL: RXCDR_CFG_GTH bit 80	GTX_CHANNEL: DRP[173] bit 1 GTX_CHANNEL: RXCDR_CFG_GTH bit 81
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[84] bit 14 GTX_CHANNEL: RXDLY_TAP_CFG bit 14	GTX_CHANNEL: DRP[84] bit 15 GTX_CHANNEL: RXDLY_TAP_CFG bit 15	GTX_CHANNEL: DRP[172] bit 14 GTX_CHANNEL: RXCDR_CFG_GTH bit 78	GTX_CHANNEL: DRP[172] bit 15 GTX_CHANNEL: RXCDR_CFG_GTH bit 79
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[84] bit 12 GTX_CHANNEL: RXDLY_TAP_CFG bit 12	GTX_CHANNEL: DRP[84] bit 13 GTX_CHANNEL: RXDLY_TAP_CFG bit 13	GTX_CHANNEL: DRP[172] bit 12 GTX_CHANNEL: RXCDR_CFG_GTH bit 76	GTX_CHANNEL: DRP[172] bit 13 GTX_CHANNEL: RXCDR_CFG_GTH bit 77
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[84] bit 10 GTX_CHANNEL: RXDLY_TAP_CFG bit 10	GTX_CHANNEL: DRP[84] bit 11 GTX_CHANNEL: RXDLY_TAP_CFG bit 11	GTX_CHANNEL: DRP[172] bit 10 GTX_CHANNEL: RXCDR_CFG_GTH bit 74	GTX_CHANNEL: DRP[172] bit 11 GTX_CHANNEL: RXCDR_CFG_GTH bit 75
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[84] bit 8 GTX_CHANNEL: RXDLY_TAP_CFG bit 8	GTX_CHANNEL: DRP[84] bit 9 GTX_CHANNEL: RXDLY_TAP_CFG bit 9	GTX_CHANNEL: DRP[172] bit 8 GTX_CHANNEL: RXCDR_CFG_GTH bit 72	GTX_CHANNEL: DRP[172] bit 9 GTX_CHANNEL: RXCDR_CFG_GTH bit 73
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[84] bit 6 GTX_CHANNEL: RXDLY_TAP_CFG bit 6	GTX_CHANNEL: DRP[84] bit 7 GTX_CHANNEL: RXDLY_TAP_CFG bit 7	GTX_CHANNEL: DRP[172] bit 6 GTX_CHANNEL: RXCDR_CFG_GTH bit 70	GTX_CHANNEL: DRP[172] bit 7 GTX_CHANNEL: RXCDR_CFG_GTH bit 71
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[84] bit 4 GTX_CHANNEL: RXDLY_TAP_CFG bit 4	GTX_CHANNEL: DRP[84] bit 5 GTX_CHANNEL: RXDLY_TAP_CFG bit 5	GTX_CHANNEL: DRP[172] bit 4 GTX_CHANNEL: RXCDR_CFG_GTH bit 68	GTX_CHANNEL: DRP[172] bit 5 GTX_CHANNEL: RXCDR_CFG_GTH bit 69
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[84] bit 2 GTX_CHANNEL: RXDLY_TAP_CFG bit 2	GTX_CHANNEL: DRP[84] bit 3 GTX_CHANNEL: RXDLY_TAP_CFG bit 3	GTX_CHANNEL: DRP[172] bit 2 GTX_CHANNEL: RXCDR_CFG_GTH bit 66	GTX_CHANNEL: DRP[172] bit 3 GTX_CHANNEL: RXCDR_CFG_GTH bit 67
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[84] bit 0 GTX_CHANNEL: RXDLY_TAP_CFG bit 0	GTX_CHANNEL: DRP[84] bit 1 GTX_CHANNEL: RXDLY_TAP_CFG bit 1	GTX_CHANNEL: DRP[172] bit 0 GTX_CHANNEL: RXCDR_CFG_GTH bit 64	GTX_CHANNEL: DRP[172] bit 1 GTX_CHANNEL: RXCDR_CFG_GTH bit 65
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[83] bit 14 GTX_CHANNEL: CHAN_BOND_MAX_SKEW bit 2	GTX_CHANNEL: DRP[83] bit 15 GTX_CHANNEL: CHAN_BOND_MAX_SKEW bit 3	GTX_CHANNEL: DRP[171] bit 14 GTX_CHANNEL: RXCDR_CFG_GTH bit 62	GTX_CHANNEL: DRP[171] bit 15 GTX_CHANNEL: RXCDR_CFG_GTH bit 63
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[83] bit 12 GTX_CHANNEL: CHAN_BOND_MAX_SKEW bit 0	GTX_CHANNEL: DRP[83] bit 13 GTX_CHANNEL: CHAN_BOND_MAX_SKEW bit 1	GTX_CHANNEL: DRP[171] bit 12 GTX_CHANNEL: RXCDR_CFG_GTH bit 60	GTX_CHANNEL: DRP[171] bit 13 GTX_CHANNEL: RXCDR_CFG_GTH bit 61
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[83] bit 10	GTX_CHANNEL: DRP[83] bit 11	GTX_CHANNEL: DRP[171] bit 10 GTX_CHANNEL: RXCDR_CFG_GTH bit 58	GTX_CHANNEL: DRP[171] bit 11 GTX_CHANNEL: RXCDR_CFG_GTH bit 59
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[83] bit 8 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 8	GTX_CHANNEL: DRP[83] bit 9 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 9	GTX_CHANNEL: DRP[171] bit 8 GTX_CHANNEL: RXCDR_CFG_GTH bit 56	GTX_CHANNEL: DRP[171] bit 9 GTX_CHANNEL: RXCDR_CFG_GTH bit 57
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[83] bit 6 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 6	GTX_CHANNEL: DRP[83] bit 7 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 7	GTX_CHANNEL: DRP[171] bit 6 GTX_CHANNEL: RXCDR_CFG_GTH bit 54	GTX_CHANNEL: DRP[171] bit 7 GTX_CHANNEL: RXCDR_CFG_GTH bit 55
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[83] bit 4 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 4	GTX_CHANNEL: DRP[83] bit 5 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 5	GTX_CHANNEL: DRP[171] bit 4 GTX_CHANNEL: RXCDR_CFG_GTH bit 52	GTX_CHANNEL: DRP[171] bit 5 GTX_CHANNEL: RXCDR_CFG_GTH bit 53
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[83] bit 2 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 2	GTX_CHANNEL: DRP[83] bit 3 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 3	GTX_CHANNEL: DRP[171] bit 2 GTX_CHANNEL: RXCDR_CFG_GTH bit 50	GTX_CHANNEL: DRP[171] bit 3 GTX_CHANNEL: RXCDR_CFG_GTH bit 51
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[83] bit 0 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 0	GTX_CHANNEL: DRP[83] bit 1 GTX_CHANNEL: CHAN_BOND_SEQ_2_4 bit 1	GTX_CHANNEL: DRP[171] bit 0 GTX_CHANNEL: RXCDR_CFG_GTH bit 48	GTX_CHANNEL: DRP[171] bit 1 GTX_CHANNEL: RXCDR_CFG_GTH bit 49
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[82] bit 14 GTX_CHANNEL: FTS_DESKEW_SEQ_ENABLE bit 2	GTX_CHANNEL: DRP[82] bit 15 GTX_CHANNEL: FTS_DESKEW_SEQ_ENABLE bit 3	GTX_CHANNEL: DRP[170] bit 14 GTX_CHANNEL: RXCDR_CFG_GTH bit 46	GTX_CHANNEL: DRP[170] bit 15 GTX_CHANNEL: RXCDR_CFG_GTH bit 47
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[82] bit 12 GTX_CHANNEL: FTS_DESKEW_SEQ_ENABLE bit 0	GTX_CHANNEL: DRP[82] bit 13 GTX_CHANNEL: FTS_DESKEW_SEQ_ENABLE bit 1	GTX_CHANNEL: DRP[170] bit 12 GTX_CHANNEL: RXCDR_CFG_GTH bit 44	GTX_CHANNEL: DRP[170] bit 13 GTX_CHANNEL: RXCDR_CFG_GTH bit 45
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[82] bit 10	GTX_CHANNEL: DRP[82] bit 11 GTX_CHANNEL: CBCC_DATA_SOURCE_SEL bit 0	GTX_CHANNEL: DRP[170] bit 10 GTX_CHANNEL: RXCDR_CFG_GTH bit 42	GTX_CHANNEL: DRP[170] bit 11 GTX_CHANNEL: RXCDR_CFG_GTH bit 43
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[82] bit 8 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 8	GTX_CHANNEL: DRP[82] bit 9 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 9	GTX_CHANNEL: DRP[170] bit 8 GTX_CHANNEL: RXCDR_CFG_GTH bit 40	GTX_CHANNEL: DRP[170] bit 9 GTX_CHANNEL: RXCDR_CFG_GTH bit 41
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[82] bit 6 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 6	GTX_CHANNEL: DRP[82] bit 7 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 7	GTX_CHANNEL: DRP[170] bit 6 GTX_CHANNEL: RXCDR_CFG_GTH bit 38	GTX_CHANNEL: DRP[170] bit 7 GTX_CHANNEL: RXCDR_CFG_GTH bit 39
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[82] bit 4 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 4	GTX_CHANNEL: DRP[82] bit 5 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 5	GTX_CHANNEL: DRP[170] bit 4 GTX_CHANNEL: RXCDR_CFG_GTH bit 36	GTX_CHANNEL: DRP[170] bit 5 GTX_CHANNEL: RXCDR_CFG_GTH bit 37
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[82] bit 2 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 2	GTX_CHANNEL: DRP[82] bit 3 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 3	GTX_CHANNEL: DRP[170] bit 2 GTX_CHANNEL: RXCDR_CFG_GTH bit 34	GTX_CHANNEL: DRP[170] bit 3 GTX_CHANNEL: RXCDR_CFG_GTH bit 35
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[82] bit 0 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 0	GTX_CHANNEL: DRP[82] bit 1 GTX_CHANNEL: CHAN_BOND_SEQ_2_3 bit 1	GTX_CHANNEL: DRP[170] bit 0 GTX_CHANNEL: RXCDR_CFG_GTH bit 32	GTX_CHANNEL: DRP[170] bit 1 GTX_CHANNEL: RXCDR_CFG_GTH bit 33
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[81] bit 14 GTX_CHANNEL: FTS_LANE_DESKEW_CFG bit 2	GTX_CHANNEL: DRP[81] bit 15 GTX_CHANNEL: FTS_LANE_DESKEW_CFG bit 3	GTX_CHANNEL: DRP[169] bit 14 GTX_CHANNEL: RXCDR_CFG_GTH bit 30	GTX_CHANNEL: DRP[169] bit 15 GTX_CHANNEL: RXCDR_CFG_GTH bit 31
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[81] bit 12 GTX_CHANNEL: FTS_LANE_DESKEW_CFG bit 0	GTX_CHANNEL: DRP[81] bit 13 GTX_CHANNEL: FTS_LANE_DESKEW_CFG bit 1	GTX_CHANNEL: DRP[169] bit 12 GTX_CHANNEL: RXCDR_CFG_GTH bit 28	GTX_CHANNEL: DRP[169] bit 13 GTX_CHANNEL: RXCDR_CFG_GTH bit 29
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[81] bit 10	GTX_CHANNEL: DRP[81] bit 11 GTX_CHANNEL: FTS_LANE_DESKEW_EN	GTX_CHANNEL: DRP[169] bit 10 GTX_CHANNEL: RXCDR_CFG_GTH bit 26	GTX_CHANNEL: DRP[169] bit 11 GTX_CHANNEL: RXCDR_CFG_GTH bit 27
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[81] bit 8 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 8	GTX_CHANNEL: DRP[81] bit 9 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 9	GTX_CHANNEL: DRP[169] bit 8 GTX_CHANNEL: RXCDR_CFG_GTH bit 24	GTX_CHANNEL: DRP[169] bit 9 GTX_CHANNEL: RXCDR_CFG_GTH bit 25
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[81] bit 6 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 6	GTX_CHANNEL: DRP[81] bit 7 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 7	GTX_CHANNEL: DRP[169] bit 6 GTX_CHANNEL: RXCDR_CFG_GTH bit 22	GTX_CHANNEL: DRP[169] bit 7 GTX_CHANNEL: RXCDR_CFG_GTH bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[81] bit 4 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 4	GTX_CHANNEL: DRP[81] bit 5 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 5	GTX_CHANNEL: DRP[169] bit 4 GTX_CHANNEL: RXCDR_CFG_GTH bit 20	GTX_CHANNEL: DRP[169] bit 5 GTX_CHANNEL: RXCDR_CFG_GTH bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[81] bit 2 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 2	GTX_CHANNEL: DRP[81] bit 3 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 3	GTX_CHANNEL: DRP[169] bit 2 GTX_CHANNEL: RXCDR_CFG_GTH bit 18	GTX_CHANNEL: DRP[169] bit 3 GTX_CHANNEL: RXCDR_CFG_GTH bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[81] bit 0 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 0	GTX_CHANNEL: DRP[81] bit 1 GTX_CHANNEL: CHAN_BOND_SEQ_2_2 bit 1	GTX_CHANNEL: DRP[169] bit 0 GTX_CHANNEL: RXCDR_CFG_GTH bit 16	GTX_CHANNEL: DRP[169] bit 1 GTX_CHANNEL: RXCDR_CFG_GTH bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[80] bit 14 GTX_CHANNEL: CHAN_BOND_SEQ_2_ENABLE bit 2	GTX_CHANNEL: DRP[80] bit 15 GTX_CHANNEL: CHAN_BOND_SEQ_2_ENABLE bit 3	GTX_CHANNEL: DRP[168] bit 14 GTX_CHANNEL: RXCDR_CFG_GTH bit 14	GTX_CHANNEL: DRP[168] bit 15 GTX_CHANNEL: RXCDR_CFG_GTH bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[80] bit 12 GTX_CHANNEL: CHAN_BOND_SEQ_2_ENABLE bit 0	GTX_CHANNEL: DRP[80] bit 13 GTX_CHANNEL: CHAN_BOND_SEQ_2_ENABLE bit 1	GTX_CHANNEL: DRP[168] bit 12 GTX_CHANNEL: RXCDR_CFG_GTH bit 12	GTX_CHANNEL: DRP[168] bit 13 GTX_CHANNEL: RXCDR_CFG_GTH bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[80] bit 10	GTX_CHANNEL: DRP[80] bit 11 GTX_CHANNEL: CHAN_BOND_SEQ_2_USE	GTX_CHANNEL: DRP[168] bit 10 GTX_CHANNEL: RXCDR_CFG_GTH bit 10	GTX_CHANNEL: DRP[168] bit 11 GTX_CHANNEL: RXCDR_CFG_GTH bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[80] bit 8 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 8	GTX_CHANNEL: DRP[80] bit 9 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 9	GTX_CHANNEL: DRP[168] bit 8 GTX_CHANNEL: RXCDR_CFG_GTH bit 8	GTX_CHANNEL: DRP[168] bit 9 GTX_CHANNEL: RXCDR_CFG_GTH bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[80] bit 6 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 6	GTX_CHANNEL: DRP[80] bit 7 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 7	GTX_CHANNEL: DRP[168] bit 6 GTX_CHANNEL: RXCDR_CFG_GTH bit 6	GTX_CHANNEL: DRP[168] bit 7 GTX_CHANNEL: RXCDR_CFG_GTH bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[80] bit 4 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 4	GTX_CHANNEL: DRP[80] bit 5 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 5	GTX_CHANNEL: DRP[168] bit 4 GTX_CHANNEL: RXCDR_CFG_GTH bit 4	GTX_CHANNEL: DRP[168] bit 5 GTX_CHANNEL: RXCDR_CFG_GTH bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[80] bit 2 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 2	GTX_CHANNEL: DRP[80] bit 3 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 3	GTX_CHANNEL: DRP[168] bit 2 GTX_CHANNEL: RXCDR_CFG_GTH bit 2	GTX_CHANNEL: DRP[168] bit 3 GTX_CHANNEL: RXCDR_CFG_GTH bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_CHANNEL: DRP[80] bit 0 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 0	GTX_CHANNEL: DRP[80] bit 1 GTX_CHANNEL: CHAN_BOND_SEQ_2_1 bit 1	GTX_CHANNEL: DRP[168] bit 0 GTX_CHANNEL: RXCDR_CFG_GTH bit 0	GTX_CHANNEL: DRP[168] bit 1 GTX_CHANNEL: RXCDR_CFG_GTH bit 1

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