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Configurable Logic Block

Tile CLB

Cells: 3

Switchbox INT

xc4000xla CLB switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H_BUF[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[1][1]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[4][7]MAIN[4][9]MAIN[3][6]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
0001111111111111CELL.SPECIAL_CLB_COUT0
0010011111111111CELL.LONG_H[4]
0010111011111111CELL.SINGLE_H[4]
0010111101111111CELL.LONG_H[5]
0011001111111111CELL.SINGLE_H[2]
0011010111111111CELL.SINGLE_H[3]
0011101011111111CELL.SINGLE_H[7]
0011101101111111CELL.DOUBLE_H0[0]
0011110011111111CELL_N.LONG_H_BUF[2]
0011110101111111CELL.SINGLE_H[6]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110011110CELL_E.LONG_V[9]
0011111110100111CELL.QUAD_H1[2]
0011111110101111CELL.QUAD_H1[0]
0011111110110111CELL.QUAD_H1[1]
0011111110111110CELL_E.LONG_V[6]
0011111111000111CELL.QUAD_H2[2]
0011111111001111CELL.QUAD_H2[0]
0011111111010111CELL.QUAD_H2[1]
0011111111011110CELL_E.LONG_V[8]
0011111111100111CELL.QUAD_H3[2]
0011111111101111CELL.QUAD_H3[0]
0011111111110111CELL.QUAD_H3[1]
0011111111111011CELL.OUT_CLB_X_S
0011111111111101CELL.OUT_CLB_XQ_S
0011111111111110CELL_E.GCLK[7]
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL_N.LONG_H[0]
0111110111111111CELL.DOUBLE_H1[0]
1011011111111111CELL.DOUBLE_H1[1]
1011111011111111CELL.SINGLE_H[5]
1011111101111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[0]
xc4000xla CLB switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[31][1]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
0001111111111111111CELL.SPECIAL_CLB_CIN
0010011111111111111CELL.SINGLE_V[0]
0010101111111111111CELL.SINGLE_V[2]
0010111011111111111CELL.SINGLE_V[4]
0011010111111111111CELL.LONG_V[4]
0011011101111111111CELL.LONG_V[2]
0011100111111111111CELL.SINGLE_V[1]
0011101101111111111CELL.SINGLE_V[6]
0011110011111111111CELL.DOUBLE_V0[1]
0011111001111111111CELL.LONG_V[5]
0011111110011111111CELL.QUAD_V0[0]
0011111110101111111CELL.QUAD_V0[1]
0011111110110111111CELL.QUAD_V0[2]
0011111111011011111CELL.QUAD_V1[0]
0011111111011101111CELL.QUAD_V2[0]
0011111111011110111CELL.QUAD_V3[0]
0011111111101011111CELL.QUAD_V1[1]
0011111111101101111CELL.QUAD_V2[1]
0011111111101110111CELL.QUAD_V3[1]
0011111111110011111CELL.QUAD_V1[2]
0011111111110101111CELL.QUAD_V2[2]
0011111111110110111CELL.QUAD_V3[2]
0011111111111111011CELL.GCLK[0]
0011111111111111101CELL.OUT_CLB_Y_E
0011111111111111110CELL.OUT_CLB_YQ_E
0111011111111111111CELL.DOUBLE_V0[0]
0111101111111111111CELL.SINGLE_V[5]
0111111011111111111CELL.DOUBLE_V1[0]
1010111111111111111CELL.DOUBLE_V1[1]
1011110111111111111CELL.LONG_V[1]
1011111101111111111CELL.SINGLE_V[7]
1111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[1][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H_BUF[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H_BUF[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][11]!MAIN[20][10]

Bel wires

xc4000xla CLB bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_G2 bit 15 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 18 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB rect MAIN_W
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB rect MAIN_E
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_W

Cells: 3

Switchbox INT

xc4000xla CLB_W switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB_W switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB_W switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB_W switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB_W switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB_W switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB_W switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H_BUF[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[8][3]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[4][7]MAIN[4][9]MAIN[3][6]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
0001111111111111CELL.SPECIAL_CLB_COUT0
0010011111111111CELL.LONG_H[4]
0010111011111111CELL.SINGLE_H[4]
0010111101111111CELL.LONG_H[5]
0011001111111111CELL.SINGLE_H[2]
0011010111111111CELL.SINGLE_H[3]
0011101011111111CELL.SINGLE_H[7]
0011101101111111CELL.DOUBLE_H0[0]
0011110011111111CELL_N.LONG_H_BUF[2]
0011110101111111CELL.SINGLE_H[6]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110011110CELL_E.LONG_V[9]
0011111110100111CELL.QUAD_H1[2]
0011111110101111CELL.QUAD_H1[0]
0011111110110111CELL.QUAD_H1[1]
0011111110111110CELL_E.LONG_V[6]
0011111111000111CELL.QUAD_H2[2]
0011111111001111CELL.QUAD_H2[0]
0011111111010111CELL.QUAD_H2[1]
0011111111011110CELL_E.LONG_V[8]
0011111111100111CELL.QUAD_H3[2]
0011111111101111CELL.QUAD_H3[0]
0011111111110111CELL.QUAD_H3[1]
0011111111111011CELL.OUT_CLB_X_S
0011111111111101CELL.OUT_CLB_XQ_S
0011111111111110CELL_E.GCLK[7]
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL_N.LONG_H[0]
0111110111111111CELL.DOUBLE_H1[0]
1011011111111111CELL.DOUBLE_H1[1]
1011111011111111CELL.SINGLE_H[5]
1011111101111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[0]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[2]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.SINGLE_V[6]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[5]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[0]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.DOUBLE_V0[0]
011101111111111111CELL.SINGLE_V[5]
011111011111111111CELL.DOUBLE_V1[0]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[7]
111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[9][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H_BUF[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H_BUF[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB_W switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB_W switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_W switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_W switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB_W switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB_W bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB_W bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB_W enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB_W enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB_W enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB_W enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB_W enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB_W enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB_W enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB_W enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB_W enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB_W enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB_W enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB_W enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB_W enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB_W enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB_W enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB_W enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB_W enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB_W bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB_W bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][11]!MAIN[20][10]

Bel wires

xc4000xla CLB_W bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB_W rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_G2 bit 15 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 - INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB_W rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_W rect MAIN_W
BitFrame
F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 - - - - - - - -
B2 - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_W rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_W rect MAIN_E
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_E

Cells: 3

Switchbox INT

xc4000xla CLB_E switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB_E switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB_E switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB_E switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB_E switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB_E switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB_E switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H_BUF[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[1][1]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[4][7]MAIN[4][9]MAIN[3][6]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
0001111111111111CELL.SPECIAL_CLB_COUT0
0010011111111111CELL.LONG_H[4]
0010111011111111CELL.SINGLE_H[4]
0010111101111111CELL.LONG_H[5]
0011001111111111CELL.SINGLE_H[2]
0011010111111111CELL.SINGLE_H[3]
0011101011111111CELL.SINGLE_H[7]
0011101101111111CELL.DOUBLE_H0[0]
0011110011111111CELL_N.LONG_H_BUF[2]
0011110101111111CELL.SINGLE_H[6]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110011110CELL_E.LONG_V[9]
0011111110100111CELL.QUAD_H1[2]
0011111110101111CELL.QUAD_H1[0]
0011111110110111CELL.QUAD_H1[1]
0011111110111110CELL_E.LONG_V[6]
0011111111000111CELL.QUAD_H2[2]
0011111111001111CELL.QUAD_H2[0]
0011111111010111CELL.QUAD_H2[1]
0011111111011110CELL_E.LONG_V[8]
0011111111100111CELL.QUAD_H3[2]
0011111111101111CELL.QUAD_H3[0]
0011111111110111CELL.QUAD_H3[1]
0011111111111011CELL.OUT_CLB_X_S
0011111111111101CELL.OUT_CLB_XQ_S
0011111111111110CELL_E.GCLK[7]
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL_N.LONG_H[0]
0111110111111111CELL.DOUBLE_H1[0]
1011011111111111CELL.DOUBLE_H1[1]
1011111011111111CELL.SINGLE_H[5]
1011111101111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[0]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[31][1]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
0001111111111111111CELL.SPECIAL_CLB_CIN
0010011111111111111CELL.SINGLE_V[0]
0010101111111111111CELL.SINGLE_V[2]
0010111011111111111CELL.SINGLE_V[4]
0011010111111111111CELL.LONG_V[4]
0011011101111111111CELL.LONG_V[2]
0011100111111111111CELL.SINGLE_V[1]
0011101101111111111CELL.SINGLE_V[6]
0011110011111111111CELL.DOUBLE_V0[1]
0011111001111111111CELL.LONG_V[5]
0011111110011111111CELL.QUAD_V0[0]
0011111110101111111CELL.QUAD_V0[1]
0011111110110111111CELL.QUAD_V0[2]
0011111111011011111CELL.QUAD_V1[0]
0011111111011101111CELL.QUAD_V2[0]
0011111111011110111CELL.QUAD_V3[0]
0011111111101011111CELL.QUAD_V1[1]
0011111111101101111CELL.QUAD_V2[1]
0011111111101110111CELL.QUAD_V3[1]
0011111111110011111CELL.QUAD_V1[2]
0011111111110101111CELL.QUAD_V2[2]
0011111111110110111CELL.QUAD_V3[2]
0011111111111111011CELL.GCLK[0]
0011111111111111101CELL.OUT_CLB_Y_E
0011111111111111110CELL.OUT_CLB_YQ_E
0111011111111111111CELL.DOUBLE_V0[0]
0111101111111111111CELL.SINGLE_V[5]
0111111011111111111CELL.DOUBLE_V1[0]
1010111111111111111CELL.DOUBLE_V1[1]
1011110111111111111CELL.LONG_V[1]
1011111101111111111CELL.SINGLE_V[7]
1111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[1][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H_BUF[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H_BUF[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB_E switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB_E switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_E switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_E switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB_E switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB_E bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB_E bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB_E enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB_E enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB_E enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB_E enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB_E enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB_E enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB_E enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB_E enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB_E enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB_E enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB_E enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB_E enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB_E enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB_E enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB_E enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB_E enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB_E enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB_E bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB_E bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][11]!MAIN[20][10]

Bel wires

xc4000xla CLB_E bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB_E rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_G2 bit 15 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 18 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB_E rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_E rect MAIN_W
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_E rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_E rect MAIN_E
BitFrame
F51 F50 F49 F48 F47 F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_S

Cells: 3

Switchbox INT

xc4000xla CLB_S switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB_S switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][12]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][12]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB_S switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][12]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][12]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][13]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB_S switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB_S switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB_S switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB_S switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H_BUF[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[1][1]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[4][7]MAIN[4][9]MAIN[3][6]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
0001111111111111CELL.SPECIAL_CLB_COUT0
0010011111111111CELL.LONG_H[4]
0010111011111111CELL.SINGLE_H[4]
0010111101111111CELL.LONG_H[5]
0011001111111111CELL.SINGLE_H[2]
0011010111111111CELL.SINGLE_H[3]
0011101011111111CELL.SINGLE_H[7]
0011101101111111CELL.DOUBLE_H0[0]
0011110011111111CELL_N.LONG_H_BUF[2]
0011110101111111CELL.SINGLE_H[6]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110011110CELL_E.LONG_V[9]
0011111110100111CELL.QUAD_H1[2]
0011111110101111CELL.QUAD_H1[0]
0011111110110111CELL.QUAD_H1[1]
0011111110111110CELL_E.LONG_V[6]
0011111111000111CELL.QUAD_H2[2]
0011111111001111CELL.QUAD_H2[0]
0011111111010111CELL.QUAD_H2[1]
0011111111011110CELL_E.LONG_V[8]
0011111111100111CELL.QUAD_H3[2]
0011111111101111CELL.QUAD_H3[0]
0011111111110111CELL.QUAD_H3[1]
0011111111111011CELL.OUT_CLB_X_S
0011111111111101CELL.OUT_CLB_XQ_S
0011111111111110CELL_E.GCLK[7]
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL_N.LONG_H[0]
0111110111111111CELL.DOUBLE_H1[0]
1011011111111111CELL.DOUBLE_H1[1]
1011111011111111CELL.SINGLE_H[5]
1011111101111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[0]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[31][1]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
0001111111111111111CELL.SPECIAL_CLB_CIN
0010011111111111111CELL.SINGLE_V[0]
0010101111111111111CELL.SINGLE_V[2]
0010111011111111111CELL.SINGLE_V[4]
0011010111111111111CELL.LONG_V[4]
0011011101111111111CELL.LONG_V[2]
0011100111111111111CELL.SINGLE_V[1]
0011101101111111111CELL.SINGLE_V[6]
0011110011111111111CELL.DOUBLE_V0[1]
0011111001111111111CELL.LONG_V[5]
0011111110011111111CELL.QUAD_V0[0]
0011111110101111111CELL.QUAD_V0[1]
0011111110110111111CELL.QUAD_V0[2]
0011111111011011111CELL.QUAD_V1[0]
0011111111011101111CELL.QUAD_V2[0]
0011111111011110111CELL.QUAD_V3[0]
0011111111101011111CELL.QUAD_V1[1]
0011111111101101111CELL.QUAD_V2[1]
0011111111101110111CELL.QUAD_V3[1]
0011111111110011111CELL.QUAD_V1[2]
0011111111110101111CELL.QUAD_V2[2]
0011111111110110111CELL.QUAD_V3[2]
0011111111111111011CELL.GCLK[0]
0011111111111111101CELL.OUT_CLB_Y_E
0011111111111111110CELL.OUT_CLB_YQ_E
0111011111111111111CELL.DOUBLE_V0[0]
0111101111111111111CELL.SINGLE_V[5]
0111111011111111111CELL.DOUBLE_V1[0]
1010111111111111111CELL.DOUBLE_V1[1]
1011110111111111111CELL.LONG_V[1]
1011111101111111111CELL.SINGLE_V[7]
1111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[1][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H_BUF[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H_BUF[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB_S switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB_S switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_S switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_S switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB_S switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB_S bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB_S bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB_S enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB_S enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB_S enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB_S enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB_S enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB_S enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB_S enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB_S enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB_S enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB_S enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB_S enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB_S enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB_S enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB_S enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB_S enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB_S enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB_S enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB_S bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB_S bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][15]!MAIN[20][10]

Bel wires

xc4000xla CLB_S bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB_S rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_G2 bit 15 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 18 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB_S rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_S rect MAIN_W
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_S rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_S rect MAIN_E
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_SW

Cells: 3

Switchbox INT

xc4000xla CLB_SW switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB_SW switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][12]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][12]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB_SW switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][12]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][12]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][13]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB_SW switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB_SW switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB_SW switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB_SW switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H_BUF[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[8][3]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[4][7]MAIN[4][9]MAIN[3][6]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
0001111111111111CELL.SPECIAL_CLB_COUT0
0010011111111111CELL.LONG_H[4]
0010111011111111CELL.SINGLE_H[4]
0010111101111111CELL.LONG_H[5]
0011001111111111CELL.SINGLE_H[2]
0011010111111111CELL.SINGLE_H[3]
0011101011111111CELL.SINGLE_H[7]
0011101101111111CELL.DOUBLE_H0[0]
0011110011111111CELL_N.LONG_H_BUF[2]
0011110101111111CELL.SINGLE_H[6]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110011110CELL_E.LONG_V[9]
0011111110100111CELL.QUAD_H1[2]
0011111110101111CELL.QUAD_H1[0]
0011111110110111CELL.QUAD_H1[1]
0011111110111110CELL_E.LONG_V[6]
0011111111000111CELL.QUAD_H2[2]
0011111111001111CELL.QUAD_H2[0]
0011111111010111CELL.QUAD_H2[1]
0011111111011110CELL_E.LONG_V[8]
0011111111100111CELL.QUAD_H3[2]
0011111111101111CELL.QUAD_H3[0]
0011111111110111CELL.QUAD_H3[1]
0011111111111011CELL.OUT_CLB_X_S
0011111111111101CELL.OUT_CLB_XQ_S
0011111111111110CELL_E.GCLK[7]
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL_N.LONG_H[0]
0111110111111111CELL.DOUBLE_H1[0]
1011011111111111CELL.DOUBLE_H1[1]
1011111011111111CELL.SINGLE_H[5]
1011111101111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[0]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[2]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.SINGLE_V[6]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[5]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[0]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.DOUBLE_V0[0]
011101111111111111CELL.SINGLE_V[5]
011111011111111111CELL.DOUBLE_V1[0]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[7]
111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[9][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H_BUF[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H_BUF[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB_SW switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB_SW switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_SW switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_SW switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB_SW switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB_SW bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB_SW bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB_SW enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB_SW enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB_SW enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB_SW enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB_SW enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB_SW enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB_SW enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB_SW enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB_SW enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB_SW enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB_SW enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB_SW enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB_SW enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB_SW enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB_SW enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB_SW enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB_SW enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB_SW bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB_SW bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][15]!MAIN[20][10]

Bel wires

xc4000xla CLB_SW bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB_SW rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_G2 bit 15 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 - INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB_SW rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_SW rect MAIN_W
BitFrame
F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 - - - - - - - -
B2 - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_SW rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_SW rect MAIN_E
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_SE

Cells: 3

Switchbox INT

xc4000xla CLB_SE switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB_SE switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][12]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][12]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB_SE switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][12]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][12]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][13]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB_SE switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB_SE switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB_SE switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB_SE switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H_BUF[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[1][1]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[4][7]MAIN[4][9]MAIN[3][6]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
0001111111111111CELL.SPECIAL_CLB_COUT0
0010011111111111CELL.LONG_H[4]
0010111011111111CELL.SINGLE_H[4]
0010111101111111CELL.LONG_H[5]
0011001111111111CELL.SINGLE_H[2]
0011010111111111CELL.SINGLE_H[3]
0011101011111111CELL.SINGLE_H[7]
0011101101111111CELL.DOUBLE_H0[0]
0011110011111111CELL_N.LONG_H_BUF[2]
0011110101111111CELL.SINGLE_H[6]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110011110CELL_E.LONG_V[9]
0011111110100111CELL.QUAD_H1[2]
0011111110101111CELL.QUAD_H1[0]
0011111110110111CELL.QUAD_H1[1]
0011111110111110CELL_E.LONG_V[6]
0011111111000111CELL.QUAD_H2[2]
0011111111001111CELL.QUAD_H2[0]
0011111111010111CELL.QUAD_H2[1]
0011111111011110CELL_E.LONG_V[8]
0011111111100111CELL.QUAD_H3[2]
0011111111101111CELL.QUAD_H3[0]
0011111111110111CELL.QUAD_H3[1]
0011111111111011CELL.OUT_CLB_X_S
0011111111111101CELL.OUT_CLB_XQ_S
0011111111111110CELL_E.GCLK[7]
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL_N.LONG_H[0]
0111110111111111CELL.DOUBLE_H1[0]
1011011111111111CELL.DOUBLE_H1[1]
1011111011111111CELL.SINGLE_H[5]
1011111101111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[0]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[31][1]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
0001111111111111111CELL.SPECIAL_CLB_CIN
0010011111111111111CELL.SINGLE_V[0]
0010101111111111111CELL.SINGLE_V[2]
0010111011111111111CELL.SINGLE_V[4]
0011010111111111111CELL.LONG_V[4]
0011011101111111111CELL.LONG_V[2]
0011100111111111111CELL.SINGLE_V[1]
0011101101111111111CELL.SINGLE_V[6]
0011110011111111111CELL.DOUBLE_V0[1]
0011111001111111111CELL.LONG_V[5]
0011111110011111111CELL.QUAD_V0[0]
0011111110101111111CELL.QUAD_V0[1]
0011111110110111111CELL.QUAD_V0[2]
0011111111011011111CELL.QUAD_V1[0]
0011111111011101111CELL.QUAD_V2[0]
0011111111011110111CELL.QUAD_V3[0]
0011111111101011111CELL.QUAD_V1[1]
0011111111101101111CELL.QUAD_V2[1]
0011111111101110111CELL.QUAD_V3[1]
0011111111110011111CELL.QUAD_V1[2]
0011111111110101111CELL.QUAD_V2[2]
0011111111110110111CELL.QUAD_V3[2]
0011111111111111011CELL.GCLK[0]
0011111111111111101CELL.OUT_CLB_Y_E
0011111111111111110CELL.OUT_CLB_YQ_E
0111011111111111111CELL.DOUBLE_V0[0]
0111101111111111111CELL.SINGLE_V[5]
0111111011111111111CELL.DOUBLE_V1[0]
1010111111111111111CELL.DOUBLE_V1[1]
1011110111111111111CELL.LONG_V[1]
1011111101111111111CELL.SINGLE_V[7]
1111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[1][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H_BUF[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H_BUF[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB_SE switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB_SE switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_SE switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_SE switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB_SE switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB_SE bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB_SE bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB_SE enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB_SE enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB_SE enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB_SE enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB_SE enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB_SE enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB_SE enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB_SE enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB_SE enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB_SE enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB_SE enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB_SE enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB_SE enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB_SE enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB_SE enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB_SE enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB_SE enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB_SE bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB_SE bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][15]!MAIN[20][10]

Bel wires

xc4000xla CLB_SE bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB_SE rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_G2 bit 15 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 18 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB_SE rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_SE rect MAIN_W
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_SE rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_SE rect MAIN_E
BitFrame
F51 F50 F49 F48 F47 F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_N

Cells: 3

Switchbox INT

xc4000xla CLB_N switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB_N switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB_N switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB_N switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB_N switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB_N switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB_N switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[1][1]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[3][6]MAIN[4][7]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
000011111111111CELL.LONG_H[4]
000111011111111CELL.SINGLE_H[4]
000111101111111CELL.LONG_H[5]
001111111111111CELL.SINGLE_H[1]
010001111111111CELL.SINGLE_H[2]
010010111111111CELL.SINGLE_H[3]
010101011111111CELL.SINGLE_H[7]
010101101111111CELL.DOUBLE_H0[0]
010110011111111CELL_N.LONG_H[2]
010110101111111CELL.SINGLE_H[6]
010111110000111CELL.QUAD_H0[2]
010111110001111CELL.QUAD_H0[0]
010111110010111CELL.QUAD_H0[1]
010111110011110CELL_E.LONG_V[9]
010111110100111CELL.QUAD_H1[2]
010111110101111CELL.QUAD_H1[0]
010111110110111CELL.QUAD_H1[1]
010111110111110CELL_E.LONG_V[6]
010111111000111CELL.QUAD_H2[2]
010111111001111CELL.QUAD_H2[0]
010111111010111CELL.QUAD_H2[1]
010111111011110CELL_E.LONG_V[8]
010111111100111CELL.QUAD_H3[2]
010111111101111CELL.QUAD_H3[0]
010111111110111CELL.QUAD_H3[1]
010111111111011CELL.OUT_CLB_X_S
010111111111101CELL.OUT_CLB_XQ_S
010111111111110CELL_E.GCLK[7]
011101111111111CELL_N.LONG_H[0]
011110111111111CELL.DOUBLE_H1[0]
110011111111111CELL.DOUBLE_H1[1]
110111011111111CELL.SINGLE_H[5]
110111101111111CELL.DOUBLE_H0[1]
111111111111111CELL.SINGLE_H[0]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[31][1]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
0001111111111111111CELL.SPECIAL_CLB_CIN
0010011111111111111CELL.SINGLE_V[0]
0010101111111111111CELL.SINGLE_V[2]
0010111011111111111CELL.SINGLE_V[4]
0011010111111111111CELL.LONG_V[4]
0011011101111111111CELL.LONG_V[2]
0011100111111111111CELL.SINGLE_V[1]
0011101101111111111CELL.SINGLE_V[6]
0011110011111111111CELL.DOUBLE_V0[1]
0011111001111111111CELL.LONG_V[5]
0011111110011111111CELL.QUAD_V0[0]
0011111110101111111CELL.QUAD_V0[1]
0011111110110111111CELL.QUAD_V0[2]
0011111111011011111CELL.QUAD_V1[0]
0011111111011101111CELL.QUAD_V2[0]
0011111111011110111CELL.QUAD_V3[0]
0011111111101011111CELL.QUAD_V1[1]
0011111111101101111CELL.QUAD_V2[1]
0011111111101110111CELL.QUAD_V3[1]
0011111111110011111CELL.QUAD_V1[2]
0011111111110101111CELL.QUAD_V2[2]
0011111111110110111CELL.QUAD_V3[2]
0011111111111111011CELL.GCLK[0]
0011111111111111101CELL.OUT_CLB_Y_E
0011111111111111110CELL.OUT_CLB_YQ_E
0111011111111111111CELL.DOUBLE_V0[0]
0111101111111111111CELL.SINGLE_V[5]
0111111011111111111CELL.DOUBLE_V1[0]
1010111111111111111CELL.DOUBLE_V1[1]
1011110111111111111CELL.LONG_V[1]
1011111101111111111CELL.SINGLE_V[7]
1111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[1][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB_N switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB_N switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_N switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_N switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB_N switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB_N bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB_N bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB_N enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB_N enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB_N enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB_N enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB_N enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB_N enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB_N enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB_N enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB_N enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB_N enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB_N enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB_N enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB_N enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB_N enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB_N enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB_N enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB_N enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB_N bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB_N bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][11]!MAIN[20][10]

Bel wires

xc4000xla CLB_N bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB_N rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 - INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 18 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB_N rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_N rect MAIN_W
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_N rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_N rect MAIN_E
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_NW

Cells: 3

Switchbox INT

xc4000xla CLB_NW switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB_NW switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB_NW switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB_NW switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB_NW switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB_NW switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB_NW switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[8][3]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[3][6]MAIN[4][7]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
000011111111111CELL.LONG_H[4]
000111011111111CELL.SINGLE_H[4]
000111101111111CELL.LONG_H[5]
001111111111111CELL.SINGLE_H[1]
010001111111111CELL.SINGLE_H[2]
010010111111111CELL.SINGLE_H[3]
010101011111111CELL.SINGLE_H[7]
010101101111111CELL.DOUBLE_H0[0]
010110011111111CELL_N.LONG_H[2]
010110101111111CELL.SINGLE_H[6]
010111110000111CELL.QUAD_H0[2]
010111110001111CELL.QUAD_H0[0]
010111110010111CELL.QUAD_H0[1]
010111110011110CELL_E.LONG_V[9]
010111110100111CELL.QUAD_H1[2]
010111110101111CELL.QUAD_H1[0]
010111110110111CELL.QUAD_H1[1]
010111110111110CELL_E.LONG_V[6]
010111111000111CELL.QUAD_H2[2]
010111111001111CELL.QUAD_H2[0]
010111111010111CELL.QUAD_H2[1]
010111111011110CELL_E.LONG_V[8]
010111111100111CELL.QUAD_H3[2]
010111111101111CELL.QUAD_H3[0]
010111111110111CELL.QUAD_H3[1]
010111111111011CELL.OUT_CLB_X_S
010111111111101CELL.OUT_CLB_XQ_S
010111111111110CELL_E.GCLK[7]
011101111111111CELL_N.LONG_H[0]
011110111111111CELL.DOUBLE_H1[0]
110011111111111CELL.DOUBLE_H1[1]
110111011111111CELL.SINGLE_H[5]
110111101111111CELL.DOUBLE_H0[1]
111111111111111CELL.SINGLE_H[0]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[2]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.SINGLE_V[6]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[5]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[0]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.DOUBLE_V0[0]
011101111111111111CELL.SINGLE_V[5]
011111011111111111CELL.DOUBLE_V1[0]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[7]
111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[9][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB_NW switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB_NW switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_NW switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_NW switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB_NW switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB_NW bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB_NW bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB_NW enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB_NW enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB_NW enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB_NW enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB_NW enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB_NW enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB_NW enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB_NW enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB_NW enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB_NW enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB_NW enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB_NW enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB_NW enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB_NW enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB_NW enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB_NW enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB_NW enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB_NW bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB_NW bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][11]!MAIN[20][10]

Bel wires

xc4000xla CLB_NW bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB_NW rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 - INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 - INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB_NW rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_NW rect MAIN_W
BitFrame
F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 - - - - - - - -
B2 - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_NW rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_NW rect MAIN_E
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_NE

Cells: 3

Switchbox INT

xc4000xla CLB_NE switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
CELL.OUT_CLB_X_HCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_HCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_HCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_HCELL.OUT_CLB_YQ
CELL.OUT_CLB_X_VCELL.OUT_CLB_X
CELL.OUT_CLB_XQ_VCELL.OUT_CLB_XQ
CELL.OUT_CLB_Y_VCELL.OUT_CLB_Y
CELL.OUT_CLB_YQ_VCELL.OUT_CLB_YQ
xc4000xla CLB_NE switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[22][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[26][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[34][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[36][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[28][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[34][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[30][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[30][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[27][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[31][8]
CELL.LONG_V[6]CELL.SINGLE_H_E[0]!MAIN[39][7]
CELL.LONG_V[7]CELL.SINGLE_H_E[3]!MAIN[38][7]
CELL.LONG_V[8]CELL.SINGLE_H_E[4]!MAIN[44][7]
CELL.LONG_V[9]CELL.SINGLE_H_E[7]!MAIN[45][7]
xc4000xla CLB_NE switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y_V!MAIN[3][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ_V!MAIN[7][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[12][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[29][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y_V!MAIN[2][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[23][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ_V!MAIN[1][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[14][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[30][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[16][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.SINGLE_H_E[0]CELL.LONG_V[6]!MAIN[42][7]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[28][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[36][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[35][7]
CELL.SINGLE_H_E[3]CELL.LONG_V[7]!MAIN[37][7]
CELL.SINGLE_H_E[4]CELL.LONG_V[8]!MAIN[43][6]
CELL.SINGLE_H_E[7]CELL.LONG_V[9]!MAIN[44][6]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ_H!MAIN[24][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[24][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X_H!MAIN[25][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[30][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[29][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[31][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ_H!MAIN[35][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[36][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X_H!MAIN[32][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[36][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[35][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[22][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[34][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y_V!MAIN[11][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[16][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ_V!MAIN[16][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[22][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X_H!MAIN[33][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[27][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ_H!MAIN[36][4]
CELL.QUAD_H0[0]CELL.QBUF[0]!MAIN[40][10]
CELL.QUAD_H0[0]CELL.OUT_CLB_YQ_V!MAIN[19][10]
CELL.QUAD_H0[1]CELL.QBUF[1]!MAIN[37][9]
CELL.QUAD_H0[1]CELL.OUT_CLB_X_S!MAIN[10][10]
CELL.QUAD_H0[2]CELL.QBUF[2]!MAIN[46][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_Y_V!MAIN[6][10]
CELL.QUAD_H0[2]CELL.OUT_CLB_XQ_S!MAIN[11][11]
CELL.QUAD_H3[0]CELL.OUT_CLB_Y_V!MAIN[7][10]
CELL.QUAD_H3[1]CELL.OUT_CLB_XQ_S!MAIN[12][11]
CELL.QUAD_H3[2]CELL.OUT_CLB_YQ_V!MAIN[18][10]
CELL.QUAD_H3[2]CELL.OUT_CLB_X_S!MAIN[11][10]
CELL.QUAD_H4[0]CELL.QBUF[0]!MAIN[39][10]
CELL.QUAD_H4[1]CELL.QBUF[1]!MAIN[39][9]
CELL.QUAD_H4[2]CELL.QBUF[2]!MAIN[45][10]
CELL.QUAD_V0[0]CELL.QBUF[0]!MAIN[41][10]
CELL.QUAD_V0[0]CELL.OUT_CLB_X_H!MAIN[42][4]
CELL.QUAD_V0[1]CELL.QBUF[1]!MAIN[37][10]
CELL.QUAD_V0[1]CELL.OUT_CLB_YQ_E!MAIN[45][4]
CELL.QUAD_V0[2]CELL.QBUF[2]!MAIN[46][11]
CELL.QUAD_V0[2]CELL.OUT_CLB_XQ_H!MAIN[37][0]
CELL.QUAD_V0[2]CELL.OUT_CLB_Y_E!MAIN[40][4]
CELL.QUAD_V3[0]CELL.OUT_CLB_XQ_H!MAIN[38][0]
CELL.QUAD_V3[1]CELL.OUT_CLB_Y_E!MAIN[41][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_X_H!MAIN[43][4]
CELL.QUAD_V3[2]CELL.OUT_CLB_YQ_E!MAIN[44][4]
CELL.QUAD_V4[0]CELL.QBUF[0]!MAIN[38][10]
CELL.QUAD_V4[1]CELL.QBUF[1]!MAIN[38][9]
CELL.QUAD_V4[2]CELL.QBUF[2]!MAIN[44][10]
xc4000xla CLB_NE switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[24][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[23][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[26][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[25][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[29][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[27][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[32][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[31][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[32][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[31][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[32][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[34][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[31][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[33][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[24][5]
CELL.SINGLE_H_E[0]CELL.QUAD_V1[0]!MAIN[43][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[26][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[27][5]
CELL.SINGLE_H_E[1]CELL.QUAD_V3[0]!MAIN[41][7]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[27][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.QUAD_V2[0]!MAIN[37][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[29][7]
CELL.SINGLE_H_E[3]CELL.QUAD_V0[1]!MAIN[45][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[35][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_H_E[4]CELL.QUAD_V0[2]!MAIN[40][7]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_H_E[5]CELL.QUAD_V1[1]!MAIN[42][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[30][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_H_E[6]CELL.QUAD_V3[2]!MAIN[43][8]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[33][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[35][9]
CELL.SINGLE_H_E[7]CELL.QUAD_V2[2]!MAIN[38][8]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[25][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[27][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[26][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[34][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[34][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[32][9]
CELL.SINGLE_V_S[0]CELL.QUAD_H2[0]!MAIN[22][10]
CELL.SINGLE_V_S[1]CELL.QUAD_H0[0]!MAIN[25][10]
CELL.SINGLE_V_S[2]CELL.QUAD_H2[1]!MAIN[25][11]
CELL.SINGLE_V_S[3]CELL.QUAD_H1[1]!MAIN[33][11]
CELL.SINGLE_V_S[4]CELL.QUAD_H0[1]!MAIN[33][10]
CELL.SINGLE_V_S[5]CELL.QUAD_H3[2]!MAIN[32][10]
CELL.SINGLE_V_S[6]CELL.QUAD_H2[2]!MAIN[34][10]
CELL.SINGLE_V_S[7]CELL.QUAD_H1[2]!MAIN[32][11]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[29][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
CELL.DOUBLE_H1[1]CELL.QUAD_V3[1]!MAIN[40][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[25][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[25][8]
CELL.DOUBLE_H2[0]CELL.QUAD_V0[0]!MAIN[39][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[29][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[30][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[30][3]
CELL.DOUBLE_V1[1]CELL.QUAD_H0[2]!MAIN[31][10]
CELL.DOUBLE_V2[0]CELL.QUAD_H3[0]!MAIN[21][10]
CELL.QUAD_H0[0]CELL.QUAD_H4[0]!MAIN[38][11]
CELL.QUAD_H0[0]CELL.QUAD_V0[0]!MAIN[39][11]
CELL.QUAD_H0[0]CELL.QUAD_V4[0]!MAIN[35][11]
CELL.QUAD_H0[1]CELL.QUAD_H4[1]!MAIN[44][8]
CELL.QUAD_H0[1]CELL.QUAD_V0[1]!MAIN[42][9]
CELL.QUAD_H0[1]CELL.QUAD_V4[1]!MAIN[43][9]
CELL.QUAD_H0[2]CELL.QUAD_H4[2]!MAIN[44][11]
CELL.QUAD_H0[2]CELL.QUAD_V0[2]!MAIN[45][11]
CELL.QUAD_H0[2]CELL.QUAD_V4[2]!MAIN[41][11]
CELL.QUAD_H4[0]CELL.QUAD_V0[0]!MAIN[37][11]
CELL.QUAD_H4[0]CELL.QUAD_V4[0]!MAIN[36][11]
CELL.QUAD_H4[1]CELL.QUAD_V0[1]!MAIN[45][9]
CELL.QUAD_H4[1]CELL.QUAD_V4[1]!MAIN[46][9]
CELL.QUAD_H4[2]CELL.QUAD_V0[2]!MAIN[43][11]
CELL.QUAD_H4[2]CELL.QUAD_V4[2]!MAIN[42][11]
CELL.QUAD_V0[0]CELL.QUAD_V4[0]!MAIN[34][11]
CELL.QUAD_V0[1]CELL.QUAD_V4[1]!MAIN[44][9]
CELL.QUAD_V0[2]CELL.QUAD_V4[2]!MAIN[40][11]
xc4000xla CLB_NE switchbox INT muxes QBUF[0]
BitsDestination
MAIN[35][10]MAIN[36][10]CELL.QBUF[0]
Source
00CELL.QUAD_V4[0]
01CELL.QUAD_V0[0]
10CELL.QUAD_H0[0]
11CELL.QUAD_H4[0]
xc4000xla CLB_NE switchbox INT muxes QBUF[1]
BitsDestination
MAIN[40][9]MAIN[41][9]CELL.QBUF[1]
Source
00CELL.QUAD_V4[1]
01CELL.QUAD_V0[1]
10CELL.QUAD_H0[1]
11CELL.QUAD_H4[1]
xc4000xla CLB_NE switchbox INT muxes QBUF[2]
BitsDestination
MAIN[42][10]MAIN[43][10]CELL.QBUF[2]
Source
00CELL.QUAD_V4[2]
01CELL.QUAD_V0[2]
10CELL.QUAD_H0[2]
11CELL.QUAD_H4[2]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[27][2]MAIN[29][0]MAIN[28][1]MAIN[27][0]MAIN[28][3]MAIN[27][1]MAIN[28][0]MAIN[28][2]MAIN[42][2]MAIN[46][0]MAIN[37][1]MAIN[44][2]MAIN[41][2]MAIN[41][3]MAIN[42][3]MAIN[37][4]MAIN[38][6]MAIN[37][6]CELL.IMUX_CLB_F1
Source
001001111111111111CELL.SINGLE_V[3]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.SINGLE_V[7]
001111111111111111CELL.SINGLE_V[0]
010001111111111111CELL.LONG_V[3]
010010111111111111CELL.DOUBLE_V0[1]
010011101111111111CELL.LONG_V[0]
010111111111111111CELL.SINGLE_V[1]
011001011111111111CELL.SINGLE_V[5]
011010011111111111CELL.LONG_V[1]
011011001111111111CELL.SINGLE_V[6]
011011110011111111CELL.QUAD_V0[0]
011011110101111111CELL.QUAD_V0[1]
011011110110111111CELL.QUAD_V0[2]
011011111011011111CELL.QUAD_V1[0]
011011111011101111CELL.QUAD_V2[0]
011011111011110111CELL.QUAD_V3[0]
011011111101011111CELL.QUAD_V1[1]
011011111101101111CELL.QUAD_V2[1]
011011111101110111CELL.QUAD_V3[1]
011011111110011111CELL.QUAD_V1[2]
011011111110101111CELL.QUAD_V2[2]
011011111110110111CELL.QUAD_V3[2]
011011111111111011CELL.GCLK[1]
011011111111111101CELL.OUT_CLB_Y_E
011011111111111110CELL.OUT_CLB_YQ_E
011111011111111111CELL.DOUBLE_V1[1]
111001111111111111CELL.DOUBLE_V1[0]
111010111111111111CELL.SINGLE_V[4]
111011101111111111CELL.DOUBLE_V0[0]
111111111111111111CELL.SINGLE_V[2]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[11][9]MAIN[11][7]MAIN[12][6]MAIN[12][8]MAIN[12][9]MAIN[13][8]MAIN[13][7]MAIN[13][6]MAIN[15][11]MAIN[16][10]MAIN[17][10]MAIN[16][11]MAIN[12][10]MAIN[10][11]MAIN[17][11]CELL.IMUX_CLB_F2
Source
001100111111111CELL.SINGLE_H[5]
001101011111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H1[1]
001111111111111CELL.SINGLE_H[0]
010100111111111CELL.SINGLE_H[4]
010101011111111CELL.DOUBLE_H0[1]
010101101111111CELL.LONG_H[4]
010111111111111CELL.SINGLE_H[1]
011000111111111CELL.SINGLE_H[6]
011001011111111CELL_N.LONG_H[2]
011001101111111CELL_N.LONG_H[0]
011011111111111CELL.SINGLE_H[3]
011101110000111CELL.QUAD_H0[2]
011101110001111CELL.QUAD_H0[0]
011101110010111CELL.QUAD_H0[1]
011101110011110CELL_E.LONG_V[9]
011101110100111CELL.QUAD_H2[2]
011101110101111CELL.QUAD_H2[0]
011101110110111CELL.QUAD_H2[1]
011101110111110CELL_E.LONG_V[7]
011101111000111CELL.QUAD_H3[2]
011101111001111CELL.QUAD_H3[0]
011101111010111CELL.QUAD_H3[1]
011101111011110CELL_E.GCLK[7]
011101111100111CELL.QUAD_H1[2]
011101111101111CELL.QUAD_H1[0]
011101111110111CELL.QUAD_H1[1]
011101111111011CELL.OUT_CLB_X_S
011101111111101CELL.OUT_CLB_XQ_S
011101111111110CELL_E.LONG_V[8]
111100111111111CELL.DOUBLE_H0[0]
111101011111111CELL.SINGLE_H[7]
111101101111111CELL.DOUBLE_H1[0]
111111111111111CELL.SINGLE_H[2]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[34][2]MAIN[36][0]MAIN[35][2]MAIN[36][1]MAIN[34][0]MAIN[35][1]MAIN[36][2]MAIN[35][0]MAIN[43][1]MAIN[39][0]MAIN[39][1]MAIN[38][1]MAIN[40][0]MAIN[40][1]MAIN[43][0]MAIN[36][3]MAIN[41][5]MAIN[42][5]CELL.IMUX_CLB_F3
Source
000011111111111111CELL.SINGLE_V[0]
000111011111111111CELL.DOUBLE_V0[0]
000111101111111111CELL.LONG_V[2]
001111111111111111CELL.SINGLE_V[3]
010001111111111111CELL.DOUBLE_V1[1]
010010111111111111CELL.LONG_V[1]
010101011111111111CELL.DOUBLE_V0[1]
010101101111111111CELL.LONG_V[5]
010110011111111111CELL.SINGLE_V[4]
010110101111111111CELL.LONG_V[4]
010111110011111111CELL.QUAD_V0[0]
010111110101111111CELL.QUAD_V0[1]
010111110110111111CELL.QUAD_V0[2]
010111111011011111CELL.QUAD_V1[0]
010111111011101111CELL.QUAD_V2[0]
010111111011110111CELL.QUAD_V3[0]
010111111101011111CELL.QUAD_V1[1]
010111111101101111CELL.QUAD_V2[1]
010111111101110111CELL.QUAD_V3[1]
010111111110011111CELL.QUAD_V1[2]
010111111110101111CELL.QUAD_V2[2]
010111111110110111CELL.QUAD_V3[2]
010111111111111011CELL.GCLK[0]
010111111111111101CELL.OUT_CLB_Y_E
010111111111111110CELL.OUT_CLB_YQ_E
011101111111111111CELL.SINGLE_V[1]
011110111111111111CELL.SINGLE_V[2]
110011111111111111CELL.SINGLE_V[6]
110111011111111111CELL.DOUBLE_V1[0]
110111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[7]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[10][7]MAIN[9][6]MAIN[10][6]MAIN[10][8]MAIN[9][7]MAIN[11][6]MAIN[9][9]MAIN[10][9]MAIN[11][8]MAIN[29][11]MAIN[29][10]MAIN[30][10]MAIN[30][11]MAIN[31][11]MAIN[14][10]MAIN[14][11]CELL.IMUX_CLB_F4
Source
0001111111111111CELL.SPECIAL_CLB_CIN
0010011111111111CELL.SINGLE_H[0]
0010110111111111CELL.DOUBLE_H1[0]
0010111011111111CELL_N.LONG_H[0]
0011001111111111CELL.LONG_H[5]
0011011101111111CELL.LONG_H_BUF[3]
0011100111111111CELL.SINGLE_H[2]
0011101011111111CELL.SINGLE_H[3]
0011110101111111CELL.SINGLE_H[7]
0011111001111111CELL_N.LONG_H[1]
0011111110000111CELL.QUAD_H0[2]
0011111110001111CELL.QUAD_H0[0]
0011111110010111CELL.QUAD_H0[1]
0011111110100111CELL.QUAD_H2[2]
0011111110101111CELL.QUAD_H2[0]
0011111110110111CELL.QUAD_H2[1]
0011111110111011CELL.LONG_V[7]
0011111111000111CELL.QUAD_H3[2]
0011111111001111CELL.QUAD_H3[0]
0011111111010111CELL.QUAD_H3[1]
0011111111011011CELL.LONG_V[9]
0011111111100111CELL.QUAD_H1[2]
0011111111101111CELL.QUAD_H1[0]
0011111111110111CELL.QUAD_H1[1]
0011111111111011CELL.GCLK[4]
0011111111111101CELL.OUT_CLB_X_S
0011111111111110CELL.OUT_CLB_XQ_S
0110111111111111CELL.SINGLE_H[1]
0111101111111111CELL.DOUBLE_H1[1]
0111111101111111CELL.DOUBLE_H0[1]
1011011111111111CELL.SINGLE_H[5]
1011110111111111CELL.DOUBLE_H0[0]
1011111011111111CELL.SINGLE_H[6]
1111111111111111CELL.SINGLE_H[4]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[22][0]MAIN[22][3]MAIN[24][0]MAIN[24][1]MAIN[23][1]MAIN[22][1]MAIN[23][0]MAIN[22][2]MAIN_W[1][1]MAIN[39][4]MAIN[38][4]MAIN[38][3]MAIN[41][6]MAIN[39][3]MAIN[45][5]MAIN[23][2]MAIN[40][5]MAIN[39][5]CELL.IMUX_CLB_G1
Source
000011111111111111CELL.SINGLE_V[0]
000101111111111111CELL.SINGLE_V[2]
000111011111111111CELL.SINGLE_V[4]
001010111111111111CELL.LONG_V[4]
001011101111111111CELL.LONG_V[3]
001100111111111111CELL.SINGLE_V[1]
001101101111111111CELL.DOUBLE_V1[0]
001110011111111111CELL.DOUBLE_V0[1]
001111001111111111CELL.LONG_V[0]
001111110011111111CELL.QUAD_V0[0]
001111110101111111CELL.QUAD_V0[1]
001111110110111111CELL.QUAD_V0[2]
001111111011011111CELL.QUAD_V1[0]
001111111011101111CELL.QUAD_V2[0]
001111111011110111CELL.QUAD_V3[0]
001111111101011111CELL.QUAD_V1[1]
001111111101101111CELL.QUAD_V2[1]
001111111101110111CELL.QUAD_V3[1]
001111111110011111CELL.QUAD_V1[2]
001111111110101111CELL.QUAD_V2[2]
001111111110110111CELL.QUAD_V3[2]
001111111111111011CELL.GCLK[1]
001111111111111101CELL.OUT_CLB_Y_E
001111111111111110CELL.OUT_CLB_YQ_E
011011111111111111CELL.SINGLE_V[3]
011101111111111111CELL.DOUBLE_V0[0]
011111011111111111CELL.SINGLE_V[7]
100111111111111111CELL.DOUBLE_V1[1]
101110111111111111CELL.LONG_V[1]
101111101111111111CELL.SINGLE_V[5]
111111111111111111CELL.SINGLE_V[6]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[3][7]MAIN[3][6]MAIN[4][7]MAIN[4][8]MAIN[3][8]MAIN[3][9]MAIN[4][6]MAIN[5][8]MAIN[4][10]MAIN[4][11]MAIN[5][10]MAIN[5][11]MAIN[9][10]MAIN[7][11]MAIN[6][11]CELL.IMUX_CLB_G2
Source
000011111111111CELL.LONG_H[4]
000111011111111CELL.SINGLE_H[4]
000111101111111CELL.LONG_H[5]
001111111111111CELL.SINGLE_H[1]
010001111111111CELL.SINGLE_H[2]
010010111111111CELL.SINGLE_H[3]
010101011111111CELL.SINGLE_H[7]
010101101111111CELL.DOUBLE_H0[0]
010110011111111CELL_N.LONG_H[2]
010110101111111CELL.SINGLE_H[6]
010111110000111CELL.QUAD_H0[2]
010111110001111CELL.QUAD_H0[0]
010111110010111CELL.QUAD_H0[1]
010111110011110CELL_E.LONG_V[9]
010111110100111CELL.QUAD_H1[2]
010111110101111CELL.QUAD_H1[0]
010111110110111CELL.QUAD_H1[1]
010111110111110CELL_E.LONG_V[6]
010111111000111CELL.QUAD_H2[2]
010111111001111CELL.QUAD_H2[0]
010111111010111CELL.QUAD_H2[1]
010111111011110CELL_E.LONG_V[8]
010111111100111CELL.QUAD_H3[2]
010111111101111CELL.QUAD_H3[0]
010111111110111CELL.QUAD_H3[1]
010111111111011CELL.OUT_CLB_X_S
010111111111101CELL.OUT_CLB_XQ_S
010111111111110CELL_E.GCLK[7]
011101111111111CELL_N.LONG_H[0]
011110111111111CELL.DOUBLE_H1[0]
110011111111111CELL.DOUBLE_H1[1]
110111011111111CELL.SINGLE_H[5]
110111101111111CELL.DOUBLE_H0[1]
111111111111111CELL.SINGLE_H[0]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[30][0]MAIN[29][2]MAIN[31][1]MAIN[29][1]MAIN[30][2]MAIN[31][0]MAIN[30][1]MAIN[31][2]MAIN[31][3]MAIN[43][2]MAIN[37][2]MAIN[39][2]MAIN[38][2]MAIN[40][3]MAIN[40][2]MAIN[46][1]MAIN[37][3]MAIN[43][5]MAIN[44][5]CELL.IMUX_CLB_G3
Source
0001111111111111111CELL.SPECIAL_CLB_CIN
0010011111111111111CELL.SINGLE_V[0]
0010101111111111111CELL.SINGLE_V[2]
0010111011111111111CELL.SINGLE_V[4]
0011010111111111111CELL.LONG_V[4]
0011011101111111111CELL.LONG_V[2]
0011100111111111111CELL.SINGLE_V[1]
0011101101111111111CELL.SINGLE_V[6]
0011110011111111111CELL.DOUBLE_V0[1]
0011111001111111111CELL.LONG_V[5]
0011111110011111111CELL.QUAD_V0[0]
0011111110101111111CELL.QUAD_V0[1]
0011111110110111111CELL.QUAD_V0[2]
0011111111011011111CELL.QUAD_V1[0]
0011111111011101111CELL.QUAD_V2[0]
0011111111011110111CELL.QUAD_V3[0]
0011111111101011111CELL.QUAD_V1[1]
0011111111101101111CELL.QUAD_V2[1]
0011111111101110111CELL.QUAD_V3[1]
0011111111110011111CELL.QUAD_V1[2]
0011111111110101111CELL.QUAD_V2[2]
0011111111110110111CELL.QUAD_V3[2]
0011111111111111011CELL.GCLK[0]
0011111111111111101CELL.OUT_CLB_Y_E
0011111111111111110CELL.OUT_CLB_YQ_E
0111011111111111111CELL.DOUBLE_V0[0]
0111101111111111111CELL.SINGLE_V[5]
0111111011111111111CELL.DOUBLE_V1[0]
1010111111111111111CELL.DOUBLE_V1[1]
1011110111111111111CELL.LONG_V[1]
1011111101111111111CELL.SINGLE_V[7]
1111111111111111111CELL.SINGLE_V[3]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[6][9]MAIN[5][9]MAIN[7][8]MAIN[5][6]MAIN[5][7]MAIN[6][7]MAIN[6][8]MAIN[6][6]MAIN[23][10]MAIN[22][11]MAIN[24][10]MAIN[23][11]MAIN[24][11]MAIN[13][10]MAIN[9][11]CELL.IMUX_CLB_G4
Source
000011111111111CELL.SINGLE_H[0]
000101111111111CELL.SINGLE_H[1]
000111011111111CELL_N.LONG_H[0]
001010111111111CELL.DOUBLE_H1[1]
001011101111111CELL.LONG_H_BUF[3]
001100111111111CELL.LONG_H[5]
001101101111111CELL.DOUBLE_H0[1]
001110011111111CELL.SINGLE_H[3]
001111001111111CELL.SINGLE_H[6]
001111110000111CELL.QUAD_H0[2]
001111110001111CELL.QUAD_H0[0]
001111110010111CELL.QUAD_H0[1]
001111110100111CELL.QUAD_H1[2]
001111110101111CELL.QUAD_H1[0]
001111110110111CELL.QUAD_H1[1]
001111110111011CELL.LONG_V[6]
001111111000111CELL.QUAD_H2[2]
001111111001111CELL.QUAD_H2[0]
001111111010111CELL.QUAD_H2[1]
001111111011011CELL.LONG_V[9]
001111111100111CELL.QUAD_H3[2]
001111111101111CELL.QUAD_H3[0]
001111111110111CELL.QUAD_H3[1]
001111111111011CELL.GCLK[4]
001111111111101CELL.OUT_CLB_X_S
001111111111110CELL.OUT_CLB_XQ_S
010111111111111CELL.DOUBLE_H1[0]
011110111111111CELL.SINGLE_H[2]
011111101111111CELL.DOUBLE_H0[0]
101011111111111CELL.SINGLE_H[5]
101101111111111CELL.SINGLE_H[4]
101111011111111CELL_N.LONG_H[1]
111111111111111CELL.SINGLE_H[7]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[24][3]MAIN[24][2]MAIN[26][1]MAIN[25][0]MAIN[25][1]MAIN[26][2]MAIN[25][2]MAIN[44][3]MAIN_W[1][2]MAIN[46][3]MAIN[46][2]MAIN[43][3]MAIN[42][6]MAIN[45][6]MAIN[26][0]MAIN[38][5]MAIN[37][5]CELL.IMUX_CLB_C1
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[1]
00011111111111011CELL.GCLK[3]
00101011111111111CELL.DOUBLE_V0[0]
00101101111111111CELL.DOUBLE_V1[0]
00110011111111111CELL.SINGLE_V[3]
00110101111111111CELL.SINGLE_V[7]
00111011111111011CELL.LONG_V[2]
00111101111111011CELL.LONG_V[3]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[2]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[1][7]MAIN[1][6]MAIN[2][7]MAIN[2][9]MAIN[1][8]MAIN[1][9]MAIN[2][6]MAIN[2][8]MAIN[1][10]MAIN[1][11]MAIN[2][10]MAIN[2][11]MAIN[8][10]MAIN[8][11]MAIN[3][11]MAIN[3][10]CELL.IMUX_CLB_C2
Source
0000111111111111CELL.LONG_H[4]
0001110111111111CELL.SINGLE_H[5]
0001111011111111CELL.LONG_H_BUF[3]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.SINGLE_H[2]
0100101111111111CELL.SINGLE_H[3]
0101010111111111CELL.SINGLE_H[7]
0101011011111111CELL.DOUBLE_H0[0]
0101100111111111CELL_N.LONG_H[1]
0101101011111111CELL.SINGLE_H[6]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100111101CELL_E.LONG_V[5]
0101111101001111CELL.QUAD_H1[2]
0101111101011111CELL.QUAD_H1[0]
0101111101101111CELL.QUAD_H1[1]
0101111101111101CELL_E.LONG_V[1]
0101111110001111CELL.QUAD_H2[2]
0101111110011111CELL.QUAD_H2[0]
0101111110101111CELL.QUAD_H2[1]
0101111110111101CELL_E.LONG_V[8]
0101111111001111CELL.QUAD_H3[2]
0101111111011111CELL.QUAD_H3[0]
0101111111101111CELL.QUAD_H3[1]
0101111111110111CELL.OUT_CLB_X_S
0101111111111011CELL.OUT_CLB_XQ_S
0101111111111101CELL_E.LONG_V[7]
0101111111111110CELL_E.GCLK[6]
0111011111111111CELL.DOUBLE_H1[0]
0111101111111111CELL_N.LONG_H[2]
1100111111111111CELL.DOUBLE_H1[1]
1101110111111111CELL.SINGLE_H[4]
1101111011111111CELL.DOUBLE_H0[1]
1111111111111111CELL.SINGLE_H[1]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[32][0]MAIN[32][1]MAIN[33][1]MAIN[33][0]MAIN[32][2]MAIN[33][2]MAIN[33][3]MAIN[42][1]MAIN[44][0]MAIN[45][0]MAIN[44][1]MAIN[41][1]MAIN[41][0]MAIN[42][0]MAIN[34][1]MAIN[40][6]MAIN[39][6]CELL.IMUX_CLB_C3
Source
00001111111111111CELL.SINGLE_V[0]
00010111111111111CELL.SINGLE_V[2]
00011111111111011CELL.GCLK[2]
00101011111111111CELL.SINGLE_V[3]
00101101111111111CELL.SINGLE_V[7]
00110011111111111CELL.DOUBLE_V0[0]
00110101111111111CELL.DOUBLE_V1[0]
00111011111111011CELL.LONG_V[3]
00111101111111011CELL.LONG_V[2]
00111110011111111CELL.QUAD_V0[0]
00111110101111111CELL.QUAD_V0[1]
00111110110111111CELL.QUAD_V0[2]
00111111011011111CELL.QUAD_V1[0]
00111111011101111CELL.QUAD_V2[0]
00111111011110111CELL.QUAD_V3[0]
00111111101011111CELL.QUAD_V1[1]
00111111101101111CELL.QUAD_V2[1]
00111111101110111CELL.QUAD_V3[1]
00111111110011111CELL.QUAD_V1[2]
00111111110101111CELL.QUAD_V2[2]
00111111110110111CELL.QUAD_V3[2]
00111111111111101CELL.OUT_CLB_Y_E
00111111111111110CELL.OUT_CLB_YQ_E
01101111111111111CELL.DOUBLE_V1[1]
01110111111111111CELL.SINGLE_V[1]
10011111111111111CELL.DOUBLE_V0[1]
10111011111111111CELL.SINGLE_V[5]
10111101111111111CELL.SINGLE_V[6]
11111111111111111CELL.SINGLE_V[4]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[8][7]MAIN[9][8]MAIN[7][7]MAIN[7][6]MAIN[8][9]MAIN[8][8]MAIN[7][9]MAIN[8][6]MAIN[26][11]MAIN[26][10]MAIN[27][10]MAIN[27][11]MAIN[28][11]MAIN[28][10]MAIN[15][10]MAIN[13][11]CELL.IMUX_CLB_C4
Source
0000111111111111CELL.SINGLE_H[1]
0001101111111111CELL.DOUBLE_H0[0]
0001110111111111CELL.SINGLE_H[6]
0011111111111111CELL.SINGLE_H[0]
0100011111111111CELL.LONG_H[4]
0100111011111111CELL.LONG_H_BUF[3]
0101001111111111CELL.SINGLE_H[2]
0101010111111111CELL.SINGLE_H[3]
0101101011111111CELL.DOUBLE_H1[0]
0101110011111111CELL_N.LONG_H[1]
0101111100001111CELL.QUAD_H0[2]
0101111100011111CELL.QUAD_H0[0]
0101111100101111CELL.QUAD_H0[1]
0101111100110111CELL.LONG_V[6]
0101111101001111CELL.QUAD_H2[2]
0101111101011111CELL.QUAD_H2[0]
0101111101101111CELL.QUAD_H2[1]
0101111101110111CELL.LONG_V[0]
0101111110001111CELL.QUAD_H3[2]
0101111110011111CELL.QUAD_H3[0]
0101111110101111CELL.QUAD_H3[1]
0101111110110111CELL.LONG_V[4]
0101111111001111CELL.QUAD_H1[2]
0101111111011111CELL.QUAD_H1[0]
0101111111101111CELL.QUAD_H1[1]
0101111111110111CELL.LONG_V[8]
0101111111111011CELL.GCLK[5]
0101111111111101CELL.OUT_CLB_X_S
0101111111111110CELL.OUT_CLB_XQ_S
0111011111111111CELL.DOUBLE_H1[1]
0111111011111111CELL.DOUBLE_H0[1]
1100111111111111CELL.SINGLE_H[4]
1101101111111111CELL.SINGLE_H[7]
1101110111111111CELL_N.LONG_H[2]
1111111111111111CELL.SINGLE_H[5]
xc4000xla CLB_NE switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[15][4]MAIN[21][4]MAIN[20][5]MAIN[18][5]MAIN[21][5]MAIN[20][4]MAIN[19][5]MAIN[19][4]MAIN[20][11]MAIN[18][11]MAIN[19][11]CELL.IMUX_CLB_K
Source
00111111111CELL.SINGLE_V[0]
01011111111CELL.SINGLE_V[3]
01101111111CELL.SINGLE_V[6]
01110111111CELL.GCLK[0]
01111011111CELL.GCLK[1]
01111101111CELL.GCLK[2]
01111110111CELL.GCLK[3]
01111111011CELL.GCLK[4]
01111111100CELL.GCLK[7]
01111111101CELL.GCLK[5]
01111111110CELL.GCLK[6]
11111111111CELL.SINGLE_V[5]
xc4000xla CLB_NE switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[21][6]MAIN[17][6]MAIN[20][6]MAIN[18][6]MAIN[19][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_NE switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[21][7]MAIN[17][7]MAIN[20][7]MAIN[18][7]MAIN[19][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X_H
00110CELL.OUT_CLB_XQ_H
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ_V
10101CELL.OUT_CLB_Y_V
11111CELL.TIE_0
xc4000xla CLB_NE switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][8]MAIN[19][8]MAIN[20][8]MAIN[18][8]MAIN[21][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000xla CLB_NE switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]MAIN[21][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000xla CLB_NE bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000xla CLB_NE bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[20][0]
F bit 1!MAIN[16][0]
F bit 2!MAIN[21][0]
F bit 3!MAIN[17][0]
F bit 4!MAIN[21][2]
F bit 5!MAIN[17][2]
F bit 6!MAIN[20][2]
F bit 7!MAIN[16][2]
F bit 8!MAIN[18][0]
F bit 9!MAIN[14][0]
F bit 10!MAIN[19][0]
F bit 11!MAIN[15][0]
F bit 12!MAIN[19][2]
F bit 13!MAIN[15][2]
F bit 14!MAIN[18][2]
F bit 15!MAIN[14][2]
G bit 0!MAIN[2][2]
G bit 1!MAIN[1][0]
G bit 2!MAIN[4][2]
G bit 3!MAIN[3][0]
G bit 4!MAIN[6][2]
G bit 5!MAIN[5][0]
G bit 6!MAIN[8][2]
G bit 7!MAIN[7][0]
G bit 8!MAIN[2][1]
G bit 9!MAIN[2][0]
G bit 10!MAIN[3][2]
G bit 11!MAIN[4][0]
G bit 12!MAIN[5][2]
G bit 13!MAIN[6][0]
G bit 14!MAIN[7][2]
G bit 15!MAIN[8][0]
H bit 0!MAIN[7][3]
H bit 1!MAIN[8][3]
H bit 2!MAIN[6][3]
H bit 3!MAIN[5][3]
H bit 4!MAIN[10][3]
H bit 5!MAIN[9][3]
H bit 6!MAIN[11][3]
H bit 7!MAIN[14][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[12][4]
FFY_SRVAL bit 0!MAIN[10][5]
FFX_EC_ENABLE!MAIN[14][5]
FFY_EC_ENABLE!MAIN[8][5]
FFX_SR_ENABLE!MAIN[12][5]
FFY_SR_ENABLE!MAIN[9][5]
FFX_CLK_INV!MAIN[17][5]
FFY_CLK_INV!MAIN[16][5]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[12][3]
READBACK_X bit 0!MAIN[0][3]
READBACK_Y bit 0!MAIN[0][5]
READBACK_XQ bit 0!MAIN[0][7]
READBACK_YQ bit 0!MAIN[0][4]
F_RAM_ENABLE!MAIN[13][2]
G_RAM_ENABLE!MAIN[9][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[3][1]
RAM_SYNC_ENABLE!MAIN[7][1]
RAM_CLK_INV!MAIN[6][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
FFX_MODE[enum: CLB_FF_MODE]
FFY_MODE[enum: CLB_FF_MODE]
xc4000xla CLB_NE enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[14][4]MAIN[17][3]MAIN[16][3]MAIN[16][4]
C11111
C20011
C30101
C40110
xc4000xla CLB_NE enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[18][3]MAIN[20][3]MAIN[19][3]MAIN[18][4]
C10011
C21111
C30101
C40110
xc4000xla CLB_NE enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[3][3]MAIN[4][4]MAIN[4][3]MAIN[5][4]
C10011
C20101
C31111
C40110
xc4000xla CLB_NE enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[1][4]MAIN[2][4]MAIN[3][4]MAIN[2][3]
C10011
C20101
C30110
C41111
xc4000xla CLB_NE enum CLB_MUX_X
CLB.MUX_XMAIN[15][3]
F0
H1
xc4000xla CLB_NE enum CLB_MUX_Y
CLB.MUX_YMAIN[6][4]
G0
H1
xc4000xla CLB_NE enum CLB_MUX_XQ
CLB.MUX_XQMAIN[21][3]
DIN0
FFX1
xc4000xla CLB_NE enum CLB_MUX_YQ
CLB.MUX_YQMAIN[1][3]
EC0
FFY1
xc4000xla CLB_NE enum CLB_MUX_D
CLB.MUX_DXMAIN[10][4]MAIN[15][6]MAIN[11][4]MAIN[13][4]
CLB.MUX_DYMAIN[5][5]MAIN[6][5]MAIN[8][4]MAIN[7][4]
F1111
G0011
H0101
DIN0110
xc4000xla CLB_NE enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[12][2]MAIN[13][0]
ADD01
SUB11
ADDSUB10
xc4000xla CLB_NE enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[13][3]MAIN[10][2]
CONST_011
CONST_110
XOR01
xc4000xla CLB_NE enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[11][0]MAIN[12][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000xla CLB_NE enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[9][0]MAIN[10][0]
CONST_010
CONST_111
XOR01
xc4000xla CLB_NE enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[11][2]
_32X11
_16X20
xc4000xla CLB_NE enum CLB_MUX_H0
CLB.MUX_H0MAIN[4][1]
G1
SR0
xc4000xla CLB_NE enum CLB_MUX_H2
CLB.MUX_H2MAIN[8][1]
F1
DIN0
xc4000xla CLB_NE enum CLB_FF_MODE
CLB.FFX_MODEMAIN[9][1]
CLB.FFY_MODEMAIN[5][1]
FF1
LATCH0

Bels TBUF

xc4000xla CLB_NE bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000xla CLB_NE bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[23][4]!MAIN[23][6]
DRIVE1_DUP!MAIN_S[21][11]!MAIN[20][10]

Bel wires

xc4000xla CLB_NE bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000xla CLB_NE rect MAIN
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 INT: !pass CELL.QUAD_V0[2] ← CELL.QBUF[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_H4[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V0[2] INT: !bipass CELL.QUAD_H4[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_V0[2] = CELL.QUAD_V4[2] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_H4[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V0[0] INT: !bipass CELL.QUAD_H4[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_H0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.QUAD_V0[0] = CELL.QUAD_V4[0] INT: !bipass CELL.SINGLE_V_S[3] = CELL.QUAD_H1[1] INT: !bipass CELL.SINGLE_V_S[7] = CELL.QUAD_H1[2] INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: !bipass CELL.SINGLE_V_S[2] = CELL.QUAD_H2[1] INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G4 bit 5 - INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: !pass CELL.QUAD_H3[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 6 -
B10 INT: !pass CELL.QUAD_H0[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_H4[2] ← CELL.QBUF[2] INT: !pass CELL.QUAD_V4[2] ← CELL.QBUF[2] INT: mux CELL.QBUF[2] bit 0 INT: mux CELL.QBUF[2] bit 1 INT: !pass CELL.QUAD_V0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H0[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_H4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V4[0] ← CELL.QBUF[0] INT: !pass CELL.QUAD_V0[1] ← CELL.QBUF[1] INT: mux CELL.QBUF[0] bit 0 INT: mux CELL.QBUF[0] bit 1 INT: !bipass CELL.SINGLE_V_S[6] = CELL.QUAD_H2[2] INT: !bipass CELL.SINGLE_V_S[4] = CELL.QUAD_H0[1] INT: !bipass CELL.SINGLE_V_S[5] = CELL.QUAD_H3[2] INT: !bipass CELL.DOUBLE_V1[1] = CELL.QUAD_H0[2] INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: !bipass CELL.SINGLE_V_S[1] = CELL.QUAD_H0[0] INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: !bipass CELL.SINGLE_V_S[0] = CELL.QUAD_H2[0] INT: !bipass CELL.DOUBLE_V2[0] = CELL.QUAD_H3[0] TBUF[1]: ! DRIVE1_DUP INT: !pass CELL.QUAD_H0[0] ← CELL.OUT_CLB_YQ_V INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_YQ_V INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_CLB_X_S INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 3 INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_CLB_Y_V INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7 -
B9 INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H4[1] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_V0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V4[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_V0[1] INT: mux CELL.QBUF[1] bit 0 INT: mux CELL.QBUF[1] bit 1 INT: !pass CELL.QUAD_H4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_V4[1] ← CELL.QBUF[1] INT: !pass CELL.QUAD_H0[1] ← CELL.QBUF[1] INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 10 INT: mux CELL.IMUX_CLB_F2 bit 14 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 9 INT: mux CELL.IMUX_CLB_C4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 14 INT: mux CELL.IMUX_CLB_G4 bit 13 - INT: mux CELL.IMUX_CLB_G2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 12 INT: mux CELL.IMUX_CLB_C2 bit 10 -
B8 - INT: !bipass CELL.SINGLE_H_E[3] = CELL.QUAD_V0[1] INT: !bipass CELL.QUAD_H0[1] = CELL.QUAD_H4[1] INT: !bipass CELL.SINGLE_H_E[6] = CELL.QUAD_V3[2] INT: !bipass CELL.SINGLE_H_E[5] = CELL.QUAD_V1[1] - INT: !bipass CELL.DOUBLE_H1[1] = CELL.QUAD_V3[1] INT: !bipass CELL.DOUBLE_H2[0] = CELL.QUAD_V0[0] INT: !bipass CELL.SINGLE_H_E[7] = CELL.QUAD_V2[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.QUAD_V2[0] - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 9 INT: mux CELL.IMUX_CLB_F2 bit 11 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 12 INT: mux CELL.IMUX_CLB_C4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 10 INT: mux CELL.IMUX_CLB_G4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 10 INT: mux CELL.IMUX_CLB_C2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 11 -
B7 - INT: !buffer CELL.LONG_V[9] ← CELL.SINGLE_H_E[7] INT: !buffer CELL.LONG_V[8] ← CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H_E[0] = CELL.QUAD_V1[0] INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[6] INT: !bipass CELL.SINGLE_H_E[1] = CELL.QUAD_V3[0] INT: !bipass CELL.SINGLE_H_E[4] = CELL.QUAD_V0[2] INT: !buffer CELL.LONG_V[6] ← CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[7] ← CELL.SINGLE_H_E[3] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[7] INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 8 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 15 INT: mux CELL.IMUX_CLB_F4 bit 11 INT: mux CELL.IMUX_CLB_C4 bit 15 INT: mux CELL.IMUX_CLB_C4 bit 13 INT: mux CELL.IMUX_CLB_G4 bit 9 INT: mux CELL.IMUX_CLB_G4 bit 10 INT: mux CELL.IMUX_CLB_G2 bit 12 INT: mux CELL.IMUX_CLB_G2 bit 14 INT: mux CELL.IMUX_CLB_C2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 15 CLB: ! READBACK_XQ bit 0
B6 - INT: mux CELL.IMUX_CLB_C1 bit 3 INT: !pass CELL.SINGLE_H_E[7] ← CELL.LONG_V[9] INT: !pass CELL.SINGLE_H_E[4] ← CELL.LONG_V[8] INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F2 bit 12 INT: mux CELL.IMUX_CLB_F4 bit 10 INT: mux CELL.IMUX_CLB_F4 bit 13 INT: mux CELL.IMUX_CLB_F4 bit 14 INT: mux CELL.IMUX_CLB_C4 bit 8 INT: mux CELL.IMUX_CLB_C4 bit 12 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 11 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_G2 bit 13 INT: mux CELL.IMUX_CLB_C2 bit 9 INT: mux CELL.IMUX_CLB_C2 bit 14 -
B5 - INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 8 INT: mux CELL.IMUX_CLB_K bit 4 INT: mux CELL.IMUX_CLB_K bit 7 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE - CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y_V CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ_V CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y_V INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ_V CLB: ! READBACK_Y bit 0
B4 - INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V0[0] ← CELL.OUT_CLB_X_H INT: !pass CELL.QUAD_V3[1] ← CELL.OUT_CLB_Y_E INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_Y_E INT: mux CELL.IMUX_CLB_G1 bit 8 INT: mux CELL.IMUX_CLB_G1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_H INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ_H TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 9 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 3 CLB: MUX_DIN bit 0 - CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 10 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 - CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3 CLB: ! READBACK_YQ bit 0
B3 INT: mux CELL.IMUX_CLB_C1 bit 7 - INT: mux CELL.IMUX_CLB_C1 bit 9 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 10 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 10 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 13 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 16 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 16 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0 CLB: ! READBACK_X bit 0
B2 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 11 INT: mux CELL.IMUX_CLB_F3 bit 15 INT: mux CELL.IMUX_CLB_F3 bit 17 INT: mux CELL.IMUX_CLB_C3 bit 11 INT: mux CELL.IMUX_CLB_C3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 11 INT: mux CELL.IMUX_CLB_G3 bit 14 INT: mux CELL.IMUX_CLB_G3 bit 17 INT: mux CELL.IMUX_CLB_F1 bit 10 INT: mux CELL.IMUX_CLB_F1 bit 17 INT: mux CELL.IMUX_CLB_C1 bit 11 INT: mux CELL.IMUX_CLB_C1 bit 10 INT: mux CELL.IMUX_CLB_C1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 10 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 - -
B1 INT: mux CELL.IMUX_CLB_G3 bit 3 - INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 9 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 14 INT: mux CELL.IMUX_CLB_F3 bit 12 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 14 INT: mux CELL.IMUX_CLB_C3 bit 15 INT: mux CELL.IMUX_CLB_G3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 12 INT: mux CELL.IMUX_CLB_G3 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 15 INT: mux CELL.IMUX_CLB_F1 bit 12 INT: mux CELL.IMUX_CLB_C1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 12 INT: mux CELL.IMUX_CLB_G1 bit 14 INT: mux CELL.IMUX_CLB_G1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 12 - - - - - - - - - - - - CLB: FFX_MODE bit 0 CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV CLB: FFY_MODE bit 0 CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE CLB: ! G bit 8 - -
B0 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 8 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_CLB_XQ_H INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_CLB_XQ_H INT: mux CELL.IMUX_CLB_F3 bit 16 INT: mux CELL.IMUX_CLB_F3 bit 10 INT: mux CELL.IMUX_CLB_F3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 13 INT: mux CELL.IMUX_CLB_C3 bit 16 INT: mux CELL.IMUX_CLB_G3 bit 13 INT: mux CELL.IMUX_CLB_G3 bit 18 INT: mux CELL.IMUX_CLB_F1 bit 16 INT: mux CELL.IMUX_CLB_F1 bit 11 INT: mux CELL.IMUX_CLB_F1 bit 14 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 13 INT: mux CELL.IMUX_CLB_G1 bit 15 INT: mux CELL.IMUX_CLB_G1 bit 11 INT: mux CELL.IMUX_CLB_G1 bit 17 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: CARRY_GPROP bit 0 CLB: CARRY_GPROP bit 1 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1 -
xc4000xla CLB_NE rect MAIN_S
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - TBUF[0]: ! DRIVE1_DUP - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_NE rect MAIN_W
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_C1 bit 8 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G1 bit 9 -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_NE rect MAIN_N
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000xla CLB_NE rect MAIN_E
BitFrame
F51 F50 F49 F48 F47 F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -