Xilinx XC9500, XC9500XL, XC9500XV CPLDs
Contents:
- Introduction
- Device structure
- Overview
- UIM and FB inputs — XC9500
- UIM and FB inputs — XC9500XL/XV
- FB global fuses
- Product terms
- Sum term, XOR gate
- Flip-flop
- Macrocell output — XC9500
- Macrocell output — XC9500XL/XV
- Input/output buffer
- Configuration pull-ups
- XC9500XL/XV bus keeper
- Global networks — XC9500
- Global networks — XC9500XL/XV
- Misc configuration
- Bitstream structure — XC9500
- Bitstream structure — XC9500XL/XV
- Database schema
- Database — devices
- JTAG interface