Xilinx XC9500, XC9500XL, XC9500XV CPLDs
XC9500 is a family of flash-based CPLDs manufactured by Xilinx. It is a derivative of the earlier XC7200 and XC7300 EPLD families. It comes in three variants:
- XC9500: 5V core logic, 3.3V or 5V I/O, original version.
- XC9500XL: 3.3V core logic, 2.5V or 3.3V I/O (5V tolerant), with some functional changes from XC9500:
- UIM no longer has wired-AND functionality
- FFs have clock enable function
- 54 (instead of 36) UIM inputs per function block
- FF has configurable clock polarity
- output enable has configurable polarity
- FOE/FCLK multiplexers and inversion have been removed
- optional weak bus keeper can be configured for all pins
- XC9500XV: 2.5V core logic, 1.8V, 2.5V, or 3.3V I/O, with minor functional changes from XC9500XL:
- larger devices have two or four I/O banks with separate VCCIO
- the bitstream now contains a
DONE
bit tied toISC_DONE
, preventing problems with partially configured devices
Devices
The following devices exist:
Device | Variant | IDCODE | Function blocks | GOE pins / FOE networks | I/O banks | Notes |
---|---|---|---|---|---|---|
xc9536 | xc9500 | 0x09502093 | 2 | 2 | 1 | Does not have FB input feedback |
xc9572 | xc9500 | 0x09504093 | 4 | 2 | 1 | GOE mapping to pads varies with package |
xc95108 | xc9500 | 0x09506093 | 6 | 2 | 1 | |
xc95144 | xc9500 | 0x09508093 | 8 | 4 | 1 | |
xc95216 | xc9500 | 0x09512093 | 12 | 4 | 1 | |
xc95288 | xc9500 | 0x09516093 | 16 | 4 | 1 | Has special input buffer enable fuses |
xc9536xl | xc9500xl | 0x09602093 | 2 | 2 | 1 | |
xc9572xl | xc9500xl | 0x09604093 | 4 | 2 | 1 | GOE mapping to pads varies with package |
xc95144xl | xc9500xl | 0x09608093 | 8 | 4 | 1 | |
xc95288xl | xc9500xl | 0x09616093 | 16 | 4 | 1 | |
xa9536xl | xc9500xl | 0x09602093 | 2 | 2 | 1 | |
xa9572xl | xc9500xl | 0x09604093 | 4 | 2 | 1 | GOE mapping to pads varies with package |
xa95144xl | xc9500xl | 0x09608093 | 8 | 4 | 1 | |
xc9536xv | xc9500xv | 0x09702093 | 2 | 2 | 1 | |
xc9572xv | xc9500xv | 0x09704093 | 4 | 2 | 1 | GOE mapping to pads varies with package |
xc95144xv | xc9500xv | 0x09708093 | 8 | 4 | 2 | |
xc95288xv | xc9500xv | 0x09716093 | 16 | 4 | 4 |
The parts starting with XA are automotive versions. They are functionally completely identical to corresponding XC versions.
Packages
The devices come in the following packages:
- PLCC:
- PC44 (JEDEC MO-047)
- PC84 (JEDEC MO-047)
- QFP:
- very thin QFP (1mm thickness):
- VQ44 (0.8mm pitch; JEDEC MS-026-ACB)
- VQ64 (0.5mm pitch; JEDEC MS-026-ACD)
- thin QFP (1.4mm thickness):
- TQ100 (0.5mm pitch; JEDEC MS-026-BED)
- TQ144 (0.5mm pitch; JEDEC MS-026-BFB)
- plastic QFP:
- PQ100 (2.7mm thickness, non-square, 30×20 pins, 0.65mm pitch; JEDEC MS-022-GC1)
- PQ160 (3.4mm thickness, 0.65mm pitch; JEDEC MS-022-DD1)
- PQ208 (3.4mm thickness, 0.5mm pitch; JEDEC MS-029-FA-1)
- platic QFP with heat sink:
- HQ208 (same footprint as PQ208)
- very thin QFP (1mm thickness):
- BGA:
- standard BGA (1.27mm pitch):
- BG256 (JEDEC MS-034-BAL-2)
- BG352
- fine-pitch BGA (1mm pitch):
- FG256
- chip-scale BGA (0.8mm pitch):
- CS48
- CS144 (JEDEC MO-216-BAG-2)
- CS280 (JEDEC MO-216-BAL-1)
- standard BGA (1.27mm pitch):
Device | cs48 | pc44 | vq44 | pc84 | pq100 | tq100 | pq160 | bg352 | hq208 | vq64 | cs144 | tq144 | bg256 | cs280 | fg256 | pq208 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
xc9536 | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc9572 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc95108 | ❌ | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc95144 | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc95216 | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc95288 | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc9536xl | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc9572xl | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc95144xl | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ |
xc95288xl | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ |
xa9536xl | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xa9572xl | ❌ | ❌ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xa95144xl | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc9536xv | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc9572xv | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
xc95144xv | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ |
xc95288xv | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ |
Pin compatibility is maintained across all 3 variants of the XC9500 family within a single package. Additionally, devices in PQ208 and HQ208 packages are pin compatible with each other.
Device pins
The XC9500 family devices have the following pads:
-
GND
: ground pins -
VCCINT
: core power, has to be:- 5V on XC9500
- 3.3V on XC9500XL
- 2.5V on XC9500XV
-
VCCIO
orVCCIO{bank}
: I/O power, has to be:- 3.3V or 5V on XC9500
- 2.5V or 3.3V on XC9500XL
- 1.8V, 2.5V, or 3.3V on XC9500XV
-
IOB_{i}_{j}
: general purpose I/O, associated with a macrocell (FBi
, MCj
); some of them also have an associated special function that can be used in addition to or instead of their plain I/O function:GCLK[0-2]
: capable of drivingFCLK*
fast clock networksGSR
: capable of drivingFSR
fast set/reset networkGOE[0-1]
(smaller devices) orGOE[0-3]
(larger devices): capable of drivingFOE*
fast output enable networks
Curiously, the
GOE
specials mapping to device pads varies with packaging on XC9572* devices. How exactly that works is unknown.The output drivers are powered by the
VCCIO
rails, and the output voltage is determined by that rail.For input, the following voltages are supported on all pins, regardless of VCCIO voltage:
- XC9500: 3.3V or 5V
- XC9500XL: 2.5V or 3.3V
- XC9500XV: 2.5V or 3.3V (notably, 1.8V is not supported)
-
TCK
,TMS
,TDI
,TDO
: dedicated JTAG pins; theTDO
pin output driver is powered by one of theVCCIO
rails