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Contents:
Xilinx XC9500, XC9500XL, XC9500XV CPLDs
Xilinx XPLA3 CPLDs
Introduction
Device structure
Bitstream structure
Database schema
Database — devices
JTAG interface
Xilinx Coolrunner II CPLDs
Xilinx FPGAs
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Xilinx XPLA3 CPLDs
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Xilinx XPLA3 CPLDs
Contents:
Introduction
Devices
Packages
Device pins
Device structure
Overview
FB columns and rows
ZIA and FB inputs
FCLK networks
Product terms
Sum term, LUT2
Register
Macrocell and IOB outputs
Input/output buffer
Misc configuration
Bitstream structure
JED structure
Fuses — IMUX bits
Fuses — product and sum terms
Fuses — macrocells
Fuses — FBs
Fuses — global bits
Database schema
Top level
Device
Bond
Speed
Part
Tile
JED bits
Database — devices
XCR3032XL
XCR3064XL
XCR3128XL
XCR3256XL
XCR3384XL
XCR3512XL
JTAG interface
IR
IDCODE
Boundary scan register
ISP instructions
Programming sequence