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Clock interconnect

Tile CLK_ROOT_2PLL

Cells: 22

Bel DCS0

ecp CLK_ROOT_2PLL bel DCS0
PinDirectionWires
OUTinputTCELL0:PCLK2
SELinputTCELL4:IMUX_C4

Bel DCS1

ecp CLK_ROOT_2PLL bel DCS1
PinDirectionWires
OUTinputTCELL0:PCLK3
SELinputTCELL4:IMUX_D4

Bel DCS2

ecp CLK_ROOT_2PLL bel DCS2
PinDirectionWires
OUTinputTCELL1:PCLK2
SELinputTCELL5:IMUX_B4

Bel DCS3

ecp CLK_ROOT_2PLL bel DCS3
PinDirectionWires
OUTinputTCELL1:PCLK3
SELinputTCELL5:IMUX_A4

Bel DCS4

ecp CLK_ROOT_2PLL bel DCS4
PinDirectionWires
OUTinputTCELL2:PCLK2
SELinputTCELL4:IMUX_A4

Bel DCS5

ecp CLK_ROOT_2PLL bel DCS5
PinDirectionWires
OUTinputTCELL2:PCLK3
SELinputTCELL4:IMUX_B4

Bel DCS6

ecp CLK_ROOT_2PLL bel DCS6
PinDirectionWires
OUTinputTCELL3:PCLK2
SELinputTCELL5:IMUX_D4

Bel DCS7

ecp CLK_ROOT_2PLL bel DCS7
PinDirectionWires
OUTinputTCELL3:PCLK3
SELinputTCELL5:IMUX_C4

Bel CLK_ROOT

ecp CLK_ROOT_2PLL bel CLK_ROOT
PinDirectionWires
PCLK0_NEinputTCELL3:PCLK0
PCLK0_NWinputTCELL2:PCLK0
PCLK0_SEinputTCELL1:PCLK0
PCLK0_SWinputTCELL0:PCLK0
PCLK1_NEinputTCELL3:PCLK1
PCLK1_NWinputTCELL2:PCLK1
PCLK1_SEinputTCELL1:PCLK1
PCLK1_SWinputTCELL0:PCLK1
PCLK_IN_EinputTCELL7:IMUX_B5
PCLK_IN_NinputTCELL9:IMUX_B5
PCLK_IN_SinputTCELL8:IMUX_B5
PCLK_IN_WinputTCELL6:IMUX_B5
SCLK0_NEinputTCELL3:SCLK0
SCLK0_NWinputTCELL2:SCLK0
SCLK0_SEinputTCELL1:SCLK0
SCLK0_SWinputTCELL0:SCLK0
SCLK1_NEinputTCELL3:SCLK1
SCLK1_NWinputTCELL2:SCLK1
SCLK1_SEinputTCELL1:SCLK1
SCLK1_SWinputTCELL0:SCLK1
SCLK2_NEinputTCELL3:SCLK2
SCLK2_NWinputTCELL2:SCLK2
SCLK2_SEinputTCELL1:SCLK2
SCLK2_SWinputTCELL0:SCLK2
SCLK3_NEinputTCELL3:SCLK3
SCLK3_NWinputTCELL2:SCLK3
SCLK3_SEinputTCELL1:SCLK3
SCLK3_SWinputTCELL0:SCLK3
SCLK_IN_E0inputTCELL13:IMUX_B5
SCLK_IN_E1inputTCELL14:IMUX_B5
SCLK_IN_E3inputTCELL15:IMUX_B0
SCLK_IN_N0inputTCELL20:IMUX_B5
SCLK_IN_N1inputTCELL21:IMUX_B5
SCLK_IN_S0inputTCELL16:IMUX_B5
SCLK_IN_S1inputTCELL17:IMUX_B5
SCLK_IN_S2inputTCELL18:IMUX_B0
SCLK_IN_S3inputTCELL19:IMUX_D5
SCLK_IN_W0inputTCELL10:IMUX_B5
SCLK_IN_W1inputTCELL11:IMUX_B5
SCLK_IN_W3inputTCELL12:IMUX_D5

Bel wires

ecp CLK_ROOT_2PLL bel wires
WirePins
TCELL0:PCLK0CLK_ROOT.PCLK0_SW
TCELL0:PCLK1CLK_ROOT.PCLK1_SW
TCELL0:PCLK2DCS0.OUT
TCELL0:PCLK3DCS1.OUT
TCELL0:SCLK0CLK_ROOT.SCLK0_SW
TCELL0:SCLK1CLK_ROOT.SCLK1_SW
TCELL0:SCLK2CLK_ROOT.SCLK2_SW
TCELL0:SCLK3CLK_ROOT.SCLK3_SW
TCELL1:PCLK0CLK_ROOT.PCLK0_SE
TCELL1:PCLK1CLK_ROOT.PCLK1_SE
TCELL1:PCLK2DCS2.OUT
TCELL1:PCLK3DCS3.OUT
TCELL1:SCLK0CLK_ROOT.SCLK0_SE
TCELL1:SCLK1CLK_ROOT.SCLK1_SE
TCELL1:SCLK2CLK_ROOT.SCLK2_SE
TCELL1:SCLK3CLK_ROOT.SCLK3_SE
TCELL2:PCLK0CLK_ROOT.PCLK0_NW
TCELL2:PCLK1CLK_ROOT.PCLK1_NW
TCELL2:PCLK2DCS4.OUT
TCELL2:PCLK3DCS5.OUT
TCELL2:SCLK0CLK_ROOT.SCLK0_NW
TCELL2:SCLK1CLK_ROOT.SCLK1_NW
TCELL2:SCLK2CLK_ROOT.SCLK2_NW
TCELL2:SCLK3CLK_ROOT.SCLK3_NW
TCELL3:PCLK0CLK_ROOT.PCLK0_NE
TCELL3:PCLK1CLK_ROOT.PCLK1_NE
TCELL3:PCLK2DCS6.OUT
TCELL3:PCLK3DCS7.OUT
TCELL3:SCLK0CLK_ROOT.SCLK0_NE
TCELL3:SCLK1CLK_ROOT.SCLK1_NE
TCELL3:SCLK2CLK_ROOT.SCLK2_NE
TCELL3:SCLK3CLK_ROOT.SCLK3_NE
TCELL4:IMUX_A4DCS4.SEL
TCELL4:IMUX_B4DCS5.SEL
TCELL4:IMUX_C4DCS0.SEL
TCELL4:IMUX_D4DCS1.SEL
TCELL5:IMUX_A4DCS3.SEL
TCELL5:IMUX_B4DCS2.SEL
TCELL5:IMUX_C4DCS7.SEL
TCELL5:IMUX_D4DCS6.SEL
TCELL6:IMUX_B5CLK_ROOT.PCLK_IN_W
TCELL7:IMUX_B5CLK_ROOT.PCLK_IN_E
TCELL8:IMUX_B5CLK_ROOT.PCLK_IN_S
TCELL9:IMUX_B5CLK_ROOT.PCLK_IN_N
TCELL10:IMUX_B5CLK_ROOT.SCLK_IN_W0
TCELL11:IMUX_B5CLK_ROOT.SCLK_IN_W1
TCELL12:IMUX_D5CLK_ROOT.SCLK_IN_W3
TCELL13:IMUX_B5CLK_ROOT.SCLK_IN_E0
TCELL14:IMUX_B5CLK_ROOT.SCLK_IN_E1
TCELL15:IMUX_B0CLK_ROOT.SCLK_IN_E3
TCELL16:IMUX_B5CLK_ROOT.SCLK_IN_S0
TCELL17:IMUX_B5CLK_ROOT.SCLK_IN_S1
TCELL18:IMUX_B0CLK_ROOT.SCLK_IN_S2
TCELL19:IMUX_D5CLK_ROOT.SCLK_IN_S3
TCELL20:IMUX_B5CLK_ROOT.SCLK_IN_N0
TCELL21:IMUX_B5CLK_ROOT.SCLK_IN_N1

Tile CLK_ROOT_4PLL

Cells: 32

Bel DCS0

ecp CLK_ROOT_4PLL bel DCS0
PinDirectionWires
OUTinputTCELL0:PCLK2
SELinputTCELL4:IMUX_D5

Bel DCS1

ecp CLK_ROOT_4PLL bel DCS1
PinDirectionWires
OUTinputTCELL0:PCLK3
SELinputTCELL5:IMUX_B0

Bel DCS2

ecp CLK_ROOT_4PLL bel DCS2
PinDirectionWires
OUTinputTCELL1:PCLK2
SELinputTCELL7:IMUX_B0

Bel DCS3

ecp CLK_ROOT_4PLL bel DCS3
PinDirectionWires
OUTinputTCELL1:PCLK3
SELinputTCELL6:IMUX_D5

Bel DCS4

ecp CLK_ROOT_4PLL bel DCS4
PinDirectionWires
OUTinputTCELL2:PCLK2
SELinputTCELL8:IMUX_D5

Bel DCS5

ecp CLK_ROOT_4PLL bel DCS5
PinDirectionWires
OUTinputTCELL2:PCLK3
SELinputTCELL9:IMUX_B0

Bel DCS6

ecp CLK_ROOT_4PLL bel DCS6
PinDirectionWires
OUTinputTCELL3:PCLK2
SELinputTCELL11:IMUX_B0

Bel DCS7

ecp CLK_ROOT_4PLL bel DCS7
PinDirectionWires
OUTinputTCELL3:PCLK3
SELinputTCELL10:IMUX_D5

Bel CLK_ROOT

ecp CLK_ROOT_4PLL bel CLK_ROOT
PinDirectionWires
PCLK0_NEinputTCELL3:PCLK0
PCLK0_NWinputTCELL2:PCLK0
PCLK0_SEinputTCELL1:PCLK0
PCLK0_SWinputTCELL0:PCLK0
PCLK1_NEinputTCELL3:PCLK1
PCLK1_NWinputTCELL2:PCLK1
PCLK1_SEinputTCELL1:PCLK1
PCLK1_SWinputTCELL0:PCLK1
PCLK_IN_EinputTCELL13:IMUX_B5
PCLK_IN_NinputTCELL15:IMUX_B5
PCLK_IN_SinputTCELL14:IMUX_B5
PCLK_IN_WinputTCELL12:IMUX_B5
SCLK0_NEinputTCELL3:SCLK0
SCLK0_NWinputTCELL2:SCLK0
SCLK0_SEinputTCELL1:SCLK0
SCLK0_SWinputTCELL0:SCLK0
SCLK1_NEinputTCELL3:SCLK1
SCLK1_NWinputTCELL2:SCLK1
SCLK1_SEinputTCELL1:SCLK1
SCLK1_SWinputTCELL0:SCLK1
SCLK2_NEinputTCELL3:SCLK2
SCLK2_NWinputTCELL2:SCLK2
SCLK2_SEinputTCELL1:SCLK2
SCLK2_SWinputTCELL0:SCLK2
SCLK3_NEinputTCELL3:SCLK3
SCLK3_NWinputTCELL2:SCLK3
SCLK3_SEinputTCELL1:SCLK3
SCLK3_SWinputTCELL0:SCLK3
SCLK_IN_E0inputTCELL20:IMUX_B5
SCLK_IN_E1inputTCELL21:IMUX_B5
SCLK_IN_E2inputTCELL22:IMUX_B0
SCLK_IN_E3inputTCELL23:IMUX_B0
SCLK_IN_N0inputTCELL28:IMUX_B5
SCLK_IN_N1inputTCELL29:IMUX_B5
SCLK_IN_N2inputTCELL30:IMUX_B0
SCLK_IN_N3inputTCELL31:IMUX_D5
SCLK_IN_S0inputTCELL24:IMUX_B5
SCLK_IN_S1inputTCELL25:IMUX_B5
SCLK_IN_S2inputTCELL26:IMUX_B0
SCLK_IN_S3inputTCELL27:IMUX_D5
SCLK_IN_W0inputTCELL16:IMUX_B5
SCLK_IN_W1inputTCELL17:IMUX_B5
SCLK_IN_W2inputTCELL18:IMUX_D5
SCLK_IN_W3inputTCELL19:IMUX_D5

Bel wires

ecp CLK_ROOT_4PLL bel wires
WirePins
TCELL0:PCLK0CLK_ROOT.PCLK0_SW
TCELL0:PCLK1CLK_ROOT.PCLK1_SW
TCELL0:PCLK2DCS0.OUT
TCELL0:PCLK3DCS1.OUT
TCELL0:SCLK0CLK_ROOT.SCLK0_SW
TCELL0:SCLK1CLK_ROOT.SCLK1_SW
TCELL0:SCLK2CLK_ROOT.SCLK2_SW
TCELL0:SCLK3CLK_ROOT.SCLK3_SW
TCELL1:PCLK0CLK_ROOT.PCLK0_SE
TCELL1:PCLK1CLK_ROOT.PCLK1_SE
TCELL1:PCLK2DCS2.OUT
TCELL1:PCLK3DCS3.OUT
TCELL1:SCLK0CLK_ROOT.SCLK0_SE
TCELL1:SCLK1CLK_ROOT.SCLK1_SE
TCELL1:SCLK2CLK_ROOT.SCLK2_SE
TCELL1:SCLK3CLK_ROOT.SCLK3_SE
TCELL2:PCLK0CLK_ROOT.PCLK0_NW
TCELL2:PCLK1CLK_ROOT.PCLK1_NW
TCELL2:PCLK2DCS4.OUT
TCELL2:PCLK3DCS5.OUT
TCELL2:SCLK0CLK_ROOT.SCLK0_NW
TCELL2:SCLK1CLK_ROOT.SCLK1_NW
TCELL2:SCLK2CLK_ROOT.SCLK2_NW
TCELL2:SCLK3CLK_ROOT.SCLK3_NW
TCELL3:PCLK0CLK_ROOT.PCLK0_NE
TCELL3:PCLK1CLK_ROOT.PCLK1_NE
TCELL3:PCLK2DCS6.OUT
TCELL3:PCLK3DCS7.OUT
TCELL3:SCLK0CLK_ROOT.SCLK0_NE
TCELL3:SCLK1CLK_ROOT.SCLK1_NE
TCELL3:SCLK2CLK_ROOT.SCLK2_NE
TCELL3:SCLK3CLK_ROOT.SCLK3_NE
TCELL4:IMUX_D5DCS0.SEL
TCELL5:IMUX_B0DCS1.SEL
TCELL6:IMUX_D5DCS3.SEL
TCELL7:IMUX_B0DCS2.SEL
TCELL8:IMUX_D5DCS4.SEL
TCELL9:IMUX_B0DCS5.SEL
TCELL10:IMUX_D5DCS7.SEL
TCELL11:IMUX_B0DCS6.SEL
TCELL12:IMUX_B5CLK_ROOT.PCLK_IN_W
TCELL13:IMUX_B5CLK_ROOT.PCLK_IN_E
TCELL14:IMUX_B5CLK_ROOT.PCLK_IN_S
TCELL15:IMUX_B5CLK_ROOT.PCLK_IN_N
TCELL16:IMUX_B5CLK_ROOT.SCLK_IN_W0
TCELL17:IMUX_B5CLK_ROOT.SCLK_IN_W1
TCELL18:IMUX_D5CLK_ROOT.SCLK_IN_W2
TCELL19:IMUX_D5CLK_ROOT.SCLK_IN_W3
TCELL20:IMUX_B5CLK_ROOT.SCLK_IN_E0
TCELL21:IMUX_B5CLK_ROOT.SCLK_IN_E1
TCELL22:IMUX_B0CLK_ROOT.SCLK_IN_E2
TCELL23:IMUX_B0CLK_ROOT.SCLK_IN_E3
TCELL24:IMUX_B5CLK_ROOT.SCLK_IN_S0
TCELL25:IMUX_B5CLK_ROOT.SCLK_IN_S1
TCELL26:IMUX_B0CLK_ROOT.SCLK_IN_S2
TCELL27:IMUX_D5CLK_ROOT.SCLK_IN_S3
TCELL28:IMUX_B5CLK_ROOT.SCLK_IN_N0
TCELL29:IMUX_B5CLK_ROOT.SCLK_IN_N1
TCELL30:IMUX_B0CLK_ROOT.SCLK_IN_N2
TCELL31:IMUX_D5CLK_ROOT.SCLK_IN_N3