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DSP

Tile DSP

Cells: 8

Bel DSP0

ecp DSP bel DSP0
PinDirectionWires
ACCUMSLOAD1inputTCELL3:IMUX_CE0
ACCUMSLOAD3inputTCELL5:IMUX_CE0
ADDNSUB1inputTCELL1:IMUX_CE0
ADDNSUB3inputTCELL7:IMUX_CE0
CE0inputTCELL0:IMUX_CE0
CE1inputTCELL2:IMUX_CE0
CE2inputTCELL4:IMUX_CE0
CE3inputTCELL6:IMUX_CE0
CLK0inputTCELL0:IMUX_CLK0
CLK1inputTCELL2:IMUX_CLK0
CLK2inputTCELL4:IMUX_CLK0
CLK3inputTCELL6:IMUX_CLK0
MUA00inputTCELL0:IMUX_A0
MUA01inputTCELL0:IMUX_B0
MUA010inputTCELL0:IMUX_C2
MUA011inputTCELL0:IMUX_D2
MUA012inputTCELL0:IMUX_A3
MUA013inputTCELL0:IMUX_B3
MUA014inputTCELL0:IMUX_C3
MUA015inputTCELL0:IMUX_D3
MUA016inputTCELL0:IMUX_A4
MUA017inputTCELL0:IMUX_B4
MUA02inputTCELL0:IMUX_C0
MUA03inputTCELL0:IMUX_D0
MUA04inputTCELL0:IMUX_A1
MUA05inputTCELL0:IMUX_B1
MUA06inputTCELL0:IMUX_C1
MUA07inputTCELL0:IMUX_D1
MUA08inputTCELL0:IMUX_A2
MUA09inputTCELL0:IMUX_B2
MUA10inputTCELL2:IMUX_A0
MUA11inputTCELL2:IMUX_B0
MUA110inputTCELL2:IMUX_C2
MUA111inputTCELL2:IMUX_D2
MUA112inputTCELL2:IMUX_A3
MUA113inputTCELL2:IMUX_B3
MUA114inputTCELL2:IMUX_C3
MUA115inputTCELL2:IMUX_D3
MUA116inputTCELL2:IMUX_A4
MUA117inputTCELL2:IMUX_B4
MUA12inputTCELL2:IMUX_C0
MUA13inputTCELL2:IMUX_D0
MUA14inputTCELL2:IMUX_A1
MUA15inputTCELL2:IMUX_B1
MUA16inputTCELL2:IMUX_C1
MUA17inputTCELL2:IMUX_D1
MUA18inputTCELL2:IMUX_A2
MUA19inputTCELL2:IMUX_B2
MUA20inputTCELL4:IMUX_A0
MUA21inputTCELL4:IMUX_B0
MUA210inputTCELL4:IMUX_C2
MUA211inputTCELL4:IMUX_D2
MUA212inputTCELL4:IMUX_A3
MUA213inputTCELL4:IMUX_B3
MUA214inputTCELL4:IMUX_C3
MUA215inputTCELL4:IMUX_D3
MUA216inputTCELL4:IMUX_A4
MUA217inputTCELL4:IMUX_B4
MUA22inputTCELL4:IMUX_C0
MUA23inputTCELL4:IMUX_D0
MUA24inputTCELL4:IMUX_A1
MUA25inputTCELL4:IMUX_B1
MUA26inputTCELL4:IMUX_C1
MUA27inputTCELL4:IMUX_D1
MUA28inputTCELL4:IMUX_A2
MUA29inputTCELL4:IMUX_B2
MUA30inputTCELL6:IMUX_A0
MUA31inputTCELL6:IMUX_B0
MUA310inputTCELL6:IMUX_C2
MUA311inputTCELL6:IMUX_D2
MUA312inputTCELL6:IMUX_A3
MUA313inputTCELL6:IMUX_B3
MUA314inputTCELL6:IMUX_C3
MUA315inputTCELL6:IMUX_D3
MUA316inputTCELL6:IMUX_A4
MUA317inputTCELL6:IMUX_B4
MUA32inputTCELL6:IMUX_C0
MUA33inputTCELL6:IMUX_D0
MUA34inputTCELL6:IMUX_A1
MUA35inputTCELL6:IMUX_B1
MUA36inputTCELL6:IMUX_C1
MUA37inputTCELL6:IMUX_D1
MUA38inputTCELL6:IMUX_A2
MUA39inputTCELL6:IMUX_B2
MUB00inputTCELL1:IMUX_A0
MUB01inputTCELL1:IMUX_B0
MUB010inputTCELL1:IMUX_C2
MUB011inputTCELL1:IMUX_D2
MUB012inputTCELL1:IMUX_A3
MUB013inputTCELL1:IMUX_B3
MUB014inputTCELL1:IMUX_C3
MUB015inputTCELL1:IMUX_D3
MUB016inputTCELL1:IMUX_A4
MUB017inputTCELL1:IMUX_B4
MUB02inputTCELL1:IMUX_C0
MUB03inputTCELL1:IMUX_D0
MUB04inputTCELL1:IMUX_A1
MUB05inputTCELL1:IMUX_B1
MUB06inputTCELL1:IMUX_C1
MUB07inputTCELL1:IMUX_D1
MUB08inputTCELL1:IMUX_A2
MUB09inputTCELL1:IMUX_B2
MUB10inputTCELL3:IMUX_A0
MUB11inputTCELL3:IMUX_B0
MUB110inputTCELL3:IMUX_C2
MUB111inputTCELL3:IMUX_D2
MUB112inputTCELL3:IMUX_A3
MUB113inputTCELL3:IMUX_B3
MUB114inputTCELL3:IMUX_C3
MUB115inputTCELL3:IMUX_D3
MUB116inputTCELL3:IMUX_A4
MUB117inputTCELL3:IMUX_B4
MUB12inputTCELL3:IMUX_C0
MUB13inputTCELL3:IMUX_D0
MUB14inputTCELL3:IMUX_A1
MUB15inputTCELL3:IMUX_B1
MUB16inputTCELL3:IMUX_C1
MUB17inputTCELL3:IMUX_D1
MUB18inputTCELL3:IMUX_A2
MUB19inputTCELL3:IMUX_B2
MUB20inputTCELL5:IMUX_A0
MUB21inputTCELL5:IMUX_B0
MUB210inputTCELL5:IMUX_C2
MUB211inputTCELL5:IMUX_D2
MUB212inputTCELL5:IMUX_A3
MUB213inputTCELL5:IMUX_B3
MUB214inputTCELL5:IMUX_C3
MUB215inputTCELL5:IMUX_D3
MUB216inputTCELL5:IMUX_A4
MUB217inputTCELL5:IMUX_B4
MUB22inputTCELL5:IMUX_C0
MUB23inputTCELL5:IMUX_D0
MUB24inputTCELL5:IMUX_A1
MUB25inputTCELL5:IMUX_B1
MUB26inputTCELL5:IMUX_C1
MUB27inputTCELL5:IMUX_D1
MUB28inputTCELL5:IMUX_A2
MUB29inputTCELL5:IMUX_B2
MUB30inputTCELL7:IMUX_A0
MUB31inputTCELL7:IMUX_B0
MUB310inputTCELL7:IMUX_C2
MUB311inputTCELL7:IMUX_D2
MUB312inputTCELL7:IMUX_A3
MUB313inputTCELL7:IMUX_B3
MUB314inputTCELL7:IMUX_C3
MUB315inputTCELL7:IMUX_D3
MUB316inputTCELL7:IMUX_A4
MUB317inputTCELL7:IMUX_B4
MUB32inputTCELL7:IMUX_C0
MUB33inputTCELL7:IMUX_D0
MUB34inputTCELL7:IMUX_A1
MUB35inputTCELL7:IMUX_B1
MUB36inputTCELL7:IMUX_C1
MUB37inputTCELL7:IMUX_D1
MUB38inputTCELL7:IMUX_A2
MUB39inputTCELL7:IMUX_B2
MUP00outputTCELL0:OUT_F0
MUP01outputTCELL0:OUT_F1
MUP010outputTCELL0:OUT_Q2
MUP011outputTCELL0:OUT_Q3
MUP012outputTCELL0:OUT_Q4
MUP013outputTCELL0:OUT_Q5
MUP014outputTCELL0:OUT_Q6
MUP015outputTCELL0:OUT_Q7
MUP016outputTCELL0:OUT_OFX0
MUP017outputTCELL0:OUT_OFX7
MUP018outputTCELL1:OUT_F0
MUP019outputTCELL1:OUT_F1
MUP02outputTCELL0:OUT_F2
MUP020outputTCELL1:OUT_F2
MUP021outputTCELL1:OUT_F3
MUP022outputTCELL1:OUT_F4
MUP023outputTCELL1:OUT_F5
MUP024outputTCELL1:OUT_F6
MUP025outputTCELL1:OUT_F7
MUP026outputTCELL1:OUT_Q0
MUP027outputTCELL1:OUT_Q1
MUP028outputTCELL1:OUT_Q2
MUP029outputTCELL1:OUT_Q3
MUP03outputTCELL0:OUT_F3
MUP030outputTCELL1:OUT_Q4
MUP031outputTCELL1:OUT_Q5
MUP032outputTCELL1:OUT_Q6
MUP033outputTCELL1:OUT_Q7
MUP034outputTCELL1:OUT_OFX0
MUP035outputTCELL1:OUT_OFX7
MUP04outputTCELL0:OUT_F4
MUP05outputTCELL0:OUT_F5
MUP06outputTCELL0:OUT_F6
MUP07outputTCELL0:OUT_F7
MUP08outputTCELL0:OUT_Q0
MUP09outputTCELL0:OUT_Q1
MUP10outputTCELL2:OUT_F0
MUP11outputTCELL2:OUT_F1
MUP110outputTCELL2:OUT_Q2
MUP111outputTCELL2:OUT_Q3
MUP112outputTCELL2:OUT_Q4
MUP113outputTCELL2:OUT_Q5
MUP114outputTCELL2:OUT_Q6
MUP115outputTCELL2:OUT_Q7
MUP116outputTCELL2:OUT_OFX0
MUP117outputTCELL2:OUT_OFX7
MUP118outputTCELL3:OUT_F0
MUP119outputTCELL3:OUT_F1
MUP12outputTCELL2:OUT_F2
MUP120outputTCELL3:OUT_F2
MUP121outputTCELL3:OUT_F3
MUP122outputTCELL3:OUT_F4
MUP123outputTCELL3:OUT_F5
MUP124outputTCELL3:OUT_F6
MUP125outputTCELL3:OUT_F7
MUP126outputTCELL3:OUT_Q0
MUP127outputTCELL3:OUT_Q1
MUP128outputTCELL3:OUT_Q2
MUP129outputTCELL3:OUT_Q3
MUP13outputTCELL2:OUT_F3
MUP130outputTCELL3:OUT_Q4
MUP131outputTCELL3:OUT_Q5
MUP132outputTCELL3:OUT_Q6
MUP133outputTCELL3:OUT_Q7
MUP134outputTCELL3:OUT_OFX0
MUP135outputTCELL3:OUT_OFX7
MUP14outputTCELL2:OUT_F4
MUP15outputTCELL2:OUT_F5
MUP16outputTCELL2:OUT_F6
MUP17outputTCELL2:OUT_F7
MUP18outputTCELL2:OUT_Q0
MUP19outputTCELL2:OUT_Q1
MUP20outputTCELL4:OUT_F0
MUP21outputTCELL4:OUT_F1
MUP210outputTCELL4:OUT_Q2
MUP211outputTCELL4:OUT_Q3
MUP212outputTCELL4:OUT_Q4
MUP213outputTCELL4:OUT_Q5
MUP214outputTCELL4:OUT_Q6
MUP215outputTCELL4:OUT_Q7
MUP216outputTCELL4:OUT_OFX0
MUP217outputTCELL4:OUT_OFX7
MUP218outputTCELL5:OUT_F0
MUP219outputTCELL5:OUT_F1
MUP22outputTCELL4:OUT_F2
MUP220outputTCELL5:OUT_F2
MUP221outputTCELL5:OUT_F3
MUP222outputTCELL5:OUT_F4
MUP223outputTCELL5:OUT_F5
MUP224outputTCELL5:OUT_F6
MUP225outputTCELL5:OUT_F7
MUP226outputTCELL5:OUT_Q0
MUP227outputTCELL5:OUT_Q1
MUP228outputTCELL5:OUT_Q2
MUP229outputTCELL5:OUT_Q3
MUP23outputTCELL4:OUT_F3
MUP230outputTCELL5:OUT_Q4
MUP231outputTCELL5:OUT_Q5
MUP232outputTCELL5:OUT_Q6
MUP233outputTCELL5:OUT_Q7
MUP234outputTCELL5:OUT_OFX0
MUP235outputTCELL5:OUT_OFX7
MUP24outputTCELL4:OUT_F4
MUP25outputTCELL4:OUT_F5
MUP26outputTCELL4:OUT_F6
MUP27outputTCELL4:OUT_F7
MUP28outputTCELL4:OUT_Q0
MUP29outputTCELL4:OUT_Q1
MUP30outputTCELL6:OUT_F0
MUP31outputTCELL6:OUT_F1
MUP310outputTCELL6:OUT_Q2
MUP311outputTCELL6:OUT_Q3
MUP312outputTCELL6:OUT_Q4
MUP313outputTCELL6:OUT_Q5
MUP314outputTCELL6:OUT_Q6
MUP315outputTCELL6:OUT_Q7
MUP316outputTCELL6:OUT_OFX0
MUP317outputTCELL6:OUT_OFX7
MUP318outputTCELL7:OUT_F0
MUP319outputTCELL7:OUT_F1
MUP32outputTCELL6:OUT_F2
MUP320outputTCELL7:OUT_F2
MUP321outputTCELL7:OUT_F3
MUP322outputTCELL7:OUT_F4
MUP323outputTCELL7:OUT_F5
MUP324outputTCELL7:OUT_F6
MUP325outputTCELL7:OUT_F7
MUP326outputTCELL7:OUT_Q0
MUP327outputTCELL7:OUT_Q1
MUP328outputTCELL7:OUT_Q2
MUP329outputTCELL7:OUT_Q3
MUP33outputTCELL6:OUT_F3
MUP330outputTCELL7:OUT_Q4
MUP331outputTCELL7:OUT_Q5
MUP332outputTCELL7:OUT_Q6
MUP333outputTCELL7:OUT_Q7
MUP334outputTCELL7:OUT_OFX0
MUP335outputTCELL7:OUT_OFX7
MUP34outputTCELL6:OUT_F4
MUP35outputTCELL6:OUT_F5
MUP36outputTCELL6:OUT_F6
MUP37outputTCELL6:OUT_F7
MUP38outputTCELL6:OUT_Q0
MUP39outputTCELL6:OUT_Q1
RST0inputTCELL1:IMUX_LSR1
RST1inputTCELL3:IMUX_LSR1
RST2inputTCELL5:IMUX_LSR1
RST3inputTCELL7:IMUX_LSR1
SIGNEDAB0inputTCELL0:IMUX_LSR1
SIGNEDAB1inputTCELL2:IMUX_LSR1
SIGNEDAB2inputTCELL4:IMUX_LSR1
SIGNEDAB3inputTCELL6:IMUX_LSR1
SROA0outputTCELL0:OUT_OFX2
SROA1outputTCELL0:OUT_OFX3
SROA10outputTCELL2:OUT_OFX3
SROA11outputTCELL2:OUT_OFX4
SROA12outputTCELL2:OUT_OFX5
SROA13outputTCELL2:OUT_OFX6
SROA14outputTCELL3:OUT_OFX2
SROA15outputTCELL3:OUT_OFX3
SROA16outputTCELL3:OUT_OFX4
SROA17outputTCELL3:OUT_OFX5
SROA2outputTCELL0:OUT_OFX4
SROA3outputTCELL0:OUT_OFX5
SROA4outputTCELL0:OUT_OFX6
SROA5outputTCELL1:OUT_OFX2
SROA6outputTCELL1:OUT_OFX3
SROA7outputTCELL1:OUT_OFX4
SROA8outputTCELL1:OUT_OFX5
SROA9outputTCELL2:OUT_OFX2
SROB0outputTCELL4:OUT_OFX2
SROB1outputTCELL4:OUT_OFX3
SROB10outputTCELL6:OUT_OFX3
SROB11outputTCELL6:OUT_OFX4
SROB12outputTCELL6:OUT_OFX5
SROB13outputTCELL6:OUT_OFX6
SROB14outputTCELL7:OUT_OFX2
SROB15outputTCELL7:OUT_OFX3
SROB16outputTCELL7:OUT_OFX4
SROB17outputTCELL7:OUT_OFX5
SROB2outputTCELL4:OUT_OFX4
SROB3outputTCELL4:OUT_OFX5
SROB4outputTCELL4:OUT_OFX6
SROB5outputTCELL5:OUT_OFX2
SROB6outputTCELL5:OUT_OFX3
SROB7outputTCELL5:OUT_OFX4
SROB8outputTCELL5:OUT_OFX5
SROB9outputTCELL6:OUT_OFX2

Bel wires

ecp DSP bel wires
WirePins
TCELL0:IMUX_A0DSP0.MUA00
TCELL0:IMUX_A1DSP0.MUA04
TCELL0:IMUX_A2DSP0.MUA08
TCELL0:IMUX_A3DSP0.MUA012
TCELL0:IMUX_A4DSP0.MUA016
TCELL0:IMUX_B0DSP0.MUA01
TCELL0:IMUX_B1DSP0.MUA05
TCELL0:IMUX_B2DSP0.MUA09
TCELL0:IMUX_B3DSP0.MUA013
TCELL0:IMUX_B4DSP0.MUA017
TCELL0:IMUX_C0DSP0.MUA02
TCELL0:IMUX_C1DSP0.MUA06
TCELL0:IMUX_C2DSP0.MUA010
TCELL0:IMUX_C3DSP0.MUA014
TCELL0:IMUX_D0DSP0.MUA03
TCELL0:IMUX_D1DSP0.MUA07
TCELL0:IMUX_D2DSP0.MUA011
TCELL0:IMUX_D3DSP0.MUA015
TCELL0:IMUX_CLK0DSP0.CLK0
TCELL0:IMUX_LSR1DSP0.SIGNEDAB0
TCELL0:IMUX_CE0DSP0.CE0
TCELL0:OUT_F0DSP0.MUP00
TCELL0:OUT_F1DSP0.MUP01
TCELL0:OUT_F2DSP0.MUP02
TCELL0:OUT_F3DSP0.MUP03
TCELL0:OUT_F4DSP0.MUP04
TCELL0:OUT_F5DSP0.MUP05
TCELL0:OUT_F6DSP0.MUP06
TCELL0:OUT_F7DSP0.MUP07
TCELL0:OUT_Q0DSP0.MUP08
TCELL0:OUT_Q1DSP0.MUP09
TCELL0:OUT_Q2DSP0.MUP010
TCELL0:OUT_Q3DSP0.MUP011
TCELL0:OUT_Q4DSP0.MUP012
TCELL0:OUT_Q5DSP0.MUP013
TCELL0:OUT_Q6DSP0.MUP014
TCELL0:OUT_Q7DSP0.MUP015
TCELL0:OUT_OFX0DSP0.MUP016
TCELL0:OUT_OFX2DSP0.SROA0
TCELL0:OUT_OFX3DSP0.SROA1
TCELL0:OUT_OFX4DSP0.SROA2
TCELL0:OUT_OFX5DSP0.SROA3
TCELL0:OUT_OFX6DSP0.SROA4
TCELL0:OUT_OFX7DSP0.MUP017
TCELL1:IMUX_A0DSP0.MUB00
TCELL1:IMUX_A1DSP0.MUB04
TCELL1:IMUX_A2DSP0.MUB08
TCELL1:IMUX_A3DSP0.MUB012
TCELL1:IMUX_A4DSP0.MUB016
TCELL1:IMUX_B0DSP0.MUB01
TCELL1:IMUX_B1DSP0.MUB05
TCELL1:IMUX_B2DSP0.MUB09
TCELL1:IMUX_B3DSP0.MUB013
TCELL1:IMUX_B4DSP0.MUB017
TCELL1:IMUX_C0DSP0.MUB02
TCELL1:IMUX_C1DSP0.MUB06
TCELL1:IMUX_C2DSP0.MUB010
TCELL1:IMUX_C3DSP0.MUB014
TCELL1:IMUX_D0DSP0.MUB03
TCELL1:IMUX_D1DSP0.MUB07
TCELL1:IMUX_D2DSP0.MUB011
TCELL1:IMUX_D3DSP0.MUB015
TCELL1:IMUX_LSR1DSP0.RST0
TCELL1:IMUX_CE0DSP0.ADDNSUB1
TCELL1:OUT_F0DSP0.MUP018
TCELL1:OUT_F1DSP0.MUP019
TCELL1:OUT_F2DSP0.MUP020
TCELL1:OUT_F3DSP0.MUP021
TCELL1:OUT_F4DSP0.MUP022
TCELL1:OUT_F5DSP0.MUP023
TCELL1:OUT_F6DSP0.MUP024
TCELL1:OUT_F7DSP0.MUP025
TCELL1:OUT_Q0DSP0.MUP026
TCELL1:OUT_Q1DSP0.MUP027
TCELL1:OUT_Q2DSP0.MUP028
TCELL1:OUT_Q3DSP0.MUP029
TCELL1:OUT_Q4DSP0.MUP030
TCELL1:OUT_Q5DSP0.MUP031
TCELL1:OUT_Q6DSP0.MUP032
TCELL1:OUT_Q7DSP0.MUP033
TCELL1:OUT_OFX0DSP0.MUP034
TCELL1:OUT_OFX2DSP0.SROA5
TCELL1:OUT_OFX3DSP0.SROA6
TCELL1:OUT_OFX4DSP0.SROA7
TCELL1:OUT_OFX5DSP0.SROA8
TCELL1:OUT_OFX7DSP0.MUP035
TCELL2:IMUX_A0DSP0.MUA10
TCELL2:IMUX_A1DSP0.MUA14
TCELL2:IMUX_A2DSP0.MUA18
TCELL2:IMUX_A3DSP0.MUA112
TCELL2:IMUX_A4DSP0.MUA116
TCELL2:IMUX_B0DSP0.MUA11
TCELL2:IMUX_B1DSP0.MUA15
TCELL2:IMUX_B2DSP0.MUA19
TCELL2:IMUX_B3DSP0.MUA113
TCELL2:IMUX_B4DSP0.MUA117
TCELL2:IMUX_C0DSP0.MUA12
TCELL2:IMUX_C1DSP0.MUA16
TCELL2:IMUX_C2DSP0.MUA110
TCELL2:IMUX_C3DSP0.MUA114
TCELL2:IMUX_D0DSP0.MUA13
TCELL2:IMUX_D1DSP0.MUA17
TCELL2:IMUX_D2DSP0.MUA111
TCELL2:IMUX_D3DSP0.MUA115
TCELL2:IMUX_CLK0DSP0.CLK1
TCELL2:IMUX_LSR1DSP0.SIGNEDAB1
TCELL2:IMUX_CE0DSP0.CE1
TCELL2:OUT_F0DSP0.MUP10
TCELL2:OUT_F1DSP0.MUP11
TCELL2:OUT_F2DSP0.MUP12
TCELL2:OUT_F3DSP0.MUP13
TCELL2:OUT_F4DSP0.MUP14
TCELL2:OUT_F5DSP0.MUP15
TCELL2:OUT_F6DSP0.MUP16
TCELL2:OUT_F7DSP0.MUP17
TCELL2:OUT_Q0DSP0.MUP18
TCELL2:OUT_Q1DSP0.MUP19
TCELL2:OUT_Q2DSP0.MUP110
TCELL2:OUT_Q3DSP0.MUP111
TCELL2:OUT_Q4DSP0.MUP112
TCELL2:OUT_Q5DSP0.MUP113
TCELL2:OUT_Q6DSP0.MUP114
TCELL2:OUT_Q7DSP0.MUP115
TCELL2:OUT_OFX0DSP0.MUP116
TCELL2:OUT_OFX2DSP0.SROA9
TCELL2:OUT_OFX3DSP0.SROA10
TCELL2:OUT_OFX4DSP0.SROA11
TCELL2:OUT_OFX5DSP0.SROA12
TCELL2:OUT_OFX6DSP0.SROA13
TCELL2:OUT_OFX7DSP0.MUP117
TCELL3:IMUX_A0DSP0.MUB10
TCELL3:IMUX_A1DSP0.MUB14
TCELL3:IMUX_A2DSP0.MUB18
TCELL3:IMUX_A3DSP0.MUB112
TCELL3:IMUX_A4DSP0.MUB116
TCELL3:IMUX_B0DSP0.MUB11
TCELL3:IMUX_B1DSP0.MUB15
TCELL3:IMUX_B2DSP0.MUB19
TCELL3:IMUX_B3DSP0.MUB113
TCELL3:IMUX_B4DSP0.MUB117
TCELL3:IMUX_C0DSP0.MUB12
TCELL3:IMUX_C1DSP0.MUB16
TCELL3:IMUX_C2DSP0.MUB110
TCELL3:IMUX_C3DSP0.MUB114
TCELL3:IMUX_D0DSP0.MUB13
TCELL3:IMUX_D1DSP0.MUB17
TCELL3:IMUX_D2DSP0.MUB111
TCELL3:IMUX_D3DSP0.MUB115
TCELL3:IMUX_LSR1DSP0.RST1
TCELL3:IMUX_CE0DSP0.ACCUMSLOAD1
TCELL3:OUT_F0DSP0.MUP118
TCELL3:OUT_F1DSP0.MUP119
TCELL3:OUT_F2DSP0.MUP120
TCELL3:OUT_F3DSP0.MUP121
TCELL3:OUT_F4DSP0.MUP122
TCELL3:OUT_F5DSP0.MUP123
TCELL3:OUT_F6DSP0.MUP124
TCELL3:OUT_F7DSP0.MUP125
TCELL3:OUT_Q0DSP0.MUP126
TCELL3:OUT_Q1DSP0.MUP127
TCELL3:OUT_Q2DSP0.MUP128
TCELL3:OUT_Q3DSP0.MUP129
TCELL3:OUT_Q4DSP0.MUP130
TCELL3:OUT_Q5DSP0.MUP131
TCELL3:OUT_Q6DSP0.MUP132
TCELL3:OUT_Q7DSP0.MUP133
TCELL3:OUT_OFX0DSP0.MUP134
TCELL3:OUT_OFX2DSP0.SROA14
TCELL3:OUT_OFX3DSP0.SROA15
TCELL3:OUT_OFX4DSP0.SROA16
TCELL3:OUT_OFX5DSP0.SROA17
TCELL3:OUT_OFX7DSP0.MUP135
TCELL4:IMUX_A0DSP0.MUA20
TCELL4:IMUX_A1DSP0.MUA24
TCELL4:IMUX_A2DSP0.MUA28
TCELL4:IMUX_A3DSP0.MUA212
TCELL4:IMUX_A4DSP0.MUA216
TCELL4:IMUX_B0DSP0.MUA21
TCELL4:IMUX_B1DSP0.MUA25
TCELL4:IMUX_B2DSP0.MUA29
TCELL4:IMUX_B3DSP0.MUA213
TCELL4:IMUX_B4DSP0.MUA217
TCELL4:IMUX_C0DSP0.MUA22
TCELL4:IMUX_C1DSP0.MUA26
TCELL4:IMUX_C2DSP0.MUA210
TCELL4:IMUX_C3DSP0.MUA214
TCELL4:IMUX_D0DSP0.MUA23
TCELL4:IMUX_D1DSP0.MUA27
TCELL4:IMUX_D2DSP0.MUA211
TCELL4:IMUX_D3DSP0.MUA215
TCELL4:IMUX_CLK0DSP0.CLK2
TCELL4:IMUX_LSR1DSP0.SIGNEDAB2
TCELL4:IMUX_CE0DSP0.CE2
TCELL4:OUT_F0DSP0.MUP20
TCELL4:OUT_F1DSP0.MUP21
TCELL4:OUT_F2DSP0.MUP22
TCELL4:OUT_F3DSP0.MUP23
TCELL4:OUT_F4DSP0.MUP24
TCELL4:OUT_F5DSP0.MUP25
TCELL4:OUT_F6DSP0.MUP26
TCELL4:OUT_F7DSP0.MUP27
TCELL4:OUT_Q0DSP0.MUP28
TCELL4:OUT_Q1DSP0.MUP29
TCELL4:OUT_Q2DSP0.MUP210
TCELL4:OUT_Q3DSP0.MUP211
TCELL4:OUT_Q4DSP0.MUP212
TCELL4:OUT_Q5DSP0.MUP213
TCELL4:OUT_Q6DSP0.MUP214
TCELL4:OUT_Q7DSP0.MUP215
TCELL4:OUT_OFX0DSP0.MUP216
TCELL4:OUT_OFX2DSP0.SROB0
TCELL4:OUT_OFX3DSP0.SROB1
TCELL4:OUT_OFX4DSP0.SROB2
TCELL4:OUT_OFX5DSP0.SROB3
TCELL4:OUT_OFX6DSP0.SROB4
TCELL4:OUT_OFX7DSP0.MUP217
TCELL5:IMUX_A0DSP0.MUB20
TCELL5:IMUX_A1DSP0.MUB24
TCELL5:IMUX_A2DSP0.MUB28
TCELL5:IMUX_A3DSP0.MUB212
TCELL5:IMUX_A4DSP0.MUB216
TCELL5:IMUX_B0DSP0.MUB21
TCELL5:IMUX_B1DSP0.MUB25
TCELL5:IMUX_B2DSP0.MUB29
TCELL5:IMUX_B3DSP0.MUB213
TCELL5:IMUX_B4DSP0.MUB217
TCELL5:IMUX_C0DSP0.MUB22
TCELL5:IMUX_C1DSP0.MUB26
TCELL5:IMUX_C2DSP0.MUB210
TCELL5:IMUX_C3DSP0.MUB214
TCELL5:IMUX_D0DSP0.MUB23
TCELL5:IMUX_D1DSP0.MUB27
TCELL5:IMUX_D2DSP0.MUB211
TCELL5:IMUX_D3DSP0.MUB215
TCELL5:IMUX_LSR1DSP0.RST2
TCELL5:IMUX_CE0DSP0.ACCUMSLOAD3
TCELL5:OUT_F0DSP0.MUP218
TCELL5:OUT_F1DSP0.MUP219
TCELL5:OUT_F2DSP0.MUP220
TCELL5:OUT_F3DSP0.MUP221
TCELL5:OUT_F4DSP0.MUP222
TCELL5:OUT_F5DSP0.MUP223
TCELL5:OUT_F6DSP0.MUP224
TCELL5:OUT_F7DSP0.MUP225
TCELL5:OUT_Q0DSP0.MUP226
TCELL5:OUT_Q1DSP0.MUP227
TCELL5:OUT_Q2DSP0.MUP228
TCELL5:OUT_Q3DSP0.MUP229
TCELL5:OUT_Q4DSP0.MUP230
TCELL5:OUT_Q5DSP0.MUP231
TCELL5:OUT_Q6DSP0.MUP232
TCELL5:OUT_Q7DSP0.MUP233
TCELL5:OUT_OFX0DSP0.MUP234
TCELL5:OUT_OFX2DSP0.SROB5
TCELL5:OUT_OFX3DSP0.SROB6
TCELL5:OUT_OFX4DSP0.SROB7
TCELL5:OUT_OFX5DSP0.SROB8
TCELL5:OUT_OFX7DSP0.MUP235
TCELL6:IMUX_A0DSP0.MUA30
TCELL6:IMUX_A1DSP0.MUA34
TCELL6:IMUX_A2DSP0.MUA38
TCELL6:IMUX_A3DSP0.MUA312
TCELL6:IMUX_A4DSP0.MUA316
TCELL6:IMUX_B0DSP0.MUA31
TCELL6:IMUX_B1DSP0.MUA35
TCELL6:IMUX_B2DSP0.MUA39
TCELL6:IMUX_B3DSP0.MUA313
TCELL6:IMUX_B4DSP0.MUA317
TCELL6:IMUX_C0DSP0.MUA32
TCELL6:IMUX_C1DSP0.MUA36
TCELL6:IMUX_C2DSP0.MUA310
TCELL6:IMUX_C3DSP0.MUA314
TCELL6:IMUX_D0DSP0.MUA33
TCELL6:IMUX_D1DSP0.MUA37
TCELL6:IMUX_D2DSP0.MUA311
TCELL6:IMUX_D3DSP0.MUA315
TCELL6:IMUX_CLK0DSP0.CLK3
TCELL6:IMUX_LSR1DSP0.SIGNEDAB3
TCELL6:IMUX_CE0DSP0.CE3
TCELL6:OUT_F0DSP0.MUP30
TCELL6:OUT_F1DSP0.MUP31
TCELL6:OUT_F2DSP0.MUP32
TCELL6:OUT_F3DSP0.MUP33
TCELL6:OUT_F4DSP0.MUP34
TCELL6:OUT_F5DSP0.MUP35
TCELL6:OUT_F6DSP0.MUP36
TCELL6:OUT_F7DSP0.MUP37
TCELL6:OUT_Q0DSP0.MUP38
TCELL6:OUT_Q1DSP0.MUP39
TCELL6:OUT_Q2DSP0.MUP310
TCELL6:OUT_Q3DSP0.MUP311
TCELL6:OUT_Q4DSP0.MUP312
TCELL6:OUT_Q5DSP0.MUP313
TCELL6:OUT_Q6DSP0.MUP314
TCELL6:OUT_Q7DSP0.MUP315
TCELL6:OUT_OFX0DSP0.MUP316
TCELL6:OUT_OFX2DSP0.SROB9
TCELL6:OUT_OFX3DSP0.SROB10
TCELL6:OUT_OFX4DSP0.SROB11
TCELL6:OUT_OFX5DSP0.SROB12
TCELL6:OUT_OFX6DSP0.SROB13
TCELL6:OUT_OFX7DSP0.MUP317
TCELL7:IMUX_A0DSP0.MUB30
TCELL7:IMUX_A1DSP0.MUB34
TCELL7:IMUX_A2DSP0.MUB38
TCELL7:IMUX_A3DSP0.MUB312
TCELL7:IMUX_A4DSP0.MUB316
TCELL7:IMUX_B0DSP0.MUB31
TCELL7:IMUX_B1DSP0.MUB35
TCELL7:IMUX_B2DSP0.MUB39
TCELL7:IMUX_B3DSP0.MUB313
TCELL7:IMUX_B4DSP0.MUB317
TCELL7:IMUX_C0DSP0.MUB32
TCELL7:IMUX_C1DSP0.MUB36
TCELL7:IMUX_C2DSP0.MUB310
TCELL7:IMUX_C3DSP0.MUB314
TCELL7:IMUX_D0DSP0.MUB33
TCELL7:IMUX_D1DSP0.MUB37
TCELL7:IMUX_D2DSP0.MUB311
TCELL7:IMUX_D3DSP0.MUB315
TCELL7:IMUX_LSR1DSP0.RST3
TCELL7:IMUX_CE0DSP0.ADDNSUB3
TCELL7:OUT_F0DSP0.MUP318
TCELL7:OUT_F1DSP0.MUP319
TCELL7:OUT_F2DSP0.MUP320
TCELL7:OUT_F3DSP0.MUP321
TCELL7:OUT_F4DSP0.MUP322
TCELL7:OUT_F5DSP0.MUP323
TCELL7:OUT_F6DSP0.MUP324
TCELL7:OUT_F7DSP0.MUP325
TCELL7:OUT_Q0DSP0.MUP326
TCELL7:OUT_Q1DSP0.MUP327
TCELL7:OUT_Q2DSP0.MUP328
TCELL7:OUT_Q3DSP0.MUP329
TCELL7:OUT_Q4DSP0.MUP330
TCELL7:OUT_Q5DSP0.MUP331
TCELL7:OUT_Q6DSP0.MUP332
TCELL7:OUT_Q7DSP0.MUP333
TCELL7:OUT_OFX0DSP0.MUP334
TCELL7:OUT_OFX2DSP0.SROB14
TCELL7:OUT_OFX3DSP0.SROB15
TCELL7:OUT_OFX4DSP0.SROB16
TCELL7:OUT_OFX5DSP0.SROB17
TCELL7:OUT_OFX7DSP0.MUP335