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DSP

Tile DSP

Cells: 9

Bel DSP0

ecp2 DSP bel DSP0
PinDirectionWires
ACCUMSLOAD1inputTCELL2:IMUX_CLK0
ACCUMSLOAD3inputTCELL5:IMUX_CLK1
ADDNSUB1inputTCELL1:IMUX_CLK1
ADDNSUB3inputTCELL7:IMUX_CLK1
CE0inputTCELL2:IMUX_CE0
CE1inputTCELL3:IMUX_CE0
CE2inputTCELL4:IMUX_CE0
CE3inputTCELL5:IMUX_CE0
CLK0inputTCELL3:IMUX_CLK1
CLK1inputTCELL3:IMUX_CLK0
CLK2inputTCELL4:IMUX_CLK0
CLK3inputTCELL4:IMUX_CLK1
LD0_MAC52inputTCELL0:IMUX_B4
LD0_MULT36inputTCELL2:IMUX_B4
LD10_MAC52inputTCELL1:IMUX_B5
LD10_MULT36inputTCELL4:IMUX_A1
LD11_MAC52inputTCELL1:IMUX_A5
LD11_MULT36inputTCELL4:IMUX_D6
LD12_MAC52inputTCELL1:IMUX_D4
LD12_MULT36inputTCELL5:IMUX_A1
LD13_MAC52inputTCELL1:IMUX_A1
LD13_MULT36inputTCELL5:IMUX_D6
LD14_MAC52inputTCELL1:IMUX_D6
LD14_MULT36inputTCELL6:IMUX_A1
LD15_MAC52inputTCELL1:IMUX_A3
LD15_MULT36inputTCELL6:IMUX_D6
LD1_MAC52inputTCELL0:IMUX_A4
LD1_MULT36inputTCELL2:IMUX_A4
LD2_MAC52inputTCELL0:IMUX_B5
LD2_MULT36inputTCELL2:IMUX_B5
LD3_MAC52inputTCELL0:IMUX_A5
LD3_MULT36inputTCELL2:IMUX_A5
LD4_MAC52inputTCELL0:IMUX_D4
LD4_MULT36inputTCELL2:IMUX_D4
LD5_MAC52inputTCELL0:IMUX_A1
LD5_MULT36inputTCELL2:IMUX_A1
LD6_MAC52inputTCELL0:IMUX_D6
LD6_MULT36inputTCELL2:IMUX_D6
LD7_MAC52inputTCELL0:IMUX_A3
LD7_MULT36inputTCELL2:IMUX_A3
LD8_MAC52inputTCELL1:IMUX_B4
LD8_MULT36inputTCELL3:IMUX_A1
LD9_MAC52inputTCELL1:IMUX_A4
LD9_MULT36inputTCELL3:IMUX_D6
MUA00inputTCELL0:IMUX_D0
MUA01inputTCELL0:IMUX_B0
MUA010inputTCELL1:IMUX_C0
MUA011inputTCELL1:IMUX_A0
MUA012inputTCELL2:IMUX_D0
MUA013inputTCELL2:IMUX_B0
MUA014inputTCELL2:IMUX_D2
MUA015inputTCELL2:IMUX_B1
MUA016inputTCELL2:IMUX_C0
MUA017inputTCELL2:IMUX_A0
MUA02inputTCELL0:IMUX_D2
MUA03inputTCELL0:IMUX_B1
MUA04inputTCELL0:IMUX_C0
MUA05inputTCELL0:IMUX_A0
MUA06inputTCELL1:IMUX_D0
MUA07inputTCELL1:IMUX_B0
MUA08inputTCELL1:IMUX_D2
MUA09inputTCELL1:IMUX_B1
MUA10inputTCELL3:IMUX_D0
MUA11inputTCELL3:IMUX_B0
MUA110inputTCELL4:IMUX_C0
MUA111inputTCELL4:IMUX_A0
MUA112inputTCELL5:IMUX_D0
MUA113inputTCELL5:IMUX_B0
MUA114inputTCELL5:IMUX_D2
MUA115inputTCELL5:IMUX_B1
MUA116inputTCELL5:IMUX_C0
MUA117inputTCELL5:IMUX_A0
MUA12inputTCELL3:IMUX_D2
MUA13inputTCELL3:IMUX_B1
MUA14inputTCELL3:IMUX_C0
MUA15inputTCELL3:IMUX_A0
MUA16inputTCELL4:IMUX_D0
MUA17inputTCELL4:IMUX_B0
MUA18inputTCELL4:IMUX_D2
MUA19inputTCELL4:IMUX_B1
MUA20inputTCELL3:IMUX_A3
MUA21inputTCELL3:IMUX_A4
MUA210inputTCELL4:IMUX_D4
MUA211inputTCELL4:IMUX_B5
MUA212inputTCELL5:IMUX_A3
MUA213inputTCELL5:IMUX_A4
MUA214inputTCELL5:IMUX_B4
MUA215inputTCELL5:IMUX_A5
MUA216inputTCELL5:IMUX_D4
MUA217inputTCELL5:IMUX_B5
MUA22inputTCELL3:IMUX_B4
MUA23inputTCELL3:IMUX_A5
MUA24inputTCELL3:IMUX_D4
MUA25inputTCELL3:IMUX_B5
MUA26inputTCELL4:IMUX_A3
MUA27inputTCELL4:IMUX_A4
MUA28inputTCELL4:IMUX_B4
MUA29inputTCELL4:IMUX_A5
MUA30inputTCELL6:IMUX_A3
MUA31inputTCELL6:IMUX_A4
MUA310inputTCELL7:IMUX_D4
MUA311inputTCELL7:IMUX_B5
MUA312inputTCELL8:IMUX_A3
MUA313inputTCELL8:IMUX_A4
MUA314inputTCELL8:IMUX_B4
MUA315inputTCELL8:IMUX_A5
MUA316inputTCELL8:IMUX_D4
MUA317inputTCELL8:IMUX_B5
MUA32inputTCELL6:IMUX_B4
MUA33inputTCELL6:IMUX_A5
MUA34inputTCELL6:IMUX_D4
MUA35inputTCELL6:IMUX_B5
MUA36inputTCELL7:IMUX_A3
MUA37inputTCELL7:IMUX_A4
MUA38inputTCELL7:IMUX_B4
MUA39inputTCELL7:IMUX_A5
MUB00inputTCELL0:IMUX_C4
MUB01inputTCELL0:IMUX_B2
MUB010inputTCELL1:IMUX_C2
MUB011inputTCELL1:IMUX_A2
MUB012inputTCELL2:IMUX_C4
MUB013inputTCELL2:IMUX_B2
MUB014inputTCELL2:IMUX_C6
MUB015inputTCELL2:IMUX_B3
MUB016inputTCELL2:IMUX_C2
MUB017inputTCELL2:IMUX_A2
MUB02inputTCELL0:IMUX_C6
MUB03inputTCELL0:IMUX_B3
MUB04inputTCELL0:IMUX_C2
MUB05inputTCELL0:IMUX_A2
MUB06inputTCELL1:IMUX_C4
MUB07inputTCELL1:IMUX_B2
MUB08inputTCELL1:IMUX_C6
MUB09inputTCELL1:IMUX_B3
MUB10inputTCELL3:IMUX_C4
MUB11inputTCELL3:IMUX_B2
MUB110inputTCELL4:IMUX_C2
MUB111inputTCELL4:IMUX_A2
MUB112inputTCELL5:IMUX_C4
MUB113inputTCELL5:IMUX_B2
MUB114inputTCELL5:IMUX_C6
MUB115inputTCELL5:IMUX_B3
MUB116inputTCELL5:IMUX_C2
MUB117inputTCELL5:IMUX_A2
MUB12inputTCELL3:IMUX_C6
MUB13inputTCELL3:IMUX_B3
MUB14inputTCELL3:IMUX_C2
MUB15inputTCELL3:IMUX_A2
MUB16inputTCELL4:IMUX_C4
MUB17inputTCELL4:IMUX_B2
MUB18inputTCELL4:IMUX_C6
MUB19inputTCELL4:IMUX_B3
MUB20inputTCELL6:IMUX_D0
MUB21inputTCELL6:IMUX_B0
MUB210inputTCELL7:IMUX_C0
MUB211inputTCELL7:IMUX_A0
MUB212inputTCELL8:IMUX_D0
MUB213inputTCELL8:IMUX_B0
MUB214inputTCELL8:IMUX_D2
MUB215inputTCELL8:IMUX_B1
MUB216inputTCELL8:IMUX_C0
MUB217inputTCELL8:IMUX_A0
MUB22inputTCELL6:IMUX_D2
MUB23inputTCELL6:IMUX_B1
MUB24inputTCELL6:IMUX_C0
MUB25inputTCELL6:IMUX_A0
MUB26inputTCELL7:IMUX_D0
MUB27inputTCELL7:IMUX_B0
MUB28inputTCELL7:IMUX_D2
MUB29inputTCELL7:IMUX_B1
MUB30inputTCELL6:IMUX_C4
MUB31inputTCELL6:IMUX_B2
MUB310inputTCELL7:IMUX_C2
MUB311inputTCELL7:IMUX_A2
MUB312inputTCELL8:IMUX_C4
MUB313inputTCELL8:IMUX_B2
MUB314inputTCELL8:IMUX_C6
MUB315inputTCELL8:IMUX_B3
MUB316inputTCELL8:IMUX_C2
MUB317inputTCELL8:IMUX_A2
MUB32inputTCELL6:IMUX_C6
MUB33inputTCELL6:IMUX_B3
MUB34inputTCELL6:IMUX_C2
MUB35inputTCELL6:IMUX_A2
MUB36inputTCELL7:IMUX_C4
MUB37inputTCELL7:IMUX_B2
MUB38inputTCELL7:IMUX_C6
MUB39inputTCELL7:IMUX_B3
MUP00outputTCELL0:OUT_F6
MUP01outputTCELL0:OUT_F7
MUP010outputTCELL2:OUT_Q6
MUP011outputTCELL2:OUT_Q7
MUP012outputTCELL3:OUT_F6
MUP013outputTCELL3:OUT_F7
MUP014outputTCELL3:OUT_Q6
MUP015outputTCELL3:OUT_Q7
MUP016outputTCELL4:OUT_F6
MUP017outputTCELL4:OUT_F7
MUP018outputTCELL3:OUT_F0
MUP019outputTCELL3:OUT_F1
MUP02outputTCELL0:OUT_Q6
MUP020outputTCELL3:OUT_F2
MUP021outputTCELL3:OUT_F3
MUP022outputTCELL3:OUT_F4
MUP023outputTCELL3:OUT_F5
MUP024outputTCELL4:OUT_F0
MUP025outputTCELL4:OUT_F1
MUP026outputTCELL4:OUT_F2
MUP027outputTCELL4:OUT_F3
MUP028outputTCELL4:OUT_F4
MUP029outputTCELL4:OUT_F5
MUP03outputTCELL0:OUT_Q7
MUP030outputTCELL5:OUT_F0
MUP031outputTCELL5:OUT_F1
MUP032outputTCELL5:OUT_F2
MUP033outputTCELL5:OUT_F3
MUP034outputTCELL5:OUT_F4
MUP035outputTCELL5:OUT_F5
MUP04outputTCELL1:OUT_F6
MUP05outputTCELL1:OUT_F7
MUP06outputTCELL1:OUT_Q6
MUP07outputTCELL1:OUT_Q7
MUP08outputTCELL2:OUT_F6
MUP09outputTCELL2:OUT_F7
MUP10outputTCELL0:OUT_Q0
MUP11outputTCELL0:OUT_Q1
MUP110outputTCELL1:OUT_Q4
MUP111outputTCELL1:OUT_Q5
MUP112outputTCELL2:OUT_Q0
MUP113outputTCELL2:OUT_Q1
MUP114outputTCELL2:OUT_Q2
MUP115outputTCELL2:OUT_Q3
MUP116outputTCELL2:OUT_Q4
MUP117outputTCELL2:OUT_Q5
MUP118outputTCELL0:OUT_F0
MUP119outputTCELL0:OUT_F1
MUP12outputTCELL0:OUT_Q2
MUP120outputTCELL0:OUT_F2
MUP121outputTCELL0:OUT_F3
MUP122outputTCELL0:OUT_F4
MUP123outputTCELL0:OUT_F5
MUP124outputTCELL1:OUT_F0
MUP125outputTCELL1:OUT_F1
MUP126outputTCELL1:OUT_F2
MUP127outputTCELL1:OUT_F3
MUP128outputTCELL1:OUT_F4
MUP129outputTCELL1:OUT_F5
MUP13outputTCELL0:OUT_Q3
MUP130outputTCELL2:OUT_F0
MUP131outputTCELL2:OUT_F1
MUP132outputTCELL2:OUT_F2
MUP133outputTCELL2:OUT_F3
MUP134outputTCELL2:OUT_F4
MUP135outputTCELL2:OUT_F5
MUP14outputTCELL0:OUT_Q4
MUP15outputTCELL0:OUT_Q5
MUP16outputTCELL1:OUT_Q0
MUP17outputTCELL1:OUT_Q1
MUP18outputTCELL1:OUT_Q2
MUP19outputTCELL1:OUT_Q3
MUP20outputTCELL4:OUT_Q6
MUP21outputTCELL4:OUT_Q7
MUP210outputTCELL7:OUT_F6
MUP211outputTCELL7:OUT_F7
MUP212outputTCELL7:OUT_Q6
MUP213outputTCELL7:OUT_Q7
MUP214outputTCELL8:OUT_F6
MUP215outputTCELL8:OUT_F7
MUP216outputTCELL8:OUT_Q6
MUP217outputTCELL8:OUT_Q7
MUP218outputTCELL3:OUT_Q0
MUP219outputTCELL3:OUT_Q1
MUP22outputTCELL5:OUT_F6
MUP220outputTCELL3:OUT_Q2
MUP221outputTCELL3:OUT_Q3
MUP222outputTCELL3:OUT_Q4
MUP223outputTCELL3:OUT_Q5
MUP224outputTCELL4:OUT_Q0
MUP225outputTCELL4:OUT_Q1
MUP226outputTCELL4:OUT_Q2
MUP227outputTCELL4:OUT_Q3
MUP228outputTCELL4:OUT_Q4
MUP229outputTCELL4:OUT_Q5
MUP23outputTCELL5:OUT_F7
MUP230outputTCELL5:OUT_Q0
MUP231outputTCELL5:OUT_Q1
MUP232outputTCELL5:OUT_Q2
MUP233outputTCELL5:OUT_Q3
MUP234outputTCELL5:OUT_Q4
MUP235outputTCELL5:OUT_Q5
MUP24outputTCELL5:OUT_Q6
MUP25outputTCELL5:OUT_Q7
MUP26outputTCELL6:OUT_F6
MUP27outputTCELL6:OUT_F7
MUP28outputTCELL6:OUT_Q6
MUP29outputTCELL6:OUT_Q7
MUP30outputTCELL6:OUT_Q0
MUP31outputTCELL6:OUT_Q1
MUP310outputTCELL7:OUT_Q4
MUP311outputTCELL7:OUT_Q5
MUP312outputTCELL8:OUT_Q0
MUP313outputTCELL8:OUT_Q1
MUP314outputTCELL8:OUT_Q2
MUP315outputTCELL8:OUT_Q3
MUP316outputTCELL8:OUT_Q4
MUP317outputTCELL8:OUT_Q5
MUP318outputTCELL6:OUT_F0
MUP319outputTCELL6:OUT_F1
MUP32outputTCELL6:OUT_Q2
MUP320outputTCELL6:OUT_F2
MUP321outputTCELL6:OUT_F3
MUP322outputTCELL6:OUT_F4
MUP323outputTCELL6:OUT_F5
MUP324outputTCELL7:OUT_F0
MUP325outputTCELL7:OUT_F1
MUP326outputTCELL7:OUT_F2
MUP327outputTCELL7:OUT_F3
MUP328outputTCELL7:OUT_F4
MUP329outputTCELL7:OUT_F5
MUP33outputTCELL6:OUT_Q3
MUP330outputTCELL8:OUT_F0
MUP331outputTCELL8:OUT_F1
MUP332outputTCELL8:OUT_F2
MUP333outputTCELL8:OUT_F3
MUP334outputTCELL8:OUT_F4
MUP335outputTCELL8:OUT_F5
MUP34outputTCELL6:OUT_Q4
MUP35outputTCELL6:OUT_Q5
MUP36outputTCELL7:OUT_Q0
MUP37outputTCELL7:OUT_Q1
MUP38outputTCELL7:OUT_Q2
MUP39outputTCELL7:OUT_Q3
RST0inputTCELL2:IMUX_LSR0
RST1inputTCELL3:IMUX_LSR0
RST2inputTCELL4:IMUX_LSR0
RST3inputTCELL5:IMUX_LSR0
SIGNEDA0inputTCELL0:IMUX_LSR0
SIGNEDA1inputTCELL1:IMUX_LSR0
SIGNEDA2inputTCELL6:IMUX_LSR0
SIGNEDA3inputTCELL8:IMUX_LSR0
SIGNEDB0inputTCELL1:IMUX_LSR1
SIGNEDB1inputTCELL6:IMUX_LSR1
SIGNEDB2inputTCELL7:IMUX_LSR1
SIGNEDB3inputTCELL8:IMUX_LSR1
SOURCEA0inputTCELL0:IMUX_CLK1
SOURCEA1inputTCELL6:IMUX_CLK1
SOURCEA2inputTCELL7:IMUX_CLK0
SOURCEA3inputTCELL8:IMUX_CLK1
SOURCEB0inputTCELL0:IMUX_CLK0
SOURCEB1inputTCELL1:IMUX_CLK0
SOURCEB2inputTCELL6:IMUX_CLK0
SOURCEB3inputTCELL8:IMUX_CLK0
SROA0outputTCELL6:OUT_Q0
SROA1outputTCELL6:OUT_Q1
SROA10outputTCELL7:OUT_Q4
SROA11outputTCELL7:OUT_Q5
SROA12outputTCELL8:OUT_Q0
SROA13outputTCELL8:OUT_Q1
SROA14outputTCELL8:OUT_Q2
SROA15outputTCELL8:OUT_Q3
SROA16outputTCELL8:OUT_Q4
SROA17outputTCELL8:OUT_Q5
SROA2outputTCELL6:OUT_Q2
SROA3outputTCELL6:OUT_Q3
SROA4outputTCELL6:OUT_Q4
SROA5outputTCELL6:OUT_Q5
SROA6outputTCELL7:OUT_Q0
SROA7outputTCELL7:OUT_Q1
SROA8outputTCELL7:OUT_Q2
SROA9outputTCELL7:OUT_Q3
SROB0outputTCELL6:OUT_F0
SROB1outputTCELL6:OUT_F1
SROB10outputTCELL7:OUT_F4
SROB11outputTCELL7:OUT_F5
SROB12outputTCELL8:OUT_F0
SROB13outputTCELL8:OUT_F1
SROB14outputTCELL8:OUT_F2
SROB15outputTCELL8:OUT_F3
SROB16outputTCELL8:OUT_F4
SROB17outputTCELL8:OUT_F5
SROB2outputTCELL6:OUT_F2
SROB3outputTCELL6:OUT_F3
SROB4outputTCELL6:OUT_F4
SROB5outputTCELL6:OUT_F5
SROB6outputTCELL7:OUT_F0
SROB7outputTCELL7:OUT_F1
SROB8outputTCELL7:OUT_F2
SROB9outputTCELL7:OUT_F3

Bel wires

ecp2 DSP bel wires
WirePins
TCELL0:IMUX_A0DSP0.MUA05
TCELL0:IMUX_A1DSP0.LD5_MAC52
TCELL0:IMUX_A2DSP0.MUB05
TCELL0:IMUX_A3DSP0.LD7_MAC52
TCELL0:IMUX_A4DSP0.LD1_MAC52
TCELL0:IMUX_A5DSP0.LD3_MAC52
TCELL0:IMUX_B0DSP0.MUA01
TCELL0:IMUX_B1DSP0.MUA03
TCELL0:IMUX_B2DSP0.MUB01
TCELL0:IMUX_B3DSP0.MUB03
TCELL0:IMUX_B4DSP0.LD0_MAC52
TCELL0:IMUX_B5DSP0.LD2_MAC52
TCELL0:IMUX_C0DSP0.MUA04
TCELL0:IMUX_C2DSP0.MUB04
TCELL0:IMUX_C4DSP0.MUB00
TCELL0:IMUX_C6DSP0.MUB02
TCELL0:IMUX_D0DSP0.MUA00
TCELL0:IMUX_D2DSP0.MUA02
TCELL0:IMUX_D4DSP0.LD4_MAC52
TCELL0:IMUX_D6DSP0.LD6_MAC52
TCELL0:IMUX_CLK0DSP0.SOURCEB0
TCELL0:IMUX_CLK1DSP0.SOURCEA0
TCELL0:IMUX_LSR0DSP0.SIGNEDA0
TCELL0:OUT_F0DSP0.MUP118
TCELL0:OUT_F1DSP0.MUP119
TCELL0:OUT_F2DSP0.MUP120
TCELL0:OUT_F3DSP0.MUP121
TCELL0:OUT_F4DSP0.MUP122
TCELL0:OUT_F5DSP0.MUP123
TCELL0:OUT_F6DSP0.MUP00
TCELL0:OUT_F7DSP0.MUP01
TCELL0:OUT_Q0DSP0.MUP10
TCELL0:OUT_Q1DSP0.MUP11
TCELL0:OUT_Q2DSP0.MUP12
TCELL0:OUT_Q3DSP0.MUP13
TCELL0:OUT_Q4DSP0.MUP14
TCELL0:OUT_Q5DSP0.MUP15
TCELL0:OUT_Q6DSP0.MUP02
TCELL0:OUT_Q7DSP0.MUP03
TCELL1:IMUX_A0DSP0.MUA011
TCELL1:IMUX_A1DSP0.LD13_MAC52
TCELL1:IMUX_A2DSP0.MUB011
TCELL1:IMUX_A3DSP0.LD15_MAC52
TCELL1:IMUX_A4DSP0.LD9_MAC52
TCELL1:IMUX_A5DSP0.LD11_MAC52
TCELL1:IMUX_B0DSP0.MUA07
TCELL1:IMUX_B1DSP0.MUA09
TCELL1:IMUX_B2DSP0.MUB07
TCELL1:IMUX_B3DSP0.MUB09
TCELL1:IMUX_B4DSP0.LD8_MAC52
TCELL1:IMUX_B5DSP0.LD10_MAC52
TCELL1:IMUX_C0DSP0.MUA010
TCELL1:IMUX_C2DSP0.MUB010
TCELL1:IMUX_C4DSP0.MUB06
TCELL1:IMUX_C6DSP0.MUB08
TCELL1:IMUX_D0DSP0.MUA06
TCELL1:IMUX_D2DSP0.MUA08
TCELL1:IMUX_D4DSP0.LD12_MAC52
TCELL1:IMUX_D6DSP0.LD14_MAC52
TCELL1:IMUX_CLK0DSP0.SOURCEB1
TCELL1:IMUX_CLK1DSP0.ADDNSUB1
TCELL1:IMUX_LSR0DSP0.SIGNEDA1
TCELL1:IMUX_LSR1DSP0.SIGNEDB0
TCELL1:OUT_F0DSP0.MUP124
TCELL1:OUT_F1DSP0.MUP125
TCELL1:OUT_F2DSP0.MUP126
TCELL1:OUT_F3DSP0.MUP127
TCELL1:OUT_F4DSP0.MUP128
TCELL1:OUT_F5DSP0.MUP129
TCELL1:OUT_F6DSP0.MUP04
TCELL1:OUT_F7DSP0.MUP05
TCELL1:OUT_Q0DSP0.MUP16
TCELL1:OUT_Q1DSP0.MUP17
TCELL1:OUT_Q2DSP0.MUP18
TCELL1:OUT_Q3DSP0.MUP19
TCELL1:OUT_Q4DSP0.MUP110
TCELL1:OUT_Q5DSP0.MUP111
TCELL1:OUT_Q6DSP0.MUP06
TCELL1:OUT_Q7DSP0.MUP07
TCELL2:IMUX_A0DSP0.MUA017
TCELL2:IMUX_A1DSP0.LD5_MULT36
TCELL2:IMUX_A2DSP0.MUB017
TCELL2:IMUX_A3DSP0.LD7_MULT36
TCELL2:IMUX_A4DSP0.LD1_MULT36
TCELL2:IMUX_A5DSP0.LD3_MULT36
TCELL2:IMUX_B0DSP0.MUA013
TCELL2:IMUX_B1DSP0.MUA015
TCELL2:IMUX_B2DSP0.MUB013
TCELL2:IMUX_B3DSP0.MUB015
TCELL2:IMUX_B4DSP0.LD0_MULT36
TCELL2:IMUX_B5DSP0.LD2_MULT36
TCELL2:IMUX_C0DSP0.MUA016
TCELL2:IMUX_C2DSP0.MUB016
TCELL2:IMUX_C4DSP0.MUB012
TCELL2:IMUX_C6DSP0.MUB014
TCELL2:IMUX_D0DSP0.MUA012
TCELL2:IMUX_D2DSP0.MUA014
TCELL2:IMUX_D4DSP0.LD4_MULT36
TCELL2:IMUX_D6DSP0.LD6_MULT36
TCELL2:IMUX_CLK0DSP0.ACCUMSLOAD1
TCELL2:IMUX_LSR0DSP0.RST0
TCELL2:IMUX_CE0DSP0.CE0
TCELL2:OUT_F0DSP0.MUP130
TCELL2:OUT_F1DSP0.MUP131
TCELL2:OUT_F2DSP0.MUP132
TCELL2:OUT_F3DSP0.MUP133
TCELL2:OUT_F4DSP0.MUP134
TCELL2:OUT_F5DSP0.MUP135
TCELL2:OUT_F6DSP0.MUP08
TCELL2:OUT_F7DSP0.MUP09
TCELL2:OUT_Q0DSP0.MUP112
TCELL2:OUT_Q1DSP0.MUP113
TCELL2:OUT_Q2DSP0.MUP114
TCELL2:OUT_Q3DSP0.MUP115
TCELL2:OUT_Q4DSP0.MUP116
TCELL2:OUT_Q5DSP0.MUP117
TCELL2:OUT_Q6DSP0.MUP010
TCELL2:OUT_Q7DSP0.MUP011
TCELL3:IMUX_A0DSP0.MUA15
TCELL3:IMUX_A1DSP0.LD8_MULT36
TCELL3:IMUX_A2DSP0.MUB15
TCELL3:IMUX_A3DSP0.MUA20
TCELL3:IMUX_A4DSP0.MUA21
TCELL3:IMUX_A5DSP0.MUA23
TCELL3:IMUX_B0DSP0.MUA11
TCELL3:IMUX_B1DSP0.MUA13
TCELL3:IMUX_B2DSP0.MUB11
TCELL3:IMUX_B3DSP0.MUB13
TCELL3:IMUX_B4DSP0.MUA22
TCELL3:IMUX_B5DSP0.MUA25
TCELL3:IMUX_C0DSP0.MUA14
TCELL3:IMUX_C2DSP0.MUB14
TCELL3:IMUX_C4DSP0.MUB10
TCELL3:IMUX_C6DSP0.MUB12
TCELL3:IMUX_D0DSP0.MUA10
TCELL3:IMUX_D2DSP0.MUA12
TCELL3:IMUX_D4DSP0.MUA24
TCELL3:IMUX_D6DSP0.LD9_MULT36
TCELL3:IMUX_CLK0DSP0.CLK1
TCELL3:IMUX_CLK1DSP0.CLK0
TCELL3:IMUX_LSR0DSP0.RST1
TCELL3:IMUX_CE0DSP0.CE1
TCELL3:OUT_F0DSP0.MUP018
TCELL3:OUT_F1DSP0.MUP019
TCELL3:OUT_F2DSP0.MUP020
TCELL3:OUT_F3DSP0.MUP021
TCELL3:OUT_F4DSP0.MUP022
TCELL3:OUT_F5DSP0.MUP023
TCELL3:OUT_F6DSP0.MUP012
TCELL3:OUT_F7DSP0.MUP013
TCELL3:OUT_Q0DSP0.MUP218
TCELL3:OUT_Q1DSP0.MUP219
TCELL3:OUT_Q2DSP0.MUP220
TCELL3:OUT_Q3DSP0.MUP221
TCELL3:OUT_Q4DSP0.MUP222
TCELL3:OUT_Q5DSP0.MUP223
TCELL3:OUT_Q6DSP0.MUP014
TCELL3:OUT_Q7DSP0.MUP015
TCELL4:IMUX_A0DSP0.MUA111
TCELL4:IMUX_A1DSP0.LD10_MULT36
TCELL4:IMUX_A2DSP0.MUB111
TCELL4:IMUX_A3DSP0.MUA26
TCELL4:IMUX_A4DSP0.MUA27
TCELL4:IMUX_A5DSP0.MUA29
TCELL4:IMUX_B0DSP0.MUA17
TCELL4:IMUX_B1DSP0.MUA19
TCELL4:IMUX_B2DSP0.MUB17
TCELL4:IMUX_B3DSP0.MUB19
TCELL4:IMUX_B4DSP0.MUA28
TCELL4:IMUX_B5DSP0.MUA211
TCELL4:IMUX_C0DSP0.MUA110
TCELL4:IMUX_C2DSP0.MUB110
TCELL4:IMUX_C4DSP0.MUB16
TCELL4:IMUX_C6DSP0.MUB18
TCELL4:IMUX_D0DSP0.MUA16
TCELL4:IMUX_D2DSP0.MUA18
TCELL4:IMUX_D4DSP0.MUA210
TCELL4:IMUX_D6DSP0.LD11_MULT36
TCELL4:IMUX_CLK0DSP0.CLK2
TCELL4:IMUX_CLK1DSP0.CLK3
TCELL4:IMUX_LSR0DSP0.RST2
TCELL4:IMUX_CE0DSP0.CE2
TCELL4:OUT_F0DSP0.MUP024
TCELL4:OUT_F1DSP0.MUP025
TCELL4:OUT_F2DSP0.MUP026
TCELL4:OUT_F3DSP0.MUP027
TCELL4:OUT_F4DSP0.MUP028
TCELL4:OUT_F5DSP0.MUP029
TCELL4:OUT_F6DSP0.MUP016
TCELL4:OUT_F7DSP0.MUP017
TCELL4:OUT_Q0DSP0.MUP224
TCELL4:OUT_Q1DSP0.MUP225
TCELL4:OUT_Q2DSP0.MUP226
TCELL4:OUT_Q3DSP0.MUP227
TCELL4:OUT_Q4DSP0.MUP228
TCELL4:OUT_Q5DSP0.MUP229
TCELL4:OUT_Q6DSP0.MUP20
TCELL4:OUT_Q7DSP0.MUP21
TCELL5:IMUX_A0DSP0.MUA117
TCELL5:IMUX_A1DSP0.LD12_MULT36
TCELL5:IMUX_A2DSP0.MUB117
TCELL5:IMUX_A3DSP0.MUA212
TCELL5:IMUX_A4DSP0.MUA213
TCELL5:IMUX_A5DSP0.MUA215
TCELL5:IMUX_B0DSP0.MUA113
TCELL5:IMUX_B1DSP0.MUA115
TCELL5:IMUX_B2DSP0.MUB113
TCELL5:IMUX_B3DSP0.MUB115
TCELL5:IMUX_B4DSP0.MUA214
TCELL5:IMUX_B5DSP0.MUA217
TCELL5:IMUX_C0DSP0.MUA116
TCELL5:IMUX_C2DSP0.MUB116
TCELL5:IMUX_C4DSP0.MUB112
TCELL5:IMUX_C6DSP0.MUB114
TCELL5:IMUX_D0DSP0.MUA112
TCELL5:IMUX_D2DSP0.MUA114
TCELL5:IMUX_D4DSP0.MUA216
TCELL5:IMUX_D6DSP0.LD13_MULT36
TCELL5:IMUX_CLK1DSP0.ACCUMSLOAD3
TCELL5:IMUX_LSR0DSP0.RST3
TCELL5:IMUX_CE0DSP0.CE3
TCELL5:OUT_F0DSP0.MUP030
TCELL5:OUT_F1DSP0.MUP031
TCELL5:OUT_F2DSP0.MUP032
TCELL5:OUT_F3DSP0.MUP033
TCELL5:OUT_F4DSP0.MUP034
TCELL5:OUT_F5DSP0.MUP035
TCELL5:OUT_F6DSP0.MUP22
TCELL5:OUT_F7DSP0.MUP23
TCELL5:OUT_Q0DSP0.MUP230
TCELL5:OUT_Q1DSP0.MUP231
TCELL5:OUT_Q2DSP0.MUP232
TCELL5:OUT_Q3DSP0.MUP233
TCELL5:OUT_Q4DSP0.MUP234
TCELL5:OUT_Q5DSP0.MUP235
TCELL5:OUT_Q6DSP0.MUP24
TCELL5:OUT_Q7DSP0.MUP25
TCELL6:IMUX_A0DSP0.MUB25
TCELL6:IMUX_A1DSP0.LD14_MULT36
TCELL6:IMUX_A2DSP0.MUB35
TCELL6:IMUX_A3DSP0.MUA30
TCELL6:IMUX_A4DSP0.MUA31
TCELL6:IMUX_A5DSP0.MUA33
TCELL6:IMUX_B0DSP0.MUB21
TCELL6:IMUX_B1DSP0.MUB23
TCELL6:IMUX_B2DSP0.MUB31
TCELL6:IMUX_B3DSP0.MUB33
TCELL6:IMUX_B4DSP0.MUA32
TCELL6:IMUX_B5DSP0.MUA35
TCELL6:IMUX_C0DSP0.MUB24
TCELL6:IMUX_C2DSP0.MUB34
TCELL6:IMUX_C4DSP0.MUB30
TCELL6:IMUX_C6DSP0.MUB32
TCELL6:IMUX_D0DSP0.MUB20
TCELL6:IMUX_D2DSP0.MUB22
TCELL6:IMUX_D4DSP0.MUA34
TCELL6:IMUX_D6DSP0.LD15_MULT36
TCELL6:IMUX_CLK0DSP0.SOURCEB2
TCELL6:IMUX_CLK1DSP0.SOURCEA1
TCELL6:IMUX_LSR0DSP0.SIGNEDA2
TCELL6:IMUX_LSR1DSP0.SIGNEDB1
TCELL6:OUT_F0DSP0.MUP318, DSP0.SROB0
TCELL6:OUT_F1DSP0.MUP319, DSP0.SROB1
TCELL6:OUT_F2DSP0.MUP320, DSP0.SROB2
TCELL6:OUT_F3DSP0.MUP321, DSP0.SROB3
TCELL6:OUT_F4DSP0.MUP322, DSP0.SROB4
TCELL6:OUT_F5DSP0.MUP323, DSP0.SROB5
TCELL6:OUT_F6DSP0.MUP26
TCELL6:OUT_F7DSP0.MUP27
TCELL6:OUT_Q0DSP0.MUP30, DSP0.SROA0
TCELL6:OUT_Q1DSP0.MUP31, DSP0.SROA1
TCELL6:OUT_Q2DSP0.MUP32, DSP0.SROA2
TCELL6:OUT_Q3DSP0.MUP33, DSP0.SROA3
TCELL6:OUT_Q4DSP0.MUP34, DSP0.SROA4
TCELL6:OUT_Q5DSP0.MUP35, DSP0.SROA5
TCELL6:OUT_Q6DSP0.MUP28
TCELL6:OUT_Q7DSP0.MUP29
TCELL7:IMUX_A0DSP0.MUB211
TCELL7:IMUX_A2DSP0.MUB311
TCELL7:IMUX_A3DSP0.MUA36
TCELL7:IMUX_A4DSP0.MUA37
TCELL7:IMUX_A5DSP0.MUA39
TCELL7:IMUX_B0DSP0.MUB27
TCELL7:IMUX_B1DSP0.MUB29
TCELL7:IMUX_B2DSP0.MUB37
TCELL7:IMUX_B3DSP0.MUB39
TCELL7:IMUX_B4DSP0.MUA38
TCELL7:IMUX_B5DSP0.MUA311
TCELL7:IMUX_C0DSP0.MUB210
TCELL7:IMUX_C2DSP0.MUB310
TCELL7:IMUX_C4DSP0.MUB36
TCELL7:IMUX_C6DSP0.MUB38
TCELL7:IMUX_D0DSP0.MUB26
TCELL7:IMUX_D2DSP0.MUB28
TCELL7:IMUX_D4DSP0.MUA310
TCELL7:IMUX_CLK0DSP0.SOURCEA2
TCELL7:IMUX_CLK1DSP0.ADDNSUB3
TCELL7:IMUX_LSR1DSP0.SIGNEDB2
TCELL7:OUT_F0DSP0.MUP324, DSP0.SROB6
TCELL7:OUT_F1DSP0.MUP325, DSP0.SROB7
TCELL7:OUT_F2DSP0.MUP326, DSP0.SROB8
TCELL7:OUT_F3DSP0.MUP327, DSP0.SROB9
TCELL7:OUT_F4DSP0.MUP328, DSP0.SROB10
TCELL7:OUT_F5DSP0.MUP329, DSP0.SROB11
TCELL7:OUT_F6DSP0.MUP210
TCELL7:OUT_F7DSP0.MUP211
TCELL7:OUT_Q0DSP0.MUP36, DSP0.SROA6
TCELL7:OUT_Q1DSP0.MUP37, DSP0.SROA7
TCELL7:OUT_Q2DSP0.MUP38, DSP0.SROA8
TCELL7:OUT_Q3DSP0.MUP39, DSP0.SROA9
TCELL7:OUT_Q4DSP0.MUP310, DSP0.SROA10
TCELL7:OUT_Q5DSP0.MUP311, DSP0.SROA11
TCELL7:OUT_Q6DSP0.MUP212
TCELL7:OUT_Q7DSP0.MUP213
TCELL8:IMUX_A0DSP0.MUB217
TCELL8:IMUX_A2DSP0.MUB317
TCELL8:IMUX_A3DSP0.MUA312
TCELL8:IMUX_A4DSP0.MUA313
TCELL8:IMUX_A5DSP0.MUA315
TCELL8:IMUX_B0DSP0.MUB213
TCELL8:IMUX_B1DSP0.MUB215
TCELL8:IMUX_B2DSP0.MUB313
TCELL8:IMUX_B3DSP0.MUB315
TCELL8:IMUX_B4DSP0.MUA314
TCELL8:IMUX_B5DSP0.MUA317
TCELL8:IMUX_C0DSP0.MUB216
TCELL8:IMUX_C2DSP0.MUB316
TCELL8:IMUX_C4DSP0.MUB312
TCELL8:IMUX_C6DSP0.MUB314
TCELL8:IMUX_D0DSP0.MUB212
TCELL8:IMUX_D2DSP0.MUB214
TCELL8:IMUX_D4DSP0.MUA316
TCELL8:IMUX_CLK0DSP0.SOURCEB3
TCELL8:IMUX_CLK1DSP0.SOURCEA3
TCELL8:IMUX_LSR0DSP0.SIGNEDA3
TCELL8:IMUX_LSR1DSP0.SIGNEDB3
TCELL8:OUT_F0DSP0.MUP330, DSP0.SROB12
TCELL8:OUT_F1DSP0.MUP331, DSP0.SROB13
TCELL8:OUT_F2DSP0.MUP332, DSP0.SROB14
TCELL8:OUT_F3DSP0.MUP333, DSP0.SROB15
TCELL8:OUT_F4DSP0.MUP334, DSP0.SROB16
TCELL8:OUT_F5DSP0.MUP335, DSP0.SROB17
TCELL8:OUT_F6DSP0.MUP214
TCELL8:OUT_F7DSP0.MUP215
TCELL8:OUT_Q0DSP0.MUP312, DSP0.SROA12
TCELL8:OUT_Q1DSP0.MUP313, DSP0.SROA13
TCELL8:OUT_Q2DSP0.MUP314, DSP0.SROA14
TCELL8:OUT_Q3DSP0.MUP315, DSP0.SROA15
TCELL8:OUT_Q4DSP0.MUP316, DSP0.SROA16
TCELL8:OUT_Q5DSP0.MUP317, DSP0.SROA17
TCELL8:OUT_Q6DSP0.MUP216
TCELL8:OUT_Q7DSP0.MUP217