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Block RAM

Tile EBR

Cells: 3

Bel EBR0

ecp2 EBR bel EBR0
PinDirectionWires
ADA0inputTCELL0:IMUX_D0
ADA1inputTCELL0:IMUX_B0
ADA10inputTCELL2:IMUX_D0
ADA11inputTCELL2:IMUX_B0
ADA12inputTCELL2:IMUX_C0
ADA13inputTCELL2:IMUX_A0
ADA2inputTCELL2:IMUX_D4
ADA3inputTCELL2:IMUX_B4
ADA4inputTCELL0:IMUX_C0
ADA5inputTCELL0:IMUX_A0
ADA6inputTCELL1:IMUX_D0
ADA7inputTCELL1:IMUX_B0
ADA8inputTCELL1:IMUX_C0
ADA9inputTCELL1:IMUX_A0
ADB0inputTCELL0:IMUX_D2
ADB1inputTCELL0:IMUX_B2
ADB10inputTCELL2:IMUX_D2
ADB11inputTCELL2:IMUX_B2
ADB12inputTCELL2:IMUX_C2
ADB13inputTCELL2:IMUX_A2
ADB2inputTCELL2:IMUX_D6
ADB3inputTCELL2:IMUX_B5
ADB3WinputTCELL1:IMUX_LSR1
ADB4inputTCELL0:IMUX_C2
ADB5inputTCELL0:IMUX_A2
ADB6inputTCELL1:IMUX_D2
ADB7inputTCELL1:IMUX_B2
ADB8inputTCELL1:IMUX_C2
ADB9inputTCELL1:IMUX_A2
BHENABLEinputTCELL1:IMUX_CE0
BLENABLEinputTCELL0:IMUX_CE2
CEAinputTCELL2:IMUX_CE0
CEBinputTCELL0:IMUX_CE0
CLKAinputTCELL1:IMUX_CLK1
CLKBinputTCELL1:IMUX_CLK0
CSA0inputTCELL0:IMUX_LSR0
CSA1inputTCELL1:IMUX_LSR0
CSA2inputTCELL2:IMUX_LSR0
CSB0inputTCELL0:IMUX_LSR2
CSB1inputTCELL1:IMUX_LSR2
CSB2inputTCELL2:IMUX_LSR2
DIA0inputTCELL0:IMUX_C4
DIA1inputTCELL0:IMUX_A4
DIA10inputTCELL1:IMUX_D4
DIA11inputTCELL1:IMUX_B4
DIA12inputTCELL2:IMUX_C4
DIA13inputTCELL2:IMUX_A4
DIA14inputTCELL2:IMUX_A1
DIA15inputTCELL2:IMUX_B1
DIA16inputTCELL2:IMUX_D4
DIA17inputTCELL2:IMUX_B4
DIA2inputTCELL0:IMUX_A1
DIA3inputTCELL0:IMUX_B1
DIA4inputTCELL0:IMUX_D4
DIA5inputTCELL0:IMUX_B4
DIA6inputTCELL1:IMUX_C4
DIA7inputTCELL1:IMUX_A4
DIA8inputTCELL1:IMUX_A1
DIA9inputTCELL1:IMUX_B1
DIB0inputTCELL0:IMUX_C6
DIB1inputTCELL0:IMUX_B3
DIB10inputTCELL1:IMUX_D6
DIB11inputTCELL1:IMUX_B5
DIB12inputTCELL2:IMUX_C6
DIB13inputTCELL2:IMUX_B3
DIB14inputTCELL2:IMUX_A3
DIB15inputTCELL2:IMUX_A5
DIB16inputTCELL2:IMUX_D6
DIB17inputTCELL2:IMUX_B5
DIB2inputTCELL0:IMUX_A3
DIB3inputTCELL0:IMUX_A5
DIB4inputTCELL0:IMUX_D6
DIB5inputTCELL0:IMUX_B5
DIB6inputTCELL1:IMUX_C6
DIB7inputTCELL1:IMUX_B3
DIB8inputTCELL1:IMUX_A3
DIB9inputTCELL1:IMUX_A5
DOA0outputTCELL0:OUT_F0
DOA1outputTCELL0:OUT_F1
DOA10outputTCELL1:OUT_F4
DOA11outputTCELL1:OUT_F5
DOA12outputTCELL2:OUT_F0
DOA13outputTCELL2:OUT_F1
DOA14outputTCELL2:OUT_F2
DOA15outputTCELL2:OUT_F3
DOA16outputTCELL2:OUT_F4
DOA17outputTCELL2:OUT_F5
DOA2outputTCELL0:OUT_F2
DOA3outputTCELL0:OUT_F3
DOA4outputTCELL0:OUT_F4
DOA5outputTCELL0:OUT_F5
DOA6outputTCELL1:OUT_F0
DOA7outputTCELL1:OUT_F1
DOA8outputTCELL1:OUT_F2
DOA9outputTCELL1:OUT_F3
DOB0outputTCELL0:OUT_Q0
DOB1outputTCELL0:OUT_Q1
DOB10outputTCELL1:OUT_Q4
DOB11outputTCELL1:OUT_Q5
DOB12outputTCELL2:OUT_Q0
DOB13outputTCELL2:OUT_Q1
DOB14outputTCELL2:OUT_Q2
DOB15outputTCELL2:OUT_Q3
DOB16outputTCELL2:OUT_Q4
DOB17outputTCELL2:OUT_Q5
DOB2outputTCELL0:OUT_Q2
DOB3outputTCELL0:OUT_Q3
DOB4outputTCELL0:OUT_Q4
DOB5outputTCELL0:OUT_Q5
DOB6outputTCELL1:OUT_Q0
DOB7outputTCELL1:OUT_Q1
DOB8outputTCELL1:OUT_Q2
DOB9outputTCELL1:OUT_Q3
MORCLKAinputTCELL0:IMUX_CLK1
MORCLKBinputTCELL0:IMUX_CLK0
RSTAinputTCELL2:IMUX_LSR1
RSTBinputTCELL0:IMUX_LSR1
WEAinputTCELL1:IMUX_CE2
WEBinputTCELL2:IMUX_CE2

Bel wires

ecp2 EBR bel wires
WirePins
TCELL0:IMUX_A0EBR0.ADA5
TCELL0:IMUX_A1EBR0.DIA2
TCELL0:IMUX_A2EBR0.ADB5
TCELL0:IMUX_A3EBR0.DIB2
TCELL0:IMUX_A4EBR0.DIA1
TCELL0:IMUX_A5EBR0.DIB3
TCELL0:IMUX_B0EBR0.ADA1
TCELL0:IMUX_B1EBR0.DIA3
TCELL0:IMUX_B2EBR0.ADB1
TCELL0:IMUX_B3EBR0.DIB1
TCELL0:IMUX_B4EBR0.DIA5
TCELL0:IMUX_B5EBR0.DIB5
TCELL0:IMUX_C0EBR0.ADA4
TCELL0:IMUX_C2EBR0.ADB4
TCELL0:IMUX_C4EBR0.DIA0
TCELL0:IMUX_C6EBR0.DIB0
TCELL0:IMUX_D0EBR0.ADA0
TCELL0:IMUX_D2EBR0.ADB0
TCELL0:IMUX_D4EBR0.DIA4
TCELL0:IMUX_D6EBR0.DIB4
TCELL0:IMUX_CLK0EBR0.MORCLKB
TCELL0:IMUX_CLK1EBR0.MORCLKA
TCELL0:IMUX_LSR0EBR0.CSA0
TCELL0:IMUX_LSR1EBR0.RSTB
TCELL0:IMUX_LSR2EBR0.CSB0
TCELL0:IMUX_CE0EBR0.CEB
TCELL0:IMUX_CE2EBR0.BLENABLE
TCELL0:OUT_F0EBR0.DOA0
TCELL0:OUT_F1EBR0.DOA1
TCELL0:OUT_F2EBR0.DOA2
TCELL0:OUT_F3EBR0.DOA3
TCELL0:OUT_F4EBR0.DOA4
TCELL0:OUT_F5EBR0.DOA5
TCELL0:OUT_Q0EBR0.DOB0
TCELL0:OUT_Q1EBR0.DOB1
TCELL0:OUT_Q2EBR0.DOB2
TCELL0:OUT_Q3EBR0.DOB3
TCELL0:OUT_Q4EBR0.DOB4
TCELL0:OUT_Q5EBR0.DOB5
TCELL1:IMUX_A0EBR0.ADA9
TCELL1:IMUX_A1EBR0.DIA8
TCELL1:IMUX_A2EBR0.ADB9
TCELL1:IMUX_A3EBR0.DIB8
TCELL1:IMUX_A4EBR0.DIA7
TCELL1:IMUX_A5EBR0.DIB9
TCELL1:IMUX_B0EBR0.ADA7
TCELL1:IMUX_B1EBR0.DIA9
TCELL1:IMUX_B2EBR0.ADB7
TCELL1:IMUX_B3EBR0.DIB7
TCELL1:IMUX_B4EBR0.DIA11
TCELL1:IMUX_B5EBR0.DIB11
TCELL1:IMUX_C0EBR0.ADA8
TCELL1:IMUX_C2EBR0.ADB8
TCELL1:IMUX_C4EBR0.DIA6
TCELL1:IMUX_C6EBR0.DIB6
TCELL1:IMUX_D0EBR0.ADA6
TCELL1:IMUX_D2EBR0.ADB6
TCELL1:IMUX_D4EBR0.DIA10
TCELL1:IMUX_D6EBR0.DIB10
TCELL1:IMUX_CLK0EBR0.CLKB
TCELL1:IMUX_CLK1EBR0.CLKA
TCELL1:IMUX_LSR0EBR0.CSA1
TCELL1:IMUX_LSR1EBR0.ADB3W
TCELL1:IMUX_LSR2EBR0.CSB1
TCELL1:IMUX_CE0EBR0.BHENABLE
TCELL1:IMUX_CE2EBR0.WEA
TCELL1:OUT_F0EBR0.DOA6
TCELL1:OUT_F1EBR0.DOA7
TCELL1:OUT_F2EBR0.DOA8
TCELL1:OUT_F3EBR0.DOA9
TCELL1:OUT_F4EBR0.DOA10
TCELL1:OUT_F5EBR0.DOA11
TCELL1:OUT_Q0EBR0.DOB6
TCELL1:OUT_Q1EBR0.DOB7
TCELL1:OUT_Q2EBR0.DOB8
TCELL1:OUT_Q3EBR0.DOB9
TCELL1:OUT_Q4EBR0.DOB10
TCELL1:OUT_Q5EBR0.DOB11
TCELL2:IMUX_A0EBR0.ADA13
TCELL2:IMUX_A1EBR0.DIA14
TCELL2:IMUX_A2EBR0.ADB13
TCELL2:IMUX_A3EBR0.DIB14
TCELL2:IMUX_A4EBR0.DIA13
TCELL2:IMUX_A5EBR0.DIB15
TCELL2:IMUX_B0EBR0.ADA11
TCELL2:IMUX_B1EBR0.DIA15
TCELL2:IMUX_B2EBR0.ADB11
TCELL2:IMUX_B3EBR0.DIB13
TCELL2:IMUX_B4EBR0.ADA3, EBR0.DIA17
TCELL2:IMUX_B5EBR0.ADB3, EBR0.DIB17
TCELL2:IMUX_C0EBR0.ADA12
TCELL2:IMUX_C2EBR0.ADB12
TCELL2:IMUX_C4EBR0.DIA12
TCELL2:IMUX_C6EBR0.DIB12
TCELL2:IMUX_D0EBR0.ADA10
TCELL2:IMUX_D2EBR0.ADB10
TCELL2:IMUX_D4EBR0.ADA2, EBR0.DIA16
TCELL2:IMUX_D6EBR0.ADB2, EBR0.DIB16
TCELL2:IMUX_LSR0EBR0.CSA2
TCELL2:IMUX_LSR1EBR0.RSTA
TCELL2:IMUX_LSR2EBR0.CSB2
TCELL2:IMUX_CE0EBR0.CEA
TCELL2:IMUX_CE2EBR0.WEB
TCELL2:OUT_F0EBR0.DOA12
TCELL2:OUT_F1EBR0.DOA13
TCELL2:OUT_F2EBR0.DOA14
TCELL2:OUT_F3EBR0.DOA15
TCELL2:OUT_F4EBR0.DOA16
TCELL2:OUT_F5EBR0.DOA17
TCELL2:OUT_Q0EBR0.DOB12
TCELL2:OUT_Q1EBR0.DOB13
TCELL2:OUT_Q2EBR0.DOB14
TCELL2:OUT_Q3EBR0.DOB15
TCELL2:OUT_Q4EBR0.DOB16
TCELL2:OUT_Q5EBR0.DOB17