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SERDES

Tile SERDES_S

Cells: 27

Bel SERDES

ecp2m SERDES_S bel SERDES
PinDirectionWires
CIN0inputCELL12.IMUX_B1
CIN1inputCELL12.IMUX_A2
CIN10inputCELL11.IMUX_A1
CIN11inputCELL11.IMUX_A0
CIN2inputCELL12.IMUX_A1
CIN3inputCELL12.IMUX_A0
CIN4inputCELL11.IMUX_B0
CIN5inputCELL11.IMUX_A5
CIN6inputCELL11.IMUX_A4
CIN7inputCELL11.IMUX_A3
CIN8inputCELL11.IMUX_B1
CIN9inputCELL11.IMUX_A2
COUT0outputCELL15.OUT_F0
COUT1outputCELL14.OUT_F1
COUT10outputCELL13.OUT_F5
COUT11outputCELL13.OUT_F4
COUT12outputCELL13.OUT_F3
COUT13outputCELL13.OUT_F2
COUT14outputCELL13.OUT_F7
COUT15outputCELL13.OUT_F6
COUT16outputCELL13.OUT_F0
COUT17outputCELL12.OUT_F1
COUT18outputCELL12.OUT_F5
COUT19outputCELL12.OUT_F4
COUT2outputCELL14.OUT_F5
COUT3outputCELL14.OUT_F4
COUT4outputCELL14.OUT_F3
COUT5outputCELL14.OUT_F2
COUT6outputCELL14.OUT_F7
COUT7outputCELL14.OUT_F6
COUT8outputCELL14.OUT_F0
COUT9outputCELL13.OUT_F1
CYAWSTNinputCELL14.IMUX_A5
FFC_CK_CORE_RXinputCELL14.IMUX_CLK0
FFC_CK_CORE_TXinputCELL15.IMUX_CLK0
FFC_EI_EN_0inputCELL25.IMUX_A0
FFC_EI_EN_1inputCELL17.IMUX_B0
FFC_EI_EN_2inputCELL9.IMUX_A0
FFC_EI_EN_3inputCELL1.IMUX_B0
FFC_ENABLE_CGALIGN_0inputCELL25.IMUX_A1
FFC_ENABLE_CGALIGN_1inputCELL17.IMUX_A5
FFC_ENABLE_CGALIGN_2inputCELL9.IMUX_A1
FFC_ENABLE_CGALIGN_3inputCELL1.IMUX_A5
FFC_FB_LOOPBACK_0inputCELL25.IMUX_A2
FFC_FB_LOOPBACK_1inputCELL17.IMUX_A4
FFC_FB_LOOPBACK_2inputCELL9.IMUX_A2
FFC_FB_LOOPBACK_3inputCELL1.IMUX_A4
FFC_LANE_RX_RST_0inputCELL26.IMUX_LSR0
FFC_LANE_RX_RST_1inputCELL16.IMUX_LSR0
FFC_LANE_RX_RST_2inputCELL10.IMUX_LSR0
FFC_LANE_RX_RST_3inputCELL0.IMUX_LSR0
FFC_LANE_TX_RST_0inputCELL22.IMUX_LSR0
FFC_LANE_TX_RST_1inputCELL17.IMUX_LSR0
FFC_LANE_TX_RST_2inputCELL6.IMUX_LSR0
FFC_LANE_TX_RST_3inputCELL1.IMUX_LSR0
FFC_MACRO_RSTinputCELL13.IMUX_LSR0
FFC_PCIE_CT_0inputCELL25.IMUX_B0
FFC_PCIE_CT_1inputCELL17.IMUX_A0
FFC_PCIE_CT_2inputCELL9.IMUX_B0
FFC_PCIE_CT_3inputCELL1.IMUX_A0
FFC_PCI_DET_EN_0inputCELL26.IMUX_A0
FFC_PCI_DET_EN_1inputCELL16.IMUX_B0
FFC_PCI_DET_EN_2inputCELL10.IMUX_A0
FFC_PCI_DET_EN_3inputCELL0.IMUX_B0
FFC_PFIFO_CLR_0inputCELL26.IMUX_A1
FFC_PFIFO_CLR_1inputCELL17.IMUX_A1
FFC_PFIFO_CLR_2inputCELL10.IMUX_A1
FFC_PFIFO_CLR_3inputCELL1.IMUX_A1
FFC_QUAD_RSTinputCELL14.IMUX_LSR0
FFC_RRST_0inputCELL19.IMUX_LSR0
FFC_RRST_1inputCELL18.IMUX_LSR0
FFC_RRST_2inputCELL9.IMUX_LSR0
FFC_RRST_3inputCELL8.IMUX_LSR0
FFC_RXPWDNB_0inputCELL26.IMUX_A3
FFC_RXPWDNB_1inputCELL16.IMUX_A1
FFC_RXPWDNB_2inputCELL10.IMUX_A3
FFC_RXPWDNB_3inputCELL0.IMUX_A1
FFC_SB_INV_RX_0inputCELL26.IMUX_A2
FFC_SB_INV_RX_1inputCELL16.IMUX_A4
FFC_SB_INV_RX_2inputCELL10.IMUX_A2
FFC_SB_INV_RX_3inputCELL0.IMUX_A4
FFC_SB_PFIFO_LP_0inputCELL25.IMUX_A5
FFC_SB_PFIFO_LP_1inputCELL16.IMUX_A5
FFC_SB_PFIFO_LP_2inputCELL9.IMUX_A5
FFC_SB_PFIFO_LP_3inputCELL0.IMUX_A5
FFC_SIGNAL_DETECT_0inputCELL25.IMUX_A4
FFC_SIGNAL_DETECT_1inputCELL17.IMUX_A2
FFC_SIGNAL_DETECT_2inputCELL9.IMUX_A4
FFC_SIGNAL_DETECT_3inputCELL1.IMUX_A2
FFC_TRSTinputCELL15.IMUX_LSR0
FFC_TXPWDNB_0inputCELL26.IMUX_B1
FFC_TXPWDNB_1inputCELL16.IMUX_A0
FFC_TXPWDNB_2inputCELL10.IMUX_B1
FFC_TXPWDNB_3inputCELL0.IMUX_A0
FFS_CC_OVERRUN_0outputCELL22.OUT_F5
FFS_CC_OVERRUN_1outputCELL20.OUT_F6
FFS_CC_OVERRUN_2outputCELL6.OUT_F1
FFS_CC_OVERRUN_3outputCELL4.OUT_F0
FFS_CC_UNDERRUN_0outputCELL22.OUT_F4
FFS_CC_UNDERRUN_1outputCELL20.OUT_F7
FFS_CC_UNDERRUN_2outputCELL6.OUT_F5
FFS_CC_UNDERRUN_3outputCELL4.OUT_F7
FFS_LS_SYNC_STATUS_0outputCELL22.OUT_F3
FFS_LS_SYNC_STATUS_1outputCELL20.OUT_F2
FFS_LS_SYNC_STATUS_2outputCELL6.OUT_F4
FFS_LS_SYNC_STATUS_3outputCELL4.OUT_F2
FFS_PCIE_CON_0outputCELL22.OUT_F2
FFS_PCIE_CON_1outputCELL20.OUT_F3
FFS_PCIE_CON_2outputCELL6.OUT_F3
FFS_PCIE_CON_3outputCELL4.OUT_F3
FFS_PCIE_DONE_0outputCELL22.OUT_F7
FFS_PCIE_DONE_1outputCELL20.OUT_F4
FFS_PCIE_DONE_2outputCELL6.OUT_F2
FFS_PCIE_DONE_3outputCELL4.OUT_F4
FFS_PLOLoutputCELL15.OUT_F7
FFS_RLOL_0outputCELL21.OUT_F7
FFS_RLOL_1outputCELL21.OUT_F3
FFS_RLOL_2outputCELL5.OUT_F3
FFS_RLOL_3outputCELL5.OUT_F6
FFS_RLOS_LO_0outputCELL22.OUT_F6
FFS_RLOS_LO_1outputCELL20.OUT_F5
FFS_RLOS_LO_2outputCELL6.OUT_F7
FFS_RLOS_LO_3outputCELL4.OUT_F5
FFS_RXFBFIFO_ERROR_0outputCELL21.OUT_F5
FFS_RXFBFIFO_ERROR_1outputCELL21.OUT_F2
FFS_RXFBFIFO_ERROR_2outputCELL5.OUT_F4
FFS_RXFBFIFO_ERROR_3outputCELL5.OUT_F0
FFS_TXFBFIFO_ERROR_0outputCELL21.OUT_F0
FFS_TXFBFIFO_ERROR_1outputCELL21.OUT_F4
FFS_TXFBFIFO_ERROR_2outputCELL5.OUT_F2
FFS_TXFBFIFO_ERROR_3outputCELL5.OUT_F7
FF_EBRD_CLK_0inputCELL24.IMUX_CLK0
FF_EBRD_CLK_1inputCELL16.IMUX_CLK0
FF_EBRD_CLK_2inputCELL8.IMUX_CLK0
FF_EBRD_CLK_3inputCELL0.IMUX_CLK0
FF_RXI_CLK_0inputCELL23.IMUX_CLK0
FF_RXI_CLK_1inputCELL17.IMUX_CLK0
FF_RXI_CLK_2inputCELL7.IMUX_CLK0
FF_RXI_CLK_3inputCELL1.IMUX_CLK0
FF_RX_D_0_0outputCELL23.OUT_F4
FF_RX_D_0_1outputCELL23.OUT_F5
FF_RX_D_0_10outputCELL25.OUT_F7
FF_RX_D_0_11outputCELL25.OUT_F2
FF_RX_D_0_12outputCELL25.OUT_F3
FF_RX_D_0_13outputCELL25.OUT_F4
FF_RX_D_0_14outputCELL25.OUT_F5
FF_RX_D_0_15outputCELL25.OUT_F1
FF_RX_D_0_16outputCELL26.OUT_F0
FF_RX_D_0_17outputCELL26.OUT_F6
FF_RX_D_0_18outputCELL26.OUT_F7
FF_RX_D_0_19outputCELL26.OUT_F2
FF_RX_D_0_2outputCELL23.OUT_F1
FF_RX_D_0_20outputCELL26.OUT_F3
FF_RX_D_0_21outputCELL26.OUT_F4
FF_RX_D_0_22outputCELL26.OUT_F5
FF_RX_D_0_23outputCELL26.OUT_F1
FF_RX_D_0_3outputCELL24.OUT_F2
FF_RX_D_0_4outputCELL24.OUT_F3
FF_RX_D_0_5outputCELL24.OUT_F4
FF_RX_D_0_6outputCELL24.OUT_F5
FF_RX_D_0_7outputCELL24.OUT_F1
FF_RX_D_0_8outputCELL25.OUT_F0
FF_RX_D_0_9outputCELL25.OUT_F6
FF_RX_D_1_0outputCELL20.OUT_F0
FF_RX_D_1_1outputCELL19.OUT_F1
FF_RX_D_1_10outputCELL18.OUT_F4
FF_RX_D_1_11outputCELL18.OUT_F3
FF_RX_D_1_12outputCELL18.OUT_F2
FF_RX_D_1_13outputCELL18.OUT_F7
FF_RX_D_1_14outputCELL18.OUT_F6
FF_RX_D_1_15outputCELL18.OUT_F0
FF_RX_D_1_16outputCELL16.OUT_F1
FF_RX_D_1_17outputCELL16.OUT_F5
FF_RX_D_1_18outputCELL16.OUT_F4
FF_RX_D_1_19outputCELL16.OUT_F3
FF_RX_D_1_2outputCELL19.OUT_F5
FF_RX_D_1_20outputCELL16.OUT_F2
FF_RX_D_1_21outputCELL16.OUT_F7
FF_RX_D_1_22outputCELL16.OUT_F6
FF_RX_D_1_23outputCELL16.OUT_F0
FF_RX_D_1_3outputCELL19.OUT_F4
FF_RX_D_1_4outputCELL19.OUT_F3
FF_RX_D_1_5outputCELL19.OUT_F2
FF_RX_D_1_6outputCELL19.OUT_F7
FF_RX_D_1_7outputCELL19.OUT_F0
FF_RX_D_1_8outputCELL18.OUT_F1
FF_RX_D_1_9outputCELL18.OUT_F5
FF_RX_D_2_0outputCELL8.OUT_F0
FF_RX_D_2_1outputCELL8.OUT_F6
FF_RX_D_2_10outputCELL9.OUT_F7
FF_RX_D_2_11outputCELL9.OUT_F2
FF_RX_D_2_12outputCELL9.OUT_F3
FF_RX_D_2_13outputCELL9.OUT_F4
FF_RX_D_2_14outputCELL9.OUT_F5
FF_RX_D_2_15outputCELL9.OUT_F1
FF_RX_D_2_16outputCELL10.OUT_F0
FF_RX_D_2_17outputCELL10.OUT_F6
FF_RX_D_2_18outputCELL10.OUT_F7
FF_RX_D_2_19outputCELL10.OUT_F2
FF_RX_D_2_2outputCELL8.OUT_F7
FF_RX_D_2_20outputCELL10.OUT_F3
FF_RX_D_2_21outputCELL10.OUT_F4
FF_RX_D_2_22outputCELL10.OUT_F5
FF_RX_D_2_23outputCELL10.OUT_F1
FF_RX_D_2_3outputCELL8.OUT_F2
FF_RX_D_2_4outputCELL8.OUT_F3
FF_RX_D_2_5outputCELL8.OUT_F4
FF_RX_D_2_6outputCELL8.OUT_F5
FF_RX_D_2_7outputCELL8.OUT_F1
FF_RX_D_2_8outputCELL9.OUT_F0
FF_RX_D_2_9outputCELL9.OUT_F6
FF_RX_D_3_0outputCELL3.OUT_F1
FF_RX_D_3_1outputCELL3.OUT_F5
FF_RX_D_3_10outputCELL1.OUT_F4
FF_RX_D_3_11outputCELL1.OUT_F3
FF_RX_D_3_12outputCELL1.OUT_F2
FF_RX_D_3_13outputCELL1.OUT_F7
FF_RX_D_3_14outputCELL1.OUT_F6
FF_RX_D_3_15outputCELL1.OUT_F0
FF_RX_D_3_16outputCELL0.OUT_F1
FF_RX_D_3_17outputCELL0.OUT_F5
FF_RX_D_3_18outputCELL0.OUT_F4
FF_RX_D_3_19outputCELL0.OUT_F3
FF_RX_D_3_2outputCELL3.OUT_F4
FF_RX_D_3_20outputCELL0.OUT_F2
FF_RX_D_3_21outputCELL0.OUT_F7
FF_RX_D_3_22outputCELL0.OUT_F6
FF_RX_D_3_23outputCELL0.OUT_F0
FF_RX_D_3_3outputCELL3.OUT_F3
FF_RX_D_3_4outputCELL3.OUT_F2
FF_RX_D_3_5outputCELL3.OUT_F7
FF_RX_D_3_6outputCELL3.OUT_F6
FF_RX_D_3_7outputCELL3.OUT_F0
FF_RX_D_3_8outputCELL1.OUT_F1
FF_RX_D_3_9outputCELL1.OUT_F5
FF_RX_F_CLK_0outputCELL24.OUT_F6
FF_RX_F_CLK_1outputCELL17.OUT_F6
FF_RX_F_CLK_2outputCELL7.OUT_F6
FF_RX_F_CLK_3outputCELL2.OUT_F6
FF_RX_H_CLK_0outputCELL24.OUT_F7
FF_RX_H_CLK_1outputCELL17.OUT_F7
FF_RX_H_CLK_2outputCELL7.OUT_F7
FF_RX_H_CLK_3outputCELL2.OUT_F7
FF_RX_Q_CLK_0outputCELL21.OUT_F6
FF_RX_Q_CLK_1outputCELL19.OUT_F6
FF_RX_Q_CLK_2outputCELL6.OUT_F6
FF_RX_Q_CLK_3outputCELL4.OUT_F6
FF_TXI_CLK_0inputCELL22.IMUX_CLK0
FF_TXI_CLK_1inputCELL18.IMUX_CLK0
FF_TXI_CLK_2inputCELL6.IMUX_CLK0
FF_TXI_CLK_3inputCELL2.IMUX_CLK0
FF_TX_D_0_0inputCELL22.IMUX_A0
FF_TX_D_0_1inputCELL22.IMUX_A1
FF_TX_D_0_10inputCELL23.IMUX_A2
FF_TX_D_0_11inputCELL23.IMUX_B1
FF_TX_D_0_12inputCELL23.IMUX_A3
FF_TX_D_0_13inputCELL23.IMUX_A4
FF_TX_D_0_14inputCELL23.IMUX_A5
FF_TX_D_0_15inputCELL23.IMUX_B0
FF_TX_D_0_16inputCELL24.IMUX_A0
FF_TX_D_0_17inputCELL24.IMUX_A1
FF_TX_D_0_18inputCELL24.IMUX_A2
FF_TX_D_0_19inputCELL24.IMUX_B1
FF_TX_D_0_2inputCELL22.IMUX_A2
FF_TX_D_0_20inputCELL24.IMUX_A3
FF_TX_D_0_21inputCELL24.IMUX_A4
FF_TX_D_0_22inputCELL24.IMUX_A5
FF_TX_D_0_23inputCELL24.IMUX_B0
FF_TX_D_0_3inputCELL22.IMUX_B1
FF_TX_D_0_4inputCELL22.IMUX_A3
FF_TX_D_0_5inputCELL22.IMUX_A4
FF_TX_D_0_6inputCELL22.IMUX_A5
FF_TX_D_0_7inputCELL22.IMUX_B0
FF_TX_D_0_8inputCELL23.IMUX_A0
FF_TX_D_0_9inputCELL23.IMUX_A1
FF_TX_D_1_0inputCELL20.IMUX_B0
FF_TX_D_1_1inputCELL20.IMUX_A5
FF_TX_D_1_10inputCELL19.IMUX_A4
FF_TX_D_1_11inputCELL19.IMUX_A3
FF_TX_D_1_12inputCELL19.IMUX_B1
FF_TX_D_1_13inputCELL19.IMUX_A2
FF_TX_D_1_14inputCELL19.IMUX_A1
FF_TX_D_1_15inputCELL19.IMUX_A0
FF_TX_D_1_16inputCELL18.IMUX_B0
FF_TX_D_1_17inputCELL18.IMUX_A5
FF_TX_D_1_18inputCELL18.IMUX_A4
FF_TX_D_1_19inputCELL18.IMUX_A3
FF_TX_D_1_2inputCELL20.IMUX_A4
FF_TX_D_1_20inputCELL18.IMUX_B1
FF_TX_D_1_21inputCELL18.IMUX_A2
FF_TX_D_1_22inputCELL18.IMUX_A1
FF_TX_D_1_23inputCELL18.IMUX_A0
FF_TX_D_1_3inputCELL20.IMUX_A3
FF_TX_D_1_4inputCELL20.IMUX_B1
FF_TX_D_1_5inputCELL20.IMUX_A2
FF_TX_D_1_6inputCELL20.IMUX_A1
FF_TX_D_1_7inputCELL20.IMUX_A0
FF_TX_D_1_8inputCELL19.IMUX_B0
FF_TX_D_1_9inputCELL19.IMUX_A5
FF_TX_D_2_0inputCELL6.IMUX_A0
FF_TX_D_2_1inputCELL6.IMUX_A1
FF_TX_D_2_10inputCELL7.IMUX_A2
FF_TX_D_2_11inputCELL7.IMUX_B1
FF_TX_D_2_12inputCELL7.IMUX_A3
FF_TX_D_2_13inputCELL7.IMUX_A4
FF_TX_D_2_14inputCELL7.IMUX_A5
FF_TX_D_2_15inputCELL7.IMUX_B0
FF_TX_D_2_16inputCELL8.IMUX_A0
FF_TX_D_2_17inputCELL8.IMUX_A1
FF_TX_D_2_18inputCELL8.IMUX_A2
FF_TX_D_2_19inputCELL8.IMUX_B1
FF_TX_D_2_2inputCELL6.IMUX_A2
FF_TX_D_2_20inputCELL8.IMUX_A3
FF_TX_D_2_21inputCELL8.IMUX_A4
FF_TX_D_2_22inputCELL8.IMUX_A5
FF_TX_D_2_23inputCELL8.IMUX_B0
FF_TX_D_2_3inputCELL6.IMUX_B1
FF_TX_D_2_4inputCELL6.IMUX_A3
FF_TX_D_2_5inputCELL6.IMUX_A4
FF_TX_D_2_6inputCELL6.IMUX_A5
FF_TX_D_2_7inputCELL6.IMUX_B0
FF_TX_D_2_8inputCELL7.IMUX_A0
FF_TX_D_2_9inputCELL7.IMUX_A1
FF_TX_D_3_0inputCELL4.IMUX_B0
FF_TX_D_3_1inputCELL4.IMUX_A5
FF_TX_D_3_10inputCELL3.IMUX_A4
FF_TX_D_3_11inputCELL3.IMUX_A3
FF_TX_D_3_12inputCELL3.IMUX_B1
FF_TX_D_3_13inputCELL3.IMUX_A2
FF_TX_D_3_14inputCELL3.IMUX_A1
FF_TX_D_3_15inputCELL3.IMUX_A0
FF_TX_D_3_16inputCELL2.IMUX_B0
FF_TX_D_3_17inputCELL2.IMUX_A5
FF_TX_D_3_18inputCELL2.IMUX_A4
FF_TX_D_3_19inputCELL2.IMUX_A3
FF_TX_D_3_2inputCELL4.IMUX_A4
FF_TX_D_3_20inputCELL2.IMUX_B1
FF_TX_D_3_21inputCELL2.IMUX_A2
FF_TX_D_3_22inputCELL2.IMUX_A1
FF_TX_D_3_23inputCELL2.IMUX_A0
FF_TX_D_3_3inputCELL4.IMUX_A3
FF_TX_D_3_4inputCELL4.IMUX_B1
FF_TX_D_3_5inputCELL4.IMUX_A2
FF_TX_D_3_6inputCELL4.IMUX_A1
FF_TX_D_3_7inputCELL4.IMUX_A0
FF_TX_D_3_8inputCELL3.IMUX_B0
FF_TX_D_3_9inputCELL3.IMUX_A5
FF_TX_F_CLKoutputCELL12.OUT_F6
FF_TX_H_CLKoutputCELL12.OUT_F7
FF_TX_Q_CLKoutputCELL15.OUT_F6
OOB_OUT_0outputCELL22.OUT_F0
OOB_OUT_1outputCELL20.OUT_F1
OOB_OUT_2outputCELL6.OUT_F0
OOB_OUT_3outputCELL4.OUT_F1
REFCK2COREoutputCELL12.OUT_F3
SCIADDR0inputCELL13.IMUX_A1
SCIADDR1inputCELL13.IMUX_A0
SCIADDR2inputCELL12.IMUX_B0
SCIADDR3inputCELL12.IMUX_A5
SCIADDR4inputCELL12.IMUX_A4
SCIADDR5inputCELL12.IMUX_A3
SCIENAUXinputCELL13.IMUX_A2
SCIENCH0inputCELL25.IMUX_A3
SCIENCH1inputCELL17.IMUX_B1
SCIENCH2inputCELL9.IMUX_A3
SCIENCH3inputCELL1.IMUX_B1
SCIINToutputCELL11.OUT_F0
SCIRDinputCELL13.IMUX_B1
SCIRDATA0outputCELL12.OUT_F0
SCIRDATA1outputCELL11.OUT_F1
SCIRDATA2outputCELL11.OUT_F5
SCIRDATA3outputCELL11.OUT_F4
SCIRDATA4outputCELL11.OUT_F3
SCIRDATA5outputCELL11.OUT_F2
SCIRDATA6outputCELL11.OUT_F7
SCIRDATA7outputCELL11.OUT_F6
SCISELAUXinputCELL13.IMUX_A3
SCISELCH0inputCELL25.IMUX_B1
SCISELCH1inputCELL17.IMUX_A3
SCISELCH2inputCELL9.IMUX_B1
SCISELCH3inputCELL1.IMUX_A3
SCIWDATA0inputCELL14.IMUX_A4
SCIWDATA1inputCELL14.IMUX_A3
SCIWDATA2inputCELL14.IMUX_B1
SCIWDATA3inputCELL14.IMUX_A2
SCIWDATA4inputCELL14.IMUX_A1
SCIWDATA5inputCELL14.IMUX_A0
SCIWDATA6inputCELL13.IMUX_B0
SCIWDATA7inputCELL13.IMUX_A5
SCIWSTNinputCELL13.IMUX_A4

Bel wires

ecp2m SERDES_S bel wires
WirePins
CELL0.IMUX_A0SERDES.FFC_TXPWDNB_3
CELL0.IMUX_A1SERDES.FFC_RXPWDNB_3
CELL0.IMUX_A4SERDES.FFC_SB_INV_RX_3
CELL0.IMUX_A5SERDES.FFC_SB_PFIFO_LP_3
CELL0.IMUX_B0SERDES.FFC_PCI_DET_EN_3
CELL0.IMUX_CLK0SERDES.FF_EBRD_CLK_3
CELL0.IMUX_LSR0SERDES.FFC_LANE_RX_RST_3
CELL0.OUT_F0SERDES.FF_RX_D_3_23
CELL0.OUT_F1SERDES.FF_RX_D_3_16
CELL0.OUT_F2SERDES.FF_RX_D_3_20
CELL0.OUT_F3SERDES.FF_RX_D_3_19
CELL0.OUT_F4SERDES.FF_RX_D_3_18
CELL0.OUT_F5SERDES.FF_RX_D_3_17
CELL0.OUT_F6SERDES.FF_RX_D_3_22
CELL0.OUT_F7SERDES.FF_RX_D_3_21
CELL1.IMUX_A0SERDES.FFC_PCIE_CT_3
CELL1.IMUX_A1SERDES.FFC_PFIFO_CLR_3
CELL1.IMUX_A2SERDES.FFC_SIGNAL_DETECT_3
CELL1.IMUX_A3SERDES.SCISELCH3
CELL1.IMUX_A4SERDES.FFC_FB_LOOPBACK_3
CELL1.IMUX_A5SERDES.FFC_ENABLE_CGALIGN_3
CELL1.IMUX_B0SERDES.FFC_EI_EN_3
CELL1.IMUX_B1SERDES.SCIENCH3
CELL1.IMUX_CLK0SERDES.FF_RXI_CLK_3
CELL1.IMUX_LSR0SERDES.FFC_LANE_TX_RST_3
CELL1.OUT_F0SERDES.FF_RX_D_3_15
CELL1.OUT_F1SERDES.FF_RX_D_3_8
CELL1.OUT_F2SERDES.FF_RX_D_3_12
CELL1.OUT_F3SERDES.FF_RX_D_3_11
CELL1.OUT_F4SERDES.FF_RX_D_3_10
CELL1.OUT_F5SERDES.FF_RX_D_3_9
CELL1.OUT_F6SERDES.FF_RX_D_3_14
CELL1.OUT_F7SERDES.FF_RX_D_3_13
CELL2.IMUX_A0SERDES.FF_TX_D_3_23
CELL2.IMUX_A1SERDES.FF_TX_D_3_22
CELL2.IMUX_A2SERDES.FF_TX_D_3_21
CELL2.IMUX_A3SERDES.FF_TX_D_3_19
CELL2.IMUX_A4SERDES.FF_TX_D_3_18
CELL2.IMUX_A5SERDES.FF_TX_D_3_17
CELL2.IMUX_B0SERDES.FF_TX_D_3_16
CELL2.IMUX_B1SERDES.FF_TX_D_3_20
CELL2.IMUX_CLK0SERDES.FF_TXI_CLK_3
CELL2.OUT_F6SERDES.FF_RX_F_CLK_3
CELL2.OUT_F7SERDES.FF_RX_H_CLK_3
CELL3.IMUX_A0SERDES.FF_TX_D_3_15
CELL3.IMUX_A1SERDES.FF_TX_D_3_14
CELL3.IMUX_A2SERDES.FF_TX_D_3_13
CELL3.IMUX_A3SERDES.FF_TX_D_3_11
CELL3.IMUX_A4SERDES.FF_TX_D_3_10
CELL3.IMUX_A5SERDES.FF_TX_D_3_9
CELL3.IMUX_B0SERDES.FF_TX_D_3_8
CELL3.IMUX_B1SERDES.FF_TX_D_3_12
CELL3.OUT_F0SERDES.FF_RX_D_3_7
CELL3.OUT_F1SERDES.FF_RX_D_3_0
CELL3.OUT_F2SERDES.FF_RX_D_3_4
CELL3.OUT_F3SERDES.FF_RX_D_3_3
CELL3.OUT_F4SERDES.FF_RX_D_3_2
CELL3.OUT_F5SERDES.FF_RX_D_3_1
CELL3.OUT_F6SERDES.FF_RX_D_3_6
CELL3.OUT_F7SERDES.FF_RX_D_3_5
CELL4.IMUX_A0SERDES.FF_TX_D_3_7
CELL4.IMUX_A1SERDES.FF_TX_D_3_6
CELL4.IMUX_A2SERDES.FF_TX_D_3_5
CELL4.IMUX_A3SERDES.FF_TX_D_3_3
CELL4.IMUX_A4SERDES.FF_TX_D_3_2
CELL4.IMUX_A5SERDES.FF_TX_D_3_1
CELL4.IMUX_B0SERDES.FF_TX_D_3_0
CELL4.IMUX_B1SERDES.FF_TX_D_3_4
CELL4.OUT_F0SERDES.FFS_CC_OVERRUN_3
CELL4.OUT_F1SERDES.OOB_OUT_3
CELL4.OUT_F2SERDES.FFS_LS_SYNC_STATUS_3
CELL4.OUT_F3SERDES.FFS_PCIE_CON_3
CELL4.OUT_F4SERDES.FFS_PCIE_DONE_3
CELL4.OUT_F5SERDES.FFS_RLOS_LO_3
CELL4.OUT_F6SERDES.FF_RX_Q_CLK_3
CELL4.OUT_F7SERDES.FFS_CC_UNDERRUN_3
CELL5.OUT_F0SERDES.FFS_RXFBFIFO_ERROR_3
CELL5.OUT_F2SERDES.FFS_TXFBFIFO_ERROR_2
CELL5.OUT_F3SERDES.FFS_RLOL_2
CELL5.OUT_F4SERDES.FFS_RXFBFIFO_ERROR_2
CELL5.OUT_F6SERDES.FFS_RLOL_3
CELL5.OUT_F7SERDES.FFS_TXFBFIFO_ERROR_3
CELL6.IMUX_A0SERDES.FF_TX_D_2_0
CELL6.IMUX_A1SERDES.FF_TX_D_2_1
CELL6.IMUX_A2SERDES.FF_TX_D_2_2
CELL6.IMUX_A3SERDES.FF_TX_D_2_4
CELL6.IMUX_A4SERDES.FF_TX_D_2_5
CELL6.IMUX_A5SERDES.FF_TX_D_2_6
CELL6.IMUX_B0SERDES.FF_TX_D_2_7
CELL6.IMUX_B1SERDES.FF_TX_D_2_3
CELL6.IMUX_CLK0SERDES.FF_TXI_CLK_2
CELL6.IMUX_LSR0SERDES.FFC_LANE_TX_RST_2
CELL6.OUT_F0SERDES.OOB_OUT_2
CELL6.OUT_F1SERDES.FFS_CC_OVERRUN_2
CELL6.OUT_F2SERDES.FFS_PCIE_DONE_2
CELL6.OUT_F3SERDES.FFS_PCIE_CON_2
CELL6.OUT_F4SERDES.FFS_LS_SYNC_STATUS_2
CELL6.OUT_F5SERDES.FFS_CC_UNDERRUN_2
CELL6.OUT_F6SERDES.FF_RX_Q_CLK_2
CELL6.OUT_F7SERDES.FFS_RLOS_LO_2
CELL7.IMUX_A0SERDES.FF_TX_D_2_8
CELL7.IMUX_A1SERDES.FF_TX_D_2_9
CELL7.IMUX_A2SERDES.FF_TX_D_2_10
CELL7.IMUX_A3SERDES.FF_TX_D_2_12
CELL7.IMUX_A4SERDES.FF_TX_D_2_13
CELL7.IMUX_A5SERDES.FF_TX_D_2_14
CELL7.IMUX_B0SERDES.FF_TX_D_2_15
CELL7.IMUX_B1SERDES.FF_TX_D_2_11
CELL7.IMUX_CLK0SERDES.FF_RXI_CLK_2
CELL7.OUT_F6SERDES.FF_RX_F_CLK_2
CELL7.OUT_F7SERDES.FF_RX_H_CLK_2
CELL8.IMUX_A0SERDES.FF_TX_D_2_16
CELL8.IMUX_A1SERDES.FF_TX_D_2_17
CELL8.IMUX_A2SERDES.FF_TX_D_2_18
CELL8.IMUX_A3SERDES.FF_TX_D_2_20
CELL8.IMUX_A4SERDES.FF_TX_D_2_21
CELL8.IMUX_A5SERDES.FF_TX_D_2_22
CELL8.IMUX_B0SERDES.FF_TX_D_2_23
CELL8.IMUX_B1SERDES.FF_TX_D_2_19
CELL8.IMUX_CLK0SERDES.FF_EBRD_CLK_2
CELL8.IMUX_LSR0SERDES.FFC_RRST_3
CELL8.OUT_F0SERDES.FF_RX_D_2_0
CELL8.OUT_F1SERDES.FF_RX_D_2_7
CELL8.OUT_F2SERDES.FF_RX_D_2_3
CELL8.OUT_F3SERDES.FF_RX_D_2_4
CELL8.OUT_F4SERDES.FF_RX_D_2_5
CELL8.OUT_F5SERDES.FF_RX_D_2_6
CELL8.OUT_F6SERDES.FF_RX_D_2_1
CELL8.OUT_F7SERDES.FF_RX_D_2_2
CELL9.IMUX_A0SERDES.FFC_EI_EN_2
CELL9.IMUX_A1SERDES.FFC_ENABLE_CGALIGN_2
CELL9.IMUX_A2SERDES.FFC_FB_LOOPBACK_2
CELL9.IMUX_A3SERDES.SCIENCH2
CELL9.IMUX_A4SERDES.FFC_SIGNAL_DETECT_2
CELL9.IMUX_A5SERDES.FFC_SB_PFIFO_LP_2
CELL9.IMUX_B0SERDES.FFC_PCIE_CT_2
CELL9.IMUX_B1SERDES.SCISELCH2
CELL9.IMUX_LSR0SERDES.FFC_RRST_2
CELL9.OUT_F0SERDES.FF_RX_D_2_8
CELL9.OUT_F1SERDES.FF_RX_D_2_15
CELL9.OUT_F2SERDES.FF_RX_D_2_11
CELL9.OUT_F3SERDES.FF_RX_D_2_12
CELL9.OUT_F4SERDES.FF_RX_D_2_13
CELL9.OUT_F5SERDES.FF_RX_D_2_14
CELL9.OUT_F6SERDES.FF_RX_D_2_9
CELL9.OUT_F7SERDES.FF_RX_D_2_10
CELL10.IMUX_A0SERDES.FFC_PCI_DET_EN_2
CELL10.IMUX_A1SERDES.FFC_PFIFO_CLR_2
CELL10.IMUX_A2SERDES.FFC_SB_INV_RX_2
CELL10.IMUX_A3SERDES.FFC_RXPWDNB_2
CELL10.IMUX_B1SERDES.FFC_TXPWDNB_2
CELL10.IMUX_LSR0SERDES.FFC_LANE_RX_RST_2
CELL10.OUT_F0SERDES.FF_RX_D_2_16
CELL10.OUT_F1SERDES.FF_RX_D_2_23
CELL10.OUT_F2SERDES.FF_RX_D_2_19
CELL10.OUT_F3SERDES.FF_RX_D_2_20
CELL10.OUT_F4SERDES.FF_RX_D_2_21
CELL10.OUT_F5SERDES.FF_RX_D_2_22
CELL10.OUT_F6SERDES.FF_RX_D_2_17
CELL10.OUT_F7SERDES.FF_RX_D_2_18
CELL11.IMUX_A0SERDES.CIN11
CELL11.IMUX_A1SERDES.CIN10
CELL11.IMUX_A2SERDES.CIN9
CELL11.IMUX_A3SERDES.CIN7
CELL11.IMUX_A4SERDES.CIN6
CELL11.IMUX_A5SERDES.CIN5
CELL11.IMUX_B0SERDES.CIN4
CELL11.IMUX_B1SERDES.CIN8
CELL11.OUT_F0SERDES.SCIINT
CELL11.OUT_F1SERDES.SCIRDATA1
CELL11.OUT_F2SERDES.SCIRDATA5
CELL11.OUT_F3SERDES.SCIRDATA4
CELL11.OUT_F4SERDES.SCIRDATA3
CELL11.OUT_F5SERDES.SCIRDATA2
CELL11.OUT_F6SERDES.SCIRDATA7
CELL11.OUT_F7SERDES.SCIRDATA6
CELL12.IMUX_A0SERDES.CIN3
CELL12.IMUX_A1SERDES.CIN2
CELL12.IMUX_A2SERDES.CIN1
CELL12.IMUX_A3SERDES.SCIADDR5
CELL12.IMUX_A4SERDES.SCIADDR4
CELL12.IMUX_A5SERDES.SCIADDR3
CELL12.IMUX_B0SERDES.SCIADDR2
CELL12.IMUX_B1SERDES.CIN0
CELL12.OUT_F0SERDES.SCIRDATA0
CELL12.OUT_F1SERDES.COUT17
CELL12.OUT_F3SERDES.REFCK2CORE
CELL12.OUT_F4SERDES.COUT19
CELL12.OUT_F5SERDES.COUT18
CELL12.OUT_F6SERDES.FF_TX_F_CLK
CELL12.OUT_F7SERDES.FF_TX_H_CLK
CELL13.IMUX_A0SERDES.SCIADDR1
CELL13.IMUX_A1SERDES.SCIADDR0
CELL13.IMUX_A2SERDES.SCIENAUX
CELL13.IMUX_A3SERDES.SCISELAUX
CELL13.IMUX_A4SERDES.SCIWSTN
CELL13.IMUX_A5SERDES.SCIWDATA7
CELL13.IMUX_B0SERDES.SCIWDATA6
CELL13.IMUX_B1SERDES.SCIRD
CELL13.IMUX_LSR0SERDES.FFC_MACRO_RST
CELL13.OUT_F0SERDES.COUT16
CELL13.OUT_F1SERDES.COUT9
CELL13.OUT_F2SERDES.COUT13
CELL13.OUT_F3SERDES.COUT12
CELL13.OUT_F4SERDES.COUT11
CELL13.OUT_F5SERDES.COUT10
CELL13.OUT_F6SERDES.COUT15
CELL13.OUT_F7SERDES.COUT14
CELL14.IMUX_A0SERDES.SCIWDATA5
CELL14.IMUX_A1SERDES.SCIWDATA4
CELL14.IMUX_A2SERDES.SCIWDATA3
CELL14.IMUX_A3SERDES.SCIWDATA1
CELL14.IMUX_A4SERDES.SCIWDATA0
CELL14.IMUX_A5SERDES.CYAWSTN
CELL14.IMUX_B1SERDES.SCIWDATA2
CELL14.IMUX_CLK0SERDES.FFC_CK_CORE_RX
CELL14.IMUX_LSR0SERDES.FFC_QUAD_RST
CELL14.OUT_F0SERDES.COUT8
CELL14.OUT_F1SERDES.COUT1
CELL14.OUT_F2SERDES.COUT5
CELL14.OUT_F3SERDES.COUT4
CELL14.OUT_F4SERDES.COUT3
CELL14.OUT_F5SERDES.COUT2
CELL14.OUT_F6SERDES.COUT7
CELL14.OUT_F7SERDES.COUT6
CELL15.IMUX_CLK0SERDES.FFC_CK_CORE_TX
CELL15.IMUX_LSR0SERDES.FFC_TRST
CELL15.OUT_F0SERDES.COUT0
CELL15.OUT_F6SERDES.FF_TX_Q_CLK
CELL15.OUT_F7SERDES.FFS_PLOL
CELL16.IMUX_A0SERDES.FFC_TXPWDNB_1
CELL16.IMUX_A1SERDES.FFC_RXPWDNB_1
CELL16.IMUX_A4SERDES.FFC_SB_INV_RX_1
CELL16.IMUX_A5SERDES.FFC_SB_PFIFO_LP_1
CELL16.IMUX_B0SERDES.FFC_PCI_DET_EN_1
CELL16.IMUX_CLK0SERDES.FF_EBRD_CLK_1
CELL16.IMUX_LSR0SERDES.FFC_LANE_RX_RST_1
CELL16.OUT_F0SERDES.FF_RX_D_1_23
CELL16.OUT_F1SERDES.FF_RX_D_1_16
CELL16.OUT_F2SERDES.FF_RX_D_1_20
CELL16.OUT_F3SERDES.FF_RX_D_1_19
CELL16.OUT_F4SERDES.FF_RX_D_1_18
CELL16.OUT_F5SERDES.FF_RX_D_1_17
CELL16.OUT_F6SERDES.FF_RX_D_1_22
CELL16.OUT_F7SERDES.FF_RX_D_1_21
CELL17.IMUX_A0SERDES.FFC_PCIE_CT_1
CELL17.IMUX_A1SERDES.FFC_PFIFO_CLR_1
CELL17.IMUX_A2SERDES.FFC_SIGNAL_DETECT_1
CELL17.IMUX_A3SERDES.SCISELCH1
CELL17.IMUX_A4SERDES.FFC_FB_LOOPBACK_1
CELL17.IMUX_A5SERDES.FFC_ENABLE_CGALIGN_1
CELL17.IMUX_B0SERDES.FFC_EI_EN_1
CELL17.IMUX_B1SERDES.SCIENCH1
CELL17.IMUX_CLK0SERDES.FF_RXI_CLK_1
CELL17.IMUX_LSR0SERDES.FFC_LANE_TX_RST_1
CELL17.OUT_F6SERDES.FF_RX_F_CLK_1
CELL17.OUT_F7SERDES.FF_RX_H_CLK_1
CELL18.IMUX_A0SERDES.FF_TX_D_1_23
CELL18.IMUX_A1SERDES.FF_TX_D_1_22
CELL18.IMUX_A2SERDES.FF_TX_D_1_21
CELL18.IMUX_A3SERDES.FF_TX_D_1_19
CELL18.IMUX_A4SERDES.FF_TX_D_1_18
CELL18.IMUX_A5SERDES.FF_TX_D_1_17
CELL18.IMUX_B0SERDES.FF_TX_D_1_16
CELL18.IMUX_B1SERDES.FF_TX_D_1_20
CELL18.IMUX_CLK0SERDES.FF_TXI_CLK_1
CELL18.IMUX_LSR0SERDES.FFC_RRST_1
CELL18.OUT_F0SERDES.FF_RX_D_1_15
CELL18.OUT_F1SERDES.FF_RX_D_1_8
CELL18.OUT_F2SERDES.FF_RX_D_1_12
CELL18.OUT_F3SERDES.FF_RX_D_1_11
CELL18.OUT_F4SERDES.FF_RX_D_1_10
CELL18.OUT_F5SERDES.FF_RX_D_1_9
CELL18.OUT_F6SERDES.FF_RX_D_1_14
CELL18.OUT_F7SERDES.FF_RX_D_1_13
CELL19.IMUX_A0SERDES.FF_TX_D_1_15
CELL19.IMUX_A1SERDES.FF_TX_D_1_14
CELL19.IMUX_A2SERDES.FF_TX_D_1_13
CELL19.IMUX_A3SERDES.FF_TX_D_1_11
CELL19.IMUX_A4SERDES.FF_TX_D_1_10
CELL19.IMUX_A5SERDES.FF_TX_D_1_9
CELL19.IMUX_B0SERDES.FF_TX_D_1_8
CELL19.IMUX_B1SERDES.FF_TX_D_1_12
CELL19.IMUX_LSR0SERDES.FFC_RRST_0
CELL19.OUT_F0SERDES.FF_RX_D_1_7
CELL19.OUT_F1SERDES.FF_RX_D_1_1
CELL19.OUT_F2SERDES.FF_RX_D_1_5
CELL19.OUT_F3SERDES.FF_RX_D_1_4
CELL19.OUT_F4SERDES.FF_RX_D_1_3
CELL19.OUT_F5SERDES.FF_RX_D_1_2
CELL19.OUT_F6SERDES.FF_RX_Q_CLK_1
CELL19.OUT_F7SERDES.FF_RX_D_1_6
CELL20.IMUX_A0SERDES.FF_TX_D_1_7
CELL20.IMUX_A1SERDES.FF_TX_D_1_6
CELL20.IMUX_A2SERDES.FF_TX_D_1_5
CELL20.IMUX_A3SERDES.FF_TX_D_1_3
CELL20.IMUX_A4SERDES.FF_TX_D_1_2
CELL20.IMUX_A5SERDES.FF_TX_D_1_1
CELL20.IMUX_B0SERDES.FF_TX_D_1_0
CELL20.IMUX_B1SERDES.FF_TX_D_1_4
CELL20.OUT_F0SERDES.FF_RX_D_1_0
CELL20.OUT_F1SERDES.OOB_OUT_1
CELL20.OUT_F2SERDES.FFS_LS_SYNC_STATUS_1
CELL20.OUT_F3SERDES.FFS_PCIE_CON_1
CELL20.OUT_F4SERDES.FFS_PCIE_DONE_1
CELL20.OUT_F5SERDES.FFS_RLOS_LO_1
CELL20.OUT_F6SERDES.FFS_CC_OVERRUN_1
CELL20.OUT_F7SERDES.FFS_CC_UNDERRUN_1
CELL21.OUT_F0SERDES.FFS_TXFBFIFO_ERROR_0
CELL21.OUT_F2SERDES.FFS_RXFBFIFO_ERROR_1
CELL21.OUT_F3SERDES.FFS_RLOL_1
CELL21.OUT_F4SERDES.FFS_TXFBFIFO_ERROR_1
CELL21.OUT_F5SERDES.FFS_RXFBFIFO_ERROR_0
CELL21.OUT_F6SERDES.FF_RX_Q_CLK_0
CELL21.OUT_F7SERDES.FFS_RLOL_0
CELL22.IMUX_A0SERDES.FF_TX_D_0_0
CELL22.IMUX_A1SERDES.FF_TX_D_0_1
CELL22.IMUX_A2SERDES.FF_TX_D_0_2
CELL22.IMUX_A3SERDES.FF_TX_D_0_4
CELL22.IMUX_A4SERDES.FF_TX_D_0_5
CELL22.IMUX_A5SERDES.FF_TX_D_0_6
CELL22.IMUX_B0SERDES.FF_TX_D_0_7
CELL22.IMUX_B1SERDES.FF_TX_D_0_3
CELL22.IMUX_CLK0SERDES.FF_TXI_CLK_0
CELL22.IMUX_LSR0SERDES.FFC_LANE_TX_RST_0
CELL22.OUT_F0SERDES.OOB_OUT_0
CELL22.OUT_F2SERDES.FFS_PCIE_CON_0
CELL22.OUT_F3SERDES.FFS_LS_SYNC_STATUS_0
CELL22.OUT_F4SERDES.FFS_CC_UNDERRUN_0
CELL22.OUT_F5SERDES.FFS_CC_OVERRUN_0
CELL22.OUT_F6SERDES.FFS_RLOS_LO_0
CELL22.OUT_F7SERDES.FFS_PCIE_DONE_0
CELL23.IMUX_A0SERDES.FF_TX_D_0_8
CELL23.IMUX_A1SERDES.FF_TX_D_0_9
CELL23.IMUX_A2SERDES.FF_TX_D_0_10
CELL23.IMUX_A3SERDES.FF_TX_D_0_12
CELL23.IMUX_A4SERDES.FF_TX_D_0_13
CELL23.IMUX_A5SERDES.FF_TX_D_0_14
CELL23.IMUX_B0SERDES.FF_TX_D_0_15
CELL23.IMUX_B1SERDES.FF_TX_D_0_11
CELL23.IMUX_CLK0SERDES.FF_RXI_CLK_0
CELL23.OUT_F1SERDES.FF_RX_D_0_2
CELL23.OUT_F4SERDES.FF_RX_D_0_0
CELL23.OUT_F5SERDES.FF_RX_D_0_1
CELL24.IMUX_A0SERDES.FF_TX_D_0_16
CELL24.IMUX_A1SERDES.FF_TX_D_0_17
CELL24.IMUX_A2SERDES.FF_TX_D_0_18
CELL24.IMUX_A3SERDES.FF_TX_D_0_20
CELL24.IMUX_A4SERDES.FF_TX_D_0_21
CELL24.IMUX_A5SERDES.FF_TX_D_0_22
CELL24.IMUX_B0SERDES.FF_TX_D_0_23
CELL24.IMUX_B1SERDES.FF_TX_D_0_19
CELL24.IMUX_CLK0SERDES.FF_EBRD_CLK_0
CELL24.OUT_F1SERDES.FF_RX_D_0_7
CELL24.OUT_F2SERDES.FF_RX_D_0_3
CELL24.OUT_F3SERDES.FF_RX_D_0_4
CELL24.OUT_F4SERDES.FF_RX_D_0_5
CELL24.OUT_F5SERDES.FF_RX_D_0_6
CELL24.OUT_F6SERDES.FF_RX_F_CLK_0
CELL24.OUT_F7SERDES.FF_RX_H_CLK_0
CELL25.IMUX_A0SERDES.FFC_EI_EN_0
CELL25.IMUX_A1SERDES.FFC_ENABLE_CGALIGN_0
CELL25.IMUX_A2SERDES.FFC_FB_LOOPBACK_0
CELL25.IMUX_A3SERDES.SCIENCH0
CELL25.IMUX_A4SERDES.FFC_SIGNAL_DETECT_0
CELL25.IMUX_A5SERDES.FFC_SB_PFIFO_LP_0
CELL25.IMUX_B0SERDES.FFC_PCIE_CT_0
CELL25.IMUX_B1SERDES.SCISELCH0
CELL25.OUT_F0SERDES.FF_RX_D_0_8
CELL25.OUT_F1SERDES.FF_RX_D_0_15
CELL25.OUT_F2SERDES.FF_RX_D_0_11
CELL25.OUT_F3SERDES.FF_RX_D_0_12
CELL25.OUT_F4SERDES.FF_RX_D_0_13
CELL25.OUT_F5SERDES.FF_RX_D_0_14
CELL25.OUT_F6SERDES.FF_RX_D_0_9
CELL25.OUT_F7SERDES.FF_RX_D_0_10
CELL26.IMUX_A0SERDES.FFC_PCI_DET_EN_0
CELL26.IMUX_A1SERDES.FFC_PFIFO_CLR_0
CELL26.IMUX_A2SERDES.FFC_SB_INV_RX_0
CELL26.IMUX_A3SERDES.FFC_RXPWDNB_0
CELL26.IMUX_B1SERDES.FFC_TXPWDNB_0
CELL26.IMUX_LSR0SERDES.FFC_LANE_RX_RST_0
CELL26.OUT_F0SERDES.FF_RX_D_0_16
CELL26.OUT_F1SERDES.FF_RX_D_0_23
CELL26.OUT_F2SERDES.FF_RX_D_0_19
CELL26.OUT_F3SERDES.FF_RX_D_0_20
CELL26.OUT_F4SERDES.FF_RX_D_0_21
CELL26.OUT_F5SERDES.FF_RX_D_0_22
CELL26.OUT_F6SERDES.FF_RX_D_0_17
CELL26.OUT_F7SERDES.FF_RX_D_0_18

Tile SERDES_N

Cells: 27

Bel SERDES

ecp2m SERDES_N bel SERDES
PinDirectionWires
CIN0inputCELL12.IMUX_B1
CIN1inputCELL12.IMUX_A2
CIN10inputCELL11.IMUX_A1
CIN11inputCELL11.IMUX_A0
CIN2inputCELL12.IMUX_A1
CIN3inputCELL12.IMUX_A0
CIN4inputCELL11.IMUX_B0
CIN5inputCELL11.IMUX_A5
CIN6inputCELL11.IMUX_A4
CIN7inputCELL11.IMUX_A3
CIN8inputCELL11.IMUX_B1
CIN9inputCELL11.IMUX_A2
COUT0outputCELL15.OUT_F0
COUT1outputCELL14.OUT_F1
COUT10outputCELL13.OUT_F5
COUT11outputCELL13.OUT_F4
COUT12outputCELL13.OUT_F3
COUT13outputCELL13.OUT_F2
COUT14outputCELL13.OUT_F7
COUT15outputCELL13.OUT_F6
COUT16outputCELL13.OUT_F0
COUT17outputCELL12.OUT_F1
COUT18outputCELL12.OUT_F5
COUT19outputCELL12.OUT_F4
COUT2outputCELL14.OUT_F5
COUT3outputCELL14.OUT_F4
COUT4outputCELL14.OUT_F3
COUT5outputCELL14.OUT_F2
COUT6outputCELL14.OUT_F7
COUT7outputCELL14.OUT_F6
COUT8outputCELL14.OUT_F0
COUT9outputCELL13.OUT_F1
CYAWSTNinputCELL14.IMUX_A5
FFC_CK_CORE_RXinputCELL14.IMUX_CLK0
FFC_CK_CORE_TXinputCELL15.IMUX_CLK0
FFC_EI_EN_0inputCELL25.IMUX_A0
FFC_EI_EN_1inputCELL17.IMUX_B0
FFC_EI_EN_2inputCELL9.IMUX_A0
FFC_EI_EN_3inputCELL1.IMUX_B0
FFC_ENABLE_CGALIGN_0inputCELL25.IMUX_A1
FFC_ENABLE_CGALIGN_1inputCELL17.IMUX_A5
FFC_ENABLE_CGALIGN_2inputCELL9.IMUX_A1
FFC_ENABLE_CGALIGN_3inputCELL1.IMUX_A5
FFC_FB_LOOPBACK_0inputCELL25.IMUX_A2
FFC_FB_LOOPBACK_1inputCELL17.IMUX_A4
FFC_FB_LOOPBACK_2inputCELL9.IMUX_A2
FFC_FB_LOOPBACK_3inputCELL1.IMUX_A4
FFC_LANE_RX_RST_0inputCELL26.IMUX_LSR0
FFC_LANE_RX_RST_1inputCELL16.IMUX_LSR0
FFC_LANE_RX_RST_2inputCELL10.IMUX_LSR0
FFC_LANE_RX_RST_3inputCELL0.IMUX_LSR0
FFC_LANE_TX_RST_0inputCELL22.IMUX_LSR0
FFC_LANE_TX_RST_1inputCELL17.IMUX_LSR0
FFC_LANE_TX_RST_2inputCELL6.IMUX_LSR0
FFC_LANE_TX_RST_3inputCELL1.IMUX_LSR0
FFC_MACRO_RSTinputCELL13.IMUX_LSR0
FFC_PCIE_CT_0inputCELL25.IMUX_B0
FFC_PCIE_CT_1inputCELL17.IMUX_A0
FFC_PCIE_CT_2inputCELL9.IMUX_B0
FFC_PCIE_CT_3inputCELL1.IMUX_A0
FFC_PCI_DET_EN_0inputCELL26.IMUX_A0
FFC_PCI_DET_EN_1inputCELL16.IMUX_B0
FFC_PCI_DET_EN_2inputCELL10.IMUX_A0
FFC_PCI_DET_EN_3inputCELL0.IMUX_B0
FFC_PFIFO_CLR_0inputCELL26.IMUX_A1
FFC_PFIFO_CLR_1inputCELL17.IMUX_A1
FFC_PFIFO_CLR_2inputCELL10.IMUX_A1
FFC_PFIFO_CLR_3inputCELL1.IMUX_A1
FFC_QUAD_RSTinputCELL14.IMUX_LSR0
FFC_RRST_0inputCELL19.IMUX_LSR0
FFC_RRST_1inputCELL18.IMUX_LSR0
FFC_RRST_2inputCELL9.IMUX_LSR0
FFC_RRST_3inputCELL8.IMUX_LSR0
FFC_RXPWDNB_0inputCELL26.IMUX_A3
FFC_RXPWDNB_1inputCELL16.IMUX_A1
FFC_RXPWDNB_2inputCELL10.IMUX_A3
FFC_RXPWDNB_3inputCELL0.IMUX_A1
FFC_SB_INV_RX_0inputCELL26.IMUX_A2
FFC_SB_INV_RX_1inputCELL16.IMUX_A4
FFC_SB_INV_RX_2inputCELL10.IMUX_A2
FFC_SB_INV_RX_3inputCELL0.IMUX_A4
FFC_SB_PFIFO_LP_0inputCELL25.IMUX_A5
FFC_SB_PFIFO_LP_1inputCELL16.IMUX_A5
FFC_SB_PFIFO_LP_2inputCELL9.IMUX_A5
FFC_SB_PFIFO_LP_3inputCELL0.IMUX_A5
FFC_SIGNAL_DETECT_0inputCELL25.IMUX_A4
FFC_SIGNAL_DETECT_1inputCELL17.IMUX_A2
FFC_SIGNAL_DETECT_2inputCELL9.IMUX_A4
FFC_SIGNAL_DETECT_3inputCELL1.IMUX_A2
FFC_TRSTinputCELL15.IMUX_LSR0
FFC_TXPWDNB_0inputCELL26.IMUX_B1
FFC_TXPWDNB_1inputCELL16.IMUX_A0
FFC_TXPWDNB_2inputCELL10.IMUX_B1
FFC_TXPWDNB_3inputCELL0.IMUX_A0
FFS_CC_OVERRUN_0outputCELL22.OUT_F5
FFS_CC_OVERRUN_1outputCELL20.OUT_F6
FFS_CC_OVERRUN_2outputCELL6.OUT_F1
FFS_CC_OVERRUN_3outputCELL4.OUT_F0
FFS_CC_UNDERRUN_0outputCELL22.OUT_F4
FFS_CC_UNDERRUN_1outputCELL20.OUT_F7
FFS_CC_UNDERRUN_2outputCELL6.OUT_F5
FFS_CC_UNDERRUN_3outputCELL4.OUT_F7
FFS_LS_SYNC_STATUS_0outputCELL22.OUT_F3
FFS_LS_SYNC_STATUS_1outputCELL20.OUT_F2
FFS_LS_SYNC_STATUS_2outputCELL6.OUT_F4
FFS_LS_SYNC_STATUS_3outputCELL4.OUT_F2
FFS_PCIE_CON_0outputCELL22.OUT_F2
FFS_PCIE_CON_1outputCELL20.OUT_F3
FFS_PCIE_CON_2outputCELL6.OUT_F3
FFS_PCIE_CON_3outputCELL4.OUT_F3
FFS_PCIE_DONE_0outputCELL22.OUT_F7
FFS_PCIE_DONE_1outputCELL20.OUT_F4
FFS_PCIE_DONE_2outputCELL6.OUT_F2
FFS_PCIE_DONE_3outputCELL4.OUT_F4
FFS_PLOLoutputCELL15.OUT_F7
FFS_RLOL_0outputCELL21.OUT_F7
FFS_RLOL_1outputCELL21.OUT_F3
FFS_RLOL_2outputCELL5.OUT_F3
FFS_RLOL_3outputCELL5.OUT_F6
FFS_RLOS_LO_0outputCELL22.OUT_F6
FFS_RLOS_LO_1outputCELL20.OUT_F5
FFS_RLOS_LO_2outputCELL6.OUT_F7
FFS_RLOS_LO_3outputCELL4.OUT_F5
FFS_RXFBFIFO_ERROR_0outputCELL21.OUT_F5
FFS_RXFBFIFO_ERROR_1outputCELL21.OUT_F2
FFS_RXFBFIFO_ERROR_2outputCELL5.OUT_F4
FFS_RXFBFIFO_ERROR_3outputCELL5.OUT_F0
FFS_TXFBFIFO_ERROR_0outputCELL21.OUT_F0
FFS_TXFBFIFO_ERROR_1outputCELL21.OUT_F4
FFS_TXFBFIFO_ERROR_2outputCELL5.OUT_F2
FFS_TXFBFIFO_ERROR_3outputCELL5.OUT_F7
FF_EBRD_CLK_0inputCELL24.IMUX_CLK0
FF_EBRD_CLK_1inputCELL16.IMUX_CLK0
FF_EBRD_CLK_2inputCELL8.IMUX_CLK0
FF_EBRD_CLK_3inputCELL0.IMUX_CLK0
FF_RXI_CLK_0inputCELL23.IMUX_CLK0
FF_RXI_CLK_1inputCELL17.IMUX_CLK0
FF_RXI_CLK_2inputCELL7.IMUX_CLK0
FF_RXI_CLK_3inputCELL1.IMUX_CLK0
FF_RX_D_0_0outputCELL23.OUT_F4
FF_RX_D_0_1outputCELL23.OUT_F5
FF_RX_D_0_10outputCELL25.OUT_F7
FF_RX_D_0_11outputCELL25.OUT_F2
FF_RX_D_0_12outputCELL25.OUT_F3
FF_RX_D_0_13outputCELL25.OUT_F4
FF_RX_D_0_14outputCELL25.OUT_F5
FF_RX_D_0_15outputCELL25.OUT_F1
FF_RX_D_0_16outputCELL26.OUT_F0
FF_RX_D_0_17outputCELL26.OUT_F6
FF_RX_D_0_18outputCELL26.OUT_F7
FF_RX_D_0_19outputCELL26.OUT_F2
FF_RX_D_0_2outputCELL23.OUT_F1
FF_RX_D_0_20outputCELL26.OUT_F3
FF_RX_D_0_21outputCELL26.OUT_F4
FF_RX_D_0_22outputCELL26.OUT_F5
FF_RX_D_0_23outputCELL26.OUT_F1
FF_RX_D_0_3outputCELL24.OUT_F2
FF_RX_D_0_4outputCELL24.OUT_F3
FF_RX_D_0_5outputCELL24.OUT_F4
FF_RX_D_0_6outputCELL24.OUT_F5
FF_RX_D_0_7outputCELL24.OUT_F1
FF_RX_D_0_8outputCELL25.OUT_F0
FF_RX_D_0_9outputCELL25.OUT_F6
FF_RX_D_1_0outputCELL20.OUT_F0
FF_RX_D_1_1outputCELL19.OUT_F1
FF_RX_D_1_10outputCELL18.OUT_F4
FF_RX_D_1_11outputCELL18.OUT_F3
FF_RX_D_1_12outputCELL18.OUT_F2
FF_RX_D_1_13outputCELL18.OUT_F7
FF_RX_D_1_14outputCELL18.OUT_F6
FF_RX_D_1_15outputCELL18.OUT_F0
FF_RX_D_1_16outputCELL16.OUT_F1
FF_RX_D_1_17outputCELL16.OUT_F5
FF_RX_D_1_18outputCELL16.OUT_F4
FF_RX_D_1_19outputCELL16.OUT_F3
FF_RX_D_1_2outputCELL19.OUT_F5
FF_RX_D_1_20outputCELL16.OUT_F2
FF_RX_D_1_21outputCELL16.OUT_F7
FF_RX_D_1_22outputCELL16.OUT_F6
FF_RX_D_1_23outputCELL16.OUT_F0
FF_RX_D_1_3outputCELL19.OUT_F4
FF_RX_D_1_4outputCELL19.OUT_F3
FF_RX_D_1_5outputCELL19.OUT_F2
FF_RX_D_1_6outputCELL19.OUT_F7
FF_RX_D_1_7outputCELL19.OUT_F0
FF_RX_D_1_8outputCELL18.OUT_F1
FF_RX_D_1_9outputCELL18.OUT_F5
FF_RX_D_2_0outputCELL8.OUT_F0
FF_RX_D_2_1outputCELL8.OUT_F6
FF_RX_D_2_10outputCELL9.OUT_F7
FF_RX_D_2_11outputCELL9.OUT_F2
FF_RX_D_2_12outputCELL9.OUT_F3
FF_RX_D_2_13outputCELL9.OUT_F4
FF_RX_D_2_14outputCELL9.OUT_F5
FF_RX_D_2_15outputCELL9.OUT_F1
FF_RX_D_2_16outputCELL10.OUT_F0
FF_RX_D_2_17outputCELL10.OUT_F6
FF_RX_D_2_18outputCELL10.OUT_F7
FF_RX_D_2_19outputCELL10.OUT_F2
FF_RX_D_2_2outputCELL8.OUT_F7
FF_RX_D_2_20outputCELL10.OUT_F3
FF_RX_D_2_21outputCELL10.OUT_F4
FF_RX_D_2_22outputCELL10.OUT_F5
FF_RX_D_2_23outputCELL10.OUT_F1
FF_RX_D_2_3outputCELL8.OUT_F2
FF_RX_D_2_4outputCELL8.OUT_F3
FF_RX_D_2_5outputCELL8.OUT_F4
FF_RX_D_2_6outputCELL8.OUT_F5
FF_RX_D_2_7outputCELL8.OUT_F1
FF_RX_D_2_8outputCELL9.OUT_F0
FF_RX_D_2_9outputCELL9.OUT_F6
FF_RX_D_3_0outputCELL3.OUT_F1
FF_RX_D_3_1outputCELL3.OUT_F5
FF_RX_D_3_10outputCELL1.OUT_F4
FF_RX_D_3_11outputCELL1.OUT_F3
FF_RX_D_3_12outputCELL1.OUT_F2
FF_RX_D_3_13outputCELL1.OUT_F7
FF_RX_D_3_14outputCELL1.OUT_F6
FF_RX_D_3_15outputCELL1.OUT_F0
FF_RX_D_3_16outputCELL0.OUT_F1
FF_RX_D_3_17outputCELL0.OUT_F5
FF_RX_D_3_18outputCELL0.OUT_F4
FF_RX_D_3_19outputCELL0.OUT_F3
FF_RX_D_3_2outputCELL3.OUT_F4
FF_RX_D_3_20outputCELL0.OUT_F2
FF_RX_D_3_21outputCELL0.OUT_F7
FF_RX_D_3_22outputCELL0.OUT_F6
FF_RX_D_3_23outputCELL0.OUT_F0
FF_RX_D_3_3outputCELL3.OUT_F3
FF_RX_D_3_4outputCELL3.OUT_F2
FF_RX_D_3_5outputCELL3.OUT_F7
FF_RX_D_3_6outputCELL3.OUT_F6
FF_RX_D_3_7outputCELL3.OUT_F0
FF_RX_D_3_8outputCELL1.OUT_F1
FF_RX_D_3_9outputCELL1.OUT_F5
FF_RX_F_CLK_0outputCELL24.OUT_F6
FF_RX_F_CLK_1outputCELL17.OUT_F6
FF_RX_F_CLK_2outputCELL7.OUT_F6
FF_RX_F_CLK_3outputCELL2.OUT_F6
FF_RX_H_CLK_0outputCELL24.OUT_F7
FF_RX_H_CLK_1outputCELL17.OUT_F7
FF_RX_H_CLK_2outputCELL7.OUT_F7
FF_RX_H_CLK_3outputCELL2.OUT_F7
FF_RX_Q_CLK_0outputCELL21.OUT_F6
FF_RX_Q_CLK_1outputCELL19.OUT_F6
FF_RX_Q_CLK_2outputCELL6.OUT_F6
FF_RX_Q_CLK_3outputCELL4.OUT_F6
FF_TXI_CLK_0inputCELL22.IMUX_CLK0
FF_TXI_CLK_1inputCELL18.IMUX_CLK0
FF_TXI_CLK_2inputCELL6.IMUX_CLK0
FF_TXI_CLK_3inputCELL2.IMUX_CLK0
FF_TX_D_0_0inputCELL22.IMUX_A0
FF_TX_D_0_1inputCELL22.IMUX_A1
FF_TX_D_0_10inputCELL23.IMUX_A2
FF_TX_D_0_11inputCELL23.IMUX_B1
FF_TX_D_0_12inputCELL23.IMUX_A3
FF_TX_D_0_13inputCELL23.IMUX_A4
FF_TX_D_0_14inputCELL23.IMUX_A5
FF_TX_D_0_15inputCELL23.IMUX_B0
FF_TX_D_0_16inputCELL24.IMUX_A0
FF_TX_D_0_17inputCELL24.IMUX_A1
FF_TX_D_0_18inputCELL24.IMUX_A2
FF_TX_D_0_19inputCELL24.IMUX_B1
FF_TX_D_0_2inputCELL22.IMUX_A2
FF_TX_D_0_20inputCELL24.IMUX_A3
FF_TX_D_0_21inputCELL24.IMUX_A4
FF_TX_D_0_22inputCELL24.IMUX_A5
FF_TX_D_0_23inputCELL24.IMUX_B0
FF_TX_D_0_3inputCELL22.IMUX_B1
FF_TX_D_0_4inputCELL22.IMUX_A3
FF_TX_D_0_5inputCELL22.IMUX_A4
FF_TX_D_0_6inputCELL22.IMUX_A5
FF_TX_D_0_7inputCELL22.IMUX_B0
FF_TX_D_0_8inputCELL23.IMUX_A0
FF_TX_D_0_9inputCELL23.IMUX_A1
FF_TX_D_1_0inputCELL20.IMUX_B0
FF_TX_D_1_1inputCELL20.IMUX_A5
FF_TX_D_1_10inputCELL19.IMUX_A4
FF_TX_D_1_11inputCELL19.IMUX_A3
FF_TX_D_1_12inputCELL19.IMUX_B1
FF_TX_D_1_13inputCELL19.IMUX_A2
FF_TX_D_1_14inputCELL19.IMUX_A1
FF_TX_D_1_15inputCELL19.IMUX_A0
FF_TX_D_1_16inputCELL18.IMUX_B0
FF_TX_D_1_17inputCELL18.IMUX_A5
FF_TX_D_1_18inputCELL18.IMUX_A4
FF_TX_D_1_19inputCELL18.IMUX_A3
FF_TX_D_1_2inputCELL20.IMUX_A4
FF_TX_D_1_20inputCELL18.IMUX_B1
FF_TX_D_1_21inputCELL18.IMUX_A2
FF_TX_D_1_22inputCELL18.IMUX_A1
FF_TX_D_1_23inputCELL18.IMUX_A0
FF_TX_D_1_3inputCELL20.IMUX_A3
FF_TX_D_1_4inputCELL20.IMUX_B1
FF_TX_D_1_5inputCELL20.IMUX_A2
FF_TX_D_1_6inputCELL20.IMUX_A1
FF_TX_D_1_7inputCELL20.IMUX_A0
FF_TX_D_1_8inputCELL19.IMUX_B0
FF_TX_D_1_9inputCELL19.IMUX_A5
FF_TX_D_2_0inputCELL6.IMUX_A0
FF_TX_D_2_1inputCELL6.IMUX_A1
FF_TX_D_2_10inputCELL7.IMUX_A2
FF_TX_D_2_11inputCELL7.IMUX_B1
FF_TX_D_2_12inputCELL7.IMUX_A3
FF_TX_D_2_13inputCELL7.IMUX_A4
FF_TX_D_2_14inputCELL7.IMUX_A5
FF_TX_D_2_15inputCELL7.IMUX_B0
FF_TX_D_2_16inputCELL8.IMUX_A0
FF_TX_D_2_17inputCELL8.IMUX_A1
FF_TX_D_2_18inputCELL8.IMUX_A2
FF_TX_D_2_19inputCELL8.IMUX_B1
FF_TX_D_2_2inputCELL6.IMUX_A2
FF_TX_D_2_20inputCELL8.IMUX_A3
FF_TX_D_2_21inputCELL8.IMUX_A4
FF_TX_D_2_22inputCELL8.IMUX_A5
FF_TX_D_2_23inputCELL8.IMUX_B0
FF_TX_D_2_3inputCELL6.IMUX_B1
FF_TX_D_2_4inputCELL6.IMUX_A3
FF_TX_D_2_5inputCELL6.IMUX_A4
FF_TX_D_2_6inputCELL6.IMUX_A5
FF_TX_D_2_7inputCELL6.IMUX_B0
FF_TX_D_2_8inputCELL7.IMUX_A0
FF_TX_D_2_9inputCELL7.IMUX_A1
FF_TX_D_3_0inputCELL4.IMUX_B0
FF_TX_D_3_1inputCELL4.IMUX_A5
FF_TX_D_3_10inputCELL3.IMUX_A4
FF_TX_D_3_11inputCELL3.IMUX_A3
FF_TX_D_3_12inputCELL3.IMUX_B1
FF_TX_D_3_13inputCELL3.IMUX_A2
FF_TX_D_3_14inputCELL3.IMUX_A1
FF_TX_D_3_15inputCELL3.IMUX_A0
FF_TX_D_3_16inputCELL2.IMUX_B0
FF_TX_D_3_17inputCELL2.IMUX_A5
FF_TX_D_3_18inputCELL2.IMUX_A4
FF_TX_D_3_19inputCELL2.IMUX_A3
FF_TX_D_3_2inputCELL4.IMUX_A4
FF_TX_D_3_20inputCELL2.IMUX_B1
FF_TX_D_3_21inputCELL2.IMUX_A2
FF_TX_D_3_22inputCELL2.IMUX_A1
FF_TX_D_3_23inputCELL2.IMUX_A0
FF_TX_D_3_3inputCELL4.IMUX_A3
FF_TX_D_3_4inputCELL4.IMUX_B1
FF_TX_D_3_5inputCELL4.IMUX_A2
FF_TX_D_3_6inputCELL4.IMUX_A1
FF_TX_D_3_7inputCELL4.IMUX_A0
FF_TX_D_3_8inputCELL3.IMUX_B0
FF_TX_D_3_9inputCELL3.IMUX_A5
FF_TX_F_CLKoutputCELL12.OUT_F6
FF_TX_H_CLKoutputCELL12.OUT_F7
FF_TX_Q_CLKoutputCELL15.OUT_F6
OOB_OUT_0outputCELL22.OUT_F0
OOB_OUT_1outputCELL20.OUT_F1
OOB_OUT_2outputCELL6.OUT_F0
OOB_OUT_3outputCELL4.OUT_F1
REFCK2COREoutputCELL12.OUT_F3
SCIADDR0inputCELL13.IMUX_A1
SCIADDR1inputCELL13.IMUX_A0
SCIADDR2inputCELL12.IMUX_B0
SCIADDR3inputCELL12.IMUX_A5
SCIADDR4inputCELL12.IMUX_A4
SCIADDR5inputCELL12.IMUX_A3
SCIENAUXinputCELL13.IMUX_A2
SCIENCH0inputCELL25.IMUX_A3
SCIENCH1inputCELL17.IMUX_B1
SCIENCH2inputCELL9.IMUX_A3
SCIENCH3inputCELL1.IMUX_B1
SCIINToutputCELL11.OUT_F0
SCIRDinputCELL13.IMUX_B1
SCIRDATA0outputCELL12.OUT_F0
SCIRDATA1outputCELL11.OUT_F1
SCIRDATA2outputCELL11.OUT_F5
SCIRDATA3outputCELL11.OUT_F4
SCIRDATA4outputCELL11.OUT_F3
SCIRDATA5outputCELL11.OUT_F2
SCIRDATA6outputCELL11.OUT_F7
SCIRDATA7outputCELL11.OUT_F6
SCISELAUXinputCELL13.IMUX_A3
SCISELCH0inputCELL25.IMUX_B1
SCISELCH1inputCELL17.IMUX_A3
SCISELCH2inputCELL9.IMUX_B1
SCISELCH3inputCELL1.IMUX_A3
SCIWDATA0inputCELL14.IMUX_A4
SCIWDATA1inputCELL14.IMUX_A3
SCIWDATA2inputCELL14.IMUX_B1
SCIWDATA3inputCELL14.IMUX_A2
SCIWDATA4inputCELL14.IMUX_A1
SCIWDATA5inputCELL14.IMUX_A0
SCIWDATA6inputCELL13.IMUX_B0
SCIWDATA7inputCELL13.IMUX_A5
SCIWSTNinputCELL13.IMUX_A4

Bel wires

ecp2m SERDES_N bel wires
WirePins
CELL0.IMUX_A0SERDES.FFC_TXPWDNB_3
CELL0.IMUX_A1SERDES.FFC_RXPWDNB_3
CELL0.IMUX_A4SERDES.FFC_SB_INV_RX_3
CELL0.IMUX_A5SERDES.FFC_SB_PFIFO_LP_3
CELL0.IMUX_B0SERDES.FFC_PCI_DET_EN_3
CELL0.IMUX_CLK0SERDES.FF_EBRD_CLK_3
CELL0.IMUX_LSR0SERDES.FFC_LANE_RX_RST_3
CELL0.OUT_F0SERDES.FF_RX_D_3_23
CELL0.OUT_F1SERDES.FF_RX_D_3_16
CELL0.OUT_F2SERDES.FF_RX_D_3_20
CELL0.OUT_F3SERDES.FF_RX_D_3_19
CELL0.OUT_F4SERDES.FF_RX_D_3_18
CELL0.OUT_F5SERDES.FF_RX_D_3_17
CELL0.OUT_F6SERDES.FF_RX_D_3_22
CELL0.OUT_F7SERDES.FF_RX_D_3_21
CELL1.IMUX_A0SERDES.FFC_PCIE_CT_3
CELL1.IMUX_A1SERDES.FFC_PFIFO_CLR_3
CELL1.IMUX_A2SERDES.FFC_SIGNAL_DETECT_3
CELL1.IMUX_A3SERDES.SCISELCH3
CELL1.IMUX_A4SERDES.FFC_FB_LOOPBACK_3
CELL1.IMUX_A5SERDES.FFC_ENABLE_CGALIGN_3
CELL1.IMUX_B0SERDES.FFC_EI_EN_3
CELL1.IMUX_B1SERDES.SCIENCH3
CELL1.IMUX_CLK0SERDES.FF_RXI_CLK_3
CELL1.IMUX_LSR0SERDES.FFC_LANE_TX_RST_3
CELL1.OUT_F0SERDES.FF_RX_D_3_15
CELL1.OUT_F1SERDES.FF_RX_D_3_8
CELL1.OUT_F2SERDES.FF_RX_D_3_12
CELL1.OUT_F3SERDES.FF_RX_D_3_11
CELL1.OUT_F4SERDES.FF_RX_D_3_10
CELL1.OUT_F5SERDES.FF_RX_D_3_9
CELL1.OUT_F6SERDES.FF_RX_D_3_14
CELL1.OUT_F7SERDES.FF_RX_D_3_13
CELL2.IMUX_A0SERDES.FF_TX_D_3_23
CELL2.IMUX_A1SERDES.FF_TX_D_3_22
CELL2.IMUX_A2SERDES.FF_TX_D_3_21
CELL2.IMUX_A3SERDES.FF_TX_D_3_19
CELL2.IMUX_A4SERDES.FF_TX_D_3_18
CELL2.IMUX_A5SERDES.FF_TX_D_3_17
CELL2.IMUX_B0SERDES.FF_TX_D_3_16
CELL2.IMUX_B1SERDES.FF_TX_D_3_20
CELL2.IMUX_CLK0SERDES.FF_TXI_CLK_3
CELL2.OUT_F6SERDES.FF_RX_F_CLK_3
CELL2.OUT_F7SERDES.FF_RX_H_CLK_3
CELL3.IMUX_A0SERDES.FF_TX_D_3_15
CELL3.IMUX_A1SERDES.FF_TX_D_3_14
CELL3.IMUX_A2SERDES.FF_TX_D_3_13
CELL3.IMUX_A3SERDES.FF_TX_D_3_11
CELL3.IMUX_A4SERDES.FF_TX_D_3_10
CELL3.IMUX_A5SERDES.FF_TX_D_3_9
CELL3.IMUX_B0SERDES.FF_TX_D_3_8
CELL3.IMUX_B1SERDES.FF_TX_D_3_12
CELL3.OUT_F0SERDES.FF_RX_D_3_7
CELL3.OUT_F1SERDES.FF_RX_D_3_0
CELL3.OUT_F2SERDES.FF_RX_D_3_4
CELL3.OUT_F3SERDES.FF_RX_D_3_3
CELL3.OUT_F4SERDES.FF_RX_D_3_2
CELL3.OUT_F5SERDES.FF_RX_D_3_1
CELL3.OUT_F6SERDES.FF_RX_D_3_6
CELL3.OUT_F7SERDES.FF_RX_D_3_5
CELL4.IMUX_A0SERDES.FF_TX_D_3_7
CELL4.IMUX_A1SERDES.FF_TX_D_3_6
CELL4.IMUX_A2SERDES.FF_TX_D_3_5
CELL4.IMUX_A3SERDES.FF_TX_D_3_3
CELL4.IMUX_A4SERDES.FF_TX_D_3_2
CELL4.IMUX_A5SERDES.FF_TX_D_3_1
CELL4.IMUX_B0SERDES.FF_TX_D_3_0
CELL4.IMUX_B1SERDES.FF_TX_D_3_4
CELL4.OUT_F0SERDES.FFS_CC_OVERRUN_3
CELL4.OUT_F1SERDES.OOB_OUT_3
CELL4.OUT_F2SERDES.FFS_LS_SYNC_STATUS_3
CELL4.OUT_F3SERDES.FFS_PCIE_CON_3
CELL4.OUT_F4SERDES.FFS_PCIE_DONE_3
CELL4.OUT_F5SERDES.FFS_RLOS_LO_3
CELL4.OUT_F6SERDES.FF_RX_Q_CLK_3
CELL4.OUT_F7SERDES.FFS_CC_UNDERRUN_3
CELL5.OUT_F0SERDES.FFS_RXFBFIFO_ERROR_3
CELL5.OUT_F2SERDES.FFS_TXFBFIFO_ERROR_2
CELL5.OUT_F3SERDES.FFS_RLOL_2
CELL5.OUT_F4SERDES.FFS_RXFBFIFO_ERROR_2
CELL5.OUT_F6SERDES.FFS_RLOL_3
CELL5.OUT_F7SERDES.FFS_TXFBFIFO_ERROR_3
CELL6.IMUX_A0SERDES.FF_TX_D_2_0
CELL6.IMUX_A1SERDES.FF_TX_D_2_1
CELL6.IMUX_A2SERDES.FF_TX_D_2_2
CELL6.IMUX_A3SERDES.FF_TX_D_2_4
CELL6.IMUX_A4SERDES.FF_TX_D_2_5
CELL6.IMUX_A5SERDES.FF_TX_D_2_6
CELL6.IMUX_B0SERDES.FF_TX_D_2_7
CELL6.IMUX_B1SERDES.FF_TX_D_2_3
CELL6.IMUX_CLK0SERDES.FF_TXI_CLK_2
CELL6.IMUX_LSR0SERDES.FFC_LANE_TX_RST_2
CELL6.OUT_F0SERDES.OOB_OUT_2
CELL6.OUT_F1SERDES.FFS_CC_OVERRUN_2
CELL6.OUT_F2SERDES.FFS_PCIE_DONE_2
CELL6.OUT_F3SERDES.FFS_PCIE_CON_2
CELL6.OUT_F4SERDES.FFS_LS_SYNC_STATUS_2
CELL6.OUT_F5SERDES.FFS_CC_UNDERRUN_2
CELL6.OUT_F6SERDES.FF_RX_Q_CLK_2
CELL6.OUT_F7SERDES.FFS_RLOS_LO_2
CELL7.IMUX_A0SERDES.FF_TX_D_2_8
CELL7.IMUX_A1SERDES.FF_TX_D_2_9
CELL7.IMUX_A2SERDES.FF_TX_D_2_10
CELL7.IMUX_A3SERDES.FF_TX_D_2_12
CELL7.IMUX_A4SERDES.FF_TX_D_2_13
CELL7.IMUX_A5SERDES.FF_TX_D_2_14
CELL7.IMUX_B0SERDES.FF_TX_D_2_15
CELL7.IMUX_B1SERDES.FF_TX_D_2_11
CELL7.IMUX_CLK0SERDES.FF_RXI_CLK_2
CELL7.OUT_F6SERDES.FF_RX_F_CLK_2
CELL7.OUT_F7SERDES.FF_RX_H_CLK_2
CELL8.IMUX_A0SERDES.FF_TX_D_2_16
CELL8.IMUX_A1SERDES.FF_TX_D_2_17
CELL8.IMUX_A2SERDES.FF_TX_D_2_18
CELL8.IMUX_A3SERDES.FF_TX_D_2_20
CELL8.IMUX_A4SERDES.FF_TX_D_2_21
CELL8.IMUX_A5SERDES.FF_TX_D_2_22
CELL8.IMUX_B0SERDES.FF_TX_D_2_23
CELL8.IMUX_B1SERDES.FF_TX_D_2_19
CELL8.IMUX_CLK0SERDES.FF_EBRD_CLK_2
CELL8.IMUX_LSR0SERDES.FFC_RRST_3
CELL8.OUT_F0SERDES.FF_RX_D_2_0
CELL8.OUT_F1SERDES.FF_RX_D_2_7
CELL8.OUT_F2SERDES.FF_RX_D_2_3
CELL8.OUT_F3SERDES.FF_RX_D_2_4
CELL8.OUT_F4SERDES.FF_RX_D_2_5
CELL8.OUT_F5SERDES.FF_RX_D_2_6
CELL8.OUT_F6SERDES.FF_RX_D_2_1
CELL8.OUT_F7SERDES.FF_RX_D_2_2
CELL9.IMUX_A0SERDES.FFC_EI_EN_2
CELL9.IMUX_A1SERDES.FFC_ENABLE_CGALIGN_2
CELL9.IMUX_A2SERDES.FFC_FB_LOOPBACK_2
CELL9.IMUX_A3SERDES.SCIENCH2
CELL9.IMUX_A4SERDES.FFC_SIGNAL_DETECT_2
CELL9.IMUX_A5SERDES.FFC_SB_PFIFO_LP_2
CELL9.IMUX_B0SERDES.FFC_PCIE_CT_2
CELL9.IMUX_B1SERDES.SCISELCH2
CELL9.IMUX_LSR0SERDES.FFC_RRST_2
CELL9.OUT_F0SERDES.FF_RX_D_2_8
CELL9.OUT_F1SERDES.FF_RX_D_2_15
CELL9.OUT_F2SERDES.FF_RX_D_2_11
CELL9.OUT_F3SERDES.FF_RX_D_2_12
CELL9.OUT_F4SERDES.FF_RX_D_2_13
CELL9.OUT_F5SERDES.FF_RX_D_2_14
CELL9.OUT_F6SERDES.FF_RX_D_2_9
CELL9.OUT_F7SERDES.FF_RX_D_2_10
CELL10.IMUX_A0SERDES.FFC_PCI_DET_EN_2
CELL10.IMUX_A1SERDES.FFC_PFIFO_CLR_2
CELL10.IMUX_A2SERDES.FFC_SB_INV_RX_2
CELL10.IMUX_A3SERDES.FFC_RXPWDNB_2
CELL10.IMUX_B1SERDES.FFC_TXPWDNB_2
CELL10.IMUX_LSR0SERDES.FFC_LANE_RX_RST_2
CELL10.OUT_F0SERDES.FF_RX_D_2_16
CELL10.OUT_F1SERDES.FF_RX_D_2_23
CELL10.OUT_F2SERDES.FF_RX_D_2_19
CELL10.OUT_F3SERDES.FF_RX_D_2_20
CELL10.OUT_F4SERDES.FF_RX_D_2_21
CELL10.OUT_F5SERDES.FF_RX_D_2_22
CELL10.OUT_F6SERDES.FF_RX_D_2_17
CELL10.OUT_F7SERDES.FF_RX_D_2_18
CELL11.IMUX_A0SERDES.CIN11
CELL11.IMUX_A1SERDES.CIN10
CELL11.IMUX_A2SERDES.CIN9
CELL11.IMUX_A3SERDES.CIN7
CELL11.IMUX_A4SERDES.CIN6
CELL11.IMUX_A5SERDES.CIN5
CELL11.IMUX_B0SERDES.CIN4
CELL11.IMUX_B1SERDES.CIN8
CELL11.OUT_F0SERDES.SCIINT
CELL11.OUT_F1SERDES.SCIRDATA1
CELL11.OUT_F2SERDES.SCIRDATA5
CELL11.OUT_F3SERDES.SCIRDATA4
CELL11.OUT_F4SERDES.SCIRDATA3
CELL11.OUT_F5SERDES.SCIRDATA2
CELL11.OUT_F6SERDES.SCIRDATA7
CELL11.OUT_F7SERDES.SCIRDATA6
CELL12.IMUX_A0SERDES.CIN3
CELL12.IMUX_A1SERDES.CIN2
CELL12.IMUX_A2SERDES.CIN1
CELL12.IMUX_A3SERDES.SCIADDR5
CELL12.IMUX_A4SERDES.SCIADDR4
CELL12.IMUX_A5SERDES.SCIADDR3
CELL12.IMUX_B0SERDES.SCIADDR2
CELL12.IMUX_B1SERDES.CIN0
CELL12.OUT_F0SERDES.SCIRDATA0
CELL12.OUT_F1SERDES.COUT17
CELL12.OUT_F3SERDES.REFCK2CORE
CELL12.OUT_F4SERDES.COUT19
CELL12.OUT_F5SERDES.COUT18
CELL12.OUT_F6SERDES.FF_TX_F_CLK
CELL12.OUT_F7SERDES.FF_TX_H_CLK
CELL13.IMUX_A0SERDES.SCIADDR1
CELL13.IMUX_A1SERDES.SCIADDR0
CELL13.IMUX_A2SERDES.SCIENAUX
CELL13.IMUX_A3SERDES.SCISELAUX
CELL13.IMUX_A4SERDES.SCIWSTN
CELL13.IMUX_A5SERDES.SCIWDATA7
CELL13.IMUX_B0SERDES.SCIWDATA6
CELL13.IMUX_B1SERDES.SCIRD
CELL13.IMUX_LSR0SERDES.FFC_MACRO_RST
CELL13.OUT_F0SERDES.COUT16
CELL13.OUT_F1SERDES.COUT9
CELL13.OUT_F2SERDES.COUT13
CELL13.OUT_F3SERDES.COUT12
CELL13.OUT_F4SERDES.COUT11
CELL13.OUT_F5SERDES.COUT10
CELL13.OUT_F6SERDES.COUT15
CELL13.OUT_F7SERDES.COUT14
CELL14.IMUX_A0SERDES.SCIWDATA5
CELL14.IMUX_A1SERDES.SCIWDATA4
CELL14.IMUX_A2SERDES.SCIWDATA3
CELL14.IMUX_A3SERDES.SCIWDATA1
CELL14.IMUX_A4SERDES.SCIWDATA0
CELL14.IMUX_A5SERDES.CYAWSTN
CELL14.IMUX_B1SERDES.SCIWDATA2
CELL14.IMUX_CLK0SERDES.FFC_CK_CORE_RX
CELL14.IMUX_LSR0SERDES.FFC_QUAD_RST
CELL14.OUT_F0SERDES.COUT8
CELL14.OUT_F1SERDES.COUT1
CELL14.OUT_F2SERDES.COUT5
CELL14.OUT_F3SERDES.COUT4
CELL14.OUT_F4SERDES.COUT3
CELL14.OUT_F5SERDES.COUT2
CELL14.OUT_F6SERDES.COUT7
CELL14.OUT_F7SERDES.COUT6
CELL15.IMUX_CLK0SERDES.FFC_CK_CORE_TX
CELL15.IMUX_LSR0SERDES.FFC_TRST
CELL15.OUT_F0SERDES.COUT0
CELL15.OUT_F6SERDES.FF_TX_Q_CLK
CELL15.OUT_F7SERDES.FFS_PLOL
CELL16.IMUX_A0SERDES.FFC_TXPWDNB_1
CELL16.IMUX_A1SERDES.FFC_RXPWDNB_1
CELL16.IMUX_A4SERDES.FFC_SB_INV_RX_1
CELL16.IMUX_A5SERDES.FFC_SB_PFIFO_LP_1
CELL16.IMUX_B0SERDES.FFC_PCI_DET_EN_1
CELL16.IMUX_CLK0SERDES.FF_EBRD_CLK_1
CELL16.IMUX_LSR0SERDES.FFC_LANE_RX_RST_1
CELL16.OUT_F0SERDES.FF_RX_D_1_23
CELL16.OUT_F1SERDES.FF_RX_D_1_16
CELL16.OUT_F2SERDES.FF_RX_D_1_20
CELL16.OUT_F3SERDES.FF_RX_D_1_19
CELL16.OUT_F4SERDES.FF_RX_D_1_18
CELL16.OUT_F5SERDES.FF_RX_D_1_17
CELL16.OUT_F6SERDES.FF_RX_D_1_22
CELL16.OUT_F7SERDES.FF_RX_D_1_21
CELL17.IMUX_A0SERDES.FFC_PCIE_CT_1
CELL17.IMUX_A1SERDES.FFC_PFIFO_CLR_1
CELL17.IMUX_A2SERDES.FFC_SIGNAL_DETECT_1
CELL17.IMUX_A3SERDES.SCISELCH1
CELL17.IMUX_A4SERDES.FFC_FB_LOOPBACK_1
CELL17.IMUX_A5SERDES.FFC_ENABLE_CGALIGN_1
CELL17.IMUX_B0SERDES.FFC_EI_EN_1
CELL17.IMUX_B1SERDES.SCIENCH1
CELL17.IMUX_CLK0SERDES.FF_RXI_CLK_1
CELL17.IMUX_LSR0SERDES.FFC_LANE_TX_RST_1
CELL17.OUT_F6SERDES.FF_RX_F_CLK_1
CELL17.OUT_F7SERDES.FF_RX_H_CLK_1
CELL18.IMUX_A0SERDES.FF_TX_D_1_23
CELL18.IMUX_A1SERDES.FF_TX_D_1_22
CELL18.IMUX_A2SERDES.FF_TX_D_1_21
CELL18.IMUX_A3SERDES.FF_TX_D_1_19
CELL18.IMUX_A4SERDES.FF_TX_D_1_18
CELL18.IMUX_A5SERDES.FF_TX_D_1_17
CELL18.IMUX_B0SERDES.FF_TX_D_1_16
CELL18.IMUX_B1SERDES.FF_TX_D_1_20
CELL18.IMUX_CLK0SERDES.FF_TXI_CLK_1
CELL18.IMUX_LSR0SERDES.FFC_RRST_1
CELL18.OUT_F0SERDES.FF_RX_D_1_15
CELL18.OUT_F1SERDES.FF_RX_D_1_8
CELL18.OUT_F2SERDES.FF_RX_D_1_12
CELL18.OUT_F3SERDES.FF_RX_D_1_11
CELL18.OUT_F4SERDES.FF_RX_D_1_10
CELL18.OUT_F5SERDES.FF_RX_D_1_9
CELL18.OUT_F6SERDES.FF_RX_D_1_14
CELL18.OUT_F7SERDES.FF_RX_D_1_13
CELL19.IMUX_A0SERDES.FF_TX_D_1_15
CELL19.IMUX_A1SERDES.FF_TX_D_1_14
CELL19.IMUX_A2SERDES.FF_TX_D_1_13
CELL19.IMUX_A3SERDES.FF_TX_D_1_11
CELL19.IMUX_A4SERDES.FF_TX_D_1_10
CELL19.IMUX_A5SERDES.FF_TX_D_1_9
CELL19.IMUX_B0SERDES.FF_TX_D_1_8
CELL19.IMUX_B1SERDES.FF_TX_D_1_12
CELL19.IMUX_LSR0SERDES.FFC_RRST_0
CELL19.OUT_F0SERDES.FF_RX_D_1_7
CELL19.OUT_F1SERDES.FF_RX_D_1_1
CELL19.OUT_F2SERDES.FF_RX_D_1_5
CELL19.OUT_F3SERDES.FF_RX_D_1_4
CELL19.OUT_F4SERDES.FF_RX_D_1_3
CELL19.OUT_F5SERDES.FF_RX_D_1_2
CELL19.OUT_F6SERDES.FF_RX_Q_CLK_1
CELL19.OUT_F7SERDES.FF_RX_D_1_6
CELL20.IMUX_A0SERDES.FF_TX_D_1_7
CELL20.IMUX_A1SERDES.FF_TX_D_1_6
CELL20.IMUX_A2SERDES.FF_TX_D_1_5
CELL20.IMUX_A3SERDES.FF_TX_D_1_3
CELL20.IMUX_A4SERDES.FF_TX_D_1_2
CELL20.IMUX_A5SERDES.FF_TX_D_1_1
CELL20.IMUX_B0SERDES.FF_TX_D_1_0
CELL20.IMUX_B1SERDES.FF_TX_D_1_4
CELL20.OUT_F0SERDES.FF_RX_D_1_0
CELL20.OUT_F1SERDES.OOB_OUT_1
CELL20.OUT_F2SERDES.FFS_LS_SYNC_STATUS_1
CELL20.OUT_F3SERDES.FFS_PCIE_CON_1
CELL20.OUT_F4SERDES.FFS_PCIE_DONE_1
CELL20.OUT_F5SERDES.FFS_RLOS_LO_1
CELL20.OUT_F6SERDES.FFS_CC_OVERRUN_1
CELL20.OUT_F7SERDES.FFS_CC_UNDERRUN_1
CELL21.OUT_F0SERDES.FFS_TXFBFIFO_ERROR_0
CELL21.OUT_F2SERDES.FFS_RXFBFIFO_ERROR_1
CELL21.OUT_F3SERDES.FFS_RLOL_1
CELL21.OUT_F4SERDES.FFS_TXFBFIFO_ERROR_1
CELL21.OUT_F5SERDES.FFS_RXFBFIFO_ERROR_0
CELL21.OUT_F6SERDES.FF_RX_Q_CLK_0
CELL21.OUT_F7SERDES.FFS_RLOL_0
CELL22.IMUX_A0SERDES.FF_TX_D_0_0
CELL22.IMUX_A1SERDES.FF_TX_D_0_1
CELL22.IMUX_A2SERDES.FF_TX_D_0_2
CELL22.IMUX_A3SERDES.FF_TX_D_0_4
CELL22.IMUX_A4SERDES.FF_TX_D_0_5
CELL22.IMUX_A5SERDES.FF_TX_D_0_6
CELL22.IMUX_B0SERDES.FF_TX_D_0_7
CELL22.IMUX_B1SERDES.FF_TX_D_0_3
CELL22.IMUX_CLK0SERDES.FF_TXI_CLK_0
CELL22.IMUX_LSR0SERDES.FFC_LANE_TX_RST_0
CELL22.OUT_F0SERDES.OOB_OUT_0
CELL22.OUT_F2SERDES.FFS_PCIE_CON_0
CELL22.OUT_F3SERDES.FFS_LS_SYNC_STATUS_0
CELL22.OUT_F4SERDES.FFS_CC_UNDERRUN_0
CELL22.OUT_F5SERDES.FFS_CC_OVERRUN_0
CELL22.OUT_F6SERDES.FFS_RLOS_LO_0
CELL22.OUT_F7SERDES.FFS_PCIE_DONE_0
CELL23.IMUX_A0SERDES.FF_TX_D_0_8
CELL23.IMUX_A1SERDES.FF_TX_D_0_9
CELL23.IMUX_A2SERDES.FF_TX_D_0_10
CELL23.IMUX_A3SERDES.FF_TX_D_0_12
CELL23.IMUX_A4SERDES.FF_TX_D_0_13
CELL23.IMUX_A5SERDES.FF_TX_D_0_14
CELL23.IMUX_B0SERDES.FF_TX_D_0_15
CELL23.IMUX_B1SERDES.FF_TX_D_0_11
CELL23.IMUX_CLK0SERDES.FF_RXI_CLK_0
CELL23.OUT_F1SERDES.FF_RX_D_0_2
CELL23.OUT_F4SERDES.FF_RX_D_0_0
CELL23.OUT_F5SERDES.FF_RX_D_0_1
CELL24.IMUX_A0SERDES.FF_TX_D_0_16
CELL24.IMUX_A1SERDES.FF_TX_D_0_17
CELL24.IMUX_A2SERDES.FF_TX_D_0_18
CELL24.IMUX_A3SERDES.FF_TX_D_0_20
CELL24.IMUX_A4SERDES.FF_TX_D_0_21
CELL24.IMUX_A5SERDES.FF_TX_D_0_22
CELL24.IMUX_B0SERDES.FF_TX_D_0_23
CELL24.IMUX_B1SERDES.FF_TX_D_0_19
CELL24.IMUX_CLK0SERDES.FF_EBRD_CLK_0
CELL24.OUT_F1SERDES.FF_RX_D_0_7
CELL24.OUT_F2SERDES.FF_RX_D_0_3
CELL24.OUT_F3SERDES.FF_RX_D_0_4
CELL24.OUT_F4SERDES.FF_RX_D_0_5
CELL24.OUT_F5SERDES.FF_RX_D_0_6
CELL24.OUT_F6SERDES.FF_RX_F_CLK_0
CELL24.OUT_F7SERDES.FF_RX_H_CLK_0
CELL25.IMUX_A0SERDES.FFC_EI_EN_0
CELL25.IMUX_A1SERDES.FFC_ENABLE_CGALIGN_0
CELL25.IMUX_A2SERDES.FFC_FB_LOOPBACK_0
CELL25.IMUX_A3SERDES.SCIENCH0
CELL25.IMUX_A4SERDES.FFC_SIGNAL_DETECT_0
CELL25.IMUX_A5SERDES.FFC_SB_PFIFO_LP_0
CELL25.IMUX_B0SERDES.FFC_PCIE_CT_0
CELL25.IMUX_B1SERDES.SCISELCH0
CELL25.OUT_F0SERDES.FF_RX_D_0_8
CELL25.OUT_F1SERDES.FF_RX_D_0_15
CELL25.OUT_F2SERDES.FF_RX_D_0_11
CELL25.OUT_F3SERDES.FF_RX_D_0_12
CELL25.OUT_F4SERDES.FF_RX_D_0_13
CELL25.OUT_F5SERDES.FF_RX_D_0_14
CELL25.OUT_F6SERDES.FF_RX_D_0_9
CELL25.OUT_F7SERDES.FF_RX_D_0_10
CELL26.IMUX_A0SERDES.FFC_PCI_DET_EN_0
CELL26.IMUX_A1SERDES.FFC_PFIFO_CLR_0
CELL26.IMUX_A2SERDES.FFC_SB_INV_RX_0
CELL26.IMUX_A3SERDES.FFC_RXPWDNB_0
CELL26.IMUX_B1SERDES.FFC_TXPWDNB_0
CELL26.IMUX_LSR0SERDES.FFC_LANE_RX_RST_0
CELL26.OUT_F0SERDES.FF_RX_D_0_16
CELL26.OUT_F1SERDES.FF_RX_D_0_23
CELL26.OUT_F2SERDES.FF_RX_D_0_19
CELL26.OUT_F3SERDES.FF_RX_D_0_20
CELL26.OUT_F4SERDES.FF_RX_D_0_21
CELL26.OUT_F5SERDES.FF_RX_D_0_22
CELL26.OUT_F6SERDES.FF_RX_D_0_17
CELL26.OUT_F7SERDES.FF_RX_D_0_18