Clock interconnect

Tile CLK_ROOT

Cells: 30

Bel DCC_SW0

ecp3 CLK_ROOT bel DCC_SW0
Pin	Direction	Wires
CE	input	TCELL11:IMUX_A2

Bel DCC_SW1

ecp3 CLK_ROOT bel DCC_SW1
Pin	Direction	Wires
CE	input	TCELL11:IMUX_B2

Bel DCC_SW2

ecp3 CLK_ROOT bel DCC_SW2
Pin	Direction	Wires
CE	input	TCELL11:IMUX_C2

Bel DCC_SW3

ecp3 CLK_ROOT bel DCC_SW3
Pin	Direction	Wires
CE	input	TCELL12:IMUX_A2

Bel DCC_SW4

ecp3 CLK_ROOT bel DCC_SW4
Pin	Direction	Wires
CE	input	TCELL12:IMUX_B2

Bel DCC_SW5

ecp3 CLK_ROOT bel DCC_SW5
Pin	Direction	Wires
CE	input	TCELL12:IMUX_C2

Bel DCC_SE0

ecp3 CLK_ROOT bel DCC_SE0
Pin	Direction	Wires
CE	input	TCELL11:IMUX_A3

Bel DCC_SE1

ecp3 CLK_ROOT bel DCC_SE1
Pin	Direction	Wires
CE	input	TCELL11:IMUX_B3

Bel DCC_SE2

ecp3 CLK_ROOT bel DCC_SE2
Pin	Direction	Wires
CE	input	TCELL11:IMUX_C3

Bel DCC_SE3

ecp3 CLK_ROOT bel DCC_SE3
Pin	Direction	Wires
CE	input	TCELL12:IMUX_A3

Bel DCC_SE4

ecp3 CLK_ROOT bel DCC_SE4
Pin	Direction	Wires
CE	input	TCELL12:IMUX_B3

Bel DCC_SE5

ecp3 CLK_ROOT bel DCC_SE5
Pin	Direction	Wires
CE	input	TCELL12:IMUX_C3

Bel DCC_NW0

ecp3 CLK_ROOT bel DCC_NW0
Pin	Direction	Wires
CE	input	TCELL11:IMUX_A0

Bel DCC_NW1

ecp3 CLK_ROOT bel DCC_NW1
Pin	Direction	Wires
CE	input	TCELL11:IMUX_B0

Bel DCC_NW2

ecp3 CLK_ROOT bel DCC_NW2
Pin	Direction	Wires
CE	input	TCELL11:IMUX_C0

Bel DCC_NW3

ecp3 CLK_ROOT bel DCC_NW3
Pin	Direction	Wires
CE	input	TCELL12:IMUX_A0

Bel DCC_NW4

ecp3 CLK_ROOT bel DCC_NW4
Pin	Direction	Wires
CE	input	TCELL12:IMUX_B0

Bel DCC_NW5

ecp3 CLK_ROOT bel DCC_NW5
Pin	Direction	Wires
CE	input	TCELL12:IMUX_C0

Bel DCC_NE0

ecp3 CLK_ROOT bel DCC_NE0
Pin	Direction	Wires
CE	input	TCELL11:IMUX_A1

Bel DCC_NE1

ecp3 CLK_ROOT bel DCC_NE1
Pin	Direction	Wires
CE	input	TCELL11:IMUX_B1

Bel DCC_NE2

ecp3 CLK_ROOT bel DCC_NE2
Pin	Direction	Wires
CE	input	TCELL11:IMUX_C1

Bel DCC_NE3

ecp3 CLK_ROOT bel DCC_NE3
Pin	Direction	Wires
CE	input	TCELL12:IMUX_A1

Bel DCC_NE4

ecp3 CLK_ROOT bel DCC_NE4
Pin	Direction	Wires
CE	input	TCELL12:IMUX_B1

Bel DCC_NE5

ecp3 CLK_ROOT bel DCC_NE5
Pin	Direction	Wires
CE	input	TCELL12:IMUX_C1

Bel DCS_SW0

ecp3 CLK_ROOT bel DCS_SW0
Pin	Direction	Wires
SEL	input	TCELL12:IMUX_D2

Bel DCS_SW1

ecp3 CLK_ROOT bel DCS_SW1
Pin	Direction	Wires
SEL	input	TCELL11:IMUX_D2

Bel DCS_SE0

ecp3 CLK_ROOT bel DCS_SE0
Pin	Direction	Wires
SEL	input	TCELL12:IMUX_D0

Bel DCS_SE1

ecp3 CLK_ROOT bel DCS_SE1
Pin	Direction	Wires
SEL	input	TCELL11:IMUX_D0

Bel DCS_NW0

ecp3 CLK_ROOT bel DCS_NW0
Pin	Direction	Wires
SEL	input	TCELL12:IMUX_D3

Bel DCS_NW1

ecp3 CLK_ROOT bel DCS_NW1
Pin	Direction	Wires
SEL	input	TCELL11:IMUX_D3

Bel DCS_NE0

ecp3 CLK_ROOT bel DCS_NE0
Pin	Direction	Wires
SEL	input	TCELL12:IMUX_D1

Bel DCS_NE1

ecp3 CLK_ROOT bel DCS_NE1
Pin	Direction	Wires
SEL	input	TCELL11:IMUX_D1

Bel CLK_ROOT

ecp3 CLK_ROOT bel CLK_ROOT
Pin	Direction	Wires
PCLK_IN_E0	input	TCELL2:IMUX_D5
PCLK_IN_E1	input	TCELL3:IMUX_D5
PCLK_IN_E2	input	TCELL4:IMUX_D5
PCLK_IN_E3	input	TCELL5:IMUX_D5
PCLK_IN_M0	input	TCELL10:IMUX_CLK0
PCLK_IN_M1	input	TCELL10:IMUX_CLK1
PCLK_IN_M2	input	TCELL11:IMUX_CLK0
PCLK_IN_M3	input	TCELL11:IMUX_CLK1
PCLK_IN_M4	input	TCELL12:IMUX_CLK0
PCLK_IN_M5	input	TCELL12:IMUX_CLK1
PCLK_IN_M6	input	TCELL13:IMUX_CLK0
PCLK_IN_M7	input	TCELL13:IMUX_CLK1
PCLK_IN_N0	input	TCELL8:IMUX_D5
PCLK_IN_N1	input	TCELL9:IMUX_D5
PCLK_IN_S0	input	TCELL6:IMUX_D5
PCLK_IN_S1	input	TCELL7:IMUX_D5
PCLK_IN_W0	input	TCELL0:IMUX_D5
PCLK_IN_W1	input	TCELL1:IMUX_D5
SCLK_IN_E0	input	TCELL18:IMUX_D5
SCLK_IN_E1	input	TCELL19:IMUX_D5
SCLK_IN_E2	input	TCELL20:IMUX_D5
SCLK_IN_E3	input	TCELL21:IMUX_D5
SCLK_IN_N0	input	TCELL26:IMUX_D5
SCLK_IN_N1	input	TCELL27:IMUX_D5
SCLK_IN_N2	input	TCELL28:IMUX_D5
SCLK_IN_N3	input	TCELL29:IMUX_D5
SCLK_IN_S0	input	TCELL22:IMUX_D5
SCLK_IN_S1	input	TCELL23:IMUX_D5
SCLK_IN_S2	input	TCELL24:IMUX_D5
SCLK_IN_S3	input	TCELL25:IMUX_D5
SCLK_IN_W0	input	TCELL14:IMUX_D5
SCLK_IN_W1	input	TCELL15:IMUX_D5
SCLK_IN_W2	input	TCELL16:IMUX_D5
SCLK_IN_W3	input	TCELL17:IMUX_D5

Bel wires

ecp3 CLK_ROOT bel wires
Wire	Pins
TCELL0:IMUX_D5	CLK_ROOT.PCLK_IN_W0
TCELL1:IMUX_D5	CLK_ROOT.PCLK_IN_W1
TCELL2:IMUX_D5	CLK_ROOT.PCLK_IN_E0
TCELL3:IMUX_D5	CLK_ROOT.PCLK_IN_E1
TCELL4:IMUX_D5	CLK_ROOT.PCLK_IN_E2
TCELL5:IMUX_D5	CLK_ROOT.PCLK_IN_E3
TCELL6:IMUX_D5	CLK_ROOT.PCLK_IN_S0
TCELL7:IMUX_D5	CLK_ROOT.PCLK_IN_S1
TCELL8:IMUX_D5	CLK_ROOT.PCLK_IN_N0
TCELL9:IMUX_D5	CLK_ROOT.PCLK_IN_N1
TCELL10:IMUX_CLK0	CLK_ROOT.PCLK_IN_M0
TCELL10:IMUX_CLK1	CLK_ROOT.PCLK_IN_M1
TCELL11:IMUX_A0	DCC_NW0.CE
TCELL11:IMUX_A1	DCC_NE0.CE
TCELL11:IMUX_A2	DCC_SW0.CE
TCELL11:IMUX_A3	DCC_SE0.CE
TCELL11:IMUX_B0	DCC_NW1.CE
TCELL11:IMUX_B1	DCC_NE1.CE
TCELL11:IMUX_B2	DCC_SW1.CE
TCELL11:IMUX_B3	DCC_SE1.CE
TCELL11:IMUX_C0	DCC_NW2.CE
TCELL11:IMUX_C1	DCC_NE2.CE
TCELL11:IMUX_C2	DCC_SW2.CE
TCELL11:IMUX_C3	DCC_SE2.CE
TCELL11:IMUX_D0	DCS_SE1.SEL
TCELL11:IMUX_D1	DCS_NE1.SEL
TCELL11:IMUX_D2	DCS_SW1.SEL
TCELL11:IMUX_D3	DCS_NW1.SEL
TCELL11:IMUX_CLK0	CLK_ROOT.PCLK_IN_M2
TCELL11:IMUX_CLK1	CLK_ROOT.PCLK_IN_M3
TCELL12:IMUX_A0	DCC_NW3.CE
TCELL12:IMUX_A1	DCC_NE3.CE
TCELL12:IMUX_A2	DCC_SW3.CE
TCELL12:IMUX_A3	DCC_SE3.CE
TCELL12:IMUX_B0	DCC_NW4.CE
TCELL12:IMUX_B1	DCC_NE4.CE
TCELL12:IMUX_B2	DCC_SW4.CE
TCELL12:IMUX_B3	DCC_SE4.CE
TCELL12:IMUX_C0	DCC_NW5.CE
TCELL12:IMUX_C1	DCC_NE5.CE
TCELL12:IMUX_C2	DCC_SW5.CE
TCELL12:IMUX_C3	DCC_SE5.CE
TCELL12:IMUX_D0	DCS_SE0.SEL
TCELL12:IMUX_D1	DCS_NE0.SEL
TCELL12:IMUX_D2	DCS_SW0.SEL
TCELL12:IMUX_D3	DCS_NW0.SEL
TCELL12:IMUX_CLK0	CLK_ROOT.PCLK_IN_M4
TCELL12:IMUX_CLK1	CLK_ROOT.PCLK_IN_M5
TCELL13:IMUX_CLK0	CLK_ROOT.PCLK_IN_M6
TCELL13:IMUX_CLK1	CLK_ROOT.PCLK_IN_M7
TCELL14:IMUX_D5	CLK_ROOT.SCLK_IN_W0
TCELL15:IMUX_D5	CLK_ROOT.SCLK_IN_W1
TCELL16:IMUX_D5	CLK_ROOT.SCLK_IN_W2
TCELL17:IMUX_D5	CLK_ROOT.SCLK_IN_W3
TCELL18:IMUX_D5	CLK_ROOT.SCLK_IN_E0
TCELL19:IMUX_D5	CLK_ROOT.SCLK_IN_E1
TCELL20:IMUX_D5	CLK_ROOT.SCLK_IN_E2
TCELL21:IMUX_D5	CLK_ROOT.SCLK_IN_E3
TCELL22:IMUX_D5	CLK_ROOT.SCLK_IN_S0
TCELL23:IMUX_D5	CLK_ROOT.SCLK_IN_S1
TCELL24:IMUX_D5	CLK_ROOT.SCLK_IN_S2
TCELL25:IMUX_D5	CLK_ROOT.SCLK_IN_S3
TCELL26:IMUX_D5	CLK_ROOT.SCLK_IN_N0
TCELL27:IMUX_D5	CLK_ROOT.SCLK_IN_N1
TCELL28:IMUX_D5	CLK_ROOT.SCLK_IN_N2
TCELL29:IMUX_D5	CLK_ROOT.SCLK_IN_N3

Tile ECLK_ROOT_W

Cells: 1

Bel ECLKSYNC0

ecp3 ECLK_ROOT_W bel ECLKSYNC0
Pin	Direction	Wires
ECLKI	input	IMUX_B4
STOP	input	IMUX_B5

Bel ECLKSYNC1

ecp3 ECLK_ROOT_W bel ECLKSYNC1
Pin	Direction	Wires
ECLKI	input	IMUX_C4
STOP	input	IMUX_C5

Bel wires

ecp3 ECLK_ROOT_W bel wires
Wire	Pins
IMUX_B4	ECLKSYNC0.ECLKI
IMUX_B5	ECLKSYNC0.STOP
IMUX_C4	ECLKSYNC1.ECLKI
IMUX_C5	ECLKSYNC1.STOP

Tile ECLK_ROOT_E

Cells: 1

Bel ECLKSYNC0

ecp3 ECLK_ROOT_E bel ECLKSYNC0
Pin	Direction	Wires
ECLKI	input	IMUX_B4
STOP	input	IMUX_B5

Bel ECLKSYNC1

ecp3 ECLK_ROOT_E bel ECLKSYNC1
Pin	Direction	Wires
ECLKI	input	IMUX_C4
STOP	input	IMUX_C5

Bel wires

ecp3 ECLK_ROOT_E bel wires
Wire	Pins
IMUX_B4	ECLKSYNC0.ECLKI
IMUX_B5	ECLKSYNC0.STOP
IMUX_C4	ECLKSYNC1.ECLKI
IMUX_C5	ECLKSYNC1.STOP

Tile ECLK_ROOT_N

Cells: 1

Bel ECLKSYNC0

ecp3 ECLK_ROOT_N bel ECLKSYNC0
Pin	Direction	Wires
ECLKI	input	IMUX_B4
STOP	input	IMUX_B5

Bel ECLKSYNC1

ecp3 ECLK_ROOT_N bel ECLKSYNC1
Pin	Direction	Wires
ECLKI	input	IMUX_C4
STOP	input	IMUX_C5

Bel wires

ecp3 ECLK_ROOT_N bel wires
Wire	Pins
IMUX_B4	ECLKSYNC0.ECLKI
IMUX_B5	ECLKSYNC0.STOP
IMUX_C4	ECLKSYNC1.ECLKI
IMUX_C5	ECLKSYNC1.STOP

Tile ECLK_TAP

Cells: 1

Bel ECLK_TAP

ecp3 ECLK_TAP bel ECLK_TAP
Pin	Direction	Wires
ECLK0	output	OUT_F6
ECLK1	output	OUT_F7

Bel wires

ecp3 ECLK_TAP bel wires
Wire	Pins
OUT_F6	ECLK_TAP.ECLK0
OUT_F7	ECLK_TAP.ECLK1

Tile HSDCLK_ROOT

Cells: 8

Bel HSDCLK_ROOT

ecp3 HSDCLK_ROOT bel HSDCLK_ROOT
Pin	Direction	Wires
OUT_E0	output	TCELL4:HSDCLK0
OUT_E1	output	TCELL5:HSDCLK0
OUT_E2	output	TCELL6:HSDCLK0
OUT_E3	output	TCELL7:HSDCLK0
OUT_E4	output	TCELL4:HSDCLK4
OUT_E5	output	TCELL5:HSDCLK4
OUT_E6	output	TCELL6:HSDCLK4
OUT_E7	output	TCELL7:HSDCLK4
OUT_W0	output	TCELL0:HSDCLK0
OUT_W1	output	TCELL1:HSDCLK0
OUT_W2	output	TCELL2:HSDCLK0
OUT_W3	output	TCELL3:HSDCLK0
OUT_W4	output	TCELL0:HSDCLK4
OUT_W5	output	TCELL1:HSDCLK4
OUT_W6	output	TCELL2:HSDCLK4
OUT_W7	output	TCELL3:HSDCLK4

Switchbox HSDCLK_SPLITTER

ecp3 HSDCLK_ROOT switchbox HSDCLK_SPLITTER
Destination	Source	Kind
TCELL0_HSDCLK0	TCELL4_HSDCLK0	buffer
TCELL0_HSDCLK4	TCELL4_HSDCLK4	buffer
TCELL1_HSDCLK0	TCELL5_HSDCLK0	buffer
TCELL1_HSDCLK4	TCELL5_HSDCLK4	buffer
TCELL2_HSDCLK0	TCELL6_HSDCLK0	buffer
TCELL2_HSDCLK4	TCELL6_HSDCLK4	buffer
TCELL3_HSDCLK0	TCELL7_HSDCLK0	buffer
TCELL3_HSDCLK4	TCELL7_HSDCLK4	buffer
TCELL4_HSDCLK0	TCELL0_HSDCLK0	buffer
TCELL4_HSDCLK4	TCELL0_HSDCLK4	buffer
TCELL5_HSDCLK0	TCELL1_HSDCLK0	buffer
TCELL5_HSDCLK4	TCELL1_HSDCLK4	buffer
TCELL6_HSDCLK0	TCELL2_HSDCLK0	buffer
TCELL6_HSDCLK4	TCELL2_HSDCLK4	buffer
TCELL7_HSDCLK0	TCELL3_HSDCLK0	buffer
TCELL7_HSDCLK4	TCELL3_HSDCLK4	buffer

Bel wires

ecp3 HSDCLK_ROOT bel wires
Wire	Pins
TCELL0:HSDCLK0	HSDCLK_ROOT.OUT_W0
TCELL0:HSDCLK4	HSDCLK_ROOT.OUT_W4
TCELL1:HSDCLK0	HSDCLK_ROOT.OUT_W1
TCELL1:HSDCLK4	HSDCLK_ROOT.OUT_W5
TCELL2:HSDCLK0	HSDCLK_ROOT.OUT_W2
TCELL2:HSDCLK4	HSDCLK_ROOT.OUT_W6
TCELL3:HSDCLK0	HSDCLK_ROOT.OUT_W3
TCELL3:HSDCLK4	HSDCLK_ROOT.OUT_W7
TCELL4:HSDCLK0	HSDCLK_ROOT.OUT_E0
TCELL4:HSDCLK4	HSDCLK_ROOT.OUT_E4
TCELL5:HSDCLK0	HSDCLK_ROOT.OUT_E1
TCELL5:HSDCLK4	HSDCLK_ROOT.OUT_E5
TCELL6:HSDCLK0	HSDCLK_ROOT.OUT_E2
TCELL6:HSDCLK4	HSDCLK_ROOT.OUT_E6
TCELL7:HSDCLK0	HSDCLK_ROOT.OUT_E3
TCELL7:HSDCLK4	HSDCLK_ROOT.OUT_E7

Tile HSDCLK_SPLITTER

Cells: 8

Switchbox HSDCLK_SPLITTER

ecp3 HSDCLK_SPLITTER switchbox HSDCLK_SPLITTER
Destination	Source	Kind
TCELL0_HSDCLK0	TCELL4_HSDCLK0	buffer
TCELL0_HSDCLK4	TCELL4_HSDCLK4	buffer
TCELL1_HSDCLK0	TCELL5_HSDCLK0	buffer
TCELL1_HSDCLK4	TCELL5_HSDCLK4	buffer
TCELL2_HSDCLK0	TCELL6_HSDCLK0	buffer
TCELL2_HSDCLK4	TCELL6_HSDCLK4	buffer
TCELL3_HSDCLK0	TCELL7_HSDCLK0	buffer
TCELL3_HSDCLK4	TCELL7_HSDCLK4	buffer
TCELL4_HSDCLK0	TCELL0_HSDCLK0	buffer
TCELL4_HSDCLK4	TCELL0_HSDCLK4	buffer
TCELL5_HSDCLK0	TCELL1_HSDCLK0	buffer
TCELL5_HSDCLK4	TCELL1_HSDCLK4	buffer
TCELL6_HSDCLK0	TCELL2_HSDCLK0	buffer
TCELL6_HSDCLK4	TCELL2_HSDCLK4	buffer
TCELL7_HSDCLK0	TCELL3_HSDCLK0	buffer
TCELL7_HSDCLK4	TCELL3_HSDCLK4	buffer

Tile PCLK0_SOURCE

Cells: 2

Bel PCLK_DCC0

ecp3 PCLK0_SOURCE bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK0
OUT_S	output	TCELL1:PCLK0

Bel PCLK_DCC1

ecp3 PCLK0_SOURCE bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK4
OUT_S	output	TCELL1:PCLK4

Bel wires

ecp3 PCLK0_SOURCE bel wires
Wire	Pins
TCELL0:PCLK0	PCLK_DCC0.OUT_N
TCELL0:PCLK4	PCLK_DCC1.OUT_N
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK0	PCLK_DCC0.OUT_S
TCELL1:PCLK4	PCLK_DCC1.OUT_S

Tile PCLK1_SOURCE

Cells: 2

Bel PCLK_DCC0

ecp3 PCLK1_SOURCE bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK1
OUT_S	output	TCELL1:PCLK1

Bel PCLK_DCC1

ecp3 PCLK1_SOURCE bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK5
OUT_S	output	TCELL1:PCLK5

Bel wires

ecp3 PCLK1_SOURCE bel wires
Wire	Pins
TCELL0:PCLK1	PCLK_DCC0.OUT_N
TCELL0:PCLK5	PCLK_DCC1.OUT_N
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK1	PCLK_DCC0.OUT_S
TCELL1:PCLK5	PCLK_DCC1.OUT_S

Tile PCLK2_SOURCE

Cells: 2

Bel PCLK_DCC0

ecp3 PCLK2_SOURCE bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK2
OUT_S	output	TCELL1:PCLK2

Bel PCLK_DCC1

ecp3 PCLK2_SOURCE bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK6
OUT_S	output	TCELL1:PCLK6

Bel wires

ecp3 PCLK2_SOURCE bel wires
Wire	Pins
TCELL0:PCLK2	PCLK_DCC0.OUT_N
TCELL0:PCLK6	PCLK_DCC1.OUT_N
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK2	PCLK_DCC0.OUT_S
TCELL1:PCLK6	PCLK_DCC1.OUT_S

Tile PCLK3_SOURCE

Cells: 2

Bel PCLK_DCC0

ecp3 PCLK3_SOURCE bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK3
OUT_S	output	TCELL1:PCLK3

Bel PCLK_DCC1

ecp3 PCLK3_SOURCE bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK7
OUT_S	output	TCELL1:PCLK7

Bel wires

ecp3 PCLK3_SOURCE bel wires
Wire	Pins
TCELL0:PCLK3	PCLK_DCC0.OUT_N
TCELL0:PCLK7	PCLK_DCC1.OUT_N
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK3	PCLK_DCC0.OUT_S
TCELL1:PCLK7	PCLK_DCC1.OUT_S

Tile PCLK0_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

ecp3 PCLK0_SOURCE_W bel PCLK_SOURCE_W
Pin	Direction	Wires
OUT_N2	output	TCELL0:PCLK2
OUT_N3	output	TCELL0:PCLK3
OUT_N6	output	TCELL0:PCLK6
OUT_N7	output	TCELL0:PCLK7
OUT_S2	output	TCELL1:PCLK2
OUT_S3	output	TCELL1:PCLK3
OUT_S6	output	TCELL1:PCLK6
OUT_S7	output	TCELL1:PCLK7

Bel PCLK_DCC0

ecp3 PCLK0_SOURCE_W bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK0
OUT_S	output	TCELL1:PCLK0

Bel PCLK_DCC1

ecp3 PCLK0_SOURCE_W bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK4
OUT_S	output	TCELL1:PCLK4

Bel wires

ecp3 PCLK0_SOURCE_W bel wires
Wire	Pins
TCELL0:PCLK0	PCLK_DCC0.OUT_N
TCELL0:PCLK2	PCLK_SOURCE_W.OUT_N2
TCELL0:PCLK3	PCLK_SOURCE_W.OUT_N3
TCELL0:PCLK4	PCLK_DCC1.OUT_N
TCELL0:PCLK6	PCLK_SOURCE_W.OUT_N6
TCELL0:PCLK7	PCLK_SOURCE_W.OUT_N7
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK0	PCLK_DCC0.OUT_S
TCELL1:PCLK2	PCLK_SOURCE_W.OUT_S2
TCELL1:PCLK3	PCLK_SOURCE_W.OUT_S3
TCELL1:PCLK4	PCLK_DCC1.OUT_S
TCELL1:PCLK6	PCLK_SOURCE_W.OUT_S6
TCELL1:PCLK7	PCLK_SOURCE_W.OUT_S7

Tile PCLK1_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

ecp3 PCLK1_SOURCE_W bel PCLK_SOURCE_W
Pin	Direction	Wires
OUT_N0	output	TCELL0:PCLK0
OUT_N3	output	TCELL0:PCLK3
OUT_N4	output	TCELL0:PCLK4
OUT_N7	output	TCELL0:PCLK7
OUT_S0	output	TCELL1:PCLK0
OUT_S3	output	TCELL1:PCLK3
OUT_S4	output	TCELL1:PCLK4
OUT_S7	output	TCELL1:PCLK7

Bel PCLK_DCC0

ecp3 PCLK1_SOURCE_W bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK1
OUT_S	output	TCELL1:PCLK1

Bel PCLK_DCC1

ecp3 PCLK1_SOURCE_W bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK5
OUT_S	output	TCELL1:PCLK5

Bel wires

ecp3 PCLK1_SOURCE_W bel wires
Wire	Pins
TCELL0:PCLK0	PCLK_SOURCE_W.OUT_N0
TCELL0:PCLK1	PCLK_DCC0.OUT_N
TCELL0:PCLK3	PCLK_SOURCE_W.OUT_N3
TCELL0:PCLK4	PCLK_SOURCE_W.OUT_N4
TCELL0:PCLK5	PCLK_DCC1.OUT_N
TCELL0:PCLK7	PCLK_SOURCE_W.OUT_N7
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK0	PCLK_SOURCE_W.OUT_S0
TCELL1:PCLK1	PCLK_DCC0.OUT_S
TCELL1:PCLK3	PCLK_SOURCE_W.OUT_S3
TCELL1:PCLK4	PCLK_SOURCE_W.OUT_S4
TCELL1:PCLK5	PCLK_DCC1.OUT_S
TCELL1:PCLK7	PCLK_SOURCE_W.OUT_S7

Tile PCLK3_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

ecp3 PCLK3_SOURCE_W bel PCLK_SOURCE_W
Pin	Direction	Wires
OUT_N1	output	TCELL0:PCLK1
OUT_N2	output	TCELL0:PCLK2
OUT_N5	output	TCELL0:PCLK5
OUT_N6	output	TCELL0:PCLK6
OUT_S1	output	TCELL1:PCLK1
OUT_S2	output	TCELL1:PCLK2
OUT_S5	output	TCELL1:PCLK5
OUT_S6	output	TCELL1:PCLK6

Bel PCLK_DCC0

ecp3 PCLK3_SOURCE_W bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK3
OUT_S	output	TCELL1:PCLK3

Bel PCLK_DCC1

ecp3 PCLK3_SOURCE_W bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK7
OUT_S	output	TCELL1:PCLK7

Bel wires

ecp3 PCLK3_SOURCE_W bel wires
Wire	Pins
TCELL0:PCLK1	PCLK_SOURCE_W.OUT_N1
TCELL0:PCLK2	PCLK_SOURCE_W.OUT_N2
TCELL0:PCLK3	PCLK_DCC0.OUT_N
TCELL0:PCLK5	PCLK_SOURCE_W.OUT_N5
TCELL0:PCLK6	PCLK_SOURCE_W.OUT_N6
TCELL0:PCLK7	PCLK_DCC1.OUT_N
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK1	PCLK_SOURCE_W.OUT_S1
TCELL1:PCLK2	PCLK_SOURCE_W.OUT_S2
TCELL1:PCLK3	PCLK_DCC0.OUT_S
TCELL1:PCLK5	PCLK_SOURCE_W.OUT_S5
TCELL1:PCLK6	PCLK_SOURCE_W.OUT_S6
TCELL1:PCLK7	PCLK_DCC1.OUT_S

Tile PCLK0_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

ecp3 PCLK0_SOURCE_E bel PCLK_SOURCE_E
Pin	Direction	Wires
OUT_N1	output	TCELL0:PCLK1
OUT_N5	output	TCELL0:PCLK5
OUT_S1	output	TCELL1:PCLK1
OUT_S5	output	TCELL1:PCLK5

Bel PCLK_DCC0

ecp3 PCLK0_SOURCE_E bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK0
OUT_S	output	TCELL1:PCLK0

Bel PCLK_DCC1

ecp3 PCLK0_SOURCE_E bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK4
OUT_S	output	TCELL1:PCLK4

Bel wires

ecp3 PCLK0_SOURCE_E bel wires
Wire	Pins
TCELL0:PCLK0	PCLK_DCC0.OUT_N
TCELL0:PCLK1	PCLK_SOURCE_E.OUT_N1
TCELL0:PCLK4	PCLK_DCC1.OUT_N
TCELL0:PCLK5	PCLK_SOURCE_E.OUT_N5
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK0	PCLK_DCC0.OUT_S
TCELL1:PCLK1	PCLK_SOURCE_E.OUT_S1
TCELL1:PCLK4	PCLK_DCC1.OUT_S
TCELL1:PCLK5	PCLK_SOURCE_E.OUT_S5

Tile PCLK2_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

ecp3 PCLK2_SOURCE_E bel PCLK_SOURCE_E
Pin	Direction	Wires
OUT_N3	output	TCELL0:PCLK3
OUT_N7	output	TCELL0:PCLK7
OUT_S3	output	TCELL1:PCLK3
OUT_S7	output	TCELL1:PCLK7

Bel PCLK_DCC0

ecp3 PCLK2_SOURCE_E bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK2
OUT_S	output	TCELL1:PCLK2

Bel PCLK_DCC1

ecp3 PCLK2_SOURCE_E bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK6
OUT_S	output	TCELL1:PCLK6

Bel wires

ecp3 PCLK2_SOURCE_E bel wires
Wire	Pins
TCELL0:PCLK2	PCLK_DCC0.OUT_N
TCELL0:PCLK3	PCLK_SOURCE_E.OUT_N3
TCELL0:PCLK6	PCLK_DCC1.OUT_N
TCELL0:PCLK7	PCLK_SOURCE_E.OUT_N7
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK2	PCLK_DCC0.OUT_S
TCELL1:PCLK3	PCLK_SOURCE_E.OUT_S3
TCELL1:PCLK6	PCLK_DCC1.OUT_S
TCELL1:PCLK7	PCLK_SOURCE_E.OUT_S7

Tile PCLK3_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

ecp3 PCLK3_SOURCE_E bel PCLK_SOURCE_E
Pin	Direction	Wires
OUT_N0	output	TCELL0:PCLK0
OUT_N4	output	TCELL0:PCLK4
OUT_S0	output	TCELL1:PCLK0
OUT_S4	output	TCELL1:PCLK4

Bel PCLK_DCC0

ecp3 PCLK3_SOURCE_E bel PCLK_DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D6
OUT_N	output	TCELL0:PCLK3
OUT_S	output	TCELL1:PCLK3

Bel PCLK_DCC1

ecp3 PCLK3_SOURCE_E bel PCLK_DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_D7
OUT_N	output	TCELL0:PCLK7
OUT_S	output	TCELL1:PCLK7

Bel wires

ecp3 PCLK3_SOURCE_E bel wires
Wire	Pins
TCELL0:PCLK0	PCLK_SOURCE_E.OUT_N0
TCELL0:PCLK3	PCLK_DCC0.OUT_N
TCELL0:PCLK4	PCLK_SOURCE_E.OUT_N4
TCELL0:PCLK7	PCLK_DCC1.OUT_N
TCELL0:IMUX_D6	PCLK_DCC0.CE
TCELL0:IMUX_D7	PCLK_DCC1.CE
TCELL1:PCLK0	PCLK_SOURCE_E.OUT_S0
TCELL1:PCLK3	PCLK_DCC0.OUT_S
TCELL1:PCLK4	PCLK_SOURCE_E.OUT_S4
TCELL1:PCLK7	PCLK_DCC1.OUT_S

Tile SCLK0_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK0_SOURCE switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK0	fixed buffer
SCLK4	VSDCLK1	fixed buffer

Tile SCLK1_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK1_SOURCE switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK1	VSDCLK0	fixed buffer
SCLK5	VSDCLK1	fixed buffer

Tile SCLK2_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK2_SOURCE switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK2	VSDCLK0	fixed buffer
SCLK6	VSDCLK1	fixed buffer

Tile SCLK3_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK3_SOURCE switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK3	VSDCLK0	fixed buffer
SCLK7	VSDCLK1	fixed buffer

Tile SCLK0_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK0_SOURCE_W switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK0	fixed buffer
SCLK2	VSDCLK4	fixed buffer
SCLK3	VSDCLK6	fixed buffer
SCLK4	VSDCLK1	fixed buffer
SCLK6	VSDCLK5	fixed buffer
SCLK7	VSDCLK7	fixed buffer

Tile SCLK1_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK1_SOURCE_W switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK6	fixed buffer
SCLK1	VSDCLK0	fixed buffer
SCLK3	VSDCLK4	fixed buffer
SCLK4	VSDCLK7	fixed buffer
SCLK5	VSDCLK1	fixed buffer
SCLK7	VSDCLK5	fixed buffer

Tile SCLK3_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK3_SOURCE_W switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK1	VSDCLK4	fixed buffer
SCLK2	VSDCLK6	fixed buffer
SCLK3	VSDCLK0	fixed buffer
SCLK5	VSDCLK5	fixed buffer
SCLK6	VSDCLK7	fixed buffer
SCLK7	VSDCLK1	fixed buffer

Tile SCLK0_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK0_SOURCE_E switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK0	fixed buffer
SCLK1	VSDCLK2	fixed buffer
SCLK4	VSDCLK1	fixed buffer
SCLK5	VSDCLK3	fixed buffer

Tile SCLK2_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK2_SOURCE_E switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK2	VSDCLK0	fixed buffer
SCLK3	VSDCLK2	fixed buffer
SCLK6	VSDCLK1	fixed buffer
SCLK7	VSDCLK3	fixed buffer

Tile SCLK3_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK3_SOURCE_E switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK2	fixed buffer
SCLK3	VSDCLK0	fixed buffer
SCLK4	VSDCLK3	fixed buffer
SCLK7	VSDCLK1	fixed buffer