Clock interconnect

Tile CLK_ROOT

Cells: 30

Bel DCC_SW0

ecp3 CLK_ROOT bel DCC_SW0
Pin	Direction	Wires
CE	input	CELL11.IMUX_A2

Bel DCC_SW1

ecp3 CLK_ROOT bel DCC_SW1
Pin	Direction	Wires
CE	input	CELL11.IMUX_B2

Bel DCC_SW2

ecp3 CLK_ROOT bel DCC_SW2
Pin	Direction	Wires
CE	input	CELL11.IMUX_C2

Bel DCC_SW3

ecp3 CLK_ROOT bel DCC_SW3
Pin	Direction	Wires
CE	input	CELL12.IMUX_A2

Bel DCC_SW4

ecp3 CLK_ROOT bel DCC_SW4
Pin	Direction	Wires
CE	input	CELL12.IMUX_B2

Bel DCC_SW5

ecp3 CLK_ROOT bel DCC_SW5
Pin	Direction	Wires
CE	input	CELL12.IMUX_C2

Bel DCC_SE0

ecp3 CLK_ROOT bel DCC_SE0
Pin	Direction	Wires
CE	input	CELL11.IMUX_A3

Bel DCC_SE1

ecp3 CLK_ROOT bel DCC_SE1
Pin	Direction	Wires
CE	input	CELL11.IMUX_B3

Bel DCC_SE2

ecp3 CLK_ROOT bel DCC_SE2
Pin	Direction	Wires
CE	input	CELL11.IMUX_C3

Bel DCC_SE3

ecp3 CLK_ROOT bel DCC_SE3
Pin	Direction	Wires
CE	input	CELL12.IMUX_A3

Bel DCC_SE4

ecp3 CLK_ROOT bel DCC_SE4
Pin	Direction	Wires
CE	input	CELL12.IMUX_B3

Bel DCC_SE5

ecp3 CLK_ROOT bel DCC_SE5
Pin	Direction	Wires
CE	input	CELL12.IMUX_C3

Bel DCC_NW0

ecp3 CLK_ROOT bel DCC_NW0
Pin	Direction	Wires
CE	input	CELL11.IMUX_A0

Bel DCC_NW1

ecp3 CLK_ROOT bel DCC_NW1
Pin	Direction	Wires
CE	input	CELL11.IMUX_B0

Bel DCC_NW2

ecp3 CLK_ROOT bel DCC_NW2
Pin	Direction	Wires
CE	input	CELL11.IMUX_C0

Bel DCC_NW3

ecp3 CLK_ROOT bel DCC_NW3
Pin	Direction	Wires
CE	input	CELL12.IMUX_A0

Bel DCC_NW4

ecp3 CLK_ROOT bel DCC_NW4
Pin	Direction	Wires
CE	input	CELL12.IMUX_B0

Bel DCC_NW5

ecp3 CLK_ROOT bel DCC_NW5
Pin	Direction	Wires
CE	input	CELL12.IMUX_C0

Bel DCC_NE0

ecp3 CLK_ROOT bel DCC_NE0
Pin	Direction	Wires
CE	input	CELL11.IMUX_A1

Bel DCC_NE1

ecp3 CLK_ROOT bel DCC_NE1
Pin	Direction	Wires
CE	input	CELL11.IMUX_B1

Bel DCC_NE2

ecp3 CLK_ROOT bel DCC_NE2
Pin	Direction	Wires
CE	input	CELL11.IMUX_C1

Bel DCC_NE3

ecp3 CLK_ROOT bel DCC_NE3
Pin	Direction	Wires
CE	input	CELL12.IMUX_A1

Bel DCC_NE4

ecp3 CLK_ROOT bel DCC_NE4
Pin	Direction	Wires
CE	input	CELL12.IMUX_B1

Bel DCC_NE5

ecp3 CLK_ROOT bel DCC_NE5
Pin	Direction	Wires
CE	input	CELL12.IMUX_C1

Bel DCS_SW0

ecp3 CLK_ROOT bel DCS_SW0
Pin	Direction	Wires
SEL	input	CELL12.IMUX_D2

Bel DCS_SW1

ecp3 CLK_ROOT bel DCS_SW1
Pin	Direction	Wires
SEL	input	CELL11.IMUX_D2

Bel DCS_SE0

ecp3 CLK_ROOT bel DCS_SE0
Pin	Direction	Wires
SEL	input	CELL12.IMUX_D0

Bel DCS_SE1

ecp3 CLK_ROOT bel DCS_SE1
Pin	Direction	Wires
SEL	input	CELL11.IMUX_D0

Bel DCS_NW0

ecp3 CLK_ROOT bel DCS_NW0
Pin	Direction	Wires
SEL	input	CELL12.IMUX_D3

Bel DCS_NW1

ecp3 CLK_ROOT bel DCS_NW1
Pin	Direction	Wires
SEL	input	CELL11.IMUX_D3

Bel DCS_NE0

ecp3 CLK_ROOT bel DCS_NE0
Pin	Direction	Wires
SEL	input	CELL12.IMUX_D1

Bel DCS_NE1

ecp3 CLK_ROOT bel DCS_NE1
Pin	Direction	Wires
SEL	input	CELL11.IMUX_D1

Bel CLK_ROOT

ecp3 CLK_ROOT bel CLK_ROOT
Pin	Direction	Wires
PCLK_IN_E0	input	CELL2.IMUX_D5
PCLK_IN_E1	input	CELL3.IMUX_D5
PCLK_IN_E2	input	CELL4.IMUX_D5
PCLK_IN_E3	input	CELL5.IMUX_D5
PCLK_IN_M0	input	CELL10.IMUX_CLK0
PCLK_IN_M1	input	CELL10.IMUX_CLK1
PCLK_IN_M2	input	CELL11.IMUX_CLK0
PCLK_IN_M3	input	CELL11.IMUX_CLK1
PCLK_IN_M4	input	CELL12.IMUX_CLK0
PCLK_IN_M5	input	CELL12.IMUX_CLK1
PCLK_IN_M6	input	CELL13.IMUX_CLK0
PCLK_IN_M7	input	CELL13.IMUX_CLK1
PCLK_IN_N0	input	CELL8.IMUX_D5
PCLK_IN_N1	input	CELL9.IMUX_D5
PCLK_IN_S0	input	CELL6.IMUX_D5
PCLK_IN_S1	input	CELL7.IMUX_D5
PCLK_IN_W0	input	CELL0.IMUX_D5
PCLK_IN_W1	input	CELL1.IMUX_D5
SCLK_IN_E0	input	CELL18.IMUX_D5
SCLK_IN_E1	input	CELL19.IMUX_D5
SCLK_IN_E2	input	CELL20.IMUX_D5
SCLK_IN_E3	input	CELL21.IMUX_D5
SCLK_IN_N0	input	CELL26.IMUX_D5
SCLK_IN_N1	input	CELL27.IMUX_D5
SCLK_IN_N2	input	CELL28.IMUX_D5
SCLK_IN_N3	input	CELL29.IMUX_D5
SCLK_IN_S0	input	CELL22.IMUX_D5
SCLK_IN_S1	input	CELL23.IMUX_D5
SCLK_IN_S2	input	CELL24.IMUX_D5
SCLK_IN_S3	input	CELL25.IMUX_D5
SCLK_IN_W0	input	CELL14.IMUX_D5
SCLK_IN_W1	input	CELL15.IMUX_D5
SCLK_IN_W2	input	CELL16.IMUX_D5
SCLK_IN_W3	input	CELL17.IMUX_D5

Bel wires

ecp3 CLK_ROOT bel wires
Wire	Pins
CELL0.IMUX_D5	CLK_ROOT.PCLK_IN_W0
CELL1.IMUX_D5	CLK_ROOT.PCLK_IN_W1
CELL2.IMUX_D5	CLK_ROOT.PCLK_IN_E0
CELL3.IMUX_D5	CLK_ROOT.PCLK_IN_E1
CELL4.IMUX_D5	CLK_ROOT.PCLK_IN_E2
CELL5.IMUX_D5	CLK_ROOT.PCLK_IN_E3
CELL6.IMUX_D5	CLK_ROOT.PCLK_IN_S0
CELL7.IMUX_D5	CLK_ROOT.PCLK_IN_S1
CELL8.IMUX_D5	CLK_ROOT.PCLK_IN_N0
CELL9.IMUX_D5	CLK_ROOT.PCLK_IN_N1
CELL10.IMUX_CLK0	CLK_ROOT.PCLK_IN_M0
CELL10.IMUX_CLK1	CLK_ROOT.PCLK_IN_M1
CELL11.IMUX_A0	DCC_NW0.CE
CELL11.IMUX_A1	DCC_NE0.CE
CELL11.IMUX_A2	DCC_SW0.CE
CELL11.IMUX_A3	DCC_SE0.CE
CELL11.IMUX_B0	DCC_NW1.CE
CELL11.IMUX_B1	DCC_NE1.CE
CELL11.IMUX_B2	DCC_SW1.CE
CELL11.IMUX_B3	DCC_SE1.CE
CELL11.IMUX_C0	DCC_NW2.CE
CELL11.IMUX_C1	DCC_NE2.CE
CELL11.IMUX_C2	DCC_SW2.CE
CELL11.IMUX_C3	DCC_SE2.CE
CELL11.IMUX_D0	DCS_SE1.SEL
CELL11.IMUX_D1	DCS_NE1.SEL
CELL11.IMUX_D2	DCS_SW1.SEL
CELL11.IMUX_D3	DCS_NW1.SEL
CELL11.IMUX_CLK0	CLK_ROOT.PCLK_IN_M2
CELL11.IMUX_CLK1	CLK_ROOT.PCLK_IN_M3
CELL12.IMUX_A0	DCC_NW3.CE
CELL12.IMUX_A1	DCC_NE3.CE
CELL12.IMUX_A2	DCC_SW3.CE
CELL12.IMUX_A3	DCC_SE3.CE
CELL12.IMUX_B0	DCC_NW4.CE
CELL12.IMUX_B1	DCC_NE4.CE
CELL12.IMUX_B2	DCC_SW4.CE
CELL12.IMUX_B3	DCC_SE4.CE
CELL12.IMUX_C0	DCC_NW5.CE
CELL12.IMUX_C1	DCC_NE5.CE
CELL12.IMUX_C2	DCC_SW5.CE
CELL12.IMUX_C3	DCC_SE5.CE
CELL12.IMUX_D0	DCS_SE0.SEL
CELL12.IMUX_D1	DCS_NE0.SEL
CELL12.IMUX_D2	DCS_SW0.SEL
CELL12.IMUX_D3	DCS_NW0.SEL
CELL12.IMUX_CLK0	CLK_ROOT.PCLK_IN_M4
CELL12.IMUX_CLK1	CLK_ROOT.PCLK_IN_M5
CELL13.IMUX_CLK0	CLK_ROOT.PCLK_IN_M6
CELL13.IMUX_CLK1	CLK_ROOT.PCLK_IN_M7
CELL14.IMUX_D5	CLK_ROOT.SCLK_IN_W0
CELL15.IMUX_D5	CLK_ROOT.SCLK_IN_W1
CELL16.IMUX_D5	CLK_ROOT.SCLK_IN_W2
CELL17.IMUX_D5	CLK_ROOT.SCLK_IN_W3
CELL18.IMUX_D5	CLK_ROOT.SCLK_IN_E0
CELL19.IMUX_D5	CLK_ROOT.SCLK_IN_E1
CELL20.IMUX_D5	CLK_ROOT.SCLK_IN_E2
CELL21.IMUX_D5	CLK_ROOT.SCLK_IN_E3
CELL22.IMUX_D5	CLK_ROOT.SCLK_IN_S0
CELL23.IMUX_D5	CLK_ROOT.SCLK_IN_S1
CELL24.IMUX_D5	CLK_ROOT.SCLK_IN_S2
CELL25.IMUX_D5	CLK_ROOT.SCLK_IN_S3
CELL26.IMUX_D5	CLK_ROOT.SCLK_IN_N0
CELL27.IMUX_D5	CLK_ROOT.SCLK_IN_N1
CELL28.IMUX_D5	CLK_ROOT.SCLK_IN_N2
CELL29.IMUX_D5	CLK_ROOT.SCLK_IN_N3

Tile ECLK_ROOT_W

Cells: 1

Bel ECLKSYNC0

ecp3 ECLK_ROOT_W bel ECLKSYNC0
Pin	Direction	Wires
ECLKI	input	IMUX_B4
STOP	input	IMUX_B5

Bel ECLKSYNC1

ecp3 ECLK_ROOT_W bel ECLKSYNC1
Pin	Direction	Wires
ECLKI	input	IMUX_C4
STOP	input	IMUX_C5

Bel wires

ecp3 ECLK_ROOT_W bel wires
Wire	Pins
IMUX_B4	ECLKSYNC0.ECLKI
IMUX_B5	ECLKSYNC0.STOP
IMUX_C4	ECLKSYNC1.ECLKI
IMUX_C5	ECLKSYNC1.STOP

Tile ECLK_ROOT_E

Cells: 1

Bel ECLKSYNC0

ecp3 ECLK_ROOT_E bel ECLKSYNC0
Pin	Direction	Wires
ECLKI	input	IMUX_B4
STOP	input	IMUX_B5

Bel ECLKSYNC1

ecp3 ECLK_ROOT_E bel ECLKSYNC1
Pin	Direction	Wires
ECLKI	input	IMUX_C4
STOP	input	IMUX_C5

Bel wires

ecp3 ECLK_ROOT_E bel wires
Wire	Pins
IMUX_B4	ECLKSYNC0.ECLKI
IMUX_B5	ECLKSYNC0.STOP
IMUX_C4	ECLKSYNC1.ECLKI
IMUX_C5	ECLKSYNC1.STOP

Tile ECLK_ROOT_N

Cells: 1

Bel ECLKSYNC0

ecp3 ECLK_ROOT_N bel ECLKSYNC0
Pin	Direction	Wires
ECLKI	input	IMUX_B4
STOP	input	IMUX_B5

Bel ECLKSYNC1

ecp3 ECLK_ROOT_N bel ECLKSYNC1
Pin	Direction	Wires
ECLKI	input	IMUX_C4
STOP	input	IMUX_C5

Bel wires

ecp3 ECLK_ROOT_N bel wires
Wire	Pins
IMUX_B4	ECLKSYNC0.ECLKI
IMUX_B5	ECLKSYNC0.STOP
IMUX_C4	ECLKSYNC1.ECLKI
IMUX_C5	ECLKSYNC1.STOP

Tile ECLK_TAP

Cells: 1

Bel ECLK_TAP

ecp3 ECLK_TAP bel ECLK_TAP
Pin	Direction	Wires
ECLK0	output	OUT_F6
ECLK1	output	OUT_F7

Bel wires

ecp3 ECLK_TAP bel wires
Wire	Pins
OUT_F6	ECLK_TAP.ECLK0
OUT_F7	ECLK_TAP.ECLK1

Tile HSDCLK_ROOT

Cells: 8

Bel HSDCLK_ROOT

ecp3 HSDCLK_ROOT bel HSDCLK_ROOT
Pin	Direction	Wires
OUT_E0	output	CELL4.HSDCLK0
OUT_E1	output	CELL5.HSDCLK0
OUT_E2	output	CELL6.HSDCLK0
OUT_E3	output	CELL7.HSDCLK0
OUT_E4	output	CELL4.HSDCLK4
OUT_E5	output	CELL5.HSDCLK4
OUT_E6	output	CELL6.HSDCLK4
OUT_E7	output	CELL7.HSDCLK4
OUT_W0	output	CELL0.HSDCLK0
OUT_W1	output	CELL1.HSDCLK0
OUT_W2	output	CELL2.HSDCLK0
OUT_W3	output	CELL3.HSDCLK0
OUT_W4	output	CELL0.HSDCLK4
OUT_W5	output	CELL1.HSDCLK4
OUT_W6	output	CELL2.HSDCLK4
OUT_W7	output	CELL3.HSDCLK4

Switchbox HSDCLK_SPLITTER

ecp3 HSDCLK_ROOT switchbox HSDCLK_SPLITTER
Destination	Source	Kind
CELL0.HSDCLK0	CELL4.HSDCLK0	buffer
CELL0.HSDCLK4	CELL4.HSDCLK4	buffer
CELL1.HSDCLK0	CELL5.HSDCLK0	buffer
CELL1.HSDCLK4	CELL5.HSDCLK4	buffer
CELL2.HSDCLK0	CELL6.HSDCLK0	buffer
CELL2.HSDCLK4	CELL6.HSDCLK4	buffer
CELL3.HSDCLK0	CELL7.HSDCLK0	buffer
CELL3.HSDCLK4	CELL7.HSDCLK4	buffer
CELL4.HSDCLK0	CELL0.HSDCLK0	buffer
CELL4.HSDCLK4	CELL0.HSDCLK4	buffer
CELL5.HSDCLK0	CELL1.HSDCLK0	buffer
CELL5.HSDCLK4	CELL1.HSDCLK4	buffer
CELL6.HSDCLK0	CELL2.HSDCLK0	buffer
CELL6.HSDCLK4	CELL2.HSDCLK4	buffer
CELL7.HSDCLK0	CELL3.HSDCLK0	buffer
CELL7.HSDCLK4	CELL3.HSDCLK4	buffer

Bel wires

ecp3 HSDCLK_ROOT bel wires
Wire	Pins
CELL0.HSDCLK0	HSDCLK_ROOT.OUT_W0
CELL0.HSDCLK4	HSDCLK_ROOT.OUT_W4
CELL1.HSDCLK0	HSDCLK_ROOT.OUT_W1
CELL1.HSDCLK4	HSDCLK_ROOT.OUT_W5
CELL2.HSDCLK0	HSDCLK_ROOT.OUT_W2
CELL2.HSDCLK4	HSDCLK_ROOT.OUT_W6
CELL3.HSDCLK0	HSDCLK_ROOT.OUT_W3
CELL3.HSDCLK4	HSDCLK_ROOT.OUT_W7
CELL4.HSDCLK0	HSDCLK_ROOT.OUT_E0
CELL4.HSDCLK4	HSDCLK_ROOT.OUT_E4
CELL5.HSDCLK0	HSDCLK_ROOT.OUT_E1
CELL5.HSDCLK4	HSDCLK_ROOT.OUT_E5
CELL6.HSDCLK0	HSDCLK_ROOT.OUT_E2
CELL6.HSDCLK4	HSDCLK_ROOT.OUT_E6
CELL7.HSDCLK0	HSDCLK_ROOT.OUT_E3
CELL7.HSDCLK4	HSDCLK_ROOT.OUT_E7

Tile HSDCLK_SPLITTER

Cells: 8

Switchbox HSDCLK_SPLITTER

ecp3 HSDCLK_SPLITTER switchbox HSDCLK_SPLITTER
Destination	Source	Kind
CELL0.HSDCLK0	CELL4.HSDCLK0	buffer
CELL0.HSDCLK4	CELL4.HSDCLK4	buffer
CELL1.HSDCLK0	CELL5.HSDCLK0	buffer
CELL1.HSDCLK4	CELL5.HSDCLK4	buffer
CELL2.HSDCLK0	CELL6.HSDCLK0	buffer
CELL2.HSDCLK4	CELL6.HSDCLK4	buffer
CELL3.HSDCLK0	CELL7.HSDCLK0	buffer
CELL3.HSDCLK4	CELL7.HSDCLK4	buffer
CELL4.HSDCLK0	CELL0.HSDCLK0	buffer
CELL4.HSDCLK4	CELL0.HSDCLK4	buffer
CELL5.HSDCLK0	CELL1.HSDCLK0	buffer
CELL5.HSDCLK4	CELL1.HSDCLK4	buffer
CELL6.HSDCLK0	CELL2.HSDCLK0	buffer
CELL6.HSDCLK4	CELL2.HSDCLK4	buffer
CELL7.HSDCLK0	CELL3.HSDCLK0	buffer
CELL7.HSDCLK4	CELL3.HSDCLK4	buffer

Tile PCLK0_SOURCE

Cells: 2

Bel PCLK_DCC0

ecp3 PCLK0_SOURCE bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK0
OUT_S	output	CELL1.PCLK0

Bel PCLK_DCC1

ecp3 PCLK0_SOURCE bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK4
OUT_S	output	CELL1.PCLK4

Bel wires

ecp3 PCLK0_SOURCE bel wires
Wire	Pins
CELL0.PCLK0	PCLK_DCC0.OUT_N
CELL0.PCLK4	PCLK_DCC1.OUT_N
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK0	PCLK_DCC0.OUT_S
CELL1.PCLK4	PCLK_DCC1.OUT_S

Tile PCLK1_SOURCE

Cells: 2

Bel PCLK_DCC0

ecp3 PCLK1_SOURCE bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK1
OUT_S	output	CELL1.PCLK1

Bel PCLK_DCC1

ecp3 PCLK1_SOURCE bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK5
OUT_S	output	CELL1.PCLK5

Bel wires

ecp3 PCLK1_SOURCE bel wires
Wire	Pins
CELL0.PCLK1	PCLK_DCC0.OUT_N
CELL0.PCLK5	PCLK_DCC1.OUT_N
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK1	PCLK_DCC0.OUT_S
CELL1.PCLK5	PCLK_DCC1.OUT_S

Tile PCLK2_SOURCE

Cells: 2

Bel PCLK_DCC0

ecp3 PCLK2_SOURCE bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK2
OUT_S	output	CELL1.PCLK2

Bel PCLK_DCC1

ecp3 PCLK2_SOURCE bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK6
OUT_S	output	CELL1.PCLK6

Bel wires

ecp3 PCLK2_SOURCE bel wires
Wire	Pins
CELL0.PCLK2	PCLK_DCC0.OUT_N
CELL0.PCLK6	PCLK_DCC1.OUT_N
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK2	PCLK_DCC0.OUT_S
CELL1.PCLK6	PCLK_DCC1.OUT_S

Tile PCLK3_SOURCE

Cells: 2

Bel PCLK_DCC0

ecp3 PCLK3_SOURCE bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK3
OUT_S	output	CELL1.PCLK3

Bel PCLK_DCC1

ecp3 PCLK3_SOURCE bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK7
OUT_S	output	CELL1.PCLK7

Bel wires

ecp3 PCLK3_SOURCE bel wires
Wire	Pins
CELL0.PCLK3	PCLK_DCC0.OUT_N
CELL0.PCLK7	PCLK_DCC1.OUT_N
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK3	PCLK_DCC0.OUT_S
CELL1.PCLK7	PCLK_DCC1.OUT_S

Tile PCLK0_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

ecp3 PCLK0_SOURCE_W bel PCLK_SOURCE_W
Pin	Direction	Wires
OUT_N2	output	CELL0.PCLK2
OUT_N3	output	CELL0.PCLK3
OUT_N6	output	CELL0.PCLK6
OUT_N7	output	CELL0.PCLK7
OUT_S2	output	CELL1.PCLK2
OUT_S3	output	CELL1.PCLK3
OUT_S6	output	CELL1.PCLK6
OUT_S7	output	CELL1.PCLK7

Bel PCLK_DCC0

ecp3 PCLK0_SOURCE_W bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK0
OUT_S	output	CELL1.PCLK0

Bel PCLK_DCC1

ecp3 PCLK0_SOURCE_W bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK4
OUT_S	output	CELL1.PCLK4

Bel wires

ecp3 PCLK0_SOURCE_W bel wires
Wire	Pins
CELL0.PCLK0	PCLK_DCC0.OUT_N
CELL0.PCLK2	PCLK_SOURCE_W.OUT_N2
CELL0.PCLK3	PCLK_SOURCE_W.OUT_N3
CELL0.PCLK4	PCLK_DCC1.OUT_N
CELL0.PCLK6	PCLK_SOURCE_W.OUT_N6
CELL0.PCLK7	PCLK_SOURCE_W.OUT_N7
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK0	PCLK_DCC0.OUT_S
CELL1.PCLK2	PCLK_SOURCE_W.OUT_S2
CELL1.PCLK3	PCLK_SOURCE_W.OUT_S3
CELL1.PCLK4	PCLK_DCC1.OUT_S
CELL1.PCLK6	PCLK_SOURCE_W.OUT_S6
CELL1.PCLK7	PCLK_SOURCE_W.OUT_S7

Tile PCLK1_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

ecp3 PCLK1_SOURCE_W bel PCLK_SOURCE_W
Pin	Direction	Wires
OUT_N0	output	CELL0.PCLK0
OUT_N3	output	CELL0.PCLK3
OUT_N4	output	CELL0.PCLK4
OUT_N7	output	CELL0.PCLK7
OUT_S0	output	CELL1.PCLK0
OUT_S3	output	CELL1.PCLK3
OUT_S4	output	CELL1.PCLK4
OUT_S7	output	CELL1.PCLK7

Bel PCLK_DCC0

ecp3 PCLK1_SOURCE_W bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK1
OUT_S	output	CELL1.PCLK1

Bel PCLK_DCC1

ecp3 PCLK1_SOURCE_W bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK5
OUT_S	output	CELL1.PCLK5

Bel wires

ecp3 PCLK1_SOURCE_W bel wires
Wire	Pins
CELL0.PCLK0	PCLK_SOURCE_W.OUT_N0
CELL0.PCLK1	PCLK_DCC0.OUT_N
CELL0.PCLK3	PCLK_SOURCE_W.OUT_N3
CELL0.PCLK4	PCLK_SOURCE_W.OUT_N4
CELL0.PCLK5	PCLK_DCC1.OUT_N
CELL0.PCLK7	PCLK_SOURCE_W.OUT_N7
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK0	PCLK_SOURCE_W.OUT_S0
CELL1.PCLK1	PCLK_DCC0.OUT_S
CELL1.PCLK3	PCLK_SOURCE_W.OUT_S3
CELL1.PCLK4	PCLK_SOURCE_W.OUT_S4
CELL1.PCLK5	PCLK_DCC1.OUT_S
CELL1.PCLK7	PCLK_SOURCE_W.OUT_S7

Tile PCLK3_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

ecp3 PCLK3_SOURCE_W bel PCLK_SOURCE_W
Pin	Direction	Wires
OUT_N1	output	CELL0.PCLK1
OUT_N2	output	CELL0.PCLK2
OUT_N5	output	CELL0.PCLK5
OUT_N6	output	CELL0.PCLK6
OUT_S1	output	CELL1.PCLK1
OUT_S2	output	CELL1.PCLK2
OUT_S5	output	CELL1.PCLK5
OUT_S6	output	CELL1.PCLK6

Bel PCLK_DCC0

ecp3 PCLK3_SOURCE_W bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK3
OUT_S	output	CELL1.PCLK3

Bel PCLK_DCC1

ecp3 PCLK3_SOURCE_W bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK7
OUT_S	output	CELL1.PCLK7

Bel wires

ecp3 PCLK3_SOURCE_W bel wires
Wire	Pins
CELL0.PCLK1	PCLK_SOURCE_W.OUT_N1
CELL0.PCLK2	PCLK_SOURCE_W.OUT_N2
CELL0.PCLK3	PCLK_DCC0.OUT_N
CELL0.PCLK5	PCLK_SOURCE_W.OUT_N5
CELL0.PCLK6	PCLK_SOURCE_W.OUT_N6
CELL0.PCLK7	PCLK_DCC1.OUT_N
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK1	PCLK_SOURCE_W.OUT_S1
CELL1.PCLK2	PCLK_SOURCE_W.OUT_S2
CELL1.PCLK3	PCLK_DCC0.OUT_S
CELL1.PCLK5	PCLK_SOURCE_W.OUT_S5
CELL1.PCLK6	PCLK_SOURCE_W.OUT_S6
CELL1.PCLK7	PCLK_DCC1.OUT_S

Tile PCLK0_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

ecp3 PCLK0_SOURCE_E bel PCLK_SOURCE_E
Pin	Direction	Wires
OUT_N1	output	CELL0.PCLK1
OUT_N5	output	CELL0.PCLK5
OUT_S1	output	CELL1.PCLK1
OUT_S5	output	CELL1.PCLK5

Bel PCLK_DCC0

ecp3 PCLK0_SOURCE_E bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK0
OUT_S	output	CELL1.PCLK0

Bel PCLK_DCC1

ecp3 PCLK0_SOURCE_E bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK4
OUT_S	output	CELL1.PCLK4

Bel wires

ecp3 PCLK0_SOURCE_E bel wires
Wire	Pins
CELL0.PCLK0	PCLK_DCC0.OUT_N
CELL0.PCLK1	PCLK_SOURCE_E.OUT_N1
CELL0.PCLK4	PCLK_DCC1.OUT_N
CELL0.PCLK5	PCLK_SOURCE_E.OUT_N5
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK0	PCLK_DCC0.OUT_S
CELL1.PCLK1	PCLK_SOURCE_E.OUT_S1
CELL1.PCLK4	PCLK_DCC1.OUT_S
CELL1.PCLK5	PCLK_SOURCE_E.OUT_S5

Tile PCLK2_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

ecp3 PCLK2_SOURCE_E bel PCLK_SOURCE_E
Pin	Direction	Wires
OUT_N3	output	CELL0.PCLK3
OUT_N7	output	CELL0.PCLK7
OUT_S3	output	CELL1.PCLK3
OUT_S7	output	CELL1.PCLK7

Bel PCLK_DCC0

ecp3 PCLK2_SOURCE_E bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK2
OUT_S	output	CELL1.PCLK2

Bel PCLK_DCC1

ecp3 PCLK2_SOURCE_E bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK6
OUT_S	output	CELL1.PCLK6

Bel wires

ecp3 PCLK2_SOURCE_E bel wires
Wire	Pins
CELL0.PCLK2	PCLK_DCC0.OUT_N
CELL0.PCLK3	PCLK_SOURCE_E.OUT_N3
CELL0.PCLK6	PCLK_DCC1.OUT_N
CELL0.PCLK7	PCLK_SOURCE_E.OUT_N7
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK2	PCLK_DCC0.OUT_S
CELL1.PCLK3	PCLK_SOURCE_E.OUT_S3
CELL1.PCLK6	PCLK_DCC1.OUT_S
CELL1.PCLK7	PCLK_SOURCE_E.OUT_S7

Tile PCLK3_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

ecp3 PCLK3_SOURCE_E bel PCLK_SOURCE_E
Pin	Direction	Wires
OUT_N0	output	CELL0.PCLK0
OUT_N4	output	CELL0.PCLK4
OUT_S0	output	CELL1.PCLK0
OUT_S4	output	CELL1.PCLK4

Bel PCLK_DCC0

ecp3 PCLK3_SOURCE_E bel PCLK_DCC0
Pin	Direction	Wires
CE	input	CELL0.IMUX_D6
OUT_N	output	CELL0.PCLK3
OUT_S	output	CELL1.PCLK3

Bel PCLK_DCC1

ecp3 PCLK3_SOURCE_E bel PCLK_DCC1
Pin	Direction	Wires
CE	input	CELL0.IMUX_D7
OUT_N	output	CELL0.PCLK7
OUT_S	output	CELL1.PCLK7

Bel wires

ecp3 PCLK3_SOURCE_E bel wires
Wire	Pins
CELL0.PCLK0	PCLK_SOURCE_E.OUT_N0
CELL0.PCLK3	PCLK_DCC0.OUT_N
CELL0.PCLK4	PCLK_SOURCE_E.OUT_N4
CELL0.PCLK7	PCLK_DCC1.OUT_N
CELL0.IMUX_D6	PCLK_DCC0.CE
CELL0.IMUX_D7	PCLK_DCC1.CE
CELL1.PCLK0	PCLK_SOURCE_E.OUT_S0
CELL1.PCLK3	PCLK_DCC0.OUT_S
CELL1.PCLK4	PCLK_SOURCE_E.OUT_S4
CELL1.PCLK7	PCLK_DCC1.OUT_S

Tile SCLK0_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK0_SOURCE switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK0	fixed buffer
SCLK4	VSDCLK1	fixed buffer

Tile SCLK1_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK1_SOURCE switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK1	VSDCLK0	fixed buffer
SCLK5	VSDCLK1	fixed buffer

Tile SCLK2_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK2_SOURCE switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK2	VSDCLK0	fixed buffer
SCLK6	VSDCLK1	fixed buffer

Tile SCLK3_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK3_SOURCE switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK3	VSDCLK0	fixed buffer
SCLK7	VSDCLK1	fixed buffer

Tile SCLK0_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK0_SOURCE_W switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK0	fixed buffer
SCLK2	VSDCLK4	fixed buffer
SCLK3	VSDCLK6	fixed buffer
SCLK4	VSDCLK1	fixed buffer
SCLK6	VSDCLK5	fixed buffer
SCLK7	VSDCLK7	fixed buffer

Tile SCLK1_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK1_SOURCE_W switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK6	fixed buffer
SCLK1	VSDCLK0	fixed buffer
SCLK3	VSDCLK4	fixed buffer
SCLK4	VSDCLK7	fixed buffer
SCLK5	VSDCLK1	fixed buffer
SCLK7	VSDCLK5	fixed buffer

Tile SCLK3_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK3_SOURCE_W switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK1	VSDCLK4	fixed buffer
SCLK2	VSDCLK6	fixed buffer
SCLK3	VSDCLK0	fixed buffer
SCLK5	VSDCLK5	fixed buffer
SCLK6	VSDCLK7	fixed buffer
SCLK7	VSDCLK1	fixed buffer

Tile SCLK0_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK0_SOURCE_E switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK0	fixed buffer
SCLK1	VSDCLK2	fixed buffer
SCLK4	VSDCLK1	fixed buffer
SCLK5	VSDCLK3	fixed buffer

Tile SCLK2_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK2_SOURCE_E switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK2	VSDCLK0	fixed buffer
SCLK3	VSDCLK2	fixed buffer
SCLK6	VSDCLK1	fixed buffer
SCLK7	VSDCLK3	fixed buffer

Tile SCLK3_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

ecp3 SCLK3_SOURCE_E switchbox SCLK_SOURCE
Destination	Source	Kind
SCLK0	VSDCLK2	fixed buffer
SCLK3	VSDCLK0	fixed buffer
SCLK4	VSDCLK3	fixed buffer
SCLK7	VSDCLK1	fixed buffer