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DSP

Tile DSP

Cells: 9

Bel DSP0

ecp3 DSP bel DSP0
PinDirectionWires
A0_0inputTCELL0:IMUX_A0
A0_1inputTCELL3:IMUX_A0
A10_0inputTCELL1:IMUX_A2
A10_1inputTCELL4:IMUX_A1
A11_0inputTCELL1:IMUX_B2
A11_1inputTCELL4:IMUX_B1
A12_0inputTCELL2:IMUX_B0
A12_1inputTCELL5:IMUX_C0
A13_0inputTCELL2:IMUX_C0
A13_1inputTCELL5:IMUX_D0
A14_0inputTCELL2:IMUX_D0
A14_1inputTCELL5:IMUX_A1
A15_0inputTCELL2:IMUX_A1
A15_1inputTCELL5:IMUX_B1
A16_0inputTCELL2:IMUX_B1
A16_1inputTCELL5:IMUX_C1
A17_0inputTCELL2:IMUX_C1
A17_1inputTCELL5:IMUX_D1
A1_0inputTCELL0:IMUX_B0
A1_1inputTCELL3:IMUX_B0
A2_0inputTCELL0:IMUX_A1
A2_1inputTCELL3:IMUX_C0
A3_0inputTCELL0:IMUX_B1
A3_1inputTCELL3:IMUX_D0
A4_0inputTCELL0:IMUX_A2
A4_1inputTCELL3:IMUX_A1
A5_0inputTCELL0:IMUX_B2
A5_1inputTCELL3:IMUX_B1
A6_0inputTCELL1:IMUX_A0
A6_1inputTCELL4:IMUX_A0
A7_0inputTCELL1:IMUX_B0
A7_1inputTCELL4:IMUX_B0
A8_0inputTCELL1:IMUX_A1
A8_1inputTCELL4:IMUX_C0
A9_0inputTCELL1:IMUX_B1
A9_1inputTCELL4:IMUX_D0
B0_0inputTCELL0:IMUX_A4
B0_1inputTCELL3:IMUX_C1
B10_0inputTCELL1:IMUX_A5
B10_1inputTCELL4:IMUX_C2
B11_0inputTCELL1:IMUX_B5
B11_1inputTCELL4:IMUX_D2
B12_0inputTCELL2:IMUX_D1
B12_1inputTCELL5:IMUX_A2
B13_0inputTCELL2:IMUX_A2
B13_1inputTCELL5:IMUX_B2
B14_0inputTCELL2:IMUX_B2
B14_1inputTCELL5:IMUX_C2
B15_0inputTCELL2:IMUX_C2
B15_1inputTCELL5:IMUX_D2
B16_0inputTCELL2:IMUX_D2
B16_1inputTCELL5:IMUX_A3
B17_0inputTCELL2:IMUX_A3
B17_1inputTCELL5:IMUX_B3
B1_0inputTCELL0:IMUX_B4
B1_1inputTCELL3:IMUX_D1
B2_0inputTCELL0:IMUX_A5
B2_1inputTCELL3:IMUX_A2
B3_0inputTCELL0:IMUX_B5
B3_1inputTCELL3:IMUX_B2
B4_0inputTCELL0:IMUX_A6
B4_1inputTCELL3:IMUX_C2
B5_0inputTCELL0:IMUX_B6
B5_1inputTCELL3:IMUX_D2
B6_0inputTCELL1:IMUX_C0
B6_1inputTCELL4:IMUX_C1
B7_0inputTCELL1:IMUX_D0
B7_1inputTCELL4:IMUX_D1
B8_0inputTCELL1:IMUX_A4
B8_1inputTCELL4:IMUX_A2
B9_0inputTCELL1:IMUX_B4
B9_1inputTCELL4:IMUX_B2
C0inputTCELL0:IMUX_C0
C1inputTCELL0:IMUX_D0
C10inputTCELL0:IMUX_C4
C11inputTCELL0:IMUX_D4
C12inputTCELL0:IMUX_C5
C13inputTCELL0:IMUX_D5
C14inputTCELL0:IMUX_C6
C15inputTCELL0:IMUX_A7
C16inputTCELL1:IMUX_C1
C17inputTCELL1:IMUX_D1
C18inputTCELL1:IMUX_C2
C19inputTCELL1:IMUX_D2
C2inputTCELL0:IMUX_C1
C20inputTCELL1:IMUX_A3
C21inputTCELL1:IMUX_B3
C22inputTCELL1:IMUX_C3
C23inputTCELL1:IMUX_D3
C24inputTCELL1:IMUX_C4
C25inputTCELL1:IMUX_D4
C26inputTCELL1:IMUX_C5
C27inputTCELL1:IMUX_D5
C28inputTCELL1:IMUX_A6
C29inputTCELL1:IMUX_B6
C3inputTCELL0:IMUX_D1
C30inputTCELL1:IMUX_C6
C31inputTCELL1:IMUX_A7
C32inputTCELL2:IMUX_A0
C33inputTCELL2:IMUX_B3
C34inputTCELL2:IMUX_C3
C35inputTCELL2:IMUX_D3
C36inputTCELL2:IMUX_A4
C37inputTCELL2:IMUX_B4
C38inputTCELL2:IMUX_C4
C39inputTCELL2:IMUX_D4
C4inputTCELL0:IMUX_C2
C40inputTCELL2:IMUX_A5
C41inputTCELL2:IMUX_B5
C42inputTCELL2:IMUX_C5
C43inputTCELL2:IMUX_D5
C44inputTCELL2:IMUX_A6
C45inputTCELL2:IMUX_B6
C46inputTCELL2:IMUX_C6
C47inputTCELL2:IMUX_A7
C48inputTCELL3:IMUX_A5
C49inputTCELL3:IMUX_A7
C5inputTCELL0:IMUX_D2
C50inputTCELL4:IMUX_C3
C51inputTCELL4:IMUX_D3
C52inputTCELL5:IMUX_A0
C53inputTCELL5:IMUX_B0
C6inputTCELL0:IMUX_A3
C7inputTCELL0:IMUX_B3
C8inputTCELL0:IMUX_C3
C9inputTCELL0:IMUX_D3
CE0inputTCELL1:IMUX_CE0
CE1inputTCELL3:IMUX_CE0
CE2inputTCELL5:IMUX_CE0
CE3inputTCELL7:IMUX_CE0
CLK0inputTCELL1:IMUX_CLK0
CLK1inputTCELL1:IMUX_CLK1
CLK2inputTCELL2:IMUX_CLK0
CLK3inputTCELL2:IMUX_CLK1
EQOMoutputTCELL3:OUT_Q4
EQPAToutputTCELL3:OUT_F4
EQPATBoutputTCELL3:OUT_Q3
EQZoutputTCELL4:OUT_Q1
EQZMoutputTCELL4:OUT_F1
OP0inputTCELL5:IMUX_CLK1
OP1inputTCELL4:IMUX_LSR2
OP10inputTCELL0:IMUX_LSR1
OP2inputTCELL4:IMUX_LSR1
OP3inputTCELL3:IMUX_LSR2
OP4inputTCELL3:IMUX_LSR1
OP5inputTCELL2:IMUX_LSR2
OP6inputTCELL2:IMUX_LSR1
OP7inputTCELL1:IMUX_LSR2
OP8inputTCELL1:IMUX_LSR1
OP9inputTCELL0:IMUX_LSR2
OVERoutputTCELL3:OUT_F3
OVERUNDERoutputTCELL3:OUT_F2
R0outputTCELL0:OUT_F0
R1outputTCELL0:OUT_Q0
R10outputTCELL1:OUT_F2
R11outputTCELL1:OUT_Q3
R12outputTCELL2:OUT_F0
R13outputTCELL2:OUT_Q0
R14outputTCELL2:OUT_F1
R15outputTCELL2:OUT_Q1
R16outputTCELL2:OUT_F2
R17outputTCELL2:OUT_Q2
R18outputTCELL0:OUT_F3
R19outputTCELL0:OUT_Q4
R2outputTCELL0:OUT_F1
R20outputTCELL0:OUT_F4
R21outputTCELL0:OUT_Q5
R22outputTCELL0:OUT_F5
R23outputTCELL0:OUT_Q6
R24outputTCELL1:OUT_F3
R25outputTCELL1:OUT_Q4
R26outputTCELL1:OUT_F4
R27outputTCELL1:OUT_Q5
R28outputTCELL1:OUT_F5
R29outputTCELL1:OUT_Q6
R3outputTCELL0:OUT_Q2
R30outputTCELL2:OUT_F3
R31outputTCELL2:OUT_Q3
R32outputTCELL2:OUT_F4
R33outputTCELL2:OUT_Q4
R34outputTCELL2:OUT_F5
R35outputTCELL2:OUT_Q5
R36outputTCELL0:OUT_F6
R37outputTCELL0:OUT_Q1
R38outputTCELL0:OUT_F7
R39outputTCELL0:OUT_Q7
R4outputTCELL0:OUT_F2
R40outputTCELL1:OUT_F6
R41outputTCELL1:OUT_Q1
R42outputTCELL1:OUT_F7
R43outputTCELL1:OUT_Q7
R44outputTCELL2:OUT_F6
R45outputTCELL2:OUT_Q6
R46outputTCELL2:OUT_F7
R47outputTCELL2:OUT_Q7
R48outputTCELL3:OUT_F0
R49outputTCELL3:OUT_Q0
R5outputTCELL0:OUT_Q3
R50outputTCELL3:OUT_F1
R51outputTCELL3:OUT_Q1
R52outputTCELL4:OUT_F0
R53outputTCELL4:OUT_Q0
R54outputTCELL3:OUT_F2
R55outputTCELL3:OUT_Q2
R56outputTCELL3:OUT_F3
R57outputTCELL3:OUT_Q3
R58outputTCELL3:OUT_F4
R59outputTCELL3:OUT_Q4
R6outputTCELL1:OUT_F0
R60outputTCELL4:OUT_F1
R61outputTCELL4:OUT_Q1
R62outputTCELL4:OUT_F2
R63outputTCELL4:OUT_Q2
R64outputTCELL4:OUT_F3
R65outputTCELL4:OUT_Q3
R66outputTCELL5:OUT_F0
R67outputTCELL5:OUT_Q0
R68outputTCELL5:OUT_F1
R69outputTCELL5:OUT_Q1
R7outputTCELL1:OUT_Q0
R70outputTCELL5:OUT_F2
R71outputTCELL5:OUT_Q2
R8outputTCELL1:OUT_F1
R9outputTCELL1:OUT_Q2
RST0inputTCELL0:IMUX_LSR0
RST1inputTCELL2:IMUX_LSR0
RST2inputTCELL4:IMUX_LSR0
RST3inputTCELL6:IMUX_LSR0
SIGNEDA_0inputTCELL0:IMUX_CE0
SIGNEDA_1inputTCELL2:IMUX_CE0
SIGNEDB_0inputTCELL0:IMUX_CE1
SIGNEDB_1inputTCELL2:IMUX_CE1
SOURCEA_0inputTCELL1:IMUX_CE1
SOURCEA_1inputTCELL3:IMUX_CE1
SOURCEB_0inputTCELL1:IMUX_LSR0
SOURCEB_1inputTCELL3:IMUX_LSR0
UNDERoutputTCELL3:OUT_Q2

Bel DSP1

ecp3 DSP bel DSP1
PinDirectionWires
A0_0inputTCELL3:IMUX_B5
A0_1inputTCELL6:IMUX_A4
A10_0inputTCELL4:IMUX_A5
A10_1inputTCELL7:IMUX_D5
A11_0inputTCELL4:IMUX_B5
A11_1inputTCELL7:IMUX_A6
A12_0inputTCELL5:IMUX_C5
A12_1inputTCELL8:IMUX_C1
A13_0inputTCELL5:IMUX_D5
A13_1inputTCELL8:IMUX_D1
A14_0inputTCELL5:IMUX_A6
A14_1inputTCELL8:IMUX_A2
A15_0inputTCELL5:IMUX_B6
A15_1inputTCELL8:IMUX_B2
A16_0inputTCELL5:IMUX_C6
A16_1inputTCELL8:IMUX_C2
A17_0inputTCELL5:IMUX_A7
A17_1inputTCELL8:IMUX_D2
A1_0inputTCELL3:IMUX_C5
A1_1inputTCELL6:IMUX_B4
A2_0inputTCELL3:IMUX_D5
A2_1inputTCELL6:IMUX_C4
A3_0inputTCELL3:IMUX_A6
A3_1inputTCELL6:IMUX_D4
A4_0inputTCELL3:IMUX_B6
A4_1inputTCELL6:IMUX_A5
A5_0inputTCELL3:IMUX_C6
A5_1inputTCELL6:IMUX_B5
A6_0inputTCELL4:IMUX_A3
A6_1inputTCELL7:IMUX_C1
A7_0inputTCELL4:IMUX_B3
A7_1inputTCELL7:IMUX_D1
A8_0inputTCELL4:IMUX_A4
A8_1inputTCELL7:IMUX_A2
A9_0inputTCELL4:IMUX_B4
A9_1inputTCELL7:IMUX_C5
B0_0inputTCELL6:IMUX_A0
B0_1inputTCELL6:IMUX_C5
B10_0inputTCELL7:IMUX_A1
B10_1inputTCELL7:IMUX_C6
B11_0inputTCELL7:IMUX_B1
B11_1inputTCELL7:IMUX_A7
B12_0inputTCELL8:IMUX_A0
B12_1inputTCELL8:IMUX_C4
B13_0inputTCELL8:IMUX_B0
B13_1inputTCELL8:IMUX_D4
B14_0inputTCELL8:IMUX_C0
B14_1inputTCELL8:IMUX_C5
B15_0inputTCELL8:IMUX_D0
B15_1inputTCELL8:IMUX_D5
B16_0inputTCELL8:IMUX_A1
B16_1inputTCELL8:IMUX_C6
B17_0inputTCELL8:IMUX_B1
B17_1inputTCELL8:IMUX_A7
B1_0inputTCELL6:IMUX_B0
B1_1inputTCELL6:IMUX_D5
B2_0inputTCELL6:IMUX_C0
B2_1inputTCELL6:IMUX_A6
B3_0inputTCELL6:IMUX_D0
B3_1inputTCELL6:IMUX_B6
B4_0inputTCELL6:IMUX_A1
B4_1inputTCELL6:IMUX_C6
B5_0inputTCELL6:IMUX_B1
B5_1inputTCELL6:IMUX_A7
B6_0inputTCELL7:IMUX_A0
B6_1inputTCELL7:IMUX_D4
B7_0inputTCELL7:IMUX_B0
B7_1inputTCELL7:IMUX_A5
B8_0inputTCELL7:IMUX_C0
B8_1inputTCELL7:IMUX_B5
B9_0inputTCELL7:IMUX_D0
B9_1inputTCELL7:IMUX_B6
C0inputTCELL3:IMUX_A3
C1inputTCELL3:IMUX_B3
C10inputTCELL4:IMUX_C5
C11inputTCELL4:IMUX_D5
C12inputTCELL4:IMUX_A6
C13inputTCELL4:IMUX_B6
C14inputTCELL4:IMUX_C6
C15inputTCELL4:IMUX_A7
C16inputTCELL5:IMUX_C3
C17inputTCELL5:IMUX_D3
C18inputTCELL5:IMUX_A4
C19inputTCELL5:IMUX_B4
C2inputTCELL3:IMUX_C3
C20inputTCELL5:IMUX_C4
C21inputTCELL5:IMUX_D4
C22inputTCELL5:IMUX_A5
C23inputTCELL5:IMUX_B5
C24inputTCELL6:IMUX_C1
C25inputTCELL6:IMUX_D1
C26inputTCELL6:IMUX_A2
C27inputTCELL6:IMUX_B2
C28inputTCELL6:IMUX_C2
C29inputTCELL6:IMUX_D2
C3inputTCELL3:IMUX_D3
C30inputTCELL6:IMUX_A3
C31inputTCELL6:IMUX_B3
C32inputTCELL6:IMUX_C3
C33inputTCELL6:IMUX_D3
C34inputTCELL7:IMUX_B2
C35inputTCELL7:IMUX_C2
C36inputTCELL7:IMUX_D2
C37inputTCELL7:IMUX_A3
C38inputTCELL7:IMUX_B3
C39inputTCELL7:IMUX_C3
C4inputTCELL3:IMUX_A4
C40inputTCELL7:IMUX_D3
C41inputTCELL7:IMUX_A4
C42inputTCELL7:IMUX_B4
C43inputTCELL7:IMUX_C4
C44inputTCELL8:IMUX_A3
C45inputTCELL8:IMUX_B3
C46inputTCELL8:IMUX_C3
C47inputTCELL8:IMUX_D3
C48inputTCELL8:IMUX_A4
C49inputTCELL8:IMUX_B4
C5inputTCELL3:IMUX_B4
C50inputTCELL8:IMUX_A5
C51inputTCELL8:IMUX_B5
C52inputTCELL8:IMUX_A6
C53inputTCELL8:IMUX_B6
C6inputTCELL3:IMUX_C4
C7inputTCELL3:IMUX_D4
C8inputTCELL4:IMUX_C4
C9inputTCELL4:IMUX_D4
CE0inputTCELL1:IMUX_CE0
CE1inputTCELL3:IMUX_CE0
CE2inputTCELL5:IMUX_CE0
CE3inputTCELL7:IMUX_CE0
CLK0inputTCELL6:IMUX_CLK0
CLK1inputTCELL6:IMUX_CLK1
CLK2inputTCELL7:IMUX_CLK0
CLK3inputTCELL7:IMUX_CLK1
EQOMoutputTCELL6:OUT_Q7
EQPAToutputTCELL6:OUT_F7
EQPATBoutputTCELL6:OUT_Q6
EQZoutputTCELL7:OUT_Q5
EQZMoutputTCELL7:OUT_F5
OP0inputTCELL8:IMUX_LSR2
OP1inputTCELL8:IMUX_LSR1
OP10inputTCELL5:IMUX_LSR1
OP2inputTCELL8:IMUX_LSR0
OP3inputTCELL8:IMUX_CE1
OP4inputTCELL8:IMUX_CE0
OP5inputTCELL7:IMUX_LSR2
OP6inputTCELL7:IMUX_LSR1
OP7inputTCELL6:IMUX_LSR2
OP8inputTCELL6:IMUX_LSR1
OP9inputTCELL5:IMUX_LSR2
OVERoutputTCELL6:OUT_F6
OVERUNDERoutputTCELL6:OUT_F5
R0outputTCELL3:OUT_F5
R1outputTCELL3:OUT_Q5
R10outputTCELL4:OUT_F6
R11outputTCELL4:OUT_Q6
R12outputTCELL5:OUT_F3
R13outputTCELL5:OUT_Q3
R14outputTCELL5:OUT_F4
R15outputTCELL5:OUT_Q4
R16outputTCELL5:OUT_F5
R17outputTCELL5:OUT_Q5
R18outputTCELL4:OUT_F7
R19outputTCELL4:OUT_Q7
R2outputTCELL3:OUT_F6
R20outputTCELL5:OUT_F6
R21outputTCELL5:OUT_Q6
R22outputTCELL5:OUT_F7
R23outputTCELL5:OUT_Q7
R24outputTCELL6:OUT_F0
R25outputTCELL6:OUT_Q0
R26outputTCELL6:OUT_F1
R27outputTCELL6:OUT_Q1
R28outputTCELL7:OUT_F0
R29outputTCELL7:OUT_Q0
R3outputTCELL3:OUT_Q6
R30outputTCELL7:OUT_F1
R31outputTCELL7:OUT_Q1
R32outputTCELL8:OUT_F0
R33outputTCELL8:OUT_Q0
R34outputTCELL8:OUT_F1
R35outputTCELL8:OUT_Q1
R36outputTCELL6:OUT_F2
R37outputTCELL6:OUT_Q2
R38outputTCELL6:OUT_F3
R39outputTCELL6:OUT_Q3
R4outputTCELL3:OUT_F7
R40outputTCELL6:OUT_F4
R41outputTCELL6:OUT_Q4
R42outputTCELL7:OUT_F2
R43outputTCELL7:OUT_Q2
R44outputTCELL7:OUT_F3
R45outputTCELL7:OUT_Q3
R46outputTCELL7:OUT_F4
R47outputTCELL7:OUT_Q4
R48outputTCELL8:OUT_F2
R49outputTCELL8:OUT_Q2
R5outputTCELL3:OUT_Q7
R50outputTCELL8:OUT_F3
R51outputTCELL8:OUT_Q3
R52outputTCELL8:OUT_F4
R53outputTCELL8:OUT_Q4
R54outputTCELL6:OUT_F5
R55outputTCELL6:OUT_Q5
R56outputTCELL6:OUT_F6
R57outputTCELL6:OUT_Q6
R58outputTCELL6:OUT_F7
R59outputTCELL6:OUT_Q7
R6outputTCELL4:OUT_F4
R60outputTCELL7:OUT_F5
R61outputTCELL7:OUT_Q5
R62outputTCELL7:OUT_F6
R63outputTCELL7:OUT_Q6
R64outputTCELL7:OUT_F7
R65outputTCELL7:OUT_Q7
R66outputTCELL8:OUT_F5
R67outputTCELL8:OUT_Q5
R68outputTCELL8:OUT_F6
R69outputTCELL8:OUT_Q6
R7outputTCELL4:OUT_Q4
R70outputTCELL8:OUT_F7
R71outputTCELL8:OUT_Q7
R8outputTCELL4:OUT_F5
R9outputTCELL4:OUT_Q5
RST0inputTCELL0:IMUX_LSR0
RST1inputTCELL2:IMUX_LSR0
RST2inputTCELL4:IMUX_LSR0
RST3inputTCELL6:IMUX_LSR0
SIGNEDA_0inputTCELL4:IMUX_CE0
SIGNEDA_1inputTCELL6:IMUX_CE0
SIGNEDB_0inputTCELL4:IMUX_CE1
SIGNEDB_1inputTCELL6:IMUX_CE1
SOURCEA_0inputTCELL5:IMUX_CE1
SOURCEA_1inputTCELL7:IMUX_CE1
SOURCEB_0inputTCELL5:IMUX_LSR0
SOURCEB_1inputTCELL7:IMUX_LSR0
UNDERoutputTCELL6:OUT_Q5

Bel wires

ecp3 DSP bel wires
WirePins
TCELL0:IMUX_A0DSP0.A0_0
TCELL0:IMUX_A1DSP0.A2_0
TCELL0:IMUX_A2DSP0.A4_0
TCELL0:IMUX_A3DSP0.C6
TCELL0:IMUX_A4DSP0.B0_0
TCELL0:IMUX_A5DSP0.B2_0
TCELL0:IMUX_A6DSP0.B4_0
TCELL0:IMUX_A7DSP0.C15
TCELL0:IMUX_B0DSP0.A1_0
TCELL0:IMUX_B1DSP0.A3_0
TCELL0:IMUX_B2DSP0.A5_0
TCELL0:IMUX_B3DSP0.C7
TCELL0:IMUX_B4DSP0.B1_0
TCELL0:IMUX_B5DSP0.B3_0
TCELL0:IMUX_B6DSP0.B5_0
TCELL0:IMUX_C0DSP0.C0
TCELL0:IMUX_C1DSP0.C2
TCELL0:IMUX_C2DSP0.C4
TCELL0:IMUX_C3DSP0.C8
TCELL0:IMUX_C4DSP0.C10
TCELL0:IMUX_C5DSP0.C12
TCELL0:IMUX_C6DSP0.C14
TCELL0:IMUX_D0DSP0.C1
TCELL0:IMUX_D1DSP0.C3
TCELL0:IMUX_D2DSP0.C5
TCELL0:IMUX_D3DSP0.C9
TCELL0:IMUX_D4DSP0.C11
TCELL0:IMUX_D5DSP0.C13
TCELL0:IMUX_LSR0DSP0.RST0, DSP1.RST0
TCELL0:IMUX_LSR1DSP0.OP10
TCELL0:IMUX_LSR2DSP0.OP9
TCELL0:IMUX_CE0DSP0.SIGNEDA_0
TCELL0:IMUX_CE1DSP0.SIGNEDB_0
TCELL0:OUT_F0DSP0.R0
TCELL0:OUT_F1DSP0.R2
TCELL0:OUT_F2DSP0.R4
TCELL0:OUT_F3DSP0.R18
TCELL0:OUT_F4DSP0.R20
TCELL0:OUT_F5DSP0.R22
TCELL0:OUT_F6DSP0.R36
TCELL0:OUT_F7DSP0.R38
TCELL0:OUT_Q0DSP0.R1
TCELL0:OUT_Q1DSP0.R37
TCELL0:OUT_Q2DSP0.R3
TCELL0:OUT_Q3DSP0.R5
TCELL0:OUT_Q4DSP0.R19
TCELL0:OUT_Q5DSP0.R21
TCELL0:OUT_Q6DSP0.R23
TCELL0:OUT_Q7DSP0.R39
TCELL1:IMUX_A0DSP0.A6_0
TCELL1:IMUX_A1DSP0.A8_0
TCELL1:IMUX_A2DSP0.A10_0
TCELL1:IMUX_A3DSP0.C20
TCELL1:IMUX_A4DSP0.B8_0
TCELL1:IMUX_A5DSP0.B10_0
TCELL1:IMUX_A6DSP0.C28
TCELL1:IMUX_A7DSP0.C31
TCELL1:IMUX_B0DSP0.A7_0
TCELL1:IMUX_B1DSP0.A9_0
TCELL1:IMUX_B2DSP0.A11_0
TCELL1:IMUX_B3DSP0.C21
TCELL1:IMUX_B4DSP0.B9_0
TCELL1:IMUX_B5DSP0.B11_0
TCELL1:IMUX_B6DSP0.C29
TCELL1:IMUX_C0DSP0.B6_0
TCELL1:IMUX_C1DSP0.C16
TCELL1:IMUX_C2DSP0.C18
TCELL1:IMUX_C3DSP0.C22
TCELL1:IMUX_C4DSP0.C24
TCELL1:IMUX_C5DSP0.C26
TCELL1:IMUX_C6DSP0.C30
TCELL1:IMUX_D0DSP0.B7_0
TCELL1:IMUX_D1DSP0.C17
TCELL1:IMUX_D2DSP0.C19
TCELL1:IMUX_D3DSP0.C23
TCELL1:IMUX_D4DSP0.C25
TCELL1:IMUX_D5DSP0.C27
TCELL1:IMUX_CLK0DSP0.CLK0
TCELL1:IMUX_CLK1DSP0.CLK1
TCELL1:IMUX_LSR0DSP0.SOURCEB_0
TCELL1:IMUX_LSR1DSP0.OP8
TCELL1:IMUX_LSR2DSP0.OP7
TCELL1:IMUX_CE0DSP0.CE0, DSP1.CE0
TCELL1:IMUX_CE1DSP0.SOURCEA_0
TCELL1:OUT_F0DSP0.R6
TCELL1:OUT_F1DSP0.R8
TCELL1:OUT_F2DSP0.R10
TCELL1:OUT_F3DSP0.R24
TCELL1:OUT_F4DSP0.R26
TCELL1:OUT_F5DSP0.R28
TCELL1:OUT_F6DSP0.R40
TCELL1:OUT_F7DSP0.R42
TCELL1:OUT_Q0DSP0.R7
TCELL1:OUT_Q1DSP0.R41
TCELL1:OUT_Q2DSP0.R9
TCELL1:OUT_Q3DSP0.R11
TCELL1:OUT_Q4DSP0.R25
TCELL1:OUT_Q5DSP0.R27
TCELL1:OUT_Q6DSP0.R29
TCELL1:OUT_Q7DSP0.R43
TCELL2:IMUX_A0DSP0.C32
TCELL2:IMUX_A1DSP0.A15_0
TCELL2:IMUX_A2DSP0.B13_0
TCELL2:IMUX_A3DSP0.B17_0
TCELL2:IMUX_A4DSP0.C36
TCELL2:IMUX_A5DSP0.C40
TCELL2:IMUX_A6DSP0.C44
TCELL2:IMUX_A7DSP0.C47
TCELL2:IMUX_B0DSP0.A12_0
TCELL2:IMUX_B1DSP0.A16_0
TCELL2:IMUX_B2DSP0.B14_0
TCELL2:IMUX_B3DSP0.C33
TCELL2:IMUX_B4DSP0.C37
TCELL2:IMUX_B5DSP0.C41
TCELL2:IMUX_B6DSP0.C45
TCELL2:IMUX_C0DSP0.A13_0
TCELL2:IMUX_C1DSP0.A17_0
TCELL2:IMUX_C2DSP0.B15_0
TCELL2:IMUX_C3DSP0.C34
TCELL2:IMUX_C4DSP0.C38
TCELL2:IMUX_C5DSP0.C42
TCELL2:IMUX_C6DSP0.C46
TCELL2:IMUX_D0DSP0.A14_0
TCELL2:IMUX_D1DSP0.B12_0
TCELL2:IMUX_D2DSP0.B16_0
TCELL2:IMUX_D3DSP0.C35
TCELL2:IMUX_D4DSP0.C39
TCELL2:IMUX_D5DSP0.C43
TCELL2:IMUX_CLK0DSP0.CLK2
TCELL2:IMUX_CLK1DSP0.CLK3
TCELL2:IMUX_LSR0DSP0.RST1, DSP1.RST1
TCELL2:IMUX_LSR1DSP0.OP6
TCELL2:IMUX_LSR2DSP0.OP5
TCELL2:IMUX_CE0DSP0.SIGNEDA_1
TCELL2:IMUX_CE1DSP0.SIGNEDB_1
TCELL2:OUT_F0DSP0.R12
TCELL2:OUT_F1DSP0.R14
TCELL2:OUT_F2DSP0.R16
TCELL2:OUT_F3DSP0.R30
TCELL2:OUT_F4DSP0.R32
TCELL2:OUT_F5DSP0.R34
TCELL2:OUT_F6DSP0.R44
TCELL2:OUT_F7DSP0.R46
TCELL2:OUT_Q0DSP0.R13
TCELL2:OUT_Q1DSP0.R15
TCELL2:OUT_Q2DSP0.R17
TCELL2:OUT_Q3DSP0.R31
TCELL2:OUT_Q4DSP0.R33
TCELL2:OUT_Q5DSP0.R35
TCELL2:OUT_Q6DSP0.R45
TCELL2:OUT_Q7DSP0.R47
TCELL3:IMUX_A0DSP0.A0_1
TCELL3:IMUX_A1DSP0.A4_1
TCELL3:IMUX_A2DSP0.B2_1
TCELL3:IMUX_A3DSP1.C0
TCELL3:IMUX_A4DSP1.C4
TCELL3:IMUX_A5DSP0.C48
TCELL3:IMUX_A6DSP1.A3_0
TCELL3:IMUX_A7DSP0.C49
TCELL3:IMUX_B0DSP0.A1_1
TCELL3:IMUX_B1DSP0.A5_1
TCELL3:IMUX_B2DSP0.B3_1
TCELL3:IMUX_B3DSP1.C1
TCELL3:IMUX_B4DSP1.C5
TCELL3:IMUX_B5DSP1.A0_0
TCELL3:IMUX_B6DSP1.A4_0
TCELL3:IMUX_C0DSP0.A2_1
TCELL3:IMUX_C1DSP0.B0_1
TCELL3:IMUX_C2DSP0.B4_1
TCELL3:IMUX_C3DSP1.C2
TCELL3:IMUX_C4DSP1.C6
TCELL3:IMUX_C5DSP1.A1_0
TCELL3:IMUX_C6DSP1.A5_0
TCELL3:IMUX_D0DSP0.A3_1
TCELL3:IMUX_D1DSP0.B1_1
TCELL3:IMUX_D2DSP0.B5_1
TCELL3:IMUX_D3DSP1.C3
TCELL3:IMUX_D4DSP1.C7
TCELL3:IMUX_D5DSP1.A2_0
TCELL3:IMUX_LSR0DSP0.SOURCEB_1
TCELL3:IMUX_LSR1DSP0.OP4
TCELL3:IMUX_LSR2DSP0.OP3
TCELL3:IMUX_CE0DSP0.CE1, DSP1.CE1
TCELL3:IMUX_CE1DSP0.SOURCEA_1
TCELL3:OUT_F0DSP0.R48
TCELL3:OUT_F1DSP0.R50
TCELL3:OUT_F2DSP0.OVERUNDER, DSP0.R54
TCELL3:OUT_F3DSP0.OVER, DSP0.R56
TCELL3:OUT_F4DSP0.EQPAT, DSP0.R58
TCELL3:OUT_F5DSP1.R0
TCELL3:OUT_F6DSP1.R2
TCELL3:OUT_F7DSP1.R4
TCELL3:OUT_Q0DSP0.R49
TCELL3:OUT_Q1DSP0.R51
TCELL3:OUT_Q2DSP0.R55, DSP0.UNDER
TCELL3:OUT_Q3DSP0.EQPATB, DSP0.R57
TCELL3:OUT_Q4DSP0.EQOM, DSP0.R59
TCELL3:OUT_Q5DSP1.R1
TCELL3:OUT_Q6DSP1.R3
TCELL3:OUT_Q7DSP1.R5
TCELL4:IMUX_A0DSP0.A6_1
TCELL4:IMUX_A1DSP0.A10_1
TCELL4:IMUX_A2DSP0.B8_1
TCELL4:IMUX_A3DSP1.A6_0
TCELL4:IMUX_A4DSP1.A8_0
TCELL4:IMUX_A5DSP1.A10_0
TCELL4:IMUX_A6DSP1.C12
TCELL4:IMUX_A7DSP1.C15
TCELL4:IMUX_B0DSP0.A7_1
TCELL4:IMUX_B1DSP0.A11_1
TCELL4:IMUX_B2DSP0.B9_1
TCELL4:IMUX_B3DSP1.A7_0
TCELL4:IMUX_B4DSP1.A9_0
TCELL4:IMUX_B5DSP1.A11_0
TCELL4:IMUX_B6DSP1.C13
TCELL4:IMUX_C0DSP0.A8_1
TCELL4:IMUX_C1DSP0.B6_1
TCELL4:IMUX_C2DSP0.B10_1
TCELL4:IMUX_C3DSP0.C50
TCELL4:IMUX_C4DSP1.C8
TCELL4:IMUX_C5DSP1.C10
TCELL4:IMUX_C6DSP1.C14
TCELL4:IMUX_D0DSP0.A9_1
TCELL4:IMUX_D1DSP0.B7_1
TCELL4:IMUX_D2DSP0.B11_1
TCELL4:IMUX_D3DSP0.C51
TCELL4:IMUX_D4DSP1.C9
TCELL4:IMUX_D5DSP1.C11
TCELL4:IMUX_LSR0DSP0.RST2, DSP1.RST2
TCELL4:IMUX_LSR1DSP0.OP2
TCELL4:IMUX_LSR2DSP0.OP1
TCELL4:IMUX_CE0DSP1.SIGNEDA_0
TCELL4:IMUX_CE1DSP1.SIGNEDB_0
TCELL4:OUT_F0DSP0.R52
TCELL4:OUT_F1DSP0.EQZM, DSP0.R60
TCELL4:OUT_F2DSP0.R62
TCELL4:OUT_F3DSP0.R64
TCELL4:OUT_F4DSP1.R6
TCELL4:OUT_F5DSP1.R8
TCELL4:OUT_F6DSP1.R10
TCELL4:OUT_F7DSP1.R18
TCELL4:OUT_Q0DSP0.R53
TCELL4:OUT_Q1DSP0.EQZ, DSP0.R61
TCELL4:OUT_Q2DSP0.R63
TCELL4:OUT_Q3DSP0.R65
TCELL4:OUT_Q4DSP1.R7
TCELL4:OUT_Q5DSP1.R9
TCELL4:OUT_Q6DSP1.R11
TCELL4:OUT_Q7DSP1.R19
TCELL5:IMUX_A0DSP0.C52
TCELL5:IMUX_A1DSP0.A14_1
TCELL5:IMUX_A2DSP0.B12_1
TCELL5:IMUX_A3DSP0.B16_1
TCELL5:IMUX_A4DSP1.C18
TCELL5:IMUX_A5DSP1.C22
TCELL5:IMUX_A6DSP1.A14_0
TCELL5:IMUX_A7DSP1.A17_0
TCELL5:IMUX_B0DSP0.C53
TCELL5:IMUX_B1DSP0.A15_1
TCELL5:IMUX_B2DSP0.B13_1
TCELL5:IMUX_B3DSP0.B17_1
TCELL5:IMUX_B4DSP1.C19
TCELL5:IMUX_B5DSP1.C23
TCELL5:IMUX_B6DSP1.A15_0
TCELL5:IMUX_C0DSP0.A12_1
TCELL5:IMUX_C1DSP0.A16_1
TCELL5:IMUX_C2DSP0.B14_1
TCELL5:IMUX_C3DSP1.C16
TCELL5:IMUX_C4DSP1.C20
TCELL5:IMUX_C5DSP1.A12_0
TCELL5:IMUX_C6DSP1.A16_0
TCELL5:IMUX_D0DSP0.A13_1
TCELL5:IMUX_D1DSP0.A17_1
TCELL5:IMUX_D2DSP0.B15_1
TCELL5:IMUX_D3DSP1.C17
TCELL5:IMUX_D4DSP1.C21
TCELL5:IMUX_D5DSP1.A13_0
TCELL5:IMUX_CLK1DSP0.OP0
TCELL5:IMUX_LSR0DSP1.SOURCEB_0
TCELL5:IMUX_LSR1DSP1.OP10
TCELL5:IMUX_LSR2DSP1.OP9
TCELL5:IMUX_CE0DSP0.CE2, DSP1.CE2
TCELL5:IMUX_CE1DSP1.SOURCEA_0
TCELL5:OUT_F0DSP0.R66
TCELL5:OUT_F1DSP0.R68
TCELL5:OUT_F2DSP0.R70
TCELL5:OUT_F3DSP1.R12
TCELL5:OUT_F4DSP1.R14
TCELL5:OUT_F5DSP1.R16
TCELL5:OUT_F6DSP1.R20
TCELL5:OUT_F7DSP1.R22
TCELL5:OUT_Q0DSP0.R67
TCELL5:OUT_Q1DSP0.R69
TCELL5:OUT_Q2DSP0.R71
TCELL5:OUT_Q3DSP1.R13
TCELL5:OUT_Q4DSP1.R15
TCELL5:OUT_Q5DSP1.R17
TCELL5:OUT_Q6DSP1.R21
TCELL5:OUT_Q7DSP1.R23
TCELL6:IMUX_A0DSP1.B0_0
TCELL6:IMUX_A1DSP1.B4_0
TCELL6:IMUX_A2DSP1.C26
TCELL6:IMUX_A3DSP1.C30
TCELL6:IMUX_A4DSP1.A0_1
TCELL6:IMUX_A5DSP1.A4_1
TCELL6:IMUX_A6DSP1.B2_1
TCELL6:IMUX_A7DSP1.B5_1
TCELL6:IMUX_B0DSP1.B1_0
TCELL6:IMUX_B1DSP1.B5_0
TCELL6:IMUX_B2DSP1.C27
TCELL6:IMUX_B3DSP1.C31
TCELL6:IMUX_B4DSP1.A1_1
TCELL6:IMUX_B5DSP1.A5_1
TCELL6:IMUX_B6DSP1.B3_1
TCELL6:IMUX_C0DSP1.B2_0
TCELL6:IMUX_C1DSP1.C24
TCELL6:IMUX_C2DSP1.C28
TCELL6:IMUX_C3DSP1.C32
TCELL6:IMUX_C4DSP1.A2_1
TCELL6:IMUX_C5DSP1.B0_1
TCELL6:IMUX_C6DSP1.B4_1
TCELL6:IMUX_D0DSP1.B3_0
TCELL6:IMUX_D1DSP1.C25
TCELL6:IMUX_D2DSP1.C29
TCELL6:IMUX_D3DSP1.C33
TCELL6:IMUX_D4DSP1.A3_1
TCELL6:IMUX_D5DSP1.B1_1
TCELL6:IMUX_CLK0DSP1.CLK0
TCELL6:IMUX_CLK1DSP1.CLK1
TCELL6:IMUX_LSR0DSP0.RST3, DSP1.RST3
TCELL6:IMUX_LSR1DSP1.OP8
TCELL6:IMUX_LSR2DSP1.OP7
TCELL6:IMUX_CE0DSP1.SIGNEDA_1
TCELL6:IMUX_CE1DSP1.SIGNEDB_1
TCELL6:OUT_F0DSP1.R24
TCELL6:OUT_F1DSP1.R26
TCELL6:OUT_F2DSP1.R36
TCELL6:OUT_F3DSP1.R38
TCELL6:OUT_F4DSP1.R40
TCELL6:OUT_F5DSP1.OVERUNDER, DSP1.R54
TCELL6:OUT_F6DSP1.OVER, DSP1.R56
TCELL6:OUT_F7DSP1.EQPAT, DSP1.R58
TCELL6:OUT_Q0DSP1.R25
TCELL6:OUT_Q1DSP1.R27
TCELL6:OUT_Q2DSP1.R37
TCELL6:OUT_Q3DSP1.R39
TCELL6:OUT_Q4DSP1.R41
TCELL6:OUT_Q5DSP1.R55, DSP1.UNDER
TCELL6:OUT_Q6DSP1.EQPATB, DSP1.R57
TCELL6:OUT_Q7DSP1.EQOM, DSP1.R59
TCELL7:IMUX_A0DSP1.B6_0
TCELL7:IMUX_A1DSP1.B10_0
TCELL7:IMUX_A2DSP1.A8_1
TCELL7:IMUX_A3DSP1.C37
TCELL7:IMUX_A4DSP1.C41
TCELL7:IMUX_A5DSP1.B7_1
TCELL7:IMUX_A6DSP1.A11_1
TCELL7:IMUX_A7DSP1.B11_1
TCELL7:IMUX_B0DSP1.B7_0
TCELL7:IMUX_B1DSP1.B11_0
TCELL7:IMUX_B2DSP1.C34
TCELL7:IMUX_B3DSP1.C38
TCELL7:IMUX_B4DSP1.C42
TCELL7:IMUX_B5DSP1.B8_1
TCELL7:IMUX_B6DSP1.B9_1
TCELL7:IMUX_C0DSP1.B8_0
TCELL7:IMUX_C1DSP1.A6_1
TCELL7:IMUX_C2DSP1.C35
TCELL7:IMUX_C3DSP1.C39
TCELL7:IMUX_C4DSP1.C43
TCELL7:IMUX_C5DSP1.A9_1
TCELL7:IMUX_C6DSP1.B10_1
TCELL7:IMUX_D0DSP1.B9_0
TCELL7:IMUX_D1DSP1.A7_1
TCELL7:IMUX_D2DSP1.C36
TCELL7:IMUX_D3DSP1.C40
TCELL7:IMUX_D4DSP1.B6_1
TCELL7:IMUX_D5DSP1.A10_1
TCELL7:IMUX_CLK0DSP1.CLK2
TCELL7:IMUX_CLK1DSP1.CLK3
TCELL7:IMUX_LSR0DSP1.SOURCEB_1
TCELL7:IMUX_LSR1DSP1.OP6
TCELL7:IMUX_LSR2DSP1.OP5
TCELL7:IMUX_CE0DSP0.CE3, DSP1.CE3
TCELL7:IMUX_CE1DSP1.SOURCEA_1
TCELL7:OUT_F0DSP1.R28
TCELL7:OUT_F1DSP1.R30
TCELL7:OUT_F2DSP1.R42
TCELL7:OUT_F3DSP1.R44
TCELL7:OUT_F4DSP1.R46
TCELL7:OUT_F5DSP1.EQZM, DSP1.R60
TCELL7:OUT_F6DSP1.R62
TCELL7:OUT_F7DSP1.R64
TCELL7:OUT_Q0DSP1.R29
TCELL7:OUT_Q1DSP1.R31
TCELL7:OUT_Q2DSP1.R43
TCELL7:OUT_Q3DSP1.R45
TCELL7:OUT_Q4DSP1.R47
TCELL7:OUT_Q5DSP1.EQZ, DSP1.R61
TCELL7:OUT_Q6DSP1.R63
TCELL7:OUT_Q7DSP1.R65
TCELL8:IMUX_A0DSP1.B12_0
TCELL8:IMUX_A1DSP1.B16_0
TCELL8:IMUX_A2DSP1.A14_1
TCELL8:IMUX_A3DSP1.C44
TCELL8:IMUX_A4DSP1.C48
TCELL8:IMUX_A5DSP1.C50
TCELL8:IMUX_A6DSP1.C52
TCELL8:IMUX_A7DSP1.B17_1
TCELL8:IMUX_B0DSP1.B13_0
TCELL8:IMUX_B1DSP1.B17_0
TCELL8:IMUX_B2DSP1.A15_1
TCELL8:IMUX_B3DSP1.C45
TCELL8:IMUX_B4DSP1.C49
TCELL8:IMUX_B5DSP1.C51
TCELL8:IMUX_B6DSP1.C53
TCELL8:IMUX_C0DSP1.B14_0
TCELL8:IMUX_C1DSP1.A12_1
TCELL8:IMUX_C2DSP1.A16_1
TCELL8:IMUX_C3DSP1.C46
TCELL8:IMUX_C4DSP1.B12_1
TCELL8:IMUX_C5DSP1.B14_1
TCELL8:IMUX_C6DSP1.B16_1
TCELL8:IMUX_D0DSP1.B15_0
TCELL8:IMUX_D1DSP1.A13_1
TCELL8:IMUX_D2DSP1.A17_1
TCELL8:IMUX_D3DSP1.C47
TCELL8:IMUX_D4DSP1.B13_1
TCELL8:IMUX_D5DSP1.B15_1
TCELL8:IMUX_LSR0DSP1.OP2
TCELL8:IMUX_LSR1DSP1.OP1
TCELL8:IMUX_LSR2DSP1.OP0
TCELL8:IMUX_CE0DSP1.OP4
TCELL8:IMUX_CE1DSP1.OP3
TCELL8:OUT_F0DSP1.R32
TCELL8:OUT_F1DSP1.R34
TCELL8:OUT_F2DSP1.R48
TCELL8:OUT_F3DSP1.R50
TCELL8:OUT_F4DSP1.R52
TCELL8:OUT_F5DSP1.R66
TCELL8:OUT_F6DSP1.R68
TCELL8:OUT_F7DSP1.R70
TCELL8:OUT_Q0DSP1.R33
TCELL8:OUT_Q1DSP1.R35
TCELL8:OUT_Q2DSP1.R49
TCELL8:OUT_Q3DSP1.R51
TCELL8:OUT_Q4DSP1.R53
TCELL8:OUT_Q5DSP1.R67
TCELL8:OUT_Q6DSP1.R69
TCELL8:OUT_Q7DSP1.R71