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Block RAM

Tile EBR

Cells: 3

Bel EBR0

ecp3 EBR bel EBR0
PinDirectionWires
ADA0inputTCELL0:IMUX_A4
ADA1inputTCELL0:IMUX_A5
ADA10inputTCELL0:IMUX_C4
ADA11inputTCELL0:IMUX_D5
ADA12inputTCELL0:IMUX_B5
ADA13inputTCELL0:IMUX_D4
ADA2inputTCELL0:IMUX_C5
ADA3inputTCELL0:IMUX_D3
ADA4inputTCELL0:IMUX_C2
ADA5inputTCELL1:IMUX_B1
ADA6inputTCELL1:IMUX_D5
ADA7inputTCELL0:IMUX_C3
ADA8inputTCELL1:IMUX_C5
ADA9inputTCELL0:IMUX_B4
ADB0inputTCELL0:IMUX_B0
ADB1inputTCELL0:IMUX_D0
ADB10inputTCELL1:IMUX_D0
ADB11inputTCELL1:IMUX_B0
ADB12inputTCELL0:IMUX_A3
ADB13inputTCELL0:IMUX_B3
ADB2inputTCELL0:IMUX_C0
ADB3inputTCELL1:IMUX_D2
ADB3WinputTCELL0:IMUX_A0
ADB4inputTCELL2:IMUX_B0
ADB5inputTCELL1:IMUX_A1
ADB6inputTCELL1:IMUX_D1
ADB7inputTCELL1:IMUX_A0
ADB8inputTCELL1:IMUX_C1
ADB9inputTCELL1:IMUX_C0
BHENABLEinputTCELL1:IMUX_C4
BLENABLEinputTCELL1:IMUX_D3
CEAinputTCELL1:IMUX_CE1
CEBinputTCELL2:IMUX_CE1
CLKAinputTCELL1:IMUX_CLK0
CLKBinputTCELL0:IMUX_CLK0
CSA0inputTCELL1:IMUX_LSR0
CSA1inputTCELL1:IMUX_LSR1
CSA2inputTCELL1:IMUX_LSR2
CSB0inputTCELL2:IMUX_LSR0
CSB1inputTCELL2:IMUX_LSR1
CSB2inputTCELL2:IMUX_LSR2
DIA0inputTCELL2:IMUX_D0
DIA1inputTCELL1:IMUX_B5
DIA10inputTCELL2:IMUX_A2
DIA11inputTCELL2:IMUX_D3
DIA12inputTCELL2:IMUX_A4
DIA13inputTCELL2:IMUX_B4
DIA14inputTCELL2:IMUX_B5
DIA15inputTCELL2:IMUX_A5
DIA16inputTCELL0:IMUX_C5
DIA17inputTCELL0:IMUX_D3
DIA2inputTCELL1:IMUX_A5
DIA3inputTCELL2:IMUX_A3
DIA4inputTCELL2:IMUX_D2
DIA5inputTCELL2:IMUX_B1
DIA6inputTCELL2:IMUX_A1
DIA7inputTCELL2:IMUX_A0
DIA8inputTCELL2:IMUX_C1
DIA9inputTCELL2:IMUX_C2
DIB0inputTCELL2:IMUX_D1
DIB1inputTCELL1:IMUX_B4
DIB10inputTCELL2:IMUX_C3
DIB11inputTCELL2:IMUX_B3
DIB12inputTCELL2:IMUX_D4
DIB13inputTCELL2:IMUX_C4
DIB14inputTCELL2:IMUX_C5
DIB15inputTCELL2:IMUX_D5
DIB16inputTCELL0:IMUX_C0
DIB17inputTCELL1:IMUX_D2
DIB2inputTCELL1:IMUX_D4
DIB3inputTCELL1:IMUX_A4
DIB4inputTCELL1:IMUX_B3
DIB5inputTCELL1:IMUX_A3
DIB6inputTCELL1:IMUX_C3
DIB7inputTCELL1:IMUX_A2
DIB8inputTCELL1:IMUX_B2
DIB9inputTCELL2:IMUX_B2
DOA0outputTCELL0:OUT_Q3
DOA1outputTCELL0:OUT_Q4
DOA10outputTCELL1:OUT_Q4
DOA11outputTCELL1:OUT_F5
DOA12outputTCELL2:OUT_Q0
DOA13outputTCELL2:OUT_F1
DOA14outputTCELL2:OUT_F2
DOA15outputTCELL2:OUT_Q3
DOA16outputTCELL2:OUT_Q4
DOA17outputTCELL2:OUT_Q5
DOA2outputTCELL0:OUT_Q5
DOA3outputTCELL0:OUT_Q1
DOA4outputTCELL0:OUT_F2
DOA5outputTCELL0:OUT_Q2
DOA6outputTCELL1:OUT_F0
DOA7outputTCELL1:OUT_F1
DOA8outputTCELL1:OUT_F2
DOA9outputTCELL1:OUT_Q3
DOB0outputTCELL0:OUT_F3
DOB1outputTCELL0:OUT_F4
DOB10outputTCELL1:OUT_F4
DOB11outputTCELL1:OUT_Q5
DOB12outputTCELL2:OUT_F0
DOB13outputTCELL2:OUT_Q1
DOB14outputTCELL2:OUT_Q2
DOB15outputTCELL2:OUT_F3
DOB16outputTCELL2:OUT_F4
DOB17outputTCELL2:OUT_F5
DOB2outputTCELL0:OUT_F5
DOB3outputTCELL0:OUT_Q0
DOB4outputTCELL0:OUT_F0
DOB5outputTCELL0:OUT_F1
DOB6outputTCELL1:OUT_Q0
DOB7outputTCELL1:OUT_Q1
DOB8outputTCELL1:OUT_Q2
DOB9outputTCELL1:OUT_F3
OCEAinputTCELL0:IMUX_CE0
OCEBinputTCELL1:IMUX_CE0
OCLKAinputTCELL0:IMUX_CLK1
OCLKBinputTCELL1:IMUX_CLK1
RSTAinputTCELL0:IMUX_LSR2
RSTBinputTCELL0:IMUX_LSR0
WEAinputTCELL2:IMUX_CE0
WEBinputTCELL0:IMUX_CE1

Bel wires

ecp3 EBR bel wires
WirePins
TCELL0:IMUX_A0EBR0.ADB3W
TCELL0:IMUX_A3EBR0.ADB12
TCELL0:IMUX_A4EBR0.ADA0
TCELL0:IMUX_A5EBR0.ADA1
TCELL0:IMUX_B0EBR0.ADB0
TCELL0:IMUX_B3EBR0.ADB13
TCELL0:IMUX_B4EBR0.ADA9
TCELL0:IMUX_B5EBR0.ADA12
TCELL0:IMUX_C0EBR0.ADB2, EBR0.DIB16
TCELL0:IMUX_C2EBR0.ADA4
TCELL0:IMUX_C3EBR0.ADA7
TCELL0:IMUX_C4EBR0.ADA10
TCELL0:IMUX_C5EBR0.ADA2, EBR0.DIA16
TCELL0:IMUX_D0EBR0.ADB1
TCELL0:IMUX_D3EBR0.ADA3, EBR0.DIA17
TCELL0:IMUX_D4EBR0.ADA13
TCELL0:IMUX_D5EBR0.ADA11
TCELL0:IMUX_CLK0EBR0.CLKB
TCELL0:IMUX_CLK1EBR0.OCLKA
TCELL0:IMUX_LSR0EBR0.RSTB
TCELL0:IMUX_LSR2EBR0.RSTA
TCELL0:IMUX_CE0EBR0.OCEA
TCELL0:IMUX_CE1EBR0.WEB
TCELL0:OUT_F0EBR0.DOB4
TCELL0:OUT_F1EBR0.DOB5
TCELL0:OUT_F2EBR0.DOA4
TCELL0:OUT_F3EBR0.DOB0
TCELL0:OUT_F4EBR0.DOB1
TCELL0:OUT_F5EBR0.DOB2
TCELL0:OUT_Q0EBR0.DOB3
TCELL0:OUT_Q1EBR0.DOA3
TCELL0:OUT_Q2EBR0.DOA5
TCELL0:OUT_Q3EBR0.DOA0
TCELL0:OUT_Q4EBR0.DOA1
TCELL0:OUT_Q5EBR0.DOA2
TCELL1:IMUX_A0EBR0.ADB7
TCELL1:IMUX_A1EBR0.ADB5
TCELL1:IMUX_A2EBR0.DIB7
TCELL1:IMUX_A3EBR0.DIB5
TCELL1:IMUX_A4EBR0.DIB3
TCELL1:IMUX_A5EBR0.DIA2
TCELL1:IMUX_B0EBR0.ADB11
TCELL1:IMUX_B1EBR0.ADA5
TCELL1:IMUX_B2EBR0.DIB8
TCELL1:IMUX_B3EBR0.DIB4
TCELL1:IMUX_B4EBR0.DIB1
TCELL1:IMUX_B5EBR0.DIA1
TCELL1:IMUX_C0EBR0.ADB9
TCELL1:IMUX_C1EBR0.ADB8
TCELL1:IMUX_C3EBR0.DIB6
TCELL1:IMUX_C4EBR0.BHENABLE
TCELL1:IMUX_C5EBR0.ADA8
TCELL1:IMUX_D0EBR0.ADB10
TCELL1:IMUX_D1EBR0.ADB6
TCELL1:IMUX_D2EBR0.ADB3, EBR0.DIB17
TCELL1:IMUX_D3EBR0.BLENABLE
TCELL1:IMUX_D4EBR0.DIB2
TCELL1:IMUX_D5EBR0.ADA6
TCELL1:IMUX_CLK0EBR0.CLKA
TCELL1:IMUX_CLK1EBR0.OCLKB
TCELL1:IMUX_LSR0EBR0.CSA0
TCELL1:IMUX_LSR1EBR0.CSA1
TCELL1:IMUX_LSR2EBR0.CSA2
TCELL1:IMUX_CE0EBR0.OCEB
TCELL1:IMUX_CE1EBR0.CEA
TCELL1:OUT_F0EBR0.DOA6
TCELL1:OUT_F1EBR0.DOA7
TCELL1:OUT_F2EBR0.DOA8
TCELL1:OUT_F3EBR0.DOB9
TCELL1:OUT_F4EBR0.DOB10
TCELL1:OUT_F5EBR0.DOA11
TCELL1:OUT_Q0EBR0.DOB6
TCELL1:OUT_Q1EBR0.DOB7
TCELL1:OUT_Q2EBR0.DOB8
TCELL1:OUT_Q3EBR0.DOA9
TCELL1:OUT_Q4EBR0.DOA10
TCELL1:OUT_Q5EBR0.DOB11
TCELL2:IMUX_A0EBR0.DIA7
TCELL2:IMUX_A1EBR0.DIA6
TCELL2:IMUX_A2EBR0.DIA10
TCELL2:IMUX_A3EBR0.DIA3
TCELL2:IMUX_A4EBR0.DIA12
TCELL2:IMUX_A5EBR0.DIA15
TCELL2:IMUX_B0EBR0.ADB4
TCELL2:IMUX_B1EBR0.DIA5
TCELL2:IMUX_B2EBR0.DIB9
TCELL2:IMUX_B3EBR0.DIB11
TCELL2:IMUX_B4EBR0.DIA13
TCELL2:IMUX_B5EBR0.DIA14
TCELL2:IMUX_C1EBR0.DIA8
TCELL2:IMUX_C2EBR0.DIA9
TCELL2:IMUX_C3EBR0.DIB10
TCELL2:IMUX_C4EBR0.DIB13
TCELL2:IMUX_C5EBR0.DIB14
TCELL2:IMUX_D0EBR0.DIA0
TCELL2:IMUX_D1EBR0.DIB0
TCELL2:IMUX_D2EBR0.DIA4
TCELL2:IMUX_D3EBR0.DIA11
TCELL2:IMUX_D4EBR0.DIB12
TCELL2:IMUX_D5EBR0.DIB15
TCELL2:IMUX_LSR0EBR0.CSB0
TCELL2:IMUX_LSR1EBR0.CSB1
TCELL2:IMUX_LSR2EBR0.CSB2
TCELL2:IMUX_CE0EBR0.WEA
TCELL2:IMUX_CE1EBR0.CEB
TCELL2:OUT_F0EBR0.DOB12
TCELL2:OUT_F1EBR0.DOA13
TCELL2:OUT_F2EBR0.DOA14
TCELL2:OUT_F3EBR0.DOB15
TCELL2:OUT_F4EBR0.DOB16
TCELL2:OUT_F5EBR0.DOB17
TCELL2:OUT_Q0EBR0.DOA12
TCELL2:OUT_Q1EBR0.DOB13
TCELL2:OUT_Q2EBR0.DOB14
TCELL2:OUT_Q3EBR0.DOA15
TCELL2:OUT_Q4EBR0.DOA16
TCELL2:OUT_Q5EBR0.DOA17