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Phase-Locked Loops

Tile PLL_W

Cells: 13

Bel PLL0

ecp3 PLL_W bel PLL0
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel wires

ecp3 PLL_W bel wires
WirePins
TCELL2:IMUX_CLK1PLL0.RESETK
TCELL3:IMUX_A0PLL0.DFPAI0
TCELL3:IMUX_A1PLL0.DFPAI2
TCELL3:IMUX_A3PLL0.TCLKI
TCELL3:IMUX_A4PLL0.FDA3
TCELL3:IMUX_B0PLL0.DRPAI0
TCELL3:IMUX_B1PLL0.DRPAI2
TCELL3:IMUX_B2PLL0.CLKI1
TCELL3:IMUX_B3PLL0.FDA0
TCELL3:IMUX_C0PLL0.DFPAI1
TCELL3:IMUX_C1PLL0.DFPAI3
TCELL3:IMUX_C2PLL0.WRDEL
TCELL3:IMUX_C3PLL0.FDA1
TCELL3:IMUX_D0PLL0.DRPAI1
TCELL3:IMUX_D1PLL0.DRPAI3
TCELL3:IMUX_D2PLL0.PWD
TCELL3:IMUX_D3PLL0.FDA2
TCELL3:IMUX_CLK0PLL0.CLKI2
TCELL3:IMUX_CLK1PLL0.CLKFB0
TCELL3:IMUX_CE0PLL0.CNTRST
TCELL3:IMUX_CE1PLL0.RESETM
TCELL3:OUT_F0PLL0.TESTOUT
TCELL3:OUT_F1PLL0.CLKOK2
TCELL3:OUT_F2PLL0.CLKOK
TCELL3:OUT_F3PLL0.CLKOS
TCELL3:OUT_F4PLL0.CLKOP
TCELL3:OUT_F5PLL0.UPLOCK
TCELL3:OUT_F6PLL0.DNLOCK
TCELL3:OUT_F7PLL0.LOCK
TCELL3:OUT_Q0PLL0.DFPAO0
TCELL3:OUT_Q1PLL0.DRPAO0
TCELL3:OUT_Q2PLL0.DFPAO1
TCELL3:OUT_Q3PLL0.DRPAO1
TCELL3:OUT_Q4PLL0.DFPAO2
TCELL3:OUT_Q5PLL0.DRPAO2
TCELL3:OUT_Q6PLL0.DFPAO3
TCELL3:OUT_Q7PLL0.DRPAO3

Tile PLL_E

Cells: 13

Bel PLL0

ecp3 PLL_E bel PLL0
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel wires

ecp3 PLL_E bel wires
WirePins
TCELL2:IMUX_CLK1PLL0.RESETK
TCELL3:IMUX_A0PLL0.DFPAI0
TCELL3:IMUX_A1PLL0.DFPAI2
TCELL3:IMUX_A3PLL0.TCLKI
TCELL3:IMUX_A4PLL0.FDA3
TCELL3:IMUX_B0PLL0.DRPAI0
TCELL3:IMUX_B1PLL0.DRPAI2
TCELL3:IMUX_B2PLL0.CLKI1
TCELL3:IMUX_B3PLL0.FDA0
TCELL3:IMUX_C0PLL0.DFPAI1
TCELL3:IMUX_C1PLL0.DFPAI3
TCELL3:IMUX_C2PLL0.WRDEL
TCELL3:IMUX_C3PLL0.FDA1
TCELL3:IMUX_D0PLL0.DRPAI1
TCELL3:IMUX_D1PLL0.DRPAI3
TCELL3:IMUX_D2PLL0.PWD
TCELL3:IMUX_D3PLL0.FDA2
TCELL3:IMUX_CLK0PLL0.CLKI2
TCELL3:IMUX_CLK1PLL0.CLKFB0
TCELL3:IMUX_CE0PLL0.CNTRST
TCELL3:IMUX_CE1PLL0.RESETM
TCELL3:OUT_F0PLL0.TESTOUT
TCELL3:OUT_F1PLL0.CLKOK2
TCELL3:OUT_F2PLL0.CLKOK
TCELL3:OUT_F3PLL0.CLKOS
TCELL3:OUT_F4PLL0.CLKOP
TCELL3:OUT_F5PLL0.UPLOCK
TCELL3:OUT_F6PLL0.DNLOCK
TCELL3:OUT_F7PLL0.LOCK
TCELL3:OUT_Q0PLL0.DFPAO0
TCELL3:OUT_Q1PLL0.DRPAO0
TCELL3:OUT_Q2PLL0.DFPAO1
TCELL3:OUT_Q3PLL0.DRPAO1
TCELL3:OUT_Q4PLL0.DFPAO2
TCELL3:OUT_Q5PLL0.DRPAO2
TCELL3:OUT_Q6PLL0.DFPAO3
TCELL3:OUT_Q7PLL0.DRPAO3

Tile PLL_A_W

Cells: 13

Bel PLL0

ecp3 PLL_A_W bel PLL0
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKFB6inputTCELL12:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKI5inputTCELL12:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel wires

ecp3 PLL_A_W bel wires
WirePins
TCELL2:IMUX_CLK1PLL0.RESETK
TCELL3:IMUX_A0PLL0.DFPAI0
TCELL3:IMUX_A1PLL0.DFPAI2
TCELL3:IMUX_A3PLL0.TCLKI
TCELL3:IMUX_A4PLL0.FDA3
TCELL3:IMUX_B0PLL0.DRPAI0
TCELL3:IMUX_B1PLL0.DRPAI2
TCELL3:IMUX_B2PLL0.CLKI1
TCELL3:IMUX_B3PLL0.FDA0
TCELL3:IMUX_C0PLL0.DFPAI1
TCELL3:IMUX_C1PLL0.DFPAI3
TCELL3:IMUX_C2PLL0.WRDEL
TCELL3:IMUX_C3PLL0.FDA1
TCELL3:IMUX_D0PLL0.DRPAI1
TCELL3:IMUX_D1PLL0.DRPAI3
TCELL3:IMUX_D2PLL0.PWD
TCELL3:IMUX_D3PLL0.FDA2
TCELL3:IMUX_CLK0PLL0.CLKI2
TCELL3:IMUX_CLK1PLL0.CLKFB0
TCELL3:IMUX_CE0PLL0.CNTRST
TCELL3:IMUX_CE1PLL0.RESETM
TCELL3:OUT_F0PLL0.TESTOUT
TCELL3:OUT_F1PLL0.CLKOK2
TCELL3:OUT_F2PLL0.CLKOK
TCELL3:OUT_F3PLL0.CLKOS
TCELL3:OUT_F4PLL0.CLKOP
TCELL3:OUT_F5PLL0.UPLOCK
TCELL3:OUT_F6PLL0.DNLOCK
TCELL3:OUT_F7PLL0.LOCK
TCELL3:OUT_Q0PLL0.DFPAO0
TCELL3:OUT_Q1PLL0.DRPAO0
TCELL3:OUT_Q2PLL0.DFPAO1
TCELL3:OUT_Q3PLL0.DRPAO1
TCELL3:OUT_Q4PLL0.DFPAO2
TCELL3:OUT_Q5PLL0.DRPAO2
TCELL3:OUT_Q6PLL0.DFPAO3
TCELL3:OUT_Q7PLL0.DRPAO3
TCELL12:IMUX_CLK0PLL0.CLKI5
TCELL12:IMUX_CLK1PLL0.CLKFB6

Tile PLL_A_E

Cells: 13

Bel PLL0

ecp3 PLL_A_E bel PLL0
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKFB6inputTCELL12:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKI5inputTCELL12:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel wires

ecp3 PLL_A_E bel wires
WirePins
TCELL2:IMUX_CLK1PLL0.RESETK
TCELL3:IMUX_A0PLL0.DFPAI0
TCELL3:IMUX_A1PLL0.DFPAI2
TCELL3:IMUX_A3PLL0.TCLKI
TCELL3:IMUX_A4PLL0.FDA3
TCELL3:IMUX_B0PLL0.DRPAI0
TCELL3:IMUX_B1PLL0.DRPAI2
TCELL3:IMUX_B2PLL0.CLKI1
TCELL3:IMUX_B3PLL0.FDA0
TCELL3:IMUX_C0PLL0.DFPAI1
TCELL3:IMUX_C1PLL0.DFPAI3
TCELL3:IMUX_C2PLL0.WRDEL
TCELL3:IMUX_C3PLL0.FDA1
TCELL3:IMUX_D0PLL0.DRPAI1
TCELL3:IMUX_D1PLL0.DRPAI3
TCELL3:IMUX_D2PLL0.PWD
TCELL3:IMUX_D3PLL0.FDA2
TCELL3:IMUX_CLK0PLL0.CLKI2
TCELL3:IMUX_CLK1PLL0.CLKFB0
TCELL3:IMUX_CE0PLL0.CNTRST
TCELL3:IMUX_CE1PLL0.RESETM
TCELL3:OUT_F0PLL0.TESTOUT
TCELL3:OUT_F1PLL0.CLKOK2
TCELL3:OUT_F2PLL0.CLKOK
TCELL3:OUT_F3PLL0.CLKOS
TCELL3:OUT_F4PLL0.CLKOP
TCELL3:OUT_F5PLL0.UPLOCK
TCELL3:OUT_F6PLL0.DNLOCK
TCELL3:OUT_F7PLL0.LOCK
TCELL3:OUT_Q0PLL0.DFPAO0
TCELL3:OUT_Q1PLL0.DRPAO0
TCELL3:OUT_Q2PLL0.DFPAO1
TCELL3:OUT_Q3PLL0.DRPAO1
TCELL3:OUT_Q4PLL0.DFPAO2
TCELL3:OUT_Q5PLL0.DRPAO2
TCELL3:OUT_Q6PLL0.DFPAO3
TCELL3:OUT_Q7PLL0.DRPAO3
TCELL12:IMUX_CLK0PLL0.CLKI5
TCELL12:IMUX_CLK1PLL0.CLKFB6

Tile PLL_DLL_W

Cells: 18

Bel DQSDLL

ecp3 PLL_DLL_W bel DQSDLL
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
LOCKoutputTCELL2:OUT_F0
RSTinputTCELL2:IMUX_CE1
UDDCNTLNinputTCELL2:IMUX_CE0

Bel DQSDLLTEST

ecp3 PLL_DLL_W bel DQSDLLTEST
PinDirectionWires
SDOUT0outputTCELL16:OUT_F2
SDOUT1outputTCELL16:OUT_Q2
SDOUT2outputTCELL16:OUT_F4
SDOUT3outputTCELL16:OUT_F5
SDOUT4outputTCELL16:OUT_Q3
SDOUT5outputTCELL16:OUT_Q1
SDOUT6outputTCELL16:OUT_F3

Bel PLL0

ecp3 PLL_DLL_W bel PLL0
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel DLL0

ecp3 PLL_DLL_W bel DLL0
PinDirectionWires
ALUHOLDinputTCELL14:IMUX_C1
CIB_DCPS_0inputTCELL12:IMUX_C4
CIB_DCPS_1inputTCELL12:IMUX_D4
CIB_DCPS_2inputTCELL12:IMUX_A5
CIB_DCPS_3inputTCELL12:IMUX_B5
CIB_DCPS_4inputTCELL12:IMUX_C5
CIB_DCPS_5inputTCELL12:IMUX_D5
CLKFB3inputTCELL14:IMUX_CLK1
CLKI1inputTCELL14:IMUX_CLK0
CLKI2inputTCELL14:IMUX_B2
CLKOPoutputTCELL14:OUT_F1
CLKOSoutputTCELL14:OUT_F2
DCNTL0outputTCELL12:OUT_F0
DCNTL1outputTCELL12:OUT_F1
DCNTL2outputTCELL12:OUT_F2
DCNTL3outputTCELL12:OUT_F3
DCNTL4outputTCELL12:OUT_F4
DCNTL5outputTCELL12:OUT_F5
DIFFoutputTCELL14:OUT_F3
GRAYI0inputTCELL14:IMUX_A0
GRAYI1inputTCELL14:IMUX_B0
GRAYI2inputTCELL14:IMUX_C0
GRAYI3inputTCELL14:IMUX_D0
GRAYI4inputTCELL14:IMUX_A1
GRAYI5inputTCELL14:IMUX_B1
GRAYO0outputTCELL14:OUT_Q0
GRAYO1outputTCELL14:OUT_Q1
GRAYO2outputTCELL14:OUT_Q2
GRAYO3outputTCELL14:OUT_Q3
GRAYO4outputTCELL14:OUT_Q4
GRAYO5outputTCELL14:OUT_Q5
INCIinputTCELL14:IMUX_D1
INCOoutputTCELL14:OUT_F5
LOCKoutputTCELL14:OUT_F4
RSTNinputTCELL14:IMUX_CE0
UDDCNTLinputTCELL14:IMUX_A2

Bel DLLDEL0

ecp3 PLL_DLL_W bel DLLDEL0
PinDirectionWires
BYPASSoutputTCELL13:OUT_F4
CLKOoutputTCELL13:OUT_F5

Bel CLKDIV0

ecp3 PLL_DLL_W bel CLKDIV0
PinDirectionWires
CDIV1outputTCELL13:OUT_F0
CDIV2outputTCELL13:OUT_F1
CDIV4outputTCELL13:OUT_F2
CDIV8outputTCELL13:OUT_F3
RELEASEinputTCELL13:IMUX_CE0
RSTinputTCELL13:IMUX_CE1

Bel ECLK_ALT_ROOT

ecp3 PLL_DLL_W bel ECLK_ALT_ROOT
PinDirectionWires
ECLK0_INinputTCELL14:IMUX_CLK0
ECLK1_INinputTCELL14:IMUX_CLK1

Bel wires

ecp3 PLL_DLL_W bel wires
WirePins
TCELL2:IMUX_CLK0DQSDLL.CLK
TCELL2:IMUX_CLK1PLL0.RESETK
TCELL2:IMUX_CE0DQSDLL.UDDCNTLN
TCELL2:IMUX_CE1DQSDLL.RST
TCELL2:OUT_F0DQSDLL.LOCK
TCELL3:IMUX_A0PLL0.DFPAI0
TCELL3:IMUX_A1PLL0.DFPAI2
TCELL3:IMUX_A3PLL0.TCLKI
TCELL3:IMUX_A4PLL0.FDA3
TCELL3:IMUX_B0PLL0.DRPAI0
TCELL3:IMUX_B1PLL0.DRPAI2
TCELL3:IMUX_B2PLL0.CLKI1
TCELL3:IMUX_B3PLL0.FDA0
TCELL3:IMUX_C0PLL0.DFPAI1
TCELL3:IMUX_C1PLL0.DFPAI3
TCELL3:IMUX_C2PLL0.WRDEL
TCELL3:IMUX_C3PLL0.FDA1
TCELL3:IMUX_D0PLL0.DRPAI1
TCELL3:IMUX_D1PLL0.DRPAI3
TCELL3:IMUX_D2PLL0.PWD
TCELL3:IMUX_D3PLL0.FDA2
TCELL3:IMUX_CLK0PLL0.CLKI2
TCELL3:IMUX_CLK1PLL0.CLKFB0
TCELL3:IMUX_CE0PLL0.CNTRST
TCELL3:IMUX_CE1PLL0.RESETM
TCELL3:OUT_F0PLL0.TESTOUT
TCELL3:OUT_F1PLL0.CLKOK2
TCELL3:OUT_F2PLL0.CLKOK
TCELL3:OUT_F3PLL0.CLKOS
TCELL3:OUT_F4PLL0.CLKOP
TCELL3:OUT_F5PLL0.UPLOCK
TCELL3:OUT_F6PLL0.DNLOCK
TCELL3:OUT_F7PLL0.LOCK
TCELL3:OUT_Q0PLL0.DFPAO0
TCELL3:OUT_Q1PLL0.DRPAO0
TCELL3:OUT_Q2PLL0.DFPAO1
TCELL3:OUT_Q3PLL0.DRPAO1
TCELL3:OUT_Q4PLL0.DFPAO2
TCELL3:OUT_Q5PLL0.DRPAO2
TCELL3:OUT_Q6PLL0.DFPAO3
TCELL3:OUT_Q7PLL0.DRPAO3
TCELL12:IMUX_A5DLL0.CIB_DCPS_2
TCELL12:IMUX_B5DLL0.CIB_DCPS_3
TCELL12:IMUX_C4DLL0.CIB_DCPS_0
TCELL12:IMUX_C5DLL0.CIB_DCPS_4
TCELL12:IMUX_D4DLL0.CIB_DCPS_1
TCELL12:IMUX_D5DLL0.CIB_DCPS_5
TCELL12:OUT_F0DLL0.DCNTL0
TCELL12:OUT_F1DLL0.DCNTL1
TCELL12:OUT_F2DLL0.DCNTL2
TCELL12:OUT_F3DLL0.DCNTL3
TCELL12:OUT_F4DLL0.DCNTL4
TCELL12:OUT_F5DLL0.DCNTL5
TCELL13:IMUX_CE0CLKDIV0.RELEASE
TCELL13:IMUX_CE1CLKDIV0.RST
TCELL13:OUT_F0CLKDIV0.CDIV1
TCELL13:OUT_F1CLKDIV0.CDIV2
TCELL13:OUT_F2CLKDIV0.CDIV4
TCELL13:OUT_F3CLKDIV0.CDIV8
TCELL13:OUT_F4DLLDEL0.BYPASS
TCELL13:OUT_F5DLLDEL0.CLKO
TCELL14:IMUX_A0DLL0.GRAYI0
TCELL14:IMUX_A1DLL0.GRAYI4
TCELL14:IMUX_A2DLL0.UDDCNTL
TCELL14:IMUX_B0DLL0.GRAYI1
TCELL14:IMUX_B1DLL0.GRAYI5
TCELL14:IMUX_B2DLL0.CLKI2
TCELL14:IMUX_C0DLL0.GRAYI2
TCELL14:IMUX_C1DLL0.ALUHOLD
TCELL14:IMUX_D0DLL0.GRAYI3
TCELL14:IMUX_D1DLL0.INCI
TCELL14:IMUX_CLK0DLL0.CLKI1, ECLK_ALT_ROOT.ECLK0_IN
TCELL14:IMUX_CLK1DLL0.CLKFB3, ECLK_ALT_ROOT.ECLK1_IN
TCELL14:IMUX_CE0DLL0.RSTN
TCELL14:OUT_F1DLL0.CLKOP
TCELL14:OUT_F2DLL0.CLKOS
TCELL14:OUT_F3DLL0.DIFF
TCELL14:OUT_F4DLL0.LOCK
TCELL14:OUT_F5DLL0.INCO
TCELL14:OUT_Q0DLL0.GRAYO0
TCELL14:OUT_Q1DLL0.GRAYO1
TCELL14:OUT_Q2DLL0.GRAYO2
TCELL14:OUT_Q3DLL0.GRAYO3
TCELL14:OUT_Q4DLL0.GRAYO4
TCELL14:OUT_Q5DLL0.GRAYO5
TCELL16:OUT_F2DQSDLLTEST.SDOUT0
TCELL16:OUT_F3DQSDLLTEST.SDOUT6
TCELL16:OUT_F4DQSDLLTEST.SDOUT2
TCELL16:OUT_F5DQSDLLTEST.SDOUT3
TCELL16:OUT_Q1DQSDLLTEST.SDOUT5
TCELL16:OUT_Q2DQSDLLTEST.SDOUT1
TCELL16:OUT_Q3DQSDLLTEST.SDOUT4

Tile PLL_DLL_E

Cells: 18

Bel DQSDLL

ecp3 PLL_DLL_E bel DQSDLL
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
LOCKoutputTCELL2:OUT_F0
RSTinputTCELL2:IMUX_CE1
UDDCNTLNinputTCELL2:IMUX_CE0

Bel DQSDLLTEST

ecp3 PLL_DLL_E bel DQSDLLTEST
PinDirectionWires
SDOUT0outputTCELL16:OUT_F2
SDOUT1outputTCELL16:OUT_Q2
SDOUT2outputTCELL16:OUT_F4
SDOUT3outputTCELL16:OUT_F5
SDOUT4outputTCELL16:OUT_Q3
SDOUT5outputTCELL16:OUT_Q1
SDOUT6outputTCELL16:OUT_F3

Bel PLL0

ecp3 PLL_DLL_E bel PLL0
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel DLL0

ecp3 PLL_DLL_E bel DLL0
PinDirectionWires
ALUHOLDinputTCELL14:IMUX_C1
CIB_DCPS_0inputTCELL12:IMUX_C4
CIB_DCPS_1inputTCELL12:IMUX_D4
CIB_DCPS_2inputTCELL12:IMUX_A5
CIB_DCPS_3inputTCELL12:IMUX_B5
CIB_DCPS_4inputTCELL12:IMUX_C5
CIB_DCPS_5inputTCELL12:IMUX_D5
CLKFB3inputTCELL14:IMUX_CLK1
CLKI1inputTCELL14:IMUX_CLK0
CLKI2inputTCELL14:IMUX_B2
CLKOPoutputTCELL14:OUT_F1
CLKOSoutputTCELL14:OUT_F2
DCNTL0outputTCELL12:OUT_F0
DCNTL1outputTCELL12:OUT_F1
DCNTL2outputTCELL12:OUT_F2
DCNTL3outputTCELL12:OUT_F3
DCNTL4outputTCELL12:OUT_F4
DCNTL5outputTCELL12:OUT_F5
DIFFoutputTCELL14:OUT_F3
GRAYI0inputTCELL14:IMUX_A0
GRAYI1inputTCELL14:IMUX_B0
GRAYI2inputTCELL14:IMUX_C0
GRAYI3inputTCELL14:IMUX_D0
GRAYI4inputTCELL14:IMUX_A1
GRAYI5inputTCELL14:IMUX_B1
GRAYO0outputTCELL14:OUT_Q0
GRAYO1outputTCELL14:OUT_Q1
GRAYO2outputTCELL14:OUT_Q2
GRAYO3outputTCELL14:OUT_Q3
GRAYO4outputTCELL14:OUT_Q4
GRAYO5outputTCELL14:OUT_Q5
INCIinputTCELL14:IMUX_D1
INCOoutputTCELL14:OUT_F5
LOCKoutputTCELL14:OUT_F4
RSTNinputTCELL14:IMUX_CE0
UDDCNTLinputTCELL14:IMUX_A2

Bel DLLDEL0

ecp3 PLL_DLL_E bel DLLDEL0
PinDirectionWires
BYPASSoutputTCELL13:OUT_F4
CLKOoutputTCELL13:OUT_F5

Bel CLKDIV0

ecp3 PLL_DLL_E bel CLKDIV0
PinDirectionWires
CDIV1outputTCELL13:OUT_F0
CDIV2outputTCELL13:OUT_F1
CDIV4outputTCELL13:OUT_F2
CDIV8outputTCELL13:OUT_F3
RELEASEinputTCELL13:IMUX_CE0
RSTinputTCELL13:IMUX_CE1

Bel ECLK_ALT_ROOT

ecp3 PLL_DLL_E bel ECLK_ALT_ROOT
PinDirectionWires
ECLK0_INinputTCELL14:IMUX_CLK0
ECLK1_INinputTCELL14:IMUX_CLK1

Bel wires

ecp3 PLL_DLL_E bel wires
WirePins
TCELL2:IMUX_CLK0DQSDLL.CLK
TCELL2:IMUX_CLK1PLL0.RESETK
TCELL2:IMUX_CE0DQSDLL.UDDCNTLN
TCELL2:IMUX_CE1DQSDLL.RST
TCELL2:OUT_F0DQSDLL.LOCK
TCELL3:IMUX_A0PLL0.DFPAI0
TCELL3:IMUX_A1PLL0.DFPAI2
TCELL3:IMUX_A3PLL0.TCLKI
TCELL3:IMUX_A4PLL0.FDA3
TCELL3:IMUX_B0PLL0.DRPAI0
TCELL3:IMUX_B1PLL0.DRPAI2
TCELL3:IMUX_B2PLL0.CLKI1
TCELL3:IMUX_B3PLL0.FDA0
TCELL3:IMUX_C0PLL0.DFPAI1
TCELL3:IMUX_C1PLL0.DFPAI3
TCELL3:IMUX_C2PLL0.WRDEL
TCELL3:IMUX_C3PLL0.FDA1
TCELL3:IMUX_D0PLL0.DRPAI1
TCELL3:IMUX_D1PLL0.DRPAI3
TCELL3:IMUX_D2PLL0.PWD
TCELL3:IMUX_D3PLL0.FDA2
TCELL3:IMUX_CLK0PLL0.CLKI2
TCELL3:IMUX_CLK1PLL0.CLKFB0
TCELL3:IMUX_CE0PLL0.CNTRST
TCELL3:IMUX_CE1PLL0.RESETM
TCELL3:OUT_F0PLL0.TESTOUT
TCELL3:OUT_F1PLL0.CLKOK2
TCELL3:OUT_F2PLL0.CLKOK
TCELL3:OUT_F3PLL0.CLKOS
TCELL3:OUT_F4PLL0.CLKOP
TCELL3:OUT_F5PLL0.UPLOCK
TCELL3:OUT_F6PLL0.DNLOCK
TCELL3:OUT_F7PLL0.LOCK
TCELL3:OUT_Q0PLL0.DFPAO0
TCELL3:OUT_Q1PLL0.DRPAO0
TCELL3:OUT_Q2PLL0.DFPAO1
TCELL3:OUT_Q3PLL0.DRPAO1
TCELL3:OUT_Q4PLL0.DFPAO2
TCELL3:OUT_Q5PLL0.DRPAO2
TCELL3:OUT_Q6PLL0.DFPAO3
TCELL3:OUT_Q7PLL0.DRPAO3
TCELL12:IMUX_A5DLL0.CIB_DCPS_2
TCELL12:IMUX_B5DLL0.CIB_DCPS_3
TCELL12:IMUX_C4DLL0.CIB_DCPS_0
TCELL12:IMUX_C5DLL0.CIB_DCPS_4
TCELL12:IMUX_D4DLL0.CIB_DCPS_1
TCELL12:IMUX_D5DLL0.CIB_DCPS_5
TCELL12:OUT_F0DLL0.DCNTL0
TCELL12:OUT_F1DLL0.DCNTL1
TCELL12:OUT_F2DLL0.DCNTL2
TCELL12:OUT_F3DLL0.DCNTL3
TCELL12:OUT_F4DLL0.DCNTL4
TCELL12:OUT_F5DLL0.DCNTL5
TCELL13:IMUX_CE0CLKDIV0.RELEASE
TCELL13:IMUX_CE1CLKDIV0.RST
TCELL13:OUT_F0CLKDIV0.CDIV1
TCELL13:OUT_F1CLKDIV0.CDIV2
TCELL13:OUT_F2CLKDIV0.CDIV4
TCELL13:OUT_F3CLKDIV0.CDIV8
TCELL13:OUT_F4DLLDEL0.BYPASS
TCELL13:OUT_F5DLLDEL0.CLKO
TCELL14:IMUX_A0DLL0.GRAYI0
TCELL14:IMUX_A1DLL0.GRAYI4
TCELL14:IMUX_A2DLL0.UDDCNTL
TCELL14:IMUX_B0DLL0.GRAYI1
TCELL14:IMUX_B1DLL0.GRAYI5
TCELL14:IMUX_B2DLL0.CLKI2
TCELL14:IMUX_C0DLL0.GRAYI2
TCELL14:IMUX_C1DLL0.ALUHOLD
TCELL14:IMUX_D0DLL0.GRAYI3
TCELL14:IMUX_D1DLL0.INCI
TCELL14:IMUX_CLK0DLL0.CLKI1, ECLK_ALT_ROOT.ECLK0_IN
TCELL14:IMUX_CLK1DLL0.CLKFB3, ECLK_ALT_ROOT.ECLK1_IN
TCELL14:IMUX_CE0DLL0.RSTN
TCELL14:OUT_F1DLL0.CLKOP
TCELL14:OUT_F2DLL0.CLKOS
TCELL14:OUT_F3DLL0.DIFF
TCELL14:OUT_F4DLL0.LOCK
TCELL14:OUT_F5DLL0.INCO
TCELL14:OUT_Q0DLL0.GRAYO0
TCELL14:OUT_Q1DLL0.GRAYO1
TCELL14:OUT_Q2DLL0.GRAYO2
TCELL14:OUT_Q3DLL0.GRAYO3
TCELL14:OUT_Q4DLL0.GRAYO4
TCELL14:OUT_Q5DLL0.GRAYO5
TCELL16:OUT_F2DQSDLLTEST.SDOUT0
TCELL16:OUT_F3DQSDLLTEST.SDOUT6
TCELL16:OUT_F4DQSDLLTEST.SDOUT2
TCELL16:OUT_F5DQSDLLTEST.SDOUT3
TCELL16:OUT_Q1DQSDLLTEST.SDOUT5
TCELL16:OUT_Q2DQSDLLTEST.SDOUT1
TCELL16:OUT_Q3DQSDLLTEST.SDOUT4

Tile PLL_DLL_A_W

Cells: 18

Bel DQSDLL

ecp3 PLL_DLL_A_W bel DQSDLL
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
LOCKoutputTCELL2:OUT_F0
RSTinputTCELL2:IMUX_CE1
UDDCNTLNinputTCELL2:IMUX_CE0

Bel DQSDLLTEST

ecp3 PLL_DLL_A_W bel DQSDLLTEST
PinDirectionWires
SDOUT0outputTCELL16:OUT_F2
SDOUT1outputTCELL16:OUT_Q2
SDOUT2outputTCELL16:OUT_F4
SDOUT3outputTCELL16:OUT_F5
SDOUT4outputTCELL16:OUT_Q3
SDOUT5outputTCELL16:OUT_Q1
SDOUT6outputTCELL16:OUT_F3

Bel PLL0

ecp3 PLL_DLL_A_W bel PLL0
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKFB6inputTCELL15:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKI5inputTCELL15:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel DLL0

ecp3 PLL_DLL_A_W bel DLL0
PinDirectionWires
ALUHOLDinputTCELL14:IMUX_C1
CIB_DCPS_0inputTCELL12:IMUX_C4
CIB_DCPS_1inputTCELL12:IMUX_D4
CIB_DCPS_2inputTCELL12:IMUX_A5
CIB_DCPS_3inputTCELL12:IMUX_B5
CIB_DCPS_4inputTCELL12:IMUX_C5
CIB_DCPS_5inputTCELL12:IMUX_D5
CLKFB3inputTCELL14:IMUX_CLK1
CLKFB5inputTCELL17:IMUX_CLK1
CLKI1inputTCELL14:IMUX_CLK0
CLKI2inputTCELL14:IMUX_B2
CLKI5inputTCELL17:IMUX_CLK0
CLKOPoutputTCELL14:OUT_F1
CLKOSoutputTCELL14:OUT_F2
DCNTL0outputTCELL12:OUT_F0
DCNTL1outputTCELL12:OUT_F1
DCNTL2outputTCELL12:OUT_F2
DCNTL3outputTCELL12:OUT_F3
DCNTL4outputTCELL12:OUT_F4
DCNTL5outputTCELL12:OUT_F5
DIFFoutputTCELL14:OUT_F3
GRAYI0inputTCELL14:IMUX_A0
GRAYI1inputTCELL14:IMUX_B0
GRAYI2inputTCELL14:IMUX_C0
GRAYI3inputTCELL14:IMUX_D0
GRAYI4inputTCELL14:IMUX_A1
GRAYI5inputTCELL14:IMUX_B1
GRAYO0outputTCELL14:OUT_Q0
GRAYO1outputTCELL14:OUT_Q1
GRAYO2outputTCELL14:OUT_Q2
GRAYO3outputTCELL14:OUT_Q3
GRAYO4outputTCELL14:OUT_Q4
GRAYO5outputTCELL14:OUT_Q5
INCIinputTCELL14:IMUX_D1
INCOoutputTCELL14:OUT_F5
LOCKoutputTCELL14:OUT_F4
RSTNinputTCELL14:IMUX_CE0
UDDCNTLinputTCELL14:IMUX_A2

Bel DLLDEL0

ecp3 PLL_DLL_A_W bel DLLDEL0
PinDirectionWires
BYPASSoutputTCELL13:OUT_F4
CLKOoutputTCELL13:OUT_F5

Bel CLKDIV0

ecp3 PLL_DLL_A_W bel CLKDIV0
PinDirectionWires
CDIV1outputTCELL13:OUT_F0
CDIV2outputTCELL13:OUT_F1
CDIV4outputTCELL13:OUT_F2
CDIV8outputTCELL13:OUT_F3
RELEASEinputTCELL13:IMUX_CE0
RSTinputTCELL13:IMUX_CE1

Bel ECLK_ALT_ROOT

ecp3 PLL_DLL_A_W bel ECLK_ALT_ROOT
PinDirectionWires
ECLK0_INinputTCELL14:IMUX_CLK0
ECLK1_INinputTCELL14:IMUX_CLK1

Bel wires

ecp3 PLL_DLL_A_W bel wires
WirePins
TCELL2:IMUX_CLK0DQSDLL.CLK
TCELL2:IMUX_CLK1PLL0.RESETK
TCELL2:IMUX_CE0DQSDLL.UDDCNTLN
TCELL2:IMUX_CE1DQSDLL.RST
TCELL2:OUT_F0DQSDLL.LOCK
TCELL3:IMUX_A0PLL0.DFPAI0
TCELL3:IMUX_A1PLL0.DFPAI2
TCELL3:IMUX_A3PLL0.TCLKI
TCELL3:IMUX_A4PLL0.FDA3
TCELL3:IMUX_B0PLL0.DRPAI0
TCELL3:IMUX_B1PLL0.DRPAI2
TCELL3:IMUX_B2PLL0.CLKI1
TCELL3:IMUX_B3PLL0.FDA0
TCELL3:IMUX_C0PLL0.DFPAI1
TCELL3:IMUX_C1PLL0.DFPAI3
TCELL3:IMUX_C2PLL0.WRDEL
TCELL3:IMUX_C3PLL0.FDA1
TCELL3:IMUX_D0PLL0.DRPAI1
TCELL3:IMUX_D1PLL0.DRPAI3
TCELL3:IMUX_D2PLL0.PWD
TCELL3:IMUX_D3PLL0.FDA2
TCELL3:IMUX_CLK0PLL0.CLKI2
TCELL3:IMUX_CLK1PLL0.CLKFB0
TCELL3:IMUX_CE0PLL0.CNTRST
TCELL3:IMUX_CE1PLL0.RESETM
TCELL3:OUT_F0PLL0.TESTOUT
TCELL3:OUT_F1PLL0.CLKOK2
TCELL3:OUT_F2PLL0.CLKOK
TCELL3:OUT_F3PLL0.CLKOS
TCELL3:OUT_F4PLL0.CLKOP
TCELL3:OUT_F5PLL0.UPLOCK
TCELL3:OUT_F6PLL0.DNLOCK
TCELL3:OUT_F7PLL0.LOCK
TCELL3:OUT_Q0PLL0.DFPAO0
TCELL3:OUT_Q1PLL0.DRPAO0
TCELL3:OUT_Q2PLL0.DFPAO1
TCELL3:OUT_Q3PLL0.DRPAO1
TCELL3:OUT_Q4PLL0.DFPAO2
TCELL3:OUT_Q5PLL0.DRPAO2
TCELL3:OUT_Q6PLL0.DFPAO3
TCELL3:OUT_Q7PLL0.DRPAO3
TCELL12:IMUX_A5DLL0.CIB_DCPS_2
TCELL12:IMUX_B5DLL0.CIB_DCPS_3
TCELL12:IMUX_C4DLL0.CIB_DCPS_0
TCELL12:IMUX_C5DLL0.CIB_DCPS_4
TCELL12:IMUX_D4DLL0.CIB_DCPS_1
TCELL12:IMUX_D5DLL0.CIB_DCPS_5
TCELL12:OUT_F0DLL0.DCNTL0
TCELL12:OUT_F1DLL0.DCNTL1
TCELL12:OUT_F2DLL0.DCNTL2
TCELL12:OUT_F3DLL0.DCNTL3
TCELL12:OUT_F4DLL0.DCNTL4
TCELL12:OUT_F5DLL0.DCNTL5
TCELL13:IMUX_CE0CLKDIV0.RELEASE
TCELL13:IMUX_CE1CLKDIV0.RST
TCELL13:OUT_F0CLKDIV0.CDIV1
TCELL13:OUT_F1CLKDIV0.CDIV2
TCELL13:OUT_F2CLKDIV0.CDIV4
TCELL13:OUT_F3CLKDIV0.CDIV8
TCELL13:OUT_F4DLLDEL0.BYPASS
TCELL13:OUT_F5DLLDEL0.CLKO
TCELL14:IMUX_A0DLL0.GRAYI0
TCELL14:IMUX_A1DLL0.GRAYI4
TCELL14:IMUX_A2DLL0.UDDCNTL
TCELL14:IMUX_B0DLL0.GRAYI1
TCELL14:IMUX_B1DLL0.GRAYI5
TCELL14:IMUX_B2DLL0.CLKI2
TCELL14:IMUX_C0DLL0.GRAYI2
TCELL14:IMUX_C1DLL0.ALUHOLD
TCELL14:IMUX_D0DLL0.GRAYI3
TCELL14:IMUX_D1DLL0.INCI
TCELL14:IMUX_CLK0DLL0.CLKI1, ECLK_ALT_ROOT.ECLK0_IN
TCELL14:IMUX_CLK1DLL0.CLKFB3, ECLK_ALT_ROOT.ECLK1_IN
TCELL14:IMUX_CE0DLL0.RSTN
TCELL14:OUT_F1DLL0.CLKOP
TCELL14:OUT_F2DLL0.CLKOS
TCELL14:OUT_F3DLL0.DIFF
TCELL14:OUT_F4DLL0.LOCK
TCELL14:OUT_F5DLL0.INCO
TCELL14:OUT_Q0DLL0.GRAYO0
TCELL14:OUT_Q1DLL0.GRAYO1
TCELL14:OUT_Q2DLL0.GRAYO2
TCELL14:OUT_Q3DLL0.GRAYO3
TCELL14:OUT_Q4DLL0.GRAYO4
TCELL14:OUT_Q5DLL0.GRAYO5
TCELL15:IMUX_CLK0PLL0.CLKI5
TCELL15:IMUX_CLK1PLL0.CLKFB6
TCELL16:OUT_F2DQSDLLTEST.SDOUT0
TCELL16:OUT_F3DQSDLLTEST.SDOUT6
TCELL16:OUT_F4DQSDLLTEST.SDOUT2
TCELL16:OUT_F5DQSDLLTEST.SDOUT3
TCELL16:OUT_Q1DQSDLLTEST.SDOUT5
TCELL16:OUT_Q2DQSDLLTEST.SDOUT1
TCELL16:OUT_Q3DQSDLLTEST.SDOUT4
TCELL17:IMUX_CLK0DLL0.CLKI5
TCELL17:IMUX_CLK1DLL0.CLKFB5

Tile PLL_DLL_A_E

Cells: 18

Bel DQSDLL

ecp3 PLL_DLL_A_E bel DQSDLL
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
LOCKoutputTCELL2:OUT_F0
RSTinputTCELL2:IMUX_CE1
UDDCNTLNinputTCELL2:IMUX_CE0

Bel DQSDLLTEST

ecp3 PLL_DLL_A_E bel DQSDLLTEST
PinDirectionWires
SDOUT0outputTCELL16:OUT_F2
SDOUT1outputTCELL16:OUT_Q2
SDOUT2outputTCELL16:OUT_F4
SDOUT3outputTCELL16:OUT_F5
SDOUT4outputTCELL16:OUT_Q3
SDOUT5outputTCELL16:OUT_Q1
SDOUT6outputTCELL16:OUT_F3

Bel PLL0

ecp3 PLL_DLL_A_E bel PLL0
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKFB6inputTCELL15:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKI5inputTCELL15:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel DLL0

ecp3 PLL_DLL_A_E bel DLL0
PinDirectionWires
ALUHOLDinputTCELL14:IMUX_C1
CIB_DCPS_0inputTCELL12:IMUX_C4
CIB_DCPS_1inputTCELL12:IMUX_D4
CIB_DCPS_2inputTCELL12:IMUX_A5
CIB_DCPS_3inputTCELL12:IMUX_B5
CIB_DCPS_4inputTCELL12:IMUX_C5
CIB_DCPS_5inputTCELL12:IMUX_D5
CLKFB3inputTCELL14:IMUX_CLK1
CLKFB5inputTCELL17:IMUX_CLK1
CLKI1inputTCELL14:IMUX_CLK0
CLKI2inputTCELL14:IMUX_B2
CLKI5inputTCELL17:IMUX_CLK0
CLKOPoutputTCELL14:OUT_F1
CLKOSoutputTCELL14:OUT_F2
DCNTL0outputTCELL12:OUT_F0
DCNTL1outputTCELL12:OUT_F1
DCNTL2outputTCELL12:OUT_F2
DCNTL3outputTCELL12:OUT_F3
DCNTL4outputTCELL12:OUT_F4
DCNTL5outputTCELL12:OUT_F5
DIFFoutputTCELL14:OUT_F3
GRAYI0inputTCELL14:IMUX_A0
GRAYI1inputTCELL14:IMUX_B0
GRAYI2inputTCELL14:IMUX_C0
GRAYI3inputTCELL14:IMUX_D0
GRAYI4inputTCELL14:IMUX_A1
GRAYI5inputTCELL14:IMUX_B1
GRAYO0outputTCELL14:OUT_Q0
GRAYO1outputTCELL14:OUT_Q1
GRAYO2outputTCELL14:OUT_Q2
GRAYO3outputTCELL14:OUT_Q3
GRAYO4outputTCELL14:OUT_Q4
GRAYO5outputTCELL14:OUT_Q5
INCIinputTCELL14:IMUX_D1
INCOoutputTCELL14:OUT_F5
LOCKoutputTCELL14:OUT_F4
RSTNinputTCELL14:IMUX_CE0
UDDCNTLinputTCELL14:IMUX_A2

Bel DLLDEL0

ecp3 PLL_DLL_A_E bel DLLDEL0
PinDirectionWires
BYPASSoutputTCELL13:OUT_F4
CLKOoutputTCELL13:OUT_F5

Bel CLKDIV0

ecp3 PLL_DLL_A_E bel CLKDIV0
PinDirectionWires
CDIV1outputTCELL13:OUT_F0
CDIV2outputTCELL13:OUT_F1
CDIV4outputTCELL13:OUT_F2
CDIV8outputTCELL13:OUT_F3
RELEASEinputTCELL13:IMUX_CE0
RSTinputTCELL13:IMUX_CE1

Bel ECLK_ALT_ROOT

ecp3 PLL_DLL_A_E bel ECLK_ALT_ROOT
PinDirectionWires
ECLK0_INinputTCELL14:IMUX_CLK0
ECLK1_INinputTCELL14:IMUX_CLK1

Bel wires

ecp3 PLL_DLL_A_E bel wires
WirePins
TCELL2:IMUX_CLK0DQSDLL.CLK
TCELL2:IMUX_CLK1PLL0.RESETK
TCELL2:IMUX_CE0DQSDLL.UDDCNTLN
TCELL2:IMUX_CE1DQSDLL.RST
TCELL2:OUT_F0DQSDLL.LOCK
TCELL3:IMUX_A0PLL0.DFPAI0
TCELL3:IMUX_A1PLL0.DFPAI2
TCELL3:IMUX_A3PLL0.TCLKI
TCELL3:IMUX_A4PLL0.FDA3
TCELL3:IMUX_B0PLL0.DRPAI0
TCELL3:IMUX_B1PLL0.DRPAI2
TCELL3:IMUX_B2PLL0.CLKI1
TCELL3:IMUX_B3PLL0.FDA0
TCELL3:IMUX_C0PLL0.DFPAI1
TCELL3:IMUX_C1PLL0.DFPAI3
TCELL3:IMUX_C2PLL0.WRDEL
TCELL3:IMUX_C3PLL0.FDA1
TCELL3:IMUX_D0PLL0.DRPAI1
TCELL3:IMUX_D1PLL0.DRPAI3
TCELL3:IMUX_D2PLL0.PWD
TCELL3:IMUX_D3PLL0.FDA2
TCELL3:IMUX_CLK0PLL0.CLKI2
TCELL3:IMUX_CLK1PLL0.CLKFB0
TCELL3:IMUX_CE0PLL0.CNTRST
TCELL3:IMUX_CE1PLL0.RESETM
TCELL3:OUT_F0PLL0.TESTOUT
TCELL3:OUT_F1PLL0.CLKOK2
TCELL3:OUT_F2PLL0.CLKOK
TCELL3:OUT_F3PLL0.CLKOS
TCELL3:OUT_F4PLL0.CLKOP
TCELL3:OUT_F5PLL0.UPLOCK
TCELL3:OUT_F6PLL0.DNLOCK
TCELL3:OUT_F7PLL0.LOCK
TCELL3:OUT_Q0PLL0.DFPAO0
TCELL3:OUT_Q1PLL0.DRPAO0
TCELL3:OUT_Q2PLL0.DFPAO1
TCELL3:OUT_Q3PLL0.DRPAO1
TCELL3:OUT_Q4PLL0.DFPAO2
TCELL3:OUT_Q5PLL0.DRPAO2
TCELL3:OUT_Q6PLL0.DFPAO3
TCELL3:OUT_Q7PLL0.DRPAO3
TCELL12:IMUX_A5DLL0.CIB_DCPS_2
TCELL12:IMUX_B5DLL0.CIB_DCPS_3
TCELL12:IMUX_C4DLL0.CIB_DCPS_0
TCELL12:IMUX_C5DLL0.CIB_DCPS_4
TCELL12:IMUX_D4DLL0.CIB_DCPS_1
TCELL12:IMUX_D5DLL0.CIB_DCPS_5
TCELL12:OUT_F0DLL0.DCNTL0
TCELL12:OUT_F1DLL0.DCNTL1
TCELL12:OUT_F2DLL0.DCNTL2
TCELL12:OUT_F3DLL0.DCNTL3
TCELL12:OUT_F4DLL0.DCNTL4
TCELL12:OUT_F5DLL0.DCNTL5
TCELL13:IMUX_CE0CLKDIV0.RELEASE
TCELL13:IMUX_CE1CLKDIV0.RST
TCELL13:OUT_F0CLKDIV0.CDIV1
TCELL13:OUT_F1CLKDIV0.CDIV2
TCELL13:OUT_F2CLKDIV0.CDIV4
TCELL13:OUT_F3CLKDIV0.CDIV8
TCELL13:OUT_F4DLLDEL0.BYPASS
TCELL13:OUT_F5DLLDEL0.CLKO
TCELL14:IMUX_A0DLL0.GRAYI0
TCELL14:IMUX_A1DLL0.GRAYI4
TCELL14:IMUX_A2DLL0.UDDCNTL
TCELL14:IMUX_B0DLL0.GRAYI1
TCELL14:IMUX_B1DLL0.GRAYI5
TCELL14:IMUX_B2DLL0.CLKI2
TCELL14:IMUX_C0DLL0.GRAYI2
TCELL14:IMUX_C1DLL0.ALUHOLD
TCELL14:IMUX_D0DLL0.GRAYI3
TCELL14:IMUX_D1DLL0.INCI
TCELL14:IMUX_CLK0DLL0.CLKI1, ECLK_ALT_ROOT.ECLK0_IN
TCELL14:IMUX_CLK1DLL0.CLKFB3, ECLK_ALT_ROOT.ECLK1_IN
TCELL14:IMUX_CE0DLL0.RSTN
TCELL14:OUT_F1DLL0.CLKOP
TCELL14:OUT_F2DLL0.CLKOS
TCELL14:OUT_F3DLL0.DIFF
TCELL14:OUT_F4DLL0.LOCK
TCELL14:OUT_F5DLL0.INCO
TCELL14:OUT_Q0DLL0.GRAYO0
TCELL14:OUT_Q1DLL0.GRAYO1
TCELL14:OUT_Q2DLL0.GRAYO2
TCELL14:OUT_Q3DLL0.GRAYO3
TCELL14:OUT_Q4DLL0.GRAYO4
TCELL14:OUT_Q5DLL0.GRAYO5
TCELL15:IMUX_CLK0PLL0.CLKI5
TCELL15:IMUX_CLK1PLL0.CLKFB6
TCELL16:OUT_F2DQSDLLTEST.SDOUT0
TCELL16:OUT_F3DQSDLLTEST.SDOUT6
TCELL16:OUT_F4DQSDLLTEST.SDOUT2
TCELL16:OUT_F5DQSDLLTEST.SDOUT3
TCELL16:OUT_Q1DQSDLLTEST.SDOUT5
TCELL16:OUT_Q2DQSDLLTEST.SDOUT1
TCELL16:OUT_Q3DQSDLLTEST.SDOUT4
TCELL17:IMUX_CLK0DLL0.CLKI5
TCELL17:IMUX_CLK1DLL0.CLKFB5