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Phase-Locked Loops

Tile PLL_W

Cells: 13

Bel PLL

ecp3 PLL_W bel PLL
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel wires

ecp3 PLL_W bel wires
WirePins
TCELL2:IMUX_CLK1PLL.RESETK
TCELL3:IMUX_A0PLL.DFPAI0
TCELL3:IMUX_A1PLL.DFPAI2
TCELL3:IMUX_A3PLL.TCLKI
TCELL3:IMUX_A4PLL.FDA3
TCELL3:IMUX_B0PLL.DRPAI0
TCELL3:IMUX_B1PLL.DRPAI2
TCELL3:IMUX_B2PLL.CLKI1
TCELL3:IMUX_B3PLL.FDA0
TCELL3:IMUX_C0PLL.DFPAI1
TCELL3:IMUX_C1PLL.DFPAI3
TCELL3:IMUX_C2PLL.WRDEL
TCELL3:IMUX_C3PLL.FDA1
TCELL3:IMUX_D0PLL.DRPAI1
TCELL3:IMUX_D1PLL.DRPAI3
TCELL3:IMUX_D2PLL.PWD
TCELL3:IMUX_D3PLL.FDA2
TCELL3:IMUX_CLK0PLL.CLKI2
TCELL3:IMUX_CLK1PLL.CLKFB0
TCELL3:IMUX_CE0PLL.CNTRST
TCELL3:IMUX_CE1PLL.RESETM
TCELL3:OUT_F0PLL.TESTOUT
TCELL3:OUT_F1PLL.CLKOK2
TCELL3:OUT_F2PLL.CLKOK
TCELL3:OUT_F3PLL.CLKOS
TCELL3:OUT_F4PLL.CLKOP
TCELL3:OUT_F5PLL.UPLOCK
TCELL3:OUT_F6PLL.DNLOCK
TCELL3:OUT_F7PLL.LOCK
TCELL3:OUT_Q0PLL.DFPAO0
TCELL3:OUT_Q1PLL.DRPAO0
TCELL3:OUT_Q2PLL.DFPAO1
TCELL3:OUT_Q3PLL.DRPAO1
TCELL3:OUT_Q4PLL.DFPAO2
TCELL3:OUT_Q5PLL.DRPAO2
TCELL3:OUT_Q6PLL.DFPAO3
TCELL3:OUT_Q7PLL.DRPAO3

Tile PLL_E

Cells: 13

Bel PLL

ecp3 PLL_E bel PLL
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel wires

ecp3 PLL_E bel wires
WirePins
TCELL2:IMUX_CLK1PLL.RESETK
TCELL3:IMUX_A0PLL.DFPAI0
TCELL3:IMUX_A1PLL.DFPAI2
TCELL3:IMUX_A3PLL.TCLKI
TCELL3:IMUX_A4PLL.FDA3
TCELL3:IMUX_B0PLL.DRPAI0
TCELL3:IMUX_B1PLL.DRPAI2
TCELL3:IMUX_B2PLL.CLKI1
TCELL3:IMUX_B3PLL.FDA0
TCELL3:IMUX_C0PLL.DFPAI1
TCELL3:IMUX_C1PLL.DFPAI3
TCELL3:IMUX_C2PLL.WRDEL
TCELL3:IMUX_C3PLL.FDA1
TCELL3:IMUX_D0PLL.DRPAI1
TCELL3:IMUX_D1PLL.DRPAI3
TCELL3:IMUX_D2PLL.PWD
TCELL3:IMUX_D3PLL.FDA2
TCELL3:IMUX_CLK0PLL.CLKI2
TCELL3:IMUX_CLK1PLL.CLKFB0
TCELL3:IMUX_CE0PLL.CNTRST
TCELL3:IMUX_CE1PLL.RESETM
TCELL3:OUT_F0PLL.TESTOUT
TCELL3:OUT_F1PLL.CLKOK2
TCELL3:OUT_F2PLL.CLKOK
TCELL3:OUT_F3PLL.CLKOS
TCELL3:OUT_F4PLL.CLKOP
TCELL3:OUT_F5PLL.UPLOCK
TCELL3:OUT_F6PLL.DNLOCK
TCELL3:OUT_F7PLL.LOCK
TCELL3:OUT_Q0PLL.DFPAO0
TCELL3:OUT_Q1PLL.DRPAO0
TCELL3:OUT_Q2PLL.DFPAO1
TCELL3:OUT_Q3PLL.DRPAO1
TCELL3:OUT_Q4PLL.DFPAO2
TCELL3:OUT_Q5PLL.DRPAO2
TCELL3:OUT_Q6PLL.DFPAO3
TCELL3:OUT_Q7PLL.DRPAO3

Tile PLL_A_W

Cells: 13

Bel PLL

ecp3 PLL_A_W bel PLL
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKFB6inputTCELL12:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKI5inputTCELL12:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel wires

ecp3 PLL_A_W bel wires
WirePins
TCELL2:IMUX_CLK1PLL.RESETK
TCELL3:IMUX_A0PLL.DFPAI0
TCELL3:IMUX_A1PLL.DFPAI2
TCELL3:IMUX_A3PLL.TCLKI
TCELL3:IMUX_A4PLL.FDA3
TCELL3:IMUX_B0PLL.DRPAI0
TCELL3:IMUX_B1PLL.DRPAI2
TCELL3:IMUX_B2PLL.CLKI1
TCELL3:IMUX_B3PLL.FDA0
TCELL3:IMUX_C0PLL.DFPAI1
TCELL3:IMUX_C1PLL.DFPAI3
TCELL3:IMUX_C2PLL.WRDEL
TCELL3:IMUX_C3PLL.FDA1
TCELL3:IMUX_D0PLL.DRPAI1
TCELL3:IMUX_D1PLL.DRPAI3
TCELL3:IMUX_D2PLL.PWD
TCELL3:IMUX_D3PLL.FDA2
TCELL3:IMUX_CLK0PLL.CLKI2
TCELL3:IMUX_CLK1PLL.CLKFB0
TCELL3:IMUX_CE0PLL.CNTRST
TCELL3:IMUX_CE1PLL.RESETM
TCELL3:OUT_F0PLL.TESTOUT
TCELL3:OUT_F1PLL.CLKOK2
TCELL3:OUT_F2PLL.CLKOK
TCELL3:OUT_F3PLL.CLKOS
TCELL3:OUT_F4PLL.CLKOP
TCELL3:OUT_F5PLL.UPLOCK
TCELL3:OUT_F6PLL.DNLOCK
TCELL3:OUT_F7PLL.LOCK
TCELL3:OUT_Q0PLL.DFPAO0
TCELL3:OUT_Q1PLL.DRPAO0
TCELL3:OUT_Q2PLL.DFPAO1
TCELL3:OUT_Q3PLL.DRPAO1
TCELL3:OUT_Q4PLL.DFPAO2
TCELL3:OUT_Q5PLL.DRPAO2
TCELL3:OUT_Q6PLL.DFPAO3
TCELL3:OUT_Q7PLL.DRPAO3
TCELL12:IMUX_CLK0PLL.CLKI5
TCELL12:IMUX_CLK1PLL.CLKFB6

Tile PLL_A_E

Cells: 13

Bel PLL

ecp3 PLL_A_E bel PLL
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKFB6inputTCELL12:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKI5inputTCELL12:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel wires

ecp3 PLL_A_E bel wires
WirePins
TCELL2:IMUX_CLK1PLL.RESETK
TCELL3:IMUX_A0PLL.DFPAI0
TCELL3:IMUX_A1PLL.DFPAI2
TCELL3:IMUX_A3PLL.TCLKI
TCELL3:IMUX_A4PLL.FDA3
TCELL3:IMUX_B0PLL.DRPAI0
TCELL3:IMUX_B1PLL.DRPAI2
TCELL3:IMUX_B2PLL.CLKI1
TCELL3:IMUX_B3PLL.FDA0
TCELL3:IMUX_C0PLL.DFPAI1
TCELL3:IMUX_C1PLL.DFPAI3
TCELL3:IMUX_C2PLL.WRDEL
TCELL3:IMUX_C3PLL.FDA1
TCELL3:IMUX_D0PLL.DRPAI1
TCELL3:IMUX_D1PLL.DRPAI3
TCELL3:IMUX_D2PLL.PWD
TCELL3:IMUX_D3PLL.FDA2
TCELL3:IMUX_CLK0PLL.CLKI2
TCELL3:IMUX_CLK1PLL.CLKFB0
TCELL3:IMUX_CE0PLL.CNTRST
TCELL3:IMUX_CE1PLL.RESETM
TCELL3:OUT_F0PLL.TESTOUT
TCELL3:OUT_F1PLL.CLKOK2
TCELL3:OUT_F2PLL.CLKOK
TCELL3:OUT_F3PLL.CLKOS
TCELL3:OUT_F4PLL.CLKOP
TCELL3:OUT_F5PLL.UPLOCK
TCELL3:OUT_F6PLL.DNLOCK
TCELL3:OUT_F7PLL.LOCK
TCELL3:OUT_Q0PLL.DFPAO0
TCELL3:OUT_Q1PLL.DRPAO0
TCELL3:OUT_Q2PLL.DFPAO1
TCELL3:OUT_Q3PLL.DRPAO1
TCELL3:OUT_Q4PLL.DFPAO2
TCELL3:OUT_Q5PLL.DRPAO2
TCELL3:OUT_Q6PLL.DFPAO3
TCELL3:OUT_Q7PLL.DRPAO3
TCELL12:IMUX_CLK0PLL.CLKI5
TCELL12:IMUX_CLK1PLL.CLKFB6

Tile PLL_DLL_W

Cells: 18

Bel DQSDLL

ecp3 PLL_DLL_W bel DQSDLL
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
LOCKoutputTCELL2:OUT_F0
RSTinputTCELL2:IMUX_CE1
UDDCNTLNinputTCELL2:IMUX_CE0

Bel DQSDLLTEST

ecp3 PLL_DLL_W bel DQSDLLTEST
PinDirectionWires
SDOUT0outputTCELL16:OUT_F2
SDOUT1outputTCELL16:OUT_Q2
SDOUT2outputTCELL16:OUT_F4
SDOUT3outputTCELL16:OUT_F5
SDOUT4outputTCELL16:OUT_Q3
SDOUT5outputTCELL16:OUT_Q1
SDOUT6outputTCELL16:OUT_F3

Bel PLL

ecp3 PLL_DLL_W bel PLL
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel DLL

ecp3 PLL_DLL_W bel DLL
PinDirectionWires
ALUHOLDinputTCELL14:IMUX_C1
CIB_DCPS_0inputTCELL12:IMUX_C4
CIB_DCPS_1inputTCELL12:IMUX_D4
CIB_DCPS_2inputTCELL12:IMUX_A5
CIB_DCPS_3inputTCELL12:IMUX_B5
CIB_DCPS_4inputTCELL12:IMUX_C5
CIB_DCPS_5inputTCELL12:IMUX_D5
CLKFB3inputTCELL14:IMUX_CLK1
CLKI1inputTCELL14:IMUX_CLK0
CLKI2inputTCELL14:IMUX_B2
CLKOPoutputTCELL14:OUT_F1
CLKOSoutputTCELL14:OUT_F2
DCNTL0outputTCELL12:OUT_F0
DCNTL1outputTCELL12:OUT_F1
DCNTL2outputTCELL12:OUT_F2
DCNTL3outputTCELL12:OUT_F3
DCNTL4outputTCELL12:OUT_F4
DCNTL5outputTCELL12:OUT_F5
DIFFoutputTCELL14:OUT_F3
GRAYI0inputTCELL14:IMUX_A0
GRAYI1inputTCELL14:IMUX_B0
GRAYI2inputTCELL14:IMUX_C0
GRAYI3inputTCELL14:IMUX_D0
GRAYI4inputTCELL14:IMUX_A1
GRAYI5inputTCELL14:IMUX_B1
GRAYO0outputTCELL14:OUT_Q0
GRAYO1outputTCELL14:OUT_Q1
GRAYO2outputTCELL14:OUT_Q2
GRAYO3outputTCELL14:OUT_Q3
GRAYO4outputTCELL14:OUT_Q4
GRAYO5outputTCELL14:OUT_Q5
INCIinputTCELL14:IMUX_D1
INCOoutputTCELL14:OUT_F5
LOCKoutputTCELL14:OUT_F4
RSTNinputTCELL14:IMUX_CE0
UDDCNTLinputTCELL14:IMUX_A2

Bel DLLDEL

ecp3 PLL_DLL_W bel DLLDEL
PinDirectionWires
BYPASSoutputTCELL13:OUT_F4
CLKOoutputTCELL13:OUT_F5

Bel CLKDIV

ecp3 PLL_DLL_W bel CLKDIV
PinDirectionWires
CDIV1outputTCELL13:OUT_F0
CDIV2outputTCELL13:OUT_F1
CDIV4outputTCELL13:OUT_F2
CDIV8outputTCELL13:OUT_F3
RELEASEinputTCELL13:IMUX_CE0
RSTinputTCELL13:IMUX_CE1

Bel ECLK_ALT_ROOT

ecp3 PLL_DLL_W bel ECLK_ALT_ROOT
PinDirectionWires
ECLK0_INinputTCELL14:IMUX_CLK0
ECLK1_INinputTCELL14:IMUX_CLK1

Bel wires

ecp3 PLL_DLL_W bel wires
WirePins
TCELL2:IMUX_CLK0DQSDLL.CLK
TCELL2:IMUX_CLK1PLL.RESETK
TCELL2:IMUX_CE0DQSDLL.UDDCNTLN
TCELL2:IMUX_CE1DQSDLL.RST
TCELL2:OUT_F0DQSDLL.LOCK
TCELL3:IMUX_A0PLL.DFPAI0
TCELL3:IMUX_A1PLL.DFPAI2
TCELL3:IMUX_A3PLL.TCLKI
TCELL3:IMUX_A4PLL.FDA3
TCELL3:IMUX_B0PLL.DRPAI0
TCELL3:IMUX_B1PLL.DRPAI2
TCELL3:IMUX_B2PLL.CLKI1
TCELL3:IMUX_B3PLL.FDA0
TCELL3:IMUX_C0PLL.DFPAI1
TCELL3:IMUX_C1PLL.DFPAI3
TCELL3:IMUX_C2PLL.WRDEL
TCELL3:IMUX_C3PLL.FDA1
TCELL3:IMUX_D0PLL.DRPAI1
TCELL3:IMUX_D1PLL.DRPAI3
TCELL3:IMUX_D2PLL.PWD
TCELL3:IMUX_D3PLL.FDA2
TCELL3:IMUX_CLK0PLL.CLKI2
TCELL3:IMUX_CLK1PLL.CLKFB0
TCELL3:IMUX_CE0PLL.CNTRST
TCELL3:IMUX_CE1PLL.RESETM
TCELL3:OUT_F0PLL.TESTOUT
TCELL3:OUT_F1PLL.CLKOK2
TCELL3:OUT_F2PLL.CLKOK
TCELL3:OUT_F3PLL.CLKOS
TCELL3:OUT_F4PLL.CLKOP
TCELL3:OUT_F5PLL.UPLOCK
TCELL3:OUT_F6PLL.DNLOCK
TCELL3:OUT_F7PLL.LOCK
TCELL3:OUT_Q0PLL.DFPAO0
TCELL3:OUT_Q1PLL.DRPAO0
TCELL3:OUT_Q2PLL.DFPAO1
TCELL3:OUT_Q3PLL.DRPAO1
TCELL3:OUT_Q4PLL.DFPAO2
TCELL3:OUT_Q5PLL.DRPAO2
TCELL3:OUT_Q6PLL.DFPAO3
TCELL3:OUT_Q7PLL.DRPAO3
TCELL12:IMUX_A5DLL.CIB_DCPS_2
TCELL12:IMUX_B5DLL.CIB_DCPS_3
TCELL12:IMUX_C4DLL.CIB_DCPS_0
TCELL12:IMUX_C5DLL.CIB_DCPS_4
TCELL12:IMUX_D4DLL.CIB_DCPS_1
TCELL12:IMUX_D5DLL.CIB_DCPS_5
TCELL12:OUT_F0DLL.DCNTL0
TCELL12:OUT_F1DLL.DCNTL1
TCELL12:OUT_F2DLL.DCNTL2
TCELL12:OUT_F3DLL.DCNTL3
TCELL12:OUT_F4DLL.DCNTL4
TCELL12:OUT_F5DLL.DCNTL5
TCELL13:IMUX_CE0CLKDIV.RELEASE
TCELL13:IMUX_CE1CLKDIV.RST
TCELL13:OUT_F0CLKDIV.CDIV1
TCELL13:OUT_F1CLKDIV.CDIV2
TCELL13:OUT_F2CLKDIV.CDIV4
TCELL13:OUT_F3CLKDIV.CDIV8
TCELL13:OUT_F4DLLDEL.BYPASS
TCELL13:OUT_F5DLLDEL.CLKO
TCELL14:IMUX_A0DLL.GRAYI0
TCELL14:IMUX_A1DLL.GRAYI4
TCELL14:IMUX_A2DLL.UDDCNTL
TCELL14:IMUX_B0DLL.GRAYI1
TCELL14:IMUX_B1DLL.GRAYI5
TCELL14:IMUX_B2DLL.CLKI2
TCELL14:IMUX_C0DLL.GRAYI2
TCELL14:IMUX_C1DLL.ALUHOLD
TCELL14:IMUX_D0DLL.GRAYI3
TCELL14:IMUX_D1DLL.INCI
TCELL14:IMUX_CLK0DLL.CLKI1, ECLK_ALT_ROOT.ECLK0_IN
TCELL14:IMUX_CLK1DLL.CLKFB3, ECLK_ALT_ROOT.ECLK1_IN
TCELL14:IMUX_CE0DLL.RSTN
TCELL14:OUT_F1DLL.CLKOP
TCELL14:OUT_F2DLL.CLKOS
TCELL14:OUT_F3DLL.DIFF
TCELL14:OUT_F4DLL.LOCK
TCELL14:OUT_F5DLL.INCO
TCELL14:OUT_Q0DLL.GRAYO0
TCELL14:OUT_Q1DLL.GRAYO1
TCELL14:OUT_Q2DLL.GRAYO2
TCELL14:OUT_Q3DLL.GRAYO3
TCELL14:OUT_Q4DLL.GRAYO4
TCELL14:OUT_Q5DLL.GRAYO5
TCELL16:OUT_F2DQSDLLTEST.SDOUT0
TCELL16:OUT_F3DQSDLLTEST.SDOUT6
TCELL16:OUT_F4DQSDLLTEST.SDOUT2
TCELL16:OUT_F5DQSDLLTEST.SDOUT3
TCELL16:OUT_Q1DQSDLLTEST.SDOUT5
TCELL16:OUT_Q2DQSDLLTEST.SDOUT1
TCELL16:OUT_Q3DQSDLLTEST.SDOUT4

Tile PLL_DLL_E

Cells: 18

Bel DQSDLL

ecp3 PLL_DLL_E bel DQSDLL
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
LOCKoutputTCELL2:OUT_F0
RSTinputTCELL2:IMUX_CE1
UDDCNTLNinputTCELL2:IMUX_CE0

Bel DQSDLLTEST

ecp3 PLL_DLL_E bel DQSDLLTEST
PinDirectionWires
SDOUT0outputTCELL16:OUT_F2
SDOUT1outputTCELL16:OUT_Q2
SDOUT2outputTCELL16:OUT_F4
SDOUT3outputTCELL16:OUT_F5
SDOUT4outputTCELL16:OUT_Q3
SDOUT5outputTCELL16:OUT_Q1
SDOUT6outputTCELL16:OUT_F3

Bel PLL

ecp3 PLL_DLL_E bel PLL
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel DLL

ecp3 PLL_DLL_E bel DLL
PinDirectionWires
ALUHOLDinputTCELL14:IMUX_C1
CIB_DCPS_0inputTCELL12:IMUX_C4
CIB_DCPS_1inputTCELL12:IMUX_D4
CIB_DCPS_2inputTCELL12:IMUX_A5
CIB_DCPS_3inputTCELL12:IMUX_B5
CIB_DCPS_4inputTCELL12:IMUX_C5
CIB_DCPS_5inputTCELL12:IMUX_D5
CLKFB3inputTCELL14:IMUX_CLK1
CLKI1inputTCELL14:IMUX_CLK0
CLKI2inputTCELL14:IMUX_B2
CLKOPoutputTCELL14:OUT_F1
CLKOSoutputTCELL14:OUT_F2
DCNTL0outputTCELL12:OUT_F0
DCNTL1outputTCELL12:OUT_F1
DCNTL2outputTCELL12:OUT_F2
DCNTL3outputTCELL12:OUT_F3
DCNTL4outputTCELL12:OUT_F4
DCNTL5outputTCELL12:OUT_F5
DIFFoutputTCELL14:OUT_F3
GRAYI0inputTCELL14:IMUX_A0
GRAYI1inputTCELL14:IMUX_B0
GRAYI2inputTCELL14:IMUX_C0
GRAYI3inputTCELL14:IMUX_D0
GRAYI4inputTCELL14:IMUX_A1
GRAYI5inputTCELL14:IMUX_B1
GRAYO0outputTCELL14:OUT_Q0
GRAYO1outputTCELL14:OUT_Q1
GRAYO2outputTCELL14:OUT_Q2
GRAYO3outputTCELL14:OUT_Q3
GRAYO4outputTCELL14:OUT_Q4
GRAYO5outputTCELL14:OUT_Q5
INCIinputTCELL14:IMUX_D1
INCOoutputTCELL14:OUT_F5
LOCKoutputTCELL14:OUT_F4
RSTNinputTCELL14:IMUX_CE0
UDDCNTLinputTCELL14:IMUX_A2

Bel DLLDEL

ecp3 PLL_DLL_E bel DLLDEL
PinDirectionWires
BYPASSoutputTCELL13:OUT_F4
CLKOoutputTCELL13:OUT_F5

Bel CLKDIV

ecp3 PLL_DLL_E bel CLKDIV
PinDirectionWires
CDIV1outputTCELL13:OUT_F0
CDIV2outputTCELL13:OUT_F1
CDIV4outputTCELL13:OUT_F2
CDIV8outputTCELL13:OUT_F3
RELEASEinputTCELL13:IMUX_CE0
RSTinputTCELL13:IMUX_CE1

Bel ECLK_ALT_ROOT

ecp3 PLL_DLL_E bel ECLK_ALT_ROOT
PinDirectionWires
ECLK0_INinputTCELL14:IMUX_CLK0
ECLK1_INinputTCELL14:IMUX_CLK1

Bel wires

ecp3 PLL_DLL_E bel wires
WirePins
TCELL2:IMUX_CLK0DQSDLL.CLK
TCELL2:IMUX_CLK1PLL.RESETK
TCELL2:IMUX_CE0DQSDLL.UDDCNTLN
TCELL2:IMUX_CE1DQSDLL.RST
TCELL2:OUT_F0DQSDLL.LOCK
TCELL3:IMUX_A0PLL.DFPAI0
TCELL3:IMUX_A1PLL.DFPAI2
TCELL3:IMUX_A3PLL.TCLKI
TCELL3:IMUX_A4PLL.FDA3
TCELL3:IMUX_B0PLL.DRPAI0
TCELL3:IMUX_B1PLL.DRPAI2
TCELL3:IMUX_B2PLL.CLKI1
TCELL3:IMUX_B3PLL.FDA0
TCELL3:IMUX_C0PLL.DFPAI1
TCELL3:IMUX_C1PLL.DFPAI3
TCELL3:IMUX_C2PLL.WRDEL
TCELL3:IMUX_C3PLL.FDA1
TCELL3:IMUX_D0PLL.DRPAI1
TCELL3:IMUX_D1PLL.DRPAI3
TCELL3:IMUX_D2PLL.PWD
TCELL3:IMUX_D3PLL.FDA2
TCELL3:IMUX_CLK0PLL.CLKI2
TCELL3:IMUX_CLK1PLL.CLKFB0
TCELL3:IMUX_CE0PLL.CNTRST
TCELL3:IMUX_CE1PLL.RESETM
TCELL3:OUT_F0PLL.TESTOUT
TCELL3:OUT_F1PLL.CLKOK2
TCELL3:OUT_F2PLL.CLKOK
TCELL3:OUT_F3PLL.CLKOS
TCELL3:OUT_F4PLL.CLKOP
TCELL3:OUT_F5PLL.UPLOCK
TCELL3:OUT_F6PLL.DNLOCK
TCELL3:OUT_F7PLL.LOCK
TCELL3:OUT_Q0PLL.DFPAO0
TCELL3:OUT_Q1PLL.DRPAO0
TCELL3:OUT_Q2PLL.DFPAO1
TCELL3:OUT_Q3PLL.DRPAO1
TCELL3:OUT_Q4PLL.DFPAO2
TCELL3:OUT_Q5PLL.DRPAO2
TCELL3:OUT_Q6PLL.DFPAO3
TCELL3:OUT_Q7PLL.DRPAO3
TCELL12:IMUX_A5DLL.CIB_DCPS_2
TCELL12:IMUX_B5DLL.CIB_DCPS_3
TCELL12:IMUX_C4DLL.CIB_DCPS_0
TCELL12:IMUX_C5DLL.CIB_DCPS_4
TCELL12:IMUX_D4DLL.CIB_DCPS_1
TCELL12:IMUX_D5DLL.CIB_DCPS_5
TCELL12:OUT_F0DLL.DCNTL0
TCELL12:OUT_F1DLL.DCNTL1
TCELL12:OUT_F2DLL.DCNTL2
TCELL12:OUT_F3DLL.DCNTL3
TCELL12:OUT_F4DLL.DCNTL4
TCELL12:OUT_F5DLL.DCNTL5
TCELL13:IMUX_CE0CLKDIV.RELEASE
TCELL13:IMUX_CE1CLKDIV.RST
TCELL13:OUT_F0CLKDIV.CDIV1
TCELL13:OUT_F1CLKDIV.CDIV2
TCELL13:OUT_F2CLKDIV.CDIV4
TCELL13:OUT_F3CLKDIV.CDIV8
TCELL13:OUT_F4DLLDEL.BYPASS
TCELL13:OUT_F5DLLDEL.CLKO
TCELL14:IMUX_A0DLL.GRAYI0
TCELL14:IMUX_A1DLL.GRAYI4
TCELL14:IMUX_A2DLL.UDDCNTL
TCELL14:IMUX_B0DLL.GRAYI1
TCELL14:IMUX_B1DLL.GRAYI5
TCELL14:IMUX_B2DLL.CLKI2
TCELL14:IMUX_C0DLL.GRAYI2
TCELL14:IMUX_C1DLL.ALUHOLD
TCELL14:IMUX_D0DLL.GRAYI3
TCELL14:IMUX_D1DLL.INCI
TCELL14:IMUX_CLK0DLL.CLKI1, ECLK_ALT_ROOT.ECLK0_IN
TCELL14:IMUX_CLK1DLL.CLKFB3, ECLK_ALT_ROOT.ECLK1_IN
TCELL14:IMUX_CE0DLL.RSTN
TCELL14:OUT_F1DLL.CLKOP
TCELL14:OUT_F2DLL.CLKOS
TCELL14:OUT_F3DLL.DIFF
TCELL14:OUT_F4DLL.LOCK
TCELL14:OUT_F5DLL.INCO
TCELL14:OUT_Q0DLL.GRAYO0
TCELL14:OUT_Q1DLL.GRAYO1
TCELL14:OUT_Q2DLL.GRAYO2
TCELL14:OUT_Q3DLL.GRAYO3
TCELL14:OUT_Q4DLL.GRAYO4
TCELL14:OUT_Q5DLL.GRAYO5
TCELL16:OUT_F2DQSDLLTEST.SDOUT0
TCELL16:OUT_F3DQSDLLTEST.SDOUT6
TCELL16:OUT_F4DQSDLLTEST.SDOUT2
TCELL16:OUT_F5DQSDLLTEST.SDOUT3
TCELL16:OUT_Q1DQSDLLTEST.SDOUT5
TCELL16:OUT_Q2DQSDLLTEST.SDOUT1
TCELL16:OUT_Q3DQSDLLTEST.SDOUT4

Tile PLL_DLL_A_W

Cells: 18

Bel DQSDLL

ecp3 PLL_DLL_A_W bel DQSDLL
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
LOCKoutputTCELL2:OUT_F0
RSTinputTCELL2:IMUX_CE1
UDDCNTLNinputTCELL2:IMUX_CE0

Bel DQSDLLTEST

ecp3 PLL_DLL_A_W bel DQSDLLTEST
PinDirectionWires
SDOUT0outputTCELL16:OUT_F2
SDOUT1outputTCELL16:OUT_Q2
SDOUT2outputTCELL16:OUT_F4
SDOUT3outputTCELL16:OUT_F5
SDOUT4outputTCELL16:OUT_Q3
SDOUT5outputTCELL16:OUT_Q1
SDOUT6outputTCELL16:OUT_F3

Bel PLL

ecp3 PLL_DLL_A_W bel PLL
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKFB6inputTCELL15:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKI5inputTCELL15:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel DLL

ecp3 PLL_DLL_A_W bel DLL
PinDirectionWires
ALUHOLDinputTCELL14:IMUX_C1
CIB_DCPS_0inputTCELL12:IMUX_C4
CIB_DCPS_1inputTCELL12:IMUX_D4
CIB_DCPS_2inputTCELL12:IMUX_A5
CIB_DCPS_3inputTCELL12:IMUX_B5
CIB_DCPS_4inputTCELL12:IMUX_C5
CIB_DCPS_5inputTCELL12:IMUX_D5
CLKFB3inputTCELL14:IMUX_CLK1
CLKFB5inputTCELL17:IMUX_CLK1
CLKI1inputTCELL14:IMUX_CLK0
CLKI2inputTCELL14:IMUX_B2
CLKI5inputTCELL17:IMUX_CLK0
CLKOPoutputTCELL14:OUT_F1
CLKOSoutputTCELL14:OUT_F2
DCNTL0outputTCELL12:OUT_F0
DCNTL1outputTCELL12:OUT_F1
DCNTL2outputTCELL12:OUT_F2
DCNTL3outputTCELL12:OUT_F3
DCNTL4outputTCELL12:OUT_F4
DCNTL5outputTCELL12:OUT_F5
DIFFoutputTCELL14:OUT_F3
GRAYI0inputTCELL14:IMUX_A0
GRAYI1inputTCELL14:IMUX_B0
GRAYI2inputTCELL14:IMUX_C0
GRAYI3inputTCELL14:IMUX_D0
GRAYI4inputTCELL14:IMUX_A1
GRAYI5inputTCELL14:IMUX_B1
GRAYO0outputTCELL14:OUT_Q0
GRAYO1outputTCELL14:OUT_Q1
GRAYO2outputTCELL14:OUT_Q2
GRAYO3outputTCELL14:OUT_Q3
GRAYO4outputTCELL14:OUT_Q4
GRAYO5outputTCELL14:OUT_Q5
INCIinputTCELL14:IMUX_D1
INCOoutputTCELL14:OUT_F5
LOCKoutputTCELL14:OUT_F4
RSTNinputTCELL14:IMUX_CE0
UDDCNTLinputTCELL14:IMUX_A2

Bel DLLDEL

ecp3 PLL_DLL_A_W bel DLLDEL
PinDirectionWires
BYPASSoutputTCELL13:OUT_F4
CLKOoutputTCELL13:OUT_F5

Bel CLKDIV

ecp3 PLL_DLL_A_W bel CLKDIV
PinDirectionWires
CDIV1outputTCELL13:OUT_F0
CDIV2outputTCELL13:OUT_F1
CDIV4outputTCELL13:OUT_F2
CDIV8outputTCELL13:OUT_F3
RELEASEinputTCELL13:IMUX_CE0
RSTinputTCELL13:IMUX_CE1

Bel ECLK_ALT_ROOT

ecp3 PLL_DLL_A_W bel ECLK_ALT_ROOT
PinDirectionWires
ECLK0_INinputTCELL14:IMUX_CLK0
ECLK1_INinputTCELL14:IMUX_CLK1

Bel wires

ecp3 PLL_DLL_A_W bel wires
WirePins
TCELL2:IMUX_CLK0DQSDLL.CLK
TCELL2:IMUX_CLK1PLL.RESETK
TCELL2:IMUX_CE0DQSDLL.UDDCNTLN
TCELL2:IMUX_CE1DQSDLL.RST
TCELL2:OUT_F0DQSDLL.LOCK
TCELL3:IMUX_A0PLL.DFPAI0
TCELL3:IMUX_A1PLL.DFPAI2
TCELL3:IMUX_A3PLL.TCLKI
TCELL3:IMUX_A4PLL.FDA3
TCELL3:IMUX_B0PLL.DRPAI0
TCELL3:IMUX_B1PLL.DRPAI2
TCELL3:IMUX_B2PLL.CLKI1
TCELL3:IMUX_B3PLL.FDA0
TCELL3:IMUX_C0PLL.DFPAI1
TCELL3:IMUX_C1PLL.DFPAI3
TCELL3:IMUX_C2PLL.WRDEL
TCELL3:IMUX_C3PLL.FDA1
TCELL3:IMUX_D0PLL.DRPAI1
TCELL3:IMUX_D1PLL.DRPAI3
TCELL3:IMUX_D2PLL.PWD
TCELL3:IMUX_D3PLL.FDA2
TCELL3:IMUX_CLK0PLL.CLKI2
TCELL3:IMUX_CLK1PLL.CLKFB0
TCELL3:IMUX_CE0PLL.CNTRST
TCELL3:IMUX_CE1PLL.RESETM
TCELL3:OUT_F0PLL.TESTOUT
TCELL3:OUT_F1PLL.CLKOK2
TCELL3:OUT_F2PLL.CLKOK
TCELL3:OUT_F3PLL.CLKOS
TCELL3:OUT_F4PLL.CLKOP
TCELL3:OUT_F5PLL.UPLOCK
TCELL3:OUT_F6PLL.DNLOCK
TCELL3:OUT_F7PLL.LOCK
TCELL3:OUT_Q0PLL.DFPAO0
TCELL3:OUT_Q1PLL.DRPAO0
TCELL3:OUT_Q2PLL.DFPAO1
TCELL3:OUT_Q3PLL.DRPAO1
TCELL3:OUT_Q4PLL.DFPAO2
TCELL3:OUT_Q5PLL.DRPAO2
TCELL3:OUT_Q6PLL.DFPAO3
TCELL3:OUT_Q7PLL.DRPAO3
TCELL12:IMUX_A5DLL.CIB_DCPS_2
TCELL12:IMUX_B5DLL.CIB_DCPS_3
TCELL12:IMUX_C4DLL.CIB_DCPS_0
TCELL12:IMUX_C5DLL.CIB_DCPS_4
TCELL12:IMUX_D4DLL.CIB_DCPS_1
TCELL12:IMUX_D5DLL.CIB_DCPS_5
TCELL12:OUT_F0DLL.DCNTL0
TCELL12:OUT_F1DLL.DCNTL1
TCELL12:OUT_F2DLL.DCNTL2
TCELL12:OUT_F3DLL.DCNTL3
TCELL12:OUT_F4DLL.DCNTL4
TCELL12:OUT_F5DLL.DCNTL5
TCELL13:IMUX_CE0CLKDIV.RELEASE
TCELL13:IMUX_CE1CLKDIV.RST
TCELL13:OUT_F0CLKDIV.CDIV1
TCELL13:OUT_F1CLKDIV.CDIV2
TCELL13:OUT_F2CLKDIV.CDIV4
TCELL13:OUT_F3CLKDIV.CDIV8
TCELL13:OUT_F4DLLDEL.BYPASS
TCELL13:OUT_F5DLLDEL.CLKO
TCELL14:IMUX_A0DLL.GRAYI0
TCELL14:IMUX_A1DLL.GRAYI4
TCELL14:IMUX_A2DLL.UDDCNTL
TCELL14:IMUX_B0DLL.GRAYI1
TCELL14:IMUX_B1DLL.GRAYI5
TCELL14:IMUX_B2DLL.CLKI2
TCELL14:IMUX_C0DLL.GRAYI2
TCELL14:IMUX_C1DLL.ALUHOLD
TCELL14:IMUX_D0DLL.GRAYI3
TCELL14:IMUX_D1DLL.INCI
TCELL14:IMUX_CLK0DLL.CLKI1, ECLK_ALT_ROOT.ECLK0_IN
TCELL14:IMUX_CLK1DLL.CLKFB3, ECLK_ALT_ROOT.ECLK1_IN
TCELL14:IMUX_CE0DLL.RSTN
TCELL14:OUT_F1DLL.CLKOP
TCELL14:OUT_F2DLL.CLKOS
TCELL14:OUT_F3DLL.DIFF
TCELL14:OUT_F4DLL.LOCK
TCELL14:OUT_F5DLL.INCO
TCELL14:OUT_Q0DLL.GRAYO0
TCELL14:OUT_Q1DLL.GRAYO1
TCELL14:OUT_Q2DLL.GRAYO2
TCELL14:OUT_Q3DLL.GRAYO3
TCELL14:OUT_Q4DLL.GRAYO4
TCELL14:OUT_Q5DLL.GRAYO5
TCELL15:IMUX_CLK0PLL.CLKI5
TCELL15:IMUX_CLK1PLL.CLKFB6
TCELL16:OUT_F2DQSDLLTEST.SDOUT0
TCELL16:OUT_F3DQSDLLTEST.SDOUT6
TCELL16:OUT_F4DQSDLLTEST.SDOUT2
TCELL16:OUT_F5DQSDLLTEST.SDOUT3
TCELL16:OUT_Q1DQSDLLTEST.SDOUT5
TCELL16:OUT_Q2DQSDLLTEST.SDOUT1
TCELL16:OUT_Q3DQSDLLTEST.SDOUT4
TCELL17:IMUX_CLK0DLL.CLKI5
TCELL17:IMUX_CLK1DLL.CLKFB5

Tile PLL_DLL_A_E

Cells: 18

Bel DQSDLL

ecp3 PLL_DLL_A_E bel DQSDLL
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
LOCKoutputTCELL2:OUT_F0
RSTinputTCELL2:IMUX_CE1
UDDCNTLNinputTCELL2:IMUX_CE0

Bel DQSDLLTEST

ecp3 PLL_DLL_A_E bel DQSDLLTEST
PinDirectionWires
SDOUT0outputTCELL16:OUT_F2
SDOUT1outputTCELL16:OUT_Q2
SDOUT2outputTCELL16:OUT_F4
SDOUT3outputTCELL16:OUT_F5
SDOUT4outputTCELL16:OUT_Q3
SDOUT5outputTCELL16:OUT_Q1
SDOUT6outputTCELL16:OUT_F3

Bel PLL

ecp3 PLL_DLL_A_E bel PLL
PinDirectionWires
CLKFB0inputTCELL3:IMUX_CLK1
CLKFB6inputTCELL15:IMUX_CLK1
CLKI1inputTCELL3:IMUX_B2
CLKI2inputTCELL3:IMUX_CLK0
CLKI5inputTCELL15:IMUX_CLK0
CLKOKoutputTCELL3:OUT_F2
CLKOK2outputTCELL3:OUT_F1
CLKOPoutputTCELL3:OUT_F4
CLKOSoutputTCELL3:OUT_F3
CNTRSTinputTCELL3:IMUX_CE0
DFPAI0inputTCELL3:IMUX_A0
DFPAI1inputTCELL3:IMUX_C0
DFPAI2inputTCELL3:IMUX_A1
DFPAI3inputTCELL3:IMUX_C1
DFPAO0outputTCELL3:OUT_Q0
DFPAO1outputTCELL3:OUT_Q2
DFPAO2outputTCELL3:OUT_Q4
DFPAO3outputTCELL3:OUT_Q6
DNLOCKoutputTCELL3:OUT_F6
DRPAI0inputTCELL3:IMUX_B0
DRPAI1inputTCELL3:IMUX_D0
DRPAI2inputTCELL3:IMUX_B1
DRPAI3inputTCELL3:IMUX_D1
DRPAO0outputTCELL3:OUT_Q1
DRPAO1outputTCELL3:OUT_Q3
DRPAO2outputTCELL3:OUT_Q5
DRPAO3outputTCELL3:OUT_Q7
FDA0inputTCELL3:IMUX_B3
FDA1inputTCELL3:IMUX_C3
FDA2inputTCELL3:IMUX_D3
FDA3inputTCELL3:IMUX_A4
LOCKoutputTCELL3:OUT_F7
PWDinputTCELL3:IMUX_D2
RESETKinputTCELL2:IMUX_CLK1
RESETMinputTCELL3:IMUX_CE1
TCLKIinputTCELL3:IMUX_A3
TESTOUToutputTCELL3:OUT_F0
UPLOCKoutputTCELL3:OUT_F5
WRDELinputTCELL3:IMUX_C2

Bel DLL

ecp3 PLL_DLL_A_E bel DLL
PinDirectionWires
ALUHOLDinputTCELL14:IMUX_C1
CIB_DCPS_0inputTCELL12:IMUX_C4
CIB_DCPS_1inputTCELL12:IMUX_D4
CIB_DCPS_2inputTCELL12:IMUX_A5
CIB_DCPS_3inputTCELL12:IMUX_B5
CIB_DCPS_4inputTCELL12:IMUX_C5
CIB_DCPS_5inputTCELL12:IMUX_D5
CLKFB3inputTCELL14:IMUX_CLK1
CLKFB5inputTCELL17:IMUX_CLK1
CLKI1inputTCELL14:IMUX_CLK0
CLKI2inputTCELL14:IMUX_B2
CLKI5inputTCELL17:IMUX_CLK0
CLKOPoutputTCELL14:OUT_F1
CLKOSoutputTCELL14:OUT_F2
DCNTL0outputTCELL12:OUT_F0
DCNTL1outputTCELL12:OUT_F1
DCNTL2outputTCELL12:OUT_F2
DCNTL3outputTCELL12:OUT_F3
DCNTL4outputTCELL12:OUT_F4
DCNTL5outputTCELL12:OUT_F5
DIFFoutputTCELL14:OUT_F3
GRAYI0inputTCELL14:IMUX_A0
GRAYI1inputTCELL14:IMUX_B0
GRAYI2inputTCELL14:IMUX_C0
GRAYI3inputTCELL14:IMUX_D0
GRAYI4inputTCELL14:IMUX_A1
GRAYI5inputTCELL14:IMUX_B1
GRAYO0outputTCELL14:OUT_Q0
GRAYO1outputTCELL14:OUT_Q1
GRAYO2outputTCELL14:OUT_Q2
GRAYO3outputTCELL14:OUT_Q3
GRAYO4outputTCELL14:OUT_Q4
GRAYO5outputTCELL14:OUT_Q5
INCIinputTCELL14:IMUX_D1
INCOoutputTCELL14:OUT_F5
LOCKoutputTCELL14:OUT_F4
RSTNinputTCELL14:IMUX_CE0
UDDCNTLinputTCELL14:IMUX_A2

Bel DLLDEL

ecp3 PLL_DLL_A_E bel DLLDEL
PinDirectionWires
BYPASSoutputTCELL13:OUT_F4
CLKOoutputTCELL13:OUT_F5

Bel CLKDIV

ecp3 PLL_DLL_A_E bel CLKDIV
PinDirectionWires
CDIV1outputTCELL13:OUT_F0
CDIV2outputTCELL13:OUT_F1
CDIV4outputTCELL13:OUT_F2
CDIV8outputTCELL13:OUT_F3
RELEASEinputTCELL13:IMUX_CE0
RSTinputTCELL13:IMUX_CE1

Bel ECLK_ALT_ROOT

ecp3 PLL_DLL_A_E bel ECLK_ALT_ROOT
PinDirectionWires
ECLK0_INinputTCELL14:IMUX_CLK0
ECLK1_INinputTCELL14:IMUX_CLK1

Bel wires

ecp3 PLL_DLL_A_E bel wires
WirePins
TCELL2:IMUX_CLK0DQSDLL.CLK
TCELL2:IMUX_CLK1PLL.RESETK
TCELL2:IMUX_CE0DQSDLL.UDDCNTLN
TCELL2:IMUX_CE1DQSDLL.RST
TCELL2:OUT_F0DQSDLL.LOCK
TCELL3:IMUX_A0PLL.DFPAI0
TCELL3:IMUX_A1PLL.DFPAI2
TCELL3:IMUX_A3PLL.TCLKI
TCELL3:IMUX_A4PLL.FDA3
TCELL3:IMUX_B0PLL.DRPAI0
TCELL3:IMUX_B1PLL.DRPAI2
TCELL3:IMUX_B2PLL.CLKI1
TCELL3:IMUX_B3PLL.FDA0
TCELL3:IMUX_C0PLL.DFPAI1
TCELL3:IMUX_C1PLL.DFPAI3
TCELL3:IMUX_C2PLL.WRDEL
TCELL3:IMUX_C3PLL.FDA1
TCELL3:IMUX_D0PLL.DRPAI1
TCELL3:IMUX_D1PLL.DRPAI3
TCELL3:IMUX_D2PLL.PWD
TCELL3:IMUX_D3PLL.FDA2
TCELL3:IMUX_CLK0PLL.CLKI2
TCELL3:IMUX_CLK1PLL.CLKFB0
TCELL3:IMUX_CE0PLL.CNTRST
TCELL3:IMUX_CE1PLL.RESETM
TCELL3:OUT_F0PLL.TESTOUT
TCELL3:OUT_F1PLL.CLKOK2
TCELL3:OUT_F2PLL.CLKOK
TCELL3:OUT_F3PLL.CLKOS
TCELL3:OUT_F4PLL.CLKOP
TCELL3:OUT_F5PLL.UPLOCK
TCELL3:OUT_F6PLL.DNLOCK
TCELL3:OUT_F7PLL.LOCK
TCELL3:OUT_Q0PLL.DFPAO0
TCELL3:OUT_Q1PLL.DRPAO0
TCELL3:OUT_Q2PLL.DFPAO1
TCELL3:OUT_Q3PLL.DRPAO1
TCELL3:OUT_Q4PLL.DFPAO2
TCELL3:OUT_Q5PLL.DRPAO2
TCELL3:OUT_Q6PLL.DFPAO3
TCELL3:OUT_Q7PLL.DRPAO3
TCELL12:IMUX_A5DLL.CIB_DCPS_2
TCELL12:IMUX_B5DLL.CIB_DCPS_3
TCELL12:IMUX_C4DLL.CIB_DCPS_0
TCELL12:IMUX_C5DLL.CIB_DCPS_4
TCELL12:IMUX_D4DLL.CIB_DCPS_1
TCELL12:IMUX_D5DLL.CIB_DCPS_5
TCELL12:OUT_F0DLL.DCNTL0
TCELL12:OUT_F1DLL.DCNTL1
TCELL12:OUT_F2DLL.DCNTL2
TCELL12:OUT_F3DLL.DCNTL3
TCELL12:OUT_F4DLL.DCNTL4
TCELL12:OUT_F5DLL.DCNTL5
TCELL13:IMUX_CE0CLKDIV.RELEASE
TCELL13:IMUX_CE1CLKDIV.RST
TCELL13:OUT_F0CLKDIV.CDIV1
TCELL13:OUT_F1CLKDIV.CDIV2
TCELL13:OUT_F2CLKDIV.CDIV4
TCELL13:OUT_F3CLKDIV.CDIV8
TCELL13:OUT_F4DLLDEL.BYPASS
TCELL13:OUT_F5DLLDEL.CLKO
TCELL14:IMUX_A0DLL.GRAYI0
TCELL14:IMUX_A1DLL.GRAYI4
TCELL14:IMUX_A2DLL.UDDCNTL
TCELL14:IMUX_B0DLL.GRAYI1
TCELL14:IMUX_B1DLL.GRAYI5
TCELL14:IMUX_B2DLL.CLKI2
TCELL14:IMUX_C0DLL.GRAYI2
TCELL14:IMUX_C1DLL.ALUHOLD
TCELL14:IMUX_D0DLL.GRAYI3
TCELL14:IMUX_D1DLL.INCI
TCELL14:IMUX_CLK0DLL.CLKI1, ECLK_ALT_ROOT.ECLK0_IN
TCELL14:IMUX_CLK1DLL.CLKFB3, ECLK_ALT_ROOT.ECLK1_IN
TCELL14:IMUX_CE0DLL.RSTN
TCELL14:OUT_F1DLL.CLKOP
TCELL14:OUT_F2DLL.CLKOS
TCELL14:OUT_F3DLL.DIFF
TCELL14:OUT_F4DLL.LOCK
TCELL14:OUT_F5DLL.INCO
TCELL14:OUT_Q0DLL.GRAYO0
TCELL14:OUT_Q1DLL.GRAYO1
TCELL14:OUT_Q2DLL.GRAYO2
TCELL14:OUT_Q3DLL.GRAYO3
TCELL14:OUT_Q4DLL.GRAYO4
TCELL14:OUT_Q5DLL.GRAYO5
TCELL15:IMUX_CLK0PLL.CLKI5
TCELL15:IMUX_CLK1PLL.CLKFB6
TCELL16:OUT_F2DQSDLLTEST.SDOUT0
TCELL16:OUT_F3DQSDLLTEST.SDOUT6
TCELL16:OUT_F4DQSDLLTEST.SDOUT2
TCELL16:OUT_F5DQSDLLTEST.SDOUT3
TCELL16:OUT_Q1DQSDLLTEST.SDOUT5
TCELL16:OUT_Q2DQSDLLTEST.SDOUT1
TCELL16:OUT_Q3DQSDLLTEST.SDOUT4
TCELL17:IMUX_CLK0DLL.CLKI5
TCELL17:IMUX_CLK1DLL.CLKFB5