SERDES
Tile SERDES
Cells: 36
Bel SERDES
| Pin | Direction | Wires |
|---|---|---|
| CIN0 | input | TCELL18:IMUX_C5 |
| CIN1 | input | TCELL18:IMUX_B5 |
| CIN10 | input | TCELL18:IMUX_A3 |
| CIN11 | input | TCELL18:IMUX_D2 |
| CIN2 | input | TCELL18:IMUX_A5 |
| CIN3 | input | TCELL18:IMUX_D4 |
| CIN4 | input | TCELL18:IMUX_C4 |
| CIN5 | input | TCELL18:IMUX_B4 |
| CIN6 | input | TCELL18:IMUX_A4 |
| CIN7 | input | TCELL18:IMUX_D3 |
| CIN8 | input | TCELL18:IMUX_C3 |
| CIN9 | input | TCELL18:IMUX_B3 |
| COUT0 | output | TCELL20:OUT_F2 |
| COUT1 | output | TCELL20:OUT_F1 |
| COUT10 | output | TCELL19:OUT_Q0 |
| COUT11 | output | TCELL19:OUT_F5 |
| COUT12 | output | TCELL19:OUT_F4 |
| COUT13 | output | TCELL19:OUT_F3 |
| COUT14 | output | TCELL19:OUT_F2 |
| COUT15 | output | TCELL19:OUT_F1 |
| COUT16 | output | TCELL19:OUT_F0 |
| COUT17 | output | TCELL18:OUT_Q7 |
| COUT18 | output | TCELL18:OUT_Q6 |
| COUT19 | output | TCELL18:OUT_Q5 |
| COUT2 | output | TCELL20:OUT_F0 |
| COUT3 | output | TCELL19:OUT_Q7 |
| COUT4 | output | TCELL19:OUT_Q6 |
| COUT5 | output | TCELL19:OUT_Q5 |
| COUT6 | output | TCELL19:OUT_Q4 |
| COUT7 | output | TCELL19:OUT_Q3 |
| COUT8 | output | TCELL19:OUT_Q2 |
| COUT9 | output | TCELL19:OUT_Q1 |
| CYAWSTN | input | TCELL18:IMUX_D1 |
| FFC_CK_CORE_RX_0 | input | TCELL30:IMUX_CLK1 |
| FFC_CK_CORE_RX_1 | input | TCELL26:IMUX_CLK0 |
| FFC_CK_CORE_RX_2 | input | TCELL9:IMUX_CLK1 |
| FFC_CK_CORE_RX_3 | input | TCELL5:IMUX_CLK0 |
| FFC_CK_CORE_TX | input | TCELL16:IMUX_CLK0 |
| FFC_DIV11_MODE_RX_0 | input | TCELL33:IMUX_C4 |
| FFC_DIV11_MODE_RX_1 | input | TCELL23:IMUX_D0 |
| FFC_DIV11_MODE_RX_2 | input | TCELL12:IMUX_C4 |
| FFC_DIV11_MODE_RX_3 | input | TCELL2:IMUX_B1 |
| FFC_DIV11_MODE_TX_0 | input | TCELL33:IMUX_B4 |
| FFC_DIV11_MODE_TX_1 | input | TCELL23:IMUX_A1 |
| FFC_DIV11_MODE_TX_2 | input | TCELL12:IMUX_B4 |
| FFC_DIV11_MODE_TX_3 | input | TCELL2:IMUX_C1 |
| FFC_EI_EN_0 | input | TCELL34:IMUX_D1 |
| FFC_EI_EN_1 | input | TCELL22:IMUX_B1 |
| FFC_EI_EN_2 | input | TCELL13:IMUX_B4 |
| FFC_EI_EN_3 | input | TCELL1:IMUX_A4 |
| FFC_ENABLE_CGALIGN_0 | input | TCELL33:IMUX_B5 |
| FFC_ENABLE_CGALIGN_1 | input | TCELL23:IMUX_A0 |
| FFC_ENABLE_CGALIGN_2 | input | TCELL12:IMUX_B5 |
| FFC_ENABLE_CGALIGN_3 | input | TCELL2:IMUX_C0 |
| FFC_FB_LOOPBACK_0 | input | TCELL34:IMUX_B1 |
| FFC_FB_LOOPBACK_1 | input | TCELL22:IMUX_B2 |
| FFC_FB_LOOPBACK_2 | input | TCELL13:IMUX_B3 |
| FFC_FB_LOOPBACK_3 | input | TCELL1:IMUX_C4 |
| FFC_LANE_RX_RST_0 | input | TCELL34:IMUX_LSR1 |
| FFC_LANE_RX_RST_1 | input | TCELL22:IMUX_LSR0 |
| FFC_LANE_RX_RST_2 | input | TCELL13:IMUX_LSR0 |
| FFC_LANE_RX_RST_3 | input | TCELL1:IMUX_LSR0 |
| FFC_LANE_TX_RST_0 | input | TCELL30:IMUX_LSR2 |
| FFC_LANE_TX_RST_1 | input | TCELL26:IMUX_LSR1 |
| FFC_LANE_TX_RST_2 | input | TCELL9:IMUX_LSR0 |
| FFC_LANE_TX_RST_3 | input | TCELL5:IMUX_LSR0 |
| FFC_LDR_CORE2TX_EN_0 | input | TCELL31:IMUX_D4 |
| FFC_LDR_CORE2TX_EN_1 | input | TCELL25:IMUX_D4 |
| FFC_LDR_CORE2TX_EN_2 | input | TCELL10:IMUX_C4 |
| FFC_LDR_CORE2TX_EN_3 | input | TCELL4:IMUX_C4 |
| FFC_MACRO_RST | input | TCELL18:IMUX_LSR0 |
| FFC_PCIE_CT_0 | input | TCELL34:IMUX_D0 |
| FFC_PCIE_CT_1 | input | TCELL22:IMUX_B3 |
| FFC_PCIE_CT_2 | input | TCELL13:IMUX_B2 |
| FFC_PCIE_CT_3 | input | TCELL1:IMUX_A5 |
| FFC_PCI_DET_EN_0 | input | TCELL34:IMUX_D4 |
| FFC_PCI_DET_EN_1 | input | TCELL21:IMUX_B1 |
| FFC_PCI_DET_EN_2 | input | TCELL14:IMUX_B4 |
| FFC_PCI_DET_EN_3 | input | TCELL1:IMUX_A1 |
| FFC_PFIFO_CLR_0 | input | TCELL34:IMUX_B0 |
| FFC_PFIFO_CLR_1 | input | TCELL22:IMUX_B4 |
| FFC_PFIFO_CLR_2 | input | TCELL13:IMUX_B1 |
| FFC_PFIFO_CLR_3 | input | TCELL1:IMUX_C5 |
| FFC_QUAD_RST | input | TCELL18:IMUX_LSR1 |
| FFC_RATE_MODE_RX_0 | input | TCELL33:IMUX_A5 |
| FFC_RATE_MODE_RX_1 | input | TCELL23:IMUX_B0 |
| FFC_RATE_MODE_RX_2 | input | TCELL12:IMUX_A5 |
| FFC_RATE_MODE_RX_3 | input | TCELL2:IMUX_D0 |
| FFC_RATE_MODE_TX_0 | input | TCELL33:IMUX_D4 |
| FFC_RATE_MODE_TX_1 | input | TCELL23:IMUX_C0 |
| FFC_RATE_MODE_TX_2 | input | TCELL12:IMUX_D4 |
| FFC_RATE_MODE_TX_3 | input | TCELL2:IMUX_A1 |
| FFC_RRST_0 | input | TCELL20:IMUX_LSR2 |
| FFC_RRST_1 | input | TCELL19:IMUX_LSR2 |
| FFC_RRST_2 | input | TCELL16:IMUX_LSR1 |
| FFC_RRST_3 | input | TCELL15:IMUX_LSR0 |
| FFC_RXPWDNB_0 | input | TCELL34:IMUX_B5 |
| FFC_RXPWDNB_1 | input | TCELL21:IMUX_B0 |
| FFC_RXPWDNB_2 | input | TCELL14:IMUX_B5 |
| FFC_RXPWDNB_3 | input | TCELL1:IMUX_C0 |
| FFC_SB_INV_RX_0 | input | TCELL34:IMUX_B4 |
| FFC_SB_INV_RX_1 | input | TCELL21:IMUX_B2 |
| FFC_SB_INV_RX_2 | input | TCELL14:IMUX_B3 |
| FFC_SB_INV_RX_3 | input | TCELL1:IMUX_C1 |
| FFC_SB_PFIFO_LP_0 | input | TCELL34:IMUX_D3 |
| FFC_SB_PFIFO_LP_1 | input | TCELL21:IMUX_B3 |
| FFC_SB_PFIFO_LP_2 | input | TCELL14:IMUX_B2 |
| FFC_SB_PFIFO_LP_3 | input | TCELL1:IMUX_A2 |
| FFC_SIGNAL_DETECT_0 | input | TCELL34:IMUX_B3 |
| FFC_SIGNAL_DETECT_1 | input | TCELL21:IMUX_B4 |
| FFC_SIGNAL_DETECT_2 | input | TCELL14:IMUX_B1 |
| FFC_SIGNAL_DETECT_3 | input | TCELL1:IMUX_C2 |
| FFC_SYNC_TOGGLE | input | TCELL18:IMUX_A2 |
| FFC_TRST | input | TCELL18:IMUX_LSR2 |
| FFC_TXPWDNB_0 | input | TCELL30:IMUX_B3 |
| FFC_TXPWDNB_1 | input | TCELL26:IMUX_B0 |
| FFC_TXPWDNB_2 | input | TCELL9:IMUX_A3 |
| FFC_TXPWDNB_3 | input | TCELL5:IMUX_B0 |
| FFS_BIST_RPT_0 | output | TCELL18:OUT_Q4 |
| FFS_BIST_RPT_1 | output | TCELL18:OUT_Q3 |
| FFS_BIST_RPT_10 | output | TCELL18:OUT_F0 |
| FFS_BIST_RPT_11 | output | TCELL17:OUT_Q7 |
| FFS_BIST_RPT_12 | output | TCELL17:OUT_Q6 |
| FFS_BIST_RPT_13 | output | TCELL17:OUT_Q5 |
| FFS_BIST_RPT_14 | output | TCELL17:OUT_Q4 |
| FFS_BIST_RPT_15 | output | TCELL17:OUT_Q3 |
| FFS_BIST_RPT_2 | output | TCELL18:OUT_Q2 |
| FFS_BIST_RPT_3 | output | TCELL18:OUT_Q1 |
| FFS_BIST_RPT_4 | output | TCELL18:OUT_Q0 |
| FFS_BIST_RPT_5 | output | TCELL18:OUT_F5 |
| FFS_BIST_RPT_6 | output | TCELL18:OUT_F4 |
| FFS_BIST_RPT_7 | output | TCELL18:OUT_F3 |
| FFS_BIST_RPT_8 | output | TCELL18:OUT_F2 |
| FFS_BIST_RPT_9 | output | TCELL18:OUT_F1 |
| FFS_CC_OVERRUN_0 | output | TCELL31:OUT_F3 |
| FFS_CC_OVERRUN_1 | output | TCELL25:OUT_Q1 |
| FFS_CC_OVERRUN_2 | output | TCELL10:OUT_Q2 |
| FFS_CC_OVERRUN_3 | output | TCELL4:OUT_Q1 |
| FFS_CC_UNDERRUN_0 | output | TCELL30:OUT_F3 |
| FFS_CC_UNDERRUN_1 | output | TCELL26:OUT_F4 |
| FFS_CC_UNDERRUN_2 | output | TCELL9:OUT_F2 |
| FFS_CC_UNDERRUN_3 | output | TCELL5:OUT_F4 |
| FFS_CDR_TRAIN_DONE_0 | output | TCELL31:OUT_F0 |
| FFS_CDR_TRAIN_DONE_1 | output | TCELL25:OUT_Q7 |
| FFS_CDR_TRAIN_DONE_2 | output | TCELL10:OUT_F0 |
| FFS_CDR_TRAIN_DONE_3 | output | TCELL4:OUT_Q7 |
| FFS_LS_SYNC_STATUS_0 | output | TCELL31:OUT_F2 |
| FFS_LS_SYNC_STATUS_1 | output | TCELL25:OUT_Q3 |
| FFS_LS_SYNC_STATUS_2 | output | TCELL10:OUT_F4 |
| FFS_LS_SYNC_STATUS_3 | output | TCELL4:OUT_Q3 |
| FFS_PCIE_CON_0 | output | TCELL28:OUT_Q3 |
| FFS_PCIE_CON_1 | output | TCELL28:OUT_F0 |
| FFS_PCIE_CON_2 | output | TCELL7:OUT_Q7 |
| FFS_PCIE_CON_3 | output | TCELL7:OUT_F0 |
| FFS_PCIE_DONE_0 | output | TCELL28:OUT_Q2 |
| FFS_PCIE_DONE_1 | output | TCELL28:OUT_F1 |
| FFS_PCIE_DONE_2 | output | TCELL7:OUT_Q5 |
| FFS_PCIE_DONE_3 | output | TCELL7:OUT_F2 |
| FFS_PLOL | output | TCELL20:OUT_F3 |
| FFS_RLOL_0 | output | TCELL32:OUT_F4 |
| FFS_RLOL_1 | output | TCELL24:OUT_F4 |
| FFS_RLOL_2 | output | TCELL11:OUT_Q1 |
| FFS_RLOL_3 | output | TCELL3:OUT_Q2 |
| FFS_RLOS_HI_0 | output | TCELL32:OUT_Q3 |
| FFS_RLOS_HI_1 | output | TCELL24:OUT_F0 |
| FFS_RLOS_HI_2 | output | TCELL11:OUT_Q5 |
| FFS_RLOS_HI_3 | output | TCELL3:OUT_F1 |
| FFS_RLOS_LO_0 | output | TCELL32:OUT_Q1 |
| FFS_RLOS_LO_1 | output | TCELL24:OUT_F2 |
| FFS_RLOS_LO_2 | output | TCELL11:OUT_Q3 |
| FFS_RLOS_LO_3 | output | TCELL3:OUT_F3 |
| FFS_RXFBFIFO_ERROR_0 | output | TCELL28:OUT_Q0 |
| FFS_RXFBFIFO_ERROR_1 | output | TCELL28:OUT_F3 |
| FFS_RXFBFIFO_ERROR_2 | output | TCELL7:OUT_Q1 |
| FFS_RXFBFIFO_ERROR_3 | output | TCELL7:OUT_Q0 |
| FFS_SKP_ADDED_0 | output | TCELL29:OUT_F2 |
| FFS_SKP_ADDED_1 | output | TCELL27:OUT_F4 |
| FFS_SKP_ADDED_2 | output | TCELL8:OUT_F4 |
| FFS_SKP_ADDED_3 | output | TCELL6:OUT_Q1 |
| FFS_SKP_DELETED_0 | output | TCELL29:OUT_F0 |
| FFS_SKP_DELETED_1 | output | TCELL27:OUT_Q1 |
| FFS_SKP_DELETED_2 | output | TCELL8:OUT_F1 |
| FFS_SKP_DELETED_3 | output | TCELL6:OUT_Q5 |
| FFS_TXFBFIFO_ERROR_0 | output | TCELL28:OUT_Q1 |
| FFS_TXFBFIFO_ERROR_1 | output | TCELL28:OUT_F2 |
| FFS_TXFBFIFO_ERROR_2 | output | TCELL7:OUT_Q3 |
| FFS_TXFBFIFO_ERROR_3 | output | TCELL7:OUT_F4 |
| FF_EBRD_CLK_0 | input | TCELL34:IMUX_CLK1 |
| FF_EBRD_CLK_1 | input | TCELL21:IMUX_CLK0 |
| FF_EBRD_CLK_2 | input | TCELL14:IMUX_CLK0 |
| FF_EBRD_CLK_3 | input | TCELL1:IMUX_CLK1 |
| FF_RXI_CLK_0 | input | TCELL33:IMUX_CLK0 |
| FF_RXI_CLK_1 | input | TCELL22:IMUX_CLK0 |
| FF_RXI_CLK_2 | input | TCELL13:IMUX_CLK0 |
| FF_RXI_CLK_3 | input | TCELL2:IMUX_CLK0 |
| FF_RX_D_0_0 | output | TCELL31:OUT_Q0 |
| FF_RX_D_0_1 | output | TCELL31:OUT_Q1 |
| FF_RX_D_0_10 | output | TCELL34:OUT_F0 |
| FF_RX_D_0_11 | output | TCELL34:OUT_F1 |
| FF_RX_D_0_12 | output | TCELL34:OUT_F2 |
| FF_RX_D_0_13 | output | TCELL34:OUT_F3 |
| FF_RX_D_0_14 | output | TCELL34:OUT_F4 |
| FF_RX_D_0_15 | output | TCELL34:OUT_F5 |
| FF_RX_D_0_16 | output | TCELL34:OUT_Q0 |
| FF_RX_D_0_17 | output | TCELL34:OUT_Q1 |
| FF_RX_D_0_18 | output | TCELL34:OUT_Q2 |
| FF_RX_D_0_19 | output | TCELL34:OUT_Q3 |
| FF_RX_D_0_2 | output | TCELL31:OUT_Q3 |
| FF_RX_D_0_20 | output | TCELL34:OUT_Q4 |
| FF_RX_D_0_21 | output | TCELL34:OUT_Q5 |
| FF_RX_D_0_22 | output | TCELL34:OUT_Q6 |
| FF_RX_D_0_23 | output | TCELL34:OUT_Q7 |
| FF_RX_D_0_3 | output | TCELL31:OUT_Q4 |
| FF_RX_D_0_4 | output | TCELL31:OUT_Q6 |
| FF_RX_D_0_5 | output | TCELL31:OUT_Q7 |
| FF_RX_D_0_6 | output | TCELL32:OUT_F0 |
| FF_RX_D_0_7 | output | TCELL32:OUT_F2 |
| FF_RX_D_0_8 | output | TCELL33:OUT_Q4 |
| FF_RX_D_0_9 | output | TCELL33:OUT_Q6 |
| FF_RX_D_1_0 | output | TCELL25:OUT_F3 |
| FF_RX_D_1_1 | output | TCELL25:OUT_F2 |
| FF_RX_D_1_10 | output | TCELL22:OUT_Q4 |
| FF_RX_D_1_11 | output | TCELL22:OUT_Q2 |
| FF_RX_D_1_12 | output | TCELL22:OUT_Q0 |
| FF_RX_D_1_13 | output | TCELL22:OUT_F4 |
| FF_RX_D_1_14 | output | TCELL22:OUT_F2 |
| FF_RX_D_1_15 | output | TCELL22:OUT_F0 |
| FF_RX_D_1_16 | output | TCELL21:OUT_Q7 |
| FF_RX_D_1_17 | output | TCELL21:OUT_Q5 |
| FF_RX_D_1_18 | output | TCELL21:OUT_Q3 |
| FF_RX_D_1_19 | output | TCELL21:OUT_Q1 |
| FF_RX_D_1_2 | output | TCELL25:OUT_F1 |
| FF_RX_D_1_20 | output | TCELL21:OUT_Q0 |
| FF_RX_D_1_21 | output | TCELL21:OUT_F4 |
| FF_RX_D_1_22 | output | TCELL21:OUT_F2 |
| FF_RX_D_1_23 | output | TCELL21:OUT_F0 |
| FF_RX_D_1_3 | output | TCELL25:OUT_F0 |
| FF_RX_D_1_4 | output | TCELL24:OUT_Q7 |
| FF_RX_D_1_5 | output | TCELL24:OUT_Q5 |
| FF_RX_D_1_6 | output | TCELL24:OUT_Q3 |
| FF_RX_D_1_7 | output | TCELL24:OUT_Q1 |
| FF_RX_D_1_8 | output | TCELL22:OUT_Q7 |
| FF_RX_D_1_9 | output | TCELL22:OUT_Q6 |
| FF_RX_D_2_0 | output | TCELL10:OUT_Q4 |
| FF_RX_D_2_1 | output | TCELL10:OUT_Q5 |
| FF_RX_D_2_10 | output | TCELL13:OUT_F4 |
| FF_RX_D_2_11 | output | TCELL13:OUT_Q0 |
| FF_RX_D_2_12 | output | TCELL13:OUT_Q2 |
| FF_RX_D_2_13 | output | TCELL13:OUT_Q4 |
| FF_RX_D_2_14 | output | TCELL13:OUT_Q6 |
| FF_RX_D_2_15 | output | TCELL13:OUT_Q7 |
| FF_RX_D_2_16 | output | TCELL14:OUT_F0 |
| FF_RX_D_2_17 | output | TCELL14:OUT_F2 |
| FF_RX_D_2_18 | output | TCELL14:OUT_F4 |
| FF_RX_D_2_19 | output | TCELL14:OUT_Q0 |
| FF_RX_D_2_2 | output | TCELL10:OUT_Q6 |
| FF_RX_D_2_20 | output | TCELL14:OUT_Q2 |
| FF_RX_D_2_21 | output | TCELL14:OUT_Q4 |
| FF_RX_D_2_22 | output | TCELL14:OUT_Q6 |
| FF_RX_D_2_23 | output | TCELL14:OUT_Q7 |
| FF_RX_D_2_3 | output | TCELL10:OUT_Q7 |
| FF_RX_D_2_4 | output | TCELL11:OUT_F0 |
| FF_RX_D_2_5 | output | TCELL11:OUT_F1 |
| FF_RX_D_2_6 | output | TCELL11:OUT_F2 |
| FF_RX_D_2_7 | output | TCELL11:OUT_F3 |
| FF_RX_D_2_8 | output | TCELL13:OUT_F0 |
| FF_RX_D_2_9 | output | TCELL13:OUT_F2 |
| FF_RX_D_3_0 | output | TCELL4:OUT_F5 |
| FF_RX_D_3_1 | output | TCELL4:OUT_F4 |
| FF_RX_D_3_10 | output | TCELL1:OUT_Q7 |
| FF_RX_D_3_11 | output | TCELL1:OUT_Q6 |
| FF_RX_D_3_12 | output | TCELL1:OUT_Q5 |
| FF_RX_D_3_13 | output | TCELL1:OUT_Q4 |
| FF_RX_D_3_14 | output | TCELL1:OUT_Q3 |
| FF_RX_D_3_15 | output | TCELL1:OUT_Q2 |
| FF_RX_D_3_16 | output | TCELL1:OUT_Q1 |
| FF_RX_D_3_17 | output | TCELL1:OUT_Q0 |
| FF_RX_D_3_18 | output | TCELL1:OUT_F5 |
| FF_RX_D_3_19 | output | TCELL1:OUT_F4 |
| FF_RX_D_3_2 | output | TCELL4:OUT_F3 |
| FF_RX_D_3_20 | output | TCELL1:OUT_F3 |
| FF_RX_D_3_21 | output | TCELL1:OUT_F2 |
| FF_RX_D_3_22 | output | TCELL1:OUT_F1 |
| FF_RX_D_3_23 | output | TCELL1:OUT_F0 |
| FF_RX_D_3_3 | output | TCELL4:OUT_F2 |
| FF_RX_D_3_4 | output | TCELL4:OUT_F1 |
| FF_RX_D_3_5 | output | TCELL4:OUT_F0 |
| FF_RX_D_3_6 | output | TCELL3:OUT_Q7 |
| FF_RX_D_3_7 | output | TCELL3:OUT_Q5 |
| FF_RX_D_3_8 | output | TCELL2:OUT_F2 |
| FF_RX_D_3_9 | output | TCELL2:OUT_F0 |
| FF_RX_F_CLK_0 | output | TCELL33:OUT_F7 |
| FF_RX_F_CLK_1 | output | TCELL23:OUT_F6 |
| FF_RX_F_CLK_2 | output | TCELL12:OUT_F7 |
| FF_RX_F_CLK_3 | output | TCELL2:OUT_F6 |
| FF_RX_H_CLK_0 | output | TCELL33:OUT_F6 |
| FF_RX_H_CLK_1 | output | TCELL23:OUT_F7 |
| FF_RX_H_CLK_2 | output | TCELL12:OUT_F6 |
| FF_RX_H_CLK_3 | output | TCELL2:OUT_F7 |
| FF_TXI_CLK_0 | input | TCELL30:IMUX_CLK0 |
| FF_TXI_CLK_1 | input | TCELL26:IMUX_CLK1 |
| FF_TXI_CLK_2 | input | TCELL9:IMUX_CLK0 |
| FF_TXI_CLK_3 | input | TCELL5:IMUX_CLK1 |
| FF_TX_D_0_0 | input | TCELL31:IMUX_D0 |
| FF_TX_D_0_1 | input | TCELL31:IMUX_B1 |
| FF_TX_D_0_10 | input | TCELL32:IMUX_B1 |
| FF_TX_D_0_11 | input | TCELL32:IMUX_D1 |
| FF_TX_D_0_12 | input | TCELL32:IMUX_B2 |
| FF_TX_D_0_13 | input | TCELL32:IMUX_D2 |
| FF_TX_D_0_14 | input | TCELL32:IMUX_B3 |
| FF_TX_D_0_15 | input | TCELL32:IMUX_D3 |
| FF_TX_D_0_16 | input | TCELL33:IMUX_B0 |
| FF_TX_D_0_17 | input | TCELL33:IMUX_D0 |
| FF_TX_D_0_18 | input | TCELL33:IMUX_B1 |
| FF_TX_D_0_19 | input | TCELL33:IMUX_D1 |
| FF_TX_D_0_2 | input | TCELL31:IMUX_D1 |
| FF_TX_D_0_20 | input | TCELL33:IMUX_B2 |
| FF_TX_D_0_21 | input | TCELL33:IMUX_D2 |
| FF_TX_D_0_22 | input | TCELL33:IMUX_B3 |
| FF_TX_D_0_23 | input | TCELL33:IMUX_D3 |
| FF_TX_D_0_3 | input | TCELL31:IMUX_B2 |
| FF_TX_D_0_4 | input | TCELL31:IMUX_D2 |
| FF_TX_D_0_5 | input | TCELL31:IMUX_B3 |
| FF_TX_D_0_6 | input | TCELL31:IMUX_D3 |
| FF_TX_D_0_7 | input | TCELL31:IMUX_B4 |
| FF_TX_D_0_8 | input | TCELL32:IMUX_B0 |
| FF_TX_D_0_9 | input | TCELL32:IMUX_D0 |
| FF_TX_D_1_0 | input | TCELL25:IMUX_D3 |
| FF_TX_D_1_1 | input | TCELL25:IMUX_B3 |
| FF_TX_D_1_10 | input | TCELL24:IMUX_D2 |
| FF_TX_D_1_11 | input | TCELL24:IMUX_B2 |
| FF_TX_D_1_12 | input | TCELL24:IMUX_D1 |
| FF_TX_D_1_13 | input | TCELL24:IMUX_B1 |
| FF_TX_D_1_14 | input | TCELL24:IMUX_D0 |
| FF_TX_D_1_15 | input | TCELL24:IMUX_B0 |
| FF_TX_D_1_16 | input | TCELL23:IMUX_B5 |
| FF_TX_D_1_17 | input | TCELL23:IMUX_D4 |
| FF_TX_D_1_18 | input | TCELL23:IMUX_B4 |
| FF_TX_D_1_19 | input | TCELL23:IMUX_D3 |
| FF_TX_D_1_2 | input | TCELL25:IMUX_D2 |
| FF_TX_D_1_20 | input | TCELL23:IMUX_B3 |
| FF_TX_D_1_21 | input | TCELL23:IMUX_D2 |
| FF_TX_D_1_22 | input | TCELL23:IMUX_B2 |
| FF_TX_D_1_23 | input | TCELL23:IMUX_D1 |
| FF_TX_D_1_3 | input | TCELL25:IMUX_B2 |
| FF_TX_D_1_4 | input | TCELL25:IMUX_D1 |
| FF_TX_D_1_5 | input | TCELL25:IMUX_B1 |
| FF_TX_D_1_6 | input | TCELL25:IMUX_D0 |
| FF_TX_D_1_7 | input | TCELL25:IMUX_B0 |
| FF_TX_D_1_8 | input | TCELL24:IMUX_D3 |
| FF_TX_D_1_9 | input | TCELL24:IMUX_B3 |
| FF_TX_D_2_0 | input | TCELL10:IMUX_C0 |
| FF_TX_D_2_1 | input | TCELL10:IMUX_A1 |
| FF_TX_D_2_10 | input | TCELL11:IMUX_A1 |
| FF_TX_D_2_11 | input | TCELL11:IMUX_C1 |
| FF_TX_D_2_12 | input | TCELL11:IMUX_A2 |
| FF_TX_D_2_13 | input | TCELL11:IMUX_C2 |
| FF_TX_D_2_14 | input | TCELL11:IMUX_A3 |
| FF_TX_D_2_15 | input | TCELL11:IMUX_C3 |
| FF_TX_D_2_16 | input | TCELL12:IMUX_B0 |
| FF_TX_D_2_17 | input | TCELL12:IMUX_D0 |
| FF_TX_D_2_18 | input | TCELL12:IMUX_B1 |
| FF_TX_D_2_19 | input | TCELL12:IMUX_D1 |
| FF_TX_D_2_2 | input | TCELL10:IMUX_C1 |
| FF_TX_D_2_20 | input | TCELL12:IMUX_B2 |
| FF_TX_D_2_21 | input | TCELL12:IMUX_D2 |
| FF_TX_D_2_22 | input | TCELL12:IMUX_B3 |
| FF_TX_D_2_23 | input | TCELL12:IMUX_D3 |
| FF_TX_D_2_3 | input | TCELL10:IMUX_A2 |
| FF_TX_D_2_4 | input | TCELL10:IMUX_C2 |
| FF_TX_D_2_5 | input | TCELL10:IMUX_A3 |
| FF_TX_D_2_6 | input | TCELL10:IMUX_C3 |
| FF_TX_D_2_7 | input | TCELL10:IMUX_A4 |
| FF_TX_D_2_8 | input | TCELL11:IMUX_A0 |
| FF_TX_D_2_9 | input | TCELL11:IMUX_C0 |
| FF_TX_D_3_0 | input | TCELL4:IMUX_C3 |
| FF_TX_D_3_1 | input | TCELL4:IMUX_A3 |
| FF_TX_D_3_10 | input | TCELL3:IMUX_C2 |
| FF_TX_D_3_11 | input | TCELL3:IMUX_A2 |
| FF_TX_D_3_12 | input | TCELL3:IMUX_C1 |
| FF_TX_D_3_13 | input | TCELL3:IMUX_A1 |
| FF_TX_D_3_14 | input | TCELL3:IMUX_C0 |
| FF_TX_D_3_15 | input | TCELL3:IMUX_A0 |
| FF_TX_D_3_16 | input | TCELL2:IMUX_C5 |
| FF_TX_D_3_17 | input | TCELL2:IMUX_A5 |
| FF_TX_D_3_18 | input | TCELL2:IMUX_C4 |
| FF_TX_D_3_19 | input | TCELL2:IMUX_A4 |
| FF_TX_D_3_2 | input | TCELL4:IMUX_C2 |
| FF_TX_D_3_20 | input | TCELL2:IMUX_C3 |
| FF_TX_D_3_21 | input | TCELL2:IMUX_A3 |
| FF_TX_D_3_22 | input | TCELL2:IMUX_C2 |
| FF_TX_D_3_23 | input | TCELL2:IMUX_A2 |
| FF_TX_D_3_3 | input | TCELL4:IMUX_A2 |
| FF_TX_D_3_4 | input | TCELL4:IMUX_C1 |
| FF_TX_D_3_5 | input | TCELL4:IMUX_A1 |
| FF_TX_D_3_6 | input | TCELL4:IMUX_C0 |
| FF_TX_D_3_7 | input | TCELL4:IMUX_A0 |
| FF_TX_D_3_8 | input | TCELL3:IMUX_C3 |
| FF_TX_D_3_9 | input | TCELL3:IMUX_A3 |
| FF_TX_F_CLK_0 | output | TCELL31:OUT_F7 |
| FF_TX_F_CLK_1 | output | TCELL25:OUT_F6 |
| FF_TX_F_CLK_2 | output | TCELL10:OUT_F7 |
| FF_TX_F_CLK_3 | output | TCELL4:OUT_F6 |
| FF_TX_H_CLK_0 | output | TCELL31:OUT_F6 |
| FF_TX_H_CLK_1 | output | TCELL25:OUT_F7 |
| FF_TX_H_CLK_2 | output | TCELL10:OUT_F6 |
| FF_TX_H_CLK_3 | output | TCELL4:OUT_F7 |
| LDR_CORE2TX_0 | input | TCELL31:IMUX_B0 |
| LDR_CORE2TX_1 | input | TCELL25:IMUX_B4 |
| LDR_CORE2TX_2 | input | TCELL10:IMUX_A0 |
| LDR_CORE2TX_3 | input | TCELL4:IMUX_A4 |
| LDR_RX2CORE_0 | output | TCELL31:OUT_F1 |
| LDR_RX2CORE_1 | output | TCELL25:OUT_Q5 |
| LDR_RX2CORE_2 | output | TCELL10:OUT_F2 |
| LDR_RX2CORE_3 | output | TCELL4:OUT_Q5 |
| PCIE_PHYSTATUS_0 | output | TCELL29:OUT_Q1 |
| PCIE_PHYSTATUS_1 | output | TCELL27:OUT_F2 |
| PCIE_PHYSTATUS_2 | output | TCELL8:OUT_Q2 |
| PCIE_PHYSTATUS_3 | output | TCELL6:OUT_F3 |
| PCIE_POWERDOWN_0_0 | input | TCELL29:IMUX_B3 |
| PCIE_POWERDOWN_0_1 | input | TCELL29:IMUX_B4 |
| PCIE_POWERDOWN_1_0 | input | TCELL27:IMUX_B1 |
| PCIE_POWERDOWN_1_1 | input | TCELL27:IMUX_B0 |
| PCIE_POWERDOWN_2_0 | input | TCELL8:IMUX_A3 |
| PCIE_POWERDOWN_2_1 | input | TCELL8:IMUX_A4 |
| PCIE_POWERDOWN_3_0 | input | TCELL6:IMUX_A1 |
| PCIE_POWERDOWN_3_1 | input | TCELL6:IMUX_B0 |
| PCIE_RXPOLARITY_0 | input | TCELL29:IMUX_B2 |
| PCIE_RXPOLARITY_1 | input | TCELL27:IMUX_B2 |
| PCIE_RXPOLARITY_2 | input | TCELL8:IMUX_A2 |
| PCIE_RXPOLARITY_3 | input | TCELL6:IMUX_D1 |
| PCIE_RXVALID_0 | output | TCELL29:OUT_Q3 |
| PCIE_RXVALID_1 | output | TCELL27:OUT_F0 |
| PCIE_RXVALID_2 | output | TCELL8:OUT_Q5 |
| PCIE_RXVALID_3 | output | TCELL6:OUT_F0 |
| PCIE_TXCOMPLIANCE_0 | input | TCELL29:IMUX_B1 |
| PCIE_TXCOMPLIANCE_1 | input | TCELL27:IMUX_B3 |
| PCIE_TXCOMPLIANCE_2 | input | TCELL8:IMUX_A1 |
| PCIE_TXCOMPLIANCE_3 | input | TCELL6:IMUX_C2 |
| PCIE_TXDETRX_PR2TLB_0 | input | TCELL29:IMUX_B0 |
| PCIE_TXDETRX_PR2TLB_1 | input | TCELL27:IMUX_B4 |
| PCIE_TXDETRX_PR2TLB_2 | input | TCELL8:IMUX_A0 |
| PCIE_TXDETRX_PR2TLB_3 | input | TCELL6:IMUX_B3 |
| REFCK2CORE | output | TCELL20:OUT_F6 |
| SCIADDR0 | input | TCELL17:IMUX_C2 |
| SCIADDR1 | input | TCELL17:IMUX_A2 |
| SCIADDR2 | input | TCELL17:IMUX_C1 |
| SCIADDR3 | input | TCELL17:IMUX_A1 |
| SCIADDR4 | input | TCELL17:IMUX_C0 |
| SCIADDR5 | input | TCELL17:IMUX_A0 |
| SCIENAUX | input | TCELL18:IMUX_B2 |
| SCIENCH0 | input | TCELL20:IMUX_B1 |
| SCIENCH1 | input | TCELL19:IMUX_B1 |
| SCIENCH2 | input | TCELL16:IMUX_B2 |
| SCIENCH3 | input | TCELL15:IMUX_B1 |
| SCIINT | output | TCELL17:OUT_F0 |
| SCIRD | input | TCELL17:IMUX_A3 |
| SCIRDATA0 | output | TCELL17:OUT_Q2 |
| SCIRDATA1 | output | TCELL17:OUT_Q1 |
| SCIRDATA2 | output | TCELL17:OUT_Q0 |
| SCIRDATA3 | output | TCELL17:OUT_F5 |
| SCIRDATA4 | output | TCELL17:OUT_F4 |
| SCIRDATA5 | output | TCELL17:OUT_F3 |
| SCIRDATA6 | output | TCELL17:OUT_F2 |
| SCIRDATA7 | output | TCELL17:OUT_F1 |
| SCISELAUX | input | TCELL18:IMUX_C2 |
| SCISELCH0 | input | TCELL20:IMUX_B0 |
| SCISELCH1 | input | TCELL19:IMUX_B0 |
| SCISELCH2 | input | TCELL16:IMUX_B3 |
| SCISELCH3 | input | TCELL15:IMUX_B2 |
| SCIWDATA0 | input | TCELL18:IMUX_C0 |
| SCIWDATA1 | input | TCELL18:IMUX_B0 |
| SCIWDATA2 | input | TCELL18:IMUX_A0 |
| SCIWDATA3 | input | TCELL17:IMUX_C5 |
| SCIWDATA4 | input | TCELL17:IMUX_A5 |
| SCIWDATA5 | input | TCELL17:IMUX_C4 |
| SCIWDATA6 | input | TCELL17:IMUX_A4 |
| SCIWDATA7 | input | TCELL17:IMUX_C3 |
| SCIWSTN | input | TCELL18:IMUX_D0 |
Bel wires
| Wire | Pins |
|---|---|
| TCELL1:IMUX_A1 | SERDES.FFC_PCI_DET_EN_3 |
| TCELL1:IMUX_A2 | SERDES.FFC_SB_PFIFO_LP_3 |
| TCELL1:IMUX_A4 | SERDES.FFC_EI_EN_3 |
| TCELL1:IMUX_A5 | SERDES.FFC_PCIE_CT_3 |
| TCELL1:IMUX_C0 | SERDES.FFC_RXPWDNB_3 |
| TCELL1:IMUX_C1 | SERDES.FFC_SB_INV_RX_3 |
| TCELL1:IMUX_C2 | SERDES.FFC_SIGNAL_DETECT_3 |
| TCELL1:IMUX_C4 | SERDES.FFC_FB_LOOPBACK_3 |
| TCELL1:IMUX_C5 | SERDES.FFC_PFIFO_CLR_3 |
| TCELL1:IMUX_CLK1 | SERDES.FF_EBRD_CLK_3 |
| TCELL1:IMUX_LSR0 | SERDES.FFC_LANE_RX_RST_3 |
| TCELL1:OUT_F0 | SERDES.FF_RX_D_3_23 |
| TCELL1:OUT_F1 | SERDES.FF_RX_D_3_22 |
| TCELL1:OUT_F2 | SERDES.FF_RX_D_3_21 |
| TCELL1:OUT_F3 | SERDES.FF_RX_D_3_20 |
| TCELL1:OUT_F4 | SERDES.FF_RX_D_3_19 |
| TCELL1:OUT_F5 | SERDES.FF_RX_D_3_18 |
| TCELL1:OUT_Q0 | SERDES.FF_RX_D_3_17 |
| TCELL1:OUT_Q1 | SERDES.FF_RX_D_3_16 |
| TCELL1:OUT_Q2 | SERDES.FF_RX_D_3_15 |
| TCELL1:OUT_Q3 | SERDES.FF_RX_D_3_14 |
| TCELL1:OUT_Q4 | SERDES.FF_RX_D_3_13 |
| TCELL1:OUT_Q5 | SERDES.FF_RX_D_3_12 |
| TCELL1:OUT_Q6 | SERDES.FF_RX_D_3_11 |
| TCELL1:OUT_Q7 | SERDES.FF_RX_D_3_10 |
| TCELL2:IMUX_A1 | SERDES.FFC_RATE_MODE_TX_3 |
| TCELL2:IMUX_A2 | SERDES.FF_TX_D_3_23 |
| TCELL2:IMUX_A3 | SERDES.FF_TX_D_3_21 |
| TCELL2:IMUX_A4 | SERDES.FF_TX_D_3_19 |
| TCELL2:IMUX_A5 | SERDES.FF_TX_D_3_17 |
| TCELL2:IMUX_B1 | SERDES.FFC_DIV11_MODE_RX_3 |
| TCELL2:IMUX_C0 | SERDES.FFC_ENABLE_CGALIGN_3 |
| TCELL2:IMUX_C1 | SERDES.FFC_DIV11_MODE_TX_3 |
| TCELL2:IMUX_C2 | SERDES.FF_TX_D_3_22 |
| TCELL2:IMUX_C3 | SERDES.FF_TX_D_3_20 |
| TCELL2:IMUX_C4 | SERDES.FF_TX_D_3_18 |
| TCELL2:IMUX_C5 | SERDES.FF_TX_D_3_16 |
| TCELL2:IMUX_D0 | SERDES.FFC_RATE_MODE_RX_3 |
| TCELL2:IMUX_CLK0 | SERDES.FF_RXI_CLK_3 |
| TCELL2:OUT_F0 | SERDES.FF_RX_D_3_9 |
| TCELL2:OUT_F2 | SERDES.FF_RX_D_3_8 |
| TCELL2:OUT_F6 | SERDES.FF_RX_F_CLK_3 |
| TCELL2:OUT_F7 | SERDES.FF_RX_H_CLK_3 |
| TCELL3:IMUX_A0 | SERDES.FF_TX_D_3_15 |
| TCELL3:IMUX_A1 | SERDES.FF_TX_D_3_13 |
| TCELL3:IMUX_A2 | SERDES.FF_TX_D_3_11 |
| TCELL3:IMUX_A3 | SERDES.FF_TX_D_3_9 |
| TCELL3:IMUX_C0 | SERDES.FF_TX_D_3_14 |
| TCELL3:IMUX_C1 | SERDES.FF_TX_D_3_12 |
| TCELL3:IMUX_C2 | SERDES.FF_TX_D_3_10 |
| TCELL3:IMUX_C3 | SERDES.FF_TX_D_3_8 |
| TCELL3:OUT_F1 | SERDES.FFS_RLOS_HI_3 |
| TCELL3:OUT_F3 | SERDES.FFS_RLOS_LO_3 |
| TCELL3:OUT_Q2 | SERDES.FFS_RLOL_3 |
| TCELL3:OUT_Q5 | SERDES.FF_RX_D_3_7 |
| TCELL3:OUT_Q7 | SERDES.FF_RX_D_3_6 |
| TCELL4:IMUX_A0 | SERDES.FF_TX_D_3_7 |
| TCELL4:IMUX_A1 | SERDES.FF_TX_D_3_5 |
| TCELL4:IMUX_A2 | SERDES.FF_TX_D_3_3 |
| TCELL4:IMUX_A3 | SERDES.FF_TX_D_3_1 |
| TCELL4:IMUX_A4 | SERDES.LDR_CORE2TX_3 |
| TCELL4:IMUX_C0 | SERDES.FF_TX_D_3_6 |
| TCELL4:IMUX_C1 | SERDES.FF_TX_D_3_4 |
| TCELL4:IMUX_C2 | SERDES.FF_TX_D_3_2 |
| TCELL4:IMUX_C3 | SERDES.FF_TX_D_3_0 |
| TCELL4:IMUX_C4 | SERDES.FFC_LDR_CORE2TX_EN_3 |
| TCELL4:OUT_F0 | SERDES.FF_RX_D_3_5 |
| TCELL4:OUT_F1 | SERDES.FF_RX_D_3_4 |
| TCELL4:OUT_F2 | SERDES.FF_RX_D_3_3 |
| TCELL4:OUT_F3 | SERDES.FF_RX_D_3_2 |
| TCELL4:OUT_F4 | SERDES.FF_RX_D_3_1 |
| TCELL4:OUT_F5 | SERDES.FF_RX_D_3_0 |
| TCELL4:OUT_F6 | SERDES.FF_TX_F_CLK_3 |
| TCELL4:OUT_F7 | SERDES.FF_TX_H_CLK_3 |
| TCELL4:OUT_Q1 | SERDES.FFS_CC_OVERRUN_3 |
| TCELL4:OUT_Q3 | SERDES.FFS_LS_SYNC_STATUS_3 |
| TCELL4:OUT_Q5 | SERDES.LDR_RX2CORE_3 |
| TCELL4:OUT_Q7 | SERDES.FFS_CDR_TRAIN_DONE_3 |
| TCELL5:IMUX_B0 | SERDES.FFC_TXPWDNB_3 |
| TCELL5:IMUX_CLK0 | SERDES.FFC_CK_CORE_RX_3 |
| TCELL5:IMUX_CLK1 | SERDES.FF_TXI_CLK_3 |
| TCELL5:IMUX_LSR0 | SERDES.FFC_LANE_TX_RST_3 |
| TCELL5:OUT_F4 | SERDES.FFS_CC_UNDERRUN_3 |
| TCELL6:IMUX_A1 | SERDES.PCIE_POWERDOWN_3_0 |
| TCELL6:IMUX_B0 | SERDES.PCIE_POWERDOWN_3_1 |
| TCELL6:IMUX_B3 | SERDES.PCIE_TXDETRX_PR2TLB_3 |
| TCELL6:IMUX_C2 | SERDES.PCIE_TXCOMPLIANCE_3 |
| TCELL6:IMUX_D1 | SERDES.PCIE_RXPOLARITY_3 |
| TCELL6:OUT_F0 | SERDES.PCIE_RXVALID_3 |
| TCELL6:OUT_F3 | SERDES.PCIE_PHYSTATUS_3 |
| TCELL6:OUT_Q1 | SERDES.FFS_SKP_ADDED_3 |
| TCELL6:OUT_Q5 | SERDES.FFS_SKP_DELETED_3 |
| TCELL7:OUT_F0 | SERDES.FFS_PCIE_CON_3 |
| TCELL7:OUT_F2 | SERDES.FFS_PCIE_DONE_3 |
| TCELL7:OUT_F4 | SERDES.FFS_TXFBFIFO_ERROR_3 |
| TCELL7:OUT_Q0 | SERDES.FFS_RXFBFIFO_ERROR_3 |
| TCELL7:OUT_Q1 | SERDES.FFS_RXFBFIFO_ERROR_2 |
| TCELL7:OUT_Q3 | SERDES.FFS_TXFBFIFO_ERROR_2 |
| TCELL7:OUT_Q5 | SERDES.FFS_PCIE_DONE_2 |
| TCELL7:OUT_Q7 | SERDES.FFS_PCIE_CON_2 |
| TCELL8:IMUX_A0 | SERDES.PCIE_TXDETRX_PR2TLB_2 |
| TCELL8:IMUX_A1 | SERDES.PCIE_TXCOMPLIANCE_2 |
| TCELL8:IMUX_A2 | SERDES.PCIE_RXPOLARITY_2 |
| TCELL8:IMUX_A3 | SERDES.PCIE_POWERDOWN_2_0 |
| TCELL8:IMUX_A4 | SERDES.PCIE_POWERDOWN_2_1 |
| TCELL8:OUT_F1 | SERDES.FFS_SKP_DELETED_2 |
| TCELL8:OUT_F4 | SERDES.FFS_SKP_ADDED_2 |
| TCELL8:OUT_Q2 | SERDES.PCIE_PHYSTATUS_2 |
| TCELL8:OUT_Q5 | SERDES.PCIE_RXVALID_2 |
| TCELL9:IMUX_A3 | SERDES.FFC_TXPWDNB_2 |
| TCELL9:IMUX_CLK0 | SERDES.FF_TXI_CLK_2 |
| TCELL9:IMUX_CLK1 | SERDES.FFC_CK_CORE_RX_2 |
| TCELL9:IMUX_LSR0 | SERDES.FFC_LANE_TX_RST_2 |
| TCELL9:OUT_F2 | SERDES.FFS_CC_UNDERRUN_2 |
| TCELL10:IMUX_A0 | SERDES.LDR_CORE2TX_2 |
| TCELL10:IMUX_A1 | SERDES.FF_TX_D_2_1 |
| TCELL10:IMUX_A2 | SERDES.FF_TX_D_2_3 |
| TCELL10:IMUX_A3 | SERDES.FF_TX_D_2_5 |
| TCELL10:IMUX_A4 | SERDES.FF_TX_D_2_7 |
| TCELL10:IMUX_C0 | SERDES.FF_TX_D_2_0 |
| TCELL10:IMUX_C1 | SERDES.FF_TX_D_2_2 |
| TCELL10:IMUX_C2 | SERDES.FF_TX_D_2_4 |
| TCELL10:IMUX_C3 | SERDES.FF_TX_D_2_6 |
| TCELL10:IMUX_C4 | SERDES.FFC_LDR_CORE2TX_EN_2 |
| TCELL10:OUT_F0 | SERDES.FFS_CDR_TRAIN_DONE_2 |
| TCELL10:OUT_F2 | SERDES.LDR_RX2CORE_2 |
| TCELL10:OUT_F4 | SERDES.FFS_LS_SYNC_STATUS_2 |
| TCELL10:OUT_F6 | SERDES.FF_TX_H_CLK_2 |
| TCELL10:OUT_F7 | SERDES.FF_TX_F_CLK_2 |
| TCELL10:OUT_Q2 | SERDES.FFS_CC_OVERRUN_2 |
| TCELL10:OUT_Q4 | SERDES.FF_RX_D_2_0 |
| TCELL10:OUT_Q5 | SERDES.FF_RX_D_2_1 |
| TCELL10:OUT_Q6 | SERDES.FF_RX_D_2_2 |
| TCELL10:OUT_Q7 | SERDES.FF_RX_D_2_3 |
| TCELL11:IMUX_A0 | SERDES.FF_TX_D_2_8 |
| TCELL11:IMUX_A1 | SERDES.FF_TX_D_2_10 |
| TCELL11:IMUX_A2 | SERDES.FF_TX_D_2_12 |
| TCELL11:IMUX_A3 | SERDES.FF_TX_D_2_14 |
| TCELL11:IMUX_C0 | SERDES.FF_TX_D_2_9 |
| TCELL11:IMUX_C1 | SERDES.FF_TX_D_2_11 |
| TCELL11:IMUX_C2 | SERDES.FF_TX_D_2_13 |
| TCELL11:IMUX_C3 | SERDES.FF_TX_D_2_15 |
| TCELL11:OUT_F0 | SERDES.FF_RX_D_2_4 |
| TCELL11:OUT_F1 | SERDES.FF_RX_D_2_5 |
| TCELL11:OUT_F2 | SERDES.FF_RX_D_2_6 |
| TCELL11:OUT_F3 | SERDES.FF_RX_D_2_7 |
| TCELL11:OUT_Q1 | SERDES.FFS_RLOL_2 |
| TCELL11:OUT_Q3 | SERDES.FFS_RLOS_LO_2 |
| TCELL11:OUT_Q5 | SERDES.FFS_RLOS_HI_2 |
| TCELL12:IMUX_A5 | SERDES.FFC_RATE_MODE_RX_2 |
| TCELL12:IMUX_B0 | SERDES.FF_TX_D_2_16 |
| TCELL12:IMUX_B1 | SERDES.FF_TX_D_2_18 |
| TCELL12:IMUX_B2 | SERDES.FF_TX_D_2_20 |
| TCELL12:IMUX_B3 | SERDES.FF_TX_D_2_22 |
| TCELL12:IMUX_B4 | SERDES.FFC_DIV11_MODE_TX_2 |
| TCELL12:IMUX_B5 | SERDES.FFC_ENABLE_CGALIGN_2 |
| TCELL12:IMUX_C4 | SERDES.FFC_DIV11_MODE_RX_2 |
| TCELL12:IMUX_D0 | SERDES.FF_TX_D_2_17 |
| TCELL12:IMUX_D1 | SERDES.FF_TX_D_2_19 |
| TCELL12:IMUX_D2 | SERDES.FF_TX_D_2_21 |
| TCELL12:IMUX_D3 | SERDES.FF_TX_D_2_23 |
| TCELL12:IMUX_D4 | SERDES.FFC_RATE_MODE_TX_2 |
| TCELL12:OUT_F6 | SERDES.FF_RX_H_CLK_2 |
| TCELL12:OUT_F7 | SERDES.FF_RX_F_CLK_2 |
| TCELL13:IMUX_B1 | SERDES.FFC_PFIFO_CLR_2 |
| TCELL13:IMUX_B2 | SERDES.FFC_PCIE_CT_2 |
| TCELL13:IMUX_B3 | SERDES.FFC_FB_LOOPBACK_2 |
| TCELL13:IMUX_B4 | SERDES.FFC_EI_EN_2 |
| TCELL13:IMUX_CLK0 | SERDES.FF_RXI_CLK_2 |
| TCELL13:IMUX_LSR0 | SERDES.FFC_LANE_RX_RST_2 |
| TCELL13:OUT_F0 | SERDES.FF_RX_D_2_8 |
| TCELL13:OUT_F2 | SERDES.FF_RX_D_2_9 |
| TCELL13:OUT_F4 | SERDES.FF_RX_D_2_10 |
| TCELL13:OUT_Q0 | SERDES.FF_RX_D_2_11 |
| TCELL13:OUT_Q2 | SERDES.FF_RX_D_2_12 |
| TCELL13:OUT_Q4 | SERDES.FF_RX_D_2_13 |
| TCELL13:OUT_Q6 | SERDES.FF_RX_D_2_14 |
| TCELL13:OUT_Q7 | SERDES.FF_RX_D_2_15 |
| TCELL14:IMUX_B1 | SERDES.FFC_SIGNAL_DETECT_2 |
| TCELL14:IMUX_B2 | SERDES.FFC_SB_PFIFO_LP_2 |
| TCELL14:IMUX_B3 | SERDES.FFC_SB_INV_RX_2 |
| TCELL14:IMUX_B4 | SERDES.FFC_PCI_DET_EN_2 |
| TCELL14:IMUX_B5 | SERDES.FFC_RXPWDNB_2 |
| TCELL14:IMUX_CLK0 | SERDES.FF_EBRD_CLK_2 |
| TCELL14:OUT_F0 | SERDES.FF_RX_D_2_16 |
| TCELL14:OUT_F2 | SERDES.FF_RX_D_2_17 |
| TCELL14:OUT_F4 | SERDES.FF_RX_D_2_18 |
| TCELL14:OUT_Q0 | SERDES.FF_RX_D_2_19 |
| TCELL14:OUT_Q2 | SERDES.FF_RX_D_2_20 |
| TCELL14:OUT_Q4 | SERDES.FF_RX_D_2_21 |
| TCELL14:OUT_Q6 | SERDES.FF_RX_D_2_22 |
| TCELL14:OUT_Q7 | SERDES.FF_RX_D_2_23 |
| TCELL15:IMUX_B1 | SERDES.SCIENCH3 |
| TCELL15:IMUX_B2 | SERDES.SCISELCH3 |
| TCELL15:IMUX_LSR0 | SERDES.FFC_RRST_3 |
| TCELL16:IMUX_B2 | SERDES.SCIENCH2 |
| TCELL16:IMUX_B3 | SERDES.SCISELCH2 |
| TCELL16:IMUX_CLK0 | SERDES.FFC_CK_CORE_TX |
| TCELL16:IMUX_LSR1 | SERDES.FFC_RRST_2 |
| TCELL17:IMUX_A0 | SERDES.SCIADDR5 |
| TCELL17:IMUX_A1 | SERDES.SCIADDR3 |
| TCELL17:IMUX_A2 | SERDES.SCIADDR1 |
| TCELL17:IMUX_A3 | SERDES.SCIRD |
| TCELL17:IMUX_A4 | SERDES.SCIWDATA6 |
| TCELL17:IMUX_A5 | SERDES.SCIWDATA4 |
| TCELL17:IMUX_C0 | SERDES.SCIADDR4 |
| TCELL17:IMUX_C1 | SERDES.SCIADDR2 |
| TCELL17:IMUX_C2 | SERDES.SCIADDR0 |
| TCELL17:IMUX_C3 | SERDES.SCIWDATA7 |
| TCELL17:IMUX_C4 | SERDES.SCIWDATA5 |
| TCELL17:IMUX_C5 | SERDES.SCIWDATA3 |
| TCELL17:OUT_F0 | SERDES.SCIINT |
| TCELL17:OUT_F1 | SERDES.SCIRDATA7 |
| TCELL17:OUT_F2 | SERDES.SCIRDATA6 |
| TCELL17:OUT_F3 | SERDES.SCIRDATA5 |
| TCELL17:OUT_F4 | SERDES.SCIRDATA4 |
| TCELL17:OUT_F5 | SERDES.SCIRDATA3 |
| TCELL17:OUT_Q0 | SERDES.SCIRDATA2 |
| TCELL17:OUT_Q1 | SERDES.SCIRDATA1 |
| TCELL17:OUT_Q2 | SERDES.SCIRDATA0 |
| TCELL17:OUT_Q3 | SERDES.FFS_BIST_RPT_15 |
| TCELL17:OUT_Q4 | SERDES.FFS_BIST_RPT_14 |
| TCELL17:OUT_Q5 | SERDES.FFS_BIST_RPT_13 |
| TCELL17:OUT_Q6 | SERDES.FFS_BIST_RPT_12 |
| TCELL17:OUT_Q7 | SERDES.FFS_BIST_RPT_11 |
| TCELL18:IMUX_A0 | SERDES.SCIWDATA2 |
| TCELL18:IMUX_A2 | SERDES.FFC_SYNC_TOGGLE |
| TCELL18:IMUX_A3 | SERDES.CIN10 |
| TCELL18:IMUX_A4 | SERDES.CIN6 |
| TCELL18:IMUX_A5 | SERDES.CIN2 |
| TCELL18:IMUX_B0 | SERDES.SCIWDATA1 |
| TCELL18:IMUX_B2 | SERDES.SCIENAUX |
| TCELL18:IMUX_B3 | SERDES.CIN9 |
| TCELL18:IMUX_B4 | SERDES.CIN5 |
| TCELL18:IMUX_B5 | SERDES.CIN1 |
| TCELL18:IMUX_C0 | SERDES.SCIWDATA0 |
| TCELL18:IMUX_C2 | SERDES.SCISELAUX |
| TCELL18:IMUX_C3 | SERDES.CIN8 |
| TCELL18:IMUX_C4 | SERDES.CIN4 |
| TCELL18:IMUX_C5 | SERDES.CIN0 |
| TCELL18:IMUX_D0 | SERDES.SCIWSTN |
| TCELL18:IMUX_D1 | SERDES.CYAWSTN |
| TCELL18:IMUX_D2 | SERDES.CIN11 |
| TCELL18:IMUX_D3 | SERDES.CIN7 |
| TCELL18:IMUX_D4 | SERDES.CIN3 |
| TCELL18:IMUX_LSR0 | SERDES.FFC_MACRO_RST |
| TCELL18:IMUX_LSR1 | SERDES.FFC_QUAD_RST |
| TCELL18:IMUX_LSR2 | SERDES.FFC_TRST |
| TCELL18:OUT_F0 | SERDES.FFS_BIST_RPT_10 |
| TCELL18:OUT_F1 | SERDES.FFS_BIST_RPT_9 |
| TCELL18:OUT_F2 | SERDES.FFS_BIST_RPT_8 |
| TCELL18:OUT_F3 | SERDES.FFS_BIST_RPT_7 |
| TCELL18:OUT_F4 | SERDES.FFS_BIST_RPT_6 |
| TCELL18:OUT_F5 | SERDES.FFS_BIST_RPT_5 |
| TCELL18:OUT_Q0 | SERDES.FFS_BIST_RPT_4 |
| TCELL18:OUT_Q1 | SERDES.FFS_BIST_RPT_3 |
| TCELL18:OUT_Q2 | SERDES.FFS_BIST_RPT_2 |
| TCELL18:OUT_Q3 | SERDES.FFS_BIST_RPT_1 |
| TCELL18:OUT_Q4 | SERDES.FFS_BIST_RPT_0 |
| TCELL18:OUT_Q5 | SERDES.COUT19 |
| TCELL18:OUT_Q6 | SERDES.COUT18 |
| TCELL18:OUT_Q7 | SERDES.COUT17 |
| TCELL19:IMUX_B0 | SERDES.SCISELCH1 |
| TCELL19:IMUX_B1 | SERDES.SCIENCH1 |
| TCELL19:IMUX_LSR2 | SERDES.FFC_RRST_1 |
| TCELL19:OUT_F0 | SERDES.COUT16 |
| TCELL19:OUT_F1 | SERDES.COUT15 |
| TCELL19:OUT_F2 | SERDES.COUT14 |
| TCELL19:OUT_F3 | SERDES.COUT13 |
| TCELL19:OUT_F4 | SERDES.COUT12 |
| TCELL19:OUT_F5 | SERDES.COUT11 |
| TCELL19:OUT_Q0 | SERDES.COUT10 |
| TCELL19:OUT_Q1 | SERDES.COUT9 |
| TCELL19:OUT_Q2 | SERDES.COUT8 |
| TCELL19:OUT_Q3 | SERDES.COUT7 |
| TCELL19:OUT_Q4 | SERDES.COUT6 |
| TCELL19:OUT_Q5 | SERDES.COUT5 |
| TCELL19:OUT_Q6 | SERDES.COUT4 |
| TCELL19:OUT_Q7 | SERDES.COUT3 |
| TCELL20:IMUX_B0 | SERDES.SCISELCH0 |
| TCELL20:IMUX_B1 | SERDES.SCIENCH0 |
| TCELL20:IMUX_LSR2 | SERDES.FFC_RRST_0 |
| TCELL20:OUT_F0 | SERDES.COUT2 |
| TCELL20:OUT_F1 | SERDES.COUT1 |
| TCELL20:OUT_F2 | SERDES.COUT0 |
| TCELL20:OUT_F3 | SERDES.FFS_PLOL |
| TCELL20:OUT_F6 | SERDES.REFCK2CORE |
| TCELL21:IMUX_B0 | SERDES.FFC_RXPWDNB_1 |
| TCELL21:IMUX_B1 | SERDES.FFC_PCI_DET_EN_1 |
| TCELL21:IMUX_B2 | SERDES.FFC_SB_INV_RX_1 |
| TCELL21:IMUX_B3 | SERDES.FFC_SB_PFIFO_LP_1 |
| TCELL21:IMUX_B4 | SERDES.FFC_SIGNAL_DETECT_1 |
| TCELL21:IMUX_CLK0 | SERDES.FF_EBRD_CLK_1 |
| TCELL21:OUT_F0 | SERDES.FF_RX_D_1_23 |
| TCELL21:OUT_F2 | SERDES.FF_RX_D_1_22 |
| TCELL21:OUT_F4 | SERDES.FF_RX_D_1_21 |
| TCELL21:OUT_Q0 | SERDES.FF_RX_D_1_20 |
| TCELL21:OUT_Q1 | SERDES.FF_RX_D_1_19 |
| TCELL21:OUT_Q3 | SERDES.FF_RX_D_1_18 |
| TCELL21:OUT_Q5 | SERDES.FF_RX_D_1_17 |
| TCELL21:OUT_Q7 | SERDES.FF_RX_D_1_16 |
| TCELL22:IMUX_B1 | SERDES.FFC_EI_EN_1 |
| TCELL22:IMUX_B2 | SERDES.FFC_FB_LOOPBACK_1 |
| TCELL22:IMUX_B3 | SERDES.FFC_PCIE_CT_1 |
| TCELL22:IMUX_B4 | SERDES.FFC_PFIFO_CLR_1 |
| TCELL22:IMUX_CLK0 | SERDES.FF_RXI_CLK_1 |
| TCELL22:IMUX_LSR0 | SERDES.FFC_LANE_RX_RST_1 |
| TCELL22:OUT_F0 | SERDES.FF_RX_D_1_15 |
| TCELL22:OUT_F2 | SERDES.FF_RX_D_1_14 |
| TCELL22:OUT_F4 | SERDES.FF_RX_D_1_13 |
| TCELL22:OUT_Q0 | SERDES.FF_RX_D_1_12 |
| TCELL22:OUT_Q2 | SERDES.FF_RX_D_1_11 |
| TCELL22:OUT_Q4 | SERDES.FF_RX_D_1_10 |
| TCELL22:OUT_Q6 | SERDES.FF_RX_D_1_9 |
| TCELL22:OUT_Q7 | SERDES.FF_RX_D_1_8 |
| TCELL23:IMUX_A0 | SERDES.FFC_ENABLE_CGALIGN_1 |
| TCELL23:IMUX_A1 | SERDES.FFC_DIV11_MODE_TX_1 |
| TCELL23:IMUX_B0 | SERDES.FFC_RATE_MODE_RX_1 |
| TCELL23:IMUX_B2 | SERDES.FF_TX_D_1_22 |
| TCELL23:IMUX_B3 | SERDES.FF_TX_D_1_20 |
| TCELL23:IMUX_B4 | SERDES.FF_TX_D_1_18 |
| TCELL23:IMUX_B5 | SERDES.FF_TX_D_1_16 |
| TCELL23:IMUX_C0 | SERDES.FFC_RATE_MODE_TX_1 |
| TCELL23:IMUX_D0 | SERDES.FFC_DIV11_MODE_RX_1 |
| TCELL23:IMUX_D1 | SERDES.FF_TX_D_1_23 |
| TCELL23:IMUX_D2 | SERDES.FF_TX_D_1_21 |
| TCELL23:IMUX_D3 | SERDES.FF_TX_D_1_19 |
| TCELL23:IMUX_D4 | SERDES.FF_TX_D_1_17 |
| TCELL23:OUT_F6 | SERDES.FF_RX_F_CLK_1 |
| TCELL23:OUT_F7 | SERDES.FF_RX_H_CLK_1 |
| TCELL24:IMUX_B0 | SERDES.FF_TX_D_1_15 |
| TCELL24:IMUX_B1 | SERDES.FF_TX_D_1_13 |
| TCELL24:IMUX_B2 | SERDES.FF_TX_D_1_11 |
| TCELL24:IMUX_B3 | SERDES.FF_TX_D_1_9 |
| TCELL24:IMUX_D0 | SERDES.FF_TX_D_1_14 |
| TCELL24:IMUX_D1 | SERDES.FF_TX_D_1_12 |
| TCELL24:IMUX_D2 | SERDES.FF_TX_D_1_10 |
| TCELL24:IMUX_D3 | SERDES.FF_TX_D_1_8 |
| TCELL24:OUT_F0 | SERDES.FFS_RLOS_HI_1 |
| TCELL24:OUT_F2 | SERDES.FFS_RLOS_LO_1 |
| TCELL24:OUT_F4 | SERDES.FFS_RLOL_1 |
| TCELL24:OUT_Q1 | SERDES.FF_RX_D_1_7 |
| TCELL24:OUT_Q3 | SERDES.FF_RX_D_1_6 |
| TCELL24:OUT_Q5 | SERDES.FF_RX_D_1_5 |
| TCELL24:OUT_Q7 | SERDES.FF_RX_D_1_4 |
| TCELL25:IMUX_B0 | SERDES.FF_TX_D_1_7 |
| TCELL25:IMUX_B1 | SERDES.FF_TX_D_1_5 |
| TCELL25:IMUX_B2 | SERDES.FF_TX_D_1_3 |
| TCELL25:IMUX_B3 | SERDES.FF_TX_D_1_1 |
| TCELL25:IMUX_B4 | SERDES.LDR_CORE2TX_1 |
| TCELL25:IMUX_D0 | SERDES.FF_TX_D_1_6 |
| TCELL25:IMUX_D1 | SERDES.FF_TX_D_1_4 |
| TCELL25:IMUX_D2 | SERDES.FF_TX_D_1_2 |
| TCELL25:IMUX_D3 | SERDES.FF_TX_D_1_0 |
| TCELL25:IMUX_D4 | SERDES.FFC_LDR_CORE2TX_EN_1 |
| TCELL25:OUT_F0 | SERDES.FF_RX_D_1_3 |
| TCELL25:OUT_F1 | SERDES.FF_RX_D_1_2 |
| TCELL25:OUT_F2 | SERDES.FF_RX_D_1_1 |
| TCELL25:OUT_F3 | SERDES.FF_RX_D_1_0 |
| TCELL25:OUT_F6 | SERDES.FF_TX_F_CLK_1 |
| TCELL25:OUT_F7 | SERDES.FF_TX_H_CLK_1 |
| TCELL25:OUT_Q1 | SERDES.FFS_CC_OVERRUN_1 |
| TCELL25:OUT_Q3 | SERDES.FFS_LS_SYNC_STATUS_1 |
| TCELL25:OUT_Q5 | SERDES.LDR_RX2CORE_1 |
| TCELL25:OUT_Q7 | SERDES.FFS_CDR_TRAIN_DONE_1 |
| TCELL26:IMUX_B0 | SERDES.FFC_TXPWDNB_1 |
| TCELL26:IMUX_CLK0 | SERDES.FFC_CK_CORE_RX_1 |
| TCELL26:IMUX_CLK1 | SERDES.FF_TXI_CLK_1 |
| TCELL26:IMUX_LSR1 | SERDES.FFC_LANE_TX_RST_1 |
| TCELL26:OUT_F4 | SERDES.FFS_CC_UNDERRUN_1 |
| TCELL27:IMUX_B0 | SERDES.PCIE_POWERDOWN_1_1 |
| TCELL27:IMUX_B1 | SERDES.PCIE_POWERDOWN_1_0 |
| TCELL27:IMUX_B2 | SERDES.PCIE_RXPOLARITY_1 |
| TCELL27:IMUX_B3 | SERDES.PCIE_TXCOMPLIANCE_1 |
| TCELL27:IMUX_B4 | SERDES.PCIE_TXDETRX_PR2TLB_1 |
| TCELL27:OUT_F0 | SERDES.PCIE_RXVALID_1 |
| TCELL27:OUT_F2 | SERDES.PCIE_PHYSTATUS_1 |
| TCELL27:OUT_F4 | SERDES.FFS_SKP_ADDED_1 |
| TCELL27:OUT_Q1 | SERDES.FFS_SKP_DELETED_1 |
| TCELL28:OUT_F0 | SERDES.FFS_PCIE_CON_1 |
| TCELL28:OUT_F1 | SERDES.FFS_PCIE_DONE_1 |
| TCELL28:OUT_F2 | SERDES.FFS_TXFBFIFO_ERROR_1 |
| TCELL28:OUT_F3 | SERDES.FFS_RXFBFIFO_ERROR_1 |
| TCELL28:OUT_Q0 | SERDES.FFS_RXFBFIFO_ERROR_0 |
| TCELL28:OUT_Q1 | SERDES.FFS_TXFBFIFO_ERROR_0 |
| TCELL28:OUT_Q2 | SERDES.FFS_PCIE_DONE_0 |
| TCELL28:OUT_Q3 | SERDES.FFS_PCIE_CON_0 |
| TCELL29:IMUX_B0 | SERDES.PCIE_TXDETRX_PR2TLB_0 |
| TCELL29:IMUX_B1 | SERDES.PCIE_TXCOMPLIANCE_0 |
| TCELL29:IMUX_B2 | SERDES.PCIE_RXPOLARITY_0 |
| TCELL29:IMUX_B3 | SERDES.PCIE_POWERDOWN_0_0 |
| TCELL29:IMUX_B4 | SERDES.PCIE_POWERDOWN_0_1 |
| TCELL29:OUT_F0 | SERDES.FFS_SKP_DELETED_0 |
| TCELL29:OUT_F2 | SERDES.FFS_SKP_ADDED_0 |
| TCELL29:OUT_Q1 | SERDES.PCIE_PHYSTATUS_0 |
| TCELL29:OUT_Q3 | SERDES.PCIE_RXVALID_0 |
| TCELL30:IMUX_B3 | SERDES.FFC_TXPWDNB_0 |
| TCELL30:IMUX_CLK0 | SERDES.FF_TXI_CLK_0 |
| TCELL30:IMUX_CLK1 | SERDES.FFC_CK_CORE_RX_0 |
| TCELL30:IMUX_LSR2 | SERDES.FFC_LANE_TX_RST_0 |
| TCELL30:OUT_F3 | SERDES.FFS_CC_UNDERRUN_0 |
| TCELL31:IMUX_B0 | SERDES.LDR_CORE2TX_0 |
| TCELL31:IMUX_B1 | SERDES.FF_TX_D_0_1 |
| TCELL31:IMUX_B2 | SERDES.FF_TX_D_0_3 |
| TCELL31:IMUX_B3 | SERDES.FF_TX_D_0_5 |
| TCELL31:IMUX_B4 | SERDES.FF_TX_D_0_7 |
| TCELL31:IMUX_D0 | SERDES.FF_TX_D_0_0 |
| TCELL31:IMUX_D1 | SERDES.FF_TX_D_0_2 |
| TCELL31:IMUX_D2 | SERDES.FF_TX_D_0_4 |
| TCELL31:IMUX_D3 | SERDES.FF_TX_D_0_6 |
| TCELL31:IMUX_D4 | SERDES.FFC_LDR_CORE2TX_EN_0 |
| TCELL31:OUT_F0 | SERDES.FFS_CDR_TRAIN_DONE_0 |
| TCELL31:OUT_F1 | SERDES.LDR_RX2CORE_0 |
| TCELL31:OUT_F2 | SERDES.FFS_LS_SYNC_STATUS_0 |
| TCELL31:OUT_F3 | SERDES.FFS_CC_OVERRUN_0 |
| TCELL31:OUT_F6 | SERDES.FF_TX_H_CLK_0 |
| TCELL31:OUT_F7 | SERDES.FF_TX_F_CLK_0 |
| TCELL31:OUT_Q0 | SERDES.FF_RX_D_0_0 |
| TCELL31:OUT_Q1 | SERDES.FF_RX_D_0_1 |
| TCELL31:OUT_Q3 | SERDES.FF_RX_D_0_2 |
| TCELL31:OUT_Q4 | SERDES.FF_RX_D_0_3 |
| TCELL31:OUT_Q6 | SERDES.FF_RX_D_0_4 |
| TCELL31:OUT_Q7 | SERDES.FF_RX_D_0_5 |
| TCELL32:IMUX_B0 | SERDES.FF_TX_D_0_8 |
| TCELL32:IMUX_B1 | SERDES.FF_TX_D_0_10 |
| TCELL32:IMUX_B2 | SERDES.FF_TX_D_0_12 |
| TCELL32:IMUX_B3 | SERDES.FF_TX_D_0_14 |
| TCELL32:IMUX_D0 | SERDES.FF_TX_D_0_9 |
| TCELL32:IMUX_D1 | SERDES.FF_TX_D_0_11 |
| TCELL32:IMUX_D2 | SERDES.FF_TX_D_0_13 |
| TCELL32:IMUX_D3 | SERDES.FF_TX_D_0_15 |
| TCELL32:OUT_F0 | SERDES.FF_RX_D_0_6 |
| TCELL32:OUT_F2 | SERDES.FF_RX_D_0_7 |
| TCELL32:OUT_F4 | SERDES.FFS_RLOL_0 |
| TCELL32:OUT_Q1 | SERDES.FFS_RLOS_LO_0 |
| TCELL32:OUT_Q3 | SERDES.FFS_RLOS_HI_0 |
| TCELL33:IMUX_A5 | SERDES.FFC_RATE_MODE_RX_0 |
| TCELL33:IMUX_B0 | SERDES.FF_TX_D_0_16 |
| TCELL33:IMUX_B1 | SERDES.FF_TX_D_0_18 |
| TCELL33:IMUX_B2 | SERDES.FF_TX_D_0_20 |
| TCELL33:IMUX_B3 | SERDES.FF_TX_D_0_22 |
| TCELL33:IMUX_B4 | SERDES.FFC_DIV11_MODE_TX_0 |
| TCELL33:IMUX_B5 | SERDES.FFC_ENABLE_CGALIGN_0 |
| TCELL33:IMUX_C4 | SERDES.FFC_DIV11_MODE_RX_0 |
| TCELL33:IMUX_D0 | SERDES.FF_TX_D_0_17 |
| TCELL33:IMUX_D1 | SERDES.FF_TX_D_0_19 |
| TCELL33:IMUX_D2 | SERDES.FF_TX_D_0_21 |
| TCELL33:IMUX_D3 | SERDES.FF_TX_D_0_23 |
| TCELL33:IMUX_D4 | SERDES.FFC_RATE_MODE_TX_0 |
| TCELL33:IMUX_CLK0 | SERDES.FF_RXI_CLK_0 |
| TCELL33:OUT_F6 | SERDES.FF_RX_H_CLK_0 |
| TCELL33:OUT_F7 | SERDES.FF_RX_F_CLK_0 |
| TCELL33:OUT_Q4 | SERDES.FF_RX_D_0_8 |
| TCELL33:OUT_Q6 | SERDES.FF_RX_D_0_9 |
| TCELL34:IMUX_B0 | SERDES.FFC_PFIFO_CLR_0 |
| TCELL34:IMUX_B1 | SERDES.FFC_FB_LOOPBACK_0 |
| TCELL34:IMUX_B3 | SERDES.FFC_SIGNAL_DETECT_0 |
| TCELL34:IMUX_B4 | SERDES.FFC_SB_INV_RX_0 |
| TCELL34:IMUX_B5 | SERDES.FFC_RXPWDNB_0 |
| TCELL34:IMUX_D0 | SERDES.FFC_PCIE_CT_0 |
| TCELL34:IMUX_D1 | SERDES.FFC_EI_EN_0 |
| TCELL34:IMUX_D3 | SERDES.FFC_SB_PFIFO_LP_0 |
| TCELL34:IMUX_D4 | SERDES.FFC_PCI_DET_EN_0 |
| TCELL34:IMUX_CLK1 | SERDES.FF_EBRD_CLK_0 |
| TCELL34:IMUX_LSR1 | SERDES.FFC_LANE_RX_RST_0 |
| TCELL34:OUT_F0 | SERDES.FF_RX_D_0_10 |
| TCELL34:OUT_F1 | SERDES.FF_RX_D_0_11 |
| TCELL34:OUT_F2 | SERDES.FF_RX_D_0_12 |
| TCELL34:OUT_F3 | SERDES.FF_RX_D_0_13 |
| TCELL34:OUT_F4 | SERDES.FF_RX_D_0_14 |
| TCELL34:OUT_F5 | SERDES.FF_RX_D_0_15 |
| TCELL34:OUT_Q0 | SERDES.FF_RX_D_0_16 |
| TCELL34:OUT_Q1 | SERDES.FF_RX_D_0_17 |
| TCELL34:OUT_Q2 | SERDES.FF_RX_D_0_18 |
| TCELL34:OUT_Q3 | SERDES.FF_RX_D_0_19 |
| TCELL34:OUT_Q4 | SERDES.FF_RX_D_0_20 |
| TCELL34:OUT_Q5 | SERDES.FF_RX_D_0_21 |
| TCELL34:OUT_Q6 | SERDES.FF_RX_D_0_22 |
| TCELL34:OUT_Q7 | SERDES.FF_RX_D_0_23 |