Clock interconnect

Tile CLK_W_S

Cells: 8

Bel DLLDEL0

ecp4 CLK_W_S bel DLLDEL0
Pin	Direction	Wires
CFLAG	output	TCELL2:OUT_Q7
DIRECTION	input	TCELL2:IMUX_D6
LOADN	input	TCELL2:IMUX_B6
MOVE	input	TCELL2:IMUX_C6

Bel DLLDEL1

ecp4 CLK_W_S bel DLLDEL1
Pin	Direction	Wires
CFLAG	output	TCELL3:OUT_Q7
DIRECTION	input	TCELL3:IMUX_D6
LOADN	input	TCELL3:IMUX_B6
MOVE	input	TCELL3:IMUX_C6

Bel DLLDEL2

ecp4 CLK_W_S bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel DLLDEL3

ecp4 CLK_W_S bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel CLKDIV0

ecp4 CLK_W_S bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_A4
CDIVX	output	TCELL4:OUT_F4
RST	input	TCELL4:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_W_S bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_B4
CDIVX	output	TCELL4:OUT_F5
RST	input	TCELL4:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_W_S bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_C2
CDIVX	output	TCELL4:OUT_F6
RST	input	TCELL3:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_W_S bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_D4
CDIVX	output	TCELL4:OUT_F7
RST	input	TCELL3:IMUX_LSR1

Bel DCC0

ecp4 CLK_W_S bel DCC0
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A2

Bel DCC1

ecp4 CLK_W_S bel DCC1
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B0

Bel DCC2

ecp4 CLK_W_S bel DCC2
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C4

Bel DCC3

ecp4 CLK_W_S bel DCC3
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D5

Bel DCC4

ecp4 CLK_W_S bel DCC4
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A3

Bel DCC5

ecp4 CLK_W_S bel DCC5
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B1

Bel DCC6

ecp4 CLK_W_S bel DCC6
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C7

Bel DCC7

ecp4 CLK_W_S bel DCC7
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D3

Bel DCC8

ecp4 CLK_W_S bel DCC8
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A2

Bel DCC9

ecp4 CLK_W_S bel DCC9
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B0

Bel DCC10

ecp4 CLK_W_S bel DCC10
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C4

Bel DCC11

ecp4 CLK_W_S bel DCC11
Pin	Direction	Wires
CE	input	TCELL3:IMUX_D5

Bel DCC12

ecp4 CLK_W_S bel DCC12
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A3

Bel DCC13

ecp4 CLK_W_S bel DCC13
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B1

Bel ECLKBRIDGECS0

ecp4 CLK_W_S bel ECLKBRIDGECS0
Pin	Direction	Wires
SEL	input	TCELL4:IMUX_A6

Bel ECLKBRIDGECS1

ecp4 CLK_W_S bel ECLKBRIDGECS1
Pin	Direction	Wires
SEL	input	TCELL3:IMUX_A6

Bel BRGECLKSYNC0

ecp4 CLK_W_S bel BRGECLKSYNC0
Pin	Direction	Wires
STOP	input	TCELL4:IMUX_A7

Bel BRGECLKSYNC1

ecp4 CLK_W_S bel BRGECLKSYNC1
Pin	Direction	Wires
STOP	input	TCELL3:IMUX_A7

Bel CLK_EDGE

ecp4 CLK_W_S bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL3:IMUX_D7
INT_IN_1	input	TCELL2:IMUX_D7
INT_IN_2	input	TCELL5:IMUX_D7
INT_IN_3	input	TCELL4:IMUX_D7

Bel CLKTEST

ecp4 CLK_W_S bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_D2
TESTIN1	input	TCELL4:IMUX_D4
TESTIN2	input	TCELL3:IMUX_D0
TESTIN3	input	TCELL3:IMUX_D1

Bel ECLKSYNC0

ecp4 CLK_W_S bel ECLKSYNC0
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F0
ECLKI	input	TCELL3:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A1

Bel ECLKSYNC1

ecp4 CLK_W_S bel ECLKSYNC1
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F1
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B3

Bel ECLKSYNC2

ecp4 CLK_W_S bel ECLKSYNC2
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F2
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C1

Bel ECLKSYNC3

ecp4 CLK_W_S bel ECLKSYNC3
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F3
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D1

Bel ECLKSYNC4

ecp4 CLK_W_S bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F0
ECLKI	input	TCELL4:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A0

Bel ECLKSYNC5

ecp4 CLK_W_S bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F1
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B2

Bel ECLKSYNC6

ecp4 CLK_W_S bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F2
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C0

Bel ECLKSYNC7

ecp4 CLK_W_S bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F3
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D0

Bel CLKTEST_ECLK

ecp4 CLK_W_S bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_A4
TESTIN1	input	TCELL4:IMUX_A5
TESTIN10	input	TCELL3:IMUX_C0
TESTIN11	input	TCELL3:IMUX_C1
TESTIN2	input	TCELL4:IMUX_B4
TESTIN3	input	TCELL4:IMUX_B5
TESTIN4	input	TCELL4:IMUX_C2
TESTIN5	input	TCELL4:IMUX_C5
TESTIN6	input	TCELL3:IMUX_A0
TESTIN7	input	TCELL3:IMUX_A1
TESTIN8	input	TCELL3:IMUX_B2
TESTIN9	input	TCELL3:IMUX_B3

Bel wires

ecp4 CLK_W_S bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC3.ECLKI
TCELL2:IMUX_B6	DLLDEL0.LOADN
TCELL2:IMUX_C6	DLLDEL0.MOVE
TCELL2:IMUX_D6	DLLDEL0.DIRECTION
TCELL2:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC2.ECLKI
TCELL2:OUT_Q7	DLLDEL0.CFLAG
TCELL3:IMUX_A0	CLKTEST_ECLK.TESTIN6
TCELL3:IMUX_A1	CLKTEST_ECLK.TESTIN7
TCELL3:IMUX_A2	DCC8.CE
TCELL3:IMUX_A3	DCC12.CE
TCELL3:IMUX_A4	CLKDIV0.ALIGNWD
TCELL3:IMUX_A6	ECLKBRIDGECS1.SEL
TCELL3:IMUX_A7	BRGECLKSYNC1.STOP
TCELL3:IMUX_B0	DCC9.CE
TCELL3:IMUX_B1	DCC13.CE
TCELL3:IMUX_B2	CLKTEST_ECLK.TESTIN8
TCELL3:IMUX_B3	CLKTEST_ECLK.TESTIN9
TCELL3:IMUX_B4	CLKDIV1.ALIGNWD
TCELL3:IMUX_B6	DLLDEL1.LOADN
TCELL3:IMUX_C0	CLKTEST_ECLK.TESTIN10
TCELL3:IMUX_C1	CLKTEST_ECLK.TESTIN11
TCELL3:IMUX_C2	CLKDIV2.ALIGNWD
TCELL3:IMUX_C4	DCC10.CE
TCELL3:IMUX_C6	DLLDEL1.MOVE
TCELL3:IMUX_D0	CLKTEST.TESTIN2
TCELL3:IMUX_D1	CLKTEST.TESTIN3
TCELL3:IMUX_D4	CLKDIV3.ALIGNWD
TCELL3:IMUX_D5	DCC11.CE
TCELL3:IMUX_D6	DLLDEL1.DIRECTION
TCELL3:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL3:IMUX_LSR0	CLKDIV2.RST
TCELL3:IMUX_LSR1	CLKDIV3.RST
TCELL3:IMUX_CLK0_DELAY	ECLKSYNC0.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC1.ECLKI
TCELL3:OUT_F0	ECLKSYNC0.ECLK
TCELL3:OUT_F1	ECLKSYNC1.ECLK
TCELL3:OUT_F2	ECLKSYNC2.ECLK
TCELL3:OUT_F3	ECLKSYNC3.ECLK
TCELL3:OUT_Q7	DLLDEL1.CFLAG
TCELL4:IMUX_A0	ECLKSYNC4.STOP
TCELL4:IMUX_A1	ECLKSYNC0.STOP
TCELL4:IMUX_A2	DCC0.CE
TCELL4:IMUX_A3	DCC4.CE
TCELL4:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL4:IMUX_A5	CLKTEST_ECLK.TESTIN1
TCELL4:IMUX_A6	ECLKBRIDGECS0.SEL
TCELL4:IMUX_A7	BRGECLKSYNC0.STOP
TCELL4:IMUX_B0	DCC1.CE
TCELL4:IMUX_B1	DCC5.CE
TCELL4:IMUX_B2	ECLKSYNC5.STOP
TCELL4:IMUX_B3	ECLKSYNC1.STOP
TCELL4:IMUX_B4	CLKTEST_ECLK.TESTIN2
TCELL4:IMUX_B5	CLKTEST_ECLK.TESTIN3
TCELL4:IMUX_B6	DLLDEL2.LOADN
TCELL4:IMUX_C0	ECLKSYNC6.STOP
TCELL4:IMUX_C1	ECLKSYNC2.STOP
TCELL4:IMUX_C2	CLKTEST_ECLK.TESTIN4
TCELL4:IMUX_C4	DCC2.CE
TCELL4:IMUX_C5	CLKTEST_ECLK.TESTIN5
TCELL4:IMUX_C6	DLLDEL2.MOVE
TCELL4:IMUX_C7	DCC6.CE
TCELL4:IMUX_D0	ECLKSYNC7.STOP
TCELL4:IMUX_D1	ECLKSYNC3.STOP
TCELL4:IMUX_D2	CLKTEST.TESTIN0
TCELL4:IMUX_D3	DCC7.CE
TCELL4:IMUX_D4	CLKTEST.TESTIN1
TCELL4:IMUX_D5	DCC3.CE
TCELL4:IMUX_D6	DLLDEL2.DIRECTION
TCELL4:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL4:IMUX_LSR0	CLKDIV0.RST
TCELL4:IMUX_LSR1	CLKDIV1.RST
TCELL4:IMUX_CLK0_DELAY	ECLKSYNC4.ECLKI
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL4:OUT_F0	ECLKSYNC4.ECLK
TCELL4:OUT_F1	ECLKSYNC5.ECLK
TCELL4:OUT_F2	ECLKSYNC6.ECLK
TCELL4:OUT_F3	ECLKSYNC7.ECLK
TCELL4:OUT_F4	CLKDIV0.CDIVX
TCELL4:OUT_F5	CLKDIV1.CDIVX
TCELL4:OUT_F6	CLKDIV2.CDIVX
TCELL4:OUT_F7	CLKDIV3.CDIVX
TCELL4:OUT_Q7	DLLDEL2.CFLAG
TCELL5:IMUX_B6	DLLDEL3.LOADN
TCELL5:IMUX_C6	DLLDEL3.MOVE
TCELL5:IMUX_D6	DLLDEL3.DIRECTION
TCELL5:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC6.ECLKI
TCELL5:OUT_Q7	DLLDEL3.CFLAG
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI

Tile CLK_W_M

Cells: 10

Bel DLLDEL0

ecp4 CLK_W_M bel DLLDEL0
Pin	Direction	Wires
CFLAG	output	TCELL2:OUT_Q7
DIRECTION	input	TCELL2:IMUX_D6
LOADN	input	TCELL2:IMUX_B6
MOVE	input	TCELL2:IMUX_C6

Bel DLLDEL1

ecp4 CLK_W_M bel DLLDEL1
Pin	Direction	Wires
CFLAG	output	TCELL3:OUT_Q7
DIRECTION	input	TCELL3:IMUX_D6
LOADN	input	TCELL3:IMUX_B6
MOVE	input	TCELL3:IMUX_C6

Bel DLLDEL2

ecp4 CLK_W_M bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel DLLDEL3

ecp4 CLK_W_M bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel CLKDIV0

ecp4 CLK_W_M bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_A4
CDIVX	output	TCELL4:OUT_F4
RST	input	TCELL4:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_W_M bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_B4
CDIVX	output	TCELL4:OUT_F5
RST	input	TCELL4:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_W_M bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_C2
CDIVX	output	TCELL4:OUT_F6
RST	input	TCELL3:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_W_M bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_D4
CDIVX	output	TCELL4:OUT_F7
RST	input	TCELL3:IMUX_LSR1

Bel DCC0

ecp4 CLK_W_M bel DCC0
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A2

Bel DCC1

ecp4 CLK_W_M bel DCC1
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B0

Bel DCC2

ecp4 CLK_W_M bel DCC2
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C4

Bel DCC3

ecp4 CLK_W_M bel DCC3
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D5

Bel DCC4

ecp4 CLK_W_M bel DCC4
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A3

Bel DCC5

ecp4 CLK_W_M bel DCC5
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B1

Bel DCC6

ecp4 CLK_W_M bel DCC6
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C7

Bel DCC7

ecp4 CLK_W_M bel DCC7
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D3

Bel DCC8

ecp4 CLK_W_M bel DCC8
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A2

Bel DCC9

ecp4 CLK_W_M bel DCC9
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B0

Bel DCC10

ecp4 CLK_W_M bel DCC10
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C4

Bel DCC11

ecp4 CLK_W_M bel DCC11
Pin	Direction	Wires
CE	input	TCELL3:IMUX_D5

Bel DCC12

ecp4 CLK_W_M bel DCC12
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A3

Bel DCC13

ecp4 CLK_W_M bel DCC13
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B1

Bel ECLKBRIDGECS0

ecp4 CLK_W_M bel ECLKBRIDGECS0
Pin	Direction	Wires
SEL	input	TCELL4:IMUX_A6

Bel ECLKBRIDGECS1

ecp4 CLK_W_M bel ECLKBRIDGECS1
Pin	Direction	Wires
SEL	input	TCELL3:IMUX_A6

Bel BRGECLKSYNC0

ecp4 CLK_W_M bel BRGECLKSYNC0
Pin	Direction	Wires
STOP	input	TCELL4:IMUX_A7

Bel BRGECLKSYNC1

ecp4 CLK_W_M bel BRGECLKSYNC1
Pin	Direction	Wires
STOP	input	TCELL3:IMUX_A7

Bel CLK_EDGE

ecp4 CLK_W_M bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL3:IMUX_D7
INT_IN_1	input	TCELL2:IMUX_D7
INT_IN_2	input	TCELL5:IMUX_D7
INT_IN_3	input	TCELL4:IMUX_D7
INT_IN_4	input	TCELL8:IMUX_C5
INT_IN_5	input	TCELL9:IMUX_C5

Bel CLKTEST

ecp4 CLK_W_M bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_D2
TESTIN1	input	TCELL4:IMUX_D4
TESTIN2	input	TCELL3:IMUX_D0
TESTIN3	input	TCELL3:IMUX_D1

Bel ECLKSYNC0

ecp4 CLK_W_M bel ECLKSYNC0
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F0
ECLKI	input	TCELL3:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A1

Bel ECLKSYNC1

ecp4 CLK_W_M bel ECLKSYNC1
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F1
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B3

Bel ECLKSYNC2

ecp4 CLK_W_M bel ECLKSYNC2
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F2
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C1

Bel ECLKSYNC3

ecp4 CLK_W_M bel ECLKSYNC3
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F3
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D1

Bel ECLKSYNC4

ecp4 CLK_W_M bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F0
ECLKI	input	TCELL4:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A0

Bel ECLKSYNC5

ecp4 CLK_W_M bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F1
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B2

Bel ECLKSYNC6

ecp4 CLK_W_M bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F2
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C0

Bel ECLKSYNC7

ecp4 CLK_W_M bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F3
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D0

Bel CLKTEST_ECLK

ecp4 CLK_W_M bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_A4
TESTIN1	input	TCELL4:IMUX_A5
TESTIN10	input	TCELL3:IMUX_C0
TESTIN11	input	TCELL3:IMUX_C1
TESTIN2	input	TCELL4:IMUX_B4
TESTIN3	input	TCELL4:IMUX_B5
TESTIN4	input	TCELL4:IMUX_C2
TESTIN5	input	TCELL4:IMUX_C5
TESTIN6	input	TCELL3:IMUX_A0
TESTIN7	input	TCELL3:IMUX_A1
TESTIN8	input	TCELL3:IMUX_B2
TESTIN9	input	TCELL3:IMUX_B3

Bel wires

ecp4 CLK_W_M bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC3.ECLKI
TCELL2:IMUX_B6	DLLDEL0.LOADN
TCELL2:IMUX_C6	DLLDEL0.MOVE
TCELL2:IMUX_D6	DLLDEL0.DIRECTION
TCELL2:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC2.ECLKI
TCELL2:OUT_Q7	DLLDEL0.CFLAG
TCELL3:IMUX_A0	CLKTEST_ECLK.TESTIN6
TCELL3:IMUX_A1	CLKTEST_ECLK.TESTIN7
TCELL3:IMUX_A2	DCC8.CE
TCELL3:IMUX_A3	DCC12.CE
TCELL3:IMUX_A4	CLKDIV0.ALIGNWD
TCELL3:IMUX_A6	ECLKBRIDGECS1.SEL
TCELL3:IMUX_A7	BRGECLKSYNC1.STOP
TCELL3:IMUX_B0	DCC9.CE
TCELL3:IMUX_B1	DCC13.CE
TCELL3:IMUX_B2	CLKTEST_ECLK.TESTIN8
TCELL3:IMUX_B3	CLKTEST_ECLK.TESTIN9
TCELL3:IMUX_B4	CLKDIV1.ALIGNWD
TCELL3:IMUX_B6	DLLDEL1.LOADN
TCELL3:IMUX_C0	CLKTEST_ECLK.TESTIN10
TCELL3:IMUX_C1	CLKTEST_ECLK.TESTIN11
TCELL3:IMUX_C2	CLKDIV2.ALIGNWD
TCELL3:IMUX_C4	DCC10.CE
TCELL3:IMUX_C6	DLLDEL1.MOVE
TCELL3:IMUX_D0	CLKTEST.TESTIN2
TCELL3:IMUX_D1	CLKTEST.TESTIN3
TCELL3:IMUX_D4	CLKDIV3.ALIGNWD
TCELL3:IMUX_D5	DCC11.CE
TCELL3:IMUX_D6	DLLDEL1.DIRECTION
TCELL3:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL3:IMUX_LSR0	CLKDIV2.RST
TCELL3:IMUX_LSR1	CLKDIV3.RST
TCELL3:IMUX_CLK0_DELAY	ECLKSYNC0.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC1.ECLKI
TCELL3:OUT_F0	ECLKSYNC0.ECLK
TCELL3:OUT_F1	ECLKSYNC1.ECLK
TCELL3:OUT_F2	ECLKSYNC2.ECLK
TCELL3:OUT_F3	ECLKSYNC3.ECLK
TCELL3:OUT_Q7	DLLDEL1.CFLAG
TCELL4:IMUX_A0	ECLKSYNC4.STOP
TCELL4:IMUX_A1	ECLKSYNC0.STOP
TCELL4:IMUX_A2	DCC0.CE
TCELL4:IMUX_A3	DCC4.CE
TCELL4:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL4:IMUX_A5	CLKTEST_ECLK.TESTIN1
TCELL4:IMUX_A6	ECLKBRIDGECS0.SEL
TCELL4:IMUX_A7	BRGECLKSYNC0.STOP
TCELL4:IMUX_B0	DCC1.CE
TCELL4:IMUX_B1	DCC5.CE
TCELL4:IMUX_B2	ECLKSYNC5.STOP
TCELL4:IMUX_B3	ECLKSYNC1.STOP
TCELL4:IMUX_B4	CLKTEST_ECLK.TESTIN2
TCELL4:IMUX_B5	CLKTEST_ECLK.TESTIN3
TCELL4:IMUX_B6	DLLDEL2.LOADN
TCELL4:IMUX_C0	ECLKSYNC6.STOP
TCELL4:IMUX_C1	ECLKSYNC2.STOP
TCELL4:IMUX_C2	CLKTEST_ECLK.TESTIN4
TCELL4:IMUX_C4	DCC2.CE
TCELL4:IMUX_C5	CLKTEST_ECLK.TESTIN5
TCELL4:IMUX_C6	DLLDEL2.MOVE
TCELL4:IMUX_C7	DCC6.CE
TCELL4:IMUX_D0	ECLKSYNC7.STOP
TCELL4:IMUX_D1	ECLKSYNC3.STOP
TCELL4:IMUX_D2	CLKTEST.TESTIN0
TCELL4:IMUX_D3	DCC7.CE
TCELL4:IMUX_D4	CLKTEST.TESTIN1
TCELL4:IMUX_D5	DCC3.CE
TCELL4:IMUX_D6	DLLDEL2.DIRECTION
TCELL4:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL4:IMUX_LSR0	CLKDIV0.RST
TCELL4:IMUX_LSR1	CLKDIV1.RST
TCELL4:IMUX_CLK0_DELAY	ECLKSYNC4.ECLKI
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL4:OUT_F0	ECLKSYNC4.ECLK
TCELL4:OUT_F1	ECLKSYNC5.ECLK
TCELL4:OUT_F2	ECLKSYNC6.ECLK
TCELL4:OUT_F3	ECLKSYNC7.ECLK
TCELL4:OUT_F4	CLKDIV0.CDIVX
TCELL4:OUT_F5	CLKDIV1.CDIVX
TCELL4:OUT_F6	CLKDIV2.CDIVX
TCELL4:OUT_F7	CLKDIV3.CDIVX
TCELL4:OUT_Q7	DLLDEL2.CFLAG
TCELL5:IMUX_B6	DLLDEL3.LOADN
TCELL5:IMUX_C6	DLLDEL3.MOVE
TCELL5:IMUX_D6	DLLDEL3.DIRECTION
TCELL5:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC6.ECLKI
TCELL5:OUT_Q7	DLLDEL3.CFLAG
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI
TCELL8:IMUX_C5	CLK_EDGE.INT_IN_4
TCELL9:IMUX_C5	CLK_EDGE.INT_IN_5

Tile CLK_W_L

Cells: 12

Bel DLLDEL0

ecp4 CLK_W_L bel DLLDEL0
Pin	Direction	Wires
CFLAG	output	TCELL2:OUT_Q7
DIRECTION	input	TCELL2:IMUX_D6
LOADN	input	TCELL2:IMUX_B6
MOVE	input	TCELL2:IMUX_C6

Bel DLLDEL1

ecp4 CLK_W_L bel DLLDEL1
Pin	Direction	Wires
CFLAG	output	TCELL3:OUT_Q7
DIRECTION	input	TCELL3:IMUX_D6
LOADN	input	TCELL3:IMUX_B6
MOVE	input	TCELL3:IMUX_C6

Bel DLLDEL2

ecp4 CLK_W_L bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel DLLDEL3

ecp4 CLK_W_L bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel CLKDIV0

ecp4 CLK_W_L bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_A4
CDIVX	output	TCELL4:OUT_F4
RST	input	TCELL4:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_W_L bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_B4
CDIVX	output	TCELL4:OUT_F5
RST	input	TCELL4:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_W_L bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_C2
CDIVX	output	TCELL4:OUT_F6
RST	input	TCELL3:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_W_L bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_D4
CDIVX	output	TCELL4:OUT_F7
RST	input	TCELL3:IMUX_LSR1

Bel DCC0

ecp4 CLK_W_L bel DCC0
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A2

Bel DCC1

ecp4 CLK_W_L bel DCC1
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B0

Bel DCC2

ecp4 CLK_W_L bel DCC2
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C4

Bel DCC3

ecp4 CLK_W_L bel DCC3
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D5

Bel DCC4

ecp4 CLK_W_L bel DCC4
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A3

Bel DCC5

ecp4 CLK_W_L bel DCC5
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B1

Bel DCC6

ecp4 CLK_W_L bel DCC6
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C7

Bel DCC7

ecp4 CLK_W_L bel DCC7
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D3

Bel DCC8

ecp4 CLK_W_L bel DCC8
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A2

Bel DCC9

ecp4 CLK_W_L bel DCC9
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B0

Bel DCC10

ecp4 CLK_W_L bel DCC10
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C4

Bel DCC11

ecp4 CLK_W_L bel DCC11
Pin	Direction	Wires
CE	input	TCELL3:IMUX_D5

Bel DCC12

ecp4 CLK_W_L bel DCC12
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A3

Bel DCC13

ecp4 CLK_W_L bel DCC13
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B1

Bel ECLKBRIDGECS0

ecp4 CLK_W_L bel ECLKBRIDGECS0
Pin	Direction	Wires
SEL	input	TCELL4:IMUX_A6

Bel ECLKBRIDGECS1

ecp4 CLK_W_L bel ECLKBRIDGECS1
Pin	Direction	Wires
SEL	input	TCELL3:IMUX_A6

Bel BRGECLKSYNC0

ecp4 CLK_W_L bel BRGECLKSYNC0
Pin	Direction	Wires
STOP	input	TCELL4:IMUX_A7

Bel BRGECLKSYNC1

ecp4 CLK_W_L bel BRGECLKSYNC1
Pin	Direction	Wires
STOP	input	TCELL3:IMUX_A7

Bel CLK_EDGE

ecp4 CLK_W_L bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL3:IMUX_D7
INT_IN_1	input	TCELL2:IMUX_D7
INT_IN_2	input	TCELL5:IMUX_D7
INT_IN_3	input	TCELL4:IMUX_D7
INT_IN_4	input	TCELL8:IMUX_C5
INT_IN_5	input	TCELL10:IMUX_C5
INT_IN_6	input	TCELL9:IMUX_C5
INT_IN_7	input	TCELL11:IMUX_C5

Bel CLKTEST

ecp4 CLK_W_L bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_D2
TESTIN1	input	TCELL4:IMUX_D4
TESTIN2	input	TCELL3:IMUX_D0
TESTIN3	input	TCELL3:IMUX_D1

Bel ECLKSYNC0

ecp4 CLK_W_L bel ECLKSYNC0
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F0
ECLKI	input	TCELL3:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A1

Bel ECLKSYNC1

ecp4 CLK_W_L bel ECLKSYNC1
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F1
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B3

Bel ECLKSYNC2

ecp4 CLK_W_L bel ECLKSYNC2
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F2
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C1

Bel ECLKSYNC3

ecp4 CLK_W_L bel ECLKSYNC3
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F3
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D1

Bel ECLKSYNC4

ecp4 CLK_W_L bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F0
ECLKI	input	TCELL4:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A0

Bel ECLKSYNC5

ecp4 CLK_W_L bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F1
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B2

Bel ECLKSYNC6

ecp4 CLK_W_L bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F2
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C0

Bel ECLKSYNC7

ecp4 CLK_W_L bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F3
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D0

Bel CLKTEST_ECLK

ecp4 CLK_W_L bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_A4
TESTIN1	input	TCELL4:IMUX_A5
TESTIN10	input	TCELL3:IMUX_C0
TESTIN11	input	TCELL3:IMUX_C1
TESTIN2	input	TCELL4:IMUX_B4
TESTIN3	input	TCELL4:IMUX_B5
TESTIN4	input	TCELL4:IMUX_C2
TESTIN5	input	TCELL4:IMUX_C5
TESTIN6	input	TCELL3:IMUX_A0
TESTIN7	input	TCELL3:IMUX_A1
TESTIN8	input	TCELL3:IMUX_B2
TESTIN9	input	TCELL3:IMUX_B3

Bel wires

ecp4 CLK_W_L bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC3.ECLKI
TCELL2:IMUX_B6	DLLDEL0.LOADN
TCELL2:IMUX_C6	DLLDEL0.MOVE
TCELL2:IMUX_D6	DLLDEL0.DIRECTION
TCELL2:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC2.ECLKI
TCELL2:OUT_Q7	DLLDEL0.CFLAG
TCELL3:IMUX_A0	CLKTEST_ECLK.TESTIN6
TCELL3:IMUX_A1	CLKTEST_ECLK.TESTIN7
TCELL3:IMUX_A2	DCC8.CE
TCELL3:IMUX_A3	DCC12.CE
TCELL3:IMUX_A4	CLKDIV0.ALIGNWD
TCELL3:IMUX_A6	ECLKBRIDGECS1.SEL
TCELL3:IMUX_A7	BRGECLKSYNC1.STOP
TCELL3:IMUX_B0	DCC9.CE
TCELL3:IMUX_B1	DCC13.CE
TCELL3:IMUX_B2	CLKTEST_ECLK.TESTIN8
TCELL3:IMUX_B3	CLKTEST_ECLK.TESTIN9
TCELL3:IMUX_B4	CLKDIV1.ALIGNWD
TCELL3:IMUX_B6	DLLDEL1.LOADN
TCELL3:IMUX_C0	CLKTEST_ECLK.TESTIN10
TCELL3:IMUX_C1	CLKTEST_ECLK.TESTIN11
TCELL3:IMUX_C2	CLKDIV2.ALIGNWD
TCELL3:IMUX_C4	DCC10.CE
TCELL3:IMUX_C6	DLLDEL1.MOVE
TCELL3:IMUX_D0	CLKTEST.TESTIN2
TCELL3:IMUX_D1	CLKTEST.TESTIN3
TCELL3:IMUX_D4	CLKDIV3.ALIGNWD
TCELL3:IMUX_D5	DCC11.CE
TCELL3:IMUX_D6	DLLDEL1.DIRECTION
TCELL3:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL3:IMUX_LSR0	CLKDIV2.RST
TCELL3:IMUX_LSR1	CLKDIV3.RST
TCELL3:IMUX_CLK0_DELAY	ECLKSYNC0.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC1.ECLKI
TCELL3:OUT_F0	ECLKSYNC0.ECLK
TCELL3:OUT_F1	ECLKSYNC1.ECLK
TCELL3:OUT_F2	ECLKSYNC2.ECLK
TCELL3:OUT_F3	ECLKSYNC3.ECLK
TCELL3:OUT_Q7	DLLDEL1.CFLAG
TCELL4:IMUX_A0	ECLKSYNC4.STOP
TCELL4:IMUX_A1	ECLKSYNC0.STOP
TCELL4:IMUX_A2	DCC0.CE
TCELL4:IMUX_A3	DCC4.CE
TCELL4:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL4:IMUX_A5	CLKTEST_ECLK.TESTIN1
TCELL4:IMUX_A6	ECLKBRIDGECS0.SEL
TCELL4:IMUX_A7	BRGECLKSYNC0.STOP
TCELL4:IMUX_B0	DCC1.CE
TCELL4:IMUX_B1	DCC5.CE
TCELL4:IMUX_B2	ECLKSYNC5.STOP
TCELL4:IMUX_B3	ECLKSYNC1.STOP
TCELL4:IMUX_B4	CLKTEST_ECLK.TESTIN2
TCELL4:IMUX_B5	CLKTEST_ECLK.TESTIN3
TCELL4:IMUX_B6	DLLDEL2.LOADN
TCELL4:IMUX_C0	ECLKSYNC6.STOP
TCELL4:IMUX_C1	ECLKSYNC2.STOP
TCELL4:IMUX_C2	CLKTEST_ECLK.TESTIN4
TCELL4:IMUX_C4	DCC2.CE
TCELL4:IMUX_C5	CLKTEST_ECLK.TESTIN5
TCELL4:IMUX_C6	DLLDEL2.MOVE
TCELL4:IMUX_C7	DCC6.CE
TCELL4:IMUX_D0	ECLKSYNC7.STOP
TCELL4:IMUX_D1	ECLKSYNC3.STOP
TCELL4:IMUX_D2	CLKTEST.TESTIN0
TCELL4:IMUX_D3	DCC7.CE
TCELL4:IMUX_D4	CLKTEST.TESTIN1
TCELL4:IMUX_D5	DCC3.CE
TCELL4:IMUX_D6	DLLDEL2.DIRECTION
TCELL4:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL4:IMUX_LSR0	CLKDIV0.RST
TCELL4:IMUX_LSR1	CLKDIV1.RST
TCELL4:IMUX_CLK0_DELAY	ECLKSYNC4.ECLKI
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL4:OUT_F0	ECLKSYNC4.ECLK
TCELL4:OUT_F1	ECLKSYNC5.ECLK
TCELL4:OUT_F2	ECLKSYNC6.ECLK
TCELL4:OUT_F3	ECLKSYNC7.ECLK
TCELL4:OUT_F4	CLKDIV0.CDIVX
TCELL4:OUT_F5	CLKDIV1.CDIVX
TCELL4:OUT_F6	CLKDIV2.CDIVX
TCELL4:OUT_F7	CLKDIV3.CDIVX
TCELL4:OUT_Q7	DLLDEL2.CFLAG
TCELL5:IMUX_B6	DLLDEL3.LOADN
TCELL5:IMUX_C6	DLLDEL3.MOVE
TCELL5:IMUX_D6	DLLDEL3.DIRECTION
TCELL5:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC6.ECLKI
TCELL5:OUT_Q7	DLLDEL3.CFLAG
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI
TCELL8:IMUX_C5	CLK_EDGE.INT_IN_4
TCELL9:IMUX_C5	CLK_EDGE.INT_IN_6
TCELL10:IMUX_C5	CLK_EDGE.INT_IN_5
TCELL11:IMUX_C5	CLK_EDGE.INT_IN_7

Tile CLK_E_S

Cells: 8

Bel DLLDEL0

ecp4 CLK_E_S bel DLLDEL0
Pin	Direction	Wires
CFLAG	output	TCELL3:OUT_Q7
DIRECTION	input	TCELL3:IMUX_D6
LOADN	input	TCELL3:IMUX_B6
MOVE	input	TCELL3:IMUX_C6

Bel DLLDEL1

ecp4 CLK_E_S bel DLLDEL1
Pin	Direction	Wires
CFLAG	output	TCELL2:OUT_Q7
DIRECTION	input	TCELL2:IMUX_D6
LOADN	input	TCELL2:IMUX_B6
MOVE	input	TCELL2:IMUX_C6

Bel DLLDEL2

ecp4 CLK_E_S bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel DLLDEL3

ecp4 CLK_E_S bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel CLKDIV0

ecp4 CLK_E_S bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_A4
CDIVX	output	TCELL4:OUT_F4
RST	input	TCELL4:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_E_S bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_B4
CDIVX	output	TCELL4:OUT_F5
RST	input	TCELL4:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_E_S bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_C2
CDIVX	output	TCELL4:OUT_F6
RST	input	TCELL3:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_E_S bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_D4
CDIVX	output	TCELL4:OUT_F7
RST	input	TCELL3:IMUX_LSR1

Bel DCC0

ecp4 CLK_E_S bel DCC0
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A2

Bel DCC1

ecp4 CLK_E_S bel DCC1
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B0

Bel DCC2

ecp4 CLK_E_S bel DCC2
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C4

Bel DCC3

ecp4 CLK_E_S bel DCC3
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D5

Bel DCC4

ecp4 CLK_E_S bel DCC4
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A3

Bel DCC5

ecp4 CLK_E_S bel DCC5
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B1

Bel DCC6

ecp4 CLK_E_S bel DCC6
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C7

Bel DCC7

ecp4 CLK_E_S bel DCC7
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D3

Bel DCC8

ecp4 CLK_E_S bel DCC8
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A2

Bel DCC9

ecp4 CLK_E_S bel DCC9
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B0

Bel DCC10

ecp4 CLK_E_S bel DCC10
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C4

Bel DCC11

ecp4 CLK_E_S bel DCC11
Pin	Direction	Wires
CE	input	TCELL3:IMUX_D5

Bel DCC12

ecp4 CLK_E_S bel DCC12
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A3

Bel DCC13

ecp4 CLK_E_S bel DCC13
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B1

Bel ECLKBRIDGECS0

ecp4 CLK_E_S bel ECLKBRIDGECS0
Pin	Direction	Wires
SEL	input	TCELL4:IMUX_A6

Bel ECLKBRIDGECS1

ecp4 CLK_E_S bel ECLKBRIDGECS1
Pin	Direction	Wires
SEL	input	TCELL3:IMUX_A6

Bel BRGECLKSYNC0

ecp4 CLK_E_S bel BRGECLKSYNC0
Pin	Direction	Wires
STOP	input	TCELL4:IMUX_A7

Bel BRGECLKSYNC1

ecp4 CLK_E_S bel BRGECLKSYNC1
Pin	Direction	Wires
STOP	input	TCELL3:IMUX_A7

Bel CLK_EDGE

ecp4 CLK_E_S bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL3:IMUX_D7
INT_IN_1	input	TCELL2:IMUX_D7
INT_IN_2	input	TCELL5:IMUX_D7
INT_IN_3	input	TCELL4:IMUX_D7

Bel CLKTEST

ecp4 CLK_E_S bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_D2
TESTIN1	input	TCELL4:IMUX_D4
TESTIN2	input	TCELL3:IMUX_D0
TESTIN3	input	TCELL3:IMUX_D1

Bel ECLKSYNC0

ecp4 CLK_E_S bel ECLKSYNC0
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F0
ECLKI	input	TCELL3:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A1

Bel ECLKSYNC1

ecp4 CLK_E_S bel ECLKSYNC1
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F1
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B3

Bel ECLKSYNC2

ecp4 CLK_E_S bel ECLKSYNC2
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F2
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C1

Bel ECLKSYNC3

ecp4 CLK_E_S bel ECLKSYNC3
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F3
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D1

Bel ECLKSYNC4

ecp4 CLK_E_S bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F0
ECLKI	input	TCELL4:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A0

Bel ECLKSYNC5

ecp4 CLK_E_S bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F1
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B2

Bel ECLKSYNC6

ecp4 CLK_E_S bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F2
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C0

Bel ECLKSYNC7

ecp4 CLK_E_S bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F3
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D0

Bel CLKTEST_ECLK

ecp4 CLK_E_S bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_A4
TESTIN1	input	TCELL4:IMUX_A5
TESTIN10	input	TCELL3:IMUX_C0
TESTIN11	input	TCELL3:IMUX_C1
TESTIN2	input	TCELL4:IMUX_B4
TESTIN3	input	TCELL4:IMUX_B5
TESTIN4	input	TCELL4:IMUX_C2
TESTIN5	input	TCELL4:IMUX_C5
TESTIN6	input	TCELL3:IMUX_A0
TESTIN7	input	TCELL3:IMUX_A1
TESTIN8	input	TCELL3:IMUX_B2
TESTIN9	input	TCELL3:IMUX_B3

Bel wires

ecp4 CLK_E_S bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC3.ECLKI
TCELL2:IMUX_B6	DLLDEL1.LOADN
TCELL2:IMUX_C6	DLLDEL1.MOVE
TCELL2:IMUX_D6	DLLDEL1.DIRECTION
TCELL2:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC2.ECLKI
TCELL2:OUT_Q7	DLLDEL1.CFLAG
TCELL3:IMUX_A0	CLKTEST_ECLK.TESTIN6
TCELL3:IMUX_A1	CLKTEST_ECLK.TESTIN7
TCELL3:IMUX_A2	DCC8.CE
TCELL3:IMUX_A3	DCC12.CE
TCELL3:IMUX_A4	CLKDIV0.ALIGNWD
TCELL3:IMUX_A6	ECLKBRIDGECS1.SEL
TCELL3:IMUX_A7	BRGECLKSYNC1.STOP
TCELL3:IMUX_B0	DCC9.CE
TCELL3:IMUX_B1	DCC13.CE
TCELL3:IMUX_B2	CLKTEST_ECLK.TESTIN8
TCELL3:IMUX_B3	CLKTEST_ECLK.TESTIN9
TCELL3:IMUX_B4	CLKDIV1.ALIGNWD
TCELL3:IMUX_B6	DLLDEL0.LOADN
TCELL3:IMUX_C0	CLKTEST_ECLK.TESTIN10
TCELL3:IMUX_C1	CLKTEST_ECLK.TESTIN11
TCELL3:IMUX_C2	CLKDIV2.ALIGNWD
TCELL3:IMUX_C4	DCC10.CE
TCELL3:IMUX_C6	DLLDEL0.MOVE
TCELL3:IMUX_D0	CLKTEST.TESTIN2
TCELL3:IMUX_D1	CLKTEST.TESTIN3
TCELL3:IMUX_D4	CLKDIV3.ALIGNWD
TCELL3:IMUX_D5	DCC11.CE
TCELL3:IMUX_D6	DLLDEL0.DIRECTION
TCELL3:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL3:IMUX_LSR0	CLKDIV2.RST
TCELL3:IMUX_LSR1	CLKDIV3.RST
TCELL3:IMUX_CLK0_DELAY	ECLKSYNC0.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC1.ECLKI
TCELL3:OUT_F0	ECLKSYNC0.ECLK
TCELL3:OUT_F1	ECLKSYNC1.ECLK
TCELL3:OUT_F2	ECLKSYNC2.ECLK
TCELL3:OUT_F3	ECLKSYNC3.ECLK
TCELL3:OUT_Q7	DLLDEL0.CFLAG
TCELL4:IMUX_A0	ECLKSYNC4.STOP
TCELL4:IMUX_A1	ECLKSYNC0.STOP
TCELL4:IMUX_A2	DCC0.CE
TCELL4:IMUX_A3	DCC4.CE
TCELL4:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL4:IMUX_A5	CLKTEST_ECLK.TESTIN1
TCELL4:IMUX_A6	ECLKBRIDGECS0.SEL
TCELL4:IMUX_A7	BRGECLKSYNC0.STOP
TCELL4:IMUX_B0	DCC1.CE
TCELL4:IMUX_B1	DCC5.CE
TCELL4:IMUX_B2	ECLKSYNC5.STOP
TCELL4:IMUX_B3	ECLKSYNC1.STOP
TCELL4:IMUX_B4	CLKTEST_ECLK.TESTIN2
TCELL4:IMUX_B5	CLKTEST_ECLK.TESTIN3
TCELL4:IMUX_B6	DLLDEL3.LOADN
TCELL4:IMUX_C0	ECLKSYNC6.STOP
TCELL4:IMUX_C1	ECLKSYNC2.STOP
TCELL4:IMUX_C2	CLKTEST_ECLK.TESTIN4
TCELL4:IMUX_C4	DCC2.CE
TCELL4:IMUX_C5	CLKTEST_ECLK.TESTIN5
TCELL4:IMUX_C6	DLLDEL3.MOVE
TCELL4:IMUX_C7	DCC6.CE
TCELL4:IMUX_D0	ECLKSYNC7.STOP
TCELL4:IMUX_D1	ECLKSYNC3.STOP
TCELL4:IMUX_D2	CLKTEST.TESTIN0
TCELL4:IMUX_D3	DCC7.CE
TCELL4:IMUX_D4	CLKTEST.TESTIN1
TCELL4:IMUX_D5	DCC3.CE
TCELL4:IMUX_D6	DLLDEL3.DIRECTION
TCELL4:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL4:IMUX_LSR0	CLKDIV0.RST
TCELL4:IMUX_LSR1	CLKDIV1.RST
TCELL4:IMUX_CLK0_DELAY	ECLKSYNC4.ECLKI
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL4:OUT_F0	ECLKSYNC4.ECLK
TCELL4:OUT_F1	ECLKSYNC5.ECLK
TCELL4:OUT_F2	ECLKSYNC6.ECLK
TCELL4:OUT_F3	ECLKSYNC7.ECLK
TCELL4:OUT_F4	CLKDIV0.CDIVX
TCELL4:OUT_F5	CLKDIV1.CDIVX
TCELL4:OUT_F6	CLKDIV2.CDIVX
TCELL4:OUT_F7	CLKDIV3.CDIVX
TCELL4:OUT_Q7	DLLDEL3.CFLAG
TCELL5:IMUX_B6	DLLDEL2.LOADN
TCELL5:IMUX_C6	DLLDEL2.MOVE
TCELL5:IMUX_D6	DLLDEL2.DIRECTION
TCELL5:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC6.ECLKI
TCELL5:OUT_Q7	DLLDEL2.CFLAG
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI

Tile CLK_E_M

Cells: 10

Bel DLLDEL0

ecp4 CLK_E_M bel DLLDEL0
Pin	Direction	Wires
CFLAG	output	TCELL3:OUT_Q7
DIRECTION	input	TCELL3:IMUX_D6
LOADN	input	TCELL3:IMUX_B6
MOVE	input	TCELL3:IMUX_C6

Bel DLLDEL1

ecp4 CLK_E_M bel DLLDEL1
Pin	Direction	Wires
CFLAG	output	TCELL2:OUT_Q7
DIRECTION	input	TCELL2:IMUX_D6
LOADN	input	TCELL2:IMUX_B6
MOVE	input	TCELL2:IMUX_C6

Bel DLLDEL2

ecp4 CLK_E_M bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel DLLDEL3

ecp4 CLK_E_M bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel CLKDIV0

ecp4 CLK_E_M bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_A4
CDIVX	output	TCELL4:OUT_F4
RST	input	TCELL4:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_E_M bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_B4
CDIVX	output	TCELL4:OUT_F5
RST	input	TCELL4:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_E_M bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_C2
CDIVX	output	TCELL4:OUT_F6
RST	input	TCELL3:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_E_M bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_D4
CDIVX	output	TCELL4:OUT_F7
RST	input	TCELL3:IMUX_LSR1

Bel DCC0

ecp4 CLK_E_M bel DCC0
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A2

Bel DCC1

ecp4 CLK_E_M bel DCC1
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B0

Bel DCC2

ecp4 CLK_E_M bel DCC2
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C4

Bel DCC3

ecp4 CLK_E_M bel DCC3
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D5

Bel DCC4

ecp4 CLK_E_M bel DCC4
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A3

Bel DCC5

ecp4 CLK_E_M bel DCC5
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B1

Bel DCC6

ecp4 CLK_E_M bel DCC6
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C7

Bel DCC7

ecp4 CLK_E_M bel DCC7
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D3

Bel DCC8

ecp4 CLK_E_M bel DCC8
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A2

Bel DCC9

ecp4 CLK_E_M bel DCC9
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B0

Bel DCC10

ecp4 CLK_E_M bel DCC10
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C4

Bel DCC11

ecp4 CLK_E_M bel DCC11
Pin	Direction	Wires
CE	input	TCELL3:IMUX_D5

Bel DCC12

ecp4 CLK_E_M bel DCC12
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A3

Bel DCC13

ecp4 CLK_E_M bel DCC13
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B1

Bel ECLKBRIDGECS0

ecp4 CLK_E_M bel ECLKBRIDGECS0
Pin	Direction	Wires
SEL	input	TCELL4:IMUX_A6

Bel ECLKBRIDGECS1

ecp4 CLK_E_M bel ECLKBRIDGECS1
Pin	Direction	Wires
SEL	input	TCELL3:IMUX_A6

Bel BRGECLKSYNC0

ecp4 CLK_E_M bel BRGECLKSYNC0
Pin	Direction	Wires
STOP	input	TCELL4:IMUX_A7

Bel BRGECLKSYNC1

ecp4 CLK_E_M bel BRGECLKSYNC1
Pin	Direction	Wires
STOP	input	TCELL3:IMUX_A7

Bel CLK_EDGE

ecp4 CLK_E_M bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL3:IMUX_D7
INT_IN_1	input	TCELL2:IMUX_D7
INT_IN_2	input	TCELL5:IMUX_D7
INT_IN_3	input	TCELL4:IMUX_D7
INT_IN_4	input	TCELL8:IMUX_C5
INT_IN_5	input	TCELL9:IMUX_C5

Bel CLKTEST

ecp4 CLK_E_M bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_D2
TESTIN1	input	TCELL4:IMUX_D4
TESTIN2	input	TCELL3:IMUX_D0
TESTIN3	input	TCELL3:IMUX_D1

Bel ECLKSYNC0

ecp4 CLK_E_M bel ECLKSYNC0
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F0
ECLKI	input	TCELL3:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A1

Bel ECLKSYNC1

ecp4 CLK_E_M bel ECLKSYNC1
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F1
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B3

Bel ECLKSYNC2

ecp4 CLK_E_M bel ECLKSYNC2
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F2
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C1

Bel ECLKSYNC3

ecp4 CLK_E_M bel ECLKSYNC3
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F3
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D1

Bel ECLKSYNC4

ecp4 CLK_E_M bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F0
ECLKI	input	TCELL4:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A0

Bel ECLKSYNC5

ecp4 CLK_E_M bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F1
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B2

Bel ECLKSYNC6

ecp4 CLK_E_M bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F2
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C0

Bel ECLKSYNC7

ecp4 CLK_E_M bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F3
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D0

Bel CLKTEST_ECLK

ecp4 CLK_E_M bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_A4
TESTIN1	input	TCELL4:IMUX_A5
TESTIN10	input	TCELL3:IMUX_C0
TESTIN11	input	TCELL3:IMUX_C1
TESTIN2	input	TCELL4:IMUX_B4
TESTIN3	input	TCELL4:IMUX_B5
TESTIN4	input	TCELL4:IMUX_C2
TESTIN5	input	TCELL4:IMUX_C5
TESTIN6	input	TCELL3:IMUX_A0
TESTIN7	input	TCELL3:IMUX_A1
TESTIN8	input	TCELL3:IMUX_B2
TESTIN9	input	TCELL3:IMUX_B3

Bel wires

ecp4 CLK_E_M bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC3.ECLKI
TCELL2:IMUX_B6	DLLDEL1.LOADN
TCELL2:IMUX_C6	DLLDEL1.MOVE
TCELL2:IMUX_D6	DLLDEL1.DIRECTION
TCELL2:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC2.ECLKI
TCELL2:OUT_Q7	DLLDEL1.CFLAG
TCELL3:IMUX_A0	CLKTEST_ECLK.TESTIN6
TCELL3:IMUX_A1	CLKTEST_ECLK.TESTIN7
TCELL3:IMUX_A2	DCC8.CE
TCELL3:IMUX_A3	DCC12.CE
TCELL3:IMUX_A4	CLKDIV0.ALIGNWD
TCELL3:IMUX_A6	ECLKBRIDGECS1.SEL
TCELL3:IMUX_A7	BRGECLKSYNC1.STOP
TCELL3:IMUX_B0	DCC9.CE
TCELL3:IMUX_B1	DCC13.CE
TCELL3:IMUX_B2	CLKTEST_ECLK.TESTIN8
TCELL3:IMUX_B3	CLKTEST_ECLK.TESTIN9
TCELL3:IMUX_B4	CLKDIV1.ALIGNWD
TCELL3:IMUX_B6	DLLDEL0.LOADN
TCELL3:IMUX_C0	CLKTEST_ECLK.TESTIN10
TCELL3:IMUX_C1	CLKTEST_ECLK.TESTIN11
TCELL3:IMUX_C2	CLKDIV2.ALIGNWD
TCELL3:IMUX_C4	DCC10.CE
TCELL3:IMUX_C6	DLLDEL0.MOVE
TCELL3:IMUX_D0	CLKTEST.TESTIN2
TCELL3:IMUX_D1	CLKTEST.TESTIN3
TCELL3:IMUX_D4	CLKDIV3.ALIGNWD
TCELL3:IMUX_D5	DCC11.CE
TCELL3:IMUX_D6	DLLDEL0.DIRECTION
TCELL3:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL3:IMUX_LSR0	CLKDIV2.RST
TCELL3:IMUX_LSR1	CLKDIV3.RST
TCELL3:IMUX_CLK0_DELAY	ECLKSYNC0.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC1.ECLKI
TCELL3:OUT_F0	ECLKSYNC0.ECLK
TCELL3:OUT_F1	ECLKSYNC1.ECLK
TCELL3:OUT_F2	ECLKSYNC2.ECLK
TCELL3:OUT_F3	ECLKSYNC3.ECLK
TCELL3:OUT_Q7	DLLDEL0.CFLAG
TCELL4:IMUX_A0	ECLKSYNC4.STOP
TCELL4:IMUX_A1	ECLKSYNC0.STOP
TCELL4:IMUX_A2	DCC0.CE
TCELL4:IMUX_A3	DCC4.CE
TCELL4:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL4:IMUX_A5	CLKTEST_ECLK.TESTIN1
TCELL4:IMUX_A6	ECLKBRIDGECS0.SEL
TCELL4:IMUX_A7	BRGECLKSYNC0.STOP
TCELL4:IMUX_B0	DCC1.CE
TCELL4:IMUX_B1	DCC5.CE
TCELL4:IMUX_B2	ECLKSYNC5.STOP
TCELL4:IMUX_B3	ECLKSYNC1.STOP
TCELL4:IMUX_B4	CLKTEST_ECLK.TESTIN2
TCELL4:IMUX_B5	CLKTEST_ECLK.TESTIN3
TCELL4:IMUX_B6	DLLDEL3.LOADN
TCELL4:IMUX_C0	ECLKSYNC6.STOP
TCELL4:IMUX_C1	ECLKSYNC2.STOP
TCELL4:IMUX_C2	CLKTEST_ECLK.TESTIN4
TCELL4:IMUX_C4	DCC2.CE
TCELL4:IMUX_C5	CLKTEST_ECLK.TESTIN5
TCELL4:IMUX_C6	DLLDEL3.MOVE
TCELL4:IMUX_C7	DCC6.CE
TCELL4:IMUX_D0	ECLKSYNC7.STOP
TCELL4:IMUX_D1	ECLKSYNC3.STOP
TCELL4:IMUX_D2	CLKTEST.TESTIN0
TCELL4:IMUX_D3	DCC7.CE
TCELL4:IMUX_D4	CLKTEST.TESTIN1
TCELL4:IMUX_D5	DCC3.CE
TCELL4:IMUX_D6	DLLDEL3.DIRECTION
TCELL4:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL4:IMUX_LSR0	CLKDIV0.RST
TCELL4:IMUX_LSR1	CLKDIV1.RST
TCELL4:IMUX_CLK0_DELAY	ECLKSYNC4.ECLKI
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL4:OUT_F0	ECLKSYNC4.ECLK
TCELL4:OUT_F1	ECLKSYNC5.ECLK
TCELL4:OUT_F2	ECLKSYNC6.ECLK
TCELL4:OUT_F3	ECLKSYNC7.ECLK
TCELL4:OUT_F4	CLKDIV0.CDIVX
TCELL4:OUT_F5	CLKDIV1.CDIVX
TCELL4:OUT_F6	CLKDIV2.CDIVX
TCELL4:OUT_F7	CLKDIV3.CDIVX
TCELL4:OUT_Q7	DLLDEL3.CFLAG
TCELL5:IMUX_B6	DLLDEL2.LOADN
TCELL5:IMUX_C6	DLLDEL2.MOVE
TCELL5:IMUX_D6	DLLDEL2.DIRECTION
TCELL5:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC6.ECLKI
TCELL5:OUT_Q7	DLLDEL2.CFLAG
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI
TCELL8:IMUX_C5	CLK_EDGE.INT_IN_4
TCELL9:IMUX_C5	CLK_EDGE.INT_IN_5

Tile CLK_E_L

Cells: 12

Bel DLLDEL0

ecp4 CLK_E_L bel DLLDEL0
Pin	Direction	Wires
CFLAG	output	TCELL3:OUT_Q7
DIRECTION	input	TCELL3:IMUX_D6
LOADN	input	TCELL3:IMUX_B6
MOVE	input	TCELL3:IMUX_C6

Bel DLLDEL1

ecp4 CLK_E_L bel DLLDEL1
Pin	Direction	Wires
CFLAG	output	TCELL2:OUT_Q7
DIRECTION	input	TCELL2:IMUX_D6
LOADN	input	TCELL2:IMUX_B6
MOVE	input	TCELL2:IMUX_C6

Bel DLLDEL2

ecp4 CLK_E_L bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel DLLDEL3

ecp4 CLK_E_L bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel CLKDIV0

ecp4 CLK_E_L bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_A4
CDIVX	output	TCELL4:OUT_F4
RST	input	TCELL4:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_E_L bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_B4
CDIVX	output	TCELL4:OUT_F5
RST	input	TCELL4:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_E_L bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_C2
CDIVX	output	TCELL4:OUT_F6
RST	input	TCELL3:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_E_L bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL3:IMUX_D4
CDIVX	output	TCELL4:OUT_F7
RST	input	TCELL3:IMUX_LSR1

Bel DCC0

ecp4 CLK_E_L bel DCC0
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A2

Bel DCC1

ecp4 CLK_E_L bel DCC1
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B0

Bel DCC2

ecp4 CLK_E_L bel DCC2
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C4

Bel DCC3

ecp4 CLK_E_L bel DCC3
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D5

Bel DCC4

ecp4 CLK_E_L bel DCC4
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A3

Bel DCC5

ecp4 CLK_E_L bel DCC5
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B1

Bel DCC6

ecp4 CLK_E_L bel DCC6
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C7

Bel DCC7

ecp4 CLK_E_L bel DCC7
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D3

Bel DCC8

ecp4 CLK_E_L bel DCC8
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A2

Bel DCC9

ecp4 CLK_E_L bel DCC9
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B0

Bel DCC10

ecp4 CLK_E_L bel DCC10
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C4

Bel DCC11

ecp4 CLK_E_L bel DCC11
Pin	Direction	Wires
CE	input	TCELL3:IMUX_D5

Bel DCC12

ecp4 CLK_E_L bel DCC12
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A3

Bel DCC13

ecp4 CLK_E_L bel DCC13
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B1

Bel ECLKBRIDGECS0

ecp4 CLK_E_L bel ECLKBRIDGECS0
Pin	Direction	Wires
SEL	input	TCELL4:IMUX_A6

Bel ECLKBRIDGECS1

ecp4 CLK_E_L bel ECLKBRIDGECS1
Pin	Direction	Wires
SEL	input	TCELL3:IMUX_A6

Bel BRGECLKSYNC0

ecp4 CLK_E_L bel BRGECLKSYNC0
Pin	Direction	Wires
STOP	input	TCELL4:IMUX_A7

Bel BRGECLKSYNC1

ecp4 CLK_E_L bel BRGECLKSYNC1
Pin	Direction	Wires
STOP	input	TCELL3:IMUX_A7

Bel CLK_EDGE

ecp4 CLK_E_L bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL3:IMUX_D7
INT_IN_1	input	TCELL2:IMUX_D7
INT_IN_2	input	TCELL5:IMUX_D7
INT_IN_3	input	TCELL4:IMUX_D7
INT_IN_4	input	TCELL8:IMUX_C5
INT_IN_5	input	TCELL10:IMUX_C5
INT_IN_6	input	TCELL9:IMUX_C5
INT_IN_7	input	TCELL11:IMUX_C5

Bel CLKTEST

ecp4 CLK_E_L bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_D2
TESTIN1	input	TCELL4:IMUX_D4
TESTIN2	input	TCELL3:IMUX_D0
TESTIN3	input	TCELL3:IMUX_D1

Bel ECLKSYNC0

ecp4 CLK_E_L bel ECLKSYNC0
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F0
ECLKI	input	TCELL3:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A1

Bel ECLKSYNC1

ecp4 CLK_E_L bel ECLKSYNC1
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F1
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B3

Bel ECLKSYNC2

ecp4 CLK_E_L bel ECLKSYNC2
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F2
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C1

Bel ECLKSYNC3

ecp4 CLK_E_L bel ECLKSYNC3
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F3
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D1

Bel ECLKSYNC4

ecp4 CLK_E_L bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F0
ECLKI	input	TCELL4:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A0

Bel ECLKSYNC5

ecp4 CLK_E_L bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F1
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B2

Bel ECLKSYNC6

ecp4 CLK_E_L bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F2
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C0

Bel ECLKSYNC7

ecp4 CLK_E_L bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F3
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D0

Bel CLKTEST_ECLK

ecp4 CLK_E_L bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL4:IMUX_A4
TESTIN1	input	TCELL4:IMUX_A5
TESTIN10	input	TCELL3:IMUX_C0
TESTIN11	input	TCELL3:IMUX_C1
TESTIN2	input	TCELL4:IMUX_B4
TESTIN3	input	TCELL4:IMUX_B5
TESTIN4	input	TCELL4:IMUX_C2
TESTIN5	input	TCELL4:IMUX_C5
TESTIN6	input	TCELL3:IMUX_A0
TESTIN7	input	TCELL3:IMUX_A1
TESTIN8	input	TCELL3:IMUX_B2
TESTIN9	input	TCELL3:IMUX_B3

Bel wires

ecp4 CLK_E_L bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC3.ECLKI
TCELL2:IMUX_B6	DLLDEL1.LOADN
TCELL2:IMUX_C6	DLLDEL1.MOVE
TCELL2:IMUX_D6	DLLDEL1.DIRECTION
TCELL2:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC2.ECLKI
TCELL2:OUT_Q7	DLLDEL1.CFLAG
TCELL3:IMUX_A0	CLKTEST_ECLK.TESTIN6
TCELL3:IMUX_A1	CLKTEST_ECLK.TESTIN7
TCELL3:IMUX_A2	DCC8.CE
TCELL3:IMUX_A3	DCC12.CE
TCELL3:IMUX_A4	CLKDIV0.ALIGNWD
TCELL3:IMUX_A6	ECLKBRIDGECS1.SEL
TCELL3:IMUX_A7	BRGECLKSYNC1.STOP
TCELL3:IMUX_B0	DCC9.CE
TCELL3:IMUX_B1	DCC13.CE
TCELL3:IMUX_B2	CLKTEST_ECLK.TESTIN8
TCELL3:IMUX_B3	CLKTEST_ECLK.TESTIN9
TCELL3:IMUX_B4	CLKDIV1.ALIGNWD
TCELL3:IMUX_B6	DLLDEL0.LOADN
TCELL3:IMUX_C0	CLKTEST_ECLK.TESTIN10
TCELL3:IMUX_C1	CLKTEST_ECLK.TESTIN11
TCELL3:IMUX_C2	CLKDIV2.ALIGNWD
TCELL3:IMUX_C4	DCC10.CE
TCELL3:IMUX_C6	DLLDEL0.MOVE
TCELL3:IMUX_D0	CLKTEST.TESTIN2
TCELL3:IMUX_D1	CLKTEST.TESTIN3
TCELL3:IMUX_D4	CLKDIV3.ALIGNWD
TCELL3:IMUX_D5	DCC11.CE
TCELL3:IMUX_D6	DLLDEL0.DIRECTION
TCELL3:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL3:IMUX_LSR0	CLKDIV2.RST
TCELL3:IMUX_LSR1	CLKDIV3.RST
TCELL3:IMUX_CLK0_DELAY	ECLKSYNC0.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC1.ECLKI
TCELL3:OUT_F0	ECLKSYNC0.ECLK
TCELL3:OUT_F1	ECLKSYNC1.ECLK
TCELL3:OUT_F2	ECLKSYNC2.ECLK
TCELL3:OUT_F3	ECLKSYNC3.ECLK
TCELL3:OUT_Q7	DLLDEL0.CFLAG
TCELL4:IMUX_A0	ECLKSYNC4.STOP
TCELL4:IMUX_A1	ECLKSYNC0.STOP
TCELL4:IMUX_A2	DCC0.CE
TCELL4:IMUX_A3	DCC4.CE
TCELL4:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL4:IMUX_A5	CLKTEST_ECLK.TESTIN1
TCELL4:IMUX_A6	ECLKBRIDGECS0.SEL
TCELL4:IMUX_A7	BRGECLKSYNC0.STOP
TCELL4:IMUX_B0	DCC1.CE
TCELL4:IMUX_B1	DCC5.CE
TCELL4:IMUX_B2	ECLKSYNC5.STOP
TCELL4:IMUX_B3	ECLKSYNC1.STOP
TCELL4:IMUX_B4	CLKTEST_ECLK.TESTIN2
TCELL4:IMUX_B5	CLKTEST_ECLK.TESTIN3
TCELL4:IMUX_B6	DLLDEL3.LOADN
TCELL4:IMUX_C0	ECLKSYNC6.STOP
TCELL4:IMUX_C1	ECLKSYNC2.STOP
TCELL4:IMUX_C2	CLKTEST_ECLK.TESTIN4
TCELL4:IMUX_C4	DCC2.CE
TCELL4:IMUX_C5	CLKTEST_ECLK.TESTIN5
TCELL4:IMUX_C6	DLLDEL3.MOVE
TCELL4:IMUX_C7	DCC6.CE
TCELL4:IMUX_D0	ECLKSYNC7.STOP
TCELL4:IMUX_D1	ECLKSYNC3.STOP
TCELL4:IMUX_D2	CLKTEST.TESTIN0
TCELL4:IMUX_D3	DCC7.CE
TCELL4:IMUX_D4	CLKTEST.TESTIN1
TCELL4:IMUX_D5	DCC3.CE
TCELL4:IMUX_D6	DLLDEL3.DIRECTION
TCELL4:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL4:IMUX_LSR0	CLKDIV0.RST
TCELL4:IMUX_LSR1	CLKDIV1.RST
TCELL4:IMUX_CLK0_DELAY	ECLKSYNC4.ECLKI
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL4:OUT_F0	ECLKSYNC4.ECLK
TCELL4:OUT_F1	ECLKSYNC5.ECLK
TCELL4:OUT_F2	ECLKSYNC6.ECLK
TCELL4:OUT_F3	ECLKSYNC7.ECLK
TCELL4:OUT_F4	CLKDIV0.CDIVX
TCELL4:OUT_F5	CLKDIV1.CDIVX
TCELL4:OUT_F6	CLKDIV2.CDIVX
TCELL4:OUT_F7	CLKDIV3.CDIVX
TCELL4:OUT_Q7	DLLDEL3.CFLAG
TCELL5:IMUX_B6	DLLDEL2.LOADN
TCELL5:IMUX_C6	DLLDEL2.MOVE
TCELL5:IMUX_D6	DLLDEL2.DIRECTION
TCELL5:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC6.ECLKI
TCELL5:OUT_Q7	DLLDEL2.CFLAG
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI
TCELL8:IMUX_C5	CLK_EDGE.INT_IN_4
TCELL9:IMUX_C5	CLK_EDGE.INT_IN_6
TCELL10:IMUX_C5	CLK_EDGE.INT_IN_5
TCELL11:IMUX_C5	CLK_EDGE.INT_IN_7

Tile CLK_S_S

Cells: 2

Bel PCSCLKDIV0

ecp4 CLK_S_S bel PCSCLKDIV0
Pin	Direction	Wires
CLKI	input	TCELL0:IMUX_CLK0_DELAY
RST	input	TCELL0:IMUX_LSR0
SEL0	input	TCELL0:IMUX_A4
SEL1	input	TCELL0:IMUX_A5
SEL2	input	TCELL0:IMUX_A6

Bel DCC0

ecp4 CLK_S_S bel DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C0

Bel DCC1

ecp4 CLK_S_S bel DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C1

Bel DCC2

ecp4 CLK_S_S bel DCC2
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C2

Bel DCC3

ecp4 CLK_S_S bel DCC3
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C3

Bel DCC4

ecp4 CLK_S_S bel DCC4
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C4

Bel DCC5

ecp4 CLK_S_S bel DCC5
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C5

Bel DCC6

ecp4 CLK_S_S bel DCC6
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C6

Bel DCC7

ecp4 CLK_S_S bel DCC7
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C7

Bel DCC8

ecp4 CLK_S_S bel DCC8
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C0

Bel DCC9

ecp4 CLK_S_S bel DCC9
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C1

Bel DCC10

ecp4 CLK_S_S bel DCC10
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C2

Bel DCC11

ecp4 CLK_S_S bel DCC11
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C3

Bel DCC12

ecp4 CLK_S_S bel DCC12
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C4

Bel DCC13

ecp4 CLK_S_S bel DCC13
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C5

Bel DCC14

ecp4 CLK_S_S bel DCC14
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C6

Bel DCC15

ecp4 CLK_S_S bel DCC15
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C7

Bel CLK_EDGE

ecp4 CLK_S_S bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL0:IMUX_D6
INT_IN_1	input	TCELL0:IMUX_D7
INT_IN_2	input	TCELL1:IMUX_D6
INT_IN_3	input	TCELL1:IMUX_D7

Bel CLKTEST

ecp4 CLK_S_S bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL0:IMUX_A0
TESTIN1	input	TCELL0:IMUX_A1
TESTIN2	input	TCELL0:IMUX_A2
TESTIN3	input	TCELL0:IMUX_A3

Bel wires

ecp4 CLK_S_S bel wires
Wire	Pins
TCELL0:IMUX_A0	CLKTEST.TESTIN0
TCELL0:IMUX_A1	CLKTEST.TESTIN1
TCELL0:IMUX_A2	CLKTEST.TESTIN2
TCELL0:IMUX_A3	CLKTEST.TESTIN3
TCELL0:IMUX_A4	PCSCLKDIV0.SEL0
TCELL0:IMUX_A5	PCSCLKDIV0.SEL1
TCELL0:IMUX_A6	PCSCLKDIV0.SEL2
TCELL0:IMUX_C0	DCC0.CE
TCELL0:IMUX_C1	DCC1.CE
TCELL0:IMUX_C2	DCC2.CE
TCELL0:IMUX_C3	DCC3.CE
TCELL0:IMUX_C4	DCC4.CE
TCELL0:IMUX_C5	DCC5.CE
TCELL0:IMUX_C6	DCC6.CE
TCELL0:IMUX_C7	DCC7.CE
TCELL0:IMUX_D6	CLK_EDGE.INT_IN_0
TCELL0:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL0:IMUX_LSR0	PCSCLKDIV0.RST
TCELL0:IMUX_CLK0_DELAY	PCSCLKDIV0.CLKI
TCELL1:IMUX_C0	DCC8.CE
TCELL1:IMUX_C1	DCC9.CE
TCELL1:IMUX_C2	DCC10.CE
TCELL1:IMUX_C3	DCC11.CE
TCELL1:IMUX_C4	DCC12.CE
TCELL1:IMUX_C5	DCC13.CE
TCELL1:IMUX_C6	DCC14.CE
TCELL1:IMUX_C7	DCC15.CE
TCELL1:IMUX_D6	CLK_EDGE.INT_IN_2
TCELL1:IMUX_D7	CLK_EDGE.INT_IN_3

Tile CLK_S_M

Cells: 4

Bel PCSCLKDIV0

ecp4 CLK_S_M bel PCSCLKDIV0
Pin	Direction	Wires
CLKI	input	TCELL0:IMUX_CLK0_DELAY
RST	input	TCELL0:IMUX_LSR0
SEL0	input	TCELL0:IMUX_A4
SEL1	input	TCELL0:IMUX_A5
SEL2	input	TCELL0:IMUX_A6

Bel PCSCLKDIV1

ecp4 CLK_S_M bel PCSCLKDIV1
Pin	Direction	Wires
CLKI	input	TCELL0:IMUX_CLK1_DELAY
RST	input	TCELL0:IMUX_LSR1
SEL0	input	TCELL0:IMUX_B4
SEL1	input	TCELL0:IMUX_B5
SEL2	input	TCELL0:IMUX_B6

Bel DCC0

ecp4 CLK_S_M bel DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C0

Bel DCC1

ecp4 CLK_S_M bel DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C1

Bel DCC2

ecp4 CLK_S_M bel DCC2
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C2

Bel DCC3

ecp4 CLK_S_M bel DCC3
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C3

Bel DCC4

ecp4 CLK_S_M bel DCC4
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C4

Bel DCC5

ecp4 CLK_S_M bel DCC5
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C5

Bel DCC6

ecp4 CLK_S_M bel DCC6
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C6

Bel DCC7

ecp4 CLK_S_M bel DCC7
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C7

Bel DCC8

ecp4 CLK_S_M bel DCC8
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C0

Bel DCC9

ecp4 CLK_S_M bel DCC9
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C1

Bel DCC10

ecp4 CLK_S_M bel DCC10
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C2

Bel DCC11

ecp4 CLK_S_M bel DCC11
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C3

Bel DCC12

ecp4 CLK_S_M bel DCC12
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C4

Bel DCC13

ecp4 CLK_S_M bel DCC13
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C5

Bel DCC14

ecp4 CLK_S_M bel DCC14
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C6

Bel DCC15

ecp4 CLK_S_M bel DCC15
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C7

Bel CLK_EDGE

ecp4 CLK_S_M bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL0:IMUX_D6
INT_IN_1	input	TCELL0:IMUX_D7
INT_IN_2	input	TCELL1:IMUX_D6
INT_IN_3	input	TCELL1:IMUX_D7
INT_IN_4	input	TCELL2:IMUX_C5
INT_IN_5	input	TCELL3:IMUX_C5

Bel CLKTEST

ecp4 CLK_S_M bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL0:IMUX_A0
TESTIN1	input	TCELL0:IMUX_A1
TESTIN2	input	TCELL0:IMUX_A2
TESTIN3	input	TCELL0:IMUX_A3

Bel wires

ecp4 CLK_S_M bel wires
Wire	Pins
TCELL0:IMUX_A0	CLKTEST.TESTIN0
TCELL0:IMUX_A1	CLKTEST.TESTIN1
TCELL0:IMUX_A2	CLKTEST.TESTIN2
TCELL0:IMUX_A3	CLKTEST.TESTIN3
TCELL0:IMUX_A4	PCSCLKDIV0.SEL0
TCELL0:IMUX_A5	PCSCLKDIV0.SEL1
TCELL0:IMUX_A6	PCSCLKDIV0.SEL2
TCELL0:IMUX_B4	PCSCLKDIV1.SEL0
TCELL0:IMUX_B5	PCSCLKDIV1.SEL1
TCELL0:IMUX_B6	PCSCLKDIV1.SEL2
TCELL0:IMUX_C0	DCC0.CE
TCELL0:IMUX_C1	DCC1.CE
TCELL0:IMUX_C2	DCC2.CE
TCELL0:IMUX_C3	DCC3.CE
TCELL0:IMUX_C4	DCC4.CE
TCELL0:IMUX_C5	DCC5.CE
TCELL0:IMUX_C6	DCC6.CE
TCELL0:IMUX_C7	DCC7.CE
TCELL0:IMUX_D6	CLK_EDGE.INT_IN_0
TCELL0:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL0:IMUX_LSR0	PCSCLKDIV0.RST
TCELL0:IMUX_LSR1	PCSCLKDIV1.RST
TCELL0:IMUX_CLK0_DELAY	PCSCLKDIV0.CLKI
TCELL0:IMUX_CLK1_DELAY	PCSCLKDIV1.CLKI
TCELL1:IMUX_C0	DCC8.CE
TCELL1:IMUX_C1	DCC9.CE
TCELL1:IMUX_C2	DCC10.CE
TCELL1:IMUX_C3	DCC11.CE
TCELL1:IMUX_C4	DCC12.CE
TCELL1:IMUX_C5	DCC13.CE
TCELL1:IMUX_C6	DCC14.CE
TCELL1:IMUX_C7	DCC15.CE
TCELL1:IMUX_D6	CLK_EDGE.INT_IN_2
TCELL1:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL2:IMUX_C5	CLK_EDGE.INT_IN_4
TCELL3:IMUX_C5	CLK_EDGE.INT_IN_5

Tile CLK_S_L

Cells: 6

Bel PCSCLKDIV0

ecp4 CLK_S_L bel PCSCLKDIV0
Pin	Direction	Wires
CLKI	input	TCELL0:IMUX_CLK0_DELAY
RST	input	TCELL0:IMUX_LSR0
SEL0	input	TCELL0:IMUX_A4
SEL1	input	TCELL0:IMUX_A5
SEL2	input	TCELL0:IMUX_A6

Bel PCSCLKDIV1

ecp4 CLK_S_L bel PCSCLKDIV1
Pin	Direction	Wires
CLKI	input	TCELL0:IMUX_CLK1_DELAY
RST	input	TCELL0:IMUX_LSR1
SEL0	input	TCELL0:IMUX_B4
SEL1	input	TCELL0:IMUX_B5
SEL2	input	TCELL0:IMUX_B6

Bel PCSCLKDIV2

ecp4 CLK_S_L bel PCSCLKDIV2
Pin	Direction	Wires
CLKI	input	TCELL1:IMUX_CLK0_DELAY
RST	input	TCELL1:IMUX_LSR0
SEL0	input	TCELL1:IMUX_A4
SEL1	input	TCELL1:IMUX_A5
SEL2	input	TCELL1:IMUX_A6

Bel DCC0

ecp4 CLK_S_L bel DCC0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C0

Bel DCC1

ecp4 CLK_S_L bel DCC1
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C1

Bel DCC2

ecp4 CLK_S_L bel DCC2
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C2

Bel DCC3

ecp4 CLK_S_L bel DCC3
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C3

Bel DCC4

ecp4 CLK_S_L bel DCC4
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C4

Bel DCC5

ecp4 CLK_S_L bel DCC5
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C5

Bel DCC6

ecp4 CLK_S_L bel DCC6
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C6

Bel DCC7

ecp4 CLK_S_L bel DCC7
Pin	Direction	Wires
CE	input	TCELL0:IMUX_C7

Bel DCC8

ecp4 CLK_S_L bel DCC8
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C0

Bel DCC9

ecp4 CLK_S_L bel DCC9
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C1

Bel DCC10

ecp4 CLK_S_L bel DCC10
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C2

Bel DCC11

ecp4 CLK_S_L bel DCC11
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C3

Bel DCC12

ecp4 CLK_S_L bel DCC12
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C4

Bel DCC13

ecp4 CLK_S_L bel DCC13
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C5

Bel DCC14

ecp4 CLK_S_L bel DCC14
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C6

Bel DCC15

ecp4 CLK_S_L bel DCC15
Pin	Direction	Wires
CE	input	TCELL1:IMUX_C7

Bel CLK_EDGE

ecp4 CLK_S_L bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL0:IMUX_D6
INT_IN_1	input	TCELL0:IMUX_D7
INT_IN_2	input	TCELL1:IMUX_D6
INT_IN_3	input	TCELL1:IMUX_D7
INT_IN_4	input	TCELL2:IMUX_C5
INT_IN_5	input	TCELL4:IMUX_C5
INT_IN_6	input	TCELL3:IMUX_C5
INT_IN_7	input	TCELL5:IMUX_C5

Bel CLKTEST

ecp4 CLK_S_L bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL0:IMUX_A0
TESTIN1	input	TCELL0:IMUX_A1
TESTIN2	input	TCELL0:IMUX_A2
TESTIN3	input	TCELL0:IMUX_A3

Bel wires

ecp4 CLK_S_L bel wires
Wire	Pins
TCELL0:IMUX_A0	CLKTEST.TESTIN0
TCELL0:IMUX_A1	CLKTEST.TESTIN1
TCELL0:IMUX_A2	CLKTEST.TESTIN2
TCELL0:IMUX_A3	CLKTEST.TESTIN3
TCELL0:IMUX_A4	PCSCLKDIV0.SEL0
TCELL0:IMUX_A5	PCSCLKDIV0.SEL1
TCELL0:IMUX_A6	PCSCLKDIV0.SEL2
TCELL0:IMUX_B4	PCSCLKDIV1.SEL0
TCELL0:IMUX_B5	PCSCLKDIV1.SEL1
TCELL0:IMUX_B6	PCSCLKDIV1.SEL2
TCELL0:IMUX_C0	DCC0.CE
TCELL0:IMUX_C1	DCC1.CE
TCELL0:IMUX_C2	DCC2.CE
TCELL0:IMUX_C3	DCC3.CE
TCELL0:IMUX_C4	DCC4.CE
TCELL0:IMUX_C5	DCC5.CE
TCELL0:IMUX_C6	DCC6.CE
TCELL0:IMUX_C7	DCC7.CE
TCELL0:IMUX_D6	CLK_EDGE.INT_IN_0
TCELL0:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL0:IMUX_LSR0	PCSCLKDIV0.RST
TCELL0:IMUX_LSR1	PCSCLKDIV1.RST
TCELL0:IMUX_CLK0_DELAY	PCSCLKDIV0.CLKI
TCELL0:IMUX_CLK1_DELAY	PCSCLKDIV1.CLKI
TCELL1:IMUX_A4	PCSCLKDIV2.SEL0
TCELL1:IMUX_A5	PCSCLKDIV2.SEL1
TCELL1:IMUX_A6	PCSCLKDIV2.SEL2
TCELL1:IMUX_C0	DCC8.CE
TCELL1:IMUX_C1	DCC9.CE
TCELL1:IMUX_C2	DCC10.CE
TCELL1:IMUX_C3	DCC11.CE
TCELL1:IMUX_C4	DCC12.CE
TCELL1:IMUX_C5	DCC13.CE
TCELL1:IMUX_C6	DCC14.CE
TCELL1:IMUX_C7	DCC15.CE
TCELL1:IMUX_D6	CLK_EDGE.INT_IN_2
TCELL1:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL1:IMUX_LSR0	PCSCLKDIV2.RST
TCELL1:IMUX_CLK0_DELAY	PCSCLKDIV2.CLKI
TCELL2:IMUX_C5	CLK_EDGE.INT_IN_4
TCELL3:IMUX_C5	CLK_EDGE.INT_IN_6
TCELL4:IMUX_C5	CLK_EDGE.INT_IN_5
TCELL5:IMUX_C5	CLK_EDGE.INT_IN_7

Tile CLK_N_S

Cells: 8

Bel DLLDEL2

ecp4 CLK_N_S bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL2:OUT_Q7
DIRECTION	input	TCELL2:IMUX_D6
LOADN	input	TCELL2:IMUX_B6
MOVE	input	TCELL2:IMUX_C6

Bel DLLDEL3

ecp4 CLK_N_S bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL3:OUT_Q7
DIRECTION	input	TCELL3:IMUX_D6
LOADN	input	TCELL3:IMUX_B6
MOVE	input	TCELL3:IMUX_C6

Bel DLLDEL4

ecp4 CLK_N_S bel DLLDEL4
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel DLLDEL5

ecp4 CLK_N_S bel DLLDEL5
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel CLKDIV0

ecp4 CLK_N_S bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL4:IMUX_A4
CDIVX	output	TCELL3:OUT_Q0
RST	input	TCELL3:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_N_S bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL4:IMUX_B4
CDIVX	output	TCELL3:OUT_Q1
RST	input	TCELL3:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_N_S bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL4:IMUX_C2
CDIVX	output	TCELL3:OUT_Q2
RST	input	TCELL4:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_N_S bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL4:IMUX_D4
CDIVX	output	TCELL3:OUT_Q3
RST	input	TCELL4:IMUX_LSR1

Bel DCC0

ecp4 CLK_N_S bel DCC0
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A2

Bel DCC1

ecp4 CLK_N_S bel DCC1
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B0

Bel DCC2

ecp4 CLK_N_S bel DCC2
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C4

Bel DCC3

ecp4 CLK_N_S bel DCC3
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A6

Bel DCC4

ecp4 CLK_N_S bel DCC4
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A3

Bel DCC5

ecp4 CLK_N_S bel DCC5
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B1

Bel DCC6

ecp4 CLK_N_S bel DCC6
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C7

Bel DCC7

ecp4 CLK_N_S bel DCC7
Pin	Direction	Wires
CE	input	TCELL3:IMUX_D3

Bel DCC8

ecp4 CLK_N_S bel DCC8
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A2

Bel DCC9

ecp4 CLK_N_S bel DCC9
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B0

Bel DCC10

ecp4 CLK_N_S bel DCC10
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C4

Bel DCC11

ecp4 CLK_N_S bel DCC11
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A6

Bel DCC12

ecp4 CLK_N_S bel DCC12
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A3

Bel DCC13

ecp4 CLK_N_S bel DCC13
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B1

Bel DCC14

ecp4 CLK_N_S bel DCC14
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C7

Bel DCC15

ecp4 CLK_N_S bel DCC15
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D3

Bel CLK_EDGE

ecp4 CLK_N_S bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL2:IMUX_D7
INT_IN_1	input	TCELL3:IMUX_D7
INT_IN_2	input	TCELL4:IMUX_D7
INT_IN_3	input	TCELL5:IMUX_D7

Bel CLKTEST

ecp4 CLK_N_S bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL2:IMUX_A5
TESTIN1	input	TCELL2:IMUX_B5
TESTIN2	input	TCELL2:IMUX_C5
TESTIN3	input	TCELL2:IMUX_D5

Bel ECLKSYNC4

ecp4 CLK_N_S bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F0
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL3:IMUX_A0

Bel ECLKSYNC5

ecp4 CLK_N_S bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F1
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL3:IMUX_B2

Bel ECLKSYNC6

ecp4 CLK_N_S bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F2
ECLKI	input	TCELL3:IMUX_CLK0_DELAY
STOP	input	TCELL3:IMUX_C0

Bel ECLKSYNC7

ecp4 CLK_N_S bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F3
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL3:IMUX_D0

Bel ECLKSYNC8

ecp4 CLK_N_S bel ECLKSYNC8
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F0
ECLKI	input	TCELL4:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A1

Bel ECLKSYNC9

ecp4 CLK_N_S bel ECLKSYNC9
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F1
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B3

Bel ECLKSYNC10

ecp4 CLK_N_S bel ECLKSYNC10
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F2
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C1

Bel ECLKSYNC11

ecp4 CLK_N_S bel ECLKSYNC11
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F3
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D1

Bel CLKTEST_ECLK

ecp4 CLK_N_S bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL3:IMUX_A4
TESTIN1	input	TCELL3:IMUX_B4
TESTIN2	input	TCELL3:IMUX_C2
TESTIN3	input	TCELL3:IMUX_D4
TESTIN4	input	TCELL3:IMUX_A7
TESTIN5	input	TCELL3:IMUX_B7
TESTIN6	input	TCELL3:IMUX_C3

Bel wires

ecp4 CLK_N_S bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC4.ECLKI
TCELL2:IMUX_A5	CLKTEST.TESTIN0
TCELL2:IMUX_B5	CLKTEST.TESTIN1
TCELL2:IMUX_B6	DLLDEL2.LOADN
TCELL2:IMUX_C5	CLKTEST.TESTIN2
TCELL2:IMUX_C6	DLLDEL2.MOVE
TCELL2:IMUX_D5	CLKTEST.TESTIN3
TCELL2:IMUX_D6	DLLDEL2.DIRECTION
TCELL2:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL2:OUT_Q7	DLLDEL2.CFLAG
TCELL3:IMUX_A0	ECLKSYNC4.STOP
TCELL3:IMUX_A2	DCC0.CE
TCELL3:IMUX_A3	DCC4.CE
TCELL3:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL3:IMUX_A6	DCC3.CE
TCELL3:IMUX_A7	CLKTEST_ECLK.TESTIN4
TCELL3:IMUX_B0	DCC1.CE
TCELL3:IMUX_B1	DCC5.CE
TCELL3:IMUX_B2	ECLKSYNC5.STOP
TCELL3:IMUX_B4	CLKTEST_ECLK.TESTIN1
TCELL3:IMUX_B6	DLLDEL3.LOADN
TCELL3:IMUX_B7	CLKTEST_ECLK.TESTIN5
TCELL3:IMUX_C0	ECLKSYNC6.STOP
TCELL3:IMUX_C2	CLKTEST_ECLK.TESTIN2
TCELL3:IMUX_C3	CLKTEST_ECLK.TESTIN6
TCELL3:IMUX_C4	DCC2.CE
TCELL3:IMUX_C6	DLLDEL3.MOVE
TCELL3:IMUX_C7	DCC6.CE
TCELL3:IMUX_D0	ECLKSYNC7.STOP
TCELL3:IMUX_D3	DCC7.CE
TCELL3:IMUX_D4	CLKTEST_ECLK.TESTIN3
TCELL3:IMUX_D6	DLLDEL3.DIRECTION
TCELL3:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL3:IMUX_LSR0	CLKDIV0.RST
TCELL3:IMUX_LSR1	CLKDIV1.RST
TCELL3:IMUX_CLK0_DELAY	ECLKSYNC6.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI
TCELL3:OUT_F0	ECLKSYNC4.ECLK
TCELL3:OUT_F1	ECLKSYNC5.ECLK
TCELL3:OUT_F2	ECLKSYNC6.ECLK
TCELL3:OUT_F3	ECLKSYNC7.ECLK
TCELL3:OUT_Q0	CLKDIV0.CDIVX
TCELL3:OUT_Q1	CLKDIV1.CDIVX
TCELL3:OUT_Q2	CLKDIV2.CDIVX
TCELL3:OUT_Q3	CLKDIV3.CDIVX
TCELL3:OUT_Q7	DLLDEL3.CFLAG
TCELL4:IMUX_A1	ECLKSYNC8.STOP
TCELL4:IMUX_A2	DCC8.CE
TCELL4:IMUX_A3	DCC12.CE
TCELL4:IMUX_A4	CLKDIV0.ALIGNWD
TCELL4:IMUX_A6	DCC11.CE
TCELL4:IMUX_B0	DCC9.CE
TCELL4:IMUX_B1	DCC13.CE
TCELL4:IMUX_B3	ECLKSYNC9.STOP
TCELL4:IMUX_B4	CLKDIV1.ALIGNWD
TCELL4:IMUX_B6	DLLDEL4.LOADN
TCELL4:IMUX_C1	ECLKSYNC10.STOP
TCELL4:IMUX_C2	CLKDIV2.ALIGNWD
TCELL4:IMUX_C4	DCC10.CE
TCELL4:IMUX_C6	DLLDEL4.MOVE
TCELL4:IMUX_C7	DCC14.CE
TCELL4:IMUX_D1	ECLKSYNC11.STOP
TCELL4:IMUX_D3	DCC15.CE
TCELL4:IMUX_D4	CLKDIV3.ALIGNWD
TCELL4:IMUX_D6	DLLDEL4.DIRECTION
TCELL4:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL4:IMUX_LSR0	CLKDIV2.RST
TCELL4:IMUX_LSR1	CLKDIV3.RST
TCELL4:IMUX_CLK0_DELAY	ECLKSYNC8.ECLKI
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC9.ECLKI
TCELL4:OUT_F0	ECLKSYNC8.ECLK
TCELL4:OUT_F1	ECLKSYNC9.ECLK
TCELL4:OUT_F2	ECLKSYNC10.ECLK
TCELL4:OUT_F3	ECLKSYNC11.ECLK
TCELL4:OUT_Q7	DLLDEL4.CFLAG
TCELL5:IMUX_B6	DLLDEL5.LOADN
TCELL5:IMUX_C6	DLLDEL5.MOVE
TCELL5:IMUX_D6	DLLDEL5.DIRECTION
TCELL5:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC10.ECLKI
TCELL5:OUT_Q7	DLLDEL5.CFLAG
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC11.ECLKI

Tile CLK_N_M

Cells: 10

Bel DLLDEL2

ecp4 CLK_N_M bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL2:OUT_Q7
DIRECTION	input	TCELL2:IMUX_D6
LOADN	input	TCELL2:IMUX_B6
MOVE	input	TCELL2:IMUX_C6

Bel DLLDEL3

ecp4 CLK_N_M bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL3:OUT_Q7
DIRECTION	input	TCELL3:IMUX_D6
LOADN	input	TCELL3:IMUX_B6
MOVE	input	TCELL3:IMUX_C6

Bel DLLDEL4

ecp4 CLK_N_M bel DLLDEL4
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel DLLDEL5

ecp4 CLK_N_M bel DLLDEL5
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel CLKDIV0

ecp4 CLK_N_M bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL4:IMUX_A4
CDIVX	output	TCELL3:OUT_Q0
RST	input	TCELL3:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_N_M bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL4:IMUX_B4
CDIVX	output	TCELL3:OUT_Q1
RST	input	TCELL3:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_N_M bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL4:IMUX_C2
CDIVX	output	TCELL3:OUT_Q2
RST	input	TCELL4:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_N_M bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL4:IMUX_D4
CDIVX	output	TCELL3:OUT_Q3
RST	input	TCELL4:IMUX_LSR1

Bel DCC0

ecp4 CLK_N_M bel DCC0
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A2

Bel DCC1

ecp4 CLK_N_M bel DCC1
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B0

Bel DCC2

ecp4 CLK_N_M bel DCC2
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C4

Bel DCC3

ecp4 CLK_N_M bel DCC3
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A6

Bel DCC4

ecp4 CLK_N_M bel DCC4
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A3

Bel DCC5

ecp4 CLK_N_M bel DCC5
Pin	Direction	Wires
CE	input	TCELL3:IMUX_B1

Bel DCC6

ecp4 CLK_N_M bel DCC6
Pin	Direction	Wires
CE	input	TCELL3:IMUX_C7

Bel DCC7

ecp4 CLK_N_M bel DCC7
Pin	Direction	Wires
CE	input	TCELL3:IMUX_D3

Bel DCC8

ecp4 CLK_N_M bel DCC8
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A2

Bel DCC9

ecp4 CLK_N_M bel DCC9
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B0

Bel DCC10

ecp4 CLK_N_M bel DCC10
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C4

Bel DCC11

ecp4 CLK_N_M bel DCC11
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A6

Bel DCC12

ecp4 CLK_N_M bel DCC12
Pin	Direction	Wires
CE	input	TCELL4:IMUX_A3

Bel DCC13

ecp4 CLK_N_M bel DCC13
Pin	Direction	Wires
CE	input	TCELL4:IMUX_B1

Bel DCC14

ecp4 CLK_N_M bel DCC14
Pin	Direction	Wires
CE	input	TCELL4:IMUX_C7

Bel DCC15

ecp4 CLK_N_M bel DCC15
Pin	Direction	Wires
CE	input	TCELL4:IMUX_D3

Bel CLK_EDGE

ecp4 CLK_N_M bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL2:IMUX_D7
INT_IN_1	input	TCELL3:IMUX_D7
INT_IN_2	input	TCELL4:IMUX_D7
INT_IN_3	input	TCELL5:IMUX_D7
INT_IN_4	input	TCELL8:IMUX_C5
INT_IN_5	input	TCELL9:IMUX_C5

Bel CLKTEST

ecp4 CLK_N_M bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL2:IMUX_A5
TESTIN1	input	TCELL2:IMUX_B5
TESTIN2	input	TCELL2:IMUX_C5
TESTIN3	input	TCELL2:IMUX_D5

Bel ECLKSYNC4

ecp4 CLK_N_M bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F0
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL3:IMUX_A0

Bel ECLKSYNC5

ecp4 CLK_N_M bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F1
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL3:IMUX_B2

Bel ECLKSYNC6

ecp4 CLK_N_M bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F2
ECLKI	input	TCELL3:IMUX_CLK0_DELAY
STOP	input	TCELL3:IMUX_C0

Bel ECLKSYNC7

ecp4 CLK_N_M bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL3:OUT_F3
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL3:IMUX_D0

Bel ECLKSYNC8

ecp4 CLK_N_M bel ECLKSYNC8
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F0
ECLKI	input	TCELL4:IMUX_CLK0_DELAY
STOP	input	TCELL4:IMUX_A1

Bel ECLKSYNC9

ecp4 CLK_N_M bel ECLKSYNC9
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F1
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_B3

Bel ECLKSYNC10

ecp4 CLK_N_M bel ECLKSYNC10
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F2
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_C1

Bel ECLKSYNC11

ecp4 CLK_N_M bel ECLKSYNC11
Pin	Direction	Wires
ECLK	output	TCELL4:OUT_F3
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL4:IMUX_D1

Bel CLKTEST_ECLK

ecp4 CLK_N_M bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL3:IMUX_A4
TESTIN1	input	TCELL3:IMUX_B4
TESTIN2	input	TCELL3:IMUX_C2
TESTIN3	input	TCELL3:IMUX_D4
TESTIN4	input	TCELL3:IMUX_A7
TESTIN5	input	TCELL3:IMUX_B7
TESTIN6	input	TCELL3:IMUX_C3

Bel wires

ecp4 CLK_N_M bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC4.ECLKI
TCELL2:IMUX_A5	CLKTEST.TESTIN0
TCELL2:IMUX_B5	CLKTEST.TESTIN1
TCELL2:IMUX_B6	DLLDEL2.LOADN
TCELL2:IMUX_C5	CLKTEST.TESTIN2
TCELL2:IMUX_C6	DLLDEL2.MOVE
TCELL2:IMUX_D5	CLKTEST.TESTIN3
TCELL2:IMUX_D6	DLLDEL2.DIRECTION
TCELL2:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL2:OUT_Q7	DLLDEL2.CFLAG
TCELL3:IMUX_A0	ECLKSYNC4.STOP
TCELL3:IMUX_A2	DCC0.CE
TCELL3:IMUX_A3	DCC4.CE
TCELL3:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL3:IMUX_A6	DCC3.CE
TCELL3:IMUX_A7	CLKTEST_ECLK.TESTIN4
TCELL3:IMUX_B0	DCC1.CE
TCELL3:IMUX_B1	DCC5.CE
TCELL3:IMUX_B2	ECLKSYNC5.STOP
TCELL3:IMUX_B4	CLKTEST_ECLK.TESTIN1
TCELL3:IMUX_B6	DLLDEL3.LOADN
TCELL3:IMUX_B7	CLKTEST_ECLK.TESTIN5
TCELL3:IMUX_C0	ECLKSYNC6.STOP
TCELL3:IMUX_C2	CLKTEST_ECLK.TESTIN2
TCELL3:IMUX_C3	CLKTEST_ECLK.TESTIN6
TCELL3:IMUX_C4	DCC2.CE
TCELL3:IMUX_C6	DLLDEL3.MOVE
TCELL3:IMUX_C7	DCC6.CE
TCELL3:IMUX_D0	ECLKSYNC7.STOP
TCELL3:IMUX_D3	DCC7.CE
TCELL3:IMUX_D4	CLKTEST_ECLK.TESTIN3
TCELL3:IMUX_D6	DLLDEL3.DIRECTION
TCELL3:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL3:IMUX_LSR0	CLKDIV0.RST
TCELL3:IMUX_LSR1	CLKDIV1.RST
TCELL3:IMUX_CLK0_DELAY	ECLKSYNC6.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI
TCELL3:OUT_F0	ECLKSYNC4.ECLK
TCELL3:OUT_F1	ECLKSYNC5.ECLK
TCELL3:OUT_F2	ECLKSYNC6.ECLK
TCELL3:OUT_F3	ECLKSYNC7.ECLK
TCELL3:OUT_Q0	CLKDIV0.CDIVX
TCELL3:OUT_Q1	CLKDIV1.CDIVX
TCELL3:OUT_Q2	CLKDIV2.CDIVX
TCELL3:OUT_Q3	CLKDIV3.CDIVX
TCELL3:OUT_Q7	DLLDEL3.CFLAG
TCELL4:IMUX_A1	ECLKSYNC8.STOP
TCELL4:IMUX_A2	DCC8.CE
TCELL4:IMUX_A3	DCC12.CE
TCELL4:IMUX_A4	CLKDIV0.ALIGNWD
TCELL4:IMUX_A6	DCC11.CE
TCELL4:IMUX_B0	DCC9.CE
TCELL4:IMUX_B1	DCC13.CE
TCELL4:IMUX_B3	ECLKSYNC9.STOP
TCELL4:IMUX_B4	CLKDIV1.ALIGNWD
TCELL4:IMUX_B6	DLLDEL4.LOADN
TCELL4:IMUX_C1	ECLKSYNC10.STOP
TCELL4:IMUX_C2	CLKDIV2.ALIGNWD
TCELL4:IMUX_C4	DCC10.CE
TCELL4:IMUX_C6	DLLDEL4.MOVE
TCELL4:IMUX_C7	DCC14.CE
TCELL4:IMUX_D1	ECLKSYNC11.STOP
TCELL4:IMUX_D3	DCC15.CE
TCELL4:IMUX_D4	CLKDIV3.ALIGNWD
TCELL4:IMUX_D6	DLLDEL4.DIRECTION
TCELL4:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL4:IMUX_LSR0	CLKDIV2.RST
TCELL4:IMUX_LSR1	CLKDIV3.RST
TCELL4:IMUX_CLK0_DELAY	ECLKSYNC8.ECLKI
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC9.ECLKI
TCELL4:OUT_F0	ECLKSYNC8.ECLK
TCELL4:OUT_F1	ECLKSYNC9.ECLK
TCELL4:OUT_F2	ECLKSYNC10.ECLK
TCELL4:OUT_F3	ECLKSYNC11.ECLK
TCELL4:OUT_Q7	DLLDEL4.CFLAG
TCELL5:IMUX_B6	DLLDEL5.LOADN
TCELL5:IMUX_C6	DLLDEL5.MOVE
TCELL5:IMUX_D6	DLLDEL5.DIRECTION
TCELL5:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC10.ECLKI
TCELL5:OUT_Q7	DLLDEL5.CFLAG
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC11.ECLKI
TCELL8:IMUX_C5	CLK_EDGE.INT_IN_4
TCELL9:IMUX_C5	CLK_EDGE.INT_IN_5

Tile CLK_N_L

Cells: 22

Bel DLLDEL0

ecp4 CLK_N_L bel DLLDEL0
Pin	Direction	Wires
CFLAG	output	TCELL4:OUT_Q7
DIRECTION	input	TCELL4:IMUX_D6
LOADN	input	TCELL4:IMUX_B6
MOVE	input	TCELL4:IMUX_C6

Bel DLLDEL1

ecp4 CLK_N_L bel DLLDEL1
Pin	Direction	Wires
CFLAG	output	TCELL5:OUT_Q7
DIRECTION	input	TCELL5:IMUX_D6
LOADN	input	TCELL5:IMUX_B6
MOVE	input	TCELL5:IMUX_C6

Bel DLLDEL2

ecp4 CLK_N_L bel DLLDEL2
Pin	Direction	Wires
CFLAG	output	TCELL6:OUT_Q7
DIRECTION	input	TCELL6:IMUX_D6
LOADN	input	TCELL6:IMUX_B6
MOVE	input	TCELL6:IMUX_C6

Bel DLLDEL3

ecp4 CLK_N_L bel DLLDEL3
Pin	Direction	Wires
CFLAG	output	TCELL7:OUT_Q7
DIRECTION	input	TCELL7:IMUX_D6
LOADN	input	TCELL7:IMUX_B6
MOVE	input	TCELL7:IMUX_C6

Bel DLLDEL4

ecp4 CLK_N_L bel DLLDEL4
Pin	Direction	Wires
CFLAG	output	TCELL8:OUT_Q7
DIRECTION	input	TCELL8:IMUX_D6
LOADN	input	TCELL8:IMUX_B6
MOVE	input	TCELL8:IMUX_C6

Bel DLLDEL5

ecp4 CLK_N_L bel DLLDEL5
Pin	Direction	Wires
CFLAG	output	TCELL9:OUT_Q7
DIRECTION	input	TCELL9:IMUX_D6
LOADN	input	TCELL9:IMUX_B6
MOVE	input	TCELL9:IMUX_C6

Bel DLLDEL6

ecp4 CLK_N_L bel DLLDEL6
Pin	Direction	Wires
CFLAG	output	TCELL10:OUT_Q7
DIRECTION	input	TCELL10:IMUX_D6
LOADN	input	TCELL10:IMUX_B6
MOVE	input	TCELL10:IMUX_C6

Bel DLLDEL7

ecp4 CLK_N_L bel DLLDEL7
Pin	Direction	Wires
CFLAG	output	TCELL11:OUT_Q7
DIRECTION	input	TCELL11:IMUX_D6
LOADN	input	TCELL11:IMUX_B6
MOVE	input	TCELL11:IMUX_C6

Bel CLKDIV0

ecp4 CLK_N_L bel CLKDIV0
Pin	Direction	Wires
ALIGNWD	input	TCELL8:IMUX_A4
CDIVX	output	TCELL7:OUT_Q0
RST	input	TCELL7:IMUX_LSR0

Bel CLKDIV1

ecp4 CLK_N_L bel CLKDIV1
Pin	Direction	Wires
ALIGNWD	input	TCELL8:IMUX_B4
CDIVX	output	TCELL7:OUT_Q1
RST	input	TCELL7:IMUX_LSR1

Bel CLKDIV2

ecp4 CLK_N_L bel CLKDIV2
Pin	Direction	Wires
ALIGNWD	input	TCELL8:IMUX_C2
CDIVX	output	TCELL7:OUT_Q2
RST	input	TCELL8:IMUX_LSR0

Bel CLKDIV3

ecp4 CLK_N_L bel CLKDIV3
Pin	Direction	Wires
ALIGNWD	input	TCELL8:IMUX_D4
CDIVX	output	TCELL7:OUT_Q3
RST	input	TCELL8:IMUX_LSR1

Bel DCC0

ecp4 CLK_N_L bel DCC0
Pin	Direction	Wires
CE	input	TCELL7:IMUX_A2

Bel DCC1

ecp4 CLK_N_L bel DCC1
Pin	Direction	Wires
CE	input	TCELL7:IMUX_B0

Bel DCC2

ecp4 CLK_N_L bel DCC2
Pin	Direction	Wires
CE	input	TCELL7:IMUX_C4

Bel DCC3

ecp4 CLK_N_L bel DCC3
Pin	Direction	Wires
CE	input	TCELL7:IMUX_A6

Bel DCC4

ecp4 CLK_N_L bel DCC4
Pin	Direction	Wires
CE	input	TCELL7:IMUX_A3

Bel DCC5

ecp4 CLK_N_L bel DCC5
Pin	Direction	Wires
CE	input	TCELL7:IMUX_B1

Bel DCC6

ecp4 CLK_N_L bel DCC6
Pin	Direction	Wires
CE	input	TCELL7:IMUX_C7

Bel DCC7

ecp4 CLK_N_L bel DCC7
Pin	Direction	Wires
CE	input	TCELL7:IMUX_D3

Bel DCC8

ecp4 CLK_N_L bel DCC8
Pin	Direction	Wires
CE	input	TCELL8:IMUX_A2

Bel DCC9

ecp4 CLK_N_L bel DCC9
Pin	Direction	Wires
CE	input	TCELL8:IMUX_B0

Bel DCC10

ecp4 CLK_N_L bel DCC10
Pin	Direction	Wires
CE	input	TCELL8:IMUX_C4

Bel DCC11

ecp4 CLK_N_L bel DCC11
Pin	Direction	Wires
CE	input	TCELL8:IMUX_A6

Bel DCC12

ecp4 CLK_N_L bel DCC12
Pin	Direction	Wires
CE	input	TCELL8:IMUX_A3

Bel DCC13

ecp4 CLK_N_L bel DCC13
Pin	Direction	Wires
CE	input	TCELL8:IMUX_B1

Bel DCC14

ecp4 CLK_N_L bel DCC14
Pin	Direction	Wires
CE	input	TCELL8:IMUX_C7

Bel DCC15

ecp4 CLK_N_L bel DCC15
Pin	Direction	Wires
CE	input	TCELL8:IMUX_D3

Bel CLK_EDGE

ecp4 CLK_N_L bel CLK_EDGE
Pin	Direction	Wires
INT_IN_0	input	TCELL6:IMUX_D7
INT_IN_1	input	TCELL7:IMUX_D7
INT_IN_2	input	TCELL8:IMUX_D7
INT_IN_3	input	TCELL9:IMUX_D7
INT_IN_4	input	TCELL18:IMUX_C5
INT_IN_5	input	TCELL20:IMUX_C5
INT_IN_6	input	TCELL19:IMUX_C5
INT_IN_7	input	TCELL21:IMUX_C5

Bel CLKTEST

ecp4 CLK_N_L bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL6:IMUX_A5
TESTIN1	input	TCELL6:IMUX_B5
TESTIN2	input	TCELL6:IMUX_C5
TESTIN3	input	TCELL6:IMUX_D5

Bel ECLKSYNC0

ecp4 CLK_N_L bel ECLKSYNC0
Pin	Direction	Wires
ECLK	output	TCELL16:OUT_F0
ECLKI	input	TCELL1:IMUX_CLK1_DELAY
STOP	input	TCELL7:IMUX_A0

Bel ECLKSYNC1

ecp4 CLK_N_L bel ECLKSYNC1
Pin	Direction	Wires
ECLK	output	TCELL16:OUT_F1
ECLKI	input	TCELL2:IMUX_CLK1_DELAY
STOP	input	TCELL7:IMUX_B2

Bel ECLKSYNC2

ecp4 CLK_N_L bel ECLKSYNC2
Pin	Direction	Wires
ECLK	output	TCELL16:OUT_F2
ECLKI	input	TCELL3:IMUX_CLK1_DELAY
STOP	input	TCELL7:IMUX_C0

Bel ECLKSYNC3

ecp4 CLK_N_L bel ECLKSYNC3
Pin	Direction	Wires
ECLK	output	TCELL16:OUT_F3
ECLKI	input	TCELL4:IMUX_CLK1_DELAY
STOP	input	TCELL7:IMUX_D0

Bel ECLKSYNC4

ecp4 CLK_N_L bel ECLKSYNC4
Pin	Direction	Wires
ECLK	output	TCELL7:OUT_F0
ECLKI	input	TCELL5:IMUX_CLK1_DELAY
STOP	input	TCELL7:IMUX_A1

Bel ECLKSYNC5

ecp4 CLK_N_L bel ECLKSYNC5
Pin	Direction	Wires
ECLK	output	TCELL7:OUT_F1
ECLKI	input	TCELL6:IMUX_CLK1_DELAY
STOP	input	TCELL7:IMUX_B3

Bel ECLKSYNC6

ecp4 CLK_N_L bel ECLKSYNC6
Pin	Direction	Wires
ECLK	output	TCELL7:OUT_F2
ECLKI	input	TCELL7:IMUX_CLK0_DELAY
STOP	input	TCELL7:IMUX_C1

Bel ECLKSYNC7

ecp4 CLK_N_L bel ECLKSYNC7
Pin	Direction	Wires
ECLK	output	TCELL7:OUT_F3
ECLKI	input	TCELL7:IMUX_CLK1_DELAY
STOP	input	TCELL7:IMUX_D1

Bel ECLKSYNC8

ecp4 CLK_N_L bel ECLKSYNC8
Pin	Direction	Wires
ECLK	output	TCELL8:OUT_F0
ECLKI	input	TCELL11:IMUX_CLK1_DELAY
STOP	input	TCELL8:IMUX_A0

Bel ECLKSYNC9

ecp4 CLK_N_L bel ECLKSYNC9
Pin	Direction	Wires
ECLK	output	TCELL8:OUT_F1
ECLKI	input	TCELL12:IMUX_CLK1_DELAY
STOP	input	TCELL8:IMUX_B2

Bel ECLKSYNC10

ecp4 CLK_N_L bel ECLKSYNC10
Pin	Direction	Wires
ECLK	output	TCELL8:OUT_F2
ECLKI	input	TCELL13:IMUX_CLK1_DELAY
STOP	input	TCELL8:IMUX_C0

Bel ECLKSYNC11

ecp4 CLK_N_L bel ECLKSYNC11
Pin	Direction	Wires
ECLK	output	TCELL8:OUT_F3
ECLKI	input	TCELL15:IMUX_CLK1_DELAY
STOP	input	TCELL8:IMUX_D0

Bel ECLKSYNC12

ecp4 CLK_N_L bel ECLKSYNC12
Pin	Direction	Wires
ECLK	output	TCELL17:OUT_F0
ECLKI	input	TCELL8:IMUX_CLK0_DELAY
STOP	input	TCELL8:IMUX_A1

Bel ECLKSYNC13

ecp4 CLK_N_L bel ECLKSYNC13
Pin	Direction	Wires
ECLK	output	TCELL17:OUT_F1
ECLKI	input	TCELL8:IMUX_CLK1_DELAY
STOP	input	TCELL8:IMUX_B3

Bel ECLKSYNC14

ecp4 CLK_N_L bel ECLKSYNC14
Pin	Direction	Wires
ECLK	output	TCELL17:OUT_F2
ECLKI	input	TCELL9:IMUX_CLK1_DELAY
STOP	input	TCELL8:IMUX_C1

Bel ECLKSYNC15

ecp4 CLK_N_L bel ECLKSYNC15
Pin	Direction	Wires
ECLK	output	TCELL17:OUT_F3
ECLKI	input	TCELL10:IMUX_CLK1_DELAY
STOP	input	TCELL8:IMUX_D1

Bel CLKTEST_ECLK

ecp4 CLK_N_L bel CLKTEST_ECLK
Pin	Direction	Wires
TESTIN0	input	TCELL7:IMUX_A4
TESTIN1	input	TCELL7:IMUX_B4
TESTIN2	input	TCELL7:IMUX_C2
TESTIN3	input	TCELL7:IMUX_D4
TESTIN4	input	TCELL7:IMUX_A7
TESTIN5	input	TCELL7:IMUX_B7
TESTIN6	input	TCELL7:IMUX_C3

Bel wires

ecp4 CLK_N_L bel wires
Wire	Pins
TCELL1:IMUX_CLK1_DELAY	ECLKSYNC0.ECLKI
TCELL2:IMUX_CLK1_DELAY	ECLKSYNC1.ECLKI
TCELL3:IMUX_CLK1_DELAY	ECLKSYNC2.ECLKI
TCELL4:IMUX_B6	DLLDEL0.LOADN
TCELL4:IMUX_C6	DLLDEL0.MOVE
TCELL4:IMUX_D6	DLLDEL0.DIRECTION
TCELL4:IMUX_CLK1_DELAY	ECLKSYNC3.ECLKI
TCELL4:OUT_Q7	DLLDEL0.CFLAG
TCELL5:IMUX_B6	DLLDEL1.LOADN
TCELL5:IMUX_C6	DLLDEL1.MOVE
TCELL5:IMUX_D6	DLLDEL1.DIRECTION
TCELL5:IMUX_CLK1_DELAY	ECLKSYNC4.ECLKI
TCELL5:OUT_Q7	DLLDEL1.CFLAG
TCELL6:IMUX_A5	CLKTEST.TESTIN0
TCELL6:IMUX_B5	CLKTEST.TESTIN1
TCELL6:IMUX_B6	DLLDEL2.LOADN
TCELL6:IMUX_C5	CLKTEST.TESTIN2
TCELL6:IMUX_C6	DLLDEL2.MOVE
TCELL6:IMUX_D5	CLKTEST.TESTIN3
TCELL6:IMUX_D6	DLLDEL2.DIRECTION
TCELL6:IMUX_D7	CLK_EDGE.INT_IN_0
TCELL6:IMUX_CLK1_DELAY	ECLKSYNC5.ECLKI
TCELL6:OUT_Q7	DLLDEL2.CFLAG
TCELL7:IMUX_A0	ECLKSYNC0.STOP
TCELL7:IMUX_A1	ECLKSYNC4.STOP
TCELL7:IMUX_A2	DCC0.CE
TCELL7:IMUX_A3	DCC4.CE
TCELL7:IMUX_A4	CLKTEST_ECLK.TESTIN0
TCELL7:IMUX_A6	DCC3.CE
TCELL7:IMUX_A7	CLKTEST_ECLK.TESTIN4
TCELL7:IMUX_B0	DCC1.CE
TCELL7:IMUX_B1	DCC5.CE
TCELL7:IMUX_B2	ECLKSYNC1.STOP
TCELL7:IMUX_B3	ECLKSYNC5.STOP
TCELL7:IMUX_B4	CLKTEST_ECLK.TESTIN1
TCELL7:IMUX_B6	DLLDEL3.LOADN
TCELL7:IMUX_B7	CLKTEST_ECLK.TESTIN5
TCELL7:IMUX_C0	ECLKSYNC2.STOP
TCELL7:IMUX_C1	ECLKSYNC6.STOP
TCELL7:IMUX_C2	CLKTEST_ECLK.TESTIN2
TCELL7:IMUX_C3	CLKTEST_ECLK.TESTIN6
TCELL7:IMUX_C4	DCC2.CE
TCELL7:IMUX_C6	DLLDEL3.MOVE
TCELL7:IMUX_C7	DCC6.CE
TCELL7:IMUX_D0	ECLKSYNC3.STOP
TCELL7:IMUX_D1	ECLKSYNC7.STOP
TCELL7:IMUX_D3	DCC7.CE
TCELL7:IMUX_D4	CLKTEST_ECLK.TESTIN3
TCELL7:IMUX_D6	DLLDEL3.DIRECTION
TCELL7:IMUX_D7	CLK_EDGE.INT_IN_1
TCELL7:IMUX_LSR0	CLKDIV0.RST
TCELL7:IMUX_LSR1	CLKDIV1.RST
TCELL7:IMUX_CLK0_DELAY	ECLKSYNC6.ECLKI
TCELL7:IMUX_CLK1_DELAY	ECLKSYNC7.ECLKI
TCELL7:OUT_F0	ECLKSYNC4.ECLK
TCELL7:OUT_F1	ECLKSYNC5.ECLK
TCELL7:OUT_F2	ECLKSYNC6.ECLK
TCELL7:OUT_F3	ECLKSYNC7.ECLK
TCELL7:OUT_Q0	CLKDIV0.CDIVX
TCELL7:OUT_Q1	CLKDIV1.CDIVX
TCELL7:OUT_Q2	CLKDIV2.CDIVX
TCELL7:OUT_Q3	CLKDIV3.CDIVX
TCELL7:OUT_Q7	DLLDEL3.CFLAG
TCELL8:IMUX_A0	ECLKSYNC8.STOP
TCELL8:IMUX_A1	ECLKSYNC12.STOP
TCELL8:IMUX_A2	DCC8.CE
TCELL8:IMUX_A3	DCC12.CE
TCELL8:IMUX_A4	CLKDIV0.ALIGNWD
TCELL8:IMUX_A6	DCC11.CE
TCELL8:IMUX_B0	DCC9.CE
TCELL8:IMUX_B1	DCC13.CE
TCELL8:IMUX_B2	ECLKSYNC9.STOP
TCELL8:IMUX_B3	ECLKSYNC13.STOP
TCELL8:IMUX_B4	CLKDIV1.ALIGNWD
TCELL8:IMUX_B6	DLLDEL4.LOADN
TCELL8:IMUX_C0	ECLKSYNC10.STOP
TCELL8:IMUX_C1	ECLKSYNC14.STOP
TCELL8:IMUX_C2	CLKDIV2.ALIGNWD
TCELL8:IMUX_C4	DCC10.CE
TCELL8:IMUX_C6	DLLDEL4.MOVE
TCELL8:IMUX_C7	DCC14.CE
TCELL8:IMUX_D0	ECLKSYNC11.STOP
TCELL8:IMUX_D1	ECLKSYNC15.STOP
TCELL8:IMUX_D3	DCC15.CE
TCELL8:IMUX_D4	CLKDIV3.ALIGNWD
TCELL8:IMUX_D6	DLLDEL4.DIRECTION
TCELL8:IMUX_D7	CLK_EDGE.INT_IN_2
TCELL8:IMUX_LSR0	CLKDIV2.RST
TCELL8:IMUX_LSR1	CLKDIV3.RST
TCELL8:IMUX_CLK0_DELAY	ECLKSYNC12.ECLKI
TCELL8:IMUX_CLK1_DELAY	ECLKSYNC13.ECLKI
TCELL8:OUT_F0	ECLKSYNC8.ECLK
TCELL8:OUT_F1	ECLKSYNC9.ECLK
TCELL8:OUT_F2	ECLKSYNC10.ECLK
TCELL8:OUT_F3	ECLKSYNC11.ECLK
TCELL8:OUT_Q7	DLLDEL4.CFLAG
TCELL9:IMUX_B6	DLLDEL5.LOADN
TCELL9:IMUX_C6	DLLDEL5.MOVE
TCELL9:IMUX_D6	DLLDEL5.DIRECTION
TCELL9:IMUX_D7	CLK_EDGE.INT_IN_3
TCELL9:IMUX_CLK1_DELAY	ECLKSYNC14.ECLKI
TCELL9:OUT_Q7	DLLDEL5.CFLAG
TCELL10:IMUX_B6	DLLDEL6.LOADN
TCELL10:IMUX_C6	DLLDEL6.MOVE
TCELL10:IMUX_D6	DLLDEL6.DIRECTION
TCELL10:IMUX_CLK1_DELAY	ECLKSYNC15.ECLKI
TCELL10:OUT_Q7	DLLDEL6.CFLAG
TCELL11:IMUX_B6	DLLDEL7.LOADN
TCELL11:IMUX_C6	DLLDEL7.MOVE
TCELL11:IMUX_D6	DLLDEL7.DIRECTION
TCELL11:IMUX_CLK1_DELAY	ECLKSYNC8.ECLKI
TCELL11:OUT_Q7	DLLDEL7.CFLAG
TCELL12:IMUX_CLK1_DELAY	ECLKSYNC9.ECLKI
TCELL13:IMUX_CLK1_DELAY	ECLKSYNC10.ECLKI
TCELL15:IMUX_CLK1_DELAY	ECLKSYNC11.ECLKI
TCELL16:OUT_F0	ECLKSYNC0.ECLK
TCELL16:OUT_F1	ECLKSYNC1.ECLK
TCELL16:OUT_F2	ECLKSYNC2.ECLK
TCELL16:OUT_F3	ECLKSYNC3.ECLK
TCELL17:OUT_F0	ECLKSYNC12.ECLK
TCELL17:OUT_F1	ECLKSYNC13.ECLK
TCELL17:OUT_F2	ECLKSYNC14.ECLK
TCELL17:OUT_F3	ECLKSYNC15.ECLK
TCELL18:IMUX_C5	CLK_EDGE.INT_IN_4
TCELL19:IMUX_C5	CLK_EDGE.INT_IN_6
TCELL20:IMUX_C5	CLK_EDGE.INT_IN_5
TCELL21:IMUX_C5	CLK_EDGE.INT_IN_7

Tile CLK_ROOT

Cells: 4

Bel DCC_SW0

ecp4 CLK_ROOT bel DCC_SW0
Pin	Direction	Wires
CE	input	TCELL0:IMUX_A0
CLKI	input	TCELL0:IMUX_D7

Bel DCC_SE0

ecp4 CLK_ROOT bel DCC_SE0
Pin	Direction	Wires
CE	input	TCELL1:IMUX_A0
CLKI	input	TCELL1:IMUX_D7

Bel DCC_NW0

ecp4 CLK_ROOT bel DCC_NW0
Pin	Direction	Wires
CE	input	TCELL2:IMUX_A0
CLKI	input	TCELL2:IMUX_D7

Bel DCC_NE0

ecp4 CLK_ROOT bel DCC_NE0
Pin	Direction	Wires
CE	input	TCELL3:IMUX_A0
CLKI	input	TCELL3:IMUX_D7

Bel DCS0

ecp4 CLK_ROOT bel DCS0
Pin	Direction	Wires
MODESEL	input	TCELL2:IMUX_C0
SEL0	input	TCELL2:IMUX_B4
SEL1	input	TCELL2:IMUX_B5
SEL2	input	TCELL2:IMUX_A3
SEL3	input	TCELL2:IMUX_A4

Bel DCS1

ecp4 CLK_ROOT bel DCS1
Pin	Direction	Wires
MODESEL	input	TCELL2:IMUX_C1
SEL0	input	TCELL2:IMUX_B6
SEL1	input	TCELL2:IMUX_B7
SEL2	input	TCELL2:IMUX_A5
SEL3	input	TCELL2:IMUX_A6

Bel CLK_ROOT

ecp4 CLK_ROOT bel CLK_ROOT
Pin	Direction	Wires
PCLK0_NE	output	TCELL3:PCLK0
PCLK0_NW	output	TCELL2:PCLK0
PCLK0_SE	output	TCELL1:PCLK0
PCLK0_SW	output	TCELL0:PCLK0
PCLK10_NE	output	TCELL3:PCLK10
PCLK10_NW	output	TCELL2:PCLK10
PCLK10_SE	output	TCELL1:PCLK10
PCLK10_SW	output	TCELL0:PCLK10
PCLK11_NE	output	TCELL3:PCLK11
PCLK11_NW	output	TCELL2:PCLK11
PCLK11_SE	output	TCELL1:PCLK11
PCLK11_SW	output	TCELL0:PCLK11
PCLK12_NE	output	TCELL3:PCLK12
PCLK12_NW	output	TCELL2:PCLK12
PCLK12_SE	output	TCELL1:PCLK12
PCLK12_SW	output	TCELL0:PCLK12
PCLK13_NE	output	TCELL3:PCLK13
PCLK13_NW	output	TCELL2:PCLK13
PCLK13_SE	output	TCELL1:PCLK13
PCLK13_SW	output	TCELL0:PCLK13
PCLK14_NE	output	TCELL3:PCLK14
PCLK14_NW	output	TCELL2:PCLK14
PCLK14_SE	output	TCELL1:PCLK14
PCLK14_SW	output	TCELL0:PCLK14
PCLK15_NE	output	TCELL3:PCLK15
PCLK15_NW	output	TCELL2:PCLK15
PCLK15_SE	output	TCELL1:PCLK15
PCLK15_SW	output	TCELL0:PCLK15
PCLK16_NE	output	TCELL3:PCLK16
PCLK16_NW	output	TCELL2:PCLK16
PCLK16_SE	output	TCELL1:PCLK16
PCLK16_SW	output	TCELL0:PCLK16
PCLK17_NE	output	TCELL3:PCLK17
PCLK17_NW	output	TCELL2:PCLK17
PCLK17_SE	output	TCELL1:PCLK17
PCLK17_SW	output	TCELL0:PCLK17
PCLK18_NE	output	TCELL3:PCLK18
PCLK18_NW	output	TCELL2:PCLK18
PCLK18_SE	output	TCELL1:PCLK18
PCLK18_SW	output	TCELL0:PCLK18
PCLK19_NE	output	TCELL3:PCLK19
PCLK19_NW	output	TCELL2:PCLK19
PCLK19_SE	output	TCELL1:PCLK19
PCLK19_SW	output	TCELL0:PCLK19
PCLK1_NE	output	TCELL3:PCLK1
PCLK1_NW	output	TCELL2:PCLK1
PCLK1_SE	output	TCELL1:PCLK1
PCLK1_SW	output	TCELL0:PCLK1
PCLK2_NE	output	TCELL3:PCLK2
PCLK2_NW	output	TCELL2:PCLK2
PCLK2_SE	output	TCELL1:PCLK2
PCLK2_SW	output	TCELL0:PCLK2
PCLK3_NE	output	TCELL3:PCLK3
PCLK3_NW	output	TCELL2:PCLK3
PCLK3_SE	output	TCELL1:PCLK3
PCLK3_SW	output	TCELL0:PCLK3
PCLK4_NE	output	TCELL3:PCLK4
PCLK4_NW	output	TCELL2:PCLK4
PCLK4_SE	output	TCELL1:PCLK4
PCLK4_SW	output	TCELL0:PCLK4
PCLK5_NE	output	TCELL3:PCLK5
PCLK5_NW	output	TCELL2:PCLK5
PCLK5_SE	output	TCELL1:PCLK5
PCLK5_SW	output	TCELL0:PCLK5
PCLK6_NE	output	TCELL3:PCLK6
PCLK6_NW	output	TCELL2:PCLK6
PCLK6_SE	output	TCELL1:PCLK6
PCLK6_SW	output	TCELL0:PCLK6
PCLK7_NE	output	TCELL3:PCLK7
PCLK7_NW	output	TCELL2:PCLK7
PCLK7_SE	output	TCELL1:PCLK7
PCLK7_SW	output	TCELL0:PCLK7
PCLK8_NE	output	TCELL3:PCLK8
PCLK8_NW	output	TCELL2:PCLK8
PCLK8_SE	output	TCELL1:PCLK8
PCLK8_SW	output	TCELL0:PCLK8
PCLK9_NE	output	TCELL3:PCLK9
PCLK9_NW	output	TCELL2:PCLK9
PCLK9_SE	output	TCELL1:PCLK9
PCLK9_SW	output	TCELL0:PCLK9

Bel CLKTEST

ecp4 CLK_ROOT bel CLKTEST
Pin	Direction	Wires
TESTIN0	input	TCELL2:IMUX_A1
TESTIN1	input	TCELL2:IMUX_A2
TESTIN10	input	TCELL3:IMUX_B2
TESTIN11	input	TCELL3:IMUX_B3
TESTIN12	input	TCELL0:IMUX_A1
TESTIN13	input	TCELL0:IMUX_A2
TESTIN14	input	TCELL0:IMUX_B0
TESTIN15	input	TCELL0:IMUX_B1
TESTIN16	input	TCELL0:IMUX_B2
TESTIN17	input	TCELL0:IMUX_B3
TESTIN18	input	TCELL1:IMUX_A1
TESTIN19	input	TCELL1:IMUX_A2
TESTIN2	input	TCELL2:IMUX_B0
TESTIN20	input	TCELL1:IMUX_B0
TESTIN21	input	TCELL1:IMUX_B1
TESTIN22	input	TCELL1:IMUX_B2
TESTIN23	input	TCELL1:IMUX_B3
TESTIN3	input	TCELL2:IMUX_B1
TESTIN4	input	TCELL2:IMUX_B2
TESTIN5	input	TCELL2:IMUX_B3
TESTIN6	input	TCELL3:IMUX_A1
TESTIN7	input	TCELL3:IMUX_A2
TESTIN8	input	TCELL3:IMUX_B0
TESTIN9	input	TCELL3:IMUX_B1

Bel wires

ecp4 CLK_ROOT bel wires
Wire	Pins
TCELL0:PCLK0	CLK_ROOT.PCLK0_SW
TCELL0:PCLK1	CLK_ROOT.PCLK1_SW
TCELL0:PCLK2	CLK_ROOT.PCLK2_SW
TCELL0:PCLK3	CLK_ROOT.PCLK3_SW
TCELL0:PCLK4	CLK_ROOT.PCLK4_SW
TCELL0:PCLK5	CLK_ROOT.PCLK5_SW
TCELL0:PCLK6	CLK_ROOT.PCLK6_SW
TCELL0:PCLK7	CLK_ROOT.PCLK7_SW
TCELL0:PCLK8	CLK_ROOT.PCLK8_SW
TCELL0:PCLK9	CLK_ROOT.PCLK9_SW
TCELL0:PCLK10	CLK_ROOT.PCLK10_SW
TCELL0:PCLK11	CLK_ROOT.PCLK11_SW
TCELL0:PCLK12	CLK_ROOT.PCLK12_SW
TCELL0:PCLK13	CLK_ROOT.PCLK13_SW
TCELL0:PCLK14	CLK_ROOT.PCLK14_SW
TCELL0:PCLK15	CLK_ROOT.PCLK15_SW
TCELL0:PCLK16	CLK_ROOT.PCLK16_SW
TCELL0:PCLK17	CLK_ROOT.PCLK17_SW
TCELL0:PCLK18	CLK_ROOT.PCLK18_SW
TCELL0:PCLK19	CLK_ROOT.PCLK19_SW
TCELL0:IMUX_A0	DCC_SW0.CE
TCELL0:IMUX_A1	CLKTEST.TESTIN12
TCELL0:IMUX_A2	CLKTEST.TESTIN13
TCELL0:IMUX_B0	CLKTEST.TESTIN14
TCELL0:IMUX_B1	CLKTEST.TESTIN15
TCELL0:IMUX_B2	CLKTEST.TESTIN16
TCELL0:IMUX_B3	CLKTEST.TESTIN17
TCELL0:IMUX_D7	DCC_SW0.CLKI
TCELL1:PCLK0	CLK_ROOT.PCLK0_SE
TCELL1:PCLK1	CLK_ROOT.PCLK1_SE
TCELL1:PCLK2	CLK_ROOT.PCLK2_SE
TCELL1:PCLK3	CLK_ROOT.PCLK3_SE
TCELL1:PCLK4	CLK_ROOT.PCLK4_SE
TCELL1:PCLK5	CLK_ROOT.PCLK5_SE
TCELL1:PCLK6	CLK_ROOT.PCLK6_SE
TCELL1:PCLK7	CLK_ROOT.PCLK7_SE
TCELL1:PCLK8	CLK_ROOT.PCLK8_SE
TCELL1:PCLK9	CLK_ROOT.PCLK9_SE
TCELL1:PCLK10	CLK_ROOT.PCLK10_SE
TCELL1:PCLK11	CLK_ROOT.PCLK11_SE
TCELL1:PCLK12	CLK_ROOT.PCLK12_SE
TCELL1:PCLK13	CLK_ROOT.PCLK13_SE
TCELL1:PCLK14	CLK_ROOT.PCLK14_SE
TCELL1:PCLK15	CLK_ROOT.PCLK15_SE
TCELL1:PCLK16	CLK_ROOT.PCLK16_SE
TCELL1:PCLK17	CLK_ROOT.PCLK17_SE
TCELL1:PCLK18	CLK_ROOT.PCLK18_SE
TCELL1:PCLK19	CLK_ROOT.PCLK19_SE
TCELL1:IMUX_A0	DCC_SE0.CE
TCELL1:IMUX_A1	CLKTEST.TESTIN18
TCELL1:IMUX_A2	CLKTEST.TESTIN19
TCELL1:IMUX_B0	CLKTEST.TESTIN20
TCELL1:IMUX_B1	CLKTEST.TESTIN21
TCELL1:IMUX_B2	CLKTEST.TESTIN22
TCELL1:IMUX_B3	CLKTEST.TESTIN23
TCELL1:IMUX_D7	DCC_SE0.CLKI
TCELL2:PCLK0	CLK_ROOT.PCLK0_NW
TCELL2:PCLK1	CLK_ROOT.PCLK1_NW
TCELL2:PCLK2	CLK_ROOT.PCLK2_NW
TCELL2:PCLK3	CLK_ROOT.PCLK3_NW
TCELL2:PCLK4	CLK_ROOT.PCLK4_NW
TCELL2:PCLK5	CLK_ROOT.PCLK5_NW
TCELL2:PCLK6	CLK_ROOT.PCLK6_NW
TCELL2:PCLK7	CLK_ROOT.PCLK7_NW
TCELL2:PCLK8	CLK_ROOT.PCLK8_NW
TCELL2:PCLK9	CLK_ROOT.PCLK9_NW
TCELL2:PCLK10	CLK_ROOT.PCLK10_NW
TCELL2:PCLK11	CLK_ROOT.PCLK11_NW
TCELL2:PCLK12	CLK_ROOT.PCLK12_NW
TCELL2:PCLK13	CLK_ROOT.PCLK13_NW
TCELL2:PCLK14	CLK_ROOT.PCLK14_NW
TCELL2:PCLK15	CLK_ROOT.PCLK15_NW
TCELL2:PCLK16	CLK_ROOT.PCLK16_NW
TCELL2:PCLK17	CLK_ROOT.PCLK17_NW
TCELL2:PCLK18	CLK_ROOT.PCLK18_NW
TCELL2:PCLK19	CLK_ROOT.PCLK19_NW
TCELL2:IMUX_A0	DCC_NW0.CE
TCELL2:IMUX_A1	CLKTEST.TESTIN0
TCELL2:IMUX_A2	CLKTEST.TESTIN1
TCELL2:IMUX_A3	DCS0.SEL2
TCELL2:IMUX_A4	DCS0.SEL3
TCELL2:IMUX_A5	DCS1.SEL2
TCELL2:IMUX_A6	DCS1.SEL3
TCELL2:IMUX_B0	CLKTEST.TESTIN2
TCELL2:IMUX_B1	CLKTEST.TESTIN3
TCELL2:IMUX_B2	CLKTEST.TESTIN4
TCELL2:IMUX_B3	CLKTEST.TESTIN5
TCELL2:IMUX_B4	DCS0.SEL0
TCELL2:IMUX_B5	DCS0.SEL1
TCELL2:IMUX_B6	DCS1.SEL0
TCELL2:IMUX_B7	DCS1.SEL1
TCELL2:IMUX_C0	DCS0.MODESEL
TCELL2:IMUX_C1	DCS1.MODESEL
TCELL2:IMUX_D7	DCC_NW0.CLKI
TCELL3:PCLK0	CLK_ROOT.PCLK0_NE
TCELL3:PCLK1	CLK_ROOT.PCLK1_NE
TCELL3:PCLK2	CLK_ROOT.PCLK2_NE
TCELL3:PCLK3	CLK_ROOT.PCLK3_NE
TCELL3:PCLK4	CLK_ROOT.PCLK4_NE
TCELL3:PCLK5	CLK_ROOT.PCLK5_NE
TCELL3:PCLK6	CLK_ROOT.PCLK6_NE
TCELL3:PCLK7	CLK_ROOT.PCLK7_NE
TCELL3:PCLK8	CLK_ROOT.PCLK8_NE
TCELL3:PCLK9	CLK_ROOT.PCLK9_NE
TCELL3:PCLK10	CLK_ROOT.PCLK10_NE
TCELL3:PCLK11	CLK_ROOT.PCLK11_NE
TCELL3:PCLK12	CLK_ROOT.PCLK12_NE
TCELL3:PCLK13	CLK_ROOT.PCLK13_NE
TCELL3:PCLK14	CLK_ROOT.PCLK14_NE
TCELL3:PCLK15	CLK_ROOT.PCLK15_NE
TCELL3:PCLK16	CLK_ROOT.PCLK16_NE
TCELL3:PCLK17	CLK_ROOT.PCLK17_NE
TCELL3:PCLK18	CLK_ROOT.PCLK18_NE
TCELL3:PCLK19	CLK_ROOT.PCLK19_NE
TCELL3:IMUX_A0	DCC_NE0.CE
TCELL3:IMUX_A1	CLKTEST.TESTIN6
TCELL3:IMUX_A2	CLKTEST.TESTIN7
TCELL3:IMUX_B0	CLKTEST.TESTIN8
TCELL3:IMUX_B1	CLKTEST.TESTIN9
TCELL3:IMUX_B2	CLKTEST.TESTIN10
TCELL3:IMUX_B3	CLKTEST.TESTIN11
TCELL3:IMUX_D7	DCC_NE0.CLKI

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