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Configuration center

Tile CONFIG

Cells: 11

Bel START

ecp4 CONFIG bel START
PinDirectionWires
STARTCLKinputTCELL0:IMUX_CLK0_DELAY

Bel OSC

ecp4 CONFIG bel OSC
PinDirectionWires
OSCoutputTCELL6:OUT_Q0
STDBYinputTCELL0:IMUX_LSR1

Bel JTAG

ecp4 CONFIG bel JTAG
PinDirectionWires
JCE1outputTCELL0:OUT_Q1
JCE2outputTCELL0:OUT_Q3
JRSTNoutputTCELL0:OUT_F6
JRTI1outputTCELL0:OUT_Q2
JRTI2outputTCELL0:OUT_Q4
JSHIFToutputTCELL0:OUT_F7
JTCKoutputTCELL7:OUT_Q0
JTDIoutputTCELL0:OUT_F5
JTDO1inputTCELL0:IMUX_A4
JTDO2inputTCELL0:IMUX_B4
JUPDATEoutputTCELL0:OUT_Q0

Bel GSR

ecp4 CONFIG bel GSR
PinDirectionWires
CLKinputTCELL10:IMUX_CLK0_DELAY
GSRinputTCELL2:IMUX_C4

Bel SED

ecp4 CONFIG bel SED
PinDirectionWires
AUTODONEoutputTCELL1:OUT_F4
SEDCLKOUToutputTCELL9:OUT_Q0
SEDDONEoutputTCELL1:OUT_F6
SEDENABLEinputTCELL1:IMUX_LSR0
SEDERRoutputTCELL1:OUT_F7
SEDEXCLKinputTCELL1:IMUX_CLK0_DELAY
SEDFRCERRinputTCELL1:IMUX_A0
SEDINPROGoutputTCELL1:OUT_Q0
SEDSTARTinputTCELL1:IMUX_LSR1

Bel PCNTR

ecp4 CONFIG bel PCNTR
PinDirectionWires
CLKinputTCELL3:IMUX_CLK1_DELAY
CLRFLAGinputTCELL3:IMUX_B0
SFLAGoutputTCELL3:OUT_Q5
STDBYoutputTCELL3:OUT_Q3
STOPoutputTCELL3:OUT_Q4
USERSTDBYinputTCELL3:IMUX_LSR1
USERTIMEOUTinputTCELL3:IMUX_C0

Bel EFB

ecp4 CONFIG bel EFB
PinDirectionWires
I2C1IRQOoutputTCELL1:OUT_Q3
I2C2IRQOoutputTCELL1:OUT_Q4
I2C2SCLIinputTCELL1:IMUX_CLK1_DELAY
I2C2SCLOoutputTCELL1:OUT_Q1
I2C2SCLOENoutputTCELL1:OUT_Q5
I2C2SDAIinputTCELL1:IMUX_C0
I2C2SDAOoutputTCELL1:OUT_Q2
I2C2SDAOENoutputTCELL1:OUT_Q6
PCS0INToutputTCELL5:OUT_F0
PCS1INToutputTCELL5:OUT_F1
PCS2INToutputTCELL5:OUT_F2
PCS3INToutputTCELL5:OUT_F3
PCS4INToutputTCELL5:OUT_F4
SMIADOoutputTCELL5:OUT_Q0
SMICLKOoutputTCELL8:OUT_Q0
SMIRDATAIinputTCELL5:IMUX_A0
SMIRDOoutputTCELL5:OUT_Q2
SMIRSTNOoutputTCELL5:OUT_Q3
SMIWDATAOoutputTCELL5:OUT_Q4
SMIWROoutputTCELL5:OUT_Q5
SPIIRQOoutputTCELL3:OUT_Q0
SPIMCSN1outputTCELL2:OUT_Q2
SPIMCSN2outputTCELL2:OUT_Q3
SPIMCSN3outputTCELL2:OUT_Q4
SPIMCSN4outputTCELL3:OUT_F0
SPIMCSN5outputTCELL3:OUT_F1
SPIMCSN6outputTCELL3:OUT_F2
SPIMCSN7outputTCELL3:OUT_F3
SPISCSNinputTCELL3:IMUX_CE0
TCCLKIinputTCELL3:IMUX_CLK0_DELAY
TCICinputTCELL3:IMUX_A0
TCINToutputTCELL3:OUT_Q1
TCOCoutputTCELL3:OUT_Q2
TCRSTNinputTCELL3:IMUX_LSR0
WBACKOoutputTCELL2:OUT_Q0
WBADRI0inputTCELL1:IMUX_A2
WBADRI1inputTCELL1:IMUX_B2
WBADRI10inputTCELL1:IMUX_C4
WBADRI11inputTCELL1:IMUX_D4
WBADRI12inputTCELL1:IMUX_A5
WBADRI13inputTCELL1:IMUX_B5
WBADRI14inputTCELL1:IMUX_C5
WBADRI15inputTCELL1:IMUX_D5
WBADRI2inputTCELL1:IMUX_C2
WBADRI3inputTCELL1:IMUX_D2
WBADRI4inputTCELL1:IMUX_A3
WBADRI5inputTCELL1:IMUX_B3
WBADRI6inputTCELL1:IMUX_C3
WBADRI7inputTCELL1:IMUX_D3
WBADRI8inputTCELL1:IMUX_A4
WBADRI9inputTCELL1:IMUX_B4
WBCFGINToutputTCELL2:OUT_Q1
WBCLKIinputTCELL2:IMUX_CLK1_DELAY
WBCYCIinputTCELL2:IMUX_A4
WBDATI0inputTCELL2:IMUX_A0
WBDATI1inputTCELL2:IMUX_B0
WBDATI2inputTCELL2:IMUX_C0
WBDATI3inputTCELL2:IMUX_D0
WBDATI4inputTCELL2:IMUX_A2
WBDATI5inputTCELL2:IMUX_B2
WBDATI6inputTCELL2:IMUX_C2
WBDATI7inputTCELL2:IMUX_D2
WBDATO0outputTCELL2:OUT_F0
WBDATO1outputTCELL2:OUT_F1
WBDATO2outputTCELL2:OUT_F2
WBDATO3outputTCELL2:OUT_F3
WBDATO4outputTCELL2:OUT_F4
WBDATO5outputTCELL2:OUT_F5
WBDATO6outputTCELL2:OUT_F6
WBDATO7outputTCELL2:OUT_F7
WBERROoutputTCELL2:OUT_Q5
WBRSTIinputTCELL2:IMUX_CE0
WBRTYOoutputTCELL2:OUT_Q6
WBSTBIinputTCELL2:IMUX_LSR1
WBWEIinputTCELL2:IMUX_B4

Bel wires

ecp4 CONFIG bel wires
WirePins
TCELL0:IMUX_A4JTAG.JTDO1
TCELL0:IMUX_B4JTAG.JTDO2
TCELL0:IMUX_LSR1OSC.STDBY
TCELL0:IMUX_CLK0_DELAYSTART.STARTCLK
TCELL0:OUT_F5JTAG.JTDI
TCELL0:OUT_F6JTAG.JRSTN
TCELL0:OUT_F7JTAG.JSHIFT
TCELL0:OUT_Q0JTAG.JUPDATE
TCELL0:OUT_Q1JTAG.JCE1
TCELL0:OUT_Q2JTAG.JRTI1
TCELL0:OUT_Q3JTAG.JCE2
TCELL0:OUT_Q4JTAG.JRTI2
TCELL1:IMUX_A0SED.SEDFRCERR
TCELL1:IMUX_A2EFB.WBADRI0
TCELL1:IMUX_A3EFB.WBADRI4
TCELL1:IMUX_A4EFB.WBADRI8
TCELL1:IMUX_A5EFB.WBADRI12
TCELL1:IMUX_B2EFB.WBADRI1
TCELL1:IMUX_B3EFB.WBADRI5
TCELL1:IMUX_B4EFB.WBADRI9
TCELL1:IMUX_B5EFB.WBADRI13
TCELL1:IMUX_C0EFB.I2C2SDAI
TCELL1:IMUX_C2EFB.WBADRI2
TCELL1:IMUX_C3EFB.WBADRI6
TCELL1:IMUX_C4EFB.WBADRI10
TCELL1:IMUX_C5EFB.WBADRI14
TCELL1:IMUX_D2EFB.WBADRI3
TCELL1:IMUX_D3EFB.WBADRI7
TCELL1:IMUX_D4EFB.WBADRI11
TCELL1:IMUX_D5EFB.WBADRI15
TCELL1:IMUX_LSR0SED.SEDENABLE
TCELL1:IMUX_LSR1SED.SEDSTART
TCELL1:IMUX_CLK0_DELAYSED.SEDEXCLK
TCELL1:IMUX_CLK1_DELAYEFB.I2C2SCLI
TCELL1:OUT_F4SED.AUTODONE
TCELL1:OUT_F6SED.SEDDONE
TCELL1:OUT_F7SED.SEDERR
TCELL1:OUT_Q0SED.SEDINPROG
TCELL1:OUT_Q1EFB.I2C2SCLO
TCELL1:OUT_Q2EFB.I2C2SDAO
TCELL1:OUT_Q3EFB.I2C1IRQO
TCELL1:OUT_Q4EFB.I2C2IRQO
TCELL1:OUT_Q5EFB.I2C2SCLOEN
TCELL1:OUT_Q6EFB.I2C2SDAOEN
TCELL2:IMUX_A0EFB.WBDATI0
TCELL2:IMUX_A2EFB.WBDATI4
TCELL2:IMUX_A4EFB.WBCYCI
TCELL2:IMUX_B0EFB.WBDATI1
TCELL2:IMUX_B2EFB.WBDATI5
TCELL2:IMUX_B4EFB.WBWEI
TCELL2:IMUX_C0EFB.WBDATI2
TCELL2:IMUX_C2EFB.WBDATI6
TCELL2:IMUX_C4GSR.GSR
TCELL2:IMUX_D0EFB.WBDATI3
TCELL2:IMUX_D2EFB.WBDATI7
TCELL2:IMUX_LSR1EFB.WBSTBI
TCELL2:IMUX_CLK1_DELAYEFB.WBCLKI
TCELL2:IMUX_CE0EFB.WBRSTI
TCELL2:OUT_F0EFB.WBDATO0
TCELL2:OUT_F1EFB.WBDATO1
TCELL2:OUT_F2EFB.WBDATO2
TCELL2:OUT_F3EFB.WBDATO3
TCELL2:OUT_F4EFB.WBDATO4
TCELL2:OUT_F5EFB.WBDATO5
TCELL2:OUT_F6EFB.WBDATO6
TCELL2:OUT_F7EFB.WBDATO7
TCELL2:OUT_Q0EFB.WBACKO
TCELL2:OUT_Q1EFB.WBCFGINT
TCELL2:OUT_Q2EFB.SPIMCSN1
TCELL2:OUT_Q3EFB.SPIMCSN2
TCELL2:OUT_Q4EFB.SPIMCSN3
TCELL2:OUT_Q5EFB.WBERRO
TCELL2:OUT_Q6EFB.WBRTYO
TCELL3:IMUX_A0EFB.TCIC
TCELL3:IMUX_B0PCNTR.CLRFLAG
TCELL3:IMUX_C0PCNTR.USERTIMEOUT
TCELL3:IMUX_LSR0EFB.TCRSTN
TCELL3:IMUX_LSR1PCNTR.USERSTDBY
TCELL3:IMUX_CLK0_DELAYEFB.TCCLKI
TCELL3:IMUX_CLK1_DELAYPCNTR.CLK
TCELL3:IMUX_CE0EFB.SPISCSN
TCELL3:OUT_F0EFB.SPIMCSN4
TCELL3:OUT_F1EFB.SPIMCSN5
TCELL3:OUT_F2EFB.SPIMCSN6
TCELL3:OUT_F3EFB.SPIMCSN7
TCELL3:OUT_Q0EFB.SPIIRQO
TCELL3:OUT_Q1EFB.TCINT
TCELL3:OUT_Q2EFB.TCOC
TCELL3:OUT_Q3PCNTR.STDBY
TCELL3:OUT_Q4PCNTR.STOP
TCELL3:OUT_Q5PCNTR.SFLAG
TCELL5:IMUX_A0EFB.SMIRDATAI
TCELL5:OUT_F0EFB.PCS0INT
TCELL5:OUT_F1EFB.PCS1INT
TCELL5:OUT_F2EFB.PCS2INT
TCELL5:OUT_F3EFB.PCS3INT
TCELL5:OUT_F4EFB.PCS4INT
TCELL5:OUT_Q0EFB.SMIADO
TCELL5:OUT_Q2EFB.SMIRDO
TCELL5:OUT_Q3EFB.SMIRSTNO
TCELL5:OUT_Q4EFB.SMIWDATAO
TCELL5:OUT_Q5EFB.SMIWRO
TCELL6:OUT_Q0OSC.OSC
TCELL7:OUT_Q0JTAG.JTCK
TCELL8:OUT_Q0EFB.SMICLKO
TCELL9:OUT_Q0SED.SEDCLKOUT
TCELL10:IMUX_CLK0_DELAYGSR.CLK