DSP
Tile DSP
Cells: 9
Bel DSP0
| Pin | Direction | Wires |
|---|---|---|
| A0_0 | input | TCELL0:IMUX_D0 |
| A0_1 | input | TCELL2:IMUX_D2 |
| A10_0 | input | TCELL1:IMUX_D2 |
| A10_1 | input | TCELL3:IMUX_D4 |
| A11_0 | input | TCELL1:IMUX_B3 |
| A11_1 | input | TCELL3:IMUX_B5 |
| A12_0 | input | TCELL1:IMUX_D4 |
| A12_1 | input | TCELL3:IMUX_D6 |
| A13_0 | input | TCELL1:IMUX_B5 |
| A13_1 | input | TCELL3:IMUX_B7 |
| A14_0 | input | TCELL1:IMUX_D6 |
| A14_1 | input | TCELL4:IMUX_D0 |
| A15_0 | input | TCELL1:IMUX_B7 |
| A15_1 | input | TCELL4:IMUX_B1 |
| A16_0 | input | TCELL2:IMUX_D0 |
| A16_1 | input | TCELL4:IMUX_D2 |
| A17_0 | input | TCELL2:IMUX_B1 |
| A17_1 | input | TCELL4:IMUX_B3 |
| A1_0 | input | TCELL0:IMUX_B1 |
| A1_1 | input | TCELL2:IMUX_B3 |
| A2_0 | input | TCELL0:IMUX_D2 |
| A2_1 | input | TCELL2:IMUX_D4 |
| A3_0 | input | TCELL0:IMUX_B3 |
| A3_1 | input | TCELL2:IMUX_B5 |
| A4_0 | input | TCELL0:IMUX_D4 |
| A4_1 | input | TCELL2:IMUX_D6 |
| A5_0 | input | TCELL0:IMUX_B5 |
| A5_1 | input | TCELL2:IMUX_B7 |
| A6_0 | input | TCELL0:IMUX_D6 |
| A6_1 | input | TCELL3:IMUX_D0 |
| A7_0 | input | TCELL0:IMUX_B7 |
| A7_1 | input | TCELL3:IMUX_B1 |
| A8_0 | input | TCELL1:IMUX_D0 |
| A8_1 | input | TCELL3:IMUX_D2 |
| A9_0 | input | TCELL1:IMUX_B1 |
| A9_1 | input | TCELL3:IMUX_B3 |
| B0_0 | input | TCELL0:IMUX_D1 |
| B0_1 | input | TCELL2:IMUX_D3 |
| B10_0 | input | TCELL1:IMUX_D3 |
| B10_1 | input | TCELL3:IMUX_D5 |
| B11_0 | input | TCELL1:IMUX_B2 |
| B11_1 | input | TCELL3:IMUX_B4 |
| B12_0 | input | TCELL1:IMUX_D5 |
| B12_1 | input | TCELL3:IMUX_D7 |
| B13_0 | input | TCELL1:IMUX_B4 |
| B13_1 | input | TCELL3:IMUX_B6 |
| B14_0 | input | TCELL1:IMUX_D7 |
| B14_1 | input | TCELL4:IMUX_D1 |
| B15_0 | input | TCELL1:IMUX_B6 |
| B15_1 | input | TCELL4:IMUX_B0 |
| B16_0 | input | TCELL2:IMUX_D1 |
| B16_1 | input | TCELL4:IMUX_D3 |
| B17_0 | input | TCELL2:IMUX_B0 |
| B17_1 | input | TCELL4:IMUX_B2 |
| B1_0 | input | TCELL0:IMUX_B0 |
| B1_1 | input | TCELL2:IMUX_B2 |
| B2_0 | input | TCELL0:IMUX_D3 |
| B2_1 | input | TCELL2:IMUX_D5 |
| B3_0 | input | TCELL0:IMUX_B2 |
| B3_1 | input | TCELL2:IMUX_B4 |
| B4_0 | input | TCELL0:IMUX_D5 |
| B4_1 | input | TCELL2:IMUX_D7 |
| B5_0 | input | TCELL0:IMUX_B4 |
| B5_1 | input | TCELL2:IMUX_B6 |
| B6_0 | input | TCELL0:IMUX_D7 |
| B6_1 | input | TCELL3:IMUX_D1 |
| B7_0 | input | TCELL0:IMUX_B6 |
| B7_1 | input | TCELL3:IMUX_B0 |
| B8_0 | input | TCELL1:IMUX_D1 |
| B8_1 | input | TCELL3:IMUX_D3 |
| B9_0 | input | TCELL1:IMUX_B0 |
| B9_1 | input | TCELL3:IMUX_B2 |
| C0 | input | TCELL0:IMUX_C4 |
| C1 | input | TCELL0:IMUX_A5 |
| C10 | input | TCELL1:IMUX_C6 |
| C11 | input | TCELL1:IMUX_A7 |
| C12 | input | TCELL1:IMUX_C0 |
| C13 | input | TCELL1:IMUX_A1 |
| C14 | input | TCELL1:IMUX_C2 |
| C15 | input | TCELL1:IMUX_A3 |
| C16 | input | TCELL2:IMUX_C4 |
| C17 | input | TCELL2:IMUX_A5 |
| C18 | input | TCELL2:IMUX_C6 |
| C19 | input | TCELL2:IMUX_A7 |
| C2 | input | TCELL0:IMUX_C6 |
| C20 | input | TCELL2:IMUX_C0 |
| C21 | input | TCELL2:IMUX_A1 |
| C22 | input | TCELL2:IMUX_C2 |
| C23 | input | TCELL2:IMUX_A3 |
| C24 | input | TCELL3:IMUX_C4 |
| C25 | input | TCELL3:IMUX_A5 |
| C26 | input | TCELL3:IMUX_C6 |
| C27 | input | TCELL3:IMUX_A7 |
| C28 | input | TCELL3:IMUX_C0 |
| C29 | input | TCELL3:IMUX_A1 |
| C3 | input | TCELL0:IMUX_A7 |
| C30 | input | TCELL3:IMUX_C2 |
| C31 | input | TCELL3:IMUX_A3 |
| C32 | input | TCELL0:IMUX_C5 |
| C33 | input | TCELL0:IMUX_A4 |
| C34 | input | TCELL0:IMUX_C7 |
| C35 | input | TCELL0:IMUX_A6 |
| C36 | input | TCELL0:IMUX_C1 |
| C37 | input | TCELL0:IMUX_A0 |
| C38 | input | TCELL0:IMUX_C3 |
| C39 | input | TCELL0:IMUX_A2 |
| C4 | input | TCELL0:IMUX_C0 |
| C40 | input | TCELL1:IMUX_C5 |
| C41 | input | TCELL1:IMUX_A4 |
| C42 | input | TCELL1:IMUX_C7 |
| C43 | input | TCELL1:IMUX_A6 |
| C44 | input | TCELL1:IMUX_C1 |
| C45 | input | TCELL1:IMUX_A0 |
| C46 | input | TCELL1:IMUX_C3 |
| C47 | input | TCELL1:IMUX_A2 |
| C48 | input | TCELL2:IMUX_C5 |
| C49 | input | TCELL2:IMUX_A4 |
| C5 | input | TCELL0:IMUX_A1 |
| C50 | input | TCELL2:IMUX_C7 |
| C51 | input | TCELL2:IMUX_A6 |
| C52 | input | TCELL2:IMUX_C1 |
| C53 | input | TCELL2:IMUX_A0 |
| C6 | input | TCELL0:IMUX_C2 |
| C7 | input | TCELL0:IMUX_A3 |
| C8 | input | TCELL1:IMUX_C4 |
| C9 | input | TCELL1:IMUX_A5 |
| CE0 | input | TCELL1:IMUX_CE0 |
| CE1 | input | TCELL1:IMUX_CE1 |
| CE2 | input | TCELL2:IMUX_CE0 |
| CE3 | input | TCELL2:IMUX_CE1 |
| CLK0 | input | TCELL1:IMUX_CLK0 |
| CLK1 | input | TCELL1:IMUX_CLK1 |
| CLK2 | input | TCELL2:IMUX_CLK0 |
| CLK3 | input | TCELL2:IMUX_CLK1 |
| EQOM | output | TCELL2:OUT_Q7 |
| EQPAT | output | TCELL2:OUT_Q6 |
| EQPATB | output | TCELL2:OUT_Q5 |
| EQZ | output | TCELL3:OUT_Q1 |
| EQZM | output | TCELL3:OUT_Q0 |
| OP0 | input | TCELL0:IMUX_CE1 |
| OP1 | input | TCELL0:IMUX_CE2 |
| OP10 | input | TCELL3:IMUX_CE3 |
| OP2 | input | TCELL0:IMUX_CE3 |
| OP3 | input | TCELL1:IMUX_CE2 |
| OP4 | input | TCELL1:IMUX_CE3 |
| OP5 | input | TCELL2:IMUX_CE2 |
| OP6 | input | TCELL2:IMUX_CE3 |
| OP7 | input | TCELL3:IMUX_CE0 |
| OP8 | input | TCELL3:IMUX_CE1 |
| OP9 | input | TCELL3:IMUX_CE2 |
| OPPRE_0 | input | TCELL3:IMUX_A4 |
| OPPRE_1 | input | TCELL3:IMUX_A6 |
| OVER | output | TCELL2:OUT_Q4 |
| OVERUNDER | output | TCELL2:OUT_Q2 |
| P0_0 | output | TCELL0:OUT_F0 |
| P0_1 | output | TCELL0:OUT_Q0 |
| P10_0 | output | TCELL1:OUT_F2 |
| P10_1 | output | TCELL1:OUT_Q2 |
| P11_0 | output | TCELL1:OUT_F3 |
| P11_1 | output | TCELL1:OUT_Q3 |
| P12_0 | output | TCELL1:OUT_F4 |
| P12_1 | output | TCELL1:OUT_Q4 |
| P13_0 | output | TCELL1:OUT_F5 |
| P13_1 | output | TCELL1:OUT_Q5 |
| P14_0 | output | TCELL1:OUT_F6 |
| P14_1 | output | TCELL1:OUT_Q6 |
| P15_0 | output | TCELL1:OUT_F7 |
| P15_1 | output | TCELL1:OUT_Q7 |
| P16_0 | output | TCELL2:OUT_F0 |
| P16_1 | output | TCELL2:OUT_Q0 |
| P17_0 | output | TCELL2:OUT_F1 |
| P17_1 | output | TCELL2:OUT_Q1 |
| P18_0 | output | TCELL2:OUT_F2 |
| P18_1 | output | TCELL2:OUT_Q2 |
| P19_0 | output | TCELL2:OUT_F3 |
| P19_1 | output | TCELL2:OUT_Q3 |
| P1_0 | output | TCELL0:OUT_F1 |
| P1_1 | output | TCELL0:OUT_Q1 |
| P20_0 | output | TCELL2:OUT_F4 |
| P20_1 | output | TCELL2:OUT_Q4 |
| P21_0 | output | TCELL2:OUT_F5 |
| P21_1 | output | TCELL2:OUT_Q5 |
| P22_0 | output | TCELL2:OUT_F6 |
| P22_1 | output | TCELL2:OUT_Q6 |
| P23_0 | output | TCELL2:OUT_F7 |
| P23_1 | output | TCELL2:OUT_Q7 |
| P24_0 | output | TCELL3:OUT_F0 |
| P24_1 | output | TCELL3:OUT_Q0 |
| P25_0 | output | TCELL3:OUT_F1 |
| P25_1 | output | TCELL3:OUT_Q1 |
| P26_0 | output | TCELL3:OUT_F2 |
| P26_1 | output | TCELL3:OUT_Q2 |
| P27_0 | output | TCELL3:OUT_F3 |
| P27_1 | output | TCELL3:OUT_Q3 |
| P28_0 | output | TCELL3:OUT_F4 |
| P28_1 | output | TCELL3:OUT_Q4 |
| P29_0 | output | TCELL3:OUT_F5 |
| P29_1 | output | TCELL3:OUT_Q5 |
| P2_0 | output | TCELL0:OUT_F2 |
| P2_1 | output | TCELL0:OUT_Q2 |
| P30_0 | output | TCELL3:OUT_F6 |
| P30_1 | output | TCELL3:OUT_Q6 |
| P31_0 | output | TCELL3:OUT_F7 |
| P31_1 | output | TCELL3:OUT_Q7 |
| P32_0 | output | TCELL4:OUT_F0 |
| P32_1 | output | TCELL4:OUT_Q0 |
| P33_0 | output | TCELL4:OUT_F1 |
| P33_1 | output | TCELL4:OUT_Q1 |
| P34_0 | output | TCELL4:OUT_F2 |
| P34_1 | output | TCELL4:OUT_Q2 |
| P35_0 | output | TCELL4:OUT_F3 |
| P35_1 | output | TCELL4:OUT_Q3 |
| P3_0 | output | TCELL0:OUT_F3 |
| P3_1 | output | TCELL0:OUT_Q3 |
| P4_0 | output | TCELL0:OUT_F4 |
| P4_1 | output | TCELL0:OUT_Q4 |
| P5_0 | output | TCELL0:OUT_F5 |
| P5_1 | output | TCELL0:OUT_Q5 |
| P6_0 | output | TCELL0:OUT_F6 |
| P6_1 | output | TCELL0:OUT_Q6 |
| P7_0 | output | TCELL0:OUT_F7 |
| P7_1 | output | TCELL0:OUT_Q7 |
| P8_0 | output | TCELL1:OUT_F0 |
| P8_1 | output | TCELL1:OUT_Q0 |
| P9_0 | output | TCELL1:OUT_F1 |
| P9_1 | output | TCELL1:OUT_Q1 |
| R0 | output | TCELL0:OUT_F0 |
| R1 | output | TCELL0:OUT_F1 |
| R10 | output | TCELL1:OUT_F2 |
| R11 | output | TCELL1:OUT_F3 |
| R12 | output | TCELL1:OUT_F4 |
| R13 | output | TCELL1:OUT_F5 |
| R14 | output | TCELL1:OUT_F6 |
| R15 | output | TCELL1:OUT_F7 |
| R16 | output | TCELL2:OUT_F0 |
| R17 | output | TCELL2:OUT_F1 |
| R18 | output | TCELL0:OUT_Q0 |
| R19 | output | TCELL0:OUT_Q1 |
| R2 | output | TCELL0:OUT_F2 |
| R20 | output | TCELL0:OUT_Q2 |
| R21 | output | TCELL0:OUT_Q3 |
| R22 | output | TCELL0:OUT_Q4 |
| R23 | output | TCELL0:OUT_Q5 |
| R24 | output | TCELL0:OUT_Q6 |
| R25 | output | TCELL0:OUT_Q7 |
| R26 | output | TCELL1:OUT_Q0 |
| R27 | output | TCELL2:OUT_F2 |
| R28 | output | TCELL2:OUT_F3 |
| R29 | output | TCELL2:OUT_F4 |
| R3 | output | TCELL0:OUT_F3 |
| R30 | output | TCELL2:OUT_F5 |
| R31 | output | TCELL2:OUT_F6 |
| R32 | output | TCELL2:OUT_F7 |
| R33 | output | TCELL3:OUT_F0 |
| R34 | output | TCELL3:OUT_F1 |
| R35 | output | TCELL3:OUT_F2 |
| R36 | output | TCELL3:OUT_F3 |
| R37 | output | TCELL3:OUT_F4 |
| R38 | output | TCELL3:OUT_F5 |
| R39 | output | TCELL3:OUT_F6 |
| R4 | output | TCELL0:OUT_F4 |
| R40 | output | TCELL3:OUT_F7 |
| R41 | output | TCELL4:OUT_F0 |
| R42 | output | TCELL4:OUT_F1 |
| R43 | output | TCELL4:OUT_F2 |
| R44 | output | TCELL4:OUT_F3 |
| R45 | output | TCELL1:OUT_Q1 |
| R46 | output | TCELL1:OUT_Q2 |
| R47 | output | TCELL1:OUT_Q3 |
| R48 | output | TCELL1:OUT_Q4 |
| R49 | output | TCELL1:OUT_Q5 |
| R5 | output | TCELL0:OUT_F5 |
| R50 | output | TCELL1:OUT_Q6 |
| R51 | output | TCELL1:OUT_Q7 |
| R52 | output | TCELL2:OUT_Q0 |
| R53 | output | TCELL2:OUT_Q1 |
| R6 | output | TCELL0:OUT_F6 |
| R7 | output | TCELL0:OUT_F7 |
| R8 | output | TCELL1:OUT_F0 |
| R9 | output | TCELL1:OUT_F1 |
| RST0 | input | TCELL3:IMUX_LSR0 |
| RST1 | input | TCELL3:IMUX_LSR1 |
| RST2 | input | TCELL5:IMUX_LSR0 |
| RST3 | input | TCELL5:IMUX_LSR1 |
| SIGNEDA_0 | input | TCELL1:IMUX_LSR1 |
| SIGNEDA_1 | input | TCELL4:IMUX_CE0 |
| SIGNEDB_0 | input | TCELL0:IMUX_CE0 |
| SIGNEDB_1 | input | TCELL4:IMUX_CE1 |
| SOURCEA_0 | input | TCELL0:IMUX_LSR0 |
| SOURCEA_1 | input | TCELL2:IMUX_LSR0 |
| SOURCEB_0 | input | TCELL0:IMUX_LSR1 |
| SOURCEB_1 | input | TCELL2:IMUX_LSR1 |
| SROA0 | output | TCELL2:OUT_Q2 |
| SROA1 | output | TCELL2:OUT_Q3 |
| SROA10 | output | TCELL3:OUT_Q4 |
| SROA11 | output | TCELL3:OUT_Q5 |
| SROA12 | output | TCELL3:OUT_Q6 |
| SROA13 | output | TCELL3:OUT_Q7 |
| SROA14 | output | TCELL4:OUT_Q0 |
| SROA15 | output | TCELL4:OUT_Q1 |
| SROA16 | output | TCELL4:OUT_Q2 |
| SROA17 | output | TCELL4:OUT_Q3 |
| SROA2 | output | TCELL2:OUT_Q4 |
| SROA3 | output | TCELL2:OUT_Q5 |
| SROA4 | output | TCELL2:OUT_Q6 |
| SROA5 | output | TCELL2:OUT_Q7 |
| SROA6 | output | TCELL3:OUT_Q0 |
| SROA7 | output | TCELL3:OUT_Q1 |
| SROA8 | output | TCELL3:OUT_Q2 |
| SROA9 | output | TCELL3:OUT_Q3 |
| UNDER | output | TCELL2:OUT_Q3 |
Bel DSP1
| Pin | Direction | Wires |
|---|---|---|
| A0_0 | input | TCELL4:IMUX_D4 |
| A0_1 | input | TCELL6:IMUX_D6 |
| A10_0 | input | TCELL5:IMUX_D6 |
| A10_1 | input | TCELL8:IMUX_D0 |
| A11_0 | input | TCELL5:IMUX_B7 |
| A11_1 | input | TCELL8:IMUX_B1 |
| A12_0 | input | TCELL6:IMUX_D0 |
| A12_1 | input | TCELL8:IMUX_D2 |
| A13_0 | input | TCELL6:IMUX_B1 |
| A13_1 | input | TCELL8:IMUX_B3 |
| A14_0 | input | TCELL6:IMUX_D2 |
| A14_1 | input | TCELL8:IMUX_D4 |
| A15_0 | input | TCELL6:IMUX_B3 |
| A15_1 | input | TCELL8:IMUX_B5 |
| A16_0 | input | TCELL6:IMUX_D4 |
| A16_1 | input | TCELL8:IMUX_D6 |
| A17_0 | input | TCELL6:IMUX_B5 |
| A17_1 | input | TCELL8:IMUX_B7 |
| A1_0 | input | TCELL4:IMUX_B5 |
| A1_1 | input | TCELL6:IMUX_B7 |
| A2_0 | input | TCELL4:IMUX_D6 |
| A2_1 | input | TCELL7:IMUX_D0 |
| A3_0 | input | TCELL4:IMUX_B7 |
| A3_1 | input | TCELL7:IMUX_B1 |
| A4_0 | input | TCELL5:IMUX_D0 |
| A4_1 | input | TCELL7:IMUX_D2 |
| A5_0 | input | TCELL5:IMUX_B1 |
| A5_1 | input | TCELL7:IMUX_B3 |
| A6_0 | input | TCELL5:IMUX_D2 |
| A6_1 | input | TCELL7:IMUX_D4 |
| A7_0 | input | TCELL5:IMUX_B3 |
| A7_1 | input | TCELL7:IMUX_B5 |
| A8_0 | input | TCELL5:IMUX_D4 |
| A8_1 | input | TCELL7:IMUX_D6 |
| A9_0 | input | TCELL5:IMUX_B5 |
| A9_1 | input | TCELL7:IMUX_B7 |
| B0_0 | input | TCELL4:IMUX_D5 |
| B0_1 | input | TCELL6:IMUX_D7 |
| B10_0 | input | TCELL5:IMUX_D7 |
| B10_1 | input | TCELL8:IMUX_D1 |
| B11_0 | input | TCELL5:IMUX_B6 |
| B11_1 | input | TCELL8:IMUX_B0 |
| B12_0 | input | TCELL6:IMUX_D1 |
| B12_1 | input | TCELL8:IMUX_D3 |
| B13_0 | input | TCELL6:IMUX_B0 |
| B13_1 | input | TCELL8:IMUX_B2 |
| B14_0 | input | TCELL6:IMUX_D3 |
| B14_1 | input | TCELL8:IMUX_D5 |
| B15_0 | input | TCELL6:IMUX_B2 |
| B15_1 | input | TCELL8:IMUX_B4 |
| B16_0 | input | TCELL6:IMUX_D5 |
| B16_1 | input | TCELL8:IMUX_D7 |
| B17_0 | input | TCELL6:IMUX_B4 |
| B17_1 | input | TCELL8:IMUX_B6 |
| B1_0 | input | TCELL4:IMUX_B4 |
| B1_1 | input | TCELL6:IMUX_B6 |
| B2_0 | input | TCELL4:IMUX_D7 |
| B2_1 | input | TCELL7:IMUX_D1 |
| B3_0 | input | TCELL4:IMUX_B6 |
| B3_1 | input | TCELL7:IMUX_B0 |
| B4_0 | input | TCELL5:IMUX_D1 |
| B4_1 | input | TCELL7:IMUX_D3 |
| B5_0 | input | TCELL5:IMUX_B0 |
| B5_1 | input | TCELL7:IMUX_B2 |
| B6_0 | input | TCELL5:IMUX_D3 |
| B6_1 | input | TCELL7:IMUX_D5 |
| B7_0 | input | TCELL5:IMUX_B2 |
| B7_1 | input | TCELL7:IMUX_B4 |
| B8_0 | input | TCELL5:IMUX_D5 |
| B8_1 | input | TCELL7:IMUX_D7 |
| B9_0 | input | TCELL5:IMUX_B4 |
| B9_1 | input | TCELL7:IMUX_B6 |
| C0 | input | TCELL5:IMUX_C4 |
| C1 | input | TCELL5:IMUX_A5 |
| C10 | input | TCELL6:IMUX_C6 |
| C11 | input | TCELL6:IMUX_A7 |
| C12 | input | TCELL6:IMUX_C0 |
| C13 | input | TCELL6:IMUX_A1 |
| C14 | input | TCELL6:IMUX_C2 |
| C15 | input | TCELL6:IMUX_A3 |
| C16 | input | TCELL7:IMUX_C4 |
| C17 | input | TCELL7:IMUX_A5 |
| C18 | input | TCELL7:IMUX_C6 |
| C19 | input | TCELL7:IMUX_A7 |
| C2 | input | TCELL5:IMUX_C6 |
| C20 | input | TCELL7:IMUX_C0 |
| C21 | input | TCELL7:IMUX_A1 |
| C22 | input | TCELL7:IMUX_C2 |
| C23 | input | TCELL7:IMUX_A3 |
| C24 | input | TCELL8:IMUX_C4 |
| C25 | input | TCELL8:IMUX_A5 |
| C26 | input | TCELL8:IMUX_C6 |
| C27 | input | TCELL8:IMUX_A7 |
| C28 | input | TCELL8:IMUX_C0 |
| C29 | input | TCELL8:IMUX_A1 |
| C3 | input | TCELL5:IMUX_A7 |
| C30 | input | TCELL8:IMUX_C2 |
| C31 | input | TCELL8:IMUX_A3 |
| C32 | input | TCELL5:IMUX_C5 |
| C33 | input | TCELL5:IMUX_A4 |
| C34 | input | TCELL5:IMUX_C7 |
| C35 | input | TCELL5:IMUX_A6 |
| C36 | input | TCELL5:IMUX_C1 |
| C37 | input | TCELL5:IMUX_A0 |
| C38 | input | TCELL5:IMUX_C3 |
| C39 | input | TCELL5:IMUX_A2 |
| C4 | input | TCELL5:IMUX_C0 |
| C40 | input | TCELL6:IMUX_C5 |
| C41 | input | TCELL6:IMUX_A4 |
| C42 | input | TCELL6:IMUX_C7 |
| C43 | input | TCELL6:IMUX_A6 |
| C44 | input | TCELL6:IMUX_C1 |
| C45 | input | TCELL6:IMUX_A0 |
| C46 | input | TCELL6:IMUX_C3 |
| C47 | input | TCELL6:IMUX_A2 |
| C48 | input | TCELL7:IMUX_C5 |
| C49 | input | TCELL7:IMUX_A4 |
| C5 | input | TCELL5:IMUX_A1 |
| C50 | input | TCELL7:IMUX_C7 |
| C51 | input | TCELL7:IMUX_A6 |
| C52 | input | TCELL7:IMUX_C1 |
| C53 | input | TCELL7:IMUX_A0 |
| C6 | input | TCELL5:IMUX_C2 |
| C7 | input | TCELL5:IMUX_A3 |
| C8 | input | TCELL6:IMUX_C4 |
| C9 | input | TCELL6:IMUX_A5 |
| CE0 | input | TCELL6:IMUX_CE0 |
| CE1 | input | TCELL6:IMUX_CE1 |
| CE2 | input | TCELL7:IMUX_CE0 |
| CE3 | input | TCELL7:IMUX_CE1 |
| CLK0 | input | TCELL6:IMUX_CLK0 |
| CLK1 | input | TCELL6:IMUX_CLK1 |
| CLK2 | input | TCELL7:IMUX_CLK0 |
| CLK3 | input | TCELL7:IMUX_CLK1 |
| EQOM | output | TCELL7:OUT_Q3 |
| EQPAT | output | TCELL7:OUT_Q2 |
| EQPATB | output | TCELL7:OUT_Q1 |
| EQZ | output | TCELL7:OUT_Q5 |
| EQZM | output | TCELL7:OUT_Q4 |
| OP0 | input | TCELL5:IMUX_CE0 |
| OP1 | input | TCELL5:IMUX_CE1 |
| OP10 | input | TCELL8:IMUX_CE2 |
| OP2 | input | TCELL5:IMUX_CE2 |
| OP3 | input | TCELL5:IMUX_CE3 |
| OP4 | input | TCELL6:IMUX_CE2 |
| OP5 | input | TCELL6:IMUX_CE3 |
| OP6 | input | TCELL7:IMUX_CE2 |
| OP7 | input | TCELL7:IMUX_CE3 |
| OP8 | input | TCELL8:IMUX_CE0 |
| OP9 | input | TCELL8:IMUX_CE1 |
| OPPRE_0 | input | TCELL4:IMUX_A4 |
| OPPRE_1 | input | TCELL4:IMUX_A6 |
| OVER | output | TCELL7:OUT_Q0 |
| OVERUNDER | output | TCELL6:OUT_Q6 |
| P0_0 | output | TCELL4:OUT_F4 |
| P0_1 | output | TCELL4:OUT_Q4 |
| P10_0 | output | TCELL5:OUT_F6 |
| P10_1 | output | TCELL5:OUT_Q6 |
| P11_0 | output | TCELL5:OUT_F7 |
| P11_1 | output | TCELL5:OUT_Q7 |
| P12_0 | output | TCELL6:OUT_F0 |
| P12_1 | output | TCELL6:OUT_Q0 |
| P13_0 | output | TCELL6:OUT_F1 |
| P13_1 | output | TCELL6:OUT_Q1 |
| P14_0 | output | TCELL6:OUT_F2 |
| P14_1 | output | TCELL6:OUT_Q2 |
| P15_0 | output | TCELL6:OUT_F3 |
| P15_1 | output | TCELL6:OUT_Q3 |
| P16_0 | output | TCELL6:OUT_F4 |
| P16_1 | output | TCELL6:OUT_Q4 |
| P17_0 | output | TCELL6:OUT_F5 |
| P17_1 | output | TCELL6:OUT_Q5 |
| P18_0 | output | TCELL6:OUT_F6 |
| P18_1 | output | TCELL6:OUT_Q6 |
| P19_0 | output | TCELL6:OUT_F7 |
| P19_1 | output | TCELL6:OUT_Q7 |
| P1_0 | output | TCELL4:OUT_F5 |
| P1_1 | output | TCELL4:OUT_Q5 |
| P20_0 | output | TCELL7:OUT_F0 |
| P20_1 | output | TCELL7:OUT_Q0 |
| P21_0 | output | TCELL7:OUT_F1 |
| P21_1 | output | TCELL7:OUT_Q1 |
| P22_0 | output | TCELL7:OUT_F2 |
| P22_1 | output | TCELL7:OUT_Q2 |
| P23_0 | output | TCELL7:OUT_F3 |
| P23_1 | output | TCELL7:OUT_Q3 |
| P24_0 | output | TCELL7:OUT_F4 |
| P24_1 | output | TCELL7:OUT_Q4 |
| P25_0 | output | TCELL7:OUT_F5 |
| P25_1 | output | TCELL7:OUT_Q5 |
| P26_0 | output | TCELL7:OUT_F6 |
| P26_1 | output | TCELL7:OUT_Q6 |
| P27_0 | output | TCELL7:OUT_F7 |
| P27_1 | output | TCELL7:OUT_Q7 |
| P28_0 | output | TCELL8:OUT_F0 |
| P28_1 | output | TCELL8:OUT_Q0 |
| P29_0 | output | TCELL8:OUT_F1 |
| P29_1 | output | TCELL8:OUT_Q1 |
| P2_0 | output | TCELL4:OUT_F6 |
| P2_1 | output | TCELL4:OUT_Q6 |
| P30_0 | output | TCELL8:OUT_F2 |
| P30_1 | output | TCELL8:OUT_Q2 |
| P31_0 | output | TCELL8:OUT_F3 |
| P31_1 | output | TCELL8:OUT_Q3 |
| P32_0 | output | TCELL8:OUT_F4 |
| P32_1 | output | TCELL8:OUT_Q4 |
| P33_0 | output | TCELL8:OUT_F5 |
| P33_1 | output | TCELL8:OUT_Q5 |
| P34_0 | output | TCELL8:OUT_F6 |
| P34_1 | output | TCELL8:OUT_Q6 |
| P35_0 | output | TCELL8:OUT_F7 |
| P35_1 | output | TCELL8:OUT_Q7 |
| P3_0 | output | TCELL4:OUT_F7 |
| P3_1 | output | TCELL4:OUT_Q7 |
| P4_0 | output | TCELL5:OUT_F0 |
| P4_1 | output | TCELL5:OUT_Q0 |
| P5_0 | output | TCELL5:OUT_F1 |
| P5_1 | output | TCELL5:OUT_Q1 |
| P6_0 | output | TCELL5:OUT_F2 |
| P6_1 | output | TCELL5:OUT_Q2 |
| P7_0 | output | TCELL5:OUT_F3 |
| P7_1 | output | TCELL5:OUT_Q3 |
| P8_0 | output | TCELL5:OUT_F4 |
| P8_1 | output | TCELL5:OUT_Q4 |
| P9_0 | output | TCELL5:OUT_F5 |
| P9_1 | output | TCELL5:OUT_Q5 |
| R0 | output | TCELL4:OUT_F4 |
| R1 | output | TCELL4:OUT_F5 |
| R10 | output | TCELL5:OUT_F6 |
| R11 | output | TCELL5:OUT_F7 |
| R12 | output | TCELL6:OUT_F0 |
| R13 | output | TCELL6:OUT_F1 |
| R14 | output | TCELL6:OUT_F2 |
| R15 | output | TCELL6:OUT_F3 |
| R16 | output | TCELL6:OUT_F4 |
| R17 | output | TCELL6:OUT_F5 |
| R18 | output | TCELL4:OUT_Q4 |
| R19 | output | TCELL4:OUT_Q5 |
| R2 | output | TCELL4:OUT_F6 |
| R20 | output | TCELL4:OUT_Q6 |
| R21 | output | TCELL4:OUT_Q7 |
| R22 | output | TCELL5:OUT_Q0 |
| R23 | output | TCELL5:OUT_Q1 |
| R24 | output | TCELL5:OUT_Q2 |
| R25 | output | TCELL5:OUT_Q3 |
| R26 | output | TCELL5:OUT_Q4 |
| R27 | output | TCELL6:OUT_F6 |
| R28 | output | TCELL6:OUT_F7 |
| R29 | output | TCELL7:OUT_F0 |
| R3 | output | TCELL4:OUT_F7 |
| R30 | output | TCELL7:OUT_F1 |
| R31 | output | TCELL7:OUT_F2 |
| R32 | output | TCELL7:OUT_F3 |
| R33 | output | TCELL7:OUT_F4 |
| R34 | output | TCELL7:OUT_F5 |
| R35 | output | TCELL7:OUT_F6 |
| R36 | output | TCELL7:OUT_F7 |
| R37 | output | TCELL8:OUT_F0 |
| R38 | output | TCELL8:OUT_F1 |
| R39 | output | TCELL8:OUT_F2 |
| R4 | output | TCELL5:OUT_F0 |
| R40 | output | TCELL8:OUT_F3 |
| R41 | output | TCELL8:OUT_F4 |
| R42 | output | TCELL8:OUT_F5 |
| R43 | output | TCELL8:OUT_F6 |
| R44 | output | TCELL8:OUT_F7 |
| R45 | output | TCELL5:OUT_Q5 |
| R46 | output | TCELL5:OUT_Q6 |
| R47 | output | TCELL5:OUT_Q7 |
| R48 | output | TCELL6:OUT_Q0 |
| R49 | output | TCELL6:OUT_Q1 |
| R5 | output | TCELL5:OUT_F1 |
| R50 | output | TCELL6:OUT_Q2 |
| R51 | output | TCELL6:OUT_Q3 |
| R52 | output | TCELL6:OUT_Q4 |
| R53 | output | TCELL6:OUT_Q5 |
| R6 | output | TCELL5:OUT_F2 |
| R7 | output | TCELL5:OUT_F3 |
| R8 | output | TCELL5:OUT_F4 |
| R9 | output | TCELL5:OUT_F5 |
| RST0 | input | TCELL3:IMUX_LSR0 |
| RST1 | input | TCELL3:IMUX_LSR1 |
| RST2 | input | TCELL5:IMUX_LSR0 |
| RST3 | input | TCELL5:IMUX_LSR1 |
| SIGNEDA_0 | input | TCELL4:IMUX_CE2 |
| SIGNEDA_1 | input | TCELL7:IMUX_LSR1 |
| SIGNEDB_0 | input | TCELL4:IMUX_CE3 |
| SIGNEDB_1 | input | TCELL8:IMUX_CE3 |
| SOURCEA_0 | input | TCELL6:IMUX_LSR0 |
| SOURCEA_1 | input | TCELL8:IMUX_LSR1 |
| SOURCEB_0 | input | TCELL6:IMUX_LSR1 |
| SOURCEB_1 | input | TCELL8:IMUX_LSR0 |
| SROA0 | output | TCELL6:OUT_Q6 |
| SROA1 | output | TCELL6:OUT_Q7 |
| SROA10 | output | TCELL8:OUT_Q0 |
| SROA11 | output | TCELL8:OUT_Q1 |
| SROA12 | output | TCELL8:OUT_Q2 |
| SROA13 | output | TCELL8:OUT_Q3 |
| SROA14 | output | TCELL8:OUT_Q4 |
| SROA15 | output | TCELL8:OUT_Q5 |
| SROA16 | output | TCELL8:OUT_Q6 |
| SROA17 | output | TCELL8:OUT_Q7 |
| SROA2 | output | TCELL7:OUT_Q0 |
| SROA3 | output | TCELL7:OUT_Q1 |
| SROA4 | output | TCELL7:OUT_Q2 |
| SROA5 | output | TCELL7:OUT_Q3 |
| SROA6 | output | TCELL7:OUT_Q4 |
| SROA7 | output | TCELL7:OUT_Q5 |
| SROA8 | output | TCELL7:OUT_Q6 |
| SROA9 | output | TCELL7:OUT_Q7 |
| UNDER | output | TCELL6:OUT_Q7 |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX_A0 | DSP0.C37 |
| TCELL0:IMUX_A1 | DSP0.C5 |
| TCELL0:IMUX_A2 | DSP0.C39 |
| TCELL0:IMUX_A3 | DSP0.C7 |
| TCELL0:IMUX_A4 | DSP0.C33 |
| TCELL0:IMUX_A5 | DSP0.C1 |
| TCELL0:IMUX_A6 | DSP0.C35 |
| TCELL0:IMUX_A7 | DSP0.C3 |
| TCELL0:IMUX_B0 | DSP0.B1_0 |
| TCELL0:IMUX_B1 | DSP0.A1_0 |
| TCELL0:IMUX_B2 | DSP0.B3_0 |
| TCELL0:IMUX_B3 | DSP0.A3_0 |
| TCELL0:IMUX_B4 | DSP0.B5_0 |
| TCELL0:IMUX_B5 | DSP0.A5_0 |
| TCELL0:IMUX_B6 | DSP0.B7_0 |
| TCELL0:IMUX_B7 | DSP0.A7_0 |
| TCELL0:IMUX_C0 | DSP0.C4 |
| TCELL0:IMUX_C1 | DSP0.C36 |
| TCELL0:IMUX_C2 | DSP0.C6 |
| TCELL0:IMUX_C3 | DSP0.C38 |
| TCELL0:IMUX_C4 | DSP0.C0 |
| TCELL0:IMUX_C5 | DSP0.C32 |
| TCELL0:IMUX_C6 | DSP0.C2 |
| TCELL0:IMUX_C7 | DSP0.C34 |
| TCELL0:IMUX_D0 | DSP0.A0_0 |
| TCELL0:IMUX_D1 | DSP0.B0_0 |
| TCELL0:IMUX_D2 | DSP0.A2_0 |
| TCELL0:IMUX_D3 | DSP0.B2_0 |
| TCELL0:IMUX_D4 | DSP0.A4_0 |
| TCELL0:IMUX_D5 | DSP0.B4_0 |
| TCELL0:IMUX_D6 | DSP0.A6_0 |
| TCELL0:IMUX_D7 | DSP0.B6_0 |
| TCELL0:IMUX_LSR0 | DSP0.SOURCEA_0 |
| TCELL0:IMUX_LSR1 | DSP0.SOURCEB_0 |
| TCELL0:IMUX_CE0 | DSP0.SIGNEDB_0 |
| TCELL0:IMUX_CE1 | DSP0.OP0 |
| TCELL0:IMUX_CE2 | DSP0.OP1 |
| TCELL0:IMUX_CE3 | DSP0.OP2 |
| TCELL0:OUT_F0 | DSP0.P0_0, DSP0.R0 |
| TCELL0:OUT_F1 | DSP0.P1_0, DSP0.R1 |
| TCELL0:OUT_F2 | DSP0.P2_0, DSP0.R2 |
| TCELL0:OUT_F3 | DSP0.P3_0, DSP0.R3 |
| TCELL0:OUT_F4 | DSP0.P4_0, DSP0.R4 |
| TCELL0:OUT_F5 | DSP0.P5_0, DSP0.R5 |
| TCELL0:OUT_F6 | DSP0.P6_0, DSP0.R6 |
| TCELL0:OUT_F7 | DSP0.P7_0, DSP0.R7 |
| TCELL0:OUT_Q0 | DSP0.P0_1, DSP0.R18 |
| TCELL0:OUT_Q1 | DSP0.P1_1, DSP0.R19 |
| TCELL0:OUT_Q2 | DSP0.P2_1, DSP0.R20 |
| TCELL0:OUT_Q3 | DSP0.P3_1, DSP0.R21 |
| TCELL0:OUT_Q4 | DSP0.P4_1, DSP0.R22 |
| TCELL0:OUT_Q5 | DSP0.P5_1, DSP0.R23 |
| TCELL0:OUT_Q6 | DSP0.P6_1, DSP0.R24 |
| TCELL0:OUT_Q7 | DSP0.P7_1, DSP0.R25 |
| TCELL1:IMUX_A0 | DSP0.C45 |
| TCELL1:IMUX_A1 | DSP0.C13 |
| TCELL1:IMUX_A2 | DSP0.C47 |
| TCELL1:IMUX_A3 | DSP0.C15 |
| TCELL1:IMUX_A4 | DSP0.C41 |
| TCELL1:IMUX_A5 | DSP0.C9 |
| TCELL1:IMUX_A6 | DSP0.C43 |
| TCELL1:IMUX_A7 | DSP0.C11 |
| TCELL1:IMUX_B0 | DSP0.B9_0 |
| TCELL1:IMUX_B1 | DSP0.A9_0 |
| TCELL1:IMUX_B2 | DSP0.B11_0 |
| TCELL1:IMUX_B3 | DSP0.A11_0 |
| TCELL1:IMUX_B4 | DSP0.B13_0 |
| TCELL1:IMUX_B5 | DSP0.A13_0 |
| TCELL1:IMUX_B6 | DSP0.B15_0 |
| TCELL1:IMUX_B7 | DSP0.A15_0 |
| TCELL1:IMUX_C0 | DSP0.C12 |
| TCELL1:IMUX_C1 | DSP0.C44 |
| TCELL1:IMUX_C2 | DSP0.C14 |
| TCELL1:IMUX_C3 | DSP0.C46 |
| TCELL1:IMUX_C4 | DSP0.C8 |
| TCELL1:IMUX_C5 | DSP0.C40 |
| TCELL1:IMUX_C6 | DSP0.C10 |
| TCELL1:IMUX_C7 | DSP0.C42 |
| TCELL1:IMUX_D0 | DSP0.A8_0 |
| TCELL1:IMUX_D1 | DSP0.B8_0 |
| TCELL1:IMUX_D2 | DSP0.A10_0 |
| TCELL1:IMUX_D3 | DSP0.B10_0 |
| TCELL1:IMUX_D4 | DSP0.A12_0 |
| TCELL1:IMUX_D5 | DSP0.B12_0 |
| TCELL1:IMUX_D6 | DSP0.A14_0 |
| TCELL1:IMUX_D7 | DSP0.B14_0 |
| TCELL1:IMUX_CLK0 | DSP0.CLK0 |
| TCELL1:IMUX_CLK1 | DSP0.CLK1 |
| TCELL1:IMUX_LSR1 | DSP0.SIGNEDA_0 |
| TCELL1:IMUX_CE0 | DSP0.CE0 |
| TCELL1:IMUX_CE1 | DSP0.CE1 |
| TCELL1:IMUX_CE2 | DSP0.OP3 |
| TCELL1:IMUX_CE3 | DSP0.OP4 |
| TCELL1:OUT_F0 | DSP0.P8_0, DSP0.R8 |
| TCELL1:OUT_F1 | DSP0.P9_0, DSP0.R9 |
| TCELL1:OUT_F2 | DSP0.P10_0, DSP0.R10 |
| TCELL1:OUT_F3 | DSP0.P11_0, DSP0.R11 |
| TCELL1:OUT_F4 | DSP0.P12_0, DSP0.R12 |
| TCELL1:OUT_F5 | DSP0.P13_0, DSP0.R13 |
| TCELL1:OUT_F6 | DSP0.P14_0, DSP0.R14 |
| TCELL1:OUT_F7 | DSP0.P15_0, DSP0.R15 |
| TCELL1:OUT_Q0 | DSP0.P8_1, DSP0.R26 |
| TCELL1:OUT_Q1 | DSP0.P9_1, DSP0.R45 |
| TCELL1:OUT_Q2 | DSP0.P10_1, DSP0.R46 |
| TCELL1:OUT_Q3 | DSP0.P11_1, DSP0.R47 |
| TCELL1:OUT_Q4 | DSP0.P12_1, DSP0.R48 |
| TCELL1:OUT_Q5 | DSP0.P13_1, DSP0.R49 |
| TCELL1:OUT_Q6 | DSP0.P14_1, DSP0.R50 |
| TCELL1:OUT_Q7 | DSP0.P15_1, DSP0.R51 |
| TCELL2:IMUX_A0 | DSP0.C53 |
| TCELL2:IMUX_A1 | DSP0.C21 |
| TCELL2:IMUX_A3 | DSP0.C23 |
| TCELL2:IMUX_A4 | DSP0.C49 |
| TCELL2:IMUX_A5 | DSP0.C17 |
| TCELL2:IMUX_A6 | DSP0.C51 |
| TCELL2:IMUX_A7 | DSP0.C19 |
| TCELL2:IMUX_B0 | DSP0.B17_0 |
| TCELL2:IMUX_B1 | DSP0.A17_0 |
| TCELL2:IMUX_B2 | DSP0.B1_1 |
| TCELL2:IMUX_B3 | DSP0.A1_1 |
| TCELL2:IMUX_B4 | DSP0.B3_1 |
| TCELL2:IMUX_B5 | DSP0.A3_1 |
| TCELL2:IMUX_B6 | DSP0.B5_1 |
| TCELL2:IMUX_B7 | DSP0.A5_1 |
| TCELL2:IMUX_C0 | DSP0.C20 |
| TCELL2:IMUX_C1 | DSP0.C52 |
| TCELL2:IMUX_C2 | DSP0.C22 |
| TCELL2:IMUX_C4 | DSP0.C16 |
| TCELL2:IMUX_C5 | DSP0.C48 |
| TCELL2:IMUX_C6 | DSP0.C18 |
| TCELL2:IMUX_C7 | DSP0.C50 |
| TCELL2:IMUX_D0 | DSP0.A16_0 |
| TCELL2:IMUX_D1 | DSP0.B16_0 |
| TCELL2:IMUX_D2 | DSP0.A0_1 |
| TCELL2:IMUX_D3 | DSP0.B0_1 |
| TCELL2:IMUX_D4 | DSP0.A2_1 |
| TCELL2:IMUX_D5 | DSP0.B2_1 |
| TCELL2:IMUX_D6 | DSP0.A4_1 |
| TCELL2:IMUX_D7 | DSP0.B4_1 |
| TCELL2:IMUX_CLK0 | DSP0.CLK2 |
| TCELL2:IMUX_CLK1 | DSP0.CLK3 |
| TCELL2:IMUX_LSR0 | DSP0.SOURCEA_1 |
| TCELL2:IMUX_LSR1 | DSP0.SOURCEB_1 |
| TCELL2:IMUX_CE0 | DSP0.CE2 |
| TCELL2:IMUX_CE1 | DSP0.CE3 |
| TCELL2:IMUX_CE2 | DSP0.OP5 |
| TCELL2:IMUX_CE3 | DSP0.OP6 |
| TCELL2:OUT_F0 | DSP0.P16_0, DSP0.R16 |
| TCELL2:OUT_F1 | DSP0.P17_0, DSP0.R17 |
| TCELL2:OUT_F2 | DSP0.P18_0, DSP0.R27 |
| TCELL2:OUT_F3 | DSP0.P19_0, DSP0.R28 |
| TCELL2:OUT_F4 | DSP0.P20_0, DSP0.R29 |
| TCELL2:OUT_F5 | DSP0.P21_0, DSP0.R30 |
| TCELL2:OUT_F6 | DSP0.P22_0, DSP0.R31 |
| TCELL2:OUT_F7 | DSP0.P23_0, DSP0.R32 |
| TCELL2:OUT_Q0 | DSP0.P16_1, DSP0.R52 |
| TCELL2:OUT_Q1 | DSP0.P17_1, DSP0.R53 |
| TCELL2:OUT_Q2 | DSP0.OVERUNDER, DSP0.P18_1, DSP0.SROA0 |
| TCELL2:OUT_Q3 | DSP0.P19_1, DSP0.SROA1, DSP0.UNDER |
| TCELL2:OUT_Q4 | DSP0.OVER, DSP0.P20_1, DSP0.SROA2 |
| TCELL2:OUT_Q5 | DSP0.EQPATB, DSP0.P21_1, DSP0.SROA3 |
| TCELL2:OUT_Q6 | DSP0.EQPAT, DSP0.P22_1, DSP0.SROA4 |
| TCELL2:OUT_Q7 | DSP0.EQOM, DSP0.P23_1, DSP0.SROA5 |
| TCELL3:IMUX_A1 | DSP0.C29 |
| TCELL3:IMUX_A3 | DSP0.C31 |
| TCELL3:IMUX_A4 | DSP0.OPPRE_0 |
| TCELL3:IMUX_A5 | DSP0.C25 |
| TCELL3:IMUX_A6 | DSP0.OPPRE_1 |
| TCELL3:IMUX_A7 | DSP0.C27 |
| TCELL3:IMUX_B0 | DSP0.B7_1 |
| TCELL3:IMUX_B1 | DSP0.A7_1 |
| TCELL3:IMUX_B2 | DSP0.B9_1 |
| TCELL3:IMUX_B3 | DSP0.A9_1 |
| TCELL3:IMUX_B4 | DSP0.B11_1 |
| TCELL3:IMUX_B5 | DSP0.A11_1 |
| TCELL3:IMUX_B6 | DSP0.B13_1 |
| TCELL3:IMUX_B7 | DSP0.A13_1 |
| TCELL3:IMUX_C0 | DSP0.C28 |
| TCELL3:IMUX_C2 | DSP0.C30 |
| TCELL3:IMUX_C4 | DSP0.C24 |
| TCELL3:IMUX_C6 | DSP0.C26 |
| TCELL3:IMUX_D0 | DSP0.A6_1 |
| TCELL3:IMUX_D1 | DSP0.B6_1 |
| TCELL3:IMUX_D2 | DSP0.A8_1 |
| TCELL3:IMUX_D3 | DSP0.B8_1 |
| TCELL3:IMUX_D4 | DSP0.A10_1 |
| TCELL3:IMUX_D5 | DSP0.B10_1 |
| TCELL3:IMUX_D6 | DSP0.A12_1 |
| TCELL3:IMUX_D7 | DSP0.B12_1 |
| TCELL3:IMUX_LSR0 | DSP0.RST0, DSP1.RST0 |
| TCELL3:IMUX_LSR1 | DSP0.RST1, DSP1.RST1 |
| TCELL3:IMUX_CE0 | DSP0.OP7 |
| TCELL3:IMUX_CE1 | DSP0.OP8 |
| TCELL3:IMUX_CE2 | DSP0.OP9 |
| TCELL3:IMUX_CE3 | DSP0.OP10 |
| TCELL3:OUT_F0 | DSP0.P24_0, DSP0.R33 |
| TCELL3:OUT_F1 | DSP0.P25_0, DSP0.R34 |
| TCELL3:OUT_F2 | DSP0.P26_0, DSP0.R35 |
| TCELL3:OUT_F3 | DSP0.P27_0, DSP0.R36 |
| TCELL3:OUT_F4 | DSP0.P28_0, DSP0.R37 |
| TCELL3:OUT_F5 | DSP0.P29_0, DSP0.R38 |
| TCELL3:OUT_F6 | DSP0.P30_0, DSP0.R39 |
| TCELL3:OUT_F7 | DSP0.P31_0, DSP0.R40 |
| TCELL3:OUT_Q0 | DSP0.EQZM, DSP0.P24_1, DSP0.SROA6 |
| TCELL3:OUT_Q1 | DSP0.EQZ, DSP0.P25_1, DSP0.SROA7 |
| TCELL3:OUT_Q2 | DSP0.P26_1, DSP0.SROA8 |
| TCELL3:OUT_Q3 | DSP0.P27_1, DSP0.SROA9 |
| TCELL3:OUT_Q4 | DSP0.P28_1, DSP0.SROA10 |
| TCELL3:OUT_Q5 | DSP0.P29_1, DSP0.SROA11 |
| TCELL3:OUT_Q6 | DSP0.P30_1, DSP0.SROA12 |
| TCELL3:OUT_Q7 | DSP0.P31_1, DSP0.SROA13 |
| TCELL4:IMUX_A4 | DSP1.OPPRE_0 |
| TCELL4:IMUX_A6 | DSP1.OPPRE_1 |
| TCELL4:IMUX_B0 | DSP0.B15_1 |
| TCELL4:IMUX_B1 | DSP0.A15_1 |
| TCELL4:IMUX_B2 | DSP0.B17_1 |
| TCELL4:IMUX_B3 | DSP0.A17_1 |
| TCELL4:IMUX_B4 | DSP1.B1_0 |
| TCELL4:IMUX_B5 | DSP1.A1_0 |
| TCELL4:IMUX_B6 | DSP1.B3_0 |
| TCELL4:IMUX_B7 | DSP1.A3_0 |
| TCELL4:IMUX_D0 | DSP0.A14_1 |
| TCELL4:IMUX_D1 | DSP0.B14_1 |
| TCELL4:IMUX_D2 | DSP0.A16_1 |
| TCELL4:IMUX_D3 | DSP0.B16_1 |
| TCELL4:IMUX_D4 | DSP1.A0_0 |
| TCELL4:IMUX_D5 | DSP1.B0_0 |
| TCELL4:IMUX_D6 | DSP1.A2_0 |
| TCELL4:IMUX_D7 | DSP1.B2_0 |
| TCELL4:IMUX_CE0 | DSP0.SIGNEDA_1 |
| TCELL4:IMUX_CE1 | DSP0.SIGNEDB_1 |
| TCELL4:IMUX_CE2 | DSP1.SIGNEDA_0 |
| TCELL4:IMUX_CE3 | DSP1.SIGNEDB_0 |
| TCELL4:OUT_F0 | DSP0.P32_0, DSP0.R41 |
| TCELL4:OUT_F1 | DSP0.P33_0, DSP0.R42 |
| TCELL4:OUT_F2 | DSP0.P34_0, DSP0.R43 |
| TCELL4:OUT_F3 | DSP0.P35_0, DSP0.R44 |
| TCELL4:OUT_F4 | DSP1.P0_0, DSP1.R0 |
| TCELL4:OUT_F5 | DSP1.P1_0, DSP1.R1 |
| TCELL4:OUT_F6 | DSP1.P2_0, DSP1.R2 |
| TCELL4:OUT_F7 | DSP1.P3_0, DSP1.R3 |
| TCELL4:OUT_Q0 | DSP0.P32_1, DSP0.SROA14 |
| TCELL4:OUT_Q1 | DSP0.P33_1, DSP0.SROA15 |
| TCELL4:OUT_Q2 | DSP0.P34_1, DSP0.SROA16 |
| TCELL4:OUT_Q3 | DSP0.P35_1, DSP0.SROA17 |
| TCELL4:OUT_Q4 | DSP1.P0_1, DSP1.R18 |
| TCELL4:OUT_Q5 | DSP1.P1_1, DSP1.R19 |
| TCELL4:OUT_Q6 | DSP1.P2_1, DSP1.R20 |
| TCELL4:OUT_Q7 | DSP1.P3_1, DSP1.R21 |
| TCELL5:IMUX_A0 | DSP1.C37 |
| TCELL5:IMUX_A1 | DSP1.C5 |
| TCELL5:IMUX_A2 | DSP1.C39 |
| TCELL5:IMUX_A3 | DSP1.C7 |
| TCELL5:IMUX_A4 | DSP1.C33 |
| TCELL5:IMUX_A5 | DSP1.C1 |
| TCELL5:IMUX_A6 | DSP1.C35 |
| TCELL5:IMUX_A7 | DSP1.C3 |
| TCELL5:IMUX_B0 | DSP1.B5_0 |
| TCELL5:IMUX_B1 | DSP1.A5_0 |
| TCELL5:IMUX_B2 | DSP1.B7_0 |
| TCELL5:IMUX_B3 | DSP1.A7_0 |
| TCELL5:IMUX_B4 | DSP1.B9_0 |
| TCELL5:IMUX_B5 | DSP1.A9_0 |
| TCELL5:IMUX_B6 | DSP1.B11_0 |
| TCELL5:IMUX_B7 | DSP1.A11_0 |
| TCELL5:IMUX_C0 | DSP1.C4 |
| TCELL5:IMUX_C1 | DSP1.C36 |
| TCELL5:IMUX_C2 | DSP1.C6 |
| TCELL5:IMUX_C3 | DSP1.C38 |
| TCELL5:IMUX_C4 | DSP1.C0 |
| TCELL5:IMUX_C5 | DSP1.C32 |
| TCELL5:IMUX_C6 | DSP1.C2 |
| TCELL5:IMUX_C7 | DSP1.C34 |
| TCELL5:IMUX_D0 | DSP1.A4_0 |
| TCELL5:IMUX_D1 | DSP1.B4_0 |
| TCELL5:IMUX_D2 | DSP1.A6_0 |
| TCELL5:IMUX_D3 | DSP1.B6_0 |
| TCELL5:IMUX_D4 | DSP1.A8_0 |
| TCELL5:IMUX_D5 | DSP1.B8_0 |
| TCELL5:IMUX_D6 | DSP1.A10_0 |
| TCELL5:IMUX_D7 | DSP1.B10_0 |
| TCELL5:IMUX_LSR0 | DSP0.RST2, DSP1.RST2 |
| TCELL5:IMUX_LSR1 | DSP0.RST3, DSP1.RST3 |
| TCELL5:IMUX_CE0 | DSP1.OP0 |
| TCELL5:IMUX_CE1 | DSP1.OP1 |
| TCELL5:IMUX_CE2 | DSP1.OP2 |
| TCELL5:IMUX_CE3 | DSP1.OP3 |
| TCELL5:OUT_F0 | DSP1.P4_0, DSP1.R4 |
| TCELL5:OUT_F1 | DSP1.P5_0, DSP1.R5 |
| TCELL5:OUT_F2 | DSP1.P6_0, DSP1.R6 |
| TCELL5:OUT_F3 | DSP1.P7_0, DSP1.R7 |
| TCELL5:OUT_F4 | DSP1.P8_0, DSP1.R8 |
| TCELL5:OUT_F5 | DSP1.P9_0, DSP1.R9 |
| TCELL5:OUT_F6 | DSP1.P10_0, DSP1.R10 |
| TCELL5:OUT_F7 | DSP1.P11_0, DSP1.R11 |
| TCELL5:OUT_Q0 | DSP1.P4_1, DSP1.R22 |
| TCELL5:OUT_Q1 | DSP1.P5_1, DSP1.R23 |
| TCELL5:OUT_Q2 | DSP1.P6_1, DSP1.R24 |
| TCELL5:OUT_Q3 | DSP1.P7_1, DSP1.R25 |
| TCELL5:OUT_Q4 | DSP1.P8_1, DSP1.R26 |
| TCELL5:OUT_Q5 | DSP1.P9_1, DSP1.R45 |
| TCELL5:OUT_Q6 | DSP1.P10_1, DSP1.R46 |
| TCELL5:OUT_Q7 | DSP1.P11_1, DSP1.R47 |
| TCELL6:IMUX_A0 | DSP1.C45 |
| TCELL6:IMUX_A1 | DSP1.C13 |
| TCELL6:IMUX_A2 | DSP1.C47 |
| TCELL6:IMUX_A3 | DSP1.C15 |
| TCELL6:IMUX_A4 | DSP1.C41 |
| TCELL6:IMUX_A5 | DSP1.C9 |
| TCELL6:IMUX_A6 | DSP1.C43 |
| TCELL6:IMUX_A7 | DSP1.C11 |
| TCELL6:IMUX_B0 | DSP1.B13_0 |
| TCELL6:IMUX_B1 | DSP1.A13_0 |
| TCELL6:IMUX_B2 | DSP1.B15_0 |
| TCELL6:IMUX_B3 | DSP1.A15_0 |
| TCELL6:IMUX_B4 | DSP1.B17_0 |
| TCELL6:IMUX_B5 | DSP1.A17_0 |
| TCELL6:IMUX_B6 | DSP1.B1_1 |
| TCELL6:IMUX_B7 | DSP1.A1_1 |
| TCELL6:IMUX_C0 | DSP1.C12 |
| TCELL6:IMUX_C1 | DSP1.C44 |
| TCELL6:IMUX_C2 | DSP1.C14 |
| TCELL6:IMUX_C3 | DSP1.C46 |
| TCELL6:IMUX_C4 | DSP1.C8 |
| TCELL6:IMUX_C5 | DSP1.C40 |
| TCELL6:IMUX_C6 | DSP1.C10 |
| TCELL6:IMUX_C7 | DSP1.C42 |
| TCELL6:IMUX_D0 | DSP1.A12_0 |
| TCELL6:IMUX_D1 | DSP1.B12_0 |
| TCELL6:IMUX_D2 | DSP1.A14_0 |
| TCELL6:IMUX_D3 | DSP1.B14_0 |
| TCELL6:IMUX_D4 | DSP1.A16_0 |
| TCELL6:IMUX_D5 | DSP1.B16_0 |
| TCELL6:IMUX_D6 | DSP1.A0_1 |
| TCELL6:IMUX_D7 | DSP1.B0_1 |
| TCELL6:IMUX_CLK0 | DSP1.CLK0 |
| TCELL6:IMUX_CLK1 | DSP1.CLK1 |
| TCELL6:IMUX_LSR0 | DSP1.SOURCEA_0 |
| TCELL6:IMUX_LSR1 | DSP1.SOURCEB_0 |
| TCELL6:IMUX_CE0 | DSP1.CE0 |
| TCELL6:IMUX_CE1 | DSP1.CE1 |
| TCELL6:IMUX_CE2 | DSP1.OP4 |
| TCELL6:IMUX_CE3 | DSP1.OP5 |
| TCELL6:OUT_F0 | DSP1.P12_0, DSP1.R12 |
| TCELL6:OUT_F1 | DSP1.P13_0, DSP1.R13 |
| TCELL6:OUT_F2 | DSP1.P14_0, DSP1.R14 |
| TCELL6:OUT_F3 | DSP1.P15_0, DSP1.R15 |
| TCELL6:OUT_F4 | DSP1.P16_0, DSP1.R16 |
| TCELL6:OUT_F5 | DSP1.P17_0, DSP1.R17 |
| TCELL6:OUT_F6 | DSP1.P18_0, DSP1.R27 |
| TCELL6:OUT_F7 | DSP1.P19_0, DSP1.R28 |
| TCELL6:OUT_Q0 | DSP1.P12_1, DSP1.R48 |
| TCELL6:OUT_Q1 | DSP1.P13_1, DSP1.R49 |
| TCELL6:OUT_Q2 | DSP1.P14_1, DSP1.R50 |
| TCELL6:OUT_Q3 | DSP1.P15_1, DSP1.R51 |
| TCELL6:OUT_Q4 | DSP1.P16_1, DSP1.R52 |
| TCELL6:OUT_Q5 | DSP1.P17_1, DSP1.R53 |
| TCELL6:OUT_Q6 | DSP1.OVERUNDER, DSP1.P18_1, DSP1.SROA0 |
| TCELL6:OUT_Q7 | DSP1.P19_1, DSP1.SROA1, DSP1.UNDER |
| TCELL7:IMUX_A0 | DSP1.C53 |
| TCELL7:IMUX_A1 | DSP1.C21 |
| TCELL7:IMUX_A3 | DSP1.C23 |
| TCELL7:IMUX_A4 | DSP1.C49 |
| TCELL7:IMUX_A5 | DSP1.C17 |
| TCELL7:IMUX_A6 | DSP1.C51 |
| TCELL7:IMUX_A7 | DSP1.C19 |
| TCELL7:IMUX_B0 | DSP1.B3_1 |
| TCELL7:IMUX_B1 | DSP1.A3_1 |
| TCELL7:IMUX_B2 | DSP1.B5_1 |
| TCELL7:IMUX_B3 | DSP1.A5_1 |
| TCELL7:IMUX_B4 | DSP1.B7_1 |
| TCELL7:IMUX_B5 | DSP1.A7_1 |
| TCELL7:IMUX_B6 | DSP1.B9_1 |
| TCELL7:IMUX_B7 | DSP1.A9_1 |
| TCELL7:IMUX_C0 | DSP1.C20 |
| TCELL7:IMUX_C1 | DSP1.C52 |
| TCELL7:IMUX_C2 | DSP1.C22 |
| TCELL7:IMUX_C4 | DSP1.C16 |
| TCELL7:IMUX_C5 | DSP1.C48 |
| TCELL7:IMUX_C6 | DSP1.C18 |
| TCELL7:IMUX_C7 | DSP1.C50 |
| TCELL7:IMUX_D0 | DSP1.A2_1 |
| TCELL7:IMUX_D1 | DSP1.B2_1 |
| TCELL7:IMUX_D2 | DSP1.A4_1 |
| TCELL7:IMUX_D3 | DSP1.B4_1 |
| TCELL7:IMUX_D4 | DSP1.A6_1 |
| TCELL7:IMUX_D5 | DSP1.B6_1 |
| TCELL7:IMUX_D6 | DSP1.A8_1 |
| TCELL7:IMUX_D7 | DSP1.B8_1 |
| TCELL7:IMUX_CLK0 | DSP1.CLK2 |
| TCELL7:IMUX_CLK1 | DSP1.CLK3 |
| TCELL7:IMUX_LSR1 | DSP1.SIGNEDA_1 |
| TCELL7:IMUX_CE0 | DSP1.CE2 |
| TCELL7:IMUX_CE1 | DSP1.CE3 |
| TCELL7:IMUX_CE2 | DSP1.OP6 |
| TCELL7:IMUX_CE3 | DSP1.OP7 |
| TCELL7:OUT_F0 | DSP1.P20_0, DSP1.R29 |
| TCELL7:OUT_F1 | DSP1.P21_0, DSP1.R30 |
| TCELL7:OUT_F2 | DSP1.P22_0, DSP1.R31 |
| TCELL7:OUT_F3 | DSP1.P23_0, DSP1.R32 |
| TCELL7:OUT_F4 | DSP1.P24_0, DSP1.R33 |
| TCELL7:OUT_F5 | DSP1.P25_0, DSP1.R34 |
| TCELL7:OUT_F6 | DSP1.P26_0, DSP1.R35 |
| TCELL7:OUT_F7 | DSP1.P27_0, DSP1.R36 |
| TCELL7:OUT_Q0 | DSP1.OVER, DSP1.P20_1, DSP1.SROA2 |
| TCELL7:OUT_Q1 | DSP1.EQPATB, DSP1.P21_1, DSP1.SROA3 |
| TCELL7:OUT_Q2 | DSP1.EQPAT, DSP1.P22_1, DSP1.SROA4 |
| TCELL7:OUT_Q3 | DSP1.EQOM, DSP1.P23_1, DSP1.SROA5 |
| TCELL7:OUT_Q4 | DSP1.EQZM, DSP1.P24_1, DSP1.SROA6 |
| TCELL7:OUT_Q5 | DSP1.EQZ, DSP1.P25_1, DSP1.SROA7 |
| TCELL7:OUT_Q6 | DSP1.P26_1, DSP1.SROA8 |
| TCELL7:OUT_Q7 | DSP1.P27_1, DSP1.SROA9 |
| TCELL8:IMUX_A1 | DSP1.C29 |
| TCELL8:IMUX_A3 | DSP1.C31 |
| TCELL8:IMUX_A5 | DSP1.C25 |
| TCELL8:IMUX_A7 | DSP1.C27 |
| TCELL8:IMUX_B0 | DSP1.B11_1 |
| TCELL8:IMUX_B1 | DSP1.A11_1 |
| TCELL8:IMUX_B2 | DSP1.B13_1 |
| TCELL8:IMUX_B3 | DSP1.A13_1 |
| TCELL8:IMUX_B4 | DSP1.B15_1 |
| TCELL8:IMUX_B5 | DSP1.A15_1 |
| TCELL8:IMUX_B6 | DSP1.B17_1 |
| TCELL8:IMUX_B7 | DSP1.A17_1 |
| TCELL8:IMUX_C0 | DSP1.C28 |
| TCELL8:IMUX_C2 | DSP1.C30 |
| TCELL8:IMUX_C4 | DSP1.C24 |
| TCELL8:IMUX_C6 | DSP1.C26 |
| TCELL8:IMUX_D0 | DSP1.A10_1 |
| TCELL8:IMUX_D1 | DSP1.B10_1 |
| TCELL8:IMUX_D2 | DSP1.A12_1 |
| TCELL8:IMUX_D3 | DSP1.B12_1 |
| TCELL8:IMUX_D4 | DSP1.A14_1 |
| TCELL8:IMUX_D5 | DSP1.B14_1 |
| TCELL8:IMUX_D6 | DSP1.A16_1 |
| TCELL8:IMUX_D7 | DSP1.B16_1 |
| TCELL8:IMUX_LSR0 | DSP1.SOURCEB_1 |
| TCELL8:IMUX_LSR1 | DSP1.SOURCEA_1 |
| TCELL8:IMUX_CE0 | DSP1.OP8 |
| TCELL8:IMUX_CE1 | DSP1.OP9 |
| TCELL8:IMUX_CE2 | DSP1.OP10 |
| TCELL8:IMUX_CE3 | DSP1.SIGNEDB_1 |
| TCELL8:OUT_F0 | DSP1.P28_0, DSP1.R37 |
| TCELL8:OUT_F1 | DSP1.P29_0, DSP1.R38 |
| TCELL8:OUT_F2 | DSP1.P30_0, DSP1.R39 |
| TCELL8:OUT_F3 | DSP1.P31_0, DSP1.R40 |
| TCELL8:OUT_F4 | DSP1.P32_0, DSP1.R41 |
| TCELL8:OUT_F5 | DSP1.P33_0, DSP1.R42 |
| TCELL8:OUT_F6 | DSP1.P34_0, DSP1.R43 |
| TCELL8:OUT_F7 | DSP1.P35_0, DSP1.R44 |
| TCELL8:OUT_Q0 | DSP1.P28_1, DSP1.SROA10 |
| TCELL8:OUT_Q1 | DSP1.P29_1, DSP1.SROA11 |
| TCELL8:OUT_Q2 | DSP1.P30_1, DSP1.SROA12 |
| TCELL8:OUT_Q3 | DSP1.P31_1, DSP1.SROA13 |
| TCELL8:OUT_Q4 | DSP1.P32_1, DSP1.SROA14 |
| TCELL8:OUT_Q5 | DSP1.P33_1, DSP1.SROA15 |
| TCELL8:OUT_Q6 | DSP1.P34_1, DSP1.SROA16 |
| TCELL8:OUT_Q7 | DSP1.P35_1, DSP1.SROA17 |