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Clock interconnect

Tile CLK_W_S

Cells: 12

Bel DLLDEL0

ecp5 CLK_W_S bel DLLDEL0
PinDirectionWires
CFLAGoutputCELL1.OUT_Q7
DIRECTIONinputCELL1.IMUX_D6
LOADNinputCELL1.IMUX_B6
MOVEinputCELL1.IMUX_C6

Bel DLLDEL1

ecp5 CLK_W_S bel DLLDEL1
PinDirectionWires
CFLAGoutputCELL0.OUT_Q7
DIRECTIONinputCELL0.IMUX_D6
LOADNinputCELL0.IMUX_B6
MOVEinputCELL0.IMUX_C6

Bel DLLDEL2

ecp5 CLK_W_S bel DLLDEL2
PinDirectionWires
CFLAGoutputCELL3.OUT_Q7
DIRECTIONinputCELL3.IMUX_D6
LOADNinputCELL3.IMUX_B6
MOVEinputCELL3.IMUX_C6

Bel DLLDEL3

ecp5 CLK_W_S bel DLLDEL3
PinDirectionWires
CFLAGoutputCELL2.OUT_Q7
DIRECTIONinputCELL2.IMUX_D6
LOADNinputCELL2.IMUX_B6
MOVEinputCELL2.IMUX_C6

Bel CLKDIV0

ecp5 CLK_W_S bel CLKDIV0
PinDirectionWires
ALIGNWDinputCELL4.IMUX_A3
CDIVXoutputCELL4.OUT_F2
RSTinputCELL4.IMUX_LSR0

Bel CLKDIV1

ecp5 CLK_W_S bel CLKDIV1
PinDirectionWires
ALIGNWDinputCELL4.IMUX_B3
CDIVXoutputCELL4.OUT_F3
RSTinputCELL4.IMUX_LSR1

Bel DCC0

ecp5 CLK_W_S bel DCC0
PinDirectionWires
CEinputCELL5.IMUX_C1

Bel DCC1

ecp5 CLK_W_S bel DCC1
PinDirectionWires
CEinputCELL5.IMUX_B0

Bel DCC2

ecp5 CLK_W_S bel DCC2
PinDirectionWires
CEinputCELL5.IMUX_C2

Bel DCC3

ecp5 CLK_W_S bel DCC3
PinDirectionWires
CEinputCELL5.IMUX_A3

Bel DCC4

ecp5 CLK_W_S bel DCC4
PinDirectionWires
CEinputCELL5.IMUX_D1

Bel DCC5

ecp5 CLK_W_S bel DCC5
PinDirectionWires
CEinputCELL5.IMUX_B1

Bel DCC6

ecp5 CLK_W_S bel DCC6
PinDirectionWires
CEinputCELL5.IMUX_A4

Bel DCC7

ecp5 CLK_W_S bel DCC7
PinDirectionWires
CEinputCELL5.IMUX_B2

Bel DCC8

ecp5 CLK_W_S bel DCC8
PinDirectionWires
CEinputCELL5.IMUX_A1

Bel DCC9

ecp5 CLK_W_S bel DCC9
PinDirectionWires
CEinputCELL5.IMUX_A0

Bel DCC10

ecp5 CLK_W_S bel DCC10
PinDirectionWires
CEinputCELL5.IMUX_D2

Bel DCC11

ecp5 CLK_W_S bel DCC11
PinDirectionWires
CEinputCELL5.IMUX_C3

Bel DCC12

ecp5 CLK_W_S bel DCC12
PinDirectionWires
CEinputCELL5.IMUX_A2

Bel DCC13

ecp5 CLK_W_S bel DCC13
PinDirectionWires
CEinputCELL5.IMUX_C0

Bel ECLKBRIDGECS0

ecp5 CLK_W_S bel ECLKBRIDGECS0
PinDirectionWires
SELinputCELL4.IMUX_A6

Bel BRGECLKSYNC0

ecp5 CLK_W_S bel BRGECLKSYNC0
PinDirectionWires
STOPinputCELL4.IMUX_A7

Bel CLK_EDGE

ecp5 CLK_W_S bel CLK_EDGE
PinDirectionWires
INT_IN_0inputCELL6.IMUX_D7
INT_IN_1inputCELL7.IMUX_D7
INT_IN_2inputCELL8.IMUX_D7
INT_IN_3inputCELL9.IMUX_D7
INT_IN_4inputCELL10.IMUX_CLK1
INT_IN_6inputCELL11.IMUX_CLK1

Bel CLKTEST

ecp5 CLK_W_S bel CLKTEST
PinDirectionWires
TESTIN0inputCELL5.IMUX_C4
TESTIN1inputCELL5.IMUX_A5
TESTIN2inputCELL5.IMUX_C5

Bel ECLKSYNC0

ecp5 CLK_W_S bel ECLKSYNC0
PinDirectionWires
ECLKoutputCELL5.OUT_F0
ECLKI_NinputCELL3.IMUX_CLK0
ECLKI_SinputCELL0.IMUX_CLK0
STOPinputCELL4.IMUX_C0

Bel ECLKSYNC1

ecp5 CLK_W_S bel ECLKSYNC1
PinDirectionWires
ECLKoutputCELL5.OUT_F1
ECLKI_NinputCELL3.IMUX_CLK1
ECLKI_SinputCELL0.IMUX_CLK1
STOPinputCELL4.IMUX_D0

Bel ECLKSYNC2

ecp5 CLK_W_S bel ECLKSYNC2
PinDirectionWires
ECLKoutputCELL4.OUT_F0
ECLKI_NinputCELL3.IMUX_CLK0
ECLKI_SinputCELL0.IMUX_CLK0
STOPinputCELL4.IMUX_A0

Bel ECLKSYNC3

ecp5 CLK_W_S bel ECLKSYNC3
PinDirectionWires
ECLKoutputCELL4.OUT_F1
ECLKI_NinputCELL3.IMUX_CLK1
ECLKI_SinputCELL0.IMUX_CLK1
STOPinputCELL4.IMUX_B0

Bel CLKTEST_ECLK

ecp5 CLK_W_S bel CLKTEST_ECLK
PinDirectionWires
TESTIN0inputCELL4.IMUX_A4
TESTIN1inputCELL4.IMUX_B4
TESTIN2inputCELL4.IMUX_C4
TESTIN3inputCELL4.IMUX_A5
TESTIN4inputCELL4.IMUX_B5
TESTIN5inputCELL4.IMUX_C5

Bel wires

ecp5 CLK_W_S bel wires
WirePins
CELL0.IMUX_B6DLLDEL1.LOADN
CELL0.IMUX_C6DLLDEL1.MOVE
CELL0.IMUX_D6DLLDEL1.DIRECTION
CELL0.IMUX_CLK0ECLKSYNC0.ECLKI_S, ECLKSYNC2.ECLKI_S
CELL0.IMUX_CLK1ECLKSYNC1.ECLKI_S, ECLKSYNC3.ECLKI_S
CELL0.OUT_Q7DLLDEL1.CFLAG
CELL1.IMUX_B6DLLDEL0.LOADN
CELL1.IMUX_C6DLLDEL0.MOVE
CELL1.IMUX_D6DLLDEL0.DIRECTION
CELL1.OUT_Q7DLLDEL0.CFLAG
CELL2.IMUX_B6DLLDEL3.LOADN
CELL2.IMUX_C6DLLDEL3.MOVE
CELL2.IMUX_D6DLLDEL3.DIRECTION
CELL2.OUT_Q7DLLDEL3.CFLAG
CELL3.IMUX_B6DLLDEL2.LOADN
CELL3.IMUX_C6DLLDEL2.MOVE
CELL3.IMUX_D6DLLDEL2.DIRECTION
CELL3.IMUX_CLK0ECLKSYNC0.ECLKI_N, ECLKSYNC2.ECLKI_N
CELL3.IMUX_CLK1ECLKSYNC1.ECLKI_N, ECLKSYNC3.ECLKI_N
CELL3.OUT_Q7DLLDEL2.CFLAG
CELL4.IMUX_A0ECLKSYNC2.STOP
CELL4.IMUX_A3CLKDIV0.ALIGNWD
CELL4.IMUX_A4CLKTEST_ECLK.TESTIN0
CELL4.IMUX_A5CLKTEST_ECLK.TESTIN3
CELL4.IMUX_A6ECLKBRIDGECS0.SEL
CELL4.IMUX_A7BRGECLKSYNC0.STOP
CELL4.IMUX_B0ECLKSYNC3.STOP
CELL4.IMUX_B3CLKDIV1.ALIGNWD
CELL4.IMUX_B4CLKTEST_ECLK.TESTIN1
CELL4.IMUX_B5CLKTEST_ECLK.TESTIN4
CELL4.IMUX_C0ECLKSYNC0.STOP
CELL4.IMUX_C4CLKTEST_ECLK.TESTIN2
CELL4.IMUX_C5CLKTEST_ECLK.TESTIN5
CELL4.IMUX_D0ECLKSYNC1.STOP
CELL4.IMUX_LSR0CLKDIV0.RST
CELL4.IMUX_LSR1CLKDIV1.RST
CELL4.OUT_F0ECLKSYNC2.ECLK
CELL4.OUT_F1ECLKSYNC3.ECLK
CELL4.OUT_F2CLKDIV0.CDIVX
CELL4.OUT_F3CLKDIV1.CDIVX
CELL5.IMUX_A0DCC9.CE
CELL5.IMUX_A1DCC8.CE
CELL5.IMUX_A2DCC12.CE
CELL5.IMUX_A3DCC3.CE
CELL5.IMUX_A4DCC6.CE
CELL5.IMUX_A5CLKTEST.TESTIN1
CELL5.IMUX_B0DCC1.CE
CELL5.IMUX_B1DCC5.CE
CELL5.IMUX_B2DCC7.CE
CELL5.IMUX_C0DCC13.CE
CELL5.IMUX_C1DCC0.CE
CELL5.IMUX_C2DCC2.CE
CELL5.IMUX_C3DCC11.CE
CELL5.IMUX_C4CLKTEST.TESTIN0
CELL5.IMUX_C5CLKTEST.TESTIN2
CELL5.IMUX_D1DCC4.CE
CELL5.IMUX_D2DCC10.CE
CELL5.OUT_F0ECLKSYNC0.ECLK
CELL5.OUT_F1ECLKSYNC1.ECLK
CELL6.IMUX_D7CLK_EDGE.INT_IN_0
CELL7.IMUX_D7CLK_EDGE.INT_IN_1
CELL8.IMUX_D7CLK_EDGE.INT_IN_2
CELL9.IMUX_D7CLK_EDGE.INT_IN_3
CELL10.IMUX_CLK1CLK_EDGE.INT_IN_4
CELL11.IMUX_CLK1CLK_EDGE.INT_IN_6

Tile CLK_W_L

Cells: 14

Bel DLLDEL0

ecp5 CLK_W_L bel DLLDEL0
PinDirectionWires
CFLAGoutputCELL1.OUT_Q7
DIRECTIONinputCELL1.IMUX_D6
LOADNinputCELL1.IMUX_B6
MOVEinputCELL1.IMUX_C6

Bel DLLDEL1

ecp5 CLK_W_L bel DLLDEL1
PinDirectionWires
CFLAGoutputCELL0.OUT_Q7
DIRECTIONinputCELL0.IMUX_D6
LOADNinputCELL0.IMUX_B6
MOVEinputCELL0.IMUX_C6

Bel DLLDEL2

ecp5 CLK_W_L bel DLLDEL2
PinDirectionWires
CFLAGoutputCELL3.OUT_Q7
DIRECTIONinputCELL3.IMUX_D6
LOADNinputCELL3.IMUX_B6
MOVEinputCELL3.IMUX_C6

Bel DLLDEL3

ecp5 CLK_W_L bel DLLDEL3
PinDirectionWires
CFLAGoutputCELL2.OUT_Q7
DIRECTIONinputCELL2.IMUX_D6
LOADNinputCELL2.IMUX_B6
MOVEinputCELL2.IMUX_C6

Bel CLKDIV0

ecp5 CLK_W_L bel CLKDIV0
PinDirectionWires
ALIGNWDinputCELL4.IMUX_A3
CDIVXoutputCELL4.OUT_F2
RSTinputCELL4.IMUX_LSR0

Bel CLKDIV1

ecp5 CLK_W_L bel CLKDIV1
PinDirectionWires
ALIGNWDinputCELL4.IMUX_B3
CDIVXoutputCELL4.OUT_F3
RSTinputCELL4.IMUX_LSR1

Bel DCC0

ecp5 CLK_W_L bel DCC0
PinDirectionWires
CEinputCELL5.IMUX_C1

Bel DCC1

ecp5 CLK_W_L bel DCC1
PinDirectionWires
CEinputCELL5.IMUX_B0

Bel DCC2

ecp5 CLK_W_L bel DCC2
PinDirectionWires
CEinputCELL5.IMUX_C2

Bel DCC3

ecp5 CLK_W_L bel DCC3
PinDirectionWires
CEinputCELL5.IMUX_A3

Bel DCC4

ecp5 CLK_W_L bel DCC4
PinDirectionWires
CEinputCELL5.IMUX_D1

Bel DCC5

ecp5 CLK_W_L bel DCC5
PinDirectionWires
CEinputCELL5.IMUX_B1

Bel DCC6

ecp5 CLK_W_L bel DCC6
PinDirectionWires
CEinputCELL5.IMUX_A4

Bel DCC7

ecp5 CLK_W_L bel DCC7
PinDirectionWires
CEinputCELL5.IMUX_B2

Bel DCC8

ecp5 CLK_W_L bel DCC8
PinDirectionWires
CEinputCELL5.IMUX_A1

Bel DCC9

ecp5 CLK_W_L bel DCC9
PinDirectionWires
CEinputCELL5.IMUX_A0

Bel DCC10

ecp5 CLK_W_L bel DCC10
PinDirectionWires
CEinputCELL5.IMUX_D2

Bel DCC11

ecp5 CLK_W_L bel DCC11
PinDirectionWires
CEinputCELL5.IMUX_C3

Bel DCC12

ecp5 CLK_W_L bel DCC12
PinDirectionWires
CEinputCELL5.IMUX_A2

Bel DCC13

ecp5 CLK_W_L bel DCC13
PinDirectionWires
CEinputCELL5.IMUX_C0

Bel ECLKBRIDGECS0

ecp5 CLK_W_L bel ECLKBRIDGECS0
PinDirectionWires
SELinputCELL4.IMUX_A6

Bel BRGECLKSYNC0

ecp5 CLK_W_L bel BRGECLKSYNC0
PinDirectionWires
STOPinputCELL4.IMUX_A7

Bel CLK_EDGE

ecp5 CLK_W_L bel CLK_EDGE
PinDirectionWires
INT_IN_0inputCELL6.IMUX_D7
INT_IN_1inputCELL7.IMUX_D7
INT_IN_2inputCELL8.IMUX_D7
INT_IN_3inputCELL9.IMUX_D7
INT_IN_4inputCELL10.IMUX_CLK1
INT_IN_5inputCELL11.IMUX_CLK1
INT_IN_6inputCELL12.IMUX_CLK1
INT_IN_7inputCELL13.IMUX_CLK1

Bel CLKTEST

ecp5 CLK_W_L bel CLKTEST
PinDirectionWires
TESTIN0inputCELL5.IMUX_C4
TESTIN1inputCELL5.IMUX_A5
TESTIN2inputCELL5.IMUX_C5

Bel ECLKSYNC0

ecp5 CLK_W_L bel ECLKSYNC0
PinDirectionWires
ECLKoutputCELL5.OUT_F0
ECLKI_NinputCELL3.IMUX_CLK0
ECLKI_SinputCELL0.IMUX_CLK0
STOPinputCELL4.IMUX_C0

Bel ECLKSYNC1

ecp5 CLK_W_L bel ECLKSYNC1
PinDirectionWires
ECLKoutputCELL5.OUT_F1
ECLKI_NinputCELL3.IMUX_CLK1
ECLKI_SinputCELL0.IMUX_CLK1
STOPinputCELL4.IMUX_D0

Bel ECLKSYNC2

ecp5 CLK_W_L bel ECLKSYNC2
PinDirectionWires
ECLKoutputCELL4.OUT_F0
ECLKI_NinputCELL3.IMUX_CLK0
ECLKI_SinputCELL0.IMUX_CLK0
STOPinputCELL4.IMUX_A0

Bel ECLKSYNC3

ecp5 CLK_W_L bel ECLKSYNC3
PinDirectionWires
ECLKoutputCELL4.OUT_F1
ECLKI_NinputCELL3.IMUX_CLK1
ECLKI_SinputCELL0.IMUX_CLK1
STOPinputCELL4.IMUX_B0

Bel CLKTEST_ECLK

ecp5 CLK_W_L bel CLKTEST_ECLK
PinDirectionWires
TESTIN0inputCELL4.IMUX_A4
TESTIN1inputCELL4.IMUX_B4
TESTIN2inputCELL4.IMUX_C4
TESTIN3inputCELL4.IMUX_A5
TESTIN4inputCELL4.IMUX_B5
TESTIN5inputCELL4.IMUX_C5

Bel wires

ecp5 CLK_W_L bel wires
WirePins
CELL0.IMUX_B6DLLDEL1.LOADN
CELL0.IMUX_C6DLLDEL1.MOVE
CELL0.IMUX_D6DLLDEL1.DIRECTION
CELL0.IMUX_CLK0ECLKSYNC0.ECLKI_S, ECLKSYNC2.ECLKI_S
CELL0.IMUX_CLK1ECLKSYNC1.ECLKI_S, ECLKSYNC3.ECLKI_S
CELL0.OUT_Q7DLLDEL1.CFLAG
CELL1.IMUX_B6DLLDEL0.LOADN
CELL1.IMUX_C6DLLDEL0.MOVE
CELL1.IMUX_D6DLLDEL0.DIRECTION
CELL1.OUT_Q7DLLDEL0.CFLAG
CELL2.IMUX_B6DLLDEL3.LOADN
CELL2.IMUX_C6DLLDEL3.MOVE
CELL2.IMUX_D6DLLDEL3.DIRECTION
CELL2.OUT_Q7DLLDEL3.CFLAG
CELL3.IMUX_B6DLLDEL2.LOADN
CELL3.IMUX_C6DLLDEL2.MOVE
CELL3.IMUX_D6DLLDEL2.DIRECTION
CELL3.IMUX_CLK0ECLKSYNC0.ECLKI_N, ECLKSYNC2.ECLKI_N
CELL3.IMUX_CLK1ECLKSYNC1.ECLKI_N, ECLKSYNC3.ECLKI_N
CELL3.OUT_Q7DLLDEL2.CFLAG
CELL4.IMUX_A0ECLKSYNC2.STOP
CELL4.IMUX_A3CLKDIV0.ALIGNWD
CELL4.IMUX_A4CLKTEST_ECLK.TESTIN0
CELL4.IMUX_A5CLKTEST_ECLK.TESTIN3
CELL4.IMUX_A6ECLKBRIDGECS0.SEL
CELL4.IMUX_A7BRGECLKSYNC0.STOP
CELL4.IMUX_B0ECLKSYNC3.STOP
CELL4.IMUX_B3CLKDIV1.ALIGNWD
CELL4.IMUX_B4CLKTEST_ECLK.TESTIN1
CELL4.IMUX_B5CLKTEST_ECLK.TESTIN4
CELL4.IMUX_C0ECLKSYNC0.STOP
CELL4.IMUX_C4CLKTEST_ECLK.TESTIN2
CELL4.IMUX_C5CLKTEST_ECLK.TESTIN5
CELL4.IMUX_D0ECLKSYNC1.STOP
CELL4.IMUX_LSR0CLKDIV0.RST
CELL4.IMUX_LSR1CLKDIV1.RST
CELL4.OUT_F0ECLKSYNC2.ECLK
CELL4.OUT_F1ECLKSYNC3.ECLK
CELL4.OUT_F2CLKDIV0.CDIVX
CELL4.OUT_F3CLKDIV1.CDIVX
CELL5.IMUX_A0DCC9.CE
CELL5.IMUX_A1DCC8.CE
CELL5.IMUX_A2DCC12.CE
CELL5.IMUX_A3DCC3.CE
CELL5.IMUX_A4DCC6.CE
CELL5.IMUX_A5CLKTEST.TESTIN1
CELL5.IMUX_B0DCC1.CE
CELL5.IMUX_B1DCC5.CE
CELL5.IMUX_B2DCC7.CE
CELL5.IMUX_C0DCC13.CE
CELL5.IMUX_C1DCC0.CE
CELL5.IMUX_C2DCC2.CE
CELL5.IMUX_C3DCC11.CE
CELL5.IMUX_C4CLKTEST.TESTIN0
CELL5.IMUX_C5CLKTEST.TESTIN2
CELL5.IMUX_D1DCC4.CE
CELL5.IMUX_D2DCC10.CE
CELL5.OUT_F0ECLKSYNC0.ECLK
CELL5.OUT_F1ECLKSYNC1.ECLK
CELL6.IMUX_D7CLK_EDGE.INT_IN_0
CELL7.IMUX_D7CLK_EDGE.INT_IN_1
CELL8.IMUX_D7CLK_EDGE.INT_IN_2
CELL9.IMUX_D7CLK_EDGE.INT_IN_3
CELL10.IMUX_CLK1CLK_EDGE.INT_IN_4
CELL11.IMUX_CLK1CLK_EDGE.INT_IN_5
CELL12.IMUX_CLK1CLK_EDGE.INT_IN_6
CELL13.IMUX_CLK1CLK_EDGE.INT_IN_7

Tile CLK_E_S

Cells: 12

Bel DLLDEL0

ecp5 CLK_E_S bel DLLDEL0
PinDirectionWires
CFLAGoutputCELL1.OUT_Q7
DIRECTIONinputCELL1.IMUX_D6
LOADNinputCELL1.IMUX_B6
MOVEinputCELL1.IMUX_C6

Bel DLLDEL1

ecp5 CLK_E_S bel DLLDEL1
PinDirectionWires
CFLAGoutputCELL0.OUT_Q7
DIRECTIONinputCELL0.IMUX_D6
LOADNinputCELL0.IMUX_B6
MOVEinputCELL0.IMUX_C6

Bel DLLDEL2

ecp5 CLK_E_S bel DLLDEL2
PinDirectionWires
CFLAGoutputCELL3.OUT_Q7
DIRECTIONinputCELL3.IMUX_D6
LOADNinputCELL3.IMUX_B6
MOVEinputCELL3.IMUX_C6

Bel DLLDEL3

ecp5 CLK_E_S bel DLLDEL3
PinDirectionWires
CFLAGoutputCELL2.OUT_Q7
DIRECTIONinputCELL2.IMUX_D6
LOADNinputCELL2.IMUX_B6
MOVEinputCELL2.IMUX_C6

Bel CLKDIV0

ecp5 CLK_E_S bel CLKDIV0
PinDirectionWires
ALIGNWDinputCELL4.IMUX_A3
CDIVXoutputCELL4.OUT_F2
RSTinputCELL4.IMUX_LSR0

Bel CLKDIV1

ecp5 CLK_E_S bel CLKDIV1
PinDirectionWires
ALIGNWDinputCELL4.IMUX_B3
CDIVXoutputCELL4.OUT_F3
RSTinputCELL4.IMUX_LSR1

Bel DCC0

ecp5 CLK_E_S bel DCC0
PinDirectionWires
CEinputCELL5.IMUX_C1

Bel DCC1

ecp5 CLK_E_S bel DCC1
PinDirectionWires
CEinputCELL5.IMUX_B0

Bel DCC2

ecp5 CLK_E_S bel DCC2
PinDirectionWires
CEinputCELL5.IMUX_C2

Bel DCC3

ecp5 CLK_E_S bel DCC3
PinDirectionWires
CEinputCELL5.IMUX_A3

Bel DCC4

ecp5 CLK_E_S bel DCC4
PinDirectionWires
CEinputCELL5.IMUX_D1

Bel DCC5

ecp5 CLK_E_S bel DCC5
PinDirectionWires
CEinputCELL5.IMUX_B1

Bel DCC6

ecp5 CLK_E_S bel DCC6
PinDirectionWires
CEinputCELL5.IMUX_A4

Bel DCC7

ecp5 CLK_E_S bel DCC7
PinDirectionWires
CEinputCELL5.IMUX_B2

Bel DCC8

ecp5 CLK_E_S bel DCC8
PinDirectionWires
CEinputCELL5.IMUX_A1

Bel DCC9

ecp5 CLK_E_S bel DCC9
PinDirectionWires
CEinputCELL5.IMUX_A0

Bel DCC10

ecp5 CLK_E_S bel DCC10
PinDirectionWires
CEinputCELL5.IMUX_D2

Bel DCC11

ecp5 CLK_E_S bel DCC11
PinDirectionWires
CEinputCELL5.IMUX_C3

Bel DCC12

ecp5 CLK_E_S bel DCC12
PinDirectionWires
CEinputCELL5.IMUX_A2

Bel DCC13

ecp5 CLK_E_S bel DCC13
PinDirectionWires
CEinputCELL5.IMUX_C0

Bel ECLKBRIDGECS0

ecp5 CLK_E_S bel ECLKBRIDGECS0
PinDirectionWires
SELinputCELL4.IMUX_A6

Bel BRGECLKSYNC0

ecp5 CLK_E_S bel BRGECLKSYNC0
PinDirectionWires
STOPinputCELL4.IMUX_A7

Bel CLK_EDGE

ecp5 CLK_E_S bel CLK_EDGE
PinDirectionWires
INT_IN_0inputCELL6.IMUX_D7
INT_IN_1inputCELL7.IMUX_D7
INT_IN_2inputCELL8.IMUX_D7
INT_IN_3inputCELL9.IMUX_D7
INT_IN_4inputCELL10.IMUX_CLK1
INT_IN_6inputCELL11.IMUX_CLK1

Bel CLKTEST

ecp5 CLK_E_S bel CLKTEST
PinDirectionWires
TESTIN0inputCELL5.IMUX_C4
TESTIN1inputCELL5.IMUX_A5
TESTIN2inputCELL5.IMUX_C5

Bel ECLKSYNC0

ecp5 CLK_E_S bel ECLKSYNC0
PinDirectionWires
ECLKoutputCELL5.OUT_F0
ECLKI_NinputCELL3.IMUX_CLK0
ECLKI_SinputCELL0.IMUX_CLK0
STOPinputCELL4.IMUX_C0

Bel ECLKSYNC1

ecp5 CLK_E_S bel ECLKSYNC1
PinDirectionWires
ECLKoutputCELL5.OUT_F1
ECLKI_NinputCELL3.IMUX_CLK1
ECLKI_SinputCELL0.IMUX_CLK1
STOPinputCELL4.IMUX_D0

Bel ECLKSYNC2

ecp5 CLK_E_S bel ECLKSYNC2
PinDirectionWires
ECLKoutputCELL4.OUT_F0
ECLKI_NinputCELL3.IMUX_CLK0
ECLKI_SinputCELL0.IMUX_CLK0
STOPinputCELL4.IMUX_A0

Bel ECLKSYNC3

ecp5 CLK_E_S bel ECLKSYNC3
PinDirectionWires
ECLKoutputCELL4.OUT_F1
ECLKI_NinputCELL3.IMUX_CLK1
ECLKI_SinputCELL0.IMUX_CLK1
STOPinputCELL4.IMUX_B0

Bel CLKTEST_ECLK

ecp5 CLK_E_S bel CLKTEST_ECLK
PinDirectionWires
TESTIN0inputCELL4.IMUX_A4
TESTIN1inputCELL4.IMUX_B4
TESTIN2inputCELL4.IMUX_C4
TESTIN3inputCELL4.IMUX_A5
TESTIN4inputCELL4.IMUX_B5
TESTIN5inputCELL4.IMUX_C5

Bel wires

ecp5 CLK_E_S bel wires
WirePins
CELL0.IMUX_B6DLLDEL1.LOADN
CELL0.IMUX_C6DLLDEL1.MOVE
CELL0.IMUX_D6DLLDEL1.DIRECTION
CELL0.IMUX_CLK0ECLKSYNC0.ECLKI_S, ECLKSYNC2.ECLKI_S
CELL0.IMUX_CLK1ECLKSYNC1.ECLKI_S, ECLKSYNC3.ECLKI_S
CELL0.OUT_Q7DLLDEL1.CFLAG
CELL1.IMUX_B6DLLDEL0.LOADN
CELL1.IMUX_C6DLLDEL0.MOVE
CELL1.IMUX_D6DLLDEL0.DIRECTION
CELL1.OUT_Q7DLLDEL0.CFLAG
CELL2.IMUX_B6DLLDEL3.LOADN
CELL2.IMUX_C6DLLDEL3.MOVE
CELL2.IMUX_D6DLLDEL3.DIRECTION
CELL2.OUT_Q7DLLDEL3.CFLAG
CELL3.IMUX_B6DLLDEL2.LOADN
CELL3.IMUX_C6DLLDEL2.MOVE
CELL3.IMUX_D6DLLDEL2.DIRECTION
CELL3.IMUX_CLK0ECLKSYNC0.ECLKI_N, ECLKSYNC2.ECLKI_N
CELL3.IMUX_CLK1ECLKSYNC1.ECLKI_N, ECLKSYNC3.ECLKI_N
CELL3.OUT_Q7DLLDEL2.CFLAG
CELL4.IMUX_A0ECLKSYNC2.STOP
CELL4.IMUX_A3CLKDIV0.ALIGNWD
CELL4.IMUX_A4CLKTEST_ECLK.TESTIN0
CELL4.IMUX_A5CLKTEST_ECLK.TESTIN3
CELL4.IMUX_A6ECLKBRIDGECS0.SEL
CELL4.IMUX_A7BRGECLKSYNC0.STOP
CELL4.IMUX_B0ECLKSYNC3.STOP
CELL4.IMUX_B3CLKDIV1.ALIGNWD
CELL4.IMUX_B4CLKTEST_ECLK.TESTIN1
CELL4.IMUX_B5CLKTEST_ECLK.TESTIN4
CELL4.IMUX_C0ECLKSYNC0.STOP
CELL4.IMUX_C4CLKTEST_ECLK.TESTIN2
CELL4.IMUX_C5CLKTEST_ECLK.TESTIN5
CELL4.IMUX_D0ECLKSYNC1.STOP
CELL4.IMUX_LSR0CLKDIV0.RST
CELL4.IMUX_LSR1CLKDIV1.RST
CELL4.OUT_F0ECLKSYNC2.ECLK
CELL4.OUT_F1ECLKSYNC3.ECLK
CELL4.OUT_F2CLKDIV0.CDIVX
CELL4.OUT_F3CLKDIV1.CDIVX
CELL5.IMUX_A0DCC9.CE
CELL5.IMUX_A1DCC8.CE
CELL5.IMUX_A2DCC12.CE
CELL5.IMUX_A3DCC3.CE
CELL5.IMUX_A4DCC6.CE
CELL5.IMUX_A5CLKTEST.TESTIN1
CELL5.IMUX_B0DCC1.CE
CELL5.IMUX_B1DCC5.CE
CELL5.IMUX_B2DCC7.CE
CELL5.IMUX_C0DCC13.CE
CELL5.IMUX_C1DCC0.CE
CELL5.IMUX_C2DCC2.CE
CELL5.IMUX_C3DCC11.CE
CELL5.IMUX_C4CLKTEST.TESTIN0
CELL5.IMUX_C5CLKTEST.TESTIN2
CELL5.IMUX_D1DCC4.CE
CELL5.IMUX_D2DCC10.CE
CELL5.OUT_F0ECLKSYNC0.ECLK
CELL5.OUT_F1ECLKSYNC1.ECLK
CELL6.IMUX_D7CLK_EDGE.INT_IN_0
CELL7.IMUX_D7CLK_EDGE.INT_IN_1
CELL8.IMUX_D7CLK_EDGE.INT_IN_2
CELL9.IMUX_D7CLK_EDGE.INT_IN_3
CELL10.IMUX_CLK1CLK_EDGE.INT_IN_4
CELL11.IMUX_CLK1CLK_EDGE.INT_IN_6

Tile CLK_E_L

Cells: 14

Bel DLLDEL0

ecp5 CLK_E_L bel DLLDEL0
PinDirectionWires
CFLAGoutputCELL1.OUT_Q7
DIRECTIONinputCELL1.IMUX_D6
LOADNinputCELL1.IMUX_B6
MOVEinputCELL1.IMUX_C6

Bel DLLDEL1

ecp5 CLK_E_L bel DLLDEL1
PinDirectionWires
CFLAGoutputCELL0.OUT_Q7
DIRECTIONinputCELL0.IMUX_D6
LOADNinputCELL0.IMUX_B6
MOVEinputCELL0.IMUX_C6

Bel DLLDEL2

ecp5 CLK_E_L bel DLLDEL2
PinDirectionWires
CFLAGoutputCELL3.OUT_Q7
DIRECTIONinputCELL3.IMUX_D6
LOADNinputCELL3.IMUX_B6
MOVEinputCELL3.IMUX_C6

Bel DLLDEL3

ecp5 CLK_E_L bel DLLDEL3
PinDirectionWires
CFLAGoutputCELL2.OUT_Q7
DIRECTIONinputCELL2.IMUX_D6
LOADNinputCELL2.IMUX_B6
MOVEinputCELL2.IMUX_C6

Bel CLKDIV0

ecp5 CLK_E_L bel CLKDIV0
PinDirectionWires
ALIGNWDinputCELL4.IMUX_A3
CDIVXoutputCELL4.OUT_F2
RSTinputCELL4.IMUX_LSR0

Bel CLKDIV1

ecp5 CLK_E_L bel CLKDIV1
PinDirectionWires
ALIGNWDinputCELL4.IMUX_B3
CDIVXoutputCELL4.OUT_F3
RSTinputCELL4.IMUX_LSR1

Bel DCC0

ecp5 CLK_E_L bel DCC0
PinDirectionWires
CEinputCELL5.IMUX_C1

Bel DCC1

ecp5 CLK_E_L bel DCC1
PinDirectionWires
CEinputCELL5.IMUX_B0

Bel DCC2

ecp5 CLK_E_L bel DCC2
PinDirectionWires
CEinputCELL5.IMUX_C2

Bel DCC3

ecp5 CLK_E_L bel DCC3
PinDirectionWires
CEinputCELL5.IMUX_A3

Bel DCC4

ecp5 CLK_E_L bel DCC4
PinDirectionWires
CEinputCELL5.IMUX_D1

Bel DCC5

ecp5 CLK_E_L bel DCC5
PinDirectionWires
CEinputCELL5.IMUX_B1

Bel DCC6

ecp5 CLK_E_L bel DCC6
PinDirectionWires
CEinputCELL5.IMUX_A4

Bel DCC7

ecp5 CLK_E_L bel DCC7
PinDirectionWires
CEinputCELL5.IMUX_B2

Bel DCC8

ecp5 CLK_E_L bel DCC8
PinDirectionWires
CEinputCELL5.IMUX_A1

Bel DCC9

ecp5 CLK_E_L bel DCC9
PinDirectionWires
CEinputCELL5.IMUX_A0

Bel DCC10

ecp5 CLK_E_L bel DCC10
PinDirectionWires
CEinputCELL5.IMUX_D2

Bel DCC11

ecp5 CLK_E_L bel DCC11
PinDirectionWires
CEinputCELL5.IMUX_C3

Bel DCC12

ecp5 CLK_E_L bel DCC12
PinDirectionWires
CEinputCELL5.IMUX_A2

Bel DCC13

ecp5 CLK_E_L bel DCC13
PinDirectionWires
CEinputCELL5.IMUX_C0

Bel ECLKBRIDGECS0

ecp5 CLK_E_L bel ECLKBRIDGECS0
PinDirectionWires
SELinputCELL4.IMUX_A6

Bel BRGECLKSYNC0

ecp5 CLK_E_L bel BRGECLKSYNC0
PinDirectionWires
STOPinputCELL4.IMUX_A7

Bel CLK_EDGE

ecp5 CLK_E_L bel CLK_EDGE
PinDirectionWires
INT_IN_0inputCELL6.IMUX_D7
INT_IN_1inputCELL7.IMUX_D7
INT_IN_2inputCELL8.IMUX_D7
INT_IN_3inputCELL9.IMUX_D7
INT_IN_4inputCELL10.IMUX_CLK1
INT_IN_5inputCELL11.IMUX_CLK1
INT_IN_6inputCELL12.IMUX_CLK1
INT_IN_7inputCELL13.IMUX_CLK1

Bel CLKTEST

ecp5 CLK_E_L bel CLKTEST
PinDirectionWires
TESTIN0inputCELL5.IMUX_C4
TESTIN1inputCELL5.IMUX_A5
TESTIN2inputCELL5.IMUX_C5

Bel ECLKSYNC0

ecp5 CLK_E_L bel ECLKSYNC0
PinDirectionWires
ECLKoutputCELL5.OUT_F0
ECLKI_NinputCELL3.IMUX_CLK0
ECLKI_SinputCELL0.IMUX_CLK0
STOPinputCELL4.IMUX_C0

Bel ECLKSYNC1

ecp5 CLK_E_L bel ECLKSYNC1
PinDirectionWires
ECLKoutputCELL5.OUT_F1
ECLKI_NinputCELL3.IMUX_CLK1
ECLKI_SinputCELL0.IMUX_CLK1
STOPinputCELL4.IMUX_D0

Bel ECLKSYNC2

ecp5 CLK_E_L bel ECLKSYNC2
PinDirectionWires
ECLKoutputCELL4.OUT_F0
ECLKI_NinputCELL3.IMUX_CLK0
ECLKI_SinputCELL0.IMUX_CLK0
STOPinputCELL4.IMUX_A0

Bel ECLKSYNC3

ecp5 CLK_E_L bel ECLKSYNC3
PinDirectionWires
ECLKoutputCELL4.OUT_F1
ECLKI_NinputCELL3.IMUX_CLK1
ECLKI_SinputCELL0.IMUX_CLK1
STOPinputCELL4.IMUX_B0

Bel CLKTEST_ECLK

ecp5 CLK_E_L bel CLKTEST_ECLK
PinDirectionWires
TESTIN0inputCELL4.IMUX_A4
TESTIN1inputCELL4.IMUX_B4
TESTIN2inputCELL4.IMUX_C4
TESTIN3inputCELL4.IMUX_A5
TESTIN4inputCELL4.IMUX_B5
TESTIN5inputCELL4.IMUX_C5

Bel wires

ecp5 CLK_E_L bel wires
WirePins
CELL0.IMUX_B6DLLDEL1.LOADN
CELL0.IMUX_C6DLLDEL1.MOVE
CELL0.IMUX_D6DLLDEL1.DIRECTION
CELL0.IMUX_CLK0ECLKSYNC0.ECLKI_S, ECLKSYNC2.ECLKI_S
CELL0.IMUX_CLK1ECLKSYNC1.ECLKI_S, ECLKSYNC3.ECLKI_S
CELL0.OUT_Q7DLLDEL1.CFLAG
CELL1.IMUX_B6DLLDEL0.LOADN
CELL1.IMUX_C6DLLDEL0.MOVE
CELL1.IMUX_D6DLLDEL0.DIRECTION
CELL1.OUT_Q7DLLDEL0.CFLAG
CELL2.IMUX_B6DLLDEL3.LOADN
CELL2.IMUX_C6DLLDEL3.MOVE
CELL2.IMUX_D6DLLDEL3.DIRECTION
CELL2.OUT_Q7DLLDEL3.CFLAG
CELL3.IMUX_B6DLLDEL2.LOADN
CELL3.IMUX_C6DLLDEL2.MOVE
CELL3.IMUX_D6DLLDEL2.DIRECTION
CELL3.IMUX_CLK0ECLKSYNC0.ECLKI_N, ECLKSYNC2.ECLKI_N
CELL3.IMUX_CLK1ECLKSYNC1.ECLKI_N, ECLKSYNC3.ECLKI_N
CELL3.OUT_Q7DLLDEL2.CFLAG
CELL4.IMUX_A0ECLKSYNC2.STOP
CELL4.IMUX_A3CLKDIV0.ALIGNWD
CELL4.IMUX_A4CLKTEST_ECLK.TESTIN0
CELL4.IMUX_A5CLKTEST_ECLK.TESTIN3
CELL4.IMUX_A6ECLKBRIDGECS0.SEL
CELL4.IMUX_A7BRGECLKSYNC0.STOP
CELL4.IMUX_B0ECLKSYNC3.STOP
CELL4.IMUX_B3CLKDIV1.ALIGNWD
CELL4.IMUX_B4CLKTEST_ECLK.TESTIN1
CELL4.IMUX_B5CLKTEST_ECLK.TESTIN4
CELL4.IMUX_C0ECLKSYNC0.STOP
CELL4.IMUX_C4CLKTEST_ECLK.TESTIN2
CELL4.IMUX_C5CLKTEST_ECLK.TESTIN5
CELL4.IMUX_D0ECLKSYNC1.STOP
CELL4.IMUX_LSR0CLKDIV0.RST
CELL4.IMUX_LSR1CLKDIV1.RST
CELL4.OUT_F0ECLKSYNC2.ECLK
CELL4.OUT_F1ECLKSYNC3.ECLK
CELL4.OUT_F2CLKDIV0.CDIVX
CELL4.OUT_F3CLKDIV1.CDIVX
CELL5.IMUX_A0DCC9.CE
CELL5.IMUX_A1DCC8.CE
CELL5.IMUX_A2DCC12.CE
CELL5.IMUX_A3DCC3.CE
CELL5.IMUX_A4DCC6.CE
CELL5.IMUX_A5CLKTEST.TESTIN1
CELL5.IMUX_B0DCC1.CE
CELL5.IMUX_B1DCC5.CE
CELL5.IMUX_B2DCC7.CE
CELL5.IMUX_C0DCC13.CE
CELL5.IMUX_C1DCC0.CE
CELL5.IMUX_C2DCC2.CE
CELL5.IMUX_C3DCC11.CE
CELL5.IMUX_C4CLKTEST.TESTIN0
CELL5.IMUX_C5CLKTEST.TESTIN2
CELL5.IMUX_D1DCC4.CE
CELL5.IMUX_D2DCC10.CE
CELL5.OUT_F0ECLKSYNC0.ECLK
CELL5.OUT_F1ECLKSYNC1.ECLK
CELL6.IMUX_D7CLK_EDGE.INT_IN_0
CELL7.IMUX_D7CLK_EDGE.INT_IN_1
CELL8.IMUX_D7CLK_EDGE.INT_IN_2
CELL9.IMUX_D7CLK_EDGE.INT_IN_3
CELL10.IMUX_CLK1CLK_EDGE.INT_IN_4
CELL11.IMUX_CLK1CLK_EDGE.INT_IN_5
CELL12.IMUX_CLK1CLK_EDGE.INT_IN_6
CELL13.IMUX_CLK1CLK_EDGE.INT_IN_7

Tile CLK_S_S

Cells: 8

Bel PCSCLKDIV0

ecp5 CLK_S_S bel PCSCLKDIV0
PinDirectionWires
CLKIinputCELL0.IMUX_CLK0
RSTinputCELL0.IMUX_LSR0
SEL0inputCELL0.IMUX_A4
SEL1inputCELL0.IMUX_A5
SEL2inputCELL0.IMUX_A6

Bel PCSCLKDIV1

ecp5 CLK_S_S bel PCSCLKDIV1
PinDirectionWires
CLKIinputCELL1.IMUX_CLK1
RSTinputCELL1.IMUX_LSR1
SEL0inputCELL1.IMUX_B4
SEL1inputCELL1.IMUX_B5
SEL2inputCELL1.IMUX_B6

Bel DCC0

ecp5 CLK_S_S bel DCC0
PinDirectionWires
CEinputCELL0.IMUX_B0

Bel DCC1

ecp5 CLK_S_S bel DCC1
PinDirectionWires
CEinputCELL0.IMUX_B1

Bel DCC2

ecp5 CLK_S_S bel DCC2
PinDirectionWires
CEinputCELL0.IMUX_B2

Bel DCC3

ecp5 CLK_S_S bel DCC3
PinDirectionWires
CEinputCELL0.IMUX_B3

Bel DCC4

ecp5 CLK_S_S bel DCC4
PinDirectionWires
CEinputCELL0.IMUX_B4

Bel DCC5

ecp5 CLK_S_S bel DCC5
PinDirectionWires
CEinputCELL0.IMUX_B5

Bel DCC6

ecp5 CLK_S_S bel DCC6
PinDirectionWires
CEinputCELL0.IMUX_B6

Bel DCC7

ecp5 CLK_S_S bel DCC7
PinDirectionWires
CEinputCELL0.IMUX_B7

Bel DCC8

ecp5 CLK_S_S bel DCC8
PinDirectionWires
CEinputCELL1.IMUX_A0

Bel DCC9

ecp5 CLK_S_S bel DCC9
PinDirectionWires
CEinputCELL1.IMUX_A1

Bel DCC10

ecp5 CLK_S_S bel DCC10
PinDirectionWires
CEinputCELL1.IMUX_A2

Bel DCC11

ecp5 CLK_S_S bel DCC11
PinDirectionWires
CEinputCELL1.IMUX_A3

Bel DCC12

ecp5 CLK_S_S bel DCC12
PinDirectionWires
CEinputCELL1.IMUX_A4

Bel DCC13

ecp5 CLK_S_S bel DCC13
PinDirectionWires
CEinputCELL1.IMUX_A5

Bel DCC14

ecp5 CLK_S_S bel DCC14
PinDirectionWires
CEinputCELL1.IMUX_A6

Bel DCC15

ecp5 CLK_S_S bel DCC15
PinDirectionWires
CEinputCELL1.IMUX_A7

Bel CLK_EDGE

ecp5 CLK_S_S bel CLK_EDGE
PinDirectionWires
INT_IN_0inputCELL2.IMUX_D7
INT_IN_1inputCELL3.IMUX_D7
INT_IN_2inputCELL4.IMUX_D7
INT_IN_3inputCELL5.IMUX_D7
INT_IN_4inputCELL6.IMUX_CLK1
INT_IN_6inputCELL7.IMUX_CLK1

Bel CLKTEST

ecp5 CLK_S_S bel CLKTEST
PinDirectionWires
TESTIN0inputCELL0.IMUX_A0
TESTIN1inputCELL0.IMUX_A1
TESTIN2inputCELL0.IMUX_A2
TESTIN3inputCELL0.IMUX_A3

Bel wires

ecp5 CLK_S_S bel wires
WirePins
CELL0.IMUX_A0CLKTEST.TESTIN0
CELL0.IMUX_A1CLKTEST.TESTIN1
CELL0.IMUX_A2CLKTEST.TESTIN2
CELL0.IMUX_A3CLKTEST.TESTIN3
CELL0.IMUX_A4PCSCLKDIV0.SEL0
CELL0.IMUX_A5PCSCLKDIV0.SEL1
CELL0.IMUX_A6PCSCLKDIV0.SEL2
CELL0.IMUX_B0DCC0.CE
CELL0.IMUX_B1DCC1.CE
CELL0.IMUX_B2DCC2.CE
CELL0.IMUX_B3DCC3.CE
CELL0.IMUX_B4DCC4.CE
CELL0.IMUX_B5DCC5.CE
CELL0.IMUX_B6DCC6.CE
CELL0.IMUX_B7DCC7.CE
CELL0.IMUX_CLK0PCSCLKDIV0.CLKI
CELL0.IMUX_LSR0PCSCLKDIV0.RST
CELL1.IMUX_A0DCC8.CE
CELL1.IMUX_A1DCC9.CE
CELL1.IMUX_A2DCC10.CE
CELL1.IMUX_A3DCC11.CE
CELL1.IMUX_A4DCC12.CE
CELL1.IMUX_A5DCC13.CE
CELL1.IMUX_A6DCC14.CE
CELL1.IMUX_A7DCC15.CE
CELL1.IMUX_B4PCSCLKDIV1.SEL0
CELL1.IMUX_B5PCSCLKDIV1.SEL1
CELL1.IMUX_B6PCSCLKDIV1.SEL2
CELL1.IMUX_CLK1PCSCLKDIV1.CLKI
CELL1.IMUX_LSR1PCSCLKDIV1.RST
CELL2.IMUX_D7CLK_EDGE.INT_IN_0
CELL3.IMUX_D7CLK_EDGE.INT_IN_1
CELL4.IMUX_D7CLK_EDGE.INT_IN_2
CELL5.IMUX_D7CLK_EDGE.INT_IN_3
CELL6.IMUX_CLK1CLK_EDGE.INT_IN_4
CELL7.IMUX_CLK1CLK_EDGE.INT_IN_6

Tile CLK_S_L

Cells: 10

Bel PCSCLKDIV0

ecp5 CLK_S_L bel PCSCLKDIV0
PinDirectionWires
CLKIinputCELL0.IMUX_CLK0
RSTinputCELL0.IMUX_LSR0
SEL0inputCELL0.IMUX_A4
SEL1inputCELL0.IMUX_A5
SEL2inputCELL0.IMUX_A6

Bel PCSCLKDIV1

ecp5 CLK_S_L bel PCSCLKDIV1
PinDirectionWires
CLKIinputCELL1.IMUX_CLK1
RSTinputCELL1.IMUX_LSR1
SEL0inputCELL1.IMUX_B4
SEL1inputCELL1.IMUX_B5
SEL2inputCELL1.IMUX_B6

Bel DCC0

ecp5 CLK_S_L bel DCC0
PinDirectionWires
CEinputCELL0.IMUX_B0

Bel DCC1

ecp5 CLK_S_L bel DCC1
PinDirectionWires
CEinputCELL0.IMUX_B1

Bel DCC2

ecp5 CLK_S_L bel DCC2
PinDirectionWires
CEinputCELL0.IMUX_B2

Bel DCC3

ecp5 CLK_S_L bel DCC3
PinDirectionWires
CEinputCELL0.IMUX_B3

Bel DCC4

ecp5 CLK_S_L bel DCC4
PinDirectionWires
CEinputCELL0.IMUX_B4

Bel DCC5

ecp5 CLK_S_L bel DCC5
PinDirectionWires
CEinputCELL0.IMUX_B5

Bel DCC6

ecp5 CLK_S_L bel DCC6
PinDirectionWires
CEinputCELL0.IMUX_B6

Bel DCC7

ecp5 CLK_S_L bel DCC7
PinDirectionWires
CEinputCELL0.IMUX_B7

Bel DCC8

ecp5 CLK_S_L bel DCC8
PinDirectionWires
CEinputCELL1.IMUX_A0

Bel DCC9

ecp5 CLK_S_L bel DCC9
PinDirectionWires
CEinputCELL1.IMUX_A1

Bel DCC10

ecp5 CLK_S_L bel DCC10
PinDirectionWires
CEinputCELL1.IMUX_A2

Bel DCC11

ecp5 CLK_S_L bel DCC11
PinDirectionWires
CEinputCELL1.IMUX_A3

Bel DCC12

ecp5 CLK_S_L bel DCC12
PinDirectionWires
CEinputCELL1.IMUX_A4

Bel DCC13

ecp5 CLK_S_L bel DCC13
PinDirectionWires
CEinputCELL1.IMUX_A5

Bel DCC14

ecp5 CLK_S_L bel DCC14
PinDirectionWires
CEinputCELL1.IMUX_A6

Bel DCC15

ecp5 CLK_S_L bel DCC15
PinDirectionWires
CEinputCELL1.IMUX_A7

Bel CLK_EDGE

ecp5 CLK_S_L bel CLK_EDGE
PinDirectionWires
INT_IN_0inputCELL2.IMUX_D7
INT_IN_1inputCELL3.IMUX_D7
INT_IN_2inputCELL4.IMUX_D7
INT_IN_3inputCELL5.IMUX_D7
INT_IN_4inputCELL6.IMUX_CLK1
INT_IN_5inputCELL7.IMUX_CLK1
INT_IN_6inputCELL8.IMUX_CLK1
INT_IN_7inputCELL9.IMUX_CLK1

Bel CLKTEST

ecp5 CLK_S_L bel CLKTEST
PinDirectionWires
TESTIN0inputCELL0.IMUX_A0
TESTIN1inputCELL0.IMUX_A1
TESTIN2inputCELL0.IMUX_A2
TESTIN3inputCELL0.IMUX_A3

Bel wires

ecp5 CLK_S_L bel wires
WirePins
CELL0.IMUX_A0CLKTEST.TESTIN0
CELL0.IMUX_A1CLKTEST.TESTIN1
CELL0.IMUX_A2CLKTEST.TESTIN2
CELL0.IMUX_A3CLKTEST.TESTIN3
CELL0.IMUX_A4PCSCLKDIV0.SEL0
CELL0.IMUX_A5PCSCLKDIV0.SEL1
CELL0.IMUX_A6PCSCLKDIV0.SEL2
CELL0.IMUX_B0DCC0.CE
CELL0.IMUX_B1DCC1.CE
CELL0.IMUX_B2DCC2.CE
CELL0.IMUX_B3DCC3.CE
CELL0.IMUX_B4DCC4.CE
CELL0.IMUX_B5DCC5.CE
CELL0.IMUX_B6DCC6.CE
CELL0.IMUX_B7DCC7.CE
CELL0.IMUX_CLK0PCSCLKDIV0.CLKI
CELL0.IMUX_LSR0PCSCLKDIV0.RST
CELL1.IMUX_A0DCC8.CE
CELL1.IMUX_A1DCC9.CE
CELL1.IMUX_A2DCC10.CE
CELL1.IMUX_A3DCC11.CE
CELL1.IMUX_A4DCC12.CE
CELL1.IMUX_A5DCC13.CE
CELL1.IMUX_A6DCC14.CE
CELL1.IMUX_A7DCC15.CE
CELL1.IMUX_B4PCSCLKDIV1.SEL0
CELL1.IMUX_B5PCSCLKDIV1.SEL1
CELL1.IMUX_B6PCSCLKDIV1.SEL2
CELL1.IMUX_CLK1PCSCLKDIV1.CLKI
CELL1.IMUX_LSR1PCSCLKDIV1.RST
CELL2.IMUX_D7CLK_EDGE.INT_IN_0
CELL3.IMUX_D7CLK_EDGE.INT_IN_1
CELL4.IMUX_D7CLK_EDGE.INT_IN_2
CELL5.IMUX_D7CLK_EDGE.INT_IN_3
CELL6.IMUX_CLK1CLK_EDGE.INT_IN_4
CELL7.IMUX_CLK1CLK_EDGE.INT_IN_5
CELL8.IMUX_CLK1CLK_EDGE.INT_IN_6
CELL9.IMUX_CLK1CLK_EDGE.INT_IN_7

Tile CLK_N_S

Cells: 10

Bel DLLDEL0

ecp5 CLK_N_S bel DLLDEL0
PinDirectionWires
CFLAGoutputCELL0.OUT_Q7
DIRECTIONinputCELL0.IMUX_D6
LOADNinputCELL0.IMUX_B6
MOVEinputCELL0.IMUX_C6

Bel DLLDEL1

ecp5 CLK_N_S bel DLLDEL1
PinDirectionWires
CFLAGoutputCELL1.OUT_Q7
DIRECTIONinputCELL1.IMUX_D6
LOADNinputCELL1.IMUX_B6
MOVEinputCELL1.IMUX_C6

Bel DLLDEL2

ecp5 CLK_N_S bel DLLDEL2
PinDirectionWires
CFLAGoutputCELL2.OUT_Q7
DIRECTIONinputCELL2.IMUX_D6
LOADNinputCELL2.IMUX_B6
MOVEinputCELL2.IMUX_C6

Bel DLLDEL3

ecp5 CLK_N_S bel DLLDEL3
PinDirectionWires
CFLAGoutputCELL3.OUT_Q7
DIRECTIONinputCELL3.IMUX_D6
LOADNinputCELL3.IMUX_B6
MOVEinputCELL3.IMUX_C6

Bel DCC0

ecp5 CLK_N_S bel DCC0
PinDirectionWires
CEinputCELL1.IMUX_A0

Bel DCC1

ecp5 CLK_N_S bel DCC1
PinDirectionWires
CEinputCELL1.IMUX_B0

Bel DCC2

ecp5 CLK_N_S bel DCC2
PinDirectionWires
CEinputCELL1.IMUX_C0

Bel DCC3

ecp5 CLK_N_S bel DCC3
PinDirectionWires
CEinputCELL1.IMUX_D0

Bel DCC4

ecp5 CLK_N_S bel DCC4
PinDirectionWires
CEinputCELL1.IMUX_A1

Bel DCC5

ecp5 CLK_N_S bel DCC5
PinDirectionWires
CEinputCELL1.IMUX_B1

Bel DCC6

ecp5 CLK_N_S bel DCC6
PinDirectionWires
CEinputCELL1.IMUX_C1

Bel DCC7

ecp5 CLK_N_S bel DCC7
PinDirectionWires
CEinputCELL1.IMUX_D1

Bel DCC8

ecp5 CLK_N_S bel DCC8
PinDirectionWires
CEinputCELL1.IMUX_A2

Bel DCC9

ecp5 CLK_N_S bel DCC9
PinDirectionWires
CEinputCELL1.IMUX_B2

Bel DCC10

ecp5 CLK_N_S bel DCC10
PinDirectionWires
CEinputCELL1.IMUX_C2

Bel DCC11

ecp5 CLK_N_S bel DCC11
PinDirectionWires
CEinputCELL1.IMUX_D2

Bel CLK_EDGE

ecp5 CLK_N_S bel CLK_EDGE
PinDirectionWires
INT_IN_0inputCELL4.IMUX_D7
INT_IN_1inputCELL5.IMUX_D7
INT_IN_2inputCELL6.IMUX_D7
INT_IN_3inputCELL7.IMUX_D7
INT_IN_4inputCELL8.IMUX_CLK1
INT_IN_6inputCELL9.IMUX_CLK1

Bel CLKTEST

ecp5 CLK_N_S bel CLKTEST
PinDirectionWires
TESTIN0inputCELL1.IMUX_A5
TESTIN1inputCELL1.IMUX_B5
TESTIN2inputCELL1.IMUX_C5

Bel wires

ecp5 CLK_N_S bel wires
WirePins
CELL0.IMUX_B6DLLDEL0.LOADN
CELL0.IMUX_C6DLLDEL0.MOVE
CELL0.IMUX_D6DLLDEL0.DIRECTION
CELL0.OUT_Q7DLLDEL0.CFLAG
CELL1.IMUX_A0DCC0.CE
CELL1.IMUX_A1DCC4.CE
CELL1.IMUX_A2DCC8.CE
CELL1.IMUX_A5CLKTEST.TESTIN0
CELL1.IMUX_B0DCC1.CE
CELL1.IMUX_B1DCC5.CE
CELL1.IMUX_B2DCC9.CE
CELL1.IMUX_B5CLKTEST.TESTIN1
CELL1.IMUX_B6DLLDEL1.LOADN
CELL1.IMUX_C0DCC2.CE
CELL1.IMUX_C1DCC6.CE
CELL1.IMUX_C2DCC10.CE
CELL1.IMUX_C5CLKTEST.TESTIN2
CELL1.IMUX_C6DLLDEL1.MOVE
CELL1.IMUX_D0DCC3.CE
CELL1.IMUX_D1DCC7.CE
CELL1.IMUX_D2DCC11.CE
CELL1.IMUX_D6DLLDEL1.DIRECTION
CELL1.OUT_Q7DLLDEL1.CFLAG
CELL2.IMUX_B6DLLDEL2.LOADN
CELL2.IMUX_C6DLLDEL2.MOVE
CELL2.IMUX_D6DLLDEL2.DIRECTION
CELL2.OUT_Q7DLLDEL2.CFLAG
CELL3.IMUX_B6DLLDEL3.LOADN
CELL3.IMUX_C6DLLDEL3.MOVE
CELL3.IMUX_D6DLLDEL3.DIRECTION
CELL3.OUT_Q7DLLDEL3.CFLAG
CELL4.IMUX_D7CLK_EDGE.INT_IN_0
CELL5.IMUX_D7CLK_EDGE.INT_IN_1
CELL6.IMUX_D7CLK_EDGE.INT_IN_2
CELL7.IMUX_D7CLK_EDGE.INT_IN_3
CELL8.IMUX_CLK1CLK_EDGE.INT_IN_4
CELL9.IMUX_CLK1CLK_EDGE.INT_IN_6

Tile CLK_N_L

Cells: 12

Bel DLLDEL0

ecp5 CLK_N_L bel DLLDEL0
PinDirectionWires
CFLAGoutputCELL0.OUT_Q7
DIRECTIONinputCELL0.IMUX_D6
LOADNinputCELL0.IMUX_B6
MOVEinputCELL0.IMUX_C6

Bel DLLDEL1

ecp5 CLK_N_L bel DLLDEL1
PinDirectionWires
CFLAGoutputCELL1.OUT_Q7
DIRECTIONinputCELL1.IMUX_D6
LOADNinputCELL1.IMUX_B6
MOVEinputCELL1.IMUX_C6

Bel DLLDEL2

ecp5 CLK_N_L bel DLLDEL2
PinDirectionWires
CFLAGoutputCELL2.OUT_Q7
DIRECTIONinputCELL2.IMUX_D6
LOADNinputCELL2.IMUX_B6
MOVEinputCELL2.IMUX_C6

Bel DLLDEL3

ecp5 CLK_N_L bel DLLDEL3
PinDirectionWires
CFLAGoutputCELL3.OUT_Q7
DIRECTIONinputCELL3.IMUX_D6
LOADNinputCELL3.IMUX_B6
MOVEinputCELL3.IMUX_C6

Bel DCC0

ecp5 CLK_N_L bel DCC0
PinDirectionWires
CEinputCELL1.IMUX_A0

Bel DCC1

ecp5 CLK_N_L bel DCC1
PinDirectionWires
CEinputCELL1.IMUX_B0

Bel DCC2

ecp5 CLK_N_L bel DCC2
PinDirectionWires
CEinputCELL1.IMUX_C0

Bel DCC3

ecp5 CLK_N_L bel DCC3
PinDirectionWires
CEinputCELL1.IMUX_D0

Bel DCC4

ecp5 CLK_N_L bel DCC4
PinDirectionWires
CEinputCELL1.IMUX_A1

Bel DCC5

ecp5 CLK_N_L bel DCC5
PinDirectionWires
CEinputCELL1.IMUX_B1

Bel DCC6

ecp5 CLK_N_L bel DCC6
PinDirectionWires
CEinputCELL1.IMUX_C1

Bel DCC7

ecp5 CLK_N_L bel DCC7
PinDirectionWires
CEinputCELL1.IMUX_D1

Bel DCC8

ecp5 CLK_N_L bel DCC8
PinDirectionWires
CEinputCELL1.IMUX_A2

Bel DCC9

ecp5 CLK_N_L bel DCC9
PinDirectionWires
CEinputCELL1.IMUX_B2

Bel DCC10

ecp5 CLK_N_L bel DCC10
PinDirectionWires
CEinputCELL1.IMUX_C2

Bel DCC11

ecp5 CLK_N_L bel DCC11
PinDirectionWires
CEinputCELL1.IMUX_D2

Bel CLK_EDGE

ecp5 CLK_N_L bel CLK_EDGE
PinDirectionWires
INT_IN_0inputCELL4.IMUX_D7
INT_IN_1inputCELL5.IMUX_D7
INT_IN_2inputCELL6.IMUX_D7
INT_IN_3inputCELL7.IMUX_D7
INT_IN_4inputCELL8.IMUX_CLK1
INT_IN_5inputCELL9.IMUX_CLK1
INT_IN_6inputCELL10.IMUX_CLK1
INT_IN_7inputCELL11.IMUX_CLK1

Bel CLKTEST

ecp5 CLK_N_L bel CLKTEST
PinDirectionWires
TESTIN0inputCELL1.IMUX_A5
TESTIN1inputCELL1.IMUX_B5
TESTIN2inputCELL1.IMUX_C5

Bel wires

ecp5 CLK_N_L bel wires
WirePins
CELL0.IMUX_B6DLLDEL0.LOADN
CELL0.IMUX_C6DLLDEL0.MOVE
CELL0.IMUX_D6DLLDEL0.DIRECTION
CELL0.OUT_Q7DLLDEL0.CFLAG
CELL1.IMUX_A0DCC0.CE
CELL1.IMUX_A1DCC4.CE
CELL1.IMUX_A2DCC8.CE
CELL1.IMUX_A5CLKTEST.TESTIN0
CELL1.IMUX_B0DCC1.CE
CELL1.IMUX_B1DCC5.CE
CELL1.IMUX_B2DCC9.CE
CELL1.IMUX_B5CLKTEST.TESTIN1
CELL1.IMUX_B6DLLDEL1.LOADN
CELL1.IMUX_C0DCC2.CE
CELL1.IMUX_C1DCC6.CE
CELL1.IMUX_C2DCC10.CE
CELL1.IMUX_C5CLKTEST.TESTIN2
CELL1.IMUX_C6DLLDEL1.MOVE
CELL1.IMUX_D0DCC3.CE
CELL1.IMUX_D1DCC7.CE
CELL1.IMUX_D2DCC11.CE
CELL1.IMUX_D6DLLDEL1.DIRECTION
CELL1.OUT_Q7DLLDEL1.CFLAG
CELL2.IMUX_B6DLLDEL2.LOADN
CELL2.IMUX_C6DLLDEL2.MOVE
CELL2.IMUX_D6DLLDEL2.DIRECTION
CELL2.OUT_Q7DLLDEL2.CFLAG
CELL3.IMUX_B6DLLDEL3.LOADN
CELL3.IMUX_C6DLLDEL3.MOVE
CELL3.IMUX_D6DLLDEL3.DIRECTION
CELL3.OUT_Q7DLLDEL3.CFLAG
CELL4.IMUX_D7CLK_EDGE.INT_IN_0
CELL5.IMUX_D7CLK_EDGE.INT_IN_1
CELL6.IMUX_D7CLK_EDGE.INT_IN_2
CELL7.IMUX_D7CLK_EDGE.INT_IN_3
CELL8.IMUX_CLK1CLK_EDGE.INT_IN_4
CELL9.IMUX_CLK1CLK_EDGE.INT_IN_5
CELL10.IMUX_CLK1CLK_EDGE.INT_IN_6
CELL11.IMUX_CLK1CLK_EDGE.INT_IN_7

Tile CLK_ROOT_S

Cells: 4

Bel DCC_SW0

ecp5 CLK_ROOT_S bel DCC_SW0
PinDirectionWires
CEinputCELL0.IMUX_A0
CLKIinputCELL0.IMUX_D7

Bel DCC_SE0

ecp5 CLK_ROOT_S bel DCC_SE0
PinDirectionWires
CEinputCELL1.IMUX_A0
CLKIinputCELL1.IMUX_D7

Bel DCC_NW0

ecp5 CLK_ROOT_S bel DCC_NW0
PinDirectionWires
CEinputCELL2.IMUX_A0
CLKIinputCELL2.IMUX_D7

Bel DCC_NE0

ecp5 CLK_ROOT_S bel DCC_NE0
PinDirectionWires
CEinputCELL3.IMUX_A0
CLKIinputCELL3.IMUX_D7

Bel DCS0

ecp5 CLK_ROOT_S bel DCS0
PinDirectionWires
MODESELinputCELL2.IMUX_C0
SEL0inputCELL2.IMUX_A3
SEL1inputCELL2.IMUX_A4

Bel DCS1

ecp5 CLK_ROOT_S bel DCS1
PinDirectionWires
MODESELinputCELL0.IMUX_C0
SEL0inputCELL0.IMUX_A3
SEL1inputCELL0.IMUX_A4

Bel CLK_ROOT

ecp5 CLK_ROOT_S bel CLK_ROOT
PinDirectionWires
PCLK0_NEoutputCELL3.PCLK0
PCLK0_NWoutputCELL2.PCLK0
PCLK0_SEoutputCELL1.PCLK0
PCLK0_SWoutputCELL0.PCLK0
PCLK10_NEoutputCELL3.PCLK10
PCLK10_NWoutputCELL2.PCLK10
PCLK10_SEoutputCELL1.PCLK10
PCLK10_SWoutputCELL0.PCLK10
PCLK11_NEoutputCELL3.PCLK11
PCLK11_NWoutputCELL2.PCLK11
PCLK11_SEoutputCELL1.PCLK11
PCLK11_SWoutputCELL0.PCLK11
PCLK12_NEoutputCELL3.PCLK12
PCLK12_NWoutputCELL2.PCLK12
PCLK12_SEoutputCELL1.PCLK12
PCLK12_SWoutputCELL0.PCLK12
PCLK13_NEoutputCELL3.PCLK13
PCLK13_NWoutputCELL2.PCLK13
PCLK13_SEoutputCELL1.PCLK13
PCLK13_SWoutputCELL0.PCLK13
PCLK14_NEoutputCELL3.PCLK14
PCLK14_NWoutputCELL2.PCLK14
PCLK14_SEoutputCELL1.PCLK14
PCLK14_SWoutputCELL0.PCLK14
PCLK15_NEoutputCELL3.PCLK15
PCLK15_NWoutputCELL2.PCLK15
PCLK15_SEoutputCELL1.PCLK15
PCLK15_SWoutputCELL0.PCLK15
PCLK1_NEoutputCELL3.PCLK1
PCLK1_NWoutputCELL2.PCLK1
PCLK1_SEoutputCELL1.PCLK1
PCLK1_SWoutputCELL0.PCLK1
PCLK2_NEoutputCELL3.PCLK2
PCLK2_NWoutputCELL2.PCLK2
PCLK2_SEoutputCELL1.PCLK2
PCLK2_SWoutputCELL0.PCLK2
PCLK3_NEoutputCELL3.PCLK3
PCLK3_NWoutputCELL2.PCLK3
PCLK3_SEoutputCELL1.PCLK3
PCLK3_SWoutputCELL0.PCLK3
PCLK4_NEoutputCELL3.PCLK4
PCLK4_NWoutputCELL2.PCLK4
PCLK4_SEoutputCELL1.PCLK4
PCLK4_SWoutputCELL0.PCLK4
PCLK5_NEoutputCELL3.PCLK5
PCLK5_NWoutputCELL2.PCLK5
PCLK5_SEoutputCELL1.PCLK5
PCLK5_SWoutputCELL0.PCLK5
PCLK6_NEoutputCELL3.PCLK6
PCLK6_NWoutputCELL2.PCLK6
PCLK6_SEoutputCELL1.PCLK6
PCLK6_SWoutputCELL0.PCLK6
PCLK7_NEoutputCELL3.PCLK7
PCLK7_NWoutputCELL2.PCLK7
PCLK7_SEoutputCELL1.PCLK7
PCLK7_SWoutputCELL0.PCLK7
PCLK8_NEoutputCELL3.PCLK8
PCLK8_NWoutputCELL2.PCLK8
PCLK8_SEoutputCELL1.PCLK8
PCLK8_SWoutputCELL0.PCLK8
PCLK9_NEoutputCELL3.PCLK9
PCLK9_NWoutputCELL2.PCLK9
PCLK9_SEoutputCELL1.PCLK9
PCLK9_SWoutputCELL0.PCLK9

Bel CLKTEST

ecp5 CLK_ROOT_S bel CLKTEST
PinDirectionWires
TESTIN0inputCELL2.IMUX_A1
TESTIN1inputCELL2.IMUX_A2
TESTIN10inputCELL3.IMUX_B2
TESTIN11inputCELL3.IMUX_B3
TESTIN12inputCELL0.IMUX_A1
TESTIN13inputCELL0.IMUX_A2
TESTIN14inputCELL0.IMUX_B0
TESTIN15inputCELL0.IMUX_B1
TESTIN16inputCELL0.IMUX_B2
TESTIN17inputCELL0.IMUX_B3
TESTIN18inputCELL1.IMUX_A1
TESTIN19inputCELL1.IMUX_A2
TESTIN2inputCELL2.IMUX_B0
TESTIN20inputCELL1.IMUX_B0
TESTIN21inputCELL1.IMUX_B1
TESTIN22inputCELL1.IMUX_B2
TESTIN23inputCELL1.IMUX_B3
TESTIN3inputCELL2.IMUX_B1
TESTIN4inputCELL2.IMUX_B2
TESTIN5inputCELL2.IMUX_B3
TESTIN6inputCELL3.IMUX_A1
TESTIN7inputCELL3.IMUX_A2
TESTIN8inputCELL3.IMUX_B0
TESTIN9inputCELL3.IMUX_B1

Bel wires

ecp5 CLK_ROOT_S bel wires
WirePins
CELL0.PCLK0CLK_ROOT.PCLK0_SW
CELL0.PCLK1CLK_ROOT.PCLK1_SW
CELL0.PCLK2CLK_ROOT.PCLK2_SW
CELL0.PCLK3CLK_ROOT.PCLK3_SW
CELL0.PCLK4CLK_ROOT.PCLK4_SW
CELL0.PCLK5CLK_ROOT.PCLK5_SW
CELL0.PCLK6CLK_ROOT.PCLK6_SW
CELL0.PCLK7CLK_ROOT.PCLK7_SW
CELL0.PCLK8CLK_ROOT.PCLK8_SW
CELL0.PCLK9CLK_ROOT.PCLK9_SW
CELL0.PCLK10CLK_ROOT.PCLK10_SW
CELL0.PCLK11CLK_ROOT.PCLK11_SW
CELL0.PCLK12CLK_ROOT.PCLK12_SW
CELL0.PCLK13CLK_ROOT.PCLK13_SW
CELL0.PCLK14CLK_ROOT.PCLK14_SW
CELL0.PCLK15CLK_ROOT.PCLK15_SW
CELL0.IMUX_A0DCC_SW0.CE
CELL0.IMUX_A1CLKTEST.TESTIN12
CELL0.IMUX_A2CLKTEST.TESTIN13
CELL0.IMUX_A3DCS1.SEL0
CELL0.IMUX_A4DCS1.SEL1
CELL0.IMUX_B0CLKTEST.TESTIN14
CELL0.IMUX_B1CLKTEST.TESTIN15
CELL0.IMUX_B2CLKTEST.TESTIN16
CELL0.IMUX_B3CLKTEST.TESTIN17
CELL0.IMUX_C0DCS1.MODESEL
CELL0.IMUX_D7DCC_SW0.CLKI
CELL1.PCLK0CLK_ROOT.PCLK0_SE
CELL1.PCLK1CLK_ROOT.PCLK1_SE
CELL1.PCLK2CLK_ROOT.PCLK2_SE
CELL1.PCLK3CLK_ROOT.PCLK3_SE
CELL1.PCLK4CLK_ROOT.PCLK4_SE
CELL1.PCLK5CLK_ROOT.PCLK5_SE
CELL1.PCLK6CLK_ROOT.PCLK6_SE
CELL1.PCLK7CLK_ROOT.PCLK7_SE
CELL1.PCLK8CLK_ROOT.PCLK8_SE
CELL1.PCLK9CLK_ROOT.PCLK9_SE
CELL1.PCLK10CLK_ROOT.PCLK10_SE
CELL1.PCLK11CLK_ROOT.PCLK11_SE
CELL1.PCLK12CLK_ROOT.PCLK12_SE
CELL1.PCLK13CLK_ROOT.PCLK13_SE
CELL1.PCLK14CLK_ROOT.PCLK14_SE
CELL1.PCLK15CLK_ROOT.PCLK15_SE
CELL1.IMUX_A0DCC_SE0.CE
CELL1.IMUX_A1CLKTEST.TESTIN18
CELL1.IMUX_A2CLKTEST.TESTIN19
CELL1.IMUX_B0CLKTEST.TESTIN20
CELL1.IMUX_B1CLKTEST.TESTIN21
CELL1.IMUX_B2CLKTEST.TESTIN22
CELL1.IMUX_B3CLKTEST.TESTIN23
CELL1.IMUX_D7DCC_SE0.CLKI
CELL2.PCLK0CLK_ROOT.PCLK0_NW
CELL2.PCLK1CLK_ROOT.PCLK1_NW
CELL2.PCLK2CLK_ROOT.PCLK2_NW
CELL2.PCLK3CLK_ROOT.PCLK3_NW
CELL2.PCLK4CLK_ROOT.PCLK4_NW
CELL2.PCLK5CLK_ROOT.PCLK5_NW
CELL2.PCLK6CLK_ROOT.PCLK6_NW
CELL2.PCLK7CLK_ROOT.PCLK7_NW
CELL2.PCLK8CLK_ROOT.PCLK8_NW
CELL2.PCLK9CLK_ROOT.PCLK9_NW
CELL2.PCLK10CLK_ROOT.PCLK10_NW
CELL2.PCLK11CLK_ROOT.PCLK11_NW
CELL2.PCLK12CLK_ROOT.PCLK12_NW
CELL2.PCLK13CLK_ROOT.PCLK13_NW
CELL2.PCLK14CLK_ROOT.PCLK14_NW
CELL2.PCLK15CLK_ROOT.PCLK15_NW
CELL2.IMUX_A0DCC_NW0.CE
CELL2.IMUX_A1CLKTEST.TESTIN0
CELL2.IMUX_A2CLKTEST.TESTIN1
CELL2.IMUX_A3DCS0.SEL0
CELL2.IMUX_A4DCS0.SEL1
CELL2.IMUX_B0CLKTEST.TESTIN2
CELL2.IMUX_B1CLKTEST.TESTIN3
CELL2.IMUX_B2CLKTEST.TESTIN4
CELL2.IMUX_B3CLKTEST.TESTIN5
CELL2.IMUX_C0DCS0.MODESEL
CELL2.IMUX_D7DCC_NW0.CLKI
CELL3.PCLK0CLK_ROOT.PCLK0_NE
CELL3.PCLK1CLK_ROOT.PCLK1_NE
CELL3.PCLK2CLK_ROOT.PCLK2_NE
CELL3.PCLK3CLK_ROOT.PCLK3_NE
CELL3.PCLK4CLK_ROOT.PCLK4_NE
CELL3.PCLK5CLK_ROOT.PCLK5_NE
CELL3.PCLK6CLK_ROOT.PCLK6_NE
CELL3.PCLK7CLK_ROOT.PCLK7_NE
CELL3.PCLK8CLK_ROOT.PCLK8_NE
CELL3.PCLK9CLK_ROOT.PCLK9_NE
CELL3.PCLK10CLK_ROOT.PCLK10_NE
CELL3.PCLK11CLK_ROOT.PCLK11_NE
CELL3.PCLK12CLK_ROOT.PCLK12_NE
CELL3.PCLK13CLK_ROOT.PCLK13_NE
CELL3.PCLK14CLK_ROOT.PCLK14_NE
CELL3.PCLK15CLK_ROOT.PCLK15_NE
CELL3.IMUX_A0DCC_NE0.CE
CELL3.IMUX_A1CLKTEST.TESTIN6
CELL3.IMUX_A2CLKTEST.TESTIN7
CELL3.IMUX_B0CLKTEST.TESTIN8
CELL3.IMUX_B1CLKTEST.TESTIN9
CELL3.IMUX_B2CLKTEST.TESTIN10
CELL3.IMUX_B3CLKTEST.TESTIN11
CELL3.IMUX_D7DCC_NE0.CLKI

Tile CLK_ROOT_L

Cells: 8

Bel DCC_SW0

ecp5 CLK_ROOT_L bel DCC_SW0
PinDirectionWires
CEinputCELL2.IMUX_A0
CLKIinputCELL2.IMUX_D7

Bel DCC_SE0

ecp5 CLK_ROOT_L bel DCC_SE0
PinDirectionWires
CEinputCELL3.IMUX_A0
CLKIinputCELL3.IMUX_D7

Bel DCC_NW0

ecp5 CLK_ROOT_L bel DCC_NW0
PinDirectionWires
CEinputCELL4.IMUX_A0
CLKIinputCELL4.IMUX_D7

Bel DCC_NE0

ecp5 CLK_ROOT_L bel DCC_NE0
PinDirectionWires
CEinputCELL5.IMUX_A0
CLKIinputCELL5.IMUX_D7

Bel DCS0

ecp5 CLK_ROOT_L bel DCS0
PinDirectionWires
MODESELinputCELL4.IMUX_C0
SEL0inputCELL4.IMUX_A3
SEL1inputCELL4.IMUX_A4

Bel DCS1

ecp5 CLK_ROOT_L bel DCS1
PinDirectionWires
MODESELinputCELL2.IMUX_C0
SEL0inputCELL2.IMUX_A3
SEL1inputCELL2.IMUX_A4

Bel CLK_ROOT

ecp5 CLK_ROOT_L bel CLK_ROOT
PinDirectionWires
PCLK0_NEoutputCELL3.PCLK0
PCLK0_NWoutputCELL2.PCLK0
PCLK0_SEoutputCELL1.PCLK0
PCLK0_SWoutputCELL0.PCLK0
PCLK10_NEoutputCELL3.PCLK10
PCLK10_NWoutputCELL2.PCLK10
PCLK10_SEoutputCELL1.PCLK10
PCLK10_SWoutputCELL0.PCLK10
PCLK11_NEoutputCELL3.PCLK11
PCLK11_NWoutputCELL2.PCLK11
PCLK11_SEoutputCELL1.PCLK11
PCLK11_SWoutputCELL0.PCLK11
PCLK12_NEoutputCELL3.PCLK12
PCLK12_NWoutputCELL2.PCLK12
PCLK12_SEoutputCELL1.PCLK12
PCLK12_SWoutputCELL0.PCLK12
PCLK13_NEoutputCELL3.PCLK13
PCLK13_NWoutputCELL2.PCLK13
PCLK13_SEoutputCELL1.PCLK13
PCLK13_SWoutputCELL0.PCLK13
PCLK14_NEoutputCELL3.PCLK14
PCLK14_NWoutputCELL2.PCLK14
PCLK14_SEoutputCELL1.PCLK14
PCLK14_SWoutputCELL0.PCLK14
PCLK15_NEoutputCELL3.PCLK15
PCLK15_NWoutputCELL2.PCLK15
PCLK15_SEoutputCELL1.PCLK15
PCLK15_SWoutputCELL0.PCLK15
PCLK1_NEoutputCELL3.PCLK1
PCLK1_NWoutputCELL2.PCLK1
PCLK1_SEoutputCELL1.PCLK1
PCLK1_SWoutputCELL0.PCLK1
PCLK2_NEoutputCELL3.PCLK2
PCLK2_NWoutputCELL2.PCLK2
PCLK2_SEoutputCELL1.PCLK2
PCLK2_SWoutputCELL0.PCLK2
PCLK3_NEoutputCELL3.PCLK3
PCLK3_NWoutputCELL2.PCLK3
PCLK3_SEoutputCELL1.PCLK3
PCLK3_SWoutputCELL0.PCLK3
PCLK4_NEoutputCELL3.PCLK4
PCLK4_NWoutputCELL2.PCLK4
PCLK4_SEoutputCELL1.PCLK4
PCLK4_SWoutputCELL0.PCLK4
PCLK5_NEoutputCELL3.PCLK5
PCLK5_NWoutputCELL2.PCLK5
PCLK5_SEoutputCELL1.PCLK5
PCLK5_SWoutputCELL0.PCLK5
PCLK6_NEoutputCELL3.PCLK6
PCLK6_NWoutputCELL2.PCLK6
PCLK6_SEoutputCELL1.PCLK6
PCLK6_SWoutputCELL0.PCLK6
PCLK7_NEoutputCELL3.PCLK7
PCLK7_NWoutputCELL2.PCLK7
PCLK7_SEoutputCELL1.PCLK7
PCLK7_SWoutputCELL0.PCLK7
PCLK8_NEoutputCELL3.PCLK8
PCLK8_NWoutputCELL2.PCLK8
PCLK8_SEoutputCELL1.PCLK8
PCLK8_SWoutputCELL0.PCLK8
PCLK9_NEoutputCELL3.PCLK9
PCLK9_NWoutputCELL2.PCLK9
PCLK9_SEoutputCELL1.PCLK9
PCLK9_SWoutputCELL0.PCLK9

Bel CLKTEST

ecp5 CLK_ROOT_L bel CLKTEST
PinDirectionWires
TESTIN0inputCELL4.IMUX_A1
TESTIN1inputCELL4.IMUX_A2
TESTIN10inputCELL5.IMUX_B2
TESTIN11inputCELL5.IMUX_B3
TESTIN12inputCELL2.IMUX_A1
TESTIN13inputCELL2.IMUX_A2
TESTIN14inputCELL2.IMUX_B0
TESTIN15inputCELL2.IMUX_B1
TESTIN16inputCELL2.IMUX_B2
TESTIN17inputCELL2.IMUX_B3
TESTIN18inputCELL3.IMUX_A1
TESTIN19inputCELL3.IMUX_A2
TESTIN2inputCELL4.IMUX_B0
TESTIN20inputCELL3.IMUX_B0
TESTIN21inputCELL3.IMUX_B1
TESTIN22inputCELL3.IMUX_B2
TESTIN23inputCELL3.IMUX_B3
TESTIN3inputCELL4.IMUX_B1
TESTIN4inputCELL4.IMUX_B2
TESTIN5inputCELL4.IMUX_B3
TESTIN6inputCELL5.IMUX_A1
TESTIN7inputCELL5.IMUX_A2
TESTIN8inputCELL5.IMUX_B0
TESTIN9inputCELL5.IMUX_B1

Bel wires

ecp5 CLK_ROOT_L bel wires
WirePins
CELL0.PCLK0CLK_ROOT.PCLK0_SW
CELL0.PCLK1CLK_ROOT.PCLK1_SW
CELL0.PCLK2CLK_ROOT.PCLK2_SW
CELL0.PCLK3CLK_ROOT.PCLK3_SW
CELL0.PCLK4CLK_ROOT.PCLK4_SW
CELL0.PCLK5CLK_ROOT.PCLK5_SW
CELL0.PCLK6CLK_ROOT.PCLK6_SW
CELL0.PCLK7CLK_ROOT.PCLK7_SW
CELL0.PCLK8CLK_ROOT.PCLK8_SW
CELL0.PCLK9CLK_ROOT.PCLK9_SW
CELL0.PCLK10CLK_ROOT.PCLK10_SW
CELL0.PCLK11CLK_ROOT.PCLK11_SW
CELL0.PCLK12CLK_ROOT.PCLK12_SW
CELL0.PCLK13CLK_ROOT.PCLK13_SW
CELL0.PCLK14CLK_ROOT.PCLK14_SW
CELL0.PCLK15CLK_ROOT.PCLK15_SW
CELL1.PCLK0CLK_ROOT.PCLK0_SE
CELL1.PCLK1CLK_ROOT.PCLK1_SE
CELL1.PCLK2CLK_ROOT.PCLK2_SE
CELL1.PCLK3CLK_ROOT.PCLK3_SE
CELL1.PCLK4CLK_ROOT.PCLK4_SE
CELL1.PCLK5CLK_ROOT.PCLK5_SE
CELL1.PCLK6CLK_ROOT.PCLK6_SE
CELL1.PCLK7CLK_ROOT.PCLK7_SE
CELL1.PCLK8CLK_ROOT.PCLK8_SE
CELL1.PCLK9CLK_ROOT.PCLK9_SE
CELL1.PCLK10CLK_ROOT.PCLK10_SE
CELL1.PCLK11CLK_ROOT.PCLK11_SE
CELL1.PCLK12CLK_ROOT.PCLK12_SE
CELL1.PCLK13CLK_ROOT.PCLK13_SE
CELL1.PCLK14CLK_ROOT.PCLK14_SE
CELL1.PCLK15CLK_ROOT.PCLK15_SE
CELL2.PCLK0CLK_ROOT.PCLK0_NW
CELL2.PCLK1CLK_ROOT.PCLK1_NW
CELL2.PCLK2CLK_ROOT.PCLK2_NW
CELL2.PCLK3CLK_ROOT.PCLK3_NW
CELL2.PCLK4CLK_ROOT.PCLK4_NW
CELL2.PCLK5CLK_ROOT.PCLK5_NW
CELL2.PCLK6CLK_ROOT.PCLK6_NW
CELL2.PCLK7CLK_ROOT.PCLK7_NW
CELL2.PCLK8CLK_ROOT.PCLK8_NW
CELL2.PCLK9CLK_ROOT.PCLK9_NW
CELL2.PCLK10CLK_ROOT.PCLK10_NW
CELL2.PCLK11CLK_ROOT.PCLK11_NW
CELL2.PCLK12CLK_ROOT.PCLK12_NW
CELL2.PCLK13CLK_ROOT.PCLK13_NW
CELL2.PCLK14CLK_ROOT.PCLK14_NW
CELL2.PCLK15CLK_ROOT.PCLK15_NW
CELL2.IMUX_A0DCC_SW0.CE
CELL2.IMUX_A1CLKTEST.TESTIN12
CELL2.IMUX_A2CLKTEST.TESTIN13
CELL2.IMUX_A3DCS1.SEL0
CELL2.IMUX_A4DCS1.SEL1
CELL2.IMUX_B0CLKTEST.TESTIN14
CELL2.IMUX_B1CLKTEST.TESTIN15
CELL2.IMUX_B2CLKTEST.TESTIN16
CELL2.IMUX_B3CLKTEST.TESTIN17
CELL2.IMUX_C0DCS1.MODESEL
CELL2.IMUX_D7DCC_SW0.CLKI
CELL3.PCLK0CLK_ROOT.PCLK0_NE
CELL3.PCLK1CLK_ROOT.PCLK1_NE
CELL3.PCLK2CLK_ROOT.PCLK2_NE
CELL3.PCLK3CLK_ROOT.PCLK3_NE
CELL3.PCLK4CLK_ROOT.PCLK4_NE
CELL3.PCLK5CLK_ROOT.PCLK5_NE
CELL3.PCLK6CLK_ROOT.PCLK6_NE
CELL3.PCLK7CLK_ROOT.PCLK7_NE
CELL3.PCLK8CLK_ROOT.PCLK8_NE
CELL3.PCLK9CLK_ROOT.PCLK9_NE
CELL3.PCLK10CLK_ROOT.PCLK10_NE
CELL3.PCLK11CLK_ROOT.PCLK11_NE
CELL3.PCLK12CLK_ROOT.PCLK12_NE
CELL3.PCLK13CLK_ROOT.PCLK13_NE
CELL3.PCLK14CLK_ROOT.PCLK14_NE
CELL3.PCLK15CLK_ROOT.PCLK15_NE
CELL3.IMUX_A0DCC_SE0.CE
CELL3.IMUX_A1CLKTEST.TESTIN18
CELL3.IMUX_A2CLKTEST.TESTIN19
CELL3.IMUX_B0CLKTEST.TESTIN20
CELL3.IMUX_B1CLKTEST.TESTIN21
CELL3.IMUX_B2CLKTEST.TESTIN22
CELL3.IMUX_B3CLKTEST.TESTIN23
CELL3.IMUX_D7DCC_SE0.CLKI
CELL4.IMUX_A0DCC_NW0.CE
CELL4.IMUX_A1CLKTEST.TESTIN0
CELL4.IMUX_A2CLKTEST.TESTIN1
CELL4.IMUX_A3DCS0.SEL0
CELL4.IMUX_A4DCS0.SEL1
CELL4.IMUX_B0CLKTEST.TESTIN2
CELL4.IMUX_B1CLKTEST.TESTIN3
CELL4.IMUX_B2CLKTEST.TESTIN4
CELL4.IMUX_B3CLKTEST.TESTIN5
CELL4.IMUX_C0DCS0.MODESEL
CELL4.IMUX_D7DCC_NW0.CLKI
CELL5.IMUX_A0DCC_NE0.CE
CELL5.IMUX_A1CLKTEST.TESTIN6
CELL5.IMUX_A2CLKTEST.TESTIN7
CELL5.IMUX_B0CLKTEST.TESTIN8
CELL5.IMUX_B1CLKTEST.TESTIN9
CELL5.IMUX_B2CLKTEST.TESTIN10
CELL5.IMUX_B3CLKTEST.TESTIN11
CELL5.IMUX_D7DCC_NE0.CLKI