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Global buffers

TODO: document

Bitstream — bottom tiles

TODO: document

Tile CLKB.FC

Cells: 1 IRIs: 0

Muxes

fpgacore CLKB.FC muxes
DestinationSources
OMUX10.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX11.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX12.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX15.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
CLK.IMUX.CLK0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.CLK1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.CLK2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.CLK3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1

Bel BUFGMUX0

fpgacore CLKB.FC bel BUFGMUX0
PinDirectionWires
CLKinputCLK.IMUX.CLK0
OoutputCLK.OUT.0

Bel BUFGMUX1

fpgacore CLKB.FC bel BUFGMUX1
PinDirectionWires
CLKinputCLK.IMUX.CLK1
OoutputCLK.OUT.1

Bel BUFGMUX2

fpgacore CLKB.FC bel BUFGMUX2
PinDirectionWires
CLKinputCLK.IMUX.CLK2
OoutputCLK.OUT.2

Bel BUFGMUX3

fpgacore CLKB.FC bel BUFGMUX3
PinDirectionWires
CLKinputCLK.IMUX.CLK3
OoutputCLK.OUT.3

Bel GLOBALSIG_S

fpgacore CLKB.FC bel GLOBALSIG_S
PinDirectionWires

Bel wires

fpgacore CLKB.FC bel wires
WirePins
CLK.IMUX.CLK0BUFGMUX0.CLK
CLK.IMUX.CLK1BUFGMUX1.CLK
CLK.IMUX.CLK2BUFGMUX2.CLK
CLK.IMUX.CLK3BUFGMUX3.CLK
CLK.OUT.0BUFGMUX0.O
CLK.OUT.1BUFGMUX1.O
CLK.OUT.2BUFGMUX2.O
CLK.OUT.3BUFGMUX3.O

Bitstream

fpgacore CLKB.FC bittile 0
BitFrame
0
57 INT:MUX.CLK.IMUX.CLK3[1]
56 INT:MUX.CLK.IMUX.CLK3[0]
55 -
54 INT:MUX.CLK.IMUX.CLK3[3]
53 INT:MUX.CLK.IMUX.CLK3[2]
52 -
51 BUFGMUX3:MUX.CLK[1]
50 -
49 -
48 BUFGMUX3:MUX.CLK[0]
47 INT:MUX.OMUX15.N[2]
46 INT:MUX.OMUX15.N[1]
45 INT:MUX.OMUX12.N[1]
44 INT:MUX.OMUX12.N[2]
43 INT:MUX.OMUX15.N[0]
42 INT:MUX.OMUX12.N[0]
41 -
40 -
39 -
38 -
37 INT:MUX.CLK.IMUX.CLK2[1]
36 INT:MUX.CLK.IMUX.CLK2[0]
35 -
34 INT:MUX.CLK.IMUX.CLK2[3]
33 INT:MUX.CLK.IMUX.CLK2[2]
32 -
31 BUFGMUX2:MUX.CLK[1]
30 -
29 -
28 BUFGMUX2:MUX.CLK[0]
27 -
26 -
25 -
24 -
23 INT:MUX.CLK.IMUX.CLK1[1]
22 INT:MUX.CLK.IMUX.CLK1[0]
21 -
20 INT:MUX.CLK.IMUX.CLK1[3]
19 INT:MUX.CLK.IMUX.CLK1[2]
18 -
17 BUFGMUX1:MUX.CLK[1]
16 -
15 -
14 BUFGMUX1:MUX.CLK[0]
13 BUFGMUX0:MUX.CLK[1]
12 -
11 -
10 BUFGMUX0:MUX.CLK[0]
9 INT:MUX.CLK.IMUX.CLK0[3]
8 INT:MUX.CLK.IMUX.CLK0[2]
7 -
6 INT:MUX.CLK.IMUX.CLK0[1]
5 INT:MUX.CLK.IMUX.CLK0[0]
4 -
3 -
2 -
1 -
0 INT:MUX.OMUX10.N[0]
fpgacore CLKB.FC bittile 1
BitFrame
0
11 INT:MUX.OMUX11.N[2]
10 INT:MUX.OMUX11.N[0]
9 INT:MUX.OMUX10.N[1]
8 INT:MUX.OMUX10.N[2]
7 INT:MUX.OMUX11.N[1]
6 -
5 -
4 -
3 -
2 -
1 -
0 -
BUFGMUX0:MUX.CLK 0.0.13 0.0.10
BUFGMUX1:MUX.CLK 0.0.17 0.0.14
BUFGMUX2:MUX.CLK 0.0.31 0.0.28
BUFGMUX3:MUX.CLK 0.0.51 0.0.48
INT 0 1
CKI 1 0
INT:MUX.CLK.IMUX.CLK0 0.0.9 0.0.8 0.0.6 0.0.5
PULLUP 0 0 0 0
DBL.W0.2 0 0 0 1
DBL.W1.2 0 0 1 0
DBL.W0.1 0 1 0 1
DBL.W1.1 0 1 1 0
DBL.E0.1 1 0 0 1
DBL.E1.1 1 0 1 0
DBL.E0.0 1 1 0 1
DBL.E1.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK1 0.0.20 0.0.19 0.0.23 0.0.22
PULLUP 0 0 0 0
DBL.W2.2 0 0 0 1
DBL.W3.2 0 0 1 0
DBL.W2.1 0 1 0 1
DBL.W3.1 0 1 1 0
DBL.E2.1 1 0 0 1
DBL.E3.1 1 0 1 0
DBL.E2.0 1 1 0 1
DBL.E3.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK2 0.0.34 0.0.33 0.0.37 0.0.36
PULLUP 0 0 0 0
DBL.W4.2 0 0 0 1
DBL.W5.2 0 0 1 0
DBL.W4.1 0 1 0 1
DBL.W5.1 0 1 1 0
DBL.E4.1 1 0 0 1
DBL.E5.1 1 0 1 0
DBL.E4.0 1 1 0 1
DBL.E5.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK3 0.0.54 0.0.53 0.0.57 0.0.56
PULLUP 0 0 0 0
DBL.W6.2 0 0 0 1
DBL.W7.2 0 0 1 0
DBL.W6.1 0 1 0 1
DBL.W7.1 0 1 1 0
DBL.E6.1 1 0 0 1
DBL.E7.1 1 0 1 0
DBL.E6.0 1 1 0 1
DBL.E7.0 1 1 1 0
INT:MUX.OMUX10.N 1.0.8 1.0.9 0.0.0
INT:MUX.OMUX11.N 1.0.11 1.0.7 1.0.10
INT:MUX.OMUX12.N 0.0.44 0.0.45 0.0.42
INT:MUX.OMUX15.N 0.0.47 0.0.46 0.0.43
NONE 0 0 0
CLK.OUT.2 0 0 1
CLK.OUT.3 0 1 0
CLK.OUT.0 1 0 1
CLK.OUT.1 1 1 0

Bitstream — top tiles

TODO: document

Tile CLKT.FC

Cells: 1 IRIs: 0

Muxes

fpgacore CLKT.FC muxes
DestinationSources
OMUX0.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX3.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX4.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX5.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
CLK.IMUX.CLK0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.CLK1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.CLK2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.CLK3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1

Bel BUFGMUX0

fpgacore CLKT.FC bel BUFGMUX0
PinDirectionWires
CLKinputCLK.IMUX.CLK0
OoutputCLK.OUT.0

Bel BUFGMUX1

fpgacore CLKT.FC bel BUFGMUX1
PinDirectionWires
CLKinputCLK.IMUX.CLK1
OoutputCLK.OUT.1

Bel BUFGMUX2

fpgacore CLKT.FC bel BUFGMUX2
PinDirectionWires
CLKinputCLK.IMUX.CLK2
OoutputCLK.OUT.2

Bel BUFGMUX3

fpgacore CLKT.FC bel BUFGMUX3
PinDirectionWires
CLKinputCLK.IMUX.CLK3
OoutputCLK.OUT.3

Bel GLOBALSIG_N

fpgacore CLKT.FC bel GLOBALSIG_N
PinDirectionWires

Bel wires

fpgacore CLKT.FC bel wires
WirePins
CLK.IMUX.CLK0BUFGMUX0.CLK
CLK.IMUX.CLK1BUFGMUX1.CLK
CLK.IMUX.CLK2BUFGMUX2.CLK
CLK.IMUX.CLK3BUFGMUX3.CLK
CLK.OUT.0BUFGMUX0.O
CLK.OUT.1BUFGMUX1.O
CLK.OUT.2BUFGMUX2.O
CLK.OUT.3BUFGMUX3.O

Bitstream

fpgacore CLKT.FC bittile 0
BitFrame
0
63 INT:MUX.OMUX0.S[0]
62 -
61 -
60 -
59 -
58 INT:MUX.CLK.IMUX.CLK3[1]
57 INT:MUX.CLK.IMUX.CLK3[0]
56 -
55 INT:MUX.CLK.IMUX.CLK3[2]
54 INT:MUX.CLK.IMUX.CLK3[3]
53 BUFGMUX3:MUX.CLK[0]
52 -
51 -
50 BUFGMUX3:MUX.CLK[1]
49 BUFGMUX2:MUX.CLK[0]
48 -
47 -
46 BUFGMUX2:MUX.CLK[1]
45 -
44 INT:MUX.CLK.IMUX.CLK2[2]
43 INT:MUX.CLK.IMUX.CLK2[3]
42 -
41 INT:MUX.CLK.IMUX.CLK2[1]
40 INT:MUX.CLK.IMUX.CLK2[0]
39 -
38 -
37 -
36 -
35 BUFGMUX1:MUX.CLK[0]
34 -
33 -
32 BUFGMUX1:MUX.CLK[1]
31 -
30 INT:MUX.CLK.IMUX.CLK1[2]
29 INT:MUX.CLK.IMUX.CLK1[3]
28 -
27 INT:MUX.CLK.IMUX.CLK1[1]
26 INT:MUX.CLK.IMUX.CLK1[0]
25 -
24 -
23 -
22 -
21 INT:MUX.OMUX4.S[0]
20 INT:MUX.OMUX5.S[0]
19 INT:MUX.OMUX4.S[2]
18 INT:MUX.OMUX4.S[1]
17 INT:MUX.OMUX5.S[1]
16 INT:MUX.OMUX5.S[2]
15 BUFGMUX0:MUX.CLK[0]
14 -
13 -
12 BUFGMUX0:MUX.CLK[1]
11 -
10 INT:MUX.CLK.IMUX.CLK0[2]
9 INT:MUX.CLK.IMUX.CLK0[3]
8 -
7 INT:MUX.CLK.IMUX.CLK0[1]
6 INT:MUX.CLK.IMUX.CLK0[0]
5 -
4 -
3 -
2 -
1 -
0 -
fpgacore CLKT.FC bittile 1
BitFrame
0
4 INT:MUX.OMUX3.S[1]
3 INT:MUX.OMUX0.S[2]
2 INT:MUX.OMUX0.S[1]
1 INT:MUX.OMUX3.S[0]
0 INT:MUX.OMUX3.S[2]
BUFGMUX0:MUX.CLK 0.0.12 0.0.15
BUFGMUX1:MUX.CLK 0.0.32 0.0.35
BUFGMUX2:MUX.CLK 0.0.46 0.0.49
BUFGMUX3:MUX.CLK 0.0.50 0.0.53
INT 0 1
CKI 1 0
INT:MUX.CLK.IMUX.CLK0 0.0.9 0.0.10 0.0.7 0.0.6
PULLUP 0 0 0 0
DBL.W0.2 0 0 0 1
DBL.W1.2 0 0 1 0
DBL.W0.1 0 1 0 1
DBL.W1.1 0 1 1 0
DBL.E0.1 1 0 0 1
DBL.E1.1 1 0 1 0
DBL.E0.0 1 1 0 1
DBL.E1.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK1 0.0.29 0.0.30 0.0.27 0.0.26
PULLUP 0 0 0 0
DBL.W2.2 0 0 0 1
DBL.W3.2 0 0 1 0
DBL.W2.1 0 1 0 1
DBL.W3.1 0 1 1 0
DBL.E2.1 1 0 0 1
DBL.E3.1 1 0 1 0
DBL.E2.0 1 1 0 1
DBL.E3.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK2 0.0.43 0.0.44 0.0.41 0.0.40
PULLUP 0 0 0 0
DBL.W4.2 0 0 0 1
DBL.W5.2 0 0 1 0
DBL.W4.1 0 1 0 1
DBL.W5.1 0 1 1 0
DBL.E4.1 1 0 0 1
DBL.E5.1 1 0 1 0
DBL.E4.0 1 1 0 1
DBL.E5.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK3 0.0.54 0.0.55 0.0.58 0.0.57
PULLUP 0 0 0 0
DBL.W6.2 0 0 0 1
DBL.W7.2 0 0 1 0
DBL.W6.1 0 1 0 1
DBL.W7.1 0 1 1 0
DBL.E6.1 1 0 0 1
DBL.E7.1 1 0 1 0
DBL.E6.0 1 1 0 1
DBL.E7.0 1 1 1 0
INT:MUX.OMUX0.S 1.0.3 1.0.2 0.0.63
INT:MUX.OMUX3.S 1.0.0 1.0.4 1.0.1
INT:MUX.OMUX4.S 0.0.19 0.0.18 0.0.21
INT:MUX.OMUX5.S 0.0.16 0.0.17 0.0.20
NONE 0 0 0
CLK.OUT.2 0 0 1
CLK.OUT.3 0 1 0
CLK.OUT.0 1 0 1
CLK.OUT.1 1 1 0