Global buffers

TODO: document

Bitstream — bottom tiles

TODO: document

Tile CLKB.FC

Cells: 1

Switchbox CLK_INT

fpgacore CLKB.FC switchbox CLK_INT
Destination	Source	Kind
OMUX10.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX11.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX12.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX15.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
CLK.IMUX.CLK0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.CLK1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.CLK2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.CLK3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux

Bel BUFGMUX0

fpgacore CLKB.FC bel BUFGMUX0
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK0
O	output	CLK.OUT.0

Bel BUFGMUX1

fpgacore CLKB.FC bel BUFGMUX1
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK1
O	output	CLK.OUT.1

Bel BUFGMUX2

fpgacore CLKB.FC bel BUFGMUX2
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK2
O	output	CLK.OUT.2

Bel BUFGMUX3

fpgacore CLKB.FC bel BUFGMUX3
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK3
O	output	CLK.OUT.3

Bel GLOBALSIG_S

fpgacore CLKB.FC bel GLOBALSIG_S
Pin	Direction	Wires

Bel wires

fpgacore CLKB.FC bel wires
Wire	Pins
CLK.IMUX.CLK0	BUFGMUX0.CLK
CLK.IMUX.CLK1	BUFGMUX1.CLK
CLK.IMUX.CLK2	BUFGMUX2.CLK
CLK.IMUX.CLK3	BUFGMUX3.CLK
CLK.OUT.0	BUFGMUX0.O
CLK.OUT.1	BUFGMUX1.O
CLK.OUT.2	BUFGMUX2.O
CLK.OUT.3	BUFGMUX3.O

Bitstream

fpgacore CLKB.FC bittile 0
Bit	Frame
Bit	0
57	CLK_INT:MUX.CLK.IMUX.CLK3[1]
56	CLK_INT:MUX.CLK.IMUX.CLK3[0]
55	-
54	CLK_INT:MUX.CLK.IMUX.CLK3[3]
53	CLK_INT:MUX.CLK.IMUX.CLK3[2]
52	-
51	BUFGMUX3:MUX.CLK[1]
50	-
49	-
48	BUFGMUX3:MUX.CLK[0]
47	CLK_INT:MUX.OMUX15.N[2]
46	CLK_INT:MUX.OMUX15.N[1]
45	CLK_INT:MUX.OMUX12.N[1]
44	CLK_INT:MUX.OMUX12.N[2]
43	CLK_INT:MUX.OMUX15.N[0]
42	CLK_INT:MUX.OMUX12.N[0]
41	-
40	-
39	-
38	-
37	CLK_INT:MUX.CLK.IMUX.CLK2[1]
36	CLK_INT:MUX.CLK.IMUX.CLK2[0]
35	-
34	CLK_INT:MUX.CLK.IMUX.CLK2[3]
33	CLK_INT:MUX.CLK.IMUX.CLK2[2]
32	-
31	BUFGMUX2:MUX.CLK[1]
30	-
29	-
28	BUFGMUX2:MUX.CLK[0]
27	-
26	-
25	-
24	-
23	CLK_INT:MUX.CLK.IMUX.CLK1[1]
22	CLK_INT:MUX.CLK.IMUX.CLK1[0]
21	-
20	CLK_INT:MUX.CLK.IMUX.CLK1[3]
19	CLK_INT:MUX.CLK.IMUX.CLK1[2]
18	-
17	BUFGMUX1:MUX.CLK[1]
16	-
15	-
14	BUFGMUX1:MUX.CLK[0]
13	BUFGMUX0:MUX.CLK[1]
12	-
11	-
10	BUFGMUX0:MUX.CLK[0]
9	CLK_INT:MUX.CLK.IMUX.CLK0[3]
8	CLK_INT:MUX.CLK.IMUX.CLK0[2]
7	-
6	CLK_INT:MUX.CLK.IMUX.CLK0[1]
5	CLK_INT:MUX.CLK.IMUX.CLK0[0]
4	-
3	-
2	-
1	-
0	CLK_INT:MUX.OMUX10.N[0]

fpgacore CLKB.FC bittile 1
Bit	Frame
Bit	0
11	CLK_INT:MUX.OMUX11.N[2]
10	CLK_INT:MUX.OMUX11.N[0]
9	CLK_INT:MUX.OMUX10.N[1]
8	CLK_INT:MUX.OMUX10.N[2]
7	CLK_INT:MUX.OMUX11.N[1]
6	-
5	-
4	-
3	-
2	-
1	-
0	-

BUFGMUX0:MUX.CLK	0.0.13	0.0.10
BUFGMUX1:MUX.CLK	0.0.17	0.0.14
BUFGMUX2:MUX.CLK	0.0.31	0.0.28
BUFGMUX3:MUX.CLK	0.0.51	0.0.48
INT	0	1
CKI	1	0

CLK_INT:MUX.CLK.IMUX.CLK0	0.0.9	0.0.8	0.0.6	0.0.5
PULLUP	0	0	0	0
DBL.W0.2	0	0	0	1
DBL.W1.2	0	0	1	0
DBL.W0.1	0	1	0	1
DBL.W1.1	0	1	1	0
DBL.E0.1	1	0	0	1
DBL.E1.1	1	0	1	0
DBL.E0.0	1	1	0	1
DBL.E1.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK1	0.0.20	0.0.19	0.0.23	0.0.22
PULLUP	0	0	0	0
DBL.W2.2	0	0	0	1
DBL.W3.2	0	0	1	0
DBL.W2.1	0	1	0	1
DBL.W3.1	0	1	1	0
DBL.E2.1	1	0	0	1
DBL.E3.1	1	0	1	0
DBL.E2.0	1	1	0	1
DBL.E3.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK2	0.0.34	0.0.33	0.0.37	0.0.36
PULLUP	0	0	0	0
DBL.W4.2	0	0	0	1
DBL.W5.2	0	0	1	0
DBL.W4.1	0	1	0	1
DBL.W5.1	0	1	1	0
DBL.E4.1	1	0	0	1
DBL.E5.1	1	0	1	0
DBL.E4.0	1	1	0	1
DBL.E5.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK3	0.0.54	0.0.53	0.0.57	0.0.56
PULLUP	0	0	0	0
DBL.W6.2	0	0	0	1
DBL.W7.2	0	0	1	0
DBL.W6.1	0	1	0	1
DBL.W7.1	0	1	1	0
DBL.E6.1	1	0	0	1
DBL.E7.1	1	0	1	0
DBL.E6.0	1	1	0	1
DBL.E7.0	1	1	1	0

CLK_INT:MUX.OMUX10.N	1.0.8	1.0.9	0.0.0
CLK_INT:MUX.OMUX11.N	1.0.11	1.0.7	1.0.10
CLK_INT:MUX.OMUX12.N	0.0.44	0.0.45	0.0.42
CLK_INT:MUX.OMUX15.N	0.0.47	0.0.46	0.0.43
NONE	0	0	0
CLK.OUT.2	0	0	1
CLK.OUT.3	0	1	0
CLK.OUT.0	1	0	1
CLK.OUT.1	1	1	0

Bitstream — top tiles

TODO: document

Tile CLKT.FC

Cells: 1

Switchbox CLK_INT

fpgacore CLKT.FC switchbox CLK_INT
Destination	Source	Kind
OMUX0.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX3.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX4.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX5.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
CLK.IMUX.CLK0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.CLK1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.CLK2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.CLK3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux

Bel BUFGMUX0

fpgacore CLKT.FC bel BUFGMUX0
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK0
O	output	CLK.OUT.0

Bel BUFGMUX1

fpgacore CLKT.FC bel BUFGMUX1
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK1
O	output	CLK.OUT.1

Bel BUFGMUX2

fpgacore CLKT.FC bel BUFGMUX2
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK2
O	output	CLK.OUT.2

Bel BUFGMUX3

fpgacore CLKT.FC bel BUFGMUX3
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK3
O	output	CLK.OUT.3

Bel GLOBALSIG_N

fpgacore CLKT.FC bel GLOBALSIG_N
Pin	Direction	Wires

Bel wires

fpgacore CLKT.FC bel wires
Wire	Pins
CLK.IMUX.CLK0	BUFGMUX0.CLK
CLK.IMUX.CLK1	BUFGMUX1.CLK
CLK.IMUX.CLK2	BUFGMUX2.CLK
CLK.IMUX.CLK3	BUFGMUX3.CLK
CLK.OUT.0	BUFGMUX0.O
CLK.OUT.1	BUFGMUX1.O
CLK.OUT.2	BUFGMUX2.O
CLK.OUT.3	BUFGMUX3.O

Bitstream

fpgacore CLKT.FC bittile 0
Bit	Frame
Bit	0
63	CLK_INT:MUX.OMUX0.S[0]
62	-
61	-
60	-
59	-
58	CLK_INT:MUX.CLK.IMUX.CLK3[1]
57	CLK_INT:MUX.CLK.IMUX.CLK3[0]
56	-
55	CLK_INT:MUX.CLK.IMUX.CLK3[2]
54	CLK_INT:MUX.CLK.IMUX.CLK3[3]
53	BUFGMUX3:MUX.CLK[0]
52	-
51	-
50	BUFGMUX3:MUX.CLK[1]
49	BUFGMUX2:MUX.CLK[0]
48	-
47	-
46	BUFGMUX2:MUX.CLK[1]
45	-
44	CLK_INT:MUX.CLK.IMUX.CLK2[2]
43	CLK_INT:MUX.CLK.IMUX.CLK2[3]
42	-
41	CLK_INT:MUX.CLK.IMUX.CLK2[1]
40	CLK_INT:MUX.CLK.IMUX.CLK2[0]
39	-
38	-
37	-
36	-
35	BUFGMUX1:MUX.CLK[0]
34	-
33	-
32	BUFGMUX1:MUX.CLK[1]
31	-
30	CLK_INT:MUX.CLK.IMUX.CLK1[2]
29	CLK_INT:MUX.CLK.IMUX.CLK1[3]
28	-
27	CLK_INT:MUX.CLK.IMUX.CLK1[1]
26	CLK_INT:MUX.CLK.IMUX.CLK1[0]
25	-
24	-
23	-
22	-
21	CLK_INT:MUX.OMUX4.S[0]
20	CLK_INT:MUX.OMUX5.S[0]
19	CLK_INT:MUX.OMUX4.S[2]
18	CLK_INT:MUX.OMUX4.S[1]
17	CLK_INT:MUX.OMUX5.S[1]
16	CLK_INT:MUX.OMUX5.S[2]
15	BUFGMUX0:MUX.CLK[0]
14	-
13	-
12	BUFGMUX0:MUX.CLK[1]
11	-
10	CLK_INT:MUX.CLK.IMUX.CLK0[2]
9	CLK_INT:MUX.CLK.IMUX.CLK0[3]
8	-
7	CLK_INT:MUX.CLK.IMUX.CLK0[1]
6	CLK_INT:MUX.CLK.IMUX.CLK0[0]
5	-
4	-
3	-
2	-
1	-
0	-

fpgacore CLKT.FC bittile 1
Bit	Frame
Bit	0
4	CLK_INT:MUX.OMUX3.S[1]
3	CLK_INT:MUX.OMUX0.S[2]
2	CLK_INT:MUX.OMUX0.S[1]
1	CLK_INT:MUX.OMUX3.S[0]
0	CLK_INT:MUX.OMUX3.S[2]

BUFGMUX0:MUX.CLK	0.0.12	0.0.15
BUFGMUX1:MUX.CLK	0.0.32	0.0.35
BUFGMUX2:MUX.CLK	0.0.46	0.0.49
BUFGMUX3:MUX.CLK	0.0.50	0.0.53
INT	0	1
CKI	1	0

CLK_INT:MUX.CLK.IMUX.CLK0	0.0.9	0.0.10	0.0.7	0.0.6
PULLUP	0	0	0	0
DBL.W0.2	0	0	0	1
DBL.W1.2	0	0	1	0
DBL.W0.1	0	1	0	1
DBL.W1.1	0	1	1	0
DBL.E0.1	1	0	0	1
DBL.E1.1	1	0	1	0
DBL.E0.0	1	1	0	1
DBL.E1.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK1	0.0.29	0.0.30	0.0.27	0.0.26
PULLUP	0	0	0	0
DBL.W2.2	0	0	0	1
DBL.W3.2	0	0	1	0
DBL.W2.1	0	1	0	1
DBL.W3.1	0	1	1	0
DBL.E2.1	1	0	0	1
DBL.E3.1	1	0	1	0
DBL.E2.0	1	1	0	1
DBL.E3.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK2	0.0.43	0.0.44	0.0.41	0.0.40
PULLUP	0	0	0	0
DBL.W4.2	0	0	0	1
DBL.W5.2	0	0	1	0
DBL.W4.1	0	1	0	1
DBL.W5.1	0	1	1	0
DBL.E4.1	1	0	0	1
DBL.E5.1	1	0	1	0
DBL.E4.0	1	1	0	1
DBL.E5.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK3	0.0.54	0.0.55	0.0.58	0.0.57
PULLUP	0	0	0	0
DBL.W6.2	0	0	0	1
DBL.W7.2	0	0	1	0
DBL.W6.1	0	1	0	1
DBL.W7.1	0	1	1	0
DBL.E6.1	1	0	0	1
DBL.E7.1	1	0	1	0
DBL.E6.0	1	1	0	1
DBL.E7.0	1	1	1	0

CLK_INT:MUX.OMUX0.S	1.0.3	1.0.2	0.0.63
CLK_INT:MUX.OMUX3.S	1.0.0	1.0.4	1.0.1
CLK_INT:MUX.OMUX4.S	0.0.19	0.0.18	0.0.21
CLK_INT:MUX.OMUX5.S	0.0.16	0.0.17	0.0.20
NONE	0	0	0
CLK.OUT.2	0	0	1
CLK.OUT.3	0	1	0
CLK.OUT.0	1	0	1
CLK.OUT.1	1	1	0

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