Clock quadrant distribution

The `CLKC` clock center tile

TODO: document

Tile CLKC

Cells: 0

Bel CLKC

fpgacore CLKC bel CLKC
Pin	Direction	Wires

The `GCLKVM` secondary clock center tiles

The GCLKVM tiles are located on the intersection of secondary vertical clock spines and the horizontal clock spine.

TODO: document

Tile GCLKVM.S3

Cells: 0

Bel GCLKVM

fpgacore GCLKVM.S3 bel GCLKVM
Pin	Direction	Wires

Bitstream

fpgacore GCLKVM.S3 bittile 0
Bit	Frame
Bit	0
38	GCLKVM:BUF.OUT_B0
37	-
36	GCLKVM:BUF.OUT_B1
35	GCLKVM:BUF.OUT_B7
34	GCLKVM:BUF.OUT_B2
33	GCLKVM:BUF.OUT_B6
32	GCLKVM:BUF.OUT_B5
31	GCLKVM:BUF.OUT_B4
30	GCLKVM:BUF.OUT_B3
29	-
28	-
27	-
26	-
25	-
24	-
23	-
22	-
21	-
20	-
19	-
18	-
17	-
16	-
15	-
14	-
13	-
12	-
11	-
10	-
9	-
8	-
7	-
6	-
5	-
4	-
3	-
2	-
1	-
0	-

fpgacore GCLKVM.S3 bittile 1
Bit	Frame
Bit	0
33	GCLKVM:BUF.OUT_T3
32	GCLKVM:BUF.OUT_T4
31	GCLKVM:BUF.OUT_T5
30	GCLKVM:BUF.OUT_T6
29	GCLKVM:BUF.OUT_T2
28	GCLKVM:BUF.OUT_T7
27	GCLKVM:BUF.OUT_T1
26	-
25	GCLKVM:BUF.OUT_T0
24	-
23	-
22	-
21	-
20	-
19	-
18	-
17	-
16	-
15	-
14	-
13	-
12	-
11	-
10	-
9	-
8	-
7	-
6	-
5	-
4	-
3	-
2	-
1	-
0	-

GCLKVM:BUF.OUT_B0	0.0.38
GCLKVM:BUF.OUT_B1	0.0.36
GCLKVM:BUF.OUT_B2	0.0.34
GCLKVM:BUF.OUT_B3	0.0.30
GCLKVM:BUF.OUT_B4	0.0.31
GCLKVM:BUF.OUT_B5	0.0.32
GCLKVM:BUF.OUT_B6	0.0.33
GCLKVM:BUF.OUT_B7	0.0.35
GCLKVM:BUF.OUT_T0	1.0.25
GCLKVM:BUF.OUT_T1	1.0.27
GCLKVM:BUF.OUT_T2	1.0.29
GCLKVM:BUF.OUT_T3	1.0.33
GCLKVM:BUF.OUT_T4	1.0.32
GCLKVM:BUF.OUT_T5	1.0.31
GCLKVM:BUF.OUT_T6	1.0.30
GCLKVM:BUF.OUT_T7	1.0.28
non-inverted	[0]

The `GCLKVC` clock spine distribution tiles

TODO: document

Tile GCLKVC

Cells: 0

Bel GCLKVC

fpgacore GCLKVC bel GCLKVC
Pin	Direction	Wires