Configuration registers

TODO: document

`COR.FC`

fpgacore REG.COR.FC bittile 0
Bit	Frame
Bit	0
0	STARTUP:GWE_CYCLE[0]
1	STARTUP:GWE_CYCLE[1]
2	STARTUP:GWE_CYCLE[2]
3	STARTUP:GTS_CYCLE[0]
4	STARTUP:GTS_CYCLE[1]
5	STARTUP:GTS_CYCLE[2]
6	-
7	-
8	-
9	-
10	-
11	-
12	STARTUP:DONE_CYCLE[0]
13	STARTUP:DONE_CYCLE[1]
14	STARTUP:DONE_CYCLE[2]
15	STARTUP:STARTUPCLK[0]
16	STARTUP:STARTUPCLK[1]
17	STARTUP:BUSCLK_FREQ[0]
18	STARTUP:BUSCLK_FREQ[1]
19	STARTUP:CONFIG_RATE[0]
20	STARTUP:CONFIG_RATE[1]
21	STARTUP:CONFIG_RATE[2]
22	-
23	CAPTURE:ONESHOT
24	STARTUP:DRIVE_DONE
25	STARTUP:DONE_PIPE
26	-
27	-
28	-
29	~STARTUP:CRC
30	STARTUP:VRDSEL[0]
31	STARTUP:VRDSEL[1]

CAPTURE:ONESHOT	0.0.23
STARTUP:DONE_PIPE	0.0.25
STARTUP:DRIVE_DONE	0.0.24
non-inverted	[0]

STARTUP:BUSCLK_FREQ	0.0.18	0.0.17
100	0	0
25	0	1
50	1	0
200	1	1

STARTUP:CONFIG_RATE	0.0.21	0.0.20	0.0.19
6	0	0	0
12	0	0	1
25	0	1	0
50	0	1	1
3	1	0	0
100	1	1	0

STARTUP:CRC	0.0.29
inverted	~[0]

STARTUP:DONE_CYCLE	0.0.14	0.0.13	0.0.12
1	0	0	0
2	0	0	1
3	0	1	0
4	0	1	1
5	1	0	0
6	1	0	1
KEEP	1	1	1

STARTUP:GTS_CYCLE	0.0.5	0.0.4	0.0.3
STARTUP:GWE_CYCLE	0.0.2	0.0.1	0.0.0
1	0	0	0
2	0	0	1
3	0	1	0
4	0	1	1
5	1	0	0
6	1	0	1
DONE	1	1	0
KEEP	1	1	1

STARTUP:STARTUPCLK	0.0.16	0.0.15
CCLK	0	0
USERCLK	0	1
JTAGCLK	1	0

STARTUP:VRDSEL	0.0.31	0.0.30
100	0	0
95	0	1
90	1	0
80	1	1

`CTL.S3`

fpgacore REG.CTL.S3 bittile 0
Bit	Frame
Bit	0
0	MISC:GTS_USR_B
1	MISC:VGG_TEST
2	MISC:BCLK_TEST
3	MISC:PERSIST
4	MISC:SECURITY[0]
5	MISC:SECURITY[1]

MISC:BCLK_TEST	0.0.2
MISC:GTS_USR_B	0.0.0
MISC:PERSIST	0.0.3
MISC:VGG_TEST	0.0.1
non-inverted	[0]

MISC:SECURITY	0.0.5	0.0.4
NONE	0	0
LEVEL1	0	1
LEVEL2	1	0

Device data

Device	MISC:SEND_VGG_DEFAULT				MISC:VGG_SENDMAX_DEFAULT
Device	[3]	[2]	[1]	[0]	[0]
xcexf10	0	0	0	0	1
xcexf20	0	0	0	0	1
xcexf40	0	0	0	0	1