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Configuration center

Tile CONFIG

Cells: 4

Bel START

machxo2 CONFIG bel START
PinDirectionWires
STARTCLKinputTCELL0:IMUX_CLK0

Bel OSC

machxo2 CONFIG bel OSC
PinDirectionWires
OSCoutputTCELL0:OUT_Q5
STDBYinputTCELL0:IMUX_LSR1

Bel JTAG

machxo2 CONFIG bel JTAG
PinDirectionWires
JCE1outputTCELL0:OUT_Q1
JCE2outputTCELL0:OUT_Q3
JRSTNoutputTCELL0:OUT_F6
JRTI1outputTCELL0:OUT_Q2
JRTI2outputTCELL0:OUT_Q4
JSHIFToutputTCELL0:OUT_F7
JTCKoutputTCELL0:OUT_F4
JTDIoutputTCELL0:OUT_F5
JTDO1inputTCELL0:IMUX_A4
JTDO2inputTCELL0:IMUX_B4
JUPDATEoutputTCELL0:OUT_Q0

Bel GSR

machxo2 CONFIG bel GSR
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
GSRinputTCELL2:IMUX_C4

Bel TSALL

machxo2 CONFIG bel TSALL
PinDirectionWires
TSALLIinputTCELL2:IMUX_LSR0

Bel SED

machxo2 CONFIG bel SED
PinDirectionWires
AUTODONEoutputTCELL1:OUT_F4
SEDCLKOUToutputTCELL1:OUT_F5
SEDDONEoutputTCELL1:OUT_F6
SEDENABLEinputTCELL1:IMUX_LSR0
SEDERRoutputTCELL1:OUT_F7
SEDEXCLKinputTCELL1:IMUX_CLK0
SEDFRCERRinputTCELL1:IMUX_A0
SEDINPROGoutputTCELL1:OUT_Q0
SEDSTARTinputTCELL1:IMUX_LSR1

Bel PCNTR

machxo2 CONFIG bel PCNTR
PinDirectionWires
CLKinputTCELL3:IMUX_CLK1
CLRFLAGinputTCELL3:IMUX_B0
SFLAGoutputTCELL3:OUT_Q5
STDBYoutputTCELL3:OUT_Q3
STOPoutputTCELL3:OUT_Q4
USERSTDBYinputTCELL3:IMUX_LSR1
USERTIMEOUTinputTCELL3:IMUX_C0

Bel EFB

machxo2 CONFIG bel EFB
PinDirectionWires
I2C1IRQOoutputTCELL1:OUT_Q3
I2C2IRQOoutputTCELL1:OUT_Q4
I2C2SCLIinputTCELL1:IMUX_CLK1
I2C2SCLOoutputTCELL1:OUT_Q1
I2C2SCLOENoutputTCELL1:OUT_Q5
I2C2SDAIinputTCELL1:IMUX_C0
I2C2SDAOoutputTCELL1:OUT_Q2
I2C2SDAOENoutputTCELL1:OUT_Q6
SPIIRQOoutputTCELL3:OUT_Q0
SPIMCSN1outputTCELL2:OUT_Q2
SPIMCSN2outputTCELL2:OUT_Q3
SPIMCSN3outputTCELL2:OUT_Q4
SPIMCSN4outputTCELL3:OUT_F0
SPIMCSN5outputTCELL3:OUT_F1
SPIMCSN6outputTCELL3:OUT_F2
SPIMCSN7outputTCELL3:OUT_F3
SPISCSNinputTCELL3:IMUX_CE0
TCCLKIinputTCELL3:IMUX_CLK0
TCICinputTCELL3:IMUX_A0
TCINToutputTCELL3:OUT_Q1
TCOCoutputTCELL3:OUT_Q2
TCRSTNinputTCELL3:IMUX_LSR0
WBACKOoutputTCELL2:OUT_Q0
WBADRI0inputTCELL1:IMUX_A2
WBADRI1inputTCELL1:IMUX_B2
WBADRI2inputTCELL1:IMUX_C2
WBADRI3inputTCELL1:IMUX_D2
WBADRI4inputTCELL1:IMUX_A4
WBADRI5inputTCELL1:IMUX_B4
WBADRI6inputTCELL1:IMUX_C4
WBADRI7inputTCELL1:IMUX_D4
WBCLKIinputTCELL2:IMUX_CLK1
WBCUFMIRQoutputTCELL2:OUT_Q1
WBCYCIinputTCELL2:IMUX_A4
WBDATI0inputTCELL2:IMUX_A0
WBDATI1inputTCELL2:IMUX_B0
WBDATI2inputTCELL2:IMUX_C0
WBDATI3inputTCELL2:IMUX_D0
WBDATI4inputTCELL2:IMUX_A2
WBDATI5inputTCELL2:IMUX_B2
WBDATI6inputTCELL2:IMUX_C2
WBDATI7inputTCELL2:IMUX_D2
WBDATO0outputTCELL2:OUT_F0
WBDATO1outputTCELL2:OUT_F1
WBDATO2outputTCELL2:OUT_F2
WBDATO3outputTCELL2:OUT_F3
WBDATO4outputTCELL2:OUT_F4
WBDATO5outputTCELL2:OUT_F5
WBDATO6outputTCELL2:OUT_F6
WBDATO7outputTCELL2:OUT_F7
WBRSTIinputTCELL2:IMUX_CE0
WBSTBIinputTCELL2:IMUX_LSR1
WBWEIinputTCELL2:IMUX_B4

Bel wires

machxo2 CONFIG bel wires
WirePins
TCELL0:IMUX_A4JTAG.JTDO1
TCELL0:IMUX_B4JTAG.JTDO2
TCELL0:IMUX_CLK0START.STARTCLK
TCELL0:IMUX_LSR1OSC.STDBY
TCELL0:OUT_F4JTAG.JTCK
TCELL0:OUT_F5JTAG.JTDI
TCELL0:OUT_F6JTAG.JRSTN
TCELL0:OUT_F7JTAG.JSHIFT
TCELL0:OUT_Q0JTAG.JUPDATE
TCELL0:OUT_Q1JTAG.JCE1
TCELL0:OUT_Q2JTAG.JRTI1
TCELL0:OUT_Q3JTAG.JCE2
TCELL0:OUT_Q4JTAG.JRTI2
TCELL0:OUT_Q5OSC.OSC
TCELL1:IMUX_A0SED.SEDFRCERR
TCELL1:IMUX_A2EFB.WBADRI0
TCELL1:IMUX_A4EFB.WBADRI4
TCELL1:IMUX_B2EFB.WBADRI1
TCELL1:IMUX_B4EFB.WBADRI5
TCELL1:IMUX_C0EFB.I2C2SDAI
TCELL1:IMUX_C2EFB.WBADRI2
TCELL1:IMUX_C4EFB.WBADRI6
TCELL1:IMUX_D2EFB.WBADRI3
TCELL1:IMUX_D4EFB.WBADRI7
TCELL1:IMUX_CLK0SED.SEDEXCLK
TCELL1:IMUX_CLK1EFB.I2C2SCLI
TCELL1:IMUX_LSR0SED.SEDENABLE
TCELL1:IMUX_LSR1SED.SEDSTART
TCELL1:OUT_F4SED.AUTODONE
TCELL1:OUT_F5SED.SEDCLKOUT
TCELL1:OUT_F6SED.SEDDONE
TCELL1:OUT_F7SED.SEDERR
TCELL1:OUT_Q0SED.SEDINPROG
TCELL1:OUT_Q1EFB.I2C2SCLO
TCELL1:OUT_Q2EFB.I2C2SDAO
TCELL1:OUT_Q3EFB.I2C1IRQO
TCELL1:OUT_Q4EFB.I2C2IRQO
TCELL1:OUT_Q5EFB.I2C2SCLOEN
TCELL1:OUT_Q6EFB.I2C2SDAOEN
TCELL2:IMUX_A0EFB.WBDATI0
TCELL2:IMUX_A2EFB.WBDATI4
TCELL2:IMUX_A4EFB.WBCYCI
TCELL2:IMUX_B0EFB.WBDATI1
TCELL2:IMUX_B2EFB.WBDATI5
TCELL2:IMUX_B4EFB.WBWEI
TCELL2:IMUX_C0EFB.WBDATI2
TCELL2:IMUX_C2EFB.WBDATI6
TCELL2:IMUX_C4GSR.GSR
TCELL2:IMUX_D0EFB.WBDATI3
TCELL2:IMUX_D2EFB.WBDATI7
TCELL2:IMUX_CLK0GSR.CLK
TCELL2:IMUX_CLK1EFB.WBCLKI
TCELL2:IMUX_LSR0TSALL.TSALLI
TCELL2:IMUX_LSR1EFB.WBSTBI
TCELL2:IMUX_CE0EFB.WBRSTI
TCELL2:OUT_F0EFB.WBDATO0
TCELL2:OUT_F1EFB.WBDATO1
TCELL2:OUT_F2EFB.WBDATO2
TCELL2:OUT_F3EFB.WBDATO3
TCELL2:OUT_F4EFB.WBDATO4
TCELL2:OUT_F5EFB.WBDATO5
TCELL2:OUT_F6EFB.WBDATO6
TCELL2:OUT_F7EFB.WBDATO7
TCELL2:OUT_Q0EFB.WBACKO
TCELL2:OUT_Q1EFB.WBCUFMIRQ
TCELL2:OUT_Q2EFB.SPIMCSN1
TCELL2:OUT_Q3EFB.SPIMCSN2
TCELL2:OUT_Q4EFB.SPIMCSN3
TCELL3:IMUX_A0EFB.TCIC
TCELL3:IMUX_B0PCNTR.CLRFLAG
TCELL3:IMUX_C0PCNTR.USERTIMEOUT
TCELL3:IMUX_CLK0EFB.TCCLKI
TCELL3:IMUX_CLK1PCNTR.CLK
TCELL3:IMUX_LSR0EFB.TCRSTN
TCELL3:IMUX_LSR1PCNTR.USERSTDBY
TCELL3:IMUX_CE0EFB.SPISCSN
TCELL3:OUT_F0EFB.SPIMCSN4
TCELL3:OUT_F1EFB.SPIMCSN5
TCELL3:OUT_F2EFB.SPIMCSN6
TCELL3:OUT_F3EFB.SPIMCSN7
TCELL3:OUT_Q0EFB.SPIIRQO
TCELL3:OUT_Q1EFB.TCINT
TCELL3:OUT_Q2EFB.TCOC
TCELL3:OUT_Q3PCNTR.STDBY
TCELL3:OUT_Q4PCNTR.STOP
TCELL3:OUT_Q5PCNTR.SFLAG

Tile CONFIG_XO3D

Cells: 10

Bel START

machxo2 CONFIG_XO3D bel START
PinDirectionWires
STARTCLKinputTCELL0:IMUX_CLK0

Bel OSC

machxo2 CONFIG_XO3D bel OSC
PinDirectionWires
OSCoutputTCELL0:OUT_Q5
STDBYinputTCELL0:IMUX_LSR1

Bel JTAG

machxo2 CONFIG_XO3D bel JTAG
PinDirectionWires
JCE1outputTCELL0:OUT_Q1
JCE2outputTCELL0:OUT_Q3
JRSTNoutputTCELL0:OUT_F6
JRTI1outputTCELL0:OUT_Q2
JRTI2outputTCELL0:OUT_Q4
JSHIFToutputTCELL0:OUT_F7
JTCKoutputTCELL0:OUT_F4
JTDIoutputTCELL0:OUT_F5
JTDO1inputTCELL0:IMUX_A4
JTDO2inputTCELL0:IMUX_B4
JUPDATEoutputTCELL0:OUT_Q0

Bel GSR

machxo2 CONFIG_XO3D bel GSR
PinDirectionWires
CLKinputTCELL2:IMUX_CLK0
GSRinputTCELL2:IMUX_C4

Bel TSALL

machxo2 CONFIG_XO3D bel TSALL
PinDirectionWires
TSALLIinputTCELL2:IMUX_LSR0

Bel SED

machxo2 CONFIG_XO3D bel SED
PinDirectionWires
AUTODONEoutputTCELL1:OUT_F4
SEDCLKOUToutputTCELL1:OUT_F5
SEDDONEoutputTCELL1:OUT_F6
SEDENABLEinputTCELL1:IMUX_LSR0
SEDERRoutputTCELL1:OUT_F7
SEDEXCLKinputTCELL1:IMUX_CLK0
SEDFRCERRinputTCELL1:IMUX_A0
SEDINPROGoutputTCELL1:OUT_Q0
SEDSTARTinputTCELL1:IMUX_LSR1

Bel PCNTR

machxo2 CONFIG_XO3D bel PCNTR
PinDirectionWires
CLKinputTCELL3:IMUX_CLK1
CLRFLAGinputTCELL3:IMUX_B0
SFLAGoutputTCELL3:OUT_Q5
STDBYoutputTCELL3:OUT_Q3
STOPoutputTCELL3:OUT_Q4
USERSTDBYinputTCELL3:IMUX_LSR1
USERTIMEOUTinputTCELL3:IMUX_C0

Bel EFB

machxo2 CONFIG_XO3D bel EFB
PinDirectionWires
I2C1IRQOoutputTCELL1:OUT_Q3
I2C2IRQOoutputTCELL1:OUT_Q4
I2C2SCLIinputTCELL1:IMUX_CLK1
I2C2SCLOoutputTCELL1:OUT_Q1
I2C2SCLOENoutputTCELL1:OUT_Q5
I2C2SDAIinputTCELL1:IMUX_C0
I2C2SDAOoutputTCELL1:OUT_Q2
I2C2SDAOENoutputTCELL1:OUT_Q6
SPIIRQOoutputTCELL3:OUT_Q0
SPIMCSN1outputTCELL2:OUT_Q2
SPIMCSN2outputTCELL2:OUT_Q3
SPIMCSN3outputTCELL2:OUT_Q4
SPIMCSN4outputTCELL3:OUT_F0
SPIMCSN5outputTCELL3:OUT_F1
SPIMCSN6outputTCELL3:OUT_F2
SPIMCSN7outputTCELL3:OUT_F3
SPISCSNinputTCELL3:IMUX_CE0
TAMPERDEToutputTCELL3:OUT_Q7
TAMPERDETCLKinputTCELL1:IMUX_CLK3
TAMPERDETENinputTCELL1:IMUX_A1
TAMPERLOCKSRCinputTCELL1:IMUX_B1
TAMPERSRC0outputTCELL3:OUT_F6
TAMPERSRC1outputTCELL3:OUT_F7
TAMPERTYPE0outputTCELL3:OUT_F4
TAMPERTYPE1outputTCELL3:OUT_F5
TCCLKIinputTCELL3:IMUX_CLK0
TCICinputTCELL3:IMUX_A0
TCINToutputTCELL3:OUT_Q1
TCOCoutputTCELL3:OUT_Q2
TCRSTNinputTCELL3:IMUX_LSR0
WBACKOoutputTCELL2:OUT_Q0
WBADRI0inputTCELL1:IMUX_A2
WBADRI1inputTCELL1:IMUX_B2
WBADRI2inputTCELL1:IMUX_C2
WBADRI3inputTCELL1:IMUX_D2
WBADRI4inputTCELL1:IMUX_A4
WBADRI5inputTCELL1:IMUX_B4
WBADRI6inputTCELL1:IMUX_C4
WBADRI7inputTCELL1:IMUX_D4
WBCLKIinputTCELL2:IMUX_CLK1
WBCUFMIRQoutputTCELL2:OUT_Q1
WBCYCIinputTCELL2:IMUX_A4
WBDATI0inputTCELL2:IMUX_A0
WBDATI1inputTCELL2:IMUX_B0
WBDATI2inputTCELL2:IMUX_C0
WBDATI3inputTCELL2:IMUX_D0
WBDATI4inputTCELL2:IMUX_A2
WBDATI5inputTCELL2:IMUX_B2
WBDATI6inputTCELL2:IMUX_C2
WBDATI7inputTCELL2:IMUX_D2
WBDATO0outputTCELL2:OUT_F0
WBDATO1outputTCELL2:OUT_F1
WBDATO2outputTCELL2:OUT_F2
WBDATO3outputTCELL2:OUT_F3
WBDATO4outputTCELL2:OUT_F4
WBDATO5outputTCELL2:OUT_F5
WBDATO6outputTCELL2:OUT_F6
WBDATO7outputTCELL2:OUT_F7
WBRSTIinputTCELL2:IMUX_CE0
WBSTBIinputTCELL2:IMUX_LSR1
WBWEIinputTCELL2:IMUX_B4

Bel ESB

machxo2 CONFIG_XO3D bel ESB
PinDirectionWires
ASFCLKIinputTCELL4:IMUX_CLK1
ASFEMPTYOoutputTCELL9:OUT_Q6
ASFFULLOoutputTCELL9:OUT_Q5
ASFRDIinputTCELL3:IMUX_B1
ASFRESETIinputTCELL4:IMUX_CE1
ASFWRIinputTCELL3:IMUX_A1
WBACKOoutputTCELL9:OUT_Q4
WBADRI0inputTCELL6:IMUX_A4
WBADRI1inputTCELL6:IMUX_B4
WBADRI10inputTCELL7:IMUX_C4
WBADRI11inputTCELL7:IMUX_D4
WBADRI12inputTCELL7:IMUX_A5
WBADRI13inputTCELL7:IMUX_B5
WBADRI14inputTCELL7:IMUX_C5
WBADRI15inputTCELL7:IMUX_D5
WBADRI16inputTCELL8:IMUX_A4
WBADRI17inputTCELL8:IMUX_B4
WBADRI2inputTCELL6:IMUX_C4
WBADRI3inputTCELL6:IMUX_D4
WBADRI4inputTCELL6:IMUX_A5
WBADRI5inputTCELL6:IMUX_B5
WBADRI6inputTCELL6:IMUX_C5
WBADRI7inputTCELL6:IMUX_D5
WBADRI8inputTCELL7:IMUX_A4
WBADRI9inputTCELL7:IMUX_B4
WBCLKIinputTCELL4:IMUX_CLK0
WBCYCIinputTCELL3:IMUX_C1
WBDATI0inputTCELL4:IMUX_A0
WBDATI1inputTCELL4:IMUX_B0
WBDATI10inputTCELL4:IMUX_C2
WBDATI11inputTCELL4:IMUX_D2
WBDATI12inputTCELL4:IMUX_A3
WBDATI13inputTCELL4:IMUX_B3
WBDATI14inputTCELL4:IMUX_C3
WBDATI15inputTCELL4:IMUX_D3
WBDATI16inputTCELL4:IMUX_A4
WBDATI17inputTCELL4:IMUX_B4
WBDATI18inputTCELL4:IMUX_C4
WBDATI19inputTCELL4:IMUX_D4
WBDATI2inputTCELL4:IMUX_C0
WBDATI20inputTCELL4:IMUX_A5
WBDATI21inputTCELL4:IMUX_B5
WBDATI22inputTCELL4:IMUX_C5
WBDATI23inputTCELL4:IMUX_D5
WBDATI24inputTCELL5:IMUX_A4
WBDATI25inputTCELL5:IMUX_B4
WBDATI26inputTCELL5:IMUX_C4
WBDATI27inputTCELL5:IMUX_D4
WBDATI28inputTCELL5:IMUX_A5
WBDATI29inputTCELL5:IMUX_B5
WBDATI3inputTCELL4:IMUX_D0
WBDATI30inputTCELL5:IMUX_C5
WBDATI31inputTCELL5:IMUX_D5
WBDATI4inputTCELL4:IMUX_A1
WBDATI5inputTCELL4:IMUX_B1
WBDATI6inputTCELL4:IMUX_C1
WBDATI7inputTCELL4:IMUX_D1
WBDATI8inputTCELL4:IMUX_A2
WBDATI9inputTCELL4:IMUX_B2
WBDATO0outputTCELL4:OUT_F0
WBDATO1outputTCELL4:OUT_F1
WBDATO10outputTCELL4:OUT_Q2
WBDATO11outputTCELL4:OUT_Q3
WBDATO12outputTCELL4:OUT_Q4
WBDATO13outputTCELL4:OUT_Q5
WBDATO14outputTCELL4:OUT_Q6
WBDATO15outputTCELL4:OUT_Q7
WBDATO16outputTCELL5:OUT_Q4
WBDATO17outputTCELL5:OUT_Q5
WBDATO18outputTCELL5:OUT_Q6
WBDATO19outputTCELL5:OUT_Q7
WBDATO2outputTCELL4:OUT_F2
WBDATO20outputTCELL6:OUT_Q4
WBDATO21outputTCELL6:OUT_Q5
WBDATO22outputTCELL6:OUT_Q6
WBDATO23outputTCELL6:OUT_Q7
WBDATO24outputTCELL7:OUT_Q4
WBDATO25outputTCELL7:OUT_Q5
WBDATO26outputTCELL7:OUT_Q6
WBDATO27outputTCELL7:OUT_Q7
WBDATO28outputTCELL8:OUT_Q4
WBDATO29outputTCELL8:OUT_Q5
WBDATO3outputTCELL4:OUT_F3
WBDATO30outputTCELL8:OUT_Q6
WBDATO31outputTCELL8:OUT_Q7
WBDATO4outputTCELL4:OUT_F4
WBDATO5outputTCELL4:OUT_F5
WBDATO6outputTCELL4:OUT_F6
WBDATO7outputTCELL4:OUT_F7
WBDATO8outputTCELL4:OUT_Q0
WBDATO9outputTCELL4:OUT_Q1
WBRSTIinputTCELL4:IMUX_CE0
WBSTBIinputTCELL4:IMUX_LSR0
WBWEIinputTCELL3:IMUX_D1

Bel wires

machxo2 CONFIG_XO3D bel wires
WirePins
TCELL0:IMUX_A4JTAG.JTDO1
TCELL0:IMUX_B4JTAG.JTDO2
TCELL0:IMUX_CLK0START.STARTCLK
TCELL0:IMUX_LSR1OSC.STDBY
TCELL0:OUT_F4JTAG.JTCK
TCELL0:OUT_F5JTAG.JTDI
TCELL0:OUT_F6JTAG.JRSTN
TCELL0:OUT_F7JTAG.JSHIFT
TCELL0:OUT_Q0JTAG.JUPDATE
TCELL0:OUT_Q1JTAG.JCE1
TCELL0:OUT_Q2JTAG.JRTI1
TCELL0:OUT_Q3JTAG.JCE2
TCELL0:OUT_Q4JTAG.JRTI2
TCELL0:OUT_Q5OSC.OSC
TCELL1:IMUX_A0SED.SEDFRCERR
TCELL1:IMUX_A1EFB.TAMPERDETEN
TCELL1:IMUX_A2EFB.WBADRI0
TCELL1:IMUX_A4EFB.WBADRI4
TCELL1:IMUX_B1EFB.TAMPERLOCKSRC
TCELL1:IMUX_B2EFB.WBADRI1
TCELL1:IMUX_B4EFB.WBADRI5
TCELL1:IMUX_C0EFB.I2C2SDAI
TCELL1:IMUX_C2EFB.WBADRI2
TCELL1:IMUX_C4EFB.WBADRI6
TCELL1:IMUX_D2EFB.WBADRI3
TCELL1:IMUX_D4EFB.WBADRI7
TCELL1:IMUX_CLK0SED.SEDEXCLK
TCELL1:IMUX_CLK1EFB.I2C2SCLI
TCELL1:IMUX_CLK3EFB.TAMPERDETCLK
TCELL1:IMUX_LSR0SED.SEDENABLE
TCELL1:IMUX_LSR1SED.SEDSTART
TCELL1:OUT_F4SED.AUTODONE
TCELL1:OUT_F5SED.SEDCLKOUT
TCELL1:OUT_F6SED.SEDDONE
TCELL1:OUT_F7SED.SEDERR
TCELL1:OUT_Q0SED.SEDINPROG
TCELL1:OUT_Q1EFB.I2C2SCLO
TCELL1:OUT_Q2EFB.I2C2SDAO
TCELL1:OUT_Q3EFB.I2C1IRQO
TCELL1:OUT_Q4EFB.I2C2IRQO
TCELL1:OUT_Q5EFB.I2C2SCLOEN
TCELL1:OUT_Q6EFB.I2C2SDAOEN
TCELL2:IMUX_A0EFB.WBDATI0
TCELL2:IMUX_A2EFB.WBDATI4
TCELL2:IMUX_A4EFB.WBCYCI
TCELL2:IMUX_B0EFB.WBDATI1
TCELL2:IMUX_B2EFB.WBDATI5
TCELL2:IMUX_B4EFB.WBWEI
TCELL2:IMUX_C0EFB.WBDATI2
TCELL2:IMUX_C2EFB.WBDATI6
TCELL2:IMUX_C4GSR.GSR
TCELL2:IMUX_D0EFB.WBDATI3
TCELL2:IMUX_D2EFB.WBDATI7
TCELL2:IMUX_CLK0GSR.CLK
TCELL2:IMUX_CLK1EFB.WBCLKI
TCELL2:IMUX_LSR0TSALL.TSALLI
TCELL2:IMUX_LSR1EFB.WBSTBI
TCELL2:IMUX_CE0EFB.WBRSTI
TCELL2:OUT_F0EFB.WBDATO0
TCELL2:OUT_F1EFB.WBDATO1
TCELL2:OUT_F2EFB.WBDATO2
TCELL2:OUT_F3EFB.WBDATO3
TCELL2:OUT_F4EFB.WBDATO4
TCELL2:OUT_F5EFB.WBDATO5
TCELL2:OUT_F6EFB.WBDATO6
TCELL2:OUT_F7EFB.WBDATO7
TCELL2:OUT_Q0EFB.WBACKO
TCELL2:OUT_Q1EFB.WBCUFMIRQ
TCELL2:OUT_Q2EFB.SPIMCSN1
TCELL2:OUT_Q3EFB.SPIMCSN2
TCELL2:OUT_Q4EFB.SPIMCSN3
TCELL3:IMUX_A0EFB.TCIC
TCELL3:IMUX_A1ESB.ASFWRI
TCELL3:IMUX_B0PCNTR.CLRFLAG
TCELL3:IMUX_B1ESB.ASFRDI
TCELL3:IMUX_C0PCNTR.USERTIMEOUT
TCELL3:IMUX_C1ESB.WBCYCI
TCELL3:IMUX_D1ESB.WBWEI
TCELL3:IMUX_CLK0EFB.TCCLKI
TCELL3:IMUX_CLK1PCNTR.CLK
TCELL3:IMUX_LSR0EFB.TCRSTN
TCELL3:IMUX_LSR1PCNTR.USERSTDBY
TCELL3:IMUX_CE0EFB.SPISCSN
TCELL3:OUT_F0EFB.SPIMCSN4
TCELL3:OUT_F1EFB.SPIMCSN5
TCELL3:OUT_F2EFB.SPIMCSN6
TCELL3:OUT_F3EFB.SPIMCSN7
TCELL3:OUT_F4EFB.TAMPERTYPE0
TCELL3:OUT_F5EFB.TAMPERTYPE1
TCELL3:OUT_F6EFB.TAMPERSRC0
TCELL3:OUT_F7EFB.TAMPERSRC1
TCELL3:OUT_Q0EFB.SPIIRQO
TCELL3:OUT_Q1EFB.TCINT
TCELL3:OUT_Q2EFB.TCOC
TCELL3:OUT_Q3PCNTR.STDBY
TCELL3:OUT_Q4PCNTR.STOP
TCELL3:OUT_Q5PCNTR.SFLAG
TCELL3:OUT_Q7EFB.TAMPERDET
TCELL4:IMUX_A0ESB.WBDATI0
TCELL4:IMUX_A1ESB.WBDATI4
TCELL4:IMUX_A2ESB.WBDATI8
TCELL4:IMUX_A3ESB.WBDATI12
TCELL4:IMUX_A4ESB.WBDATI16
TCELL4:IMUX_A5ESB.WBDATI20
TCELL4:IMUX_B0ESB.WBDATI1
TCELL4:IMUX_B1ESB.WBDATI5
TCELL4:IMUX_B2ESB.WBDATI9
TCELL4:IMUX_B3ESB.WBDATI13
TCELL4:IMUX_B4ESB.WBDATI17
TCELL4:IMUX_B5ESB.WBDATI21
TCELL4:IMUX_C0ESB.WBDATI2
TCELL4:IMUX_C1ESB.WBDATI6
TCELL4:IMUX_C2ESB.WBDATI10
TCELL4:IMUX_C3ESB.WBDATI14
TCELL4:IMUX_C4ESB.WBDATI18
TCELL4:IMUX_C5ESB.WBDATI22
TCELL4:IMUX_D0ESB.WBDATI3
TCELL4:IMUX_D1ESB.WBDATI7
TCELL4:IMUX_D2ESB.WBDATI11
TCELL4:IMUX_D3ESB.WBDATI15
TCELL4:IMUX_D4ESB.WBDATI19
TCELL4:IMUX_D5ESB.WBDATI23
TCELL4:IMUX_CLK0ESB.WBCLKI
TCELL4:IMUX_CLK1ESB.ASFCLKI
TCELL4:IMUX_LSR0ESB.WBSTBI
TCELL4:IMUX_CE0ESB.WBRSTI
TCELL4:IMUX_CE1ESB.ASFRESETI
TCELL4:OUT_F0ESB.WBDATO0
TCELL4:OUT_F1ESB.WBDATO1
TCELL4:OUT_F2ESB.WBDATO2
TCELL4:OUT_F3ESB.WBDATO3
TCELL4:OUT_F4ESB.WBDATO4
TCELL4:OUT_F5ESB.WBDATO5
TCELL4:OUT_F6ESB.WBDATO6
TCELL4:OUT_F7ESB.WBDATO7
TCELL4:OUT_Q0ESB.WBDATO8
TCELL4:OUT_Q1ESB.WBDATO9
TCELL4:OUT_Q2ESB.WBDATO10
TCELL4:OUT_Q3ESB.WBDATO11
TCELL4:OUT_Q4ESB.WBDATO12
TCELL4:OUT_Q5ESB.WBDATO13
TCELL4:OUT_Q6ESB.WBDATO14
TCELL4:OUT_Q7ESB.WBDATO15
TCELL5:IMUX_A4ESB.WBDATI24
TCELL5:IMUX_A5ESB.WBDATI28
TCELL5:IMUX_B4ESB.WBDATI25
TCELL5:IMUX_B5ESB.WBDATI29
TCELL5:IMUX_C4ESB.WBDATI26
TCELL5:IMUX_C5ESB.WBDATI30
TCELL5:IMUX_D4ESB.WBDATI27
TCELL5:IMUX_D5ESB.WBDATI31
TCELL5:OUT_Q4ESB.WBDATO16
TCELL5:OUT_Q5ESB.WBDATO17
TCELL5:OUT_Q6ESB.WBDATO18
TCELL5:OUT_Q7ESB.WBDATO19
TCELL6:IMUX_A4ESB.WBADRI0
TCELL6:IMUX_A5ESB.WBADRI4
TCELL6:IMUX_B4ESB.WBADRI1
TCELL6:IMUX_B5ESB.WBADRI5
TCELL6:IMUX_C4ESB.WBADRI2
TCELL6:IMUX_C5ESB.WBADRI6
TCELL6:IMUX_D4ESB.WBADRI3
TCELL6:IMUX_D5ESB.WBADRI7
TCELL6:OUT_Q4ESB.WBDATO20
TCELL6:OUT_Q5ESB.WBDATO21
TCELL6:OUT_Q6ESB.WBDATO22
TCELL6:OUT_Q7ESB.WBDATO23
TCELL7:IMUX_A4ESB.WBADRI8
TCELL7:IMUX_A5ESB.WBADRI12
TCELL7:IMUX_B4ESB.WBADRI9
TCELL7:IMUX_B5ESB.WBADRI13
TCELL7:IMUX_C4ESB.WBADRI10
TCELL7:IMUX_C5ESB.WBADRI14
TCELL7:IMUX_D4ESB.WBADRI11
TCELL7:IMUX_D5ESB.WBADRI15
TCELL7:OUT_Q4ESB.WBDATO24
TCELL7:OUT_Q5ESB.WBDATO25
TCELL7:OUT_Q6ESB.WBDATO26
TCELL7:OUT_Q7ESB.WBDATO27
TCELL8:IMUX_A4ESB.WBADRI16
TCELL8:IMUX_B4ESB.WBADRI17
TCELL8:OUT_Q4ESB.WBDATO28
TCELL8:OUT_Q5ESB.WBDATO29
TCELL8:OUT_Q6ESB.WBDATO30
TCELL8:OUT_Q7ESB.WBDATO31
TCELL9:OUT_Q4ESB.WBACKO
TCELL9:OUT_Q5ESB.ASFFULLO
TCELL9:OUT_Q6ESB.ASFEMPTYO