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Block RAM

Tile EBR

Cells: 3

Bel EBR0

machxo2 EBR bel EBR0
PinDirectionWires
ADA0inputTCELL0:IMUX_A4
ADA1inputTCELL1:IMUX_B2
ADA10inputTCELL0:IMUX_C4
ADA11inputTCELL1:IMUX_B3
ADA12inputTCELL1:IMUX_D2
ADA2inputTCELL1:IMUX_A3
ADA3inputTCELL0:IMUX_D3
ADA4inputTCELL2:IMUX_C2
ADA5inputTCELL2:IMUX_B2
ADA6inputTCELL1:IMUX_D5
ADA7inputTCELL1:IMUX_A4
ADA8inputTCELL1:IMUX_C5
ADA9inputTCELL0:IMUX_B4
ADB0inputTCELL1:IMUX_C2
ADB1inputTCELL1:IMUX_A2
ADB10inputTCELL1:IMUX_D0
ADB11inputTCELL1:IMUX_B0
ADB12inputTCELL1:IMUX_C3
ADB2inputTCELL2:IMUX_C0
ADB3inputTCELL2:IMUX_D3
ADB4inputTCELL2:IMUX_B0
ADB5inputTCELL2:IMUX_A2
ADB6inputTCELL1:IMUX_D1
ADB7inputTCELL1:IMUX_A0
ADB8inputTCELL1:IMUX_C1
ADB9inputTCELL1:IMUX_C0
AEoutputTCELL1:OUT_Q4
AFoutputTCELL1:OUT_F4
CEAinputTCELL1:IMUX_CE1
CEBinputTCELL2:IMUX_CE1
CLKAinputTCELL1:IMUX_CLK0
CLKBinputTCELL1:IMUX_CLK3
CSA0inputTCELL1:IMUX_LSR0
CSA1inputTCELL1:IMUX_LSR1
CSA2inputTCELL1:IMUX_LSR2
CSB0inputTCELL2:IMUX_LSR0
CSB1inputTCELL2:IMUX_LSR1
CSB2inputTCELL2:IMUX_LSR2
DIA0inputTCELL2:IMUX_D0
DIA1inputTCELL1:IMUX_B5
DIA2inputTCELL1:IMUX_A5
DIA3inputTCELL2:IMUX_A3
DIA4inputTCELL2:IMUX_D2
DIA5inputTCELL2:IMUX_B1
DIA6inputTCELL2:IMUX_A1
DIA7inputTCELL2:IMUX_A0
DIA8inputTCELL2:IMUX_C1
DIB0inputTCELL2:IMUX_D1
DIB1inputTCELL1:IMUX_B4
DIB2inputTCELL1:IMUX_D4
DIB3inputTCELL2:IMUX_B3
DIB4inputTCELL2:IMUX_C3
DIB5inputTCELL2:IMUX_D4
DIB6inputTCELL2:IMUX_C4
DIB7inputTCELL2:IMUX_B4
DIB8inputTCELL2:IMUX_A4
DOA0outputTCELL0:OUT_F0
DOA1outputTCELL0:OUT_F1
DOA2outputTCELL0:OUT_F2
DOA3outputTCELL1:OUT_F0
DOA4outputTCELL1:OUT_F1
DOA5outputTCELL1:OUT_F2
DOA6outputTCELL2:OUT_F0
DOA7outputTCELL2:OUT_F1
DOA8outputTCELL2:OUT_F2
DOB0outputTCELL0:OUT_Q0
DOB1outputTCELL0:OUT_Q1
DOB2outputTCELL0:OUT_Q2
DOB3outputTCELL1:OUT_Q0
DOB4outputTCELL1:OUT_Q1
DOB5outputTCELL1:OUT_Q2
DOB6outputTCELL2:OUT_Q0
DOB7outputTCELL2:OUT_Q1
DOB8outputTCELL2:OUT_Q2
EFoutputTCELL1:OUT_Q3
FFoutputTCELL1:OUT_F3
OCEAinputTCELL0:IMUX_CE0
OCEBinputTCELL1:IMUX_CE0
RSTAinputTCELL0:IMUX_LSR2
RSTBinputTCELL0:IMUX_LSR0
WEAinputTCELL1:IMUX_LSR3
WEBinputTCELL2:IMUX_LSR3

Bel wires

machxo2 EBR bel wires
WirePins
TCELL0:IMUX_A4EBR0.ADA0
TCELL0:IMUX_B4EBR0.ADA9
TCELL0:IMUX_C4EBR0.ADA10
TCELL0:IMUX_D3EBR0.ADA3
TCELL0:IMUX_LSR0EBR0.RSTB
TCELL0:IMUX_LSR2EBR0.RSTA
TCELL0:IMUX_CE0EBR0.OCEA
TCELL0:OUT_F0EBR0.DOA0
TCELL0:OUT_F1EBR0.DOA1
TCELL0:OUT_F2EBR0.DOA2
TCELL0:OUT_Q0EBR0.DOB0
TCELL0:OUT_Q1EBR0.DOB1
TCELL0:OUT_Q2EBR0.DOB2
TCELL1:IMUX_A0EBR0.ADB7
TCELL1:IMUX_A2EBR0.ADB1
TCELL1:IMUX_A3EBR0.ADA2
TCELL1:IMUX_A4EBR0.ADA7
TCELL1:IMUX_A5EBR0.DIA2
TCELL1:IMUX_B0EBR0.ADB11
TCELL1:IMUX_B2EBR0.ADA1
TCELL1:IMUX_B3EBR0.ADA11
TCELL1:IMUX_B4EBR0.DIB1
TCELL1:IMUX_B5EBR0.DIA1
TCELL1:IMUX_C0EBR0.ADB9
TCELL1:IMUX_C1EBR0.ADB8
TCELL1:IMUX_C2EBR0.ADB0
TCELL1:IMUX_C3EBR0.ADB12
TCELL1:IMUX_C5EBR0.ADA8
TCELL1:IMUX_D0EBR0.ADB10
TCELL1:IMUX_D1EBR0.ADB6
TCELL1:IMUX_D2EBR0.ADA12
TCELL1:IMUX_D4EBR0.DIB2
TCELL1:IMUX_D5EBR0.ADA6
TCELL1:IMUX_CLK0EBR0.CLKA
TCELL1:IMUX_CLK3EBR0.CLKB
TCELL1:IMUX_LSR0EBR0.CSA0
TCELL1:IMUX_LSR1EBR0.CSA1
TCELL1:IMUX_LSR2EBR0.CSA2
TCELL1:IMUX_LSR3EBR0.WEA
TCELL1:IMUX_CE0EBR0.OCEB
TCELL1:IMUX_CE1EBR0.CEA
TCELL1:OUT_F0EBR0.DOA3
TCELL1:OUT_F1EBR0.DOA4
TCELL1:OUT_F2EBR0.DOA5
TCELL1:OUT_F3EBR0.FF
TCELL1:OUT_F4EBR0.AF
TCELL1:OUT_Q0EBR0.DOB3
TCELL1:OUT_Q1EBR0.DOB4
TCELL1:OUT_Q2EBR0.DOB5
TCELL1:OUT_Q3EBR0.EF
TCELL1:OUT_Q4EBR0.AE
TCELL2:IMUX_A0EBR0.DIA7
TCELL2:IMUX_A1EBR0.DIA6
TCELL2:IMUX_A2EBR0.ADB5
TCELL2:IMUX_A3EBR0.DIA3
TCELL2:IMUX_A4EBR0.DIB8
TCELL2:IMUX_B0EBR0.ADB4
TCELL2:IMUX_B1EBR0.DIA5
TCELL2:IMUX_B2EBR0.ADA5
TCELL2:IMUX_B3EBR0.DIB3
TCELL2:IMUX_B4EBR0.DIB7
TCELL2:IMUX_C0EBR0.ADB2
TCELL2:IMUX_C1EBR0.DIA8
TCELL2:IMUX_C2EBR0.ADA4
TCELL2:IMUX_C3EBR0.DIB4
TCELL2:IMUX_C4EBR0.DIB6
TCELL2:IMUX_D0EBR0.DIA0
TCELL2:IMUX_D1EBR0.DIB0
TCELL2:IMUX_D2EBR0.DIA4
TCELL2:IMUX_D3EBR0.ADB3
TCELL2:IMUX_D4EBR0.DIB5
TCELL2:IMUX_LSR0EBR0.CSB0
TCELL2:IMUX_LSR1EBR0.CSB1
TCELL2:IMUX_LSR2EBR0.CSB2
TCELL2:IMUX_LSR3EBR0.WEB
TCELL2:IMUX_CE1EBR0.CEB
TCELL2:OUT_F0EBR0.DOA6
TCELL2:OUT_F1EBR0.DOA7
TCELL2:OUT_F2EBR0.DOA8
TCELL2:OUT_Q0EBR0.DOB6
TCELL2:OUT_Q1EBR0.DOB7
TCELL2:OUT_Q2EBR0.DOB8

Tile EBR_N

Cells: 3

Bel EBR0

machxo2 EBR_N bel EBR0
PinDirectionWires
ADA0inputTCELL0:IMUX_A4
ADA1inputTCELL1:IMUX_B2
ADA10inputTCELL0:IMUX_C4
ADA11inputTCELL1:IMUX_B3
ADA12inputTCELL1:IMUX_D2
ADA2inputTCELL1:IMUX_A3
ADA3inputTCELL0:IMUX_D3
ADA4inputTCELL2:IMUX_C2
ADA5inputTCELL2:IMUX_B2
ADA6inputTCELL1:IMUX_D5
ADA7inputTCELL1:IMUX_A4
ADA8inputTCELL1:IMUX_C5
ADA9inputTCELL0:IMUX_B4
ADB0inputTCELL1:IMUX_C2
ADB1inputTCELL1:IMUX_A2
ADB10inputTCELL1:IMUX_D0
ADB11inputTCELL1:IMUX_B0
ADB12inputTCELL1:IMUX_C3
ADB2inputTCELL2:IMUX_C0
ADB3inputTCELL2:IMUX_D3
ADB4inputTCELL2:IMUX_B0
ADB5inputTCELL2:IMUX_A2
ADB6inputTCELL1:IMUX_D1
ADB7inputTCELL1:IMUX_A0
ADB8inputTCELL1:IMUX_C1
ADB9inputTCELL1:IMUX_C0
AEoutputTCELL1:OUT_Q4
AFoutputTCELL1:OUT_F4
CEAinputTCELL1:IMUX_CE1
CEBinputTCELL2:IMUX_CE1
CLKAinputTCELL1:IMUX_CLK0
CLKBinputTCELL1:IMUX_CLK3
CSA0inputTCELL1:IMUX_LSR0
CSA1inputTCELL1:IMUX_LSR1
CSA2inputTCELL1:IMUX_LSR2
CSB0inputTCELL2:IMUX_LSR0
CSB1inputTCELL2:IMUX_LSR1
CSB2inputTCELL2:IMUX_LSR2
DIA0inputTCELL2:IMUX_D0
DIA1inputTCELL1:IMUX_B5
DIA2inputTCELL1:IMUX_A5
DIA3inputTCELL2:IMUX_A3
DIA4inputTCELL2:IMUX_D2
DIA5inputTCELL2:IMUX_B1
DIA6inputTCELL2:IMUX_A1
DIA7inputTCELL2:IMUX_A0
DIA8inputTCELL2:IMUX_C1
DIB0inputTCELL2:IMUX_D1
DIB1inputTCELL1:IMUX_B4
DIB2inputTCELL1:IMUX_D4
DIB3inputTCELL2:IMUX_B3
DIB4inputTCELL2:IMUX_C3
DIB5inputTCELL2:IMUX_D4
DIB6inputTCELL2:IMUX_C4
DIB7inputTCELL2:IMUX_B4
DIB8inputTCELL2:IMUX_A4
DOA0outputTCELL0:OUT_F0
DOA1outputTCELL0:OUT_F1
DOA2outputTCELL0:OUT_F2
DOA3outputTCELL1:OUT_F0
DOA4outputTCELL1:OUT_F1
DOA5outputTCELL1:OUT_F2
DOA6outputTCELL2:OUT_F0
DOA7outputTCELL2:OUT_F1
DOA8outputTCELL2:OUT_F2
DOB0outputTCELL0:OUT_Q0
DOB1outputTCELL0:OUT_Q1
DOB2outputTCELL0:OUT_Q2
DOB3outputTCELL1:OUT_Q0
DOB4outputTCELL1:OUT_Q1
DOB5outputTCELL1:OUT_Q2
DOB6outputTCELL2:OUT_Q0
DOB7outputTCELL2:OUT_Q1
DOB8outputTCELL2:OUT_Q2
EFoutputTCELL1:OUT_Q3
FFoutputTCELL1:OUT_F3
OCEAinputTCELL0:IMUX_CE0
OCEBinputTCELL1:IMUX_CE0
RSTAinputTCELL0:IMUX_LSR2
RSTBinputTCELL0:IMUX_LSR0
WEAinputTCELL1:IMUX_LSR3
WEBinputTCELL2:IMUX_LSR3

Bel wires

machxo2 EBR_N bel wires
WirePins
TCELL0:IMUX_A4EBR0.ADA0
TCELL0:IMUX_B4EBR0.ADA9
TCELL0:IMUX_C4EBR0.ADA10
TCELL0:IMUX_D3EBR0.ADA3
TCELL0:IMUX_LSR0EBR0.RSTB
TCELL0:IMUX_LSR2EBR0.RSTA
TCELL0:IMUX_CE0EBR0.OCEA
TCELL0:OUT_F0EBR0.DOA0
TCELL0:OUT_F1EBR0.DOA1
TCELL0:OUT_F2EBR0.DOA2
TCELL0:OUT_Q0EBR0.DOB0
TCELL0:OUT_Q1EBR0.DOB1
TCELL0:OUT_Q2EBR0.DOB2
TCELL1:IMUX_A0EBR0.ADB7
TCELL1:IMUX_A2EBR0.ADB1
TCELL1:IMUX_A3EBR0.ADA2
TCELL1:IMUX_A4EBR0.ADA7
TCELL1:IMUX_A5EBR0.DIA2
TCELL1:IMUX_B0EBR0.ADB11
TCELL1:IMUX_B2EBR0.ADA1
TCELL1:IMUX_B3EBR0.ADA11
TCELL1:IMUX_B4EBR0.DIB1
TCELL1:IMUX_B5EBR0.DIA1
TCELL1:IMUX_C0EBR0.ADB9
TCELL1:IMUX_C1EBR0.ADB8
TCELL1:IMUX_C2EBR0.ADB0
TCELL1:IMUX_C3EBR0.ADB12
TCELL1:IMUX_C5EBR0.ADA8
TCELL1:IMUX_D0EBR0.ADB10
TCELL1:IMUX_D1EBR0.ADB6
TCELL1:IMUX_D2EBR0.ADA12
TCELL1:IMUX_D4EBR0.DIB2
TCELL1:IMUX_D5EBR0.ADA6
TCELL1:IMUX_CLK0EBR0.CLKA
TCELL1:IMUX_CLK3EBR0.CLKB
TCELL1:IMUX_LSR0EBR0.CSA0
TCELL1:IMUX_LSR1EBR0.CSA1
TCELL1:IMUX_LSR2EBR0.CSA2
TCELL1:IMUX_LSR3EBR0.WEA
TCELL1:IMUX_CE0EBR0.OCEB
TCELL1:IMUX_CE1EBR0.CEA
TCELL1:OUT_F0EBR0.DOA3
TCELL1:OUT_F1EBR0.DOA4
TCELL1:OUT_F2EBR0.DOA5
TCELL1:OUT_F3EBR0.FF
TCELL1:OUT_F4EBR0.AF
TCELL1:OUT_Q0EBR0.DOB3
TCELL1:OUT_Q1EBR0.DOB4
TCELL1:OUT_Q2EBR0.DOB5
TCELL1:OUT_Q3EBR0.EF
TCELL1:OUT_Q4EBR0.AE
TCELL2:IMUX_A0EBR0.DIA7
TCELL2:IMUX_A1EBR0.DIA6
TCELL2:IMUX_A2EBR0.ADB5
TCELL2:IMUX_A3EBR0.DIA3
TCELL2:IMUX_A4EBR0.DIB8
TCELL2:IMUX_B0EBR0.ADB4
TCELL2:IMUX_B1EBR0.DIA5
TCELL2:IMUX_B2EBR0.ADA5
TCELL2:IMUX_B3EBR0.DIB3
TCELL2:IMUX_B4EBR0.DIB7
TCELL2:IMUX_C0EBR0.ADB2
TCELL2:IMUX_C1EBR0.DIA8
TCELL2:IMUX_C2EBR0.ADA4
TCELL2:IMUX_C3EBR0.DIB4
TCELL2:IMUX_C4EBR0.DIB6
TCELL2:IMUX_D0EBR0.DIA0
TCELL2:IMUX_D1EBR0.DIB0
TCELL2:IMUX_D2EBR0.DIA4
TCELL2:IMUX_D3EBR0.ADB3
TCELL2:IMUX_D4EBR0.DIB5
TCELL2:IMUX_LSR0EBR0.CSB0
TCELL2:IMUX_LSR1EBR0.CSB1
TCELL2:IMUX_LSR2EBR0.CSB2
TCELL2:IMUX_LSR3EBR0.WEB
TCELL2:IMUX_CE1EBR0.CEB
TCELL2:OUT_F0EBR0.DOA6
TCELL2:OUT_F1EBR0.DOA7
TCELL2:OUT_F2EBR0.DOA8
TCELL2:OUT_Q0EBR0.DOB6
TCELL2:OUT_Q1EBR0.DOB7
TCELL2:OUT_Q2EBR0.DOB8