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Clock interconnect

Tile CLK_ROOT_0EBR

Cells: 8

Bel DCC0

machxo2 CLK_ROOT_0EBR bel DCC0
PinDirectionWires
CEinputCELL6.IMUX_A0

Bel DCC1

machxo2 CLK_ROOT_0EBR bel DCC1
PinDirectionWires
CEinputCELL6.IMUX_B0

Bel DCC2

machxo2 CLK_ROOT_0EBR bel DCC2
PinDirectionWires
CEinputCELL6.IMUX_C0

Bel DCC3

machxo2 CLK_ROOT_0EBR bel DCC3
PinDirectionWires
CEinputCELL6.IMUX_D0

Bel DCC4

machxo2 CLK_ROOT_0EBR bel DCC4
PinDirectionWires
CEinputCELL6.IMUX_A1

Bel DCC5

machxo2 CLK_ROOT_0EBR bel DCC5
PinDirectionWires
CEinputCELL6.IMUX_B1

Bel DCC6

machxo2 CLK_ROOT_0EBR bel DCC6
PinDirectionWires
CEinputCELL6.IMUX_C1

Bel DCC7

machxo2 CLK_ROOT_0EBR bel DCC7
PinDirectionWires
CEinputCELL6.IMUX_D1

Bel DCM0

machxo2 CLK_ROOT_0EBR bel DCM0
PinDirectionWires
SELinputCELL5.IMUX_A5

Bel DCM1

machxo2 CLK_ROOT_0EBR bel DCM1
PinDirectionWires
SELinputCELL5.IMUX_B5

Bel CLK_ROOT

machxo2 CLK_ROOT_0EBR bel CLK_ROOT
PinDirectionWires
PCLK_IN_E0inputCELL3.IMUX_CLK0
PCLK_IN_E1inputCELL3.IMUX_CLK1
PCLK_IN_N0inputCELL6.IMUX_CLK0
PCLK_IN_N1inputCELL6.IMUX_CLK1
PCLK_IN_S0inputCELL4.IMUX_CLK0
PCLK_IN_S1inputCELL4.IMUX_CLK1
PCLK_IN_W0inputCELL1.IMUX_CLK0
PCLK_IN_W1inputCELL1.IMUX_CLK1
SCLK_IN_E0inputCELL3.IMUX_A5
SCLK_IN_E1inputCELL3.IMUX_B5
SCLK_IN_M0inputCELL0.IMUX_A5
SCLK_IN_M1inputCELL0.IMUX_B5
SCLK_IN_M2inputCELL4.IMUX_C5
SCLK_IN_M3inputCELL4.IMUX_D5
SCLK_IN_M4inputCELL7.IMUX_A5
SCLK_IN_M5inputCELL7.IMUX_B5
SCLK_IN_M6inputCELL2.IMUX_C5
SCLK_IN_M7inputCELL2.IMUX_D5
SCLK_IN_N0inputCELL6.IMUX_A5
SCLK_IN_N1inputCELL6.IMUX_B5
SCLK_IN_S0inputCELL4.IMUX_A5
SCLK_IN_S1inputCELL4.IMUX_B5
SCLK_IN_W0inputCELL1.IMUX_A5
SCLK_IN_W1inputCELL1.IMUX_B5

Bel CLKTEST

machxo2 CLK_ROOT_0EBR bel CLKTEST
PinDirectionWires
TESTIN0inputCELL6.IMUX_A2
TESTIN1inputCELL6.IMUX_B2
TESTIN10inputCELL6.IMUX_C4
TESTIN2inputCELL6.IMUX_C2
TESTIN3inputCELL6.IMUX_D2
TESTIN4inputCELL6.IMUX_A3
TESTIN5inputCELL6.IMUX_B3
TESTIN6inputCELL6.IMUX_C3
TESTIN7inputCELL6.IMUX_D3
TESTIN8inputCELL6.IMUX_A4
TESTIN9inputCELL6.IMUX_B4

Bel wires

machxo2 CLK_ROOT_0EBR bel wires
WirePins
CELL0.IMUX_A5CLK_ROOT.SCLK_IN_M0
CELL0.IMUX_B5CLK_ROOT.SCLK_IN_M1
CELL1.IMUX_A5CLK_ROOT.SCLK_IN_W0
CELL1.IMUX_B5CLK_ROOT.SCLK_IN_W1
CELL1.IMUX_CLK0CLK_ROOT.PCLK_IN_W0
CELL1.IMUX_CLK1CLK_ROOT.PCLK_IN_W1
CELL2.IMUX_C5CLK_ROOT.SCLK_IN_M6
CELL2.IMUX_D5CLK_ROOT.SCLK_IN_M7
CELL3.IMUX_A5CLK_ROOT.SCLK_IN_E0
CELL3.IMUX_B5CLK_ROOT.SCLK_IN_E1
CELL3.IMUX_CLK0CLK_ROOT.PCLK_IN_E0
CELL3.IMUX_CLK1CLK_ROOT.PCLK_IN_E1
CELL4.IMUX_A5CLK_ROOT.SCLK_IN_S0
CELL4.IMUX_B5CLK_ROOT.SCLK_IN_S1
CELL4.IMUX_C5CLK_ROOT.SCLK_IN_M2
CELL4.IMUX_D5CLK_ROOT.SCLK_IN_M3
CELL4.IMUX_CLK0CLK_ROOT.PCLK_IN_S0
CELL4.IMUX_CLK1CLK_ROOT.PCLK_IN_S1
CELL5.IMUX_A5DCM0.SEL
CELL5.IMUX_B5DCM1.SEL
CELL6.IMUX_A0DCC0.CE
CELL6.IMUX_A1DCC4.CE
CELL6.IMUX_A2CLKTEST.TESTIN0
CELL6.IMUX_A3CLKTEST.TESTIN4
CELL6.IMUX_A4CLKTEST.TESTIN8
CELL6.IMUX_A5CLK_ROOT.SCLK_IN_N0
CELL6.IMUX_B0DCC1.CE
CELL6.IMUX_B1DCC5.CE
CELL6.IMUX_B2CLKTEST.TESTIN1
CELL6.IMUX_B3CLKTEST.TESTIN5
CELL6.IMUX_B4CLKTEST.TESTIN9
CELL6.IMUX_B5CLK_ROOT.SCLK_IN_N1
CELL6.IMUX_C0DCC2.CE
CELL6.IMUX_C1DCC6.CE
CELL6.IMUX_C2CLKTEST.TESTIN2
CELL6.IMUX_C3CLKTEST.TESTIN6
CELL6.IMUX_C4CLKTEST.TESTIN10
CELL6.IMUX_D0DCC3.CE
CELL6.IMUX_D1DCC7.CE
CELL6.IMUX_D2CLKTEST.TESTIN3
CELL6.IMUX_D3CLKTEST.TESTIN7
CELL6.IMUX_CLK0CLK_ROOT.PCLK_IN_N0
CELL6.IMUX_CLK1CLK_ROOT.PCLK_IN_N1
CELL7.IMUX_A5CLK_ROOT.SCLK_IN_M4
CELL7.IMUX_B5CLK_ROOT.SCLK_IN_M5

Tile CLK_ROOT_1EBR

Cells: 8

Bel DCC0

machxo2 CLK_ROOT_1EBR bel DCC0
PinDirectionWires
CEinputCELL2.IMUX_A0

Bel DCC1

machxo2 CLK_ROOT_1EBR bel DCC1
PinDirectionWires
CEinputCELL2.IMUX_B0

Bel DCC2

machxo2 CLK_ROOT_1EBR bel DCC2
PinDirectionWires
CEinputCELL2.IMUX_C0

Bel DCC3

machxo2 CLK_ROOT_1EBR bel DCC3
PinDirectionWires
CEinputCELL2.IMUX_D0

Bel DCC4

machxo2 CLK_ROOT_1EBR bel DCC4
PinDirectionWires
CEinputCELL2.IMUX_A1

Bel DCC5

machxo2 CLK_ROOT_1EBR bel DCC5
PinDirectionWires
CEinputCELL2.IMUX_B1

Bel DCC6

machxo2 CLK_ROOT_1EBR bel DCC6
PinDirectionWires
CEinputCELL2.IMUX_C1

Bel DCC7

machxo2 CLK_ROOT_1EBR bel DCC7
PinDirectionWires
CEinputCELL2.IMUX_D1

Bel DCM0

machxo2 CLK_ROOT_1EBR bel DCM0
PinDirectionWires
SELinputCELL2.IMUX_A5

Bel DCM1

machxo2 CLK_ROOT_1EBR bel DCM1
PinDirectionWires
SELinputCELL2.IMUX_B5

Bel ECLKBRIDGECS0

machxo2 CLK_ROOT_1EBR bel ECLKBRIDGECS0
PinDirectionWires
CLK0inputCELL6.IMUX_CLK2
CLK1inputCELL6.IMUX_CLK3
SELinputCELL0.IMUX_A5

Bel ECLKBRIDGECS1

machxo2 CLK_ROOT_1EBR bel ECLKBRIDGECS1
PinDirectionWires
CLK0inputCELL7.IMUX_CLK2
CLK1inputCELL7.IMUX_CLK3
SELinputCELL0.IMUX_B5

Bel CLK_ROOT

machxo2 CLK_ROOT_1EBR bel CLK_ROOT
PinDirectionWires
PCLK_IN_E0inputCELL5.IMUX_CLK0
PCLK_IN_E1inputCELL5.IMUX_CLK1
PCLK_IN_M2inputCELL2.IMUX_CLK0
PCLK_IN_M3inputCELL2.IMUX_CLK1
PCLK_IN_N0inputCELL7.IMUX_CLK0
PCLK_IN_N1inputCELL7.IMUX_CLK1
PCLK_IN_S0inputCELL6.IMUX_CLK0
PCLK_IN_S1inputCELL6.IMUX_CLK1
PCLK_IN_W0inputCELL4.IMUX_CLK0
PCLK_IN_W1inputCELL4.IMUX_CLK1
SCLK_IN_E0inputCELL5.IMUX_A5
SCLK_IN_E1inputCELL5.IMUX_B5
SCLK_IN_M0inputCELL1.IMUX_A5
SCLK_IN_M1inputCELL1.IMUX_B5
SCLK_IN_M2inputCELL1.IMUX_C5
SCLK_IN_M3inputCELL1.IMUX_D5
SCLK_IN_M4inputCELL3.IMUX_A5
SCLK_IN_M5inputCELL3.IMUX_B5
SCLK_IN_M6inputCELL3.IMUX_C5
SCLK_IN_M7inputCELL3.IMUX_D5
SCLK_IN_N0inputCELL7.IMUX_A5
SCLK_IN_N1inputCELL7.IMUX_B5
SCLK_IN_S0inputCELL6.IMUX_A5
SCLK_IN_S1inputCELL6.IMUX_B5
SCLK_IN_W0inputCELL4.IMUX_A5
SCLK_IN_W1inputCELL4.IMUX_B5

Bel CLKTEST

machxo2 CLK_ROOT_1EBR bel CLKTEST
PinDirectionWires
TESTIN0inputCELL2.IMUX_A2
TESTIN1inputCELL2.IMUX_B2
TESTIN10inputCELL2.IMUX_C4
TESTIN2inputCELL2.IMUX_C2
TESTIN3inputCELL2.IMUX_D2
TESTIN4inputCELL2.IMUX_A3
TESTIN5inputCELL2.IMUX_B3
TESTIN6inputCELL2.IMUX_C3
TESTIN7inputCELL2.IMUX_D3
TESTIN8inputCELL2.IMUX_A4
TESTIN9inputCELL2.IMUX_B4

Bel wires

machxo2 CLK_ROOT_1EBR bel wires
WirePins
CELL0.IMUX_A5ECLKBRIDGECS0.SEL
CELL0.IMUX_B5ECLKBRIDGECS1.SEL
CELL1.IMUX_A5CLK_ROOT.SCLK_IN_M0
CELL1.IMUX_B5CLK_ROOT.SCLK_IN_M1
CELL1.IMUX_C5CLK_ROOT.SCLK_IN_M2
CELL1.IMUX_D5CLK_ROOT.SCLK_IN_M3
CELL2.IMUX_A0DCC0.CE
CELL2.IMUX_A1DCC4.CE
CELL2.IMUX_A2CLKTEST.TESTIN0
CELL2.IMUX_A3CLKTEST.TESTIN4
CELL2.IMUX_A4CLKTEST.TESTIN8
CELL2.IMUX_A5DCM0.SEL
CELL2.IMUX_B0DCC1.CE
CELL2.IMUX_B1DCC5.CE
CELL2.IMUX_B2CLKTEST.TESTIN1
CELL2.IMUX_B3CLKTEST.TESTIN5
CELL2.IMUX_B4CLKTEST.TESTIN9
CELL2.IMUX_B5DCM1.SEL
CELL2.IMUX_C0DCC2.CE
CELL2.IMUX_C1DCC6.CE
CELL2.IMUX_C2CLKTEST.TESTIN2
CELL2.IMUX_C3CLKTEST.TESTIN6
CELL2.IMUX_C4CLKTEST.TESTIN10
CELL2.IMUX_D0DCC3.CE
CELL2.IMUX_D1DCC7.CE
CELL2.IMUX_D2CLKTEST.TESTIN3
CELL2.IMUX_D3CLKTEST.TESTIN7
CELL2.IMUX_CLK0CLK_ROOT.PCLK_IN_M2
CELL2.IMUX_CLK1CLK_ROOT.PCLK_IN_M3
CELL3.IMUX_A5CLK_ROOT.SCLK_IN_M4
CELL3.IMUX_B5CLK_ROOT.SCLK_IN_M5
CELL3.IMUX_C5CLK_ROOT.SCLK_IN_M6
CELL3.IMUX_D5CLK_ROOT.SCLK_IN_M7
CELL4.IMUX_A5CLK_ROOT.SCLK_IN_W0
CELL4.IMUX_B5CLK_ROOT.SCLK_IN_W1
CELL4.IMUX_CLK0CLK_ROOT.PCLK_IN_W0
CELL4.IMUX_CLK1CLK_ROOT.PCLK_IN_W1
CELL5.IMUX_A5CLK_ROOT.SCLK_IN_E0
CELL5.IMUX_B5CLK_ROOT.SCLK_IN_E1
CELL5.IMUX_CLK0CLK_ROOT.PCLK_IN_E0
CELL5.IMUX_CLK1CLK_ROOT.PCLK_IN_E1
CELL6.IMUX_A5CLK_ROOT.SCLK_IN_S0
CELL6.IMUX_B5CLK_ROOT.SCLK_IN_S1
CELL6.IMUX_CLK0CLK_ROOT.PCLK_IN_S0
CELL6.IMUX_CLK1CLK_ROOT.PCLK_IN_S1
CELL6.IMUX_CLK2ECLKBRIDGECS0.CLK0
CELL6.IMUX_CLK3ECLKBRIDGECS0.CLK1
CELL7.IMUX_A5CLK_ROOT.SCLK_IN_N0
CELL7.IMUX_B5CLK_ROOT.SCLK_IN_N1
CELL7.IMUX_CLK0CLK_ROOT.PCLK_IN_N0
CELL7.IMUX_CLK1CLK_ROOT.PCLK_IN_N1
CELL7.IMUX_CLK2ECLKBRIDGECS1.CLK0
CELL7.IMUX_CLK3ECLKBRIDGECS1.CLK1

Tile CLK_ROOT_2EBR

Cells: 13

Bel DCC0

machxo2 CLK_ROOT_2EBR bel DCC0
PinDirectionWires
CEinputCELL2.IMUX_A0

Bel DCC1

machxo2 CLK_ROOT_2EBR bel DCC1
PinDirectionWires
CEinputCELL2.IMUX_B0

Bel DCC2

machxo2 CLK_ROOT_2EBR bel DCC2
PinDirectionWires
CEinputCELL2.IMUX_C0

Bel DCC3

machxo2 CLK_ROOT_2EBR bel DCC3
PinDirectionWires
CEinputCELL2.IMUX_D0

Bel DCC4

machxo2 CLK_ROOT_2EBR bel DCC4
PinDirectionWires
CEinputCELL2.IMUX_A1

Bel DCC5

machxo2 CLK_ROOT_2EBR bel DCC5
PinDirectionWires
CEinputCELL2.IMUX_B1

Bel DCC6

machxo2 CLK_ROOT_2EBR bel DCC6
PinDirectionWires
CEinputCELL2.IMUX_C1

Bel DCC7

machxo2 CLK_ROOT_2EBR bel DCC7
PinDirectionWires
CEinputCELL2.IMUX_D1

Bel DCM0

machxo2 CLK_ROOT_2EBR bel DCM0
PinDirectionWires
SELinputCELL2.IMUX_A5

Bel DCM1

machxo2 CLK_ROOT_2EBR bel DCM1
PinDirectionWires
SELinputCELL2.IMUX_B5

Bel ECLKBRIDGECS0

machxo2 CLK_ROOT_2EBR bel ECLKBRIDGECS0
PinDirectionWires
CLK0inputCELL6.IMUX_CLK2
CLK1inputCELL6.IMUX_CLK3
SELinputCELL0.IMUX_A5

Bel ECLKBRIDGECS1

machxo2 CLK_ROOT_2EBR bel ECLKBRIDGECS1
PinDirectionWires
CLK0inputCELL7.IMUX_CLK2
CLK1inputCELL7.IMUX_CLK3
SELinputCELL0.IMUX_B5

Bel CLK_ROOT

machxo2 CLK_ROOT_2EBR bel CLK_ROOT
PinDirectionWires
PCLK_IN_E0inputCELL12.IMUX_CLK0
PCLK_IN_E1inputCELL12.IMUX_CLK1
PCLK_IN_E2inputCELL5.IMUX_CLK0
PCLK_IN_E3inputCELL5.IMUX_CLK1
PCLK_IN_M0inputCELL2.IMUX_CLK0
PCLK_IN_M1inputCELL2.IMUX_CLK1
PCLK_IN_M2inputCELL9.IMUX_CLK0
PCLK_IN_M3inputCELL9.IMUX_CLK1
PCLK_IN_N0inputCELL7.IMUX_CLK0
PCLK_IN_N1inputCELL7.IMUX_CLK1
PCLK_IN_S0inputCELL6.IMUX_CLK0
PCLK_IN_S1inputCELL6.IMUX_CLK1
PCLK_IN_W0inputCELL11.IMUX_CLK0
PCLK_IN_W1inputCELL11.IMUX_CLK1
PCLK_IN_W2inputCELL4.IMUX_CLK0
PCLK_IN_W3inputCELL4.IMUX_CLK1
SCLK_IN_E0inputCELL5.IMUX_A5
SCLK_IN_E1inputCELL5.IMUX_B5
SCLK_IN_M0inputCELL1.IMUX_A5
SCLK_IN_M1inputCELL1.IMUX_B5
SCLK_IN_M2inputCELL8.IMUX_C5
SCLK_IN_M3inputCELL8.IMUX_D5
SCLK_IN_M4inputCELL3.IMUX_A5
SCLK_IN_M5inputCELL3.IMUX_B5
SCLK_IN_M6inputCELL10.IMUX_C5
SCLK_IN_M7inputCELL10.IMUX_D5
SCLK_IN_N0inputCELL7.IMUX_A5
SCLK_IN_N1inputCELL7.IMUX_B5
SCLK_IN_S0inputCELL6.IMUX_A5
SCLK_IN_S1inputCELL6.IMUX_B5
SCLK_IN_W0inputCELL4.IMUX_A5
SCLK_IN_W1inputCELL4.IMUX_B5

Bel CLKTEST

machxo2 CLK_ROOT_2EBR bel CLKTEST
PinDirectionWires
TESTIN0inputCELL2.IMUX_A2
TESTIN1inputCELL2.IMUX_B2
TESTIN10inputCELL2.IMUX_C4
TESTIN2inputCELL2.IMUX_C2
TESTIN3inputCELL2.IMUX_D2
TESTIN4inputCELL2.IMUX_A3
TESTIN5inputCELL2.IMUX_B3
TESTIN6inputCELL2.IMUX_C3
TESTIN7inputCELL2.IMUX_D3
TESTIN8inputCELL2.IMUX_A4
TESTIN9inputCELL2.IMUX_B4

Bel wires

machxo2 CLK_ROOT_2EBR bel wires
WirePins
CELL0.IMUX_A5ECLKBRIDGECS0.SEL
CELL0.IMUX_B5ECLKBRIDGECS1.SEL
CELL1.IMUX_A5CLK_ROOT.SCLK_IN_M0
CELL1.IMUX_B5CLK_ROOT.SCLK_IN_M1
CELL2.IMUX_A0DCC0.CE
CELL2.IMUX_A1DCC4.CE
CELL2.IMUX_A2CLKTEST.TESTIN0
CELL2.IMUX_A3CLKTEST.TESTIN4
CELL2.IMUX_A4CLKTEST.TESTIN8
CELL2.IMUX_A5DCM0.SEL
CELL2.IMUX_B0DCC1.CE
CELL2.IMUX_B1DCC5.CE
CELL2.IMUX_B2CLKTEST.TESTIN1
CELL2.IMUX_B3CLKTEST.TESTIN5
CELL2.IMUX_B4CLKTEST.TESTIN9
CELL2.IMUX_B5DCM1.SEL
CELL2.IMUX_C0DCC2.CE
CELL2.IMUX_C1DCC6.CE
CELL2.IMUX_C2CLKTEST.TESTIN2
CELL2.IMUX_C3CLKTEST.TESTIN6
CELL2.IMUX_C4CLKTEST.TESTIN10
CELL2.IMUX_D0DCC3.CE
CELL2.IMUX_D1DCC7.CE
CELL2.IMUX_D2CLKTEST.TESTIN3
CELL2.IMUX_D3CLKTEST.TESTIN7
CELL2.IMUX_CLK0CLK_ROOT.PCLK_IN_M0
CELL2.IMUX_CLK1CLK_ROOT.PCLK_IN_M1
CELL3.IMUX_A5CLK_ROOT.SCLK_IN_M4
CELL3.IMUX_B5CLK_ROOT.SCLK_IN_M5
CELL4.IMUX_A5CLK_ROOT.SCLK_IN_W0
CELL4.IMUX_B5CLK_ROOT.SCLK_IN_W1
CELL4.IMUX_CLK0CLK_ROOT.PCLK_IN_W2
CELL4.IMUX_CLK1CLK_ROOT.PCLK_IN_W3
CELL5.IMUX_A5CLK_ROOT.SCLK_IN_E0
CELL5.IMUX_B5CLK_ROOT.SCLK_IN_E1
CELL5.IMUX_CLK0CLK_ROOT.PCLK_IN_E2
CELL5.IMUX_CLK1CLK_ROOT.PCLK_IN_E3
CELL6.IMUX_A5CLK_ROOT.SCLK_IN_S0
CELL6.IMUX_B5CLK_ROOT.SCLK_IN_S1
CELL6.IMUX_CLK0CLK_ROOT.PCLK_IN_S0
CELL6.IMUX_CLK1CLK_ROOT.PCLK_IN_S1
CELL6.IMUX_CLK2ECLKBRIDGECS0.CLK0
CELL6.IMUX_CLK3ECLKBRIDGECS0.CLK1
CELL7.IMUX_A5CLK_ROOT.SCLK_IN_N0
CELL7.IMUX_B5CLK_ROOT.SCLK_IN_N1
CELL7.IMUX_CLK0CLK_ROOT.PCLK_IN_N0
CELL7.IMUX_CLK1CLK_ROOT.PCLK_IN_N1
CELL7.IMUX_CLK2ECLKBRIDGECS1.CLK0
CELL7.IMUX_CLK3ECLKBRIDGECS1.CLK1
CELL8.IMUX_C5CLK_ROOT.SCLK_IN_M2
CELL8.IMUX_D5CLK_ROOT.SCLK_IN_M3
CELL9.IMUX_CLK0CLK_ROOT.PCLK_IN_M2
CELL9.IMUX_CLK1CLK_ROOT.PCLK_IN_M3
CELL10.IMUX_C5CLK_ROOT.SCLK_IN_M6
CELL10.IMUX_D5CLK_ROOT.SCLK_IN_M7
CELL11.IMUX_CLK0CLK_ROOT.PCLK_IN_W0
CELL11.IMUX_CLK1CLK_ROOT.PCLK_IN_W1
CELL12.IMUX_CLK0CLK_ROOT.PCLK_IN_E0
CELL12.IMUX_CLK1CLK_ROOT.PCLK_IN_E1

Tile CLK_ROOT_3EBR

Cells: 14

Bel DCC0

machxo2 CLK_ROOT_3EBR bel DCC0
PinDirectionWires
CEinputCELL1.IMUX_A0

Bel DCC1

machxo2 CLK_ROOT_3EBR bel DCC1
PinDirectionWires
CEinputCELL1.IMUX_B0

Bel DCC2

machxo2 CLK_ROOT_3EBR bel DCC2
PinDirectionWires
CEinputCELL1.IMUX_C0

Bel DCC3

machxo2 CLK_ROOT_3EBR bel DCC3
PinDirectionWires
CEinputCELL1.IMUX_D0

Bel DCC4

machxo2 CLK_ROOT_3EBR bel DCC4
PinDirectionWires
CEinputCELL1.IMUX_A1

Bel DCC5

machxo2 CLK_ROOT_3EBR bel DCC5
PinDirectionWires
CEinputCELL1.IMUX_B1

Bel DCC6

machxo2 CLK_ROOT_3EBR bel DCC6
PinDirectionWires
CEinputCELL1.IMUX_C1

Bel DCC7

machxo2 CLK_ROOT_3EBR bel DCC7
PinDirectionWires
CEinputCELL1.IMUX_D1

Bel DCM0

machxo2 CLK_ROOT_3EBR bel DCM0
PinDirectionWires
SELinputCELL1.IMUX_A5

Bel DCM1

machxo2 CLK_ROOT_3EBR bel DCM1
PinDirectionWires
SELinputCELL1.IMUX_B5

Bel ECLKBRIDGECS0

machxo2 CLK_ROOT_3EBR bel ECLKBRIDGECS0
PinDirectionWires
CLK0inputCELL4.IMUX_CLK2
CLK1inputCELL4.IMUX_CLK3
SELinputCELL0.IMUX_A5

Bel ECLKBRIDGECS1

machxo2 CLK_ROOT_3EBR bel ECLKBRIDGECS1
PinDirectionWires
CLK0inputCELL5.IMUX_CLK2
CLK1inputCELL5.IMUX_CLK3
SELinputCELL0.IMUX_B5

Bel CLK_ROOT

machxo2 CLK_ROOT_3EBR bel CLK_ROOT
PinDirectionWires
PCLK_IN_E0inputCELL13.IMUX_CLK0
PCLK_IN_E1inputCELL13.IMUX_CLK1
PCLK_IN_E2inputCELL3.IMUX_CLK0
PCLK_IN_E3inputCELL3.IMUX_CLK1
PCLK_IN_M0inputCELL10.IMUX_CLK0
PCLK_IN_M1inputCELL10.IMUX_CLK1
PCLK_IN_M2inputCELL7.IMUX_CLK0
PCLK_IN_M3inputCELL7.IMUX_CLK1
PCLK_IN_N0inputCELL5.IMUX_CLK0
PCLK_IN_N1inputCELL5.IMUX_CLK1
PCLK_IN_S0inputCELL4.IMUX_CLK0
PCLK_IN_S1inputCELL4.IMUX_CLK1
PCLK_IN_W0inputCELL12.IMUX_CLK0
PCLK_IN_W1inputCELL12.IMUX_CLK1
PCLK_IN_W2inputCELL2.IMUX_CLK0
PCLK_IN_W3inputCELL2.IMUX_CLK1
SCLK_IN_E0inputCELL3.IMUX_A5
SCLK_IN_E1inputCELL3.IMUX_B5
SCLK_IN_M0inputCELL9.IMUX_A5
SCLK_IN_M1inputCELL9.IMUX_B5
SCLK_IN_M2inputCELL6.IMUX_C5
SCLK_IN_M3inputCELL6.IMUX_D5
SCLK_IN_M4inputCELL11.IMUX_A5
SCLK_IN_M5inputCELL11.IMUX_B5
SCLK_IN_M6inputCELL8.IMUX_C5
SCLK_IN_M7inputCELL8.IMUX_D5
SCLK_IN_N0inputCELL5.IMUX_A5
SCLK_IN_N1inputCELL5.IMUX_B5
SCLK_IN_S0inputCELL4.IMUX_A5
SCLK_IN_S1inputCELL4.IMUX_B5
SCLK_IN_W0inputCELL2.IMUX_A5
SCLK_IN_W1inputCELL2.IMUX_B5

Bel CLKTEST

machxo2 CLK_ROOT_3EBR bel CLKTEST
PinDirectionWires
TESTIN0inputCELL1.IMUX_A2
TESTIN1inputCELL1.IMUX_B2
TESTIN10inputCELL1.IMUX_C4
TESTIN2inputCELL1.IMUX_C2
TESTIN3inputCELL1.IMUX_D2
TESTIN4inputCELL1.IMUX_A3
TESTIN5inputCELL1.IMUX_B3
TESTIN6inputCELL1.IMUX_C3
TESTIN7inputCELL1.IMUX_D3
TESTIN8inputCELL1.IMUX_A4
TESTIN9inputCELL1.IMUX_B4

Bel wires

machxo2 CLK_ROOT_3EBR bel wires
WirePins
CELL0.IMUX_A5ECLKBRIDGECS0.SEL
CELL0.IMUX_B5ECLKBRIDGECS1.SEL
CELL1.IMUX_A0DCC0.CE
CELL1.IMUX_A1DCC4.CE
CELL1.IMUX_A2CLKTEST.TESTIN0
CELL1.IMUX_A3CLKTEST.TESTIN4
CELL1.IMUX_A4CLKTEST.TESTIN8
CELL1.IMUX_A5DCM0.SEL
CELL1.IMUX_B0DCC1.CE
CELL1.IMUX_B1DCC5.CE
CELL1.IMUX_B2CLKTEST.TESTIN1
CELL1.IMUX_B3CLKTEST.TESTIN5
CELL1.IMUX_B4CLKTEST.TESTIN9
CELL1.IMUX_B5DCM1.SEL
CELL1.IMUX_C0DCC2.CE
CELL1.IMUX_C1DCC6.CE
CELL1.IMUX_C2CLKTEST.TESTIN2
CELL1.IMUX_C3CLKTEST.TESTIN6
CELL1.IMUX_C4CLKTEST.TESTIN10
CELL1.IMUX_D0DCC3.CE
CELL1.IMUX_D1DCC7.CE
CELL1.IMUX_D2CLKTEST.TESTIN3
CELL1.IMUX_D3CLKTEST.TESTIN7
CELL2.IMUX_A5CLK_ROOT.SCLK_IN_W0
CELL2.IMUX_B5CLK_ROOT.SCLK_IN_W1
CELL2.IMUX_CLK0CLK_ROOT.PCLK_IN_W2
CELL2.IMUX_CLK1CLK_ROOT.PCLK_IN_W3
CELL3.IMUX_A5CLK_ROOT.SCLK_IN_E0
CELL3.IMUX_B5CLK_ROOT.SCLK_IN_E1
CELL3.IMUX_CLK0CLK_ROOT.PCLK_IN_E2
CELL3.IMUX_CLK1CLK_ROOT.PCLK_IN_E3
CELL4.IMUX_A5CLK_ROOT.SCLK_IN_S0
CELL4.IMUX_B5CLK_ROOT.SCLK_IN_S1
CELL4.IMUX_CLK0CLK_ROOT.PCLK_IN_S0
CELL4.IMUX_CLK1CLK_ROOT.PCLK_IN_S1
CELL4.IMUX_CLK2ECLKBRIDGECS0.CLK0
CELL4.IMUX_CLK3ECLKBRIDGECS0.CLK1
CELL5.IMUX_A5CLK_ROOT.SCLK_IN_N0
CELL5.IMUX_B5CLK_ROOT.SCLK_IN_N1
CELL5.IMUX_CLK0CLK_ROOT.PCLK_IN_N0
CELL5.IMUX_CLK1CLK_ROOT.PCLK_IN_N1
CELL5.IMUX_CLK2ECLKBRIDGECS1.CLK0
CELL5.IMUX_CLK3ECLKBRIDGECS1.CLK1
CELL6.IMUX_C5CLK_ROOT.SCLK_IN_M2
CELL6.IMUX_D5CLK_ROOT.SCLK_IN_M3
CELL7.IMUX_CLK0CLK_ROOT.PCLK_IN_M2
CELL7.IMUX_CLK1CLK_ROOT.PCLK_IN_M3
CELL8.IMUX_C5CLK_ROOT.SCLK_IN_M6
CELL8.IMUX_D5CLK_ROOT.SCLK_IN_M7
CELL9.IMUX_A5CLK_ROOT.SCLK_IN_M0
CELL9.IMUX_B5CLK_ROOT.SCLK_IN_M1
CELL10.IMUX_CLK0CLK_ROOT.PCLK_IN_M0
CELL10.IMUX_CLK1CLK_ROOT.PCLK_IN_M1
CELL11.IMUX_A5CLK_ROOT.SCLK_IN_M4
CELL11.IMUX_B5CLK_ROOT.SCLK_IN_M5
CELL12.IMUX_CLK0CLK_ROOT.PCLK_IN_W0
CELL12.IMUX_CLK1CLK_ROOT.PCLK_IN_W1
CELL13.IMUX_CLK0CLK_ROOT.PCLK_IN_E0
CELL13.IMUX_CLK1CLK_ROOT.PCLK_IN_E1

Tile CLK_W

Cells: 1

Bel DLLDEL0

machxo2 CLK_W bel DLLDEL0
PinDirectionWires

Bel DLLDEL1

machxo2 CLK_W bel DLLDEL1
PinDirectionWires

Bel DLLDEL2

machxo2 CLK_W bel DLLDEL2
PinDirectionWires

Tile CLK_E

Cells: 1

Bel DLLDEL0

machxo2 CLK_E bel DLLDEL0
PinDirectionWires

Tile CLK_E_DQS

Cells: 5

Bel DQS0

machxo2 CLK_E_DQS bel DQS0
PinDirectionWires
BURSTDEToutputCELL4.OUT_Q4
DATAVALIDoutputCELL3.OUT_Q7
DDRCLKPOLoutputCELL3.OUT_Q4
DQSR90outputCELL3.OUT_Q5
DQSW90outputCELL3.OUT_Q6
READinputCELL3.IMUX_A5
READCLKSEL0inputCELL3.IMUX_B5
READCLKSEL1inputCELL3.IMUX_C5
RSTinputCELL4.IMUX_D5
SCLKinputCELL2.IMUX_CLK2

Bel DQS1

machxo2 CLK_E_DQS bel DQS1
PinDirectionWires
BURSTDEToutputCELL0.OUT_Q4
DATAVALIDoutputCELL1.OUT_Q7
DDRCLKPOLoutputCELL1.OUT_Q4
DQSR90outputCELL1.OUT_Q5
DQSW90outputCELL1.OUT_Q6
READinputCELL1.IMUX_A5
READCLKSEL0inputCELL1.IMUX_B5
READCLKSEL1inputCELL1.IMUX_C5
RSTinputCELL0.IMUX_D5
SCLKinputCELL2.IMUX_CLK3

Bel DLLDEL0

machxo2 CLK_E_DQS bel DLLDEL0
PinDirectionWires

Bel wires

machxo2 CLK_E_DQS bel wires
WirePins
CELL0.IMUX_D5DQS1.RST
CELL0.OUT_Q4DQS1.BURSTDET
CELL1.IMUX_A5DQS1.READ
CELL1.IMUX_B5DQS1.READCLKSEL0
CELL1.IMUX_C5DQS1.READCLKSEL1
CELL1.OUT_Q4DQS1.DDRCLKPOL
CELL1.OUT_Q5DQS1.DQSR90
CELL1.OUT_Q6DQS1.DQSW90
CELL1.OUT_Q7DQS1.DATAVALID
CELL2.IMUX_CLK2DQS0.SCLK
CELL2.IMUX_CLK3DQS1.SCLK
CELL3.IMUX_A5DQS0.READ
CELL3.IMUX_B5DQS0.READCLKSEL0
CELL3.IMUX_C5DQS0.READCLKSEL1
CELL3.OUT_Q4DQS0.DDRCLKPOL
CELL3.OUT_Q5DQS0.DQSR90
CELL3.OUT_Q6DQS0.DQSW90
CELL3.OUT_Q7DQS0.DATAVALID
CELL4.IMUX_D5DQS0.RST
CELL4.OUT_Q4DQS0.BURSTDET

Tile CLK_S

Cells: 1

Bel DLLDEL0

machxo2 CLK_S bel DLLDEL0
PinDirectionWires

Bel DLLDEL1

machxo2 CLK_S bel DLLDEL1
PinDirectionWires

Bel CLKDIV0

machxo2 CLK_S bel CLKDIV0
PinDirectionWires
ALIGNWDinputIMUX_A0
CDIV1outputOUT_F1
CDIVXoutputOUT_F0
RSTinputIMUX_A2

Bel CLKDIV1

machxo2 CLK_S bel CLKDIV1
PinDirectionWires
ALIGNWDinputIMUX_A1
CDIV1outputOUT_F3
CDIVXoutputOUT_F2
RSTinputIMUX_A3

Bel CLKFBBUF0

machxo2 CLK_S bel CLKFBBUF0
PinDirectionWires

Bel CLKFBBUF1

machxo2 CLK_S bel CLKFBBUF1
PinDirectionWires

Bel ECLKSYNC0

machxo2 CLK_S bel ECLKSYNC0
PinDirectionWires
ECLKIinputIMUX_CLK2
ECLKOoutputOUT_Q4
STOPinputIMUX_C5

Bel ECLKSYNC1

machxo2 CLK_S bel ECLKSYNC1
PinDirectionWires
ECLKIinputIMUX_CLK3
ECLKOoutputOUT_Q5
STOPinputIMUX_D5

Bel wires

machxo2 CLK_S bel wires
WirePins
IMUX_A0CLKDIV0.ALIGNWD
IMUX_A1CLKDIV1.ALIGNWD
IMUX_A2CLKDIV0.RST
IMUX_A3CLKDIV1.RST
IMUX_C5ECLKSYNC0.STOP
IMUX_D5ECLKSYNC1.STOP
IMUX_CLK2ECLKSYNC0.ECLKI
IMUX_CLK3ECLKSYNC1.ECLKI
OUT_F0CLKDIV0.CDIVX
OUT_F1CLKDIV0.CDIV1
OUT_F2CLKDIV1.CDIVX
OUT_F3CLKDIV1.CDIV1
OUT_Q4ECLKSYNC0.ECLKO
OUT_Q5ECLKSYNC1.ECLKO

Tile CLK_N

Cells: 1

Bel DLLDEL0

machxo2 CLK_N bel DLLDEL0
PinDirectionWires

Bel DLLDEL1

machxo2 CLK_N bel DLLDEL1
PinDirectionWires

Bel CLKDIV0

machxo2 CLK_N bel CLKDIV0
PinDirectionWires
ALIGNWDinputIMUX_A0
CDIV1outputOUT_F1
CDIVXoutputOUT_F0
RSTinputIMUX_A2

Bel CLKDIV1

machxo2 CLK_N bel CLKDIV1
PinDirectionWires
ALIGNWDinputIMUX_A1
CDIV1outputOUT_F3
CDIVXoutputOUT_F2
RSTinputIMUX_A3

Bel ECLKSYNC0

machxo2 CLK_N bel ECLKSYNC0
PinDirectionWires
ECLKIinputIMUX_CLK2
ECLKOoutputOUT_Q4
STOPinputIMUX_C5

Bel ECLKSYNC1

machxo2 CLK_N bel ECLKSYNC1
PinDirectionWires
ECLKIinputIMUX_CLK3
ECLKOoutputOUT_Q5
STOPinputIMUX_D5

Bel wires

machxo2 CLK_N bel wires
WirePins
IMUX_A0CLKDIV0.ALIGNWD
IMUX_A1CLKDIV1.ALIGNWD
IMUX_A2CLKDIV0.RST
IMUX_A3CLKDIV1.RST
IMUX_C5ECLKSYNC0.STOP
IMUX_D5ECLKSYNC1.STOP
IMUX_CLK2ECLKSYNC0.ECLKI
IMUX_CLK3ECLKSYNC1.ECLKI
OUT_F0CLKDIV0.CDIVX
OUT_F1CLKDIV0.CDIV1
OUT_F2CLKDIV1.CDIVX
OUT_F3CLKDIV1.CDIV1
OUT_Q4ECLKSYNC0.ECLKO
OUT_Q5ECLKSYNC1.ECLKO

Tile PCLK0_SOURCE

Cells: 2

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK0
OUT_SoutputCELL1.PCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK4
OUT_SoutputCELL1.PCLK4

Bel wires

machxo2 PCLK0_SOURCE bel wires
WirePins
CELL0.PCLK0PCLK_DCC0.OUT_N
CELL0.PCLK4PCLK_DCC1.OUT_N
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK0PCLK_DCC0.OUT_S
CELL1.PCLK4PCLK_DCC1.OUT_S

Tile PCLK0_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

machxo2 PCLK0_SOURCE_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N1outputCELL0.PCLK1
OUT_N5outputCELL0.PCLK5
OUT_S1outputCELL1.PCLK1
OUT_S5outputCELL1.PCLK5

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_E bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK0
OUT_SoutputCELL1.PCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_E bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK4
OUT_SoutputCELL1.PCLK4

Bel wires

machxo2 PCLK0_SOURCE_E bel wires
WirePins
CELL0.PCLK0PCLK_DCC0.OUT_N
CELL0.PCLK1PCLK_SOURCE_E.OUT_N1
CELL0.PCLK4PCLK_DCC1.OUT_N
CELL0.PCLK5PCLK_SOURCE_E.OUT_N5
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK0PCLK_DCC0.OUT_S
CELL1.PCLK1PCLK_SOURCE_E.OUT_S1
CELL1.PCLK4PCLK_DCC1.OUT_S
CELL1.PCLK5PCLK_SOURCE_E.OUT_S5

Tile PCLK0_SOURCE_IO_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_IO_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_IO_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK4

Bel wires

machxo2 PCLK0_SOURCE_IO_N bel wires
WirePins
PCLK0PCLK_DCC0.OUT_N
PCLK4PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK0_SOURCE_IO_N_E

Cells: 1

Bel PCLK_SOURCE_E

machxo2 PCLK0_SOURCE_IO_N_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N1outputPCLK1
OUT_N5outputPCLK5

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_IO_N_E bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_IO_N_E bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK4

Bel wires

machxo2 PCLK0_SOURCE_IO_N_E bel wires
WirePins
PCLK0PCLK_DCC0.OUT_N
PCLK1PCLK_SOURCE_E.OUT_N1
PCLK4PCLK_DCC1.OUT_N
PCLK5PCLK_SOURCE_E.OUT_N5
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK0_SOURCE_IO_N_W

Cells: 1

Bel PCLK_SOURCE_W

machxo2 PCLK0_SOURCE_IO_N_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N2outputPCLK2
OUT_N3outputPCLK3
OUT_N6outputPCLK6
OUT_N7outputPCLK7

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_IO_N_W bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_IO_N_W bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK4

Bel wires

machxo2 PCLK0_SOURCE_IO_N_W bel wires
WirePins
PCLK0PCLK_DCC0.OUT_N
PCLK2PCLK_SOURCE_W.OUT_N2
PCLK3PCLK_SOURCE_W.OUT_N3
PCLK4PCLK_DCC1.OUT_N
PCLK6PCLK_SOURCE_W.OUT_N6
PCLK7PCLK_SOURCE_W.OUT_N7
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK0_SOURCE_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK4

Bel wires

machxo2 PCLK0_SOURCE_N bel wires
WirePins
PCLK0PCLK_DCC0.OUT_N
PCLK4PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK0_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

machxo2 PCLK0_SOURCE_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N2outputCELL0.PCLK2
OUT_N3outputCELL0.PCLK3
OUT_N6outputCELL0.PCLK6
OUT_N7outputCELL0.PCLK7
OUT_S2outputCELL1.PCLK2
OUT_S3outputCELL1.PCLK3
OUT_S6outputCELL1.PCLK6
OUT_S7outputCELL1.PCLK7

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_W bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK0
OUT_SoutputCELL1.PCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_W bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK4
OUT_SoutputCELL1.PCLK4

Bel wires

machxo2 PCLK0_SOURCE_W bel wires
WirePins
CELL0.PCLK0PCLK_DCC0.OUT_N
CELL0.PCLK2PCLK_SOURCE_W.OUT_N2
CELL0.PCLK3PCLK_SOURCE_W.OUT_N3
CELL0.PCLK4PCLK_DCC1.OUT_N
CELL0.PCLK6PCLK_SOURCE_W.OUT_N6
CELL0.PCLK7PCLK_SOURCE_W.OUT_N7
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK0PCLK_DCC0.OUT_S
CELL1.PCLK2PCLK_SOURCE_W.OUT_S2
CELL1.PCLK3PCLK_SOURCE_W.OUT_S3
CELL1.PCLK4PCLK_DCC1.OUT_S
CELL1.PCLK6PCLK_SOURCE_W.OUT_S6
CELL1.PCLK7PCLK_SOURCE_W.OUT_S7

Tile PCLK1_SOURCE

Cells: 2

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK1
OUT_SoutputCELL1.PCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK5
OUT_SoutputCELL1.PCLK5

Bel wires

machxo2 PCLK1_SOURCE bel wires
WirePins
CELL0.PCLK1PCLK_DCC0.OUT_N
CELL0.PCLK5PCLK_DCC1.OUT_N
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK1PCLK_DCC0.OUT_S
CELL1.PCLK5PCLK_DCC1.OUT_S

Tile PCLK1_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

machxo2 PCLK1_SOURCE_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N2outputCELL0.PCLK2
OUT_N6outputCELL0.PCLK6
OUT_S2outputCELL1.PCLK2
OUT_S6outputCELL1.PCLK6

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_E bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK1
OUT_SoutputCELL1.PCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_E bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK5
OUT_SoutputCELL1.PCLK5

Bel wires

machxo2 PCLK1_SOURCE_E bel wires
WirePins
CELL0.PCLK1PCLK_DCC0.OUT_N
CELL0.PCLK2PCLK_SOURCE_E.OUT_N2
CELL0.PCLK5PCLK_DCC1.OUT_N
CELL0.PCLK6PCLK_SOURCE_E.OUT_N6
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK1PCLK_DCC0.OUT_S
CELL1.PCLK2PCLK_SOURCE_E.OUT_S2
CELL1.PCLK5PCLK_DCC1.OUT_S
CELL1.PCLK6PCLK_SOURCE_E.OUT_S6

Tile PCLK1_SOURCE_IO_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_IO_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_IO_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_IO_N bel wires
WirePins
PCLK1PCLK_DCC0.OUT_N
PCLK5PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_IO_N_E

Cells: 1

Bel PCLK_SOURCE_E

machxo2 PCLK1_SOURCE_IO_N_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N2outputPCLK2
OUT_N6outputPCLK6

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_IO_N_E bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_IO_N_E bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_IO_N_E bel wires
WirePins
PCLK1PCLK_DCC0.OUT_N
PCLK2PCLK_SOURCE_E.OUT_N2
PCLK5PCLK_DCC1.OUT_N
PCLK6PCLK_SOURCE_E.OUT_N6
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_N bel wires
WirePins
PCLK1PCLK_DCC0.OUT_N
PCLK5PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_N_E

Cells: 1

Bel PCLK_SOURCE_E

machxo2 PCLK1_SOURCE_N_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N2outputPCLK2
OUT_N6outputPCLK6

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_N_E bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_N_E bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_N_E bel wires
WirePins
PCLK1PCLK_DCC0.OUT_N
PCLK2PCLK_SOURCE_E.OUT_N2
PCLK5PCLK_DCC1.OUT_N
PCLK6PCLK_SOURCE_E.OUT_N6
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_N_W

Cells: 1

Bel PCLK_SOURCE_W

machxo2 PCLK1_SOURCE_N_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N0outputPCLK0
OUT_N3outputPCLK3
OUT_N4outputPCLK4
OUT_N7outputPCLK7

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_N_W bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_N_W bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_N_W bel wires
WirePins
PCLK0PCLK_SOURCE_W.OUT_N0
PCLK1PCLK_DCC0.OUT_N
PCLK3PCLK_SOURCE_W.OUT_N3
PCLK4PCLK_SOURCE_W.OUT_N4
PCLK5PCLK_DCC1.OUT_N
PCLK7PCLK_SOURCE_W.OUT_N7
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

machxo2 PCLK1_SOURCE_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N0outputCELL0.PCLK0
OUT_N3outputCELL0.PCLK3
OUT_N4outputCELL0.PCLK4
OUT_N7outputCELL0.PCLK7
OUT_S0outputCELL1.PCLK0
OUT_S3outputCELL1.PCLK3
OUT_S4outputCELL1.PCLK4
OUT_S7outputCELL1.PCLK7

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_W bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK1
OUT_SoutputCELL1.PCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_W bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK5
OUT_SoutputCELL1.PCLK5

Bel wires

machxo2 PCLK1_SOURCE_W bel wires
WirePins
CELL0.PCLK0PCLK_SOURCE_W.OUT_N0
CELL0.PCLK1PCLK_DCC0.OUT_N
CELL0.PCLK3PCLK_SOURCE_W.OUT_N3
CELL0.PCLK4PCLK_SOURCE_W.OUT_N4
CELL0.PCLK5PCLK_DCC1.OUT_N
CELL0.PCLK7PCLK_SOURCE_W.OUT_N7
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK0PCLK_SOURCE_W.OUT_S0
CELL1.PCLK1PCLK_DCC0.OUT_S
CELL1.PCLK3PCLK_SOURCE_W.OUT_S3
CELL1.PCLK4PCLK_SOURCE_W.OUT_S4
CELL1.PCLK5PCLK_DCC1.OUT_S
CELL1.PCLK7PCLK_SOURCE_W.OUT_S7

Tile PCLK2_SOURCE

Cells: 2

Bel PCLK_DCC0

machxo2 PCLK2_SOURCE bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK2
OUT_SoutputCELL1.PCLK2

Bel PCLK_DCC1

machxo2 PCLK2_SOURCE bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK6
OUT_SoutputCELL1.PCLK6

Bel wires

machxo2 PCLK2_SOURCE bel wires
WirePins
CELL0.PCLK2PCLK_DCC0.OUT_N
CELL0.PCLK6PCLK_DCC1.OUT_N
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK2PCLK_DCC0.OUT_S
CELL1.PCLK6PCLK_DCC1.OUT_S

Tile PCLK2_SOURCE_IO_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK2_SOURCE_IO_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK2

Bel PCLK_DCC1

machxo2 PCLK2_SOURCE_IO_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK6

Bel wires

machxo2 PCLK2_SOURCE_IO_N bel wires
WirePins
PCLK2PCLK_DCC0.OUT_N
PCLK6PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK2_SOURCE_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK2_SOURCE_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK2

Bel PCLK_DCC1

machxo2 PCLK2_SOURCE_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK6

Bel wires

machxo2 PCLK2_SOURCE_N bel wires
WirePins
PCLK2PCLK_DCC0.OUT_N
PCLK6PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK2_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

machxo2 PCLK2_SOURCE_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N0outputCELL0.PCLK0
OUT_N1outputCELL0.PCLK1
OUT_N4outputCELL0.PCLK4
OUT_N5outputCELL0.PCLK5
OUT_S0outputCELL1.PCLK0
OUT_S1outputCELL1.PCLK1
OUT_S4outputCELL1.PCLK4
OUT_S5outputCELL1.PCLK5

Bel PCLK_DCC0

machxo2 PCLK2_SOURCE_W bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK2
OUT_SoutputCELL1.PCLK2

Bel PCLK_DCC1

machxo2 PCLK2_SOURCE_W bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK6
OUT_SoutputCELL1.PCLK6

Bel wires

machxo2 PCLK2_SOURCE_W bel wires
WirePins
CELL0.PCLK0PCLK_SOURCE_W.OUT_N0
CELL0.PCLK1PCLK_SOURCE_W.OUT_N1
CELL0.PCLK2PCLK_DCC0.OUT_N
CELL0.PCLK4PCLK_SOURCE_W.OUT_N4
CELL0.PCLK5PCLK_SOURCE_W.OUT_N5
CELL0.PCLK6PCLK_DCC1.OUT_N
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK0PCLK_SOURCE_W.OUT_S0
CELL1.PCLK1PCLK_SOURCE_W.OUT_S1
CELL1.PCLK2PCLK_DCC0.OUT_S
CELL1.PCLK4PCLK_SOURCE_W.OUT_S4
CELL1.PCLK5PCLK_SOURCE_W.OUT_S5
CELL1.PCLK6PCLK_DCC1.OUT_S

Tile PCLK3_SOURCE

Cells: 2

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK3
OUT_SoutputCELL1.PCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK7
OUT_SoutputCELL1.PCLK7

Bel wires

machxo2 PCLK3_SOURCE bel wires
WirePins
CELL0.PCLK3PCLK_DCC0.OUT_N
CELL0.PCLK7PCLK_DCC1.OUT_N
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK3PCLK_DCC0.OUT_S
CELL1.PCLK7PCLK_DCC1.OUT_S

Tile PCLK3_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

machxo2 PCLK3_SOURCE_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N0outputCELL0.PCLK0
OUT_N4outputCELL0.PCLK4
OUT_S0outputCELL1.PCLK0
OUT_S4outputCELL1.PCLK4

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_E bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK3
OUT_SoutputCELL1.PCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_E bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK7
OUT_SoutputCELL1.PCLK7

Bel wires

machxo2 PCLK3_SOURCE_E bel wires
WirePins
CELL0.PCLK0PCLK_SOURCE_E.OUT_N0
CELL0.PCLK3PCLK_DCC0.OUT_N
CELL0.PCLK4PCLK_SOURCE_E.OUT_N4
CELL0.PCLK7PCLK_DCC1.OUT_N
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK0PCLK_SOURCE_E.OUT_S0
CELL1.PCLK3PCLK_DCC0.OUT_S
CELL1.PCLK4PCLK_SOURCE_E.OUT_S4
CELL1.PCLK7PCLK_DCC1.OUT_S

Tile PCLK3_SOURCE_IO_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_IO_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_IO_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK7

Bel wires

machxo2 PCLK3_SOURCE_IO_N bel wires
WirePins
PCLK3PCLK_DCC0.OUT_N
PCLK7PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK3_SOURCE_IO_N_W

Cells: 1

Bel PCLK_SOURCE_W

machxo2 PCLK3_SOURCE_IO_N_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N1outputPCLK1
OUT_N2outputPCLK2
OUT_N5outputPCLK5
OUT_N6outputPCLK6

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_IO_N_W bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_IO_N_W bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK7

Bel wires

machxo2 PCLK3_SOURCE_IO_N_W bel wires
WirePins
PCLK1PCLK_SOURCE_W.OUT_N1
PCLK2PCLK_SOURCE_W.OUT_N2
PCLK3PCLK_DCC0.OUT_N
PCLK5PCLK_SOURCE_W.OUT_N5
PCLK6PCLK_SOURCE_W.OUT_N6
PCLK7PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK3_SOURCE_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK7

Bel wires

machxo2 PCLK3_SOURCE_N bel wires
WirePins
PCLK3PCLK_DCC0.OUT_N
PCLK7PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK3_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

machxo2 PCLK3_SOURCE_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N1outputCELL0.PCLK1
OUT_N2outputCELL0.PCLK2
OUT_N5outputCELL0.PCLK5
OUT_N6outputCELL0.PCLK6
OUT_S1outputCELL1.PCLK1
OUT_S2outputCELL1.PCLK2
OUT_S5outputCELL1.PCLK5
OUT_S6outputCELL1.PCLK6

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_W bel PCLK_DCC0
PinDirectionWires
CEinputCELL0.IMUX_D6
OUT_NoutputCELL0.PCLK3
OUT_SoutputCELL1.PCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_W bel PCLK_DCC1
PinDirectionWires
CEinputCELL0.IMUX_D7
OUT_NoutputCELL0.PCLK7
OUT_SoutputCELL1.PCLK7

Bel wires

machxo2 PCLK3_SOURCE_W bel wires
WirePins
CELL0.PCLK1PCLK_SOURCE_W.OUT_N1
CELL0.PCLK2PCLK_SOURCE_W.OUT_N2
CELL0.PCLK3PCLK_DCC0.OUT_N
CELL0.PCLK5PCLK_SOURCE_W.OUT_N5
CELL0.PCLK6PCLK_SOURCE_W.OUT_N6
CELL0.PCLK7PCLK_DCC1.OUT_N
CELL0.IMUX_D6PCLK_DCC0.CE
CELL0.IMUX_D7PCLK_DCC1.CE
CELL1.PCLK1PCLK_SOURCE_W.OUT_S1
CELL1.PCLK2PCLK_SOURCE_W.OUT_S2
CELL1.PCLK3PCLK_DCC0.OUT_S
CELL1.PCLK5PCLK_SOURCE_W.OUT_S5
CELL1.PCLK6PCLK_SOURCE_W.OUT_S6
CELL1.PCLK7PCLK_DCC1.OUT_S

Tile HSDCLK_ROOT

Cells: 8

Bel HSDCLK_ROOT

machxo2 HSDCLK_ROOT bel HSDCLK_ROOT
PinDirectionWires
OUT_E0outputCELL4.HSDCLK0
OUT_E1outputCELL5.HSDCLK0
OUT_E2outputCELL6.HSDCLK0
OUT_E3outputCELL7.HSDCLK0
OUT_E4outputCELL4.HSDCLK4
OUT_E5outputCELL5.HSDCLK4
OUT_E6outputCELL6.HSDCLK4
OUT_E7outputCELL7.HSDCLK4
OUT_W0outputCELL0.HSDCLK0
OUT_W1outputCELL1.HSDCLK0
OUT_W2outputCELL2.HSDCLK0
OUT_W3outputCELL3.HSDCLK0
OUT_W4outputCELL0.HSDCLK4
OUT_W5outputCELL1.HSDCLK4
OUT_W6outputCELL2.HSDCLK4
OUT_W7outputCELL3.HSDCLK4

Switchbox HSDCLK_SPLITTER

machxo2 HSDCLK_ROOT switchbox HSDCLK_SPLITTER
DestinationSourceKind
CELL0.HSDCLK0CELL4.HSDCLK0buffer
CELL0.HSDCLK4CELL4.HSDCLK4buffer
CELL1.HSDCLK0CELL5.HSDCLK0buffer
CELL1.HSDCLK4CELL5.HSDCLK4buffer
CELL2.HSDCLK0CELL6.HSDCLK0buffer
CELL2.HSDCLK4CELL6.HSDCLK4buffer
CELL3.HSDCLK0CELL7.HSDCLK0buffer
CELL3.HSDCLK4CELL7.HSDCLK4buffer
CELL4.HSDCLK0CELL0.HSDCLK0buffer
CELL4.HSDCLK4CELL0.HSDCLK4buffer
CELL5.HSDCLK0CELL1.HSDCLK0buffer
CELL5.HSDCLK4CELL1.HSDCLK4buffer
CELL6.HSDCLK0CELL2.HSDCLK0buffer
CELL6.HSDCLK4CELL2.HSDCLK4buffer
CELL7.HSDCLK0CELL3.HSDCLK0buffer
CELL7.HSDCLK4CELL3.HSDCLK4buffer

Bel wires

machxo2 HSDCLK_ROOT bel wires
WirePins
CELL0.HSDCLK0HSDCLK_ROOT.OUT_W0
CELL0.HSDCLK4HSDCLK_ROOT.OUT_W4
CELL1.HSDCLK0HSDCLK_ROOT.OUT_W1
CELL1.HSDCLK4HSDCLK_ROOT.OUT_W5
CELL2.HSDCLK0HSDCLK_ROOT.OUT_W2
CELL2.HSDCLK4HSDCLK_ROOT.OUT_W6
CELL3.HSDCLK0HSDCLK_ROOT.OUT_W3
CELL3.HSDCLK4HSDCLK_ROOT.OUT_W7
CELL4.HSDCLK0HSDCLK_ROOT.OUT_E0
CELL4.HSDCLK4HSDCLK_ROOT.OUT_E4
CELL5.HSDCLK0HSDCLK_ROOT.OUT_E1
CELL5.HSDCLK4HSDCLK_ROOT.OUT_E5
CELL6.HSDCLK0HSDCLK_ROOT.OUT_E2
CELL6.HSDCLK4HSDCLK_ROOT.OUT_E6
CELL7.HSDCLK0HSDCLK_ROOT.OUT_E3
CELL7.HSDCLK4HSDCLK_ROOT.OUT_E7

Tile SCLK0_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK0_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK0fixed buffer
SCLK4VSDCLK1fixed buffer

Tile SCLK0_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK0_SOURCE_E switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK0fixed buffer
SCLK1VSDCLK2fixed buffer
SCLK4VSDCLK1fixed buffer
SCLK5VSDCLK3fixed buffer

Tile SCLK0_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK0_SOURCE_W switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK0fixed buffer
SCLK2VSDCLK4fixed buffer
SCLK3VSDCLK6fixed buffer
SCLK4VSDCLK1fixed buffer
SCLK6VSDCLK5fixed buffer
SCLK7VSDCLK7fixed buffer

Tile SCLK1_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK1_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK1VSDCLK0fixed buffer
SCLK5VSDCLK1fixed buffer

Tile SCLK1_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK1_SOURCE_E switchbox SCLK_SOURCE
DestinationSourceKind
SCLK1VSDCLK0fixed buffer
SCLK2VSDCLK2fixed buffer
SCLK5VSDCLK1fixed buffer
SCLK6VSDCLK3fixed buffer

Tile SCLK1_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK1_SOURCE_W switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK6fixed buffer
SCLK1VSDCLK0fixed buffer
SCLK3VSDCLK4fixed buffer
SCLK4VSDCLK7fixed buffer
SCLK5VSDCLK1fixed buffer
SCLK7VSDCLK5fixed buffer

Tile SCLK2_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK2_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK2VSDCLK0fixed buffer
SCLK6VSDCLK1fixed buffer

Tile SCLK2_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK2_SOURCE_E switchbox SCLK_SOURCE
DestinationSourceKind
SCLK2VSDCLK0fixed buffer
SCLK3VSDCLK2fixed buffer
SCLK6VSDCLK1fixed buffer
SCLK7VSDCLK3fixed buffer

Tile SCLK2_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK2_SOURCE_W switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK4fixed buffer
SCLK1VSDCLK6fixed buffer
SCLK2VSDCLK0fixed buffer
SCLK4VSDCLK5fixed buffer
SCLK5VSDCLK7fixed buffer
SCLK6VSDCLK1fixed buffer

Tile SCLK3_SOURCE

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK3_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK3VSDCLK0fixed buffer
SCLK7VSDCLK1fixed buffer

Tile SCLK3_SOURCE_E

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK3_SOURCE_E switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK2fixed buffer
SCLK3VSDCLK0fixed buffer
SCLK4VSDCLK3fixed buffer
SCLK7VSDCLK1fixed buffer

Tile SCLK3_SOURCE_W

Cells: 1

Switchbox SCLK_SOURCE

machxo2 SCLK3_SOURCE_W switchbox SCLK_SOURCE
DestinationSourceKind
SCLK1VSDCLK4fixed buffer
SCLK2VSDCLK6fixed buffer
SCLK3VSDCLK0fixed buffer
SCLK5VSDCLK5fixed buffer
SCLK6VSDCLK7fixed buffer
SCLK7VSDCLK1fixed buffer