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Clock interconnect

Tile CLK_ROOT_0EBR

Cells: 8

Bel DCC0

machxo2 CLK_ROOT_0EBR bel DCC0
PinDirectionWires
CEinputTCELL6:IMUX_A0

Bel DCC1

machxo2 CLK_ROOT_0EBR bel DCC1
PinDirectionWires
CEinputTCELL6:IMUX_B0

Bel DCC2

machxo2 CLK_ROOT_0EBR bel DCC2
PinDirectionWires
CEinputTCELL6:IMUX_C0

Bel DCC3

machxo2 CLK_ROOT_0EBR bel DCC3
PinDirectionWires
CEinputTCELL6:IMUX_D0

Bel DCC4

machxo2 CLK_ROOT_0EBR bel DCC4
PinDirectionWires
CEinputTCELL6:IMUX_A1

Bel DCC5

machxo2 CLK_ROOT_0EBR bel DCC5
PinDirectionWires
CEinputTCELL6:IMUX_B1

Bel DCC6

machxo2 CLK_ROOT_0EBR bel DCC6
PinDirectionWires
CEinputTCELL6:IMUX_C1

Bel DCC7

machxo2 CLK_ROOT_0EBR bel DCC7
PinDirectionWires
CEinputTCELL6:IMUX_D1

Bel DCM0

machxo2 CLK_ROOT_0EBR bel DCM0
PinDirectionWires
SELinputTCELL5:IMUX_A5

Bel DCM1

machxo2 CLK_ROOT_0EBR bel DCM1
PinDirectionWires
SELinputTCELL5:IMUX_B5

Bel CENTEST

machxo2 CLK_ROOT_0EBR bel CENTEST
PinDirectionWires
TESTIN0inputTCELL6:IMUX_A2
TESTIN1inputTCELL6:IMUX_B2
TESTIN10inputTCELL6:IMUX_C4
TESTIN2inputTCELL6:IMUX_C2
TESTIN3inputTCELL6:IMUX_D2
TESTIN4inputTCELL6:IMUX_A3
TESTIN5inputTCELL6:IMUX_B3
TESTIN6inputTCELL6:IMUX_C3
TESTIN7inputTCELL6:IMUX_D3
TESTIN8inputTCELL6:IMUX_A4
TESTIN9inputTCELL6:IMUX_B4

Bel CLK_ROOT

machxo2 CLK_ROOT_0EBR bel CLK_ROOT
PinDirectionWires
PCLK_IN_E0inputTCELL3:IMUX_CLK0
PCLK_IN_E1inputTCELL3:IMUX_CLK1
PCLK_IN_N0inputTCELL6:IMUX_CLK0
PCLK_IN_N1inputTCELL6:IMUX_CLK1
PCLK_IN_S0inputTCELL4:IMUX_CLK0
PCLK_IN_S1inputTCELL4:IMUX_CLK1
PCLK_IN_W0inputTCELL1:IMUX_CLK0
PCLK_IN_W1inputTCELL1:IMUX_CLK1
SCLK_IN_E0inputTCELL3:IMUX_A5
SCLK_IN_E1inputTCELL3:IMUX_B5
SCLK_IN_M0inputTCELL0:IMUX_A5
SCLK_IN_M1inputTCELL0:IMUX_B5
SCLK_IN_M2inputTCELL4:IMUX_C5
SCLK_IN_M3inputTCELL4:IMUX_D5
SCLK_IN_M4inputTCELL7:IMUX_A5
SCLK_IN_M5inputTCELL7:IMUX_B5
SCLK_IN_M6inputTCELL2:IMUX_C5
SCLK_IN_M7inputTCELL2:IMUX_D5
SCLK_IN_N0inputTCELL6:IMUX_A5
SCLK_IN_N1inputTCELL6:IMUX_B5
SCLK_IN_S0inputTCELL4:IMUX_A5
SCLK_IN_S1inputTCELL4:IMUX_B5
SCLK_IN_W0inputTCELL1:IMUX_A5
SCLK_IN_W1inputTCELL1:IMUX_B5

Bel wires

machxo2 CLK_ROOT_0EBR bel wires
WirePins
TCELL0:IMUX_A5CLK_ROOT.SCLK_IN_M0
TCELL0:IMUX_B5CLK_ROOT.SCLK_IN_M1
TCELL1:IMUX_A5CLK_ROOT.SCLK_IN_W0
TCELL1:IMUX_B5CLK_ROOT.SCLK_IN_W1
TCELL1:IMUX_CLK0CLK_ROOT.PCLK_IN_W0
TCELL1:IMUX_CLK1CLK_ROOT.PCLK_IN_W1
TCELL2:IMUX_C5CLK_ROOT.SCLK_IN_M6
TCELL2:IMUX_D5CLK_ROOT.SCLK_IN_M7
TCELL3:IMUX_A5CLK_ROOT.SCLK_IN_E0
TCELL3:IMUX_B5CLK_ROOT.SCLK_IN_E1
TCELL3:IMUX_CLK0CLK_ROOT.PCLK_IN_E0
TCELL3:IMUX_CLK1CLK_ROOT.PCLK_IN_E1
TCELL4:IMUX_A5CLK_ROOT.SCLK_IN_S0
TCELL4:IMUX_B5CLK_ROOT.SCLK_IN_S1
TCELL4:IMUX_C5CLK_ROOT.SCLK_IN_M2
TCELL4:IMUX_D5CLK_ROOT.SCLK_IN_M3
TCELL4:IMUX_CLK0CLK_ROOT.PCLK_IN_S0
TCELL4:IMUX_CLK1CLK_ROOT.PCLK_IN_S1
TCELL5:IMUX_A5DCM0.SEL
TCELL5:IMUX_B5DCM1.SEL
TCELL6:IMUX_A0DCC0.CE
TCELL6:IMUX_A1DCC4.CE
TCELL6:IMUX_A2CENTEST.TESTIN0
TCELL6:IMUX_A3CENTEST.TESTIN4
TCELL6:IMUX_A4CENTEST.TESTIN8
TCELL6:IMUX_A5CLK_ROOT.SCLK_IN_N0
TCELL6:IMUX_B0DCC1.CE
TCELL6:IMUX_B1DCC5.CE
TCELL6:IMUX_B2CENTEST.TESTIN1
TCELL6:IMUX_B3CENTEST.TESTIN5
TCELL6:IMUX_B4CENTEST.TESTIN9
TCELL6:IMUX_B5CLK_ROOT.SCLK_IN_N1
TCELL6:IMUX_C0DCC2.CE
TCELL6:IMUX_C1DCC6.CE
TCELL6:IMUX_C2CENTEST.TESTIN2
TCELL6:IMUX_C3CENTEST.TESTIN6
TCELL6:IMUX_C4CENTEST.TESTIN10
TCELL6:IMUX_D0DCC3.CE
TCELL6:IMUX_D1DCC7.CE
TCELL6:IMUX_D2CENTEST.TESTIN3
TCELL6:IMUX_D3CENTEST.TESTIN7
TCELL6:IMUX_CLK0CLK_ROOT.PCLK_IN_N0
TCELL6:IMUX_CLK1CLK_ROOT.PCLK_IN_N1
TCELL7:IMUX_A5CLK_ROOT.SCLK_IN_M4
TCELL7:IMUX_B5CLK_ROOT.SCLK_IN_M5

Tile CLK_ROOT_1EBR

Cells: 8

Bel DCC0

machxo2 CLK_ROOT_1EBR bel DCC0
PinDirectionWires
CEinputTCELL2:IMUX_A0

Bel DCC1

machxo2 CLK_ROOT_1EBR bel DCC1
PinDirectionWires
CEinputTCELL2:IMUX_B0

Bel DCC2

machxo2 CLK_ROOT_1EBR bel DCC2
PinDirectionWires
CEinputTCELL2:IMUX_C0

Bel DCC3

machxo2 CLK_ROOT_1EBR bel DCC3
PinDirectionWires
CEinputTCELL2:IMUX_D0

Bel DCC4

machxo2 CLK_ROOT_1EBR bel DCC4
PinDirectionWires
CEinputTCELL2:IMUX_A1

Bel DCC5

machxo2 CLK_ROOT_1EBR bel DCC5
PinDirectionWires
CEinputTCELL2:IMUX_B1

Bel DCC6

machxo2 CLK_ROOT_1EBR bel DCC6
PinDirectionWires
CEinputTCELL2:IMUX_C1

Bel DCC7

machxo2 CLK_ROOT_1EBR bel DCC7
PinDirectionWires
CEinputTCELL2:IMUX_D1

Bel DCM0

machxo2 CLK_ROOT_1EBR bel DCM0
PinDirectionWires
SELinputTCELL2:IMUX_A5

Bel DCM1

machxo2 CLK_ROOT_1EBR bel DCM1
PinDirectionWires
SELinputTCELL2:IMUX_B5

Bel ECLKBRIDGECS0

machxo2 CLK_ROOT_1EBR bel ECLKBRIDGECS0
PinDirectionWires
CLK0inputTCELL6:IMUX_CLK2
CLK1inputTCELL6:IMUX_CLK3
SELinputTCELL0:IMUX_A5

Bel ECLKBRIDGECS1

machxo2 CLK_ROOT_1EBR bel ECLKBRIDGECS1
PinDirectionWires
CLK0inputTCELL7:IMUX_CLK2
CLK1inputTCELL7:IMUX_CLK3
SELinputTCELL0:IMUX_B5

Bel CENTEST

machxo2 CLK_ROOT_1EBR bel CENTEST
PinDirectionWires
TESTIN0inputTCELL2:IMUX_A2
TESTIN1inputTCELL2:IMUX_B2
TESTIN10inputTCELL2:IMUX_C4
TESTIN2inputTCELL2:IMUX_C2
TESTIN3inputTCELL2:IMUX_D2
TESTIN4inputTCELL2:IMUX_A3
TESTIN5inputTCELL2:IMUX_B3
TESTIN6inputTCELL2:IMUX_C3
TESTIN7inputTCELL2:IMUX_D3
TESTIN8inputTCELL2:IMUX_A4
TESTIN9inputTCELL2:IMUX_B4

Bel CLK_ROOT

machxo2 CLK_ROOT_1EBR bel CLK_ROOT
PinDirectionWires
PCLK_IN_E0inputTCELL5:IMUX_CLK0
PCLK_IN_E1inputTCELL5:IMUX_CLK1
PCLK_IN_M2inputTCELL2:IMUX_CLK0
PCLK_IN_M3inputTCELL2:IMUX_CLK1
PCLK_IN_N0inputTCELL7:IMUX_CLK0
PCLK_IN_N1inputTCELL7:IMUX_CLK1
PCLK_IN_S0inputTCELL6:IMUX_CLK0
PCLK_IN_S1inputTCELL6:IMUX_CLK1
PCLK_IN_W0inputTCELL4:IMUX_CLK0
PCLK_IN_W1inputTCELL4:IMUX_CLK1
SCLK_IN_E0inputTCELL5:IMUX_A5
SCLK_IN_E1inputTCELL5:IMUX_B5
SCLK_IN_M0inputTCELL1:IMUX_A5
SCLK_IN_M1inputTCELL1:IMUX_B5
SCLK_IN_M2inputTCELL1:IMUX_C5
SCLK_IN_M3inputTCELL1:IMUX_D5
SCLK_IN_M4inputTCELL3:IMUX_A5
SCLK_IN_M5inputTCELL3:IMUX_B5
SCLK_IN_M6inputTCELL3:IMUX_C5
SCLK_IN_M7inputTCELL3:IMUX_D5
SCLK_IN_N0inputTCELL7:IMUX_A5
SCLK_IN_N1inputTCELL7:IMUX_B5
SCLK_IN_S0inputTCELL6:IMUX_A5
SCLK_IN_S1inputTCELL6:IMUX_B5
SCLK_IN_W0inputTCELL4:IMUX_A5
SCLK_IN_W1inputTCELL4:IMUX_B5

Bel wires

machxo2 CLK_ROOT_1EBR bel wires
WirePins
TCELL0:IMUX_A5ECLKBRIDGECS0.SEL
TCELL0:IMUX_B5ECLKBRIDGECS1.SEL
TCELL1:IMUX_A5CLK_ROOT.SCLK_IN_M0
TCELL1:IMUX_B5CLK_ROOT.SCLK_IN_M1
TCELL1:IMUX_C5CLK_ROOT.SCLK_IN_M2
TCELL1:IMUX_D5CLK_ROOT.SCLK_IN_M3
TCELL2:IMUX_A0DCC0.CE
TCELL2:IMUX_A1DCC4.CE
TCELL2:IMUX_A2CENTEST.TESTIN0
TCELL2:IMUX_A3CENTEST.TESTIN4
TCELL2:IMUX_A4CENTEST.TESTIN8
TCELL2:IMUX_A5DCM0.SEL
TCELL2:IMUX_B0DCC1.CE
TCELL2:IMUX_B1DCC5.CE
TCELL2:IMUX_B2CENTEST.TESTIN1
TCELL2:IMUX_B3CENTEST.TESTIN5
TCELL2:IMUX_B4CENTEST.TESTIN9
TCELL2:IMUX_B5DCM1.SEL
TCELL2:IMUX_C0DCC2.CE
TCELL2:IMUX_C1DCC6.CE
TCELL2:IMUX_C2CENTEST.TESTIN2
TCELL2:IMUX_C3CENTEST.TESTIN6
TCELL2:IMUX_C4CENTEST.TESTIN10
TCELL2:IMUX_D0DCC3.CE
TCELL2:IMUX_D1DCC7.CE
TCELL2:IMUX_D2CENTEST.TESTIN3
TCELL2:IMUX_D3CENTEST.TESTIN7
TCELL2:IMUX_CLK0CLK_ROOT.PCLK_IN_M2
TCELL2:IMUX_CLK1CLK_ROOT.PCLK_IN_M3
TCELL3:IMUX_A5CLK_ROOT.SCLK_IN_M4
TCELL3:IMUX_B5CLK_ROOT.SCLK_IN_M5
TCELL3:IMUX_C5CLK_ROOT.SCLK_IN_M6
TCELL3:IMUX_D5CLK_ROOT.SCLK_IN_M7
TCELL4:IMUX_A5CLK_ROOT.SCLK_IN_W0
TCELL4:IMUX_B5CLK_ROOT.SCLK_IN_W1
TCELL4:IMUX_CLK0CLK_ROOT.PCLK_IN_W0
TCELL4:IMUX_CLK1CLK_ROOT.PCLK_IN_W1
TCELL5:IMUX_A5CLK_ROOT.SCLK_IN_E0
TCELL5:IMUX_B5CLK_ROOT.SCLK_IN_E1
TCELL5:IMUX_CLK0CLK_ROOT.PCLK_IN_E0
TCELL5:IMUX_CLK1CLK_ROOT.PCLK_IN_E1
TCELL6:IMUX_A5CLK_ROOT.SCLK_IN_S0
TCELL6:IMUX_B5CLK_ROOT.SCLK_IN_S1
TCELL6:IMUX_CLK0CLK_ROOT.PCLK_IN_S0
TCELL6:IMUX_CLK1CLK_ROOT.PCLK_IN_S1
TCELL6:IMUX_CLK2ECLKBRIDGECS0.CLK0
TCELL6:IMUX_CLK3ECLKBRIDGECS0.CLK1
TCELL7:IMUX_A5CLK_ROOT.SCLK_IN_N0
TCELL7:IMUX_B5CLK_ROOT.SCLK_IN_N1
TCELL7:IMUX_CLK0CLK_ROOT.PCLK_IN_N0
TCELL7:IMUX_CLK1CLK_ROOT.PCLK_IN_N1
TCELL7:IMUX_CLK2ECLKBRIDGECS1.CLK0
TCELL7:IMUX_CLK3ECLKBRIDGECS1.CLK1

Tile CLK_ROOT_2EBR

Cells: 13

Bel DCC0

machxo2 CLK_ROOT_2EBR bel DCC0
PinDirectionWires
CEinputTCELL2:IMUX_A0

Bel DCC1

machxo2 CLK_ROOT_2EBR bel DCC1
PinDirectionWires
CEinputTCELL2:IMUX_B0

Bel DCC2

machxo2 CLK_ROOT_2EBR bel DCC2
PinDirectionWires
CEinputTCELL2:IMUX_C0

Bel DCC3

machxo2 CLK_ROOT_2EBR bel DCC3
PinDirectionWires
CEinputTCELL2:IMUX_D0

Bel DCC4

machxo2 CLK_ROOT_2EBR bel DCC4
PinDirectionWires
CEinputTCELL2:IMUX_A1

Bel DCC5

machxo2 CLK_ROOT_2EBR bel DCC5
PinDirectionWires
CEinputTCELL2:IMUX_B1

Bel DCC6

machxo2 CLK_ROOT_2EBR bel DCC6
PinDirectionWires
CEinputTCELL2:IMUX_C1

Bel DCC7

machxo2 CLK_ROOT_2EBR bel DCC7
PinDirectionWires
CEinputTCELL2:IMUX_D1

Bel DCM0

machxo2 CLK_ROOT_2EBR bel DCM0
PinDirectionWires
SELinputTCELL2:IMUX_A5

Bel DCM1

machxo2 CLK_ROOT_2EBR bel DCM1
PinDirectionWires
SELinputTCELL2:IMUX_B5

Bel ECLKBRIDGECS0

machxo2 CLK_ROOT_2EBR bel ECLKBRIDGECS0
PinDirectionWires
CLK0inputTCELL6:IMUX_CLK2
CLK1inputTCELL6:IMUX_CLK3
SELinputTCELL0:IMUX_A5

Bel ECLKBRIDGECS1

machxo2 CLK_ROOT_2EBR bel ECLKBRIDGECS1
PinDirectionWires
CLK0inputTCELL7:IMUX_CLK2
CLK1inputTCELL7:IMUX_CLK3
SELinputTCELL0:IMUX_B5

Bel CENTEST

machxo2 CLK_ROOT_2EBR bel CENTEST
PinDirectionWires
TESTIN0inputTCELL2:IMUX_A2
TESTIN1inputTCELL2:IMUX_B2
TESTIN10inputTCELL2:IMUX_C4
TESTIN2inputTCELL2:IMUX_C2
TESTIN3inputTCELL2:IMUX_D2
TESTIN4inputTCELL2:IMUX_A3
TESTIN5inputTCELL2:IMUX_B3
TESTIN6inputTCELL2:IMUX_C3
TESTIN7inputTCELL2:IMUX_D3
TESTIN8inputTCELL2:IMUX_A4
TESTIN9inputTCELL2:IMUX_B4

Bel CLK_ROOT

machxo2 CLK_ROOT_2EBR bel CLK_ROOT
PinDirectionWires
PCLK_IN_E0inputTCELL12:IMUX_CLK0
PCLK_IN_E1inputTCELL12:IMUX_CLK1
PCLK_IN_E2inputTCELL5:IMUX_CLK0
PCLK_IN_E3inputTCELL5:IMUX_CLK1
PCLK_IN_M0inputTCELL2:IMUX_CLK0
PCLK_IN_M1inputTCELL2:IMUX_CLK1
PCLK_IN_M2inputTCELL9:IMUX_CLK0
PCLK_IN_M3inputTCELL9:IMUX_CLK1
PCLK_IN_N0inputTCELL7:IMUX_CLK0
PCLK_IN_N1inputTCELL7:IMUX_CLK1
PCLK_IN_S0inputTCELL6:IMUX_CLK0
PCLK_IN_S1inputTCELL6:IMUX_CLK1
PCLK_IN_W0inputTCELL11:IMUX_CLK0
PCLK_IN_W1inputTCELL11:IMUX_CLK1
PCLK_IN_W2inputTCELL4:IMUX_CLK0
PCLK_IN_W3inputTCELL4:IMUX_CLK1
SCLK_IN_E0inputTCELL5:IMUX_A5
SCLK_IN_E1inputTCELL5:IMUX_B5
SCLK_IN_M0inputTCELL1:IMUX_A5
SCLK_IN_M1inputTCELL1:IMUX_B5
SCLK_IN_M2inputTCELL8:IMUX_C5
SCLK_IN_M3inputTCELL8:IMUX_D5
SCLK_IN_M4inputTCELL3:IMUX_A5
SCLK_IN_M5inputTCELL3:IMUX_B5
SCLK_IN_M6inputTCELL10:IMUX_C5
SCLK_IN_M7inputTCELL10:IMUX_D5
SCLK_IN_N0inputTCELL7:IMUX_A5
SCLK_IN_N1inputTCELL7:IMUX_B5
SCLK_IN_S0inputTCELL6:IMUX_A5
SCLK_IN_S1inputTCELL6:IMUX_B5
SCLK_IN_W0inputTCELL4:IMUX_A5
SCLK_IN_W1inputTCELL4:IMUX_B5

Bel wires

machxo2 CLK_ROOT_2EBR bel wires
WirePins
TCELL0:IMUX_A5ECLKBRIDGECS0.SEL
TCELL0:IMUX_B5ECLKBRIDGECS1.SEL
TCELL1:IMUX_A5CLK_ROOT.SCLK_IN_M0
TCELL1:IMUX_B5CLK_ROOT.SCLK_IN_M1
TCELL2:IMUX_A0DCC0.CE
TCELL2:IMUX_A1DCC4.CE
TCELL2:IMUX_A2CENTEST.TESTIN0
TCELL2:IMUX_A3CENTEST.TESTIN4
TCELL2:IMUX_A4CENTEST.TESTIN8
TCELL2:IMUX_A5DCM0.SEL
TCELL2:IMUX_B0DCC1.CE
TCELL2:IMUX_B1DCC5.CE
TCELL2:IMUX_B2CENTEST.TESTIN1
TCELL2:IMUX_B3CENTEST.TESTIN5
TCELL2:IMUX_B4CENTEST.TESTIN9
TCELL2:IMUX_B5DCM1.SEL
TCELL2:IMUX_C0DCC2.CE
TCELL2:IMUX_C1DCC6.CE
TCELL2:IMUX_C2CENTEST.TESTIN2
TCELL2:IMUX_C3CENTEST.TESTIN6
TCELL2:IMUX_C4CENTEST.TESTIN10
TCELL2:IMUX_D0DCC3.CE
TCELL2:IMUX_D1DCC7.CE
TCELL2:IMUX_D2CENTEST.TESTIN3
TCELL2:IMUX_D3CENTEST.TESTIN7
TCELL2:IMUX_CLK0CLK_ROOT.PCLK_IN_M0
TCELL2:IMUX_CLK1CLK_ROOT.PCLK_IN_M1
TCELL3:IMUX_A5CLK_ROOT.SCLK_IN_M4
TCELL3:IMUX_B5CLK_ROOT.SCLK_IN_M5
TCELL4:IMUX_A5CLK_ROOT.SCLK_IN_W0
TCELL4:IMUX_B5CLK_ROOT.SCLK_IN_W1
TCELL4:IMUX_CLK0CLK_ROOT.PCLK_IN_W2
TCELL4:IMUX_CLK1CLK_ROOT.PCLK_IN_W3
TCELL5:IMUX_A5CLK_ROOT.SCLK_IN_E0
TCELL5:IMUX_B5CLK_ROOT.SCLK_IN_E1
TCELL5:IMUX_CLK0CLK_ROOT.PCLK_IN_E2
TCELL5:IMUX_CLK1CLK_ROOT.PCLK_IN_E3
TCELL6:IMUX_A5CLK_ROOT.SCLK_IN_S0
TCELL6:IMUX_B5CLK_ROOT.SCLK_IN_S1
TCELL6:IMUX_CLK0CLK_ROOT.PCLK_IN_S0
TCELL6:IMUX_CLK1CLK_ROOT.PCLK_IN_S1
TCELL6:IMUX_CLK2ECLKBRIDGECS0.CLK0
TCELL6:IMUX_CLK3ECLKBRIDGECS0.CLK1
TCELL7:IMUX_A5CLK_ROOT.SCLK_IN_N0
TCELL7:IMUX_B5CLK_ROOT.SCLK_IN_N1
TCELL7:IMUX_CLK0CLK_ROOT.PCLK_IN_N0
TCELL7:IMUX_CLK1CLK_ROOT.PCLK_IN_N1
TCELL7:IMUX_CLK2ECLKBRIDGECS1.CLK0
TCELL7:IMUX_CLK3ECLKBRIDGECS1.CLK1
TCELL8:IMUX_C5CLK_ROOT.SCLK_IN_M2
TCELL8:IMUX_D5CLK_ROOT.SCLK_IN_M3
TCELL9:IMUX_CLK0CLK_ROOT.PCLK_IN_M2
TCELL9:IMUX_CLK1CLK_ROOT.PCLK_IN_M3
TCELL10:IMUX_C5CLK_ROOT.SCLK_IN_M6
TCELL10:IMUX_D5CLK_ROOT.SCLK_IN_M7
TCELL11:IMUX_CLK0CLK_ROOT.PCLK_IN_W0
TCELL11:IMUX_CLK1CLK_ROOT.PCLK_IN_W1
TCELL12:IMUX_CLK0CLK_ROOT.PCLK_IN_E0
TCELL12:IMUX_CLK1CLK_ROOT.PCLK_IN_E1

Tile CLK_ROOT_3EBR

Cells: 14

Bel DCC0

machxo2 CLK_ROOT_3EBR bel DCC0
PinDirectionWires
CEinputTCELL1:IMUX_A0

Bel DCC1

machxo2 CLK_ROOT_3EBR bel DCC1
PinDirectionWires
CEinputTCELL1:IMUX_B0

Bel DCC2

machxo2 CLK_ROOT_3EBR bel DCC2
PinDirectionWires
CEinputTCELL1:IMUX_C0

Bel DCC3

machxo2 CLK_ROOT_3EBR bel DCC3
PinDirectionWires
CEinputTCELL1:IMUX_D0

Bel DCC4

machxo2 CLK_ROOT_3EBR bel DCC4
PinDirectionWires
CEinputTCELL1:IMUX_A1

Bel DCC5

machxo2 CLK_ROOT_3EBR bel DCC5
PinDirectionWires
CEinputTCELL1:IMUX_B1

Bel DCC6

machxo2 CLK_ROOT_3EBR bel DCC6
PinDirectionWires
CEinputTCELL1:IMUX_C1

Bel DCC7

machxo2 CLK_ROOT_3EBR bel DCC7
PinDirectionWires
CEinputTCELL1:IMUX_D1

Bel DCM0

machxo2 CLK_ROOT_3EBR bel DCM0
PinDirectionWires
SELinputTCELL1:IMUX_A5

Bel DCM1

machxo2 CLK_ROOT_3EBR bel DCM1
PinDirectionWires
SELinputTCELL1:IMUX_B5

Bel ECLKBRIDGECS0

machxo2 CLK_ROOT_3EBR bel ECLKBRIDGECS0
PinDirectionWires
CLK0inputTCELL4:IMUX_CLK2
CLK1inputTCELL4:IMUX_CLK3
SELinputTCELL0:IMUX_A5

Bel ECLKBRIDGECS1

machxo2 CLK_ROOT_3EBR bel ECLKBRIDGECS1
PinDirectionWires
CLK0inputTCELL5:IMUX_CLK2
CLK1inputTCELL5:IMUX_CLK3
SELinputTCELL0:IMUX_B5

Bel CENTEST

machxo2 CLK_ROOT_3EBR bel CENTEST
PinDirectionWires
TESTIN0inputTCELL1:IMUX_A2
TESTIN1inputTCELL1:IMUX_B2
TESTIN10inputTCELL1:IMUX_C4
TESTIN2inputTCELL1:IMUX_C2
TESTIN3inputTCELL1:IMUX_D2
TESTIN4inputTCELL1:IMUX_A3
TESTIN5inputTCELL1:IMUX_B3
TESTIN6inputTCELL1:IMUX_C3
TESTIN7inputTCELL1:IMUX_D3
TESTIN8inputTCELL1:IMUX_A4
TESTIN9inputTCELL1:IMUX_B4

Bel CLK_ROOT

machxo2 CLK_ROOT_3EBR bel CLK_ROOT
PinDirectionWires
PCLK_IN_E0inputTCELL13:IMUX_CLK0
PCLK_IN_E1inputTCELL13:IMUX_CLK1
PCLK_IN_E2inputTCELL3:IMUX_CLK0
PCLK_IN_E3inputTCELL3:IMUX_CLK1
PCLK_IN_M0inputTCELL10:IMUX_CLK0
PCLK_IN_M1inputTCELL10:IMUX_CLK1
PCLK_IN_M2inputTCELL7:IMUX_CLK0
PCLK_IN_M3inputTCELL7:IMUX_CLK1
PCLK_IN_N0inputTCELL5:IMUX_CLK0
PCLK_IN_N1inputTCELL5:IMUX_CLK1
PCLK_IN_S0inputTCELL4:IMUX_CLK0
PCLK_IN_S1inputTCELL4:IMUX_CLK1
PCLK_IN_W0inputTCELL12:IMUX_CLK0
PCLK_IN_W1inputTCELL12:IMUX_CLK1
PCLK_IN_W2inputTCELL2:IMUX_CLK0
PCLK_IN_W3inputTCELL2:IMUX_CLK1
SCLK_IN_E0inputTCELL3:IMUX_A5
SCLK_IN_E1inputTCELL3:IMUX_B5
SCLK_IN_M0inputTCELL9:IMUX_A5
SCLK_IN_M1inputTCELL9:IMUX_B5
SCLK_IN_M2inputTCELL6:IMUX_C5
SCLK_IN_M3inputTCELL6:IMUX_D5
SCLK_IN_M4inputTCELL11:IMUX_A5
SCLK_IN_M5inputTCELL11:IMUX_B5
SCLK_IN_M6inputTCELL8:IMUX_C5
SCLK_IN_M7inputTCELL8:IMUX_D5
SCLK_IN_N0inputTCELL5:IMUX_A5
SCLK_IN_N1inputTCELL5:IMUX_B5
SCLK_IN_S0inputTCELL4:IMUX_A5
SCLK_IN_S1inputTCELL4:IMUX_B5
SCLK_IN_W0inputTCELL2:IMUX_A5
SCLK_IN_W1inputTCELL2:IMUX_B5

Bel wires

machxo2 CLK_ROOT_3EBR bel wires
WirePins
TCELL0:IMUX_A5ECLKBRIDGECS0.SEL
TCELL0:IMUX_B5ECLKBRIDGECS1.SEL
TCELL1:IMUX_A0DCC0.CE
TCELL1:IMUX_A1DCC4.CE
TCELL1:IMUX_A2CENTEST.TESTIN0
TCELL1:IMUX_A3CENTEST.TESTIN4
TCELL1:IMUX_A4CENTEST.TESTIN8
TCELL1:IMUX_A5DCM0.SEL
TCELL1:IMUX_B0DCC1.CE
TCELL1:IMUX_B1DCC5.CE
TCELL1:IMUX_B2CENTEST.TESTIN1
TCELL1:IMUX_B3CENTEST.TESTIN5
TCELL1:IMUX_B4CENTEST.TESTIN9
TCELL1:IMUX_B5DCM1.SEL
TCELL1:IMUX_C0DCC2.CE
TCELL1:IMUX_C1DCC6.CE
TCELL1:IMUX_C2CENTEST.TESTIN2
TCELL1:IMUX_C3CENTEST.TESTIN6
TCELL1:IMUX_C4CENTEST.TESTIN10
TCELL1:IMUX_D0DCC3.CE
TCELL1:IMUX_D1DCC7.CE
TCELL1:IMUX_D2CENTEST.TESTIN3
TCELL1:IMUX_D3CENTEST.TESTIN7
TCELL2:IMUX_A5CLK_ROOT.SCLK_IN_W0
TCELL2:IMUX_B5CLK_ROOT.SCLK_IN_W1
TCELL2:IMUX_CLK0CLK_ROOT.PCLK_IN_W2
TCELL2:IMUX_CLK1CLK_ROOT.PCLK_IN_W3
TCELL3:IMUX_A5CLK_ROOT.SCLK_IN_E0
TCELL3:IMUX_B5CLK_ROOT.SCLK_IN_E1
TCELL3:IMUX_CLK0CLK_ROOT.PCLK_IN_E2
TCELL3:IMUX_CLK1CLK_ROOT.PCLK_IN_E3
TCELL4:IMUX_A5CLK_ROOT.SCLK_IN_S0
TCELL4:IMUX_B5CLK_ROOT.SCLK_IN_S1
TCELL4:IMUX_CLK0CLK_ROOT.PCLK_IN_S0
TCELL4:IMUX_CLK1CLK_ROOT.PCLK_IN_S1
TCELL4:IMUX_CLK2ECLKBRIDGECS0.CLK0
TCELL4:IMUX_CLK3ECLKBRIDGECS0.CLK1
TCELL5:IMUX_A5CLK_ROOT.SCLK_IN_N0
TCELL5:IMUX_B5CLK_ROOT.SCLK_IN_N1
TCELL5:IMUX_CLK0CLK_ROOT.PCLK_IN_N0
TCELL5:IMUX_CLK1CLK_ROOT.PCLK_IN_N1
TCELL5:IMUX_CLK2ECLKBRIDGECS1.CLK0
TCELL5:IMUX_CLK3ECLKBRIDGECS1.CLK1
TCELL6:IMUX_C5CLK_ROOT.SCLK_IN_M2
TCELL6:IMUX_D5CLK_ROOT.SCLK_IN_M3
TCELL7:IMUX_CLK0CLK_ROOT.PCLK_IN_M2
TCELL7:IMUX_CLK1CLK_ROOT.PCLK_IN_M3
TCELL8:IMUX_C5CLK_ROOT.SCLK_IN_M6
TCELL8:IMUX_D5CLK_ROOT.SCLK_IN_M7
TCELL9:IMUX_A5CLK_ROOT.SCLK_IN_M0
TCELL9:IMUX_B5CLK_ROOT.SCLK_IN_M1
TCELL10:IMUX_CLK0CLK_ROOT.PCLK_IN_M0
TCELL10:IMUX_CLK1CLK_ROOT.PCLK_IN_M1
TCELL11:IMUX_A5CLK_ROOT.SCLK_IN_M4
TCELL11:IMUX_B5CLK_ROOT.SCLK_IN_M5
TCELL12:IMUX_CLK0CLK_ROOT.PCLK_IN_W0
TCELL12:IMUX_CLK1CLK_ROOT.PCLK_IN_W1
TCELL13:IMUX_CLK0CLK_ROOT.PCLK_IN_E0
TCELL13:IMUX_CLK1CLK_ROOT.PCLK_IN_E1

Tile CLK_W

Cells: 1

Bel DLLDEL0

machxo2 CLK_W bel DLLDEL0
PinDirectionWires

Bel DLLDEL1

machxo2 CLK_W bel DLLDEL1
PinDirectionWires

Bel DLLDEL2

machxo2 CLK_W bel DLLDEL2
PinDirectionWires

Tile CLK_E

Cells: 1

Bel DLLDEL0

machxo2 CLK_E bel DLLDEL0
PinDirectionWires

Tile CLK_E_DQS

Cells: 5

Bel DQS0

machxo2 CLK_E_DQS bel DQS0
PinDirectionWires
BURSTDEToutputTCELL4:OUT_Q4
DATAVALIDoutputTCELL3:OUT_Q7
DDRCLKPOLoutputTCELL3:OUT_Q4
DQSR90outputTCELL3:OUT_Q5
DQSW90outputTCELL3:OUT_Q6
READinputTCELL3:IMUX_A5
READCLKSEL0inputTCELL3:IMUX_B5
READCLKSEL1inputTCELL3:IMUX_C5
RSTinputTCELL4:IMUX_D5
SCLKinputTCELL2:IMUX_CLK2

Bel DQS1

machxo2 CLK_E_DQS bel DQS1
PinDirectionWires
BURSTDEToutputTCELL0:OUT_Q4
DATAVALIDoutputTCELL1:OUT_Q7
DDRCLKPOLoutputTCELL1:OUT_Q4
DQSR90outputTCELL1:OUT_Q5
DQSW90outputTCELL1:OUT_Q6
READinputTCELL1:IMUX_A5
READCLKSEL0inputTCELL1:IMUX_B5
READCLKSEL1inputTCELL1:IMUX_C5
RSTinputTCELL0:IMUX_D5
SCLKinputTCELL2:IMUX_CLK3

Bel DLLDEL0

machxo2 CLK_E_DQS bel DLLDEL0
PinDirectionWires

Bel wires

machxo2 CLK_E_DQS bel wires
WirePins
TCELL0:IMUX_D5DQS1.RST
TCELL0:OUT_Q4DQS1.BURSTDET
TCELL1:IMUX_A5DQS1.READ
TCELL1:IMUX_B5DQS1.READCLKSEL0
TCELL1:IMUX_C5DQS1.READCLKSEL1
TCELL1:OUT_Q4DQS1.DDRCLKPOL
TCELL1:OUT_Q5DQS1.DQSR90
TCELL1:OUT_Q6DQS1.DQSW90
TCELL1:OUT_Q7DQS1.DATAVALID
TCELL2:IMUX_CLK2DQS0.SCLK
TCELL2:IMUX_CLK3DQS1.SCLK
TCELL3:IMUX_A5DQS0.READ
TCELL3:IMUX_B5DQS0.READCLKSEL0
TCELL3:IMUX_C5DQS0.READCLKSEL1
TCELL3:OUT_Q4DQS0.DDRCLKPOL
TCELL3:OUT_Q5DQS0.DQSR90
TCELL3:OUT_Q6DQS0.DQSW90
TCELL3:OUT_Q7DQS0.DATAVALID
TCELL4:IMUX_D5DQS0.RST
TCELL4:OUT_Q4DQS0.BURSTDET

Tile CLK_S

Cells: 1

Bel DLLDEL0

machxo2 CLK_S bel DLLDEL0
PinDirectionWires

Bel DLLDEL1

machxo2 CLK_S bel DLLDEL1
PinDirectionWires

Bel CLKDIV0

machxo2 CLK_S bel CLKDIV0
PinDirectionWires
ALIGNWDinputIMUX_A0
CDIV1outputOUT_F1
CDIVXoutputOUT_F0
RSTinputIMUX_A2

Bel CLKDIV1

machxo2 CLK_S bel CLKDIV1
PinDirectionWires
ALIGNWDinputIMUX_A1
CDIV1outputOUT_F3
CDIVXoutputOUT_F2
RSTinputIMUX_A3

Bel CLKFBBUF0

machxo2 CLK_S bel CLKFBBUF0
PinDirectionWires

Bel CLKFBBUF1

machxo2 CLK_S bel CLKFBBUF1
PinDirectionWires

Bel ECLKSYNC0

machxo2 CLK_S bel ECLKSYNC0
PinDirectionWires
ECLKIinputIMUX_CLK2
ECLKOoutputOUT_Q4
STOPinputIMUX_C5

Bel ECLKSYNC1

machxo2 CLK_S bel ECLKSYNC1
PinDirectionWires
ECLKIinputIMUX_CLK3
ECLKOoutputOUT_Q5
STOPinputIMUX_D5

Bel wires

machxo2 CLK_S bel wires
WirePins
IMUX_A0CLKDIV0.ALIGNWD
IMUX_A1CLKDIV1.ALIGNWD
IMUX_A2CLKDIV0.RST
IMUX_A3CLKDIV1.RST
IMUX_C5ECLKSYNC0.STOP
IMUX_D5ECLKSYNC1.STOP
IMUX_CLK2ECLKSYNC0.ECLKI
IMUX_CLK3ECLKSYNC1.ECLKI
OUT_F0CLKDIV0.CDIVX
OUT_F1CLKDIV0.CDIV1
OUT_F2CLKDIV1.CDIVX
OUT_F3CLKDIV1.CDIV1
OUT_Q4ECLKSYNC0.ECLKO
OUT_Q5ECLKSYNC1.ECLKO

Tile CLK_N

Cells: 1

Bel DLLDEL0

machxo2 CLK_N bel DLLDEL0
PinDirectionWires

Bel DLLDEL1

machxo2 CLK_N bel DLLDEL1
PinDirectionWires

Bel CLKDIV0

machxo2 CLK_N bel CLKDIV0
PinDirectionWires
ALIGNWDinputIMUX_A0
CDIV1outputOUT_F1
CDIVXoutputOUT_F0
RSTinputIMUX_A2

Bel CLKDIV1

machxo2 CLK_N bel CLKDIV1
PinDirectionWires
ALIGNWDinputIMUX_A1
CDIV1outputOUT_F3
CDIVXoutputOUT_F2
RSTinputIMUX_A3

Bel ECLKSYNC0

machxo2 CLK_N bel ECLKSYNC0
PinDirectionWires
ECLKIinputIMUX_CLK2
ECLKOoutputOUT_Q4
STOPinputIMUX_C5

Bel ECLKSYNC1

machxo2 CLK_N bel ECLKSYNC1
PinDirectionWires
ECLKIinputIMUX_CLK3
ECLKOoutputOUT_Q5
STOPinputIMUX_D5

Bel wires

machxo2 CLK_N bel wires
WirePins
IMUX_A0CLKDIV0.ALIGNWD
IMUX_A1CLKDIV1.ALIGNWD
IMUX_A2CLKDIV0.RST
IMUX_A3CLKDIV1.RST
IMUX_C5ECLKSYNC0.STOP
IMUX_D5ECLKSYNC1.STOP
IMUX_CLK2ECLKSYNC0.ECLKI
IMUX_CLK3ECLKSYNC1.ECLKI
OUT_F0CLKDIV0.CDIVX
OUT_F1CLKDIV0.CDIV1
OUT_F2CLKDIV1.CDIVX
OUT_F3CLKDIV1.CDIV1
OUT_Q4ECLKSYNC0.ECLKO
OUT_Q5ECLKSYNC1.ECLKO

Tile PCLK0_SOURCE

Cells: 2

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK0
OUT_SoutputTCELL1:PCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK4
OUT_SoutputTCELL1:PCLK4

Bel wires

machxo2 PCLK0_SOURCE bel wires
WirePins
TCELL0:PCLK0PCLK_DCC0.OUT_N
TCELL0:PCLK4PCLK_DCC1.OUT_N
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK0PCLK_DCC0.OUT_S
TCELL1:PCLK4PCLK_DCC1.OUT_S

Tile PCLK0_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

machxo2 PCLK0_SOURCE_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N1outputTCELL0:PCLK1
OUT_N5outputTCELL0:PCLK5
OUT_S1outputTCELL1:PCLK1
OUT_S5outputTCELL1:PCLK5

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_E bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK0
OUT_SoutputTCELL1:PCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_E bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK4
OUT_SoutputTCELL1:PCLK4

Bel wires

machxo2 PCLK0_SOURCE_E bel wires
WirePins
TCELL0:PCLK0PCLK_DCC0.OUT_N
TCELL0:PCLK1PCLK_SOURCE_E.OUT_N1
TCELL0:PCLK4PCLK_DCC1.OUT_N
TCELL0:PCLK5PCLK_SOURCE_E.OUT_N5
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK0PCLK_DCC0.OUT_S
TCELL1:PCLK1PCLK_SOURCE_E.OUT_S1
TCELL1:PCLK4PCLK_DCC1.OUT_S
TCELL1:PCLK5PCLK_SOURCE_E.OUT_S5

Tile PCLK0_SOURCE_IO_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_IO_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_IO_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK4

Bel wires

machxo2 PCLK0_SOURCE_IO_N bel wires
WirePins
PCLK0PCLK_DCC0.OUT_N
PCLK4PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK0_SOURCE_IO_N_E

Cells: 1

Bel PCLK_SOURCE_E

machxo2 PCLK0_SOURCE_IO_N_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N1outputPCLK1
OUT_N5outputPCLK5

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_IO_N_E bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_IO_N_E bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK4

Bel wires

machxo2 PCLK0_SOURCE_IO_N_E bel wires
WirePins
PCLK0PCLK_DCC0.OUT_N
PCLK1PCLK_SOURCE_E.OUT_N1
PCLK4PCLK_DCC1.OUT_N
PCLK5PCLK_SOURCE_E.OUT_N5
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK0_SOURCE_IO_N_W

Cells: 1

Bel PCLK_SOURCE_W

machxo2 PCLK0_SOURCE_IO_N_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N2outputPCLK2
OUT_N3outputPCLK3
OUT_N6outputPCLK6
OUT_N7outputPCLK7

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_IO_N_W bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_IO_N_W bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK4

Bel wires

machxo2 PCLK0_SOURCE_IO_N_W bel wires
WirePins
PCLK0PCLK_DCC0.OUT_N
PCLK2PCLK_SOURCE_W.OUT_N2
PCLK3PCLK_SOURCE_W.OUT_N3
PCLK4PCLK_DCC1.OUT_N
PCLK6PCLK_SOURCE_W.OUT_N6
PCLK7PCLK_SOURCE_W.OUT_N7
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK0_SOURCE_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK4

Bel wires

machxo2 PCLK0_SOURCE_N bel wires
WirePins
PCLK0PCLK_DCC0.OUT_N
PCLK4PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK0_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

machxo2 PCLK0_SOURCE_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N2outputTCELL0:PCLK2
OUT_N3outputTCELL0:PCLK3
OUT_N6outputTCELL0:PCLK6
OUT_N7outputTCELL0:PCLK7
OUT_S2outputTCELL1:PCLK2
OUT_S3outputTCELL1:PCLK3
OUT_S6outputTCELL1:PCLK6
OUT_S7outputTCELL1:PCLK7

Bel PCLK_DCC0

machxo2 PCLK0_SOURCE_W bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK0
OUT_SoutputTCELL1:PCLK0

Bel PCLK_DCC1

machxo2 PCLK0_SOURCE_W bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK4
OUT_SoutputTCELL1:PCLK4

Bel wires

machxo2 PCLK0_SOURCE_W bel wires
WirePins
TCELL0:PCLK0PCLK_DCC0.OUT_N
TCELL0:PCLK2PCLK_SOURCE_W.OUT_N2
TCELL0:PCLK3PCLK_SOURCE_W.OUT_N3
TCELL0:PCLK4PCLK_DCC1.OUT_N
TCELL0:PCLK6PCLK_SOURCE_W.OUT_N6
TCELL0:PCLK7PCLK_SOURCE_W.OUT_N7
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK0PCLK_DCC0.OUT_S
TCELL1:PCLK2PCLK_SOURCE_W.OUT_S2
TCELL1:PCLK3PCLK_SOURCE_W.OUT_S3
TCELL1:PCLK4PCLK_DCC1.OUT_S
TCELL1:PCLK6PCLK_SOURCE_W.OUT_S6
TCELL1:PCLK7PCLK_SOURCE_W.OUT_S7

Tile PCLK1_SOURCE

Cells: 2

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK1
OUT_SoutputTCELL1:PCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK5
OUT_SoutputTCELL1:PCLK5

Bel wires

machxo2 PCLK1_SOURCE bel wires
WirePins
TCELL0:PCLK1PCLK_DCC0.OUT_N
TCELL0:PCLK5PCLK_DCC1.OUT_N
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK1PCLK_DCC0.OUT_S
TCELL1:PCLK5PCLK_DCC1.OUT_S

Tile PCLK1_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

machxo2 PCLK1_SOURCE_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N2outputTCELL0:PCLK2
OUT_N6outputTCELL0:PCLK6
OUT_S2outputTCELL1:PCLK2
OUT_S6outputTCELL1:PCLK6

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_E bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK1
OUT_SoutputTCELL1:PCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_E bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK5
OUT_SoutputTCELL1:PCLK5

Bel wires

machxo2 PCLK1_SOURCE_E bel wires
WirePins
TCELL0:PCLK1PCLK_DCC0.OUT_N
TCELL0:PCLK2PCLK_SOURCE_E.OUT_N2
TCELL0:PCLK5PCLK_DCC1.OUT_N
TCELL0:PCLK6PCLK_SOURCE_E.OUT_N6
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK1PCLK_DCC0.OUT_S
TCELL1:PCLK2PCLK_SOURCE_E.OUT_S2
TCELL1:PCLK5PCLK_DCC1.OUT_S
TCELL1:PCLK6PCLK_SOURCE_E.OUT_S6

Tile PCLK1_SOURCE_IO_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_IO_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_IO_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_IO_N bel wires
WirePins
PCLK1PCLK_DCC0.OUT_N
PCLK5PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_IO_N_E

Cells: 1

Bel PCLK_SOURCE_E

machxo2 PCLK1_SOURCE_IO_N_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N2outputPCLK2
OUT_N6outputPCLK6

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_IO_N_E bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_IO_N_E bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_IO_N_E bel wires
WirePins
PCLK1PCLK_DCC0.OUT_N
PCLK2PCLK_SOURCE_E.OUT_N2
PCLK5PCLK_DCC1.OUT_N
PCLK6PCLK_SOURCE_E.OUT_N6
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_N bel wires
WirePins
PCLK1PCLK_DCC0.OUT_N
PCLK5PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_N_E

Cells: 1

Bel PCLK_SOURCE_E

machxo2 PCLK1_SOURCE_N_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N2outputPCLK2
OUT_N6outputPCLK6

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_N_E bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_N_E bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_N_E bel wires
WirePins
PCLK1PCLK_DCC0.OUT_N
PCLK2PCLK_SOURCE_E.OUT_N2
PCLK5PCLK_DCC1.OUT_N
PCLK6PCLK_SOURCE_E.OUT_N6
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_N_W

Cells: 1

Bel PCLK_SOURCE_W

machxo2 PCLK1_SOURCE_N_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N0outputPCLK0
OUT_N3outputPCLK3
OUT_N4outputPCLK4
OUT_N7outputPCLK7

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_N_W bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_N_W bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK5

Bel wires

machxo2 PCLK1_SOURCE_N_W bel wires
WirePins
PCLK0PCLK_SOURCE_W.OUT_N0
PCLK1PCLK_DCC0.OUT_N
PCLK3PCLK_SOURCE_W.OUT_N3
PCLK4PCLK_SOURCE_W.OUT_N4
PCLK5PCLK_DCC1.OUT_N
PCLK7PCLK_SOURCE_W.OUT_N7
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK1_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

machxo2 PCLK1_SOURCE_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N0outputTCELL0:PCLK0
OUT_N3outputTCELL0:PCLK3
OUT_N4outputTCELL0:PCLK4
OUT_N7outputTCELL0:PCLK7
OUT_S0outputTCELL1:PCLK0
OUT_S3outputTCELL1:PCLK3
OUT_S4outputTCELL1:PCLK4
OUT_S7outputTCELL1:PCLK7

Bel PCLK_DCC0

machxo2 PCLK1_SOURCE_W bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK1
OUT_SoutputTCELL1:PCLK1

Bel PCLK_DCC1

machxo2 PCLK1_SOURCE_W bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK5
OUT_SoutputTCELL1:PCLK5

Bel wires

machxo2 PCLK1_SOURCE_W bel wires
WirePins
TCELL0:PCLK0PCLK_SOURCE_W.OUT_N0
TCELL0:PCLK1PCLK_DCC0.OUT_N
TCELL0:PCLK3PCLK_SOURCE_W.OUT_N3
TCELL0:PCLK4PCLK_SOURCE_W.OUT_N4
TCELL0:PCLK5PCLK_DCC1.OUT_N
TCELL0:PCLK7PCLK_SOURCE_W.OUT_N7
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK0PCLK_SOURCE_W.OUT_S0
TCELL1:PCLK1PCLK_DCC0.OUT_S
TCELL1:PCLK3PCLK_SOURCE_W.OUT_S3
TCELL1:PCLK4PCLK_SOURCE_W.OUT_S4
TCELL1:PCLK5PCLK_DCC1.OUT_S
TCELL1:PCLK7PCLK_SOURCE_W.OUT_S7

Tile PCLK2_SOURCE

Cells: 2

Bel PCLK_DCC0

machxo2 PCLK2_SOURCE bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK2
OUT_SoutputTCELL1:PCLK2

Bel PCLK_DCC1

machxo2 PCLK2_SOURCE bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK6
OUT_SoutputTCELL1:PCLK6

Bel wires

machxo2 PCLK2_SOURCE bel wires
WirePins
TCELL0:PCLK2PCLK_DCC0.OUT_N
TCELL0:PCLK6PCLK_DCC1.OUT_N
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK2PCLK_DCC0.OUT_S
TCELL1:PCLK6PCLK_DCC1.OUT_S

Tile PCLK2_SOURCE_IO_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK2_SOURCE_IO_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK2

Bel PCLK_DCC1

machxo2 PCLK2_SOURCE_IO_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK6

Bel wires

machxo2 PCLK2_SOURCE_IO_N bel wires
WirePins
PCLK2PCLK_DCC0.OUT_N
PCLK6PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK2_SOURCE_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK2_SOURCE_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK2

Bel PCLK_DCC1

machxo2 PCLK2_SOURCE_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK6

Bel wires

machxo2 PCLK2_SOURCE_N bel wires
WirePins
PCLK2PCLK_DCC0.OUT_N
PCLK6PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK2_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

machxo2 PCLK2_SOURCE_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N0outputTCELL0:PCLK0
OUT_N1outputTCELL0:PCLK1
OUT_N4outputTCELL0:PCLK4
OUT_N5outputTCELL0:PCLK5
OUT_S0outputTCELL1:PCLK0
OUT_S1outputTCELL1:PCLK1
OUT_S4outputTCELL1:PCLK4
OUT_S5outputTCELL1:PCLK5

Bel PCLK_DCC0

machxo2 PCLK2_SOURCE_W bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK2
OUT_SoutputTCELL1:PCLK2

Bel PCLK_DCC1

machxo2 PCLK2_SOURCE_W bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK6
OUT_SoutputTCELL1:PCLK6

Bel wires

machxo2 PCLK2_SOURCE_W bel wires
WirePins
TCELL0:PCLK0PCLK_SOURCE_W.OUT_N0
TCELL0:PCLK1PCLK_SOURCE_W.OUT_N1
TCELL0:PCLK2PCLK_DCC0.OUT_N
TCELL0:PCLK4PCLK_SOURCE_W.OUT_N4
TCELL0:PCLK5PCLK_SOURCE_W.OUT_N5
TCELL0:PCLK6PCLK_DCC1.OUT_N
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK0PCLK_SOURCE_W.OUT_S0
TCELL1:PCLK1PCLK_SOURCE_W.OUT_S1
TCELL1:PCLK2PCLK_DCC0.OUT_S
TCELL1:PCLK4PCLK_SOURCE_W.OUT_S4
TCELL1:PCLK5PCLK_SOURCE_W.OUT_S5
TCELL1:PCLK6PCLK_DCC1.OUT_S

Tile PCLK3_SOURCE

Cells: 2

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK3
OUT_SoutputTCELL1:PCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK7
OUT_SoutputTCELL1:PCLK7

Bel wires

machxo2 PCLK3_SOURCE bel wires
WirePins
TCELL0:PCLK3PCLK_DCC0.OUT_N
TCELL0:PCLK7PCLK_DCC1.OUT_N
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK3PCLK_DCC0.OUT_S
TCELL1:PCLK7PCLK_DCC1.OUT_S

Tile PCLK3_SOURCE_E

Cells: 2

Bel PCLK_SOURCE_E

machxo2 PCLK3_SOURCE_E bel PCLK_SOURCE_E
PinDirectionWires
OUT_N0outputTCELL0:PCLK0
OUT_N4outputTCELL0:PCLK4
OUT_S0outputTCELL1:PCLK0
OUT_S4outputTCELL1:PCLK4

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_E bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK3
OUT_SoutputTCELL1:PCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_E bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK7
OUT_SoutputTCELL1:PCLK7

Bel wires

machxo2 PCLK3_SOURCE_E bel wires
WirePins
TCELL0:PCLK0PCLK_SOURCE_E.OUT_N0
TCELL0:PCLK3PCLK_DCC0.OUT_N
TCELL0:PCLK4PCLK_SOURCE_E.OUT_N4
TCELL0:PCLK7PCLK_DCC1.OUT_N
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK0PCLK_SOURCE_E.OUT_S0
TCELL1:PCLK3PCLK_DCC0.OUT_S
TCELL1:PCLK4PCLK_SOURCE_E.OUT_S4
TCELL1:PCLK7PCLK_DCC1.OUT_S

Tile PCLK3_SOURCE_IO_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_IO_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_IO_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK7

Bel wires

machxo2 PCLK3_SOURCE_IO_N bel wires
WirePins
PCLK3PCLK_DCC0.OUT_N
PCLK7PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK3_SOURCE_IO_N_W

Cells: 1

Bel PCLK_SOURCE_W

machxo2 PCLK3_SOURCE_IO_N_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N1outputPCLK1
OUT_N2outputPCLK2
OUT_N5outputPCLK5
OUT_N6outputPCLK6

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_IO_N_W bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_IO_N_W bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK7

Bel wires

machxo2 PCLK3_SOURCE_IO_N_W bel wires
WirePins
PCLK1PCLK_SOURCE_W.OUT_N1
PCLK2PCLK_SOURCE_W.OUT_N2
PCLK3PCLK_DCC0.OUT_N
PCLK5PCLK_SOURCE_W.OUT_N5
PCLK6PCLK_SOURCE_W.OUT_N6
PCLK7PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK3_SOURCE_N

Cells: 1

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_N bel PCLK_DCC0
PinDirectionWires
CEinputIMUX_D6
OUT_NoutputPCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_N bel PCLK_DCC1
PinDirectionWires
CEinputIMUX_D7
OUT_NoutputPCLK7

Bel wires

machxo2 PCLK3_SOURCE_N bel wires
WirePins
PCLK3PCLK_DCC0.OUT_N
PCLK7PCLK_DCC1.OUT_N
IMUX_D6PCLK_DCC0.CE
IMUX_D7PCLK_DCC1.CE

Tile PCLK3_SOURCE_W

Cells: 2

Bel PCLK_SOURCE_W

machxo2 PCLK3_SOURCE_W bel PCLK_SOURCE_W
PinDirectionWires
OUT_N1outputTCELL0:PCLK1
OUT_N2outputTCELL0:PCLK2
OUT_N5outputTCELL0:PCLK5
OUT_N6outputTCELL0:PCLK6
OUT_S1outputTCELL1:PCLK1
OUT_S2outputTCELL1:PCLK2
OUT_S5outputTCELL1:PCLK5
OUT_S6outputTCELL1:PCLK6

Bel PCLK_DCC0

machxo2 PCLK3_SOURCE_W bel PCLK_DCC0
PinDirectionWires
CEinputTCELL0:IMUX_D6
OUT_NoutputTCELL0:PCLK3
OUT_SoutputTCELL1:PCLK3

Bel PCLK_DCC1

machxo2 PCLK3_SOURCE_W bel PCLK_DCC1
PinDirectionWires
CEinputTCELL0:IMUX_D7
OUT_NoutputTCELL0:PCLK7
OUT_SoutputTCELL1:PCLK7

Bel wires

machxo2 PCLK3_SOURCE_W bel wires
WirePins
TCELL0:PCLK1PCLK_SOURCE_W.OUT_N1
TCELL0:PCLK2PCLK_SOURCE_W.OUT_N2
TCELL0:PCLK3PCLK_DCC0.OUT_N
TCELL0:PCLK5PCLK_SOURCE_W.OUT_N5
TCELL0:PCLK6PCLK_SOURCE_W.OUT_N6
TCELL0:PCLK7PCLK_DCC1.OUT_N
TCELL0:IMUX_D6PCLK_DCC0.CE
TCELL0:IMUX_D7PCLK_DCC1.CE
TCELL1:PCLK1PCLK_SOURCE_W.OUT_S1
TCELL1:PCLK2PCLK_SOURCE_W.OUT_S2
TCELL1:PCLK3PCLK_DCC0.OUT_S
TCELL1:PCLK5PCLK_SOURCE_W.OUT_S5
TCELL1:PCLK6PCLK_SOURCE_W.OUT_S6
TCELL1:PCLK7PCLK_DCC1.OUT_S

Tile HSDCLK_ROOT

Cells: 8

Bel HSDCLK_ROOT

machxo2 HSDCLK_ROOT bel HSDCLK_ROOT
PinDirectionWires
OUT_E0outputTCELL4:HSDCLK0
OUT_E1outputTCELL5:HSDCLK0
OUT_E2outputTCELL6:HSDCLK0
OUT_E3outputTCELL7:HSDCLK0
OUT_E4outputTCELL4:HSDCLK4
OUT_E5outputTCELL5:HSDCLK4
OUT_E6outputTCELL6:HSDCLK4
OUT_E7outputTCELL7:HSDCLK4
OUT_W0outputTCELL0:HSDCLK0
OUT_W1outputTCELL1:HSDCLK0
OUT_W2outputTCELL2:HSDCLK0
OUT_W3outputTCELL3:HSDCLK0
OUT_W4outputTCELL0:HSDCLK4
OUT_W5outputTCELL1:HSDCLK4
OUT_W6outputTCELL2:HSDCLK4
OUT_W7outputTCELL3:HSDCLK4

Bel HSDCLK_SPLITTER

Switchbox HSDCLK_SPLITTER

machxo2 HSDCLK_ROOT switchbox HSDCLK_SPLITTER
DestinationSourceKind
TCELL0_HSDCLK0TCELL4_HSDCLK0buffer
TCELL0_HSDCLK4TCELL4_HSDCLK4buffer
TCELL1_HSDCLK0TCELL5_HSDCLK0buffer
TCELL1_HSDCLK4TCELL5_HSDCLK4buffer
TCELL2_HSDCLK0TCELL6_HSDCLK0buffer
TCELL2_HSDCLK4TCELL6_HSDCLK4buffer
TCELL3_HSDCLK0TCELL7_HSDCLK0buffer
TCELL3_HSDCLK4TCELL7_HSDCLK4buffer
TCELL4_HSDCLK0TCELL0_HSDCLK0buffer
TCELL4_HSDCLK4TCELL0_HSDCLK4buffer
TCELL5_HSDCLK0TCELL1_HSDCLK0buffer
TCELL5_HSDCLK4TCELL1_HSDCLK4buffer
TCELL6_HSDCLK0TCELL2_HSDCLK0buffer
TCELL6_HSDCLK4TCELL2_HSDCLK4buffer
TCELL7_HSDCLK0TCELL3_HSDCLK0buffer
TCELL7_HSDCLK4TCELL3_HSDCLK4buffer

Bel wires

machxo2 HSDCLK_ROOT bel wires
WirePins
TCELL0:HSDCLK0HSDCLK_ROOT.OUT_W0
TCELL0:HSDCLK4HSDCLK_ROOT.OUT_W4
TCELL1:HSDCLK0HSDCLK_ROOT.OUT_W1
TCELL1:HSDCLK4HSDCLK_ROOT.OUT_W5
TCELL2:HSDCLK0HSDCLK_ROOT.OUT_W2
TCELL2:HSDCLK4HSDCLK_ROOT.OUT_W6
TCELL3:HSDCLK0HSDCLK_ROOT.OUT_W3
TCELL3:HSDCLK4HSDCLK_ROOT.OUT_W7
TCELL4:HSDCLK0HSDCLK_ROOT.OUT_E0
TCELL4:HSDCLK4HSDCLK_ROOT.OUT_E4
TCELL5:HSDCLK0HSDCLK_ROOT.OUT_E1
TCELL5:HSDCLK4HSDCLK_ROOT.OUT_E5
TCELL6:HSDCLK0HSDCLK_ROOT.OUT_E2
TCELL6:HSDCLK4HSDCLK_ROOT.OUT_E6
TCELL7:HSDCLK0HSDCLK_ROOT.OUT_E3
TCELL7:HSDCLK4HSDCLK_ROOT.OUT_E7

Tile SCLK0_SOURCE

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK0_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK0fixed buffer
SCLK4VSDCLK1fixed buffer

Tile SCLK0_SOURCE_E

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK0_SOURCE_E switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK0fixed buffer
SCLK1VSDCLK2fixed buffer
SCLK4VSDCLK1fixed buffer
SCLK5VSDCLK3fixed buffer

Tile SCLK0_SOURCE_W

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK0_SOURCE_W switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK0fixed buffer
SCLK2VSDCLK4fixed buffer
SCLK3VSDCLK6fixed buffer
SCLK4VSDCLK1fixed buffer
SCLK6VSDCLK5fixed buffer
SCLK7VSDCLK7fixed buffer

Tile SCLK1_SOURCE

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK1_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK1VSDCLK0fixed buffer
SCLK5VSDCLK1fixed buffer

Tile SCLK1_SOURCE_E

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK1_SOURCE_E switchbox SCLK_SOURCE
DestinationSourceKind
SCLK1VSDCLK0fixed buffer
SCLK2VSDCLK2fixed buffer
SCLK5VSDCLK1fixed buffer
SCLK6VSDCLK3fixed buffer

Tile SCLK1_SOURCE_W

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK1_SOURCE_W switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK6fixed buffer
SCLK1VSDCLK0fixed buffer
SCLK3VSDCLK4fixed buffer
SCLK4VSDCLK7fixed buffer
SCLK5VSDCLK1fixed buffer
SCLK7VSDCLK5fixed buffer

Tile SCLK2_SOURCE

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK2_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK2VSDCLK0fixed buffer
SCLK6VSDCLK1fixed buffer

Tile SCLK2_SOURCE_E

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK2_SOURCE_E switchbox SCLK_SOURCE
DestinationSourceKind
SCLK2VSDCLK0fixed buffer
SCLK3VSDCLK2fixed buffer
SCLK6VSDCLK1fixed buffer
SCLK7VSDCLK3fixed buffer

Tile SCLK2_SOURCE_W

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK2_SOURCE_W switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK4fixed buffer
SCLK1VSDCLK6fixed buffer
SCLK2VSDCLK0fixed buffer
SCLK4VSDCLK5fixed buffer
SCLK5VSDCLK7fixed buffer
SCLK6VSDCLK1fixed buffer

Tile SCLK3_SOURCE

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK3_SOURCE switchbox SCLK_SOURCE
DestinationSourceKind
SCLK3VSDCLK0fixed buffer
SCLK7VSDCLK1fixed buffer

Tile SCLK3_SOURCE_E

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK3_SOURCE_E switchbox SCLK_SOURCE
DestinationSourceKind
SCLK0VSDCLK2fixed buffer
SCLK3VSDCLK0fixed buffer
SCLK4VSDCLK3fixed buffer
SCLK7VSDCLK1fixed buffer

Tile SCLK3_SOURCE_W

Cells: 1

Bel SCLK_SOURCE

Switchbox SCLK_SOURCE

machxo2 SCLK3_SOURCE_W switchbox SCLK_SOURCE
DestinationSourceKind
SCLK1VSDCLK4fixed buffer
SCLK2VSDCLK6fixed buffer
SCLK3VSDCLK0fixed buffer
SCLK5VSDCLK5fixed buffer
SCLK6VSDCLK7fixed buffer
SCLK7VSDCLK1fixed buffer