Phase-Locked Loops
Tile PLL_SW
Cells: 6
Bel PLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL1:IMUX_CLK1 |
| CLKI | input | TCELL1:IMUX_CLK0 |
| CLKOP | output | TCELL0:OUT_Q2 |
| CLKOS | output | TCELL0:OUT_F2 |
| LOCK | output | TCELL1:OUT_OFX6 |
| RST | input | TCELL1:IMUX_LSR3 |
| SMIRDATA | output | TCELL1:OUT_OFX3 |
| TPFB | output | TCELL0:OUT_F4 |
| TPREF | output | TCELL0:OUT_Q4 |
Bel PLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL1:IMUX_CLK3 |
| CLKI | input | TCELL1:IMUX_CLK2 |
| CLKOP | output | TCELL0:OUT_Q7 |
| CLKOS | output | TCELL0:OUT_F7 |
| LOCK | output | TCELL1:OUT_OFX4 |
| RST | input | TCELL1:IMUX_LSR2 |
| SMIRDATA | output | TCELL1:OUT_OFX2 |
| TPFB | output | TCELL0:OUT_Q5 |
| TPREF | output | TCELL0:OUT_F5 |
Bel PLL_SMI
| Pin | Direction | Wires |
|---|---|---|
| SMIADDR0 | input | TCELL0:IMUX_B2 |
| SMIADDR1 | input | TCELL0:IMUX_A2 |
| SMIADDR2 | input | TCELL0:IMUX_A1 |
| SMIADDR3 | input | TCELL0:IMUX_B1 |
| SMIADDR4 | input | TCELL0:IMUX_C1 |
| SMIADDR5 | input | TCELL0:IMUX_D1 |
| SMIADDR6 | input | TCELL0:IMUX_D0 |
| SMIADDR7 | input | TCELL0:IMUX_C0 |
| SMIADDR8 | input | TCELL0:IMUX_B0 |
| SMIADDR9 | input | TCELL0:IMUX_A0 |
| SMICLK | input | TCELL0:IMUX_C2 |
| SMIRD | input | TCELL0:IMUX_C3 |
| SMIRSTN | input | TCELL0:IMUX_LSR0 |
| SMIWDATA | input | TCELL0:IMUX_D3 |
| SMIWR | input | TCELL0:IMUX_D2 |
Bel DLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL0:IMUX_CLK3 |
| CLKI | input | TCELL0:IMUX_CLK2 |
| CLKOP | output | TCELL1:OUT_F6 |
| CLKOS | output | TCELL1:OUT_Q6 |
| DTCCST0 | input | TCELL0:IMUX_A6 |
| DTCCST1 | input | TCELL0:IMUX_B6 |
| LOCK | output | TCELL1:OUT_Q3 |
| RST | input | TCELL1:IMUX_LSR0 |
| SMIRDATA | output | TCELL1:OUT_Q5 |
| UDDCNTL | input | TCELL0:IMUX_A5 |
Bel DLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL2:IMUX_CLK2 |
| CLKI | input | TCELL3:IMUX_CLK2 |
| CLKOP | output | TCELL1:OUT_OFX7 |
| CLKOS | output | TCELL1:OUT_F7 |
| DTCCST0 | input | TCELL0:IMUX_C5 |
| DTCCST1 | input | TCELL0:IMUX_D5 |
| LOCK | output | TCELL1:OUT_Q2 |
| RST | input | TCELL0:IMUX_LSR3 |
| SMIRDATA | output | TCELL1:OUT_Q4 |
| UDDCNTL | input | TCELL0:IMUX_B5 |
Bel DLL2
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL0:IMUX_CLK0 |
| CLKI | input | TCELL0:IMUX_CLK1 |
| CLKOP | output | TCELL0:OUT_F1 |
| CLKOS | output | TCELL0:OUT_Q1 |
| DTCCST0 | input | TCELL0:IMUX_B4 |
| DTCCST1 | input | TCELL0:IMUX_A4 |
| LOCK | output | TCELL1:OUT_F3 |
| RST | input | TCELL0:IMUX_LSR2 |
| SMIRDATA | output | TCELL1:OUT_F5 |
| UDDCNTL | input | TCELL0:IMUX_D4 |
Bel DLL3
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL5:IMUX_CLK1 |
| CLKI | input | TCELL4:IMUX_CLK1 |
| CLKOP | output | TCELL0:OUT_F0 |
| CLKOS | output | TCELL0:OUT_OFX0 |
| DTCCST0 | input | TCELL0:IMUX_B3 |
| DTCCST1 | input | TCELL0:IMUX_A3 |
| LOCK | output | TCELL1:OUT_F2 |
| RST | input | TCELL0:IMUX_LSR1 |
| SMIRDATA | output | TCELL1:OUT_F4 |
| UDDCNTL | input | TCELL0:IMUX_C4 |
Bel DLL_DCNTL0
| Pin | Direction | Wires |
|---|---|---|
| DCNTL_IN0 | input | TCELL1:IMUX_D0 |
| DCNTL_IN1 | input | TCELL1:IMUX_D1 |
| DCNTL_IN2 | input | TCELL1:IMUX_C1 |
| DCNTL_IN3 | input | TCELL1:IMUX_B1 |
| DCNTL_IN4 | input | TCELL1:IMUX_A1 |
| DCNTL_IN5 | input | TCELL1:IMUX_A2 |
| DCNTL_IN6 | input | TCELL1:IMUX_D2 |
| DCNTL_IN7 | input | TCELL1:IMUX_C2 |
| DCNTL_IN8 | input | TCELL1:IMUX_B2 |
| DCNTL_OUT0 | output | TCELL0:OUT_F6 |
| DCNTL_OUT1 | output | TCELL0:OUT_Q6 |
| DCNTL_OUT2 | output | TCELL0:OUT_OFX7 |
| DCNTL_OUT3 | output | TCELL1:OUT_OFX0 |
| DCNTL_OUT4 | output | TCELL1:OUT_F0 |
| DCNTL_OUT5 | output | TCELL1:OUT_Q0 |
| DCNTL_OUT6 | output | TCELL1:OUT_Q1 |
| DCNTL_OUT7 | output | TCELL1:OUT_F1 |
| DCNTL_OUT8 | output | TCELL1:OUT_OFX1 |
Bel DLL_DCNTL1
| Pin | Direction | Wires |
|---|---|---|
| DCNTL_IN0 | input | TCELL0:IMUX_C6 |
| DCNTL_IN1 | input | TCELL0:IMUX_D6 |
| DCNTL_IN2 | input | TCELL0:IMUX_D7 |
| DCNTL_IN3 | input | TCELL0:IMUX_C7 |
| DCNTL_IN4 | input | TCELL0:IMUX_B7 |
| DCNTL_IN5 | input | TCELL0:IMUX_A7 |
| DCNTL_IN6 | input | TCELL1:IMUX_C0 |
| DCNTL_IN7 | input | TCELL1:IMUX_B0 |
| DCNTL_IN8 | input | TCELL1:IMUX_A0 |
| DCNTL_OUT0 | output | TCELL0:OUT_Q0 |
| DCNTL_OUT1 | output | TCELL0:OUT_OFX1 |
| DCNTL_OUT2 | output | TCELL0:OUT_OFX2 |
| DCNTL_OUT3 | output | TCELL0:OUT_Q3 |
| DCNTL_OUT4 | output | TCELL0:OUT_F3 |
| DCNTL_OUT5 | output | TCELL0:OUT_OFX3 |
| DCNTL_OUT6 | output | TCELL0:OUT_OFX4 |
| DCNTL_OUT7 | output | TCELL0:OUT_OFX5 |
| DCNTL_OUT8 | output | TCELL0:OUT_OFX6 |
Bel PROMON
| Pin | Direction | Wires |
|---|---|---|
| PROCHK | input | TCELL1:IMUX_B4 |
| PROMON | output | TCELL1:OUT_Q7 |
Bel RNET
| Pin | Direction | Wires |
|---|---|---|
| RNETI0 | input | TCELL1:IMUX_D5 |
| RNETI1 | input | TCELL1:IMUX_D4 |
| RNETI2 | input | TCELL1:IMUX_C4 |
| RNETI3 | input | TCELL1:IMUX_A5 |
| RNETI4 | input | TCELL1:IMUX_B5 |
| RNETI5 | input | TCELL1:IMUX_C5 |
| RNETO0 | output | TCELL4:OUT_IO7 |
| RNETO1 | output | TCELL4:OUT_IO5 |
| RNETO2 | output | TCELL3:OUT_IO1 |
| RNETO3 | output | TCELL2:OUT_IO7 |
| RNETO4 | output | TCELL2:OUT_IO1 |
| RNETO5 | output | TCELL1:OUT_OFX5 |
| RNETUPD | input | TCELL1:IMUX_CE3 |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX_A0 | PLL_SMI.SMIADDR9 |
| TCELL0:IMUX_A1 | PLL_SMI.SMIADDR2 |
| TCELL0:IMUX_A2 | PLL_SMI.SMIADDR1 |
| TCELL0:IMUX_A3 | DLL3.DTCCST1 |
| TCELL0:IMUX_A4 | DLL2.DTCCST1 |
| TCELL0:IMUX_A5 | DLL0.UDDCNTL |
| TCELL0:IMUX_A6 | DLL0.DTCCST0 |
| TCELL0:IMUX_A7 | DLL_DCNTL1.DCNTL_IN5 |
| TCELL0:IMUX_B0 | PLL_SMI.SMIADDR8 |
| TCELL0:IMUX_B1 | PLL_SMI.SMIADDR3 |
| TCELL0:IMUX_B2 | PLL_SMI.SMIADDR0 |
| TCELL0:IMUX_B3 | DLL3.DTCCST0 |
| TCELL0:IMUX_B4 | DLL2.DTCCST0 |
| TCELL0:IMUX_B5 | DLL1.UDDCNTL |
| TCELL0:IMUX_B6 | DLL0.DTCCST1 |
| TCELL0:IMUX_B7 | DLL_DCNTL1.DCNTL_IN4 |
| TCELL0:IMUX_C0 | PLL_SMI.SMIADDR7 |
| TCELL0:IMUX_C1 | PLL_SMI.SMIADDR4 |
| TCELL0:IMUX_C2 | PLL_SMI.SMICLK |
| TCELL0:IMUX_C3 | PLL_SMI.SMIRD |
| TCELL0:IMUX_C4 | DLL3.UDDCNTL |
| TCELL0:IMUX_C5 | DLL1.DTCCST0 |
| TCELL0:IMUX_C6 | DLL_DCNTL1.DCNTL_IN0 |
| TCELL0:IMUX_C7 | DLL_DCNTL1.DCNTL_IN3 |
| TCELL0:IMUX_D0 | PLL_SMI.SMIADDR6 |
| TCELL0:IMUX_D1 | PLL_SMI.SMIADDR5 |
| TCELL0:IMUX_D2 | PLL_SMI.SMIWR |
| TCELL0:IMUX_D3 | PLL_SMI.SMIWDATA |
| TCELL0:IMUX_D4 | DLL2.UDDCNTL |
| TCELL0:IMUX_D5 | DLL1.DTCCST1 |
| TCELL0:IMUX_D6 | DLL_DCNTL1.DCNTL_IN1 |
| TCELL0:IMUX_D7 | DLL_DCNTL1.DCNTL_IN2 |
| TCELL0:IMUX_CLK0 | DLL2.CLKFB |
| TCELL0:IMUX_CLK1 | DLL2.CLKI |
| TCELL0:IMUX_CLK2 | DLL0.CLKI |
| TCELL0:IMUX_CLK3 | DLL0.CLKFB |
| TCELL0:IMUX_LSR0 | PLL_SMI.SMIRSTN |
| TCELL0:IMUX_LSR1 | DLL3.RST |
| TCELL0:IMUX_LSR2 | DLL2.RST |
| TCELL0:IMUX_LSR3 | DLL1.RST |
| TCELL0:OUT_F0 | DLL3.CLKOP |
| TCELL0:OUT_F1 | DLL2.CLKOP |
| TCELL0:OUT_F2 | PLL0.CLKOS |
| TCELL0:OUT_F3 | DLL_DCNTL1.DCNTL_OUT4 |
| TCELL0:OUT_F4 | PLL0.TPFB |
| TCELL0:OUT_F5 | PLL1.TPREF |
| TCELL0:OUT_F6 | DLL_DCNTL0.DCNTL_OUT0 |
| TCELL0:OUT_F7 | PLL1.CLKOS |
| TCELL0:OUT_Q0 | DLL_DCNTL1.DCNTL_OUT0 |
| TCELL0:OUT_Q1 | DLL2.CLKOS |
| TCELL0:OUT_Q2 | PLL0.CLKOP |
| TCELL0:OUT_Q3 | DLL_DCNTL1.DCNTL_OUT3 |
| TCELL0:OUT_Q4 | PLL0.TPREF |
| TCELL0:OUT_Q5 | PLL1.TPFB |
| TCELL0:OUT_Q6 | DLL_DCNTL0.DCNTL_OUT1 |
| TCELL0:OUT_Q7 | PLL1.CLKOP |
| TCELL0:OUT_OFX0 | DLL3.CLKOS |
| TCELL0:OUT_OFX1 | DLL_DCNTL1.DCNTL_OUT1 |
| TCELL0:OUT_OFX2 | DLL_DCNTL1.DCNTL_OUT2 |
| TCELL0:OUT_OFX3 | DLL_DCNTL1.DCNTL_OUT5 |
| TCELL0:OUT_OFX4 | DLL_DCNTL1.DCNTL_OUT6 |
| TCELL0:OUT_OFX5 | DLL_DCNTL1.DCNTL_OUT7 |
| TCELL0:OUT_OFX6 | DLL_DCNTL1.DCNTL_OUT8 |
| TCELL0:OUT_OFX7 | DLL_DCNTL0.DCNTL_OUT2 |
| TCELL1:IMUX_A0 | DLL_DCNTL1.DCNTL_IN8 |
| TCELL1:IMUX_A1 | DLL_DCNTL0.DCNTL_IN4 |
| TCELL1:IMUX_A2 | DLL_DCNTL0.DCNTL_IN5 |
| TCELL1:IMUX_A5 | RNET.RNETI3 |
| TCELL1:IMUX_B0 | DLL_DCNTL1.DCNTL_IN7 |
| TCELL1:IMUX_B1 | DLL_DCNTL0.DCNTL_IN3 |
| TCELL1:IMUX_B2 | DLL_DCNTL0.DCNTL_IN8 |
| TCELL1:IMUX_B4 | PROMON.PROCHK |
| TCELL1:IMUX_B5 | RNET.RNETI4 |
| TCELL1:IMUX_C0 | DLL_DCNTL1.DCNTL_IN6 |
| TCELL1:IMUX_C1 | DLL_DCNTL0.DCNTL_IN2 |
| TCELL1:IMUX_C2 | DLL_DCNTL0.DCNTL_IN7 |
| TCELL1:IMUX_C4 | RNET.RNETI2 |
| TCELL1:IMUX_C5 | RNET.RNETI5 |
| TCELL1:IMUX_D0 | DLL_DCNTL0.DCNTL_IN0 |
| TCELL1:IMUX_D1 | DLL_DCNTL0.DCNTL_IN1 |
| TCELL1:IMUX_D2 | DLL_DCNTL0.DCNTL_IN6 |
| TCELL1:IMUX_D4 | RNET.RNETI1 |
| TCELL1:IMUX_D5 | RNET.RNETI0 |
| TCELL1:IMUX_CLK0 | PLL0.CLKI |
| TCELL1:IMUX_CLK1 | PLL0.CLKFB |
| TCELL1:IMUX_CLK2 | PLL1.CLKI |
| TCELL1:IMUX_CLK3 | PLL1.CLKFB |
| TCELL1:IMUX_LSR0 | DLL0.RST |
| TCELL1:IMUX_LSR2 | PLL1.RST |
| TCELL1:IMUX_LSR3 | PLL0.RST |
| TCELL1:IMUX_CE3 | RNET.RNETUPD |
| TCELL1:OUT_F0 | DLL_DCNTL0.DCNTL_OUT4 |
| TCELL1:OUT_F1 | DLL_DCNTL0.DCNTL_OUT7 |
| TCELL1:OUT_F2 | DLL3.LOCK |
| TCELL1:OUT_F3 | DLL2.LOCK |
| TCELL1:OUT_F4 | DLL3.SMIRDATA |
| TCELL1:OUT_F5 | DLL2.SMIRDATA |
| TCELL1:OUT_F6 | DLL0.CLKOP |
| TCELL1:OUT_F7 | DLL1.CLKOS |
| TCELL1:OUT_Q0 | DLL_DCNTL0.DCNTL_OUT5 |
| TCELL1:OUT_Q1 | DLL_DCNTL0.DCNTL_OUT6 |
| TCELL1:OUT_Q2 | DLL1.LOCK |
| TCELL1:OUT_Q3 | DLL0.LOCK |
| TCELL1:OUT_Q4 | DLL1.SMIRDATA |
| TCELL1:OUT_Q5 | DLL0.SMIRDATA |
| TCELL1:OUT_Q6 | DLL0.CLKOS |
| TCELL1:OUT_Q7 | PROMON.PROMON |
| TCELL1:OUT_OFX0 | DLL_DCNTL0.DCNTL_OUT3 |
| TCELL1:OUT_OFX1 | DLL_DCNTL0.DCNTL_OUT8 |
| TCELL1:OUT_OFX2 | PLL1.SMIRDATA |
| TCELL1:OUT_OFX3 | PLL0.SMIRDATA |
| TCELL1:OUT_OFX4 | PLL1.LOCK |
| TCELL1:OUT_OFX5 | RNET.RNETO5 |
| TCELL1:OUT_OFX6 | PLL0.LOCK |
| TCELL1:OUT_OFX7 | DLL1.CLKOP |
| TCELL2:IMUX_CLK2 | DLL1.CLKFB |
| TCELL2:OUT_IO1 | RNET.RNETO4 |
| TCELL2:OUT_IO7 | RNET.RNETO3 |
| TCELL3:IMUX_CLK2 | DLL1.CLKI |
| TCELL3:OUT_IO1 | RNET.RNETO2 |
| TCELL4:IMUX_CLK1 | DLL3.CLKI |
| TCELL4:OUT_IO5 | RNET.RNETO1 |
| TCELL4:OUT_IO7 | RNET.RNETO0 |
| TCELL5:IMUX_CLK1 | DLL3.CLKFB |
Tile PLL_SE
Cells: 6
Bel PLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL1:IMUX_CLK2 |
| CLKI | input | TCELL1:IMUX_CLK3 |
| CLKOP | output | TCELL0:OUT_Q5 |
| CLKOS | output | TCELL0:OUT_F5 |
| LOCK | output | TCELL1:OUT_OFX1 |
| RST | input | TCELL1:IMUX_LSR0 |
| SMIRDATA | output | TCELL1:OUT_OFX4 |
| TPFB | output | TCELL0:OUT_F3 |
| TPREF | output | TCELL0:OUT_Q3 |
Bel PLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL1:IMUX_CLK0 |
| CLKI | input | TCELL1:IMUX_CLK1 |
| CLKOP | output | TCELL0:OUT_Q0 |
| CLKOS | output | TCELL0:OUT_F0 |
| LOCK | output | TCELL1:OUT_OFX3 |
| RST | input | TCELL1:IMUX_LSR1 |
| SMIRDATA | output | TCELL1:OUT_OFX5 |
| TPFB | output | TCELL0:OUT_Q2 |
| TPREF | output | TCELL0:OUT_F2 |
Bel PLL_SMI
| Pin | Direction | Wires |
|---|---|---|
| SMIADDR0 | input | TCELL0:IMUX_B5 |
| SMIADDR1 | input | TCELL0:IMUX_A5 |
| SMIADDR2 | input | TCELL0:IMUX_A6 |
| SMIADDR3 | input | TCELL0:IMUX_B6 |
| SMIADDR4 | input | TCELL0:IMUX_C6 |
| SMIADDR5 | input | TCELL0:IMUX_D6 |
| SMIADDR6 | input | TCELL0:IMUX_D7 |
| SMIADDR7 | input | TCELL0:IMUX_C7 |
| SMIADDR8 | input | TCELL0:IMUX_B7 |
| SMIADDR9 | input | TCELL0:IMUX_A7 |
| SMICLK | input | TCELL0:IMUX_C5 |
| SMIRD | input | TCELL0:IMUX_C4 |
| SMIRSTN | input | TCELL0:IMUX_LSR3 |
| SMIWDATA | input | TCELL0:IMUX_D4 |
| SMIWR | input | TCELL0:IMUX_D5 |
Bel DLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL0:IMUX_CLK0 |
| CLKI | input | TCELL0:IMUX_CLK1 |
| CLKOP | output | TCELL1:OUT_F1 |
| CLKOS | output | TCELL1:OUT_Q1 |
| DTCCST0 | input | TCELL0:IMUX_A1 |
| DTCCST1 | input | TCELL0:IMUX_B1 |
| LOCK | output | TCELL1:OUT_Q4 |
| RST | input | TCELL1:IMUX_LSR3 |
| SMIRDATA | output | TCELL1:OUT_Q2 |
| UDDCNTL | input | TCELL0:IMUX_A2 |
Bel DLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL2:IMUX_CLK2 |
| CLKI | input | TCELL3:IMUX_CLK2 |
| CLKOP | output | TCELL1:OUT_OFX0 |
| CLKOS | output | TCELL1:OUT_F0 |
| DTCCST0 | input | TCELL0:IMUX_C2 |
| DTCCST1 | input | TCELL0:IMUX_D2 |
| LOCK | output | TCELL1:OUT_Q5 |
| RST | input | TCELL0:IMUX_LSR0 |
| SMIRDATA | output | TCELL1:OUT_Q3 |
| UDDCNTL | input | TCELL0:IMUX_B2 |
Bel DLL2
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL0:IMUX_CLK3 |
| CLKI | input | TCELL0:IMUX_CLK2 |
| CLKOP | output | TCELL0:OUT_F6 |
| CLKOS | output | TCELL0:OUT_Q6 |
| DTCCST0 | input | TCELL0:IMUX_B3 |
| DTCCST1 | input | TCELL0:IMUX_A3 |
| LOCK | output | TCELL1:OUT_F4 |
| RST | input | TCELL0:IMUX_LSR1 |
| SMIRDATA | output | TCELL1:OUT_F2 |
| UDDCNTL | input | TCELL0:IMUX_D3 |
Bel DLL3
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL5:IMUX_CLK2 |
| CLKI | input | TCELL4:IMUX_CLK2 |
| CLKOP | output | TCELL0:OUT_F7 |
| CLKOS | output | TCELL0:OUT_OFX7 |
| DTCCST0 | input | TCELL0:IMUX_B4 |
| DTCCST1 | input | TCELL0:IMUX_A4 |
| LOCK | output | TCELL1:OUT_F5 |
| RST | input | TCELL0:IMUX_LSR2 |
| SMIRDATA | output | TCELL1:OUT_F3 |
| UDDCNTL | input | TCELL0:IMUX_C3 |
Bel DLL_DCNTL0
| Pin | Direction | Wires |
|---|---|---|
| DCNTL_IN0 | input | TCELL1:IMUX_D7 |
| DCNTL_IN1 | input | TCELL1:IMUX_D6 |
| DCNTL_IN2 | input | TCELL1:IMUX_C6 |
| DCNTL_IN3 | input | TCELL1:IMUX_B6 |
| DCNTL_IN4 | input | TCELL1:IMUX_A6 |
| DCNTL_IN5 | input | TCELL1:IMUX_A5 |
| DCNTL_IN6 | input | TCELL1:IMUX_D5 |
| DCNTL_IN7 | input | TCELL1:IMUX_C5 |
| DCNTL_IN8 | input | TCELL1:IMUX_B5 |
| DCNTL_OUT0 | output | TCELL0:OUT_F1 |
| DCNTL_OUT1 | output | TCELL0:OUT_Q1 |
| DCNTL_OUT2 | output | TCELL0:OUT_OFX0 |
| DCNTL_OUT3 | output | TCELL1:OUT_OFX7 |
| DCNTL_OUT4 | output | TCELL1:OUT_F7 |
| DCNTL_OUT5 | output | TCELL1:OUT_Q7 |
| DCNTL_OUT6 | output | TCELL1:OUT_Q6 |
| DCNTL_OUT7 | output | TCELL1:OUT_F6 |
| DCNTL_OUT8 | output | TCELL1:OUT_OFX6 |
Bel DLL_DCNTL1
| Pin | Direction | Wires |
|---|---|---|
| DCNTL_IN0 | input | TCELL0:IMUX_C1 |
| DCNTL_IN1 | input | TCELL0:IMUX_D1 |
| DCNTL_IN2 | input | TCELL0:IMUX_D0 |
| DCNTL_IN3 | input | TCELL0:IMUX_C0 |
| DCNTL_IN4 | input | TCELL0:IMUX_B0 |
| DCNTL_IN5 | input | TCELL0:IMUX_A0 |
| DCNTL_IN6 | input | TCELL1:IMUX_C7 |
| DCNTL_IN7 | input | TCELL1:IMUX_B7 |
| DCNTL_IN8 | input | TCELL1:IMUX_A7 |
| DCNTL_OUT0 | output | TCELL0:OUT_Q7 |
| DCNTL_OUT1 | output | TCELL0:OUT_OFX6 |
| DCNTL_OUT2 | output | TCELL0:OUT_OFX5 |
| DCNTL_OUT3 | output | TCELL0:OUT_Q4 |
| DCNTL_OUT4 | output | TCELL0:OUT_F4 |
| DCNTL_OUT5 | output | TCELL0:OUT_OFX4 |
| DCNTL_OUT6 | output | TCELL0:OUT_OFX3 |
| DCNTL_OUT7 | output | TCELL0:OUT_OFX2 |
| DCNTL_OUT8 | output | TCELL0:OUT_OFX1 |
Bel PROMON
| Pin | Direction | Wires |
|---|---|---|
| PROCHK | input | TCELL1:IMUX_B3 |
| PROMON | output | TCELL1:OUT_Q0 |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX_A0 | DLL_DCNTL1.DCNTL_IN5 |
| TCELL0:IMUX_A1 | DLL0.DTCCST0 |
| TCELL0:IMUX_A2 | DLL0.UDDCNTL |
| TCELL0:IMUX_A3 | DLL2.DTCCST1 |
| TCELL0:IMUX_A4 | DLL3.DTCCST1 |
| TCELL0:IMUX_A5 | PLL_SMI.SMIADDR1 |
| TCELL0:IMUX_A6 | PLL_SMI.SMIADDR2 |
| TCELL0:IMUX_A7 | PLL_SMI.SMIADDR9 |
| TCELL0:IMUX_B0 | DLL_DCNTL1.DCNTL_IN4 |
| TCELL0:IMUX_B1 | DLL0.DTCCST1 |
| TCELL0:IMUX_B2 | DLL1.UDDCNTL |
| TCELL0:IMUX_B3 | DLL2.DTCCST0 |
| TCELL0:IMUX_B4 | DLL3.DTCCST0 |
| TCELL0:IMUX_B5 | PLL_SMI.SMIADDR0 |
| TCELL0:IMUX_B6 | PLL_SMI.SMIADDR3 |
| TCELL0:IMUX_B7 | PLL_SMI.SMIADDR8 |
| TCELL0:IMUX_C0 | DLL_DCNTL1.DCNTL_IN3 |
| TCELL0:IMUX_C1 | DLL_DCNTL1.DCNTL_IN0 |
| TCELL0:IMUX_C2 | DLL1.DTCCST0 |
| TCELL0:IMUX_C3 | DLL3.UDDCNTL |
| TCELL0:IMUX_C4 | PLL_SMI.SMIRD |
| TCELL0:IMUX_C5 | PLL_SMI.SMICLK |
| TCELL0:IMUX_C6 | PLL_SMI.SMIADDR4 |
| TCELL0:IMUX_C7 | PLL_SMI.SMIADDR7 |
| TCELL0:IMUX_D0 | DLL_DCNTL1.DCNTL_IN2 |
| TCELL0:IMUX_D1 | DLL_DCNTL1.DCNTL_IN1 |
| TCELL0:IMUX_D2 | DLL1.DTCCST1 |
| TCELL0:IMUX_D3 | DLL2.UDDCNTL |
| TCELL0:IMUX_D4 | PLL_SMI.SMIWDATA |
| TCELL0:IMUX_D5 | PLL_SMI.SMIWR |
| TCELL0:IMUX_D6 | PLL_SMI.SMIADDR5 |
| TCELL0:IMUX_D7 | PLL_SMI.SMIADDR6 |
| TCELL0:IMUX_CLK0 | DLL0.CLKFB |
| TCELL0:IMUX_CLK1 | DLL0.CLKI |
| TCELL0:IMUX_CLK2 | DLL2.CLKI |
| TCELL0:IMUX_CLK3 | DLL2.CLKFB |
| TCELL0:IMUX_LSR0 | DLL1.RST |
| TCELL0:IMUX_LSR1 | DLL2.RST |
| TCELL0:IMUX_LSR2 | DLL3.RST |
| TCELL0:IMUX_LSR3 | PLL_SMI.SMIRSTN |
| TCELL0:OUT_F0 | PLL1.CLKOS |
| TCELL0:OUT_F1 | DLL_DCNTL0.DCNTL_OUT0 |
| TCELL0:OUT_F2 | PLL1.TPREF |
| TCELL0:OUT_F3 | PLL0.TPFB |
| TCELL0:OUT_F4 | DLL_DCNTL1.DCNTL_OUT4 |
| TCELL0:OUT_F5 | PLL0.CLKOS |
| TCELL0:OUT_F6 | DLL2.CLKOP |
| TCELL0:OUT_F7 | DLL3.CLKOP |
| TCELL0:OUT_Q0 | PLL1.CLKOP |
| TCELL0:OUT_Q1 | DLL_DCNTL0.DCNTL_OUT1 |
| TCELL0:OUT_Q2 | PLL1.TPFB |
| TCELL0:OUT_Q3 | PLL0.TPREF |
| TCELL0:OUT_Q4 | DLL_DCNTL1.DCNTL_OUT3 |
| TCELL0:OUT_Q5 | PLL0.CLKOP |
| TCELL0:OUT_Q6 | DLL2.CLKOS |
| TCELL0:OUT_Q7 | DLL_DCNTL1.DCNTL_OUT0 |
| TCELL0:OUT_OFX0 | DLL_DCNTL0.DCNTL_OUT2 |
| TCELL0:OUT_OFX1 | DLL_DCNTL1.DCNTL_OUT8 |
| TCELL0:OUT_OFX2 | DLL_DCNTL1.DCNTL_OUT7 |
| TCELL0:OUT_OFX3 | DLL_DCNTL1.DCNTL_OUT6 |
| TCELL0:OUT_OFX4 | DLL_DCNTL1.DCNTL_OUT5 |
| TCELL0:OUT_OFX5 | DLL_DCNTL1.DCNTL_OUT2 |
| TCELL0:OUT_OFX6 | DLL_DCNTL1.DCNTL_OUT1 |
| TCELL0:OUT_OFX7 | DLL3.CLKOS |
| TCELL1:IMUX_A5 | DLL_DCNTL0.DCNTL_IN5 |
| TCELL1:IMUX_A6 | DLL_DCNTL0.DCNTL_IN4 |
| TCELL1:IMUX_A7 | DLL_DCNTL1.DCNTL_IN8 |
| TCELL1:IMUX_B3 | PROMON.PROCHK |
| TCELL1:IMUX_B5 | DLL_DCNTL0.DCNTL_IN8 |
| TCELL1:IMUX_B6 | DLL_DCNTL0.DCNTL_IN3 |
| TCELL1:IMUX_B7 | DLL_DCNTL1.DCNTL_IN7 |
| TCELL1:IMUX_C5 | DLL_DCNTL0.DCNTL_IN7 |
| TCELL1:IMUX_C6 | DLL_DCNTL0.DCNTL_IN2 |
| TCELL1:IMUX_C7 | DLL_DCNTL1.DCNTL_IN6 |
| TCELL1:IMUX_D5 | DLL_DCNTL0.DCNTL_IN6 |
| TCELL1:IMUX_D6 | DLL_DCNTL0.DCNTL_IN1 |
| TCELL1:IMUX_D7 | DLL_DCNTL0.DCNTL_IN0 |
| TCELL1:IMUX_CLK0 | PLL1.CLKFB |
| TCELL1:IMUX_CLK1 | PLL1.CLKI |
| TCELL1:IMUX_CLK2 | PLL0.CLKFB |
| TCELL1:IMUX_CLK3 | PLL0.CLKI |
| TCELL1:IMUX_LSR0 | PLL0.RST |
| TCELL1:IMUX_LSR1 | PLL1.RST |
| TCELL1:IMUX_LSR3 | DLL0.RST |
| TCELL1:OUT_F0 | DLL1.CLKOS |
| TCELL1:OUT_F1 | DLL0.CLKOP |
| TCELL1:OUT_F2 | DLL2.SMIRDATA |
| TCELL1:OUT_F3 | DLL3.SMIRDATA |
| TCELL1:OUT_F4 | DLL2.LOCK |
| TCELL1:OUT_F5 | DLL3.LOCK |
| TCELL1:OUT_F6 | DLL_DCNTL0.DCNTL_OUT7 |
| TCELL1:OUT_F7 | DLL_DCNTL0.DCNTL_OUT4 |
| TCELL1:OUT_Q0 | PROMON.PROMON |
| TCELL1:OUT_Q1 | DLL0.CLKOS |
| TCELL1:OUT_Q2 | DLL0.SMIRDATA |
| TCELL1:OUT_Q3 | DLL1.SMIRDATA |
| TCELL1:OUT_Q4 | DLL0.LOCK |
| TCELL1:OUT_Q5 | DLL1.LOCK |
| TCELL1:OUT_Q6 | DLL_DCNTL0.DCNTL_OUT6 |
| TCELL1:OUT_Q7 | DLL_DCNTL0.DCNTL_OUT5 |
| TCELL1:OUT_OFX0 | DLL1.CLKOP |
| TCELL1:OUT_OFX1 | PLL0.LOCK |
| TCELL1:OUT_OFX3 | PLL1.LOCK |
| TCELL1:OUT_OFX4 | PLL0.SMIRDATA |
| TCELL1:OUT_OFX5 | PLL1.SMIRDATA |
| TCELL1:OUT_OFX6 | DLL_DCNTL0.DCNTL_OUT8 |
| TCELL1:OUT_OFX7 | DLL_DCNTL0.DCNTL_OUT3 |
| TCELL2:IMUX_CLK2 | DLL1.CLKFB |
| TCELL3:IMUX_CLK2 | DLL1.CLKI |
| TCELL4:IMUX_CLK2 | DLL3.CLKI |
| TCELL5:IMUX_CLK2 | DLL3.CLKFB |
Tile PLL_NW
Cells: 3
Bel SERDES_CORNER
| Pin | Direction | Wires |
|---|---|---|
| CIN_0 | input | TCELL2:IO_W0_1 |
| CIN_1 | input | TCELL2:IO_W1_1 |
| CIN_10 | input | TCELL2:IO_W10_1 |
| CIN_11 | input | TCELL2:IO_W11_1 |
| CIN_12 | input | TCELL2:IO_W12_1 |
| CIN_2 | input | TCELL2:IO_W2_1 |
| CIN_3 | input | TCELL2:IO_W3_1 |
| CIN_4 | input | TCELL2:IO_W4_1 |
| CIN_5 | input | TCELL2:IO_W5_1 |
| CIN_6 | input | TCELL2:IO_W6_1 |
| CIN_7 | input | TCELL2:IO_W7_1 |
| CIN_8 | input | TCELL2:IO_W8_1 |
| CIN_9 | input | TCELL2:IO_W9_1 |
| COUT_0 | output | TCELL2:IO_E0_2 |
| COUT_1 | output | TCELL2:IO_E1_2 |
| COUT_10 | output | TCELL2:IO_E13_2 |
| COUT_11 | output | TCELL2:IO_E14_2 |
| COUT_12 | output | TCELL2:IO_E15_2 |
| COUT_13 | output | TCELL2:IO_E16_2 |
| COUT_14 | output | TCELL2:IO_E17_2 |
| COUT_15 | output | TCELL2:IO_E18_2 |
| COUT_16 | output | TCELL2:IO_E19_2 |
| COUT_17 | output | TCELL2:IO_E20_2 |
| COUT_18 | output | TCELL2:IO_E21_2 |
| COUT_19 | output | TCELL2:IO_E22_2 |
| COUT_2 | output | TCELL2:IO_E2_2 |
| COUT_20 | output | TCELL2:IO_E23_2 |
| COUT_21 | output | TCELL2:IO_E24_2 |
| COUT_3 | output | TCELL2:IO_E3_2 |
| COUT_4 | output | TCELL2:IO_E4_2 |
| COUT_5 | output | TCELL2:IO_E5_2 |
| COUT_6 | output | TCELL2:IO_E9_2 |
| COUT_7 | output | TCELL2:IO_E10_2 |
| COUT_8 | output | TCELL2:IO_E11_2 |
| COUT_9 | output | TCELL2:IO_E12_2 |
| SERDES0_BS4PAD_0 | output | TCELL2:IO_E25_2 |
| SERDES0_BS4PAD_1 | output | TCELL2:IO_E26_2 |
| SERDES0_BS4PAD_2 | output | TCELL2:IO_E27_2 |
| SERDES0_BS4PAD_3 | output | TCELL2:IO_E28_2 |
| SERDES1_BS4PAD_0 | output | TCELL2:IO_E29_2 |
| SERDES1_BS4PAD_1 | output | TCELL2:IO_E30_2 |
| SERDES1_BS4PAD_2 | output | TCELL2:IO_E31_2 |
| SERDES1_BS4PAD_3 | output | TCELL2:IO_E0_3 |
| SERDES2_BS4PAD_0 | output | TCELL2:IO_E1_3 |
| SERDES2_BS4PAD_1 | output | TCELL2:IO_E2_3 |
| SERDES2_BS4PAD_2 | output | TCELL2:IO_E3_3 |
| SERDES2_BS4PAD_3 | output | TCELL2:IO_E4_3 |
| SERDES3_BS4PAD_0 | output | TCELL2:IO_E5_3 |
| SERDES3_BS4PAD_1 | output | TCELL2:IO_E9_3 |
| SERDES3_BS4PAD_2 | output | TCELL2:IO_E10_3 |
| SERDES3_BS4PAD_3 | output | TCELL2:IO_E11_3 |
| TCK_FMAC_PCS | output | TCELL2:IO_E7_2 |
| TESTCLK_MACO | input | TCELL2:IO_W14_1 |
Bel PLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL0:IMUX_CLK1 |
| CLKI | input | TCELL0:IMUX_CLK0 |
| CLKOP | output | TCELL0:OUT_F1 |
| CLKOS | output | TCELL0:OUT_F0 |
| LOCK | output | TCELL0:OUT_Q3 |
| RST | input | TCELL0:IMUX_LSR0 |
| SMIRDATA | output | TCELL0:OUT_OFX1 |
| TPFB | output | TCELL0:OUT_Q5 |
| TPREF | output | TCELL0:OUT_Q4 |
Bel PLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL0:IMUX_CLK3 |
| CLKI | input | TCELL0:IMUX_CLK2 |
| CLKOP | output | TCELL0:OUT_F3 |
| CLKOS | output | TCELL0:OUT_F2 |
| LOCK | output | TCELL0:OUT_Q2 |
| RST | input | TCELL0:IMUX_LSR1 |
| SMIRDATA | output | TCELL0:OUT_OFX0 |
| TPFB | output | TCELL0:OUT_Q7 |
| TPREF | output | TCELL0:OUT_Q6 |
Bel PLL_SMI
| Pin | Direction | Wires |
|---|---|---|
| SMIADDR0 | input | TCELL0:IMUX_A1 |
| SMIADDR1 | input | TCELL0:IMUX_A2 |
| SMIADDR2 | input | TCELL0:IMUX_A3 |
| SMIADDR3 | input | TCELL0:IMUX_A4 |
| SMIADDR4 | input | TCELL0:IMUX_A5 |
| SMIADDR5 | input | TCELL0:IMUX_A6 |
| SMIADDR6 | input | TCELL0:IMUX_A7 |
| SMIADDR7 | input | TCELL0:IMUX_B0 |
| SMIADDR8 | input | TCELL0:IMUX_B1 |
| SMIADDR9 | input | TCELL0:IMUX_B2 |
| SMICLK | input | TCELL0:IMUX_B3 |
| SMIRD | input | TCELL0:IMUX_B4 |
| SMIRSTN | input | TCELL1:IMUX_LSR0 |
| SMIWDATA | input | TCELL0:IMUX_B6 |
| SMIWR | input | TCELL0:IMUX_B7 |
Bel DLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL1:IMUX_CLK1 |
| CLKI | input | TCELL1:IMUX_CLK0 |
| CLKOP | output | TCELL0:OUT_F4 |
| CLKOS | output | TCELL0:OUT_F5 |
| DTCCST0 | input | TCELL0:IMUX_C2 |
| DTCCST1 | input | TCELL0:IMUX_C3 |
| LOCK | output | TCELL0:OUT_Q1 |
| RST | input | TCELL0:IMUX_LSR2 |
| SMIRDATA | output | TCELL0:OUT_OFX3 |
| UDDCNTL | input | TCELL0:IMUX_C0 |
Bel DLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL1:IMUX_CLK3 |
| CLKI | input | TCELL1:IMUX_CLK2 |
| CLKOP | output | TCELL0:OUT_F6 |
| CLKOS | output | TCELL0:OUT_F7 |
| DTCCST0 | input | TCELL0:IMUX_C4 |
| DTCCST1 | input | TCELL0:IMUX_C5 |
| LOCK | output | TCELL0:OUT_Q0 |
| RST | input | TCELL0:IMUX_LSR3 |
| SMIRDATA | output | TCELL0:OUT_OFX2 |
| UDDCNTL | input | TCELL0:IMUX_C1 |
Bel DLL_DCNTL0
| Pin | Direction | Wires |
|---|---|---|
| DCNTL_IN0 | input | TCELL1:IMUX_A0 |
| DCNTL_IN1 | input | TCELL1:IMUX_A1 |
| DCNTL_IN2 | input | TCELL1:IMUX_A2 |
| DCNTL_IN3 | input | TCELL1:IMUX_A3 |
| DCNTL_IN4 | input | TCELL1:IMUX_A4 |
| DCNTL_IN5 | input | TCELL1:IMUX_A5 |
| DCNTL_IN6 | input | TCELL1:IMUX_A6 |
| DCNTL_IN7 | input | TCELL1:IMUX_A7 |
| DCNTL_IN8 | input | TCELL1:IMUX_B0 |
| DCNTL_OUT0 | output | TCELL1:OUT_F6 |
| DCNTL_OUT1 | output | TCELL1:OUT_F7 |
| DCNTL_OUT2 | output | TCELL1:OUT_Q0 |
| DCNTL_OUT3 | output | TCELL1:OUT_Q1 |
| DCNTL_OUT4 | output | TCELL1:OUT_Q2 |
| DCNTL_OUT5 | output | TCELL1:OUT_Q3 |
| DCNTL_OUT6 | output | TCELL1:OUT_Q4 |
| DCNTL_OUT7 | output | TCELL1:OUT_Q5 |
| DCNTL_OUT8 | output | TCELL1:OUT_Q6 |
Bel DLL_DCNTL1
| Pin | Direction | Wires |
|---|---|---|
| DCNTL_IN0 | input | TCELL1:IMUX_B1 |
| DCNTL_IN1 | input | TCELL1:IMUX_B2 |
| DCNTL_IN2 | input | TCELL1:IMUX_B3 |
| DCNTL_IN3 | input | TCELL1:IMUX_B4 |
| DCNTL_IN4 | input | TCELL1:IMUX_B5 |
| DCNTL_IN5 | input | TCELL1:IMUX_B6 |
| DCNTL_IN6 | input | TCELL1:IMUX_B7 |
| DCNTL_IN7 | input | TCELL1:IMUX_C0 |
| DCNTL_IN8 | input | TCELL1:IMUX_C1 |
| DCNTL_OUT0 | output | TCELL1:OUT_Q7 |
| DCNTL_OUT1 | output | TCELL1:OUT_OFX0 |
| DCNTL_OUT2 | output | TCELL1:OUT_OFX1 |
| DCNTL_OUT3 | output | TCELL1:OUT_OFX2 |
| DCNTL_OUT4 | output | TCELL1:OUT_OFX3 |
| DCNTL_OUT5 | output | TCELL1:OUT_OFX4 |
| DCNTL_OUT6 | output | TCELL1:OUT_OFX5 |
| DCNTL_OUT7 | output | TCELL1:OUT_OFX6 |
| DCNTL_OUT8 | output | TCELL1:OUT_OFX7 |
Bel M0
| Pin | Direction | Wires |
|---|---|---|
| M0 | output | TCELL1:OUT_F2 |
Bel M1
| Pin | Direction | Wires |
|---|---|---|
| M1 | output | TCELL1:OUT_F3 |
Bel M2
| Pin | Direction | Wires |
|---|---|---|
| M2 | output | TCELL1:OUT_F4 |
Bel M3
| Pin | Direction | Wires |
|---|---|---|
| M3 | output | TCELL1:OUT_F5 |
Bel RESETN
| Pin | Direction | Wires |
|---|---|---|
| RSTN | output | TCELL1:OUT_F0 |
Bel RDCFGN
| Pin | Direction | Wires |
|---|---|---|
| RDCFGN | output | TCELL1:OUT_F1 |
| TSALLN | input | TCELL0:IMUX_CE0 |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX_A1 | PLL_SMI.SMIADDR0 |
| TCELL0:IMUX_A2 | PLL_SMI.SMIADDR1 |
| TCELL0:IMUX_A3 | PLL_SMI.SMIADDR2 |
| TCELL0:IMUX_A4 | PLL_SMI.SMIADDR3 |
| TCELL0:IMUX_A5 | PLL_SMI.SMIADDR4 |
| TCELL0:IMUX_A6 | PLL_SMI.SMIADDR5 |
| TCELL0:IMUX_A7 | PLL_SMI.SMIADDR6 |
| TCELL0:IMUX_B0 | PLL_SMI.SMIADDR7 |
| TCELL0:IMUX_B1 | PLL_SMI.SMIADDR8 |
| TCELL0:IMUX_B2 | PLL_SMI.SMIADDR9 |
| TCELL0:IMUX_B3 | PLL_SMI.SMICLK |
| TCELL0:IMUX_B4 | PLL_SMI.SMIRD |
| TCELL0:IMUX_B6 | PLL_SMI.SMIWDATA |
| TCELL0:IMUX_B7 | PLL_SMI.SMIWR |
| TCELL0:IMUX_C0 | DLL0.UDDCNTL |
| TCELL0:IMUX_C1 | DLL1.UDDCNTL |
| TCELL0:IMUX_C2 | DLL0.DTCCST0 |
| TCELL0:IMUX_C3 | DLL0.DTCCST1 |
| TCELL0:IMUX_C4 | DLL1.DTCCST0 |
| TCELL0:IMUX_C5 | DLL1.DTCCST1 |
| TCELL0:IMUX_CLK0 | PLL0.CLKI |
| TCELL0:IMUX_CLK1 | PLL0.CLKFB |
| TCELL0:IMUX_CLK2 | PLL1.CLKI |
| TCELL0:IMUX_CLK3 | PLL1.CLKFB |
| TCELL0:IMUX_LSR0 | PLL0.RST |
| TCELL0:IMUX_LSR1 | PLL1.RST |
| TCELL0:IMUX_LSR2 | DLL0.RST |
| TCELL0:IMUX_LSR3 | DLL1.RST |
| TCELL0:IMUX_CE0 | RDCFGN.TSALLN |
| TCELL0:OUT_F0 | PLL0.CLKOS |
| TCELL0:OUT_F1 | PLL0.CLKOP |
| TCELL0:OUT_F2 | PLL1.CLKOS |
| TCELL0:OUT_F3 | PLL1.CLKOP |
| TCELL0:OUT_F4 | DLL0.CLKOP |
| TCELL0:OUT_F5 | DLL0.CLKOS |
| TCELL0:OUT_F6 | DLL1.CLKOP |
| TCELL0:OUT_F7 | DLL1.CLKOS |
| TCELL0:OUT_Q0 | DLL1.LOCK |
| TCELL0:OUT_Q1 | DLL0.LOCK |
| TCELL0:OUT_Q2 | PLL1.LOCK |
| TCELL0:OUT_Q3 | PLL0.LOCK |
| TCELL0:OUT_Q4 | PLL0.TPREF |
| TCELL0:OUT_Q5 | PLL0.TPFB |
| TCELL0:OUT_Q6 | PLL1.TPREF |
| TCELL0:OUT_Q7 | PLL1.TPFB |
| TCELL0:OUT_OFX0 | PLL1.SMIRDATA |
| TCELL0:OUT_OFX1 | PLL0.SMIRDATA |
| TCELL0:OUT_OFX2 | DLL1.SMIRDATA |
| TCELL0:OUT_OFX3 | DLL0.SMIRDATA |
| TCELL1:IMUX_A0 | DLL_DCNTL0.DCNTL_IN0 |
| TCELL1:IMUX_A1 | DLL_DCNTL0.DCNTL_IN1 |
| TCELL1:IMUX_A2 | DLL_DCNTL0.DCNTL_IN2 |
| TCELL1:IMUX_A3 | DLL_DCNTL0.DCNTL_IN3 |
| TCELL1:IMUX_A4 | DLL_DCNTL0.DCNTL_IN4 |
| TCELL1:IMUX_A5 | DLL_DCNTL0.DCNTL_IN5 |
| TCELL1:IMUX_A6 | DLL_DCNTL0.DCNTL_IN6 |
| TCELL1:IMUX_A7 | DLL_DCNTL0.DCNTL_IN7 |
| TCELL1:IMUX_B0 | DLL_DCNTL0.DCNTL_IN8 |
| TCELL1:IMUX_B1 | DLL_DCNTL1.DCNTL_IN0 |
| TCELL1:IMUX_B2 | DLL_DCNTL1.DCNTL_IN1 |
| TCELL1:IMUX_B3 | DLL_DCNTL1.DCNTL_IN2 |
| TCELL1:IMUX_B4 | DLL_DCNTL1.DCNTL_IN3 |
| TCELL1:IMUX_B5 | DLL_DCNTL1.DCNTL_IN4 |
| TCELL1:IMUX_B6 | DLL_DCNTL1.DCNTL_IN5 |
| TCELL1:IMUX_B7 | DLL_DCNTL1.DCNTL_IN6 |
| TCELL1:IMUX_C0 | DLL_DCNTL1.DCNTL_IN7 |
| TCELL1:IMUX_C1 | DLL_DCNTL1.DCNTL_IN8 |
| TCELL1:IMUX_CLK0 | DLL0.CLKI |
| TCELL1:IMUX_CLK1 | DLL0.CLKFB |
| TCELL1:IMUX_CLK2 | DLL1.CLKI |
| TCELL1:IMUX_CLK3 | DLL1.CLKFB |
| TCELL1:IMUX_LSR0 | PLL_SMI.SMIRSTN |
| TCELL1:OUT_F0 | RESETN.RSTN |
| TCELL1:OUT_F1 | RDCFGN.RDCFGN |
| TCELL1:OUT_F2 | M0.M0 |
| TCELL1:OUT_F3 | M1.M1 |
| TCELL1:OUT_F4 | M2.M2 |
| TCELL1:OUT_F5 | M3.M3 |
| TCELL1:OUT_F6 | DLL_DCNTL0.DCNTL_OUT0 |
| TCELL1:OUT_F7 | DLL_DCNTL0.DCNTL_OUT1 |
| TCELL1:OUT_Q0 | DLL_DCNTL0.DCNTL_OUT2 |
| TCELL1:OUT_Q1 | DLL_DCNTL0.DCNTL_OUT3 |
| TCELL1:OUT_Q2 | DLL_DCNTL0.DCNTL_OUT4 |
| TCELL1:OUT_Q3 | DLL_DCNTL0.DCNTL_OUT5 |
| TCELL1:OUT_Q4 | DLL_DCNTL0.DCNTL_OUT6 |
| TCELL1:OUT_Q5 | DLL_DCNTL0.DCNTL_OUT7 |
| TCELL1:OUT_Q6 | DLL_DCNTL0.DCNTL_OUT8 |
| TCELL1:OUT_Q7 | DLL_DCNTL1.DCNTL_OUT0 |
| TCELL1:OUT_OFX0 | DLL_DCNTL1.DCNTL_OUT1 |
| TCELL1:OUT_OFX1 | DLL_DCNTL1.DCNTL_OUT2 |
| TCELL1:OUT_OFX2 | DLL_DCNTL1.DCNTL_OUT3 |
| TCELL1:OUT_OFX3 | DLL_DCNTL1.DCNTL_OUT4 |
| TCELL1:OUT_OFX4 | DLL_DCNTL1.DCNTL_OUT5 |
| TCELL1:OUT_OFX5 | DLL_DCNTL1.DCNTL_OUT6 |
| TCELL1:OUT_OFX6 | DLL_DCNTL1.DCNTL_OUT7 |
| TCELL1:OUT_OFX7 | DLL_DCNTL1.DCNTL_OUT8 |
| TCELL2:IO_W0_1 | SERDES_CORNER.CIN_0 |
| TCELL2:IO_W1_1 | SERDES_CORNER.CIN_1 |
| TCELL2:IO_W2_1 | SERDES_CORNER.CIN_2 |
| TCELL2:IO_W3_1 | SERDES_CORNER.CIN_3 |
| TCELL2:IO_W4_1 | SERDES_CORNER.CIN_4 |
| TCELL2:IO_W5_1 | SERDES_CORNER.CIN_5 |
| TCELL2:IO_W6_1 | SERDES_CORNER.CIN_6 |
| TCELL2:IO_W7_1 | SERDES_CORNER.CIN_7 |
| TCELL2:IO_W8_1 | SERDES_CORNER.CIN_8 |
| TCELL2:IO_W9_1 | SERDES_CORNER.CIN_9 |
| TCELL2:IO_W10_1 | SERDES_CORNER.CIN_10 |
| TCELL2:IO_W11_1 | SERDES_CORNER.CIN_11 |
| TCELL2:IO_W12_1 | SERDES_CORNER.CIN_12 |
| TCELL2:IO_W14_1 | SERDES_CORNER.TESTCLK_MACO |
| TCELL2:IO_E0_2 | SERDES_CORNER.COUT_0 |
| TCELL2:IO_E0_3 | SERDES_CORNER.SERDES1_BS4PAD_3 |
| TCELL2:IO_E1_2 | SERDES_CORNER.COUT_1 |
| TCELL2:IO_E1_3 | SERDES_CORNER.SERDES2_BS4PAD_0 |
| TCELL2:IO_E2_2 | SERDES_CORNER.COUT_2 |
| TCELL2:IO_E2_3 | SERDES_CORNER.SERDES2_BS4PAD_1 |
| TCELL2:IO_E3_2 | SERDES_CORNER.COUT_3 |
| TCELL2:IO_E3_3 | SERDES_CORNER.SERDES2_BS4PAD_2 |
| TCELL2:IO_E4_2 | SERDES_CORNER.COUT_4 |
| TCELL2:IO_E4_3 | SERDES_CORNER.SERDES2_BS4PAD_3 |
| TCELL2:IO_E5_2 | SERDES_CORNER.COUT_5 |
| TCELL2:IO_E5_3 | SERDES_CORNER.SERDES3_BS4PAD_0 |
| TCELL2:IO_E7_2 | SERDES_CORNER.TCK_FMAC_PCS |
| TCELL2:IO_E9_2 | SERDES_CORNER.COUT_6 |
| TCELL2:IO_E9_3 | SERDES_CORNER.SERDES3_BS4PAD_1 |
| TCELL2:IO_E10_2 | SERDES_CORNER.COUT_7 |
| TCELL2:IO_E10_3 | SERDES_CORNER.SERDES3_BS4PAD_2 |
| TCELL2:IO_E11_2 | SERDES_CORNER.COUT_8 |
| TCELL2:IO_E11_3 | SERDES_CORNER.SERDES3_BS4PAD_3 |
| TCELL2:IO_E12_2 | SERDES_CORNER.COUT_9 |
| TCELL2:IO_E13_2 | SERDES_CORNER.COUT_10 |
| TCELL2:IO_E14_2 | SERDES_CORNER.COUT_11 |
| TCELL2:IO_E15_2 | SERDES_CORNER.COUT_12 |
| TCELL2:IO_E16_2 | SERDES_CORNER.COUT_13 |
| TCELL2:IO_E17_2 | SERDES_CORNER.COUT_14 |
| TCELL2:IO_E18_2 | SERDES_CORNER.COUT_15 |
| TCELL2:IO_E19_2 | SERDES_CORNER.COUT_16 |
| TCELL2:IO_E20_2 | SERDES_CORNER.COUT_17 |
| TCELL2:IO_E21_2 | SERDES_CORNER.COUT_18 |
| TCELL2:IO_E22_2 | SERDES_CORNER.COUT_19 |
| TCELL2:IO_E23_2 | SERDES_CORNER.COUT_20 |
| TCELL2:IO_E24_2 | SERDES_CORNER.COUT_21 |
| TCELL2:IO_E25_2 | SERDES_CORNER.SERDES0_BS4PAD_0 |
| TCELL2:IO_E26_2 | SERDES_CORNER.SERDES0_BS4PAD_1 |
| TCELL2:IO_E27_2 | SERDES_CORNER.SERDES0_BS4PAD_2 |
| TCELL2:IO_E28_2 | SERDES_CORNER.SERDES0_BS4PAD_3 |
| TCELL2:IO_E29_2 | SERDES_CORNER.SERDES1_BS4PAD_0 |
| TCELL2:IO_E30_2 | SERDES_CORNER.SERDES1_BS4PAD_1 |
| TCELL2:IO_E31_2 | SERDES_CORNER.SERDES1_BS4PAD_2 |
Tile PLL_NE
Cells: 3
Bel SERDES_CORNER
| Pin | Direction | Wires |
|---|---|---|
| CIN_0 | input | TCELL2:IO_E0_1 |
| CIN_1 | input | TCELL2:IO_E1_1 |
| CIN_10 | input | TCELL2:IO_E10_1 |
| CIN_11 | input | TCELL2:IO_E11_1 |
| CIN_12 | input | TCELL2:IO_E12_1 |
| CIN_2 | input | TCELL2:IO_E2_1 |
| CIN_3 | input | TCELL2:IO_E3_1 |
| CIN_4 | input | TCELL2:IO_E4_1 |
| CIN_5 | input | TCELL2:IO_E5_1 |
| CIN_6 | input | TCELL2:IO_E6_1 |
| CIN_7 | input | TCELL2:IO_E7_1 |
| CIN_8 | input | TCELL2:IO_E8_1 |
| CIN_9 | input | TCELL2:IO_E9_1 |
| COUT_0 | output | TCELL2:IO_W0_2 |
| COUT_1 | output | TCELL2:IO_W1_2 |
| COUT_10 | output | TCELL2:IO_W13_2 |
| COUT_11 | output | TCELL2:IO_W14_2 |
| COUT_12 | output | TCELL2:IO_W15_2 |
| COUT_13 | output | TCELL2:IO_W16_2 |
| COUT_14 | output | TCELL2:IO_W17_2 |
| COUT_15 | output | TCELL2:IO_W18_2 |
| COUT_16 | output | TCELL2:IO_W19_2 |
| COUT_17 | output | TCELL2:IO_W20_2 |
| COUT_18 | output | TCELL2:IO_W21_2 |
| COUT_19 | output | TCELL2:IO_W22_2 |
| COUT_2 | output | TCELL2:IO_W2_2 |
| COUT_20 | output | TCELL2:IO_W23_2 |
| COUT_21 | output | TCELL2:IO_W24_2 |
| COUT_3 | output | TCELL2:IO_W3_2 |
| COUT_4 | output | TCELL2:IO_W4_2 |
| COUT_5 | output | TCELL2:IO_W5_2 |
| COUT_6 | output | TCELL2:IO_W9_2 |
| COUT_7 | output | TCELL2:IO_W10_2 |
| COUT_8 | output | TCELL2:IO_W11_2 |
| COUT_9 | output | TCELL2:IO_W12_2 |
| SERDES0_BS4PAD_0 | output | TCELL2:IO_W25_2 |
| SERDES0_BS4PAD_1 | output | TCELL2:IO_W26_2 |
| SERDES0_BS4PAD_2 | output | TCELL2:IO_W27_2 |
| SERDES0_BS4PAD_3 | output | TCELL2:IO_W28_2 |
| SERDES1_BS4PAD_0 | output | TCELL2:IO_W29_2 |
| SERDES1_BS4PAD_1 | output | TCELL2:IO_W30_2 |
| SERDES1_BS4PAD_2 | output | TCELL2:IO_W31_2 |
| SERDES1_BS4PAD_3 | output | TCELL2:IO_W0_3 |
| SERDES2_BS4PAD_0 | output | TCELL2:IO_W1_3 |
| SERDES2_BS4PAD_1 | output | TCELL2:IO_W2_3 |
| SERDES2_BS4PAD_2 | output | TCELL2:IO_W3_3 |
| SERDES2_BS4PAD_3 | output | TCELL2:IO_W4_3 |
| SERDES3_BS4PAD_0 | output | TCELL2:IO_W5_3 |
| SERDES3_BS4PAD_1 | output | TCELL2:IO_W9_3 |
| SERDES3_BS4PAD_2 | output | TCELL2:IO_W10_3 |
| SERDES3_BS4PAD_3 | output | TCELL2:IO_W11_3 |
| TCK_FMAC_PCS | output | TCELL2:IO_W7_2 |
| TESTCLK_MACO | input | TCELL2:IO_E14_1 |
Bel PLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL0:IMUX_CLK2 |
| CLKI | input | TCELL0:IMUX_CLK3 |
| CLKOP | output | TCELL0:OUT_F6 |
| CLKOS | output | TCELL0:OUT_F7 |
| LOCK | output | TCELL0:OUT_Q4 |
| RST | input | TCELL0:IMUX_LSR3 |
| SMIRDATA | output | TCELL0:OUT_OFX6 |
| TPFB | output | TCELL0:OUT_Q2 |
| TPREF | output | TCELL0:OUT_Q3 |
Bel PLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL0:IMUX_CLK0 |
| CLKI | input | TCELL0:IMUX_CLK1 |
| CLKOP | output | TCELL0:OUT_F4 |
| CLKOS | output | TCELL0:OUT_F5 |
| LOCK | output | TCELL0:OUT_Q5 |
| RST | input | TCELL0:IMUX_LSR2 |
| SMIRDATA | output | TCELL0:OUT_OFX7 |
| TPFB | output | TCELL0:OUT_Q0 |
| TPREF | output | TCELL0:OUT_Q1 |
Bel PLL_SMI
| Pin | Direction | Wires |
|---|---|---|
| SMIADDR0 | input | TCELL0:IMUX_A6 |
| SMIADDR1 | input | TCELL0:IMUX_A5 |
| SMIADDR2 | input | TCELL0:IMUX_A4 |
| SMIADDR3 | input | TCELL0:IMUX_A3 |
| SMIADDR4 | input | TCELL0:IMUX_A2 |
| SMIADDR5 | input | TCELL0:IMUX_A1 |
| SMIADDR6 | input | TCELL0:IMUX_A0 |
| SMIADDR7 | input | TCELL0:IMUX_B7 |
| SMIADDR8 | input | TCELL0:IMUX_B6 |
| SMIADDR9 | input | TCELL0:IMUX_B5 |
| SMICLK | input | TCELL0:IMUX_B4 |
| SMIRD | input | TCELL0:IMUX_B3 |
| SMIRSTN | input | TCELL1:IMUX_LSR3 |
| SMIWDATA | input | TCELL0:IMUX_B1 |
| SMIWR | input | TCELL0:IMUX_B0 |
Bel DLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL1:IMUX_CLK2 |
| CLKI | input | TCELL1:IMUX_CLK3 |
| CLKOP | output | TCELL0:OUT_F3 |
| CLKOS | output | TCELL0:OUT_F2 |
| DTCCST0 | input | TCELL0:IMUX_C5 |
| DTCCST1 | input | TCELL0:IMUX_C4 |
| LOCK | output | TCELL0:OUT_Q6 |
| RST | input | TCELL0:IMUX_LSR1 |
| SMIRDATA | output | TCELL0:OUT_OFX4 |
| UDDCNTL | input | TCELL0:IMUX_C7 |
Bel DLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKFB | input | TCELL1:IMUX_CLK0 |
| CLKI | input | TCELL1:IMUX_CLK1 |
| CLKOP | output | TCELL0:OUT_F1 |
| CLKOS | output | TCELL0:OUT_F0 |
| DTCCST0 | input | TCELL0:IMUX_C3 |
| DTCCST1 | input | TCELL0:IMUX_C2 |
| LOCK | output | TCELL0:OUT_Q7 |
| RST | input | TCELL0:IMUX_LSR0 |
| SMIRDATA | output | TCELL0:OUT_OFX5 |
| UDDCNTL | input | TCELL0:IMUX_C6 |
Bel DLL_DCNTL0
| Pin | Direction | Wires |
|---|---|---|
| DCNTL_IN0 | input | TCELL1:IMUX_A7 |
| DCNTL_IN1 | input | TCELL1:IMUX_A6 |
| DCNTL_IN2 | input | TCELL1:IMUX_A5 |
| DCNTL_IN3 | input | TCELL1:IMUX_A4 |
| DCNTL_IN4 | input | TCELL1:IMUX_A3 |
| DCNTL_IN5 | input | TCELL1:IMUX_A2 |
| DCNTL_IN6 | input | TCELL1:IMUX_A1 |
| DCNTL_IN7 | input | TCELL1:IMUX_A0 |
| DCNTL_IN8 | input | TCELL1:IMUX_B7 |
| DCNTL_OUT0 | output | TCELL1:OUT_F1 |
| DCNTL_OUT1 | output | TCELL1:OUT_F0 |
| DCNTL_OUT2 | output | TCELL1:OUT_Q7 |
| DCNTL_OUT3 | output | TCELL1:OUT_Q6 |
| DCNTL_OUT4 | output | TCELL1:OUT_Q5 |
| DCNTL_OUT5 | output | TCELL1:OUT_Q4 |
| DCNTL_OUT6 | output | TCELL1:OUT_Q3 |
| DCNTL_OUT7 | output | TCELL1:OUT_Q2 |
| DCNTL_OUT8 | output | TCELL1:OUT_Q1 |
Bel DLL_DCNTL1
| Pin | Direction | Wires |
|---|---|---|
| DCNTL_IN0 | input | TCELL1:IMUX_B6 |
| DCNTL_IN1 | input | TCELL1:IMUX_B5 |
| DCNTL_IN2 | input | TCELL1:IMUX_B4 |
| DCNTL_IN3 | input | TCELL1:IMUX_B3 |
| DCNTL_IN4 | input | TCELL1:IMUX_B2 |
| DCNTL_IN5 | input | TCELL1:IMUX_B1 |
| DCNTL_IN6 | input | TCELL1:IMUX_B0 |
| DCNTL_IN7 | input | TCELL1:IMUX_C7 |
| DCNTL_IN8 | input | TCELL1:IMUX_C6 |
| DCNTL_OUT0 | output | TCELL1:OUT_Q0 |
| DCNTL_OUT1 | output | TCELL1:OUT_OFX7 |
| DCNTL_OUT2 | output | TCELL1:OUT_OFX6 |
| DCNTL_OUT3 | output | TCELL1:OUT_OFX5 |
| DCNTL_OUT4 | output | TCELL1:OUT_OFX4 |
| DCNTL_OUT5 | output | TCELL1:OUT_OFX3 |
| DCNTL_OUT6 | output | TCELL1:OUT_OFX2 |
| DCNTL_OUT7 | output | TCELL1:OUT_OFX1 |
| DCNTL_OUT8 | output | TCELL1:OUT_OFX0 |
Bel CCLK
| Pin | Direction | Wires |
|---|---|---|
| CCLK | output | TCELL1:OUT_F7 |
Bel TCK
| Pin | Direction | Wires |
|---|---|---|
| TCK | output | TCELL1:OUT_F6 |
Bel TMS
| Pin | Direction | Wires |
|---|---|---|
| TMS | output | TCELL1:OUT_F4 |
Bel TDI
| Pin | Direction | Wires |
|---|---|---|
| TDI | output | TCELL1:OUT_F5 |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX_A0 | PLL_SMI.SMIADDR6 |
| TCELL0:IMUX_A1 | PLL_SMI.SMIADDR5 |
| TCELL0:IMUX_A2 | PLL_SMI.SMIADDR4 |
| TCELL0:IMUX_A3 | PLL_SMI.SMIADDR3 |
| TCELL0:IMUX_A4 | PLL_SMI.SMIADDR2 |
| TCELL0:IMUX_A5 | PLL_SMI.SMIADDR1 |
| TCELL0:IMUX_A6 | PLL_SMI.SMIADDR0 |
| TCELL0:IMUX_B0 | PLL_SMI.SMIWR |
| TCELL0:IMUX_B1 | PLL_SMI.SMIWDATA |
| TCELL0:IMUX_B3 | PLL_SMI.SMIRD |
| TCELL0:IMUX_B4 | PLL_SMI.SMICLK |
| TCELL0:IMUX_B5 | PLL_SMI.SMIADDR9 |
| TCELL0:IMUX_B6 | PLL_SMI.SMIADDR8 |
| TCELL0:IMUX_B7 | PLL_SMI.SMIADDR7 |
| TCELL0:IMUX_C2 | DLL1.DTCCST1 |
| TCELL0:IMUX_C3 | DLL1.DTCCST0 |
| TCELL0:IMUX_C4 | DLL0.DTCCST1 |
| TCELL0:IMUX_C5 | DLL0.DTCCST0 |
| TCELL0:IMUX_C6 | DLL1.UDDCNTL |
| TCELL0:IMUX_C7 | DLL0.UDDCNTL |
| TCELL0:IMUX_CLK0 | PLL1.CLKFB |
| TCELL0:IMUX_CLK1 | PLL1.CLKI |
| TCELL0:IMUX_CLK2 | PLL0.CLKFB |
| TCELL0:IMUX_CLK3 | PLL0.CLKI |
| TCELL0:IMUX_LSR0 | DLL1.RST |
| TCELL0:IMUX_LSR1 | DLL0.RST |
| TCELL0:IMUX_LSR2 | PLL1.RST |
| TCELL0:IMUX_LSR3 | PLL0.RST |
| TCELL0:OUT_F0 | DLL1.CLKOS |
| TCELL0:OUT_F1 | DLL1.CLKOP |
| TCELL0:OUT_F2 | DLL0.CLKOS |
| TCELL0:OUT_F3 | DLL0.CLKOP |
| TCELL0:OUT_F4 | PLL1.CLKOP |
| TCELL0:OUT_F5 | PLL1.CLKOS |
| TCELL0:OUT_F6 | PLL0.CLKOP |
| TCELL0:OUT_F7 | PLL0.CLKOS |
| TCELL0:OUT_Q0 | PLL1.TPFB |
| TCELL0:OUT_Q1 | PLL1.TPREF |
| TCELL0:OUT_Q2 | PLL0.TPFB |
| TCELL0:OUT_Q3 | PLL0.TPREF |
| TCELL0:OUT_Q4 | PLL0.LOCK |
| TCELL0:OUT_Q5 | PLL1.LOCK |
| TCELL0:OUT_Q6 | DLL0.LOCK |
| TCELL0:OUT_Q7 | DLL1.LOCK |
| TCELL0:OUT_OFX4 | DLL0.SMIRDATA |
| TCELL0:OUT_OFX5 | DLL1.SMIRDATA |
| TCELL0:OUT_OFX6 | PLL0.SMIRDATA |
| TCELL0:OUT_OFX7 | PLL1.SMIRDATA |
| TCELL1:IMUX_A0 | DLL_DCNTL0.DCNTL_IN7 |
| TCELL1:IMUX_A1 | DLL_DCNTL0.DCNTL_IN6 |
| TCELL1:IMUX_A2 | DLL_DCNTL0.DCNTL_IN5 |
| TCELL1:IMUX_A3 | DLL_DCNTL0.DCNTL_IN4 |
| TCELL1:IMUX_A4 | DLL_DCNTL0.DCNTL_IN3 |
| TCELL1:IMUX_A5 | DLL_DCNTL0.DCNTL_IN2 |
| TCELL1:IMUX_A6 | DLL_DCNTL0.DCNTL_IN1 |
| TCELL1:IMUX_A7 | DLL_DCNTL0.DCNTL_IN0 |
| TCELL1:IMUX_B0 | DLL_DCNTL1.DCNTL_IN6 |
| TCELL1:IMUX_B1 | DLL_DCNTL1.DCNTL_IN5 |
| TCELL1:IMUX_B2 | DLL_DCNTL1.DCNTL_IN4 |
| TCELL1:IMUX_B3 | DLL_DCNTL1.DCNTL_IN3 |
| TCELL1:IMUX_B4 | DLL_DCNTL1.DCNTL_IN2 |
| TCELL1:IMUX_B5 | DLL_DCNTL1.DCNTL_IN1 |
| TCELL1:IMUX_B6 | DLL_DCNTL1.DCNTL_IN0 |
| TCELL1:IMUX_B7 | DLL_DCNTL0.DCNTL_IN8 |
| TCELL1:IMUX_C6 | DLL_DCNTL1.DCNTL_IN8 |
| TCELL1:IMUX_C7 | DLL_DCNTL1.DCNTL_IN7 |
| TCELL1:IMUX_CLK0 | DLL1.CLKFB |
| TCELL1:IMUX_CLK1 | DLL1.CLKI |
| TCELL1:IMUX_CLK2 | DLL0.CLKFB |
| TCELL1:IMUX_CLK3 | DLL0.CLKI |
| TCELL1:IMUX_LSR3 | PLL_SMI.SMIRSTN |
| TCELL1:OUT_F0 | DLL_DCNTL0.DCNTL_OUT1 |
| TCELL1:OUT_F1 | DLL_DCNTL0.DCNTL_OUT0 |
| TCELL1:OUT_F4 | TMS.TMS |
| TCELL1:OUT_F5 | TDI.TDI |
| TCELL1:OUT_F6 | TCK.TCK |
| TCELL1:OUT_F7 | CCLK.CCLK |
| TCELL1:OUT_Q0 | DLL_DCNTL1.DCNTL_OUT0 |
| TCELL1:OUT_Q1 | DLL_DCNTL0.DCNTL_OUT8 |
| TCELL1:OUT_Q2 | DLL_DCNTL0.DCNTL_OUT7 |
| TCELL1:OUT_Q3 | DLL_DCNTL0.DCNTL_OUT6 |
| TCELL1:OUT_Q4 | DLL_DCNTL0.DCNTL_OUT5 |
| TCELL1:OUT_Q5 | DLL_DCNTL0.DCNTL_OUT4 |
| TCELL1:OUT_Q6 | DLL_DCNTL0.DCNTL_OUT3 |
| TCELL1:OUT_Q7 | DLL_DCNTL0.DCNTL_OUT2 |
| TCELL1:OUT_OFX0 | DLL_DCNTL1.DCNTL_OUT8 |
| TCELL1:OUT_OFX1 | DLL_DCNTL1.DCNTL_OUT7 |
| TCELL1:OUT_OFX2 | DLL_DCNTL1.DCNTL_OUT6 |
| TCELL1:OUT_OFX3 | DLL_DCNTL1.DCNTL_OUT5 |
| TCELL1:OUT_OFX4 | DLL_DCNTL1.DCNTL_OUT4 |
| TCELL1:OUT_OFX5 | DLL_DCNTL1.DCNTL_OUT3 |
| TCELL1:OUT_OFX6 | DLL_DCNTL1.DCNTL_OUT2 |
| TCELL1:OUT_OFX7 | DLL_DCNTL1.DCNTL_OUT1 |
| TCELL2:IO_W0_2 | SERDES_CORNER.COUT_0 |
| TCELL2:IO_W0_3 | SERDES_CORNER.SERDES1_BS4PAD_3 |
| TCELL2:IO_W1_2 | SERDES_CORNER.COUT_1 |
| TCELL2:IO_W1_3 | SERDES_CORNER.SERDES2_BS4PAD_0 |
| TCELL2:IO_W2_2 | SERDES_CORNER.COUT_2 |
| TCELL2:IO_W2_3 | SERDES_CORNER.SERDES2_BS4PAD_1 |
| TCELL2:IO_W3_2 | SERDES_CORNER.COUT_3 |
| TCELL2:IO_W3_3 | SERDES_CORNER.SERDES2_BS4PAD_2 |
| TCELL2:IO_W4_2 | SERDES_CORNER.COUT_4 |
| TCELL2:IO_W4_3 | SERDES_CORNER.SERDES2_BS4PAD_3 |
| TCELL2:IO_W5_2 | SERDES_CORNER.COUT_5 |
| TCELL2:IO_W5_3 | SERDES_CORNER.SERDES3_BS4PAD_0 |
| TCELL2:IO_W7_2 | SERDES_CORNER.TCK_FMAC_PCS |
| TCELL2:IO_W9_2 | SERDES_CORNER.COUT_6 |
| TCELL2:IO_W9_3 | SERDES_CORNER.SERDES3_BS4PAD_1 |
| TCELL2:IO_W10_2 | SERDES_CORNER.COUT_7 |
| TCELL2:IO_W10_3 | SERDES_CORNER.SERDES3_BS4PAD_2 |
| TCELL2:IO_W11_2 | SERDES_CORNER.COUT_8 |
| TCELL2:IO_W11_3 | SERDES_CORNER.SERDES3_BS4PAD_3 |
| TCELL2:IO_W12_2 | SERDES_CORNER.COUT_9 |
| TCELL2:IO_W13_2 | SERDES_CORNER.COUT_10 |
| TCELL2:IO_W14_2 | SERDES_CORNER.COUT_11 |
| TCELL2:IO_W15_2 | SERDES_CORNER.COUT_12 |
| TCELL2:IO_W16_2 | SERDES_CORNER.COUT_13 |
| TCELL2:IO_W17_2 | SERDES_CORNER.COUT_14 |
| TCELL2:IO_W18_2 | SERDES_CORNER.COUT_15 |
| TCELL2:IO_W19_2 | SERDES_CORNER.COUT_16 |
| TCELL2:IO_W20_2 | SERDES_CORNER.COUT_17 |
| TCELL2:IO_W21_2 | SERDES_CORNER.COUT_18 |
| TCELL2:IO_W22_2 | SERDES_CORNER.COUT_19 |
| TCELL2:IO_W23_2 | SERDES_CORNER.COUT_20 |
| TCELL2:IO_W24_2 | SERDES_CORNER.COUT_21 |
| TCELL2:IO_W25_2 | SERDES_CORNER.SERDES0_BS4PAD_0 |
| TCELL2:IO_W26_2 | SERDES_CORNER.SERDES0_BS4PAD_1 |
| TCELL2:IO_W27_2 | SERDES_CORNER.SERDES0_BS4PAD_2 |
| TCELL2:IO_W28_2 | SERDES_CORNER.SERDES0_BS4PAD_3 |
| TCELL2:IO_W29_2 | SERDES_CORNER.SERDES1_BS4PAD_0 |
| TCELL2:IO_W30_2 | SERDES_CORNER.SERDES1_BS4PAD_1 |
| TCELL2:IO_W31_2 | SERDES_CORNER.SERDES1_BS4PAD_2 |
| TCELL2:IO_E0_1 | SERDES_CORNER.CIN_0 |
| TCELL2:IO_E1_1 | SERDES_CORNER.CIN_1 |
| TCELL2:IO_E2_1 | SERDES_CORNER.CIN_2 |
| TCELL2:IO_E3_1 | SERDES_CORNER.CIN_3 |
| TCELL2:IO_E4_1 | SERDES_CORNER.CIN_4 |
| TCELL2:IO_E5_1 | SERDES_CORNER.CIN_5 |
| TCELL2:IO_E6_1 | SERDES_CORNER.CIN_6 |
| TCELL2:IO_E7_1 | SERDES_CORNER.CIN_7 |
| TCELL2:IO_E8_1 | SERDES_CORNER.CIN_8 |
| TCELL2:IO_E9_1 | SERDES_CORNER.CIN_9 |
| TCELL2:IO_E10_1 | SERDES_CORNER.CIN_10 |
| TCELL2:IO_E11_1 | SERDES_CORNER.CIN_11 |
| TCELL2:IO_E12_1 | SERDES_CORNER.CIN_12 |
| TCELL2:IO_E14_1 | SERDES_CORNER.TESTCLK_MACO |