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Phase-Locked Loops

Tile PLL_SW

Cells: 6

Bel PLL0

scm PLL_SW bel PLL0
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK1
CLKIinputCELL1.IMUX_CLK0
CLKOPoutputCELL0.OUT_Q2
CLKOSoutputCELL0.OUT_F2
LOCKoutputCELL1.OUT_OFX6
RSTinputCELL1.IMUX_LSR3
SMIRDATAoutputCELL1.OUT_OFX3
TPFBoutputCELL0.OUT_F4
TPREFoutputCELL0.OUT_Q4

Bel PLL1

scm PLL_SW bel PLL1
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK3
CLKIinputCELL1.IMUX_CLK2
CLKOPoutputCELL0.OUT_Q7
CLKOSoutputCELL0.OUT_F7
LOCKoutputCELL1.OUT_OFX4
RSTinputCELL1.IMUX_LSR2
SMIRDATAoutputCELL1.OUT_OFX2
TPFBoutputCELL0.OUT_Q5
TPREFoutputCELL0.OUT_F5

Bel PLL_SMI

scm PLL_SW bel PLL_SMI
PinDirectionWires
SMIADDR0inputCELL0.IMUX_B2
SMIADDR1inputCELL0.IMUX_A2
SMIADDR2inputCELL0.IMUX_A1
SMIADDR3inputCELL0.IMUX_B1
SMIADDR4inputCELL0.IMUX_C1
SMIADDR5inputCELL0.IMUX_D1
SMIADDR6inputCELL0.IMUX_D0
SMIADDR7inputCELL0.IMUX_C0
SMIADDR8inputCELL0.IMUX_B0
SMIADDR9inputCELL0.IMUX_A0
SMICLKinputCELL0.IMUX_C2
SMIRDinputCELL0.IMUX_C3
SMIRSTNinputCELL0.IMUX_LSR0
SMIWDATAinputCELL0.IMUX_D3
SMIWRinputCELL0.IMUX_D2

Bel DLL0

scm PLL_SW bel DLL0
PinDirectionWires
CLKFBinputCELL0.IMUX_CLK3
CLKIinputCELL0.IMUX_CLK2
CLKOPoutputCELL1.OUT_F6
CLKOSoutputCELL1.OUT_Q6
DTCCST0inputCELL0.IMUX_A6
DTCCST1inputCELL0.IMUX_B6
LOCKoutputCELL1.OUT_Q3
RSTinputCELL1.IMUX_LSR0
SMIRDATAoutputCELL1.OUT_Q5
UDDCNTLinputCELL0.IMUX_A5

Bel DLL1

scm PLL_SW bel DLL1
PinDirectionWires
CLKFBinputCELL2.IMUX_CLK2
CLKIinputCELL3.IMUX_CLK2
CLKOPoutputCELL1.OUT_OFX7
CLKOSoutputCELL1.OUT_F7
DTCCST0inputCELL0.IMUX_C5
DTCCST1inputCELL0.IMUX_D5
LOCKoutputCELL1.OUT_Q2
RSTinputCELL0.IMUX_LSR3
SMIRDATAoutputCELL1.OUT_Q4
UDDCNTLinputCELL0.IMUX_B5

Bel DLL2

scm PLL_SW bel DLL2
PinDirectionWires
CLKFBinputCELL0.IMUX_CLK0
CLKIinputCELL0.IMUX_CLK1
CLKOPoutputCELL0.OUT_F1
CLKOSoutputCELL0.OUT_Q1
DTCCST0inputCELL0.IMUX_B4
DTCCST1inputCELL0.IMUX_A4
LOCKoutputCELL1.OUT_F3
RSTinputCELL0.IMUX_LSR2
SMIRDATAoutputCELL1.OUT_F5
UDDCNTLinputCELL0.IMUX_D4

Bel DLL3

scm PLL_SW bel DLL3
PinDirectionWires
CLKFBinputCELL5.IMUX_CLK1
CLKIinputCELL4.IMUX_CLK1
CLKOPoutputCELL0.OUT_F0
CLKOSoutputCELL0.OUT_OFX0
DTCCST0inputCELL0.IMUX_B3
DTCCST1inputCELL0.IMUX_A3
LOCKoutputCELL1.OUT_F2
RSTinputCELL0.IMUX_LSR1
SMIRDATAoutputCELL1.OUT_F4
UDDCNTLinputCELL0.IMUX_C4

Bel DLL_DCNTL0

scm PLL_SW bel DLL_DCNTL0
PinDirectionWires
DCNTL_IN0inputCELL1.IMUX_D0
DCNTL_IN1inputCELL1.IMUX_D1
DCNTL_IN2inputCELL1.IMUX_C1
DCNTL_IN3inputCELL1.IMUX_B1
DCNTL_IN4inputCELL1.IMUX_A1
DCNTL_IN5inputCELL1.IMUX_A2
DCNTL_IN6inputCELL1.IMUX_D2
DCNTL_IN7inputCELL1.IMUX_C2
DCNTL_IN8inputCELL1.IMUX_B2
DCNTL_OUT0outputCELL0.OUT_F6
DCNTL_OUT1outputCELL0.OUT_Q6
DCNTL_OUT2outputCELL0.OUT_OFX7
DCNTL_OUT3outputCELL1.OUT_OFX0
DCNTL_OUT4outputCELL1.OUT_F0
DCNTL_OUT5outputCELL1.OUT_Q0
DCNTL_OUT6outputCELL1.OUT_Q1
DCNTL_OUT7outputCELL1.OUT_F1
DCNTL_OUT8outputCELL1.OUT_OFX1

Bel DLL_DCNTL1

scm PLL_SW bel DLL_DCNTL1
PinDirectionWires
DCNTL_IN0inputCELL0.IMUX_C6
DCNTL_IN1inputCELL0.IMUX_D6
DCNTL_IN2inputCELL0.IMUX_D7
DCNTL_IN3inputCELL0.IMUX_C7
DCNTL_IN4inputCELL0.IMUX_B7
DCNTL_IN5inputCELL0.IMUX_A7
DCNTL_IN6inputCELL1.IMUX_C0
DCNTL_IN7inputCELL1.IMUX_B0
DCNTL_IN8inputCELL1.IMUX_A0
DCNTL_OUT0outputCELL0.OUT_Q0
DCNTL_OUT1outputCELL0.OUT_OFX1
DCNTL_OUT2outputCELL0.OUT_OFX2
DCNTL_OUT3outputCELL0.OUT_Q3
DCNTL_OUT4outputCELL0.OUT_F3
DCNTL_OUT5outputCELL0.OUT_OFX3
DCNTL_OUT6outputCELL0.OUT_OFX4
DCNTL_OUT7outputCELL0.OUT_OFX5
DCNTL_OUT8outputCELL0.OUT_OFX6

Bel PROMON

scm PLL_SW bel PROMON
PinDirectionWires
PROCHKinputCELL1.IMUX_B4
PROMONoutputCELL1.OUT_Q7

Bel RNET

scm PLL_SW bel RNET
PinDirectionWires
RNETI0inputCELL1.IMUX_D5
RNETI1inputCELL1.IMUX_D4
RNETI2inputCELL1.IMUX_C4
RNETI3inputCELL1.IMUX_A5
RNETI4inputCELL1.IMUX_B5
RNETI5inputCELL1.IMUX_C5
RNETO0outputCELL4.OUT_IO7
RNETO1outputCELL4.OUT_IO5
RNETO2outputCELL3.OUT_IO1
RNETO3outputCELL2.OUT_IO7
RNETO4outputCELL2.OUT_IO1
RNETO5outputCELL1.OUT_OFX5
RNETUPDinputCELL1.IMUX_CE3

Bel wires

scm PLL_SW bel wires
WirePins
CELL0.IMUX_A0PLL_SMI.SMIADDR9
CELL0.IMUX_A1PLL_SMI.SMIADDR2
CELL0.IMUX_A2PLL_SMI.SMIADDR1
CELL0.IMUX_A3DLL3.DTCCST1
CELL0.IMUX_A4DLL2.DTCCST1
CELL0.IMUX_A5DLL0.UDDCNTL
CELL0.IMUX_A6DLL0.DTCCST0
CELL0.IMUX_A7DLL_DCNTL1.DCNTL_IN5
CELL0.IMUX_B0PLL_SMI.SMIADDR8
CELL0.IMUX_B1PLL_SMI.SMIADDR3
CELL0.IMUX_B2PLL_SMI.SMIADDR0
CELL0.IMUX_B3DLL3.DTCCST0
CELL0.IMUX_B4DLL2.DTCCST0
CELL0.IMUX_B5DLL1.UDDCNTL
CELL0.IMUX_B6DLL0.DTCCST1
CELL0.IMUX_B7DLL_DCNTL1.DCNTL_IN4
CELL0.IMUX_C0PLL_SMI.SMIADDR7
CELL0.IMUX_C1PLL_SMI.SMIADDR4
CELL0.IMUX_C2PLL_SMI.SMICLK
CELL0.IMUX_C3PLL_SMI.SMIRD
CELL0.IMUX_C4DLL3.UDDCNTL
CELL0.IMUX_C5DLL1.DTCCST0
CELL0.IMUX_C6DLL_DCNTL1.DCNTL_IN0
CELL0.IMUX_C7DLL_DCNTL1.DCNTL_IN3
CELL0.IMUX_D0PLL_SMI.SMIADDR6
CELL0.IMUX_D1PLL_SMI.SMIADDR5
CELL0.IMUX_D2PLL_SMI.SMIWR
CELL0.IMUX_D3PLL_SMI.SMIWDATA
CELL0.IMUX_D4DLL2.UDDCNTL
CELL0.IMUX_D5DLL1.DTCCST1
CELL0.IMUX_D6DLL_DCNTL1.DCNTL_IN1
CELL0.IMUX_D7DLL_DCNTL1.DCNTL_IN2
CELL0.IMUX_CLK0DLL2.CLKFB
CELL0.IMUX_CLK1DLL2.CLKI
CELL0.IMUX_CLK2DLL0.CLKI
CELL0.IMUX_CLK3DLL0.CLKFB
CELL0.IMUX_LSR0PLL_SMI.SMIRSTN
CELL0.IMUX_LSR1DLL3.RST
CELL0.IMUX_LSR2DLL2.RST
CELL0.IMUX_LSR3DLL1.RST
CELL0.OUT_F0DLL3.CLKOP
CELL0.OUT_F1DLL2.CLKOP
CELL0.OUT_F2PLL0.CLKOS
CELL0.OUT_F3DLL_DCNTL1.DCNTL_OUT4
CELL0.OUT_F4PLL0.TPFB
CELL0.OUT_F5PLL1.TPREF
CELL0.OUT_F6DLL_DCNTL0.DCNTL_OUT0
CELL0.OUT_F7PLL1.CLKOS
CELL0.OUT_Q0DLL_DCNTL1.DCNTL_OUT0
CELL0.OUT_Q1DLL2.CLKOS
CELL0.OUT_Q2PLL0.CLKOP
CELL0.OUT_Q3DLL_DCNTL1.DCNTL_OUT3
CELL0.OUT_Q4PLL0.TPREF
CELL0.OUT_Q5PLL1.TPFB
CELL0.OUT_Q6DLL_DCNTL0.DCNTL_OUT1
CELL0.OUT_Q7PLL1.CLKOP
CELL0.OUT_OFX0DLL3.CLKOS
CELL0.OUT_OFX1DLL_DCNTL1.DCNTL_OUT1
CELL0.OUT_OFX2DLL_DCNTL1.DCNTL_OUT2
CELL0.OUT_OFX3DLL_DCNTL1.DCNTL_OUT5
CELL0.OUT_OFX4DLL_DCNTL1.DCNTL_OUT6
CELL0.OUT_OFX5DLL_DCNTL1.DCNTL_OUT7
CELL0.OUT_OFX6DLL_DCNTL1.DCNTL_OUT8
CELL0.OUT_OFX7DLL_DCNTL0.DCNTL_OUT2
CELL1.IMUX_A0DLL_DCNTL1.DCNTL_IN8
CELL1.IMUX_A1DLL_DCNTL0.DCNTL_IN4
CELL1.IMUX_A2DLL_DCNTL0.DCNTL_IN5
CELL1.IMUX_A5RNET.RNETI3
CELL1.IMUX_B0DLL_DCNTL1.DCNTL_IN7
CELL1.IMUX_B1DLL_DCNTL0.DCNTL_IN3
CELL1.IMUX_B2DLL_DCNTL0.DCNTL_IN8
CELL1.IMUX_B4PROMON.PROCHK
CELL1.IMUX_B5RNET.RNETI4
CELL1.IMUX_C0DLL_DCNTL1.DCNTL_IN6
CELL1.IMUX_C1DLL_DCNTL0.DCNTL_IN2
CELL1.IMUX_C2DLL_DCNTL0.DCNTL_IN7
CELL1.IMUX_C4RNET.RNETI2
CELL1.IMUX_C5RNET.RNETI5
CELL1.IMUX_D0DLL_DCNTL0.DCNTL_IN0
CELL1.IMUX_D1DLL_DCNTL0.DCNTL_IN1
CELL1.IMUX_D2DLL_DCNTL0.DCNTL_IN6
CELL1.IMUX_D4RNET.RNETI1
CELL1.IMUX_D5RNET.RNETI0
CELL1.IMUX_CLK0PLL0.CLKI
CELL1.IMUX_CLK1PLL0.CLKFB
CELL1.IMUX_CLK2PLL1.CLKI
CELL1.IMUX_CLK3PLL1.CLKFB
CELL1.IMUX_LSR0DLL0.RST
CELL1.IMUX_LSR2PLL1.RST
CELL1.IMUX_LSR3PLL0.RST
CELL1.IMUX_CE3RNET.RNETUPD
CELL1.OUT_F0DLL_DCNTL0.DCNTL_OUT4
CELL1.OUT_F1DLL_DCNTL0.DCNTL_OUT7
CELL1.OUT_F2DLL3.LOCK
CELL1.OUT_F3DLL2.LOCK
CELL1.OUT_F4DLL3.SMIRDATA
CELL1.OUT_F5DLL2.SMIRDATA
CELL1.OUT_F6DLL0.CLKOP
CELL1.OUT_F7DLL1.CLKOS
CELL1.OUT_Q0DLL_DCNTL0.DCNTL_OUT5
CELL1.OUT_Q1DLL_DCNTL0.DCNTL_OUT6
CELL1.OUT_Q2DLL1.LOCK
CELL1.OUT_Q3DLL0.LOCK
CELL1.OUT_Q4DLL1.SMIRDATA
CELL1.OUT_Q5DLL0.SMIRDATA
CELL1.OUT_Q6DLL0.CLKOS
CELL1.OUT_Q7PROMON.PROMON
CELL1.OUT_OFX0DLL_DCNTL0.DCNTL_OUT3
CELL1.OUT_OFX1DLL_DCNTL0.DCNTL_OUT8
CELL1.OUT_OFX2PLL1.SMIRDATA
CELL1.OUT_OFX3PLL0.SMIRDATA
CELL1.OUT_OFX4PLL1.LOCK
CELL1.OUT_OFX5RNET.RNETO5
CELL1.OUT_OFX6PLL0.LOCK
CELL1.OUT_OFX7DLL1.CLKOP
CELL2.IMUX_CLK2DLL1.CLKFB
CELL2.OUT_IO1RNET.RNETO4
CELL2.OUT_IO7RNET.RNETO3
CELL3.IMUX_CLK2DLL1.CLKI
CELL3.OUT_IO1RNET.RNETO2
CELL4.IMUX_CLK1DLL3.CLKI
CELL4.OUT_IO5RNET.RNETO1
CELL4.OUT_IO7RNET.RNETO0
CELL5.IMUX_CLK1DLL3.CLKFB

Tile PLL_SE

Cells: 6

Bel PLL0

scm PLL_SE bel PLL0
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK2
CLKIinputCELL1.IMUX_CLK3
CLKOPoutputCELL0.OUT_Q5
CLKOSoutputCELL0.OUT_F5
LOCKoutputCELL1.OUT_OFX1
RSTinputCELL1.IMUX_LSR0
SMIRDATAoutputCELL1.OUT_OFX4
TPFBoutputCELL0.OUT_F3
TPREFoutputCELL0.OUT_Q3

Bel PLL1

scm PLL_SE bel PLL1
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK0
CLKIinputCELL1.IMUX_CLK1
CLKOPoutputCELL0.OUT_Q0
CLKOSoutputCELL0.OUT_F0
LOCKoutputCELL1.OUT_OFX3
RSTinputCELL1.IMUX_LSR1
SMIRDATAoutputCELL1.OUT_OFX5
TPFBoutputCELL0.OUT_Q2
TPREFoutputCELL0.OUT_F2

Bel PLL_SMI

scm PLL_SE bel PLL_SMI
PinDirectionWires
SMIADDR0inputCELL0.IMUX_B5
SMIADDR1inputCELL0.IMUX_A5
SMIADDR2inputCELL0.IMUX_A6
SMIADDR3inputCELL0.IMUX_B6
SMIADDR4inputCELL0.IMUX_C6
SMIADDR5inputCELL0.IMUX_D6
SMIADDR6inputCELL0.IMUX_D7
SMIADDR7inputCELL0.IMUX_C7
SMIADDR8inputCELL0.IMUX_B7
SMIADDR9inputCELL0.IMUX_A7
SMICLKinputCELL0.IMUX_C5
SMIRDinputCELL0.IMUX_C4
SMIRSTNinputCELL0.IMUX_LSR3
SMIWDATAinputCELL0.IMUX_D4
SMIWRinputCELL0.IMUX_D5

Bel DLL0

scm PLL_SE bel DLL0
PinDirectionWires
CLKFBinputCELL0.IMUX_CLK0
CLKIinputCELL0.IMUX_CLK1
CLKOPoutputCELL1.OUT_F1
CLKOSoutputCELL1.OUT_Q1
DTCCST0inputCELL0.IMUX_A1
DTCCST1inputCELL0.IMUX_B1
LOCKoutputCELL1.OUT_Q4
RSTinputCELL1.IMUX_LSR3
SMIRDATAoutputCELL1.OUT_Q2
UDDCNTLinputCELL0.IMUX_A2

Bel DLL1

scm PLL_SE bel DLL1
PinDirectionWires
CLKFBinputCELL2.IMUX_CLK2
CLKIinputCELL3.IMUX_CLK2
CLKOPoutputCELL1.OUT_OFX0
CLKOSoutputCELL1.OUT_F0
DTCCST0inputCELL0.IMUX_C2
DTCCST1inputCELL0.IMUX_D2
LOCKoutputCELL1.OUT_Q5
RSTinputCELL0.IMUX_LSR0
SMIRDATAoutputCELL1.OUT_Q3
UDDCNTLinputCELL0.IMUX_B2

Bel DLL2

scm PLL_SE bel DLL2
PinDirectionWires
CLKFBinputCELL0.IMUX_CLK3
CLKIinputCELL0.IMUX_CLK2
CLKOPoutputCELL0.OUT_F6
CLKOSoutputCELL0.OUT_Q6
DTCCST0inputCELL0.IMUX_B3
DTCCST1inputCELL0.IMUX_A3
LOCKoutputCELL1.OUT_F4
RSTinputCELL0.IMUX_LSR1
SMIRDATAoutputCELL1.OUT_F2
UDDCNTLinputCELL0.IMUX_D3

Bel DLL3

scm PLL_SE bel DLL3
PinDirectionWires
CLKFBinputCELL5.IMUX_CLK2
CLKIinputCELL4.IMUX_CLK2
CLKOPoutputCELL0.OUT_F7
CLKOSoutputCELL0.OUT_OFX7
DTCCST0inputCELL0.IMUX_B4
DTCCST1inputCELL0.IMUX_A4
LOCKoutputCELL1.OUT_F5
RSTinputCELL0.IMUX_LSR2
SMIRDATAoutputCELL1.OUT_F3
UDDCNTLinputCELL0.IMUX_C3

Bel DLL_DCNTL0

scm PLL_SE bel DLL_DCNTL0
PinDirectionWires
DCNTL_IN0inputCELL1.IMUX_D7
DCNTL_IN1inputCELL1.IMUX_D6
DCNTL_IN2inputCELL1.IMUX_C6
DCNTL_IN3inputCELL1.IMUX_B6
DCNTL_IN4inputCELL1.IMUX_A6
DCNTL_IN5inputCELL1.IMUX_A5
DCNTL_IN6inputCELL1.IMUX_D5
DCNTL_IN7inputCELL1.IMUX_C5
DCNTL_IN8inputCELL1.IMUX_B5
DCNTL_OUT0outputCELL0.OUT_F1
DCNTL_OUT1outputCELL0.OUT_Q1
DCNTL_OUT2outputCELL0.OUT_OFX0
DCNTL_OUT3outputCELL1.OUT_OFX7
DCNTL_OUT4outputCELL1.OUT_F7
DCNTL_OUT5outputCELL1.OUT_Q7
DCNTL_OUT6outputCELL1.OUT_Q6
DCNTL_OUT7outputCELL1.OUT_F6
DCNTL_OUT8outputCELL1.OUT_OFX6

Bel DLL_DCNTL1

scm PLL_SE bel DLL_DCNTL1
PinDirectionWires
DCNTL_IN0inputCELL0.IMUX_C1
DCNTL_IN1inputCELL0.IMUX_D1
DCNTL_IN2inputCELL0.IMUX_D0
DCNTL_IN3inputCELL0.IMUX_C0
DCNTL_IN4inputCELL0.IMUX_B0
DCNTL_IN5inputCELL0.IMUX_A0
DCNTL_IN6inputCELL1.IMUX_C7
DCNTL_IN7inputCELL1.IMUX_B7
DCNTL_IN8inputCELL1.IMUX_A7
DCNTL_OUT0outputCELL0.OUT_Q7
DCNTL_OUT1outputCELL0.OUT_OFX6
DCNTL_OUT2outputCELL0.OUT_OFX5
DCNTL_OUT3outputCELL0.OUT_Q4
DCNTL_OUT4outputCELL0.OUT_F4
DCNTL_OUT5outputCELL0.OUT_OFX4
DCNTL_OUT6outputCELL0.OUT_OFX3
DCNTL_OUT7outputCELL0.OUT_OFX2
DCNTL_OUT8outputCELL0.OUT_OFX1

Bel PROMON

scm PLL_SE bel PROMON
PinDirectionWires
PROCHKinputCELL1.IMUX_B3
PROMONoutputCELL1.OUT_Q0

Bel wires

scm PLL_SE bel wires
WirePins
CELL0.IMUX_A0DLL_DCNTL1.DCNTL_IN5
CELL0.IMUX_A1DLL0.DTCCST0
CELL0.IMUX_A2DLL0.UDDCNTL
CELL0.IMUX_A3DLL2.DTCCST1
CELL0.IMUX_A4DLL3.DTCCST1
CELL0.IMUX_A5PLL_SMI.SMIADDR1
CELL0.IMUX_A6PLL_SMI.SMIADDR2
CELL0.IMUX_A7PLL_SMI.SMIADDR9
CELL0.IMUX_B0DLL_DCNTL1.DCNTL_IN4
CELL0.IMUX_B1DLL0.DTCCST1
CELL0.IMUX_B2DLL1.UDDCNTL
CELL0.IMUX_B3DLL2.DTCCST0
CELL0.IMUX_B4DLL3.DTCCST0
CELL0.IMUX_B5PLL_SMI.SMIADDR0
CELL0.IMUX_B6PLL_SMI.SMIADDR3
CELL0.IMUX_B7PLL_SMI.SMIADDR8
CELL0.IMUX_C0DLL_DCNTL1.DCNTL_IN3
CELL0.IMUX_C1DLL_DCNTL1.DCNTL_IN0
CELL0.IMUX_C2DLL1.DTCCST0
CELL0.IMUX_C3DLL3.UDDCNTL
CELL0.IMUX_C4PLL_SMI.SMIRD
CELL0.IMUX_C5PLL_SMI.SMICLK
CELL0.IMUX_C6PLL_SMI.SMIADDR4
CELL0.IMUX_C7PLL_SMI.SMIADDR7
CELL0.IMUX_D0DLL_DCNTL1.DCNTL_IN2
CELL0.IMUX_D1DLL_DCNTL1.DCNTL_IN1
CELL0.IMUX_D2DLL1.DTCCST1
CELL0.IMUX_D3DLL2.UDDCNTL
CELL0.IMUX_D4PLL_SMI.SMIWDATA
CELL0.IMUX_D5PLL_SMI.SMIWR
CELL0.IMUX_D6PLL_SMI.SMIADDR5
CELL0.IMUX_D7PLL_SMI.SMIADDR6
CELL0.IMUX_CLK0DLL0.CLKFB
CELL0.IMUX_CLK1DLL0.CLKI
CELL0.IMUX_CLK2DLL2.CLKI
CELL0.IMUX_CLK3DLL2.CLKFB
CELL0.IMUX_LSR0DLL1.RST
CELL0.IMUX_LSR1DLL2.RST
CELL0.IMUX_LSR2DLL3.RST
CELL0.IMUX_LSR3PLL_SMI.SMIRSTN
CELL0.OUT_F0PLL1.CLKOS
CELL0.OUT_F1DLL_DCNTL0.DCNTL_OUT0
CELL0.OUT_F2PLL1.TPREF
CELL0.OUT_F3PLL0.TPFB
CELL0.OUT_F4DLL_DCNTL1.DCNTL_OUT4
CELL0.OUT_F5PLL0.CLKOS
CELL0.OUT_F6DLL2.CLKOP
CELL0.OUT_F7DLL3.CLKOP
CELL0.OUT_Q0PLL1.CLKOP
CELL0.OUT_Q1DLL_DCNTL0.DCNTL_OUT1
CELL0.OUT_Q2PLL1.TPFB
CELL0.OUT_Q3PLL0.TPREF
CELL0.OUT_Q4DLL_DCNTL1.DCNTL_OUT3
CELL0.OUT_Q5PLL0.CLKOP
CELL0.OUT_Q6DLL2.CLKOS
CELL0.OUT_Q7DLL_DCNTL1.DCNTL_OUT0
CELL0.OUT_OFX0DLL_DCNTL0.DCNTL_OUT2
CELL0.OUT_OFX1DLL_DCNTL1.DCNTL_OUT8
CELL0.OUT_OFX2DLL_DCNTL1.DCNTL_OUT7
CELL0.OUT_OFX3DLL_DCNTL1.DCNTL_OUT6
CELL0.OUT_OFX4DLL_DCNTL1.DCNTL_OUT5
CELL0.OUT_OFX5DLL_DCNTL1.DCNTL_OUT2
CELL0.OUT_OFX6DLL_DCNTL1.DCNTL_OUT1
CELL0.OUT_OFX7DLL3.CLKOS
CELL1.IMUX_A5DLL_DCNTL0.DCNTL_IN5
CELL1.IMUX_A6DLL_DCNTL0.DCNTL_IN4
CELL1.IMUX_A7DLL_DCNTL1.DCNTL_IN8
CELL1.IMUX_B3PROMON.PROCHK
CELL1.IMUX_B5DLL_DCNTL0.DCNTL_IN8
CELL1.IMUX_B6DLL_DCNTL0.DCNTL_IN3
CELL1.IMUX_B7DLL_DCNTL1.DCNTL_IN7
CELL1.IMUX_C5DLL_DCNTL0.DCNTL_IN7
CELL1.IMUX_C6DLL_DCNTL0.DCNTL_IN2
CELL1.IMUX_C7DLL_DCNTL1.DCNTL_IN6
CELL1.IMUX_D5DLL_DCNTL0.DCNTL_IN6
CELL1.IMUX_D6DLL_DCNTL0.DCNTL_IN1
CELL1.IMUX_D7DLL_DCNTL0.DCNTL_IN0
CELL1.IMUX_CLK0PLL1.CLKFB
CELL1.IMUX_CLK1PLL1.CLKI
CELL1.IMUX_CLK2PLL0.CLKFB
CELL1.IMUX_CLK3PLL0.CLKI
CELL1.IMUX_LSR0PLL0.RST
CELL1.IMUX_LSR1PLL1.RST
CELL1.IMUX_LSR3DLL0.RST
CELL1.OUT_F0DLL1.CLKOS
CELL1.OUT_F1DLL0.CLKOP
CELL1.OUT_F2DLL2.SMIRDATA
CELL1.OUT_F3DLL3.SMIRDATA
CELL1.OUT_F4DLL2.LOCK
CELL1.OUT_F5DLL3.LOCK
CELL1.OUT_F6DLL_DCNTL0.DCNTL_OUT7
CELL1.OUT_F7DLL_DCNTL0.DCNTL_OUT4
CELL1.OUT_Q0PROMON.PROMON
CELL1.OUT_Q1DLL0.CLKOS
CELL1.OUT_Q2DLL0.SMIRDATA
CELL1.OUT_Q3DLL1.SMIRDATA
CELL1.OUT_Q4DLL0.LOCK
CELL1.OUT_Q5DLL1.LOCK
CELL1.OUT_Q6DLL_DCNTL0.DCNTL_OUT6
CELL1.OUT_Q7DLL_DCNTL0.DCNTL_OUT5
CELL1.OUT_OFX0DLL1.CLKOP
CELL1.OUT_OFX1PLL0.LOCK
CELL1.OUT_OFX3PLL1.LOCK
CELL1.OUT_OFX4PLL0.SMIRDATA
CELL1.OUT_OFX5PLL1.SMIRDATA
CELL1.OUT_OFX6DLL_DCNTL0.DCNTL_OUT8
CELL1.OUT_OFX7DLL_DCNTL0.DCNTL_OUT3
CELL2.IMUX_CLK2DLL1.CLKFB
CELL3.IMUX_CLK2DLL1.CLKI
CELL4.IMUX_CLK2DLL3.CLKI
CELL5.IMUX_CLK2DLL3.CLKFB

Tile PLL_NW

Cells: 3

Bel SERDES_CORNER

scm PLL_NW bel SERDES_CORNER
PinDirectionWires
CIN_0inputCELL2.IO_W0_1
CIN_1inputCELL2.IO_W1_1
CIN_10inputCELL2.IO_W10_1
CIN_11inputCELL2.IO_W11_1
CIN_12inputCELL2.IO_W12_1
CIN_2inputCELL2.IO_W2_1
CIN_3inputCELL2.IO_W3_1
CIN_4inputCELL2.IO_W4_1
CIN_5inputCELL2.IO_W5_1
CIN_6inputCELL2.IO_W6_1
CIN_7inputCELL2.IO_W7_1
CIN_8inputCELL2.IO_W8_1
CIN_9inputCELL2.IO_W9_1
COUT_0outputCELL2.IO_E0_2
COUT_1outputCELL2.IO_E1_2
COUT_10outputCELL2.IO_E13_2
COUT_11outputCELL2.IO_E14_2
COUT_12outputCELL2.IO_E15_2
COUT_13outputCELL2.IO_E16_2
COUT_14outputCELL2.IO_E17_2
COUT_15outputCELL2.IO_E18_2
COUT_16outputCELL2.IO_E19_2
COUT_17outputCELL2.IO_E20_2
COUT_18outputCELL2.IO_E21_2
COUT_19outputCELL2.IO_E22_2
COUT_2outputCELL2.IO_E2_2
COUT_20outputCELL2.IO_E23_2
COUT_21outputCELL2.IO_E24_2
COUT_3outputCELL2.IO_E3_2
COUT_4outputCELL2.IO_E4_2
COUT_5outputCELL2.IO_E5_2
COUT_6outputCELL2.IO_E9_2
COUT_7outputCELL2.IO_E10_2
COUT_8outputCELL2.IO_E11_2
COUT_9outputCELL2.IO_E12_2
SERDES0_BS4PAD_0outputCELL2.IO_E25_2
SERDES0_BS4PAD_1outputCELL2.IO_E26_2
SERDES0_BS4PAD_2outputCELL2.IO_E27_2
SERDES0_BS4PAD_3outputCELL2.IO_E28_2
SERDES1_BS4PAD_0outputCELL2.IO_E29_2
SERDES1_BS4PAD_1outputCELL2.IO_E30_2
SERDES1_BS4PAD_2outputCELL2.IO_E31_2
SERDES1_BS4PAD_3outputCELL2.IO_E0_3
SERDES2_BS4PAD_0outputCELL2.IO_E1_3
SERDES2_BS4PAD_1outputCELL2.IO_E2_3
SERDES2_BS4PAD_2outputCELL2.IO_E3_3
SERDES2_BS4PAD_3outputCELL2.IO_E4_3
SERDES3_BS4PAD_0outputCELL2.IO_E5_3
SERDES3_BS4PAD_1outputCELL2.IO_E9_3
SERDES3_BS4PAD_2outputCELL2.IO_E10_3
SERDES3_BS4PAD_3outputCELL2.IO_E11_3
TCK_FMAC_PCSoutputCELL2.IO_E7_2
TESTCLK_MACOinputCELL2.IO_W14_1

Bel PLL0

scm PLL_NW bel PLL0
PinDirectionWires
CLKFBinputCELL0.IMUX_CLK1
CLKIinputCELL0.IMUX_CLK0
CLKOPoutputCELL0.OUT_F1
CLKOSoutputCELL0.OUT_F0
LOCKoutputCELL0.OUT_Q3
RSTinputCELL0.IMUX_LSR0
SMIRDATAoutputCELL0.OUT_OFX1
TPFBoutputCELL0.OUT_Q5
TPREFoutputCELL0.OUT_Q4

Bel PLL1

scm PLL_NW bel PLL1
PinDirectionWires
CLKFBinputCELL0.IMUX_CLK3
CLKIinputCELL0.IMUX_CLK2
CLKOPoutputCELL0.OUT_F3
CLKOSoutputCELL0.OUT_F2
LOCKoutputCELL0.OUT_Q2
RSTinputCELL0.IMUX_LSR1
SMIRDATAoutputCELL0.OUT_OFX0
TPFBoutputCELL0.OUT_Q7
TPREFoutputCELL0.OUT_Q6

Bel PLL_SMI

scm PLL_NW bel PLL_SMI
PinDirectionWires
SMIADDR0inputCELL0.IMUX_A1
SMIADDR1inputCELL0.IMUX_A2
SMIADDR2inputCELL0.IMUX_A3
SMIADDR3inputCELL0.IMUX_A4
SMIADDR4inputCELL0.IMUX_A5
SMIADDR5inputCELL0.IMUX_A6
SMIADDR6inputCELL0.IMUX_A7
SMIADDR7inputCELL0.IMUX_B0
SMIADDR8inputCELL0.IMUX_B1
SMIADDR9inputCELL0.IMUX_B2
SMICLKinputCELL0.IMUX_B3
SMIRDinputCELL0.IMUX_B4
SMIRSTNinputCELL1.IMUX_LSR0
SMIWDATAinputCELL0.IMUX_B6
SMIWRinputCELL0.IMUX_B7

Bel DLL0

scm PLL_NW bel DLL0
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK1
CLKIinputCELL1.IMUX_CLK0
CLKOPoutputCELL0.OUT_F4
CLKOSoutputCELL0.OUT_F5
DTCCST0inputCELL0.IMUX_C2
DTCCST1inputCELL0.IMUX_C3
LOCKoutputCELL0.OUT_Q1
RSTinputCELL0.IMUX_LSR2
SMIRDATAoutputCELL0.OUT_OFX3
UDDCNTLinputCELL0.IMUX_C0

Bel DLL1

scm PLL_NW bel DLL1
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK3
CLKIinputCELL1.IMUX_CLK2
CLKOPoutputCELL0.OUT_F6
CLKOSoutputCELL0.OUT_F7
DTCCST0inputCELL0.IMUX_C4
DTCCST1inputCELL0.IMUX_C5
LOCKoutputCELL0.OUT_Q0
RSTinputCELL0.IMUX_LSR3
SMIRDATAoutputCELL0.OUT_OFX2
UDDCNTLinputCELL0.IMUX_C1

Bel DLL_DCNTL0

scm PLL_NW bel DLL_DCNTL0
PinDirectionWires
DCNTL_IN0inputCELL1.IMUX_A0
DCNTL_IN1inputCELL1.IMUX_A1
DCNTL_IN2inputCELL1.IMUX_A2
DCNTL_IN3inputCELL1.IMUX_A3
DCNTL_IN4inputCELL1.IMUX_A4
DCNTL_IN5inputCELL1.IMUX_A5
DCNTL_IN6inputCELL1.IMUX_A6
DCNTL_IN7inputCELL1.IMUX_A7
DCNTL_IN8inputCELL1.IMUX_B0
DCNTL_OUT0outputCELL1.OUT_F6
DCNTL_OUT1outputCELL1.OUT_F7
DCNTL_OUT2outputCELL1.OUT_Q0
DCNTL_OUT3outputCELL1.OUT_Q1
DCNTL_OUT4outputCELL1.OUT_Q2
DCNTL_OUT5outputCELL1.OUT_Q3
DCNTL_OUT6outputCELL1.OUT_Q4
DCNTL_OUT7outputCELL1.OUT_Q5
DCNTL_OUT8outputCELL1.OUT_Q6

Bel DLL_DCNTL1

scm PLL_NW bel DLL_DCNTL1
PinDirectionWires
DCNTL_IN0inputCELL1.IMUX_B1
DCNTL_IN1inputCELL1.IMUX_B2
DCNTL_IN2inputCELL1.IMUX_B3
DCNTL_IN3inputCELL1.IMUX_B4
DCNTL_IN4inputCELL1.IMUX_B5
DCNTL_IN5inputCELL1.IMUX_B6
DCNTL_IN6inputCELL1.IMUX_B7
DCNTL_IN7inputCELL1.IMUX_C0
DCNTL_IN8inputCELL1.IMUX_C1
DCNTL_OUT0outputCELL1.OUT_Q7
DCNTL_OUT1outputCELL1.OUT_OFX0
DCNTL_OUT2outputCELL1.OUT_OFX1
DCNTL_OUT3outputCELL1.OUT_OFX2
DCNTL_OUT4outputCELL1.OUT_OFX3
DCNTL_OUT5outputCELL1.OUT_OFX4
DCNTL_OUT6outputCELL1.OUT_OFX5
DCNTL_OUT7outputCELL1.OUT_OFX6
DCNTL_OUT8outputCELL1.OUT_OFX7

Bel M0

scm PLL_NW bel M0
PinDirectionWires
M0outputCELL1.OUT_F2

Bel M1

scm PLL_NW bel M1
PinDirectionWires
M1outputCELL1.OUT_F3

Bel M2

scm PLL_NW bel M2
PinDirectionWires
M2outputCELL1.OUT_F4

Bel M3

scm PLL_NW bel M3
PinDirectionWires
M3outputCELL1.OUT_F5

Bel RESETN

scm PLL_NW bel RESETN
PinDirectionWires
RSTNoutputCELL1.OUT_F0

Bel RDCFGN

scm PLL_NW bel RDCFGN
PinDirectionWires
RDCFGNoutputCELL1.OUT_F1
TSALLNinputCELL0.IMUX_CE0

Bel wires

scm PLL_NW bel wires
WirePins
CELL0.IMUX_A1PLL_SMI.SMIADDR0
CELL0.IMUX_A2PLL_SMI.SMIADDR1
CELL0.IMUX_A3PLL_SMI.SMIADDR2
CELL0.IMUX_A4PLL_SMI.SMIADDR3
CELL0.IMUX_A5PLL_SMI.SMIADDR4
CELL0.IMUX_A6PLL_SMI.SMIADDR5
CELL0.IMUX_A7PLL_SMI.SMIADDR6
CELL0.IMUX_B0PLL_SMI.SMIADDR7
CELL0.IMUX_B1PLL_SMI.SMIADDR8
CELL0.IMUX_B2PLL_SMI.SMIADDR9
CELL0.IMUX_B3PLL_SMI.SMICLK
CELL0.IMUX_B4PLL_SMI.SMIRD
CELL0.IMUX_B6PLL_SMI.SMIWDATA
CELL0.IMUX_B7PLL_SMI.SMIWR
CELL0.IMUX_C0DLL0.UDDCNTL
CELL0.IMUX_C1DLL1.UDDCNTL
CELL0.IMUX_C2DLL0.DTCCST0
CELL0.IMUX_C3DLL0.DTCCST1
CELL0.IMUX_C4DLL1.DTCCST0
CELL0.IMUX_C5DLL1.DTCCST1
CELL0.IMUX_CLK0PLL0.CLKI
CELL0.IMUX_CLK1PLL0.CLKFB
CELL0.IMUX_CLK2PLL1.CLKI
CELL0.IMUX_CLK3PLL1.CLKFB
CELL0.IMUX_LSR0PLL0.RST
CELL0.IMUX_LSR1PLL1.RST
CELL0.IMUX_LSR2DLL0.RST
CELL0.IMUX_LSR3DLL1.RST
CELL0.IMUX_CE0RDCFGN.TSALLN
CELL0.OUT_F0PLL0.CLKOS
CELL0.OUT_F1PLL0.CLKOP
CELL0.OUT_F2PLL1.CLKOS
CELL0.OUT_F3PLL1.CLKOP
CELL0.OUT_F4DLL0.CLKOP
CELL0.OUT_F5DLL0.CLKOS
CELL0.OUT_F6DLL1.CLKOP
CELL0.OUT_F7DLL1.CLKOS
CELL0.OUT_Q0DLL1.LOCK
CELL0.OUT_Q1DLL0.LOCK
CELL0.OUT_Q2PLL1.LOCK
CELL0.OUT_Q3PLL0.LOCK
CELL0.OUT_Q4PLL0.TPREF
CELL0.OUT_Q5PLL0.TPFB
CELL0.OUT_Q6PLL1.TPREF
CELL0.OUT_Q7PLL1.TPFB
CELL0.OUT_OFX0PLL1.SMIRDATA
CELL0.OUT_OFX1PLL0.SMIRDATA
CELL0.OUT_OFX2DLL1.SMIRDATA
CELL0.OUT_OFX3DLL0.SMIRDATA
CELL1.IMUX_A0DLL_DCNTL0.DCNTL_IN0
CELL1.IMUX_A1DLL_DCNTL0.DCNTL_IN1
CELL1.IMUX_A2DLL_DCNTL0.DCNTL_IN2
CELL1.IMUX_A3DLL_DCNTL0.DCNTL_IN3
CELL1.IMUX_A4DLL_DCNTL0.DCNTL_IN4
CELL1.IMUX_A5DLL_DCNTL0.DCNTL_IN5
CELL1.IMUX_A6DLL_DCNTL0.DCNTL_IN6
CELL1.IMUX_A7DLL_DCNTL0.DCNTL_IN7
CELL1.IMUX_B0DLL_DCNTL0.DCNTL_IN8
CELL1.IMUX_B1DLL_DCNTL1.DCNTL_IN0
CELL1.IMUX_B2DLL_DCNTL1.DCNTL_IN1
CELL1.IMUX_B3DLL_DCNTL1.DCNTL_IN2
CELL1.IMUX_B4DLL_DCNTL1.DCNTL_IN3
CELL1.IMUX_B5DLL_DCNTL1.DCNTL_IN4
CELL1.IMUX_B6DLL_DCNTL1.DCNTL_IN5
CELL1.IMUX_B7DLL_DCNTL1.DCNTL_IN6
CELL1.IMUX_C0DLL_DCNTL1.DCNTL_IN7
CELL1.IMUX_C1DLL_DCNTL1.DCNTL_IN8
CELL1.IMUX_CLK0DLL0.CLKI
CELL1.IMUX_CLK1DLL0.CLKFB
CELL1.IMUX_CLK2DLL1.CLKI
CELL1.IMUX_CLK3DLL1.CLKFB
CELL1.IMUX_LSR0PLL_SMI.SMIRSTN
CELL1.OUT_F0RESETN.RSTN
CELL1.OUT_F1RDCFGN.RDCFGN
CELL1.OUT_F2M0.M0
CELL1.OUT_F3M1.M1
CELL1.OUT_F4M2.M2
CELL1.OUT_F5M3.M3
CELL1.OUT_F6DLL_DCNTL0.DCNTL_OUT0
CELL1.OUT_F7DLL_DCNTL0.DCNTL_OUT1
CELL1.OUT_Q0DLL_DCNTL0.DCNTL_OUT2
CELL1.OUT_Q1DLL_DCNTL0.DCNTL_OUT3
CELL1.OUT_Q2DLL_DCNTL0.DCNTL_OUT4
CELL1.OUT_Q3DLL_DCNTL0.DCNTL_OUT5
CELL1.OUT_Q4DLL_DCNTL0.DCNTL_OUT6
CELL1.OUT_Q5DLL_DCNTL0.DCNTL_OUT7
CELL1.OUT_Q6DLL_DCNTL0.DCNTL_OUT8
CELL1.OUT_Q7DLL_DCNTL1.DCNTL_OUT0
CELL1.OUT_OFX0DLL_DCNTL1.DCNTL_OUT1
CELL1.OUT_OFX1DLL_DCNTL1.DCNTL_OUT2
CELL1.OUT_OFX2DLL_DCNTL1.DCNTL_OUT3
CELL1.OUT_OFX3DLL_DCNTL1.DCNTL_OUT4
CELL1.OUT_OFX4DLL_DCNTL1.DCNTL_OUT5
CELL1.OUT_OFX5DLL_DCNTL1.DCNTL_OUT6
CELL1.OUT_OFX6DLL_DCNTL1.DCNTL_OUT7
CELL1.OUT_OFX7DLL_DCNTL1.DCNTL_OUT8
CELL2.IO_W0_1SERDES_CORNER.CIN_0
CELL2.IO_W1_1SERDES_CORNER.CIN_1
CELL2.IO_W2_1SERDES_CORNER.CIN_2
CELL2.IO_W3_1SERDES_CORNER.CIN_3
CELL2.IO_W4_1SERDES_CORNER.CIN_4
CELL2.IO_W5_1SERDES_CORNER.CIN_5
CELL2.IO_W6_1SERDES_CORNER.CIN_6
CELL2.IO_W7_1SERDES_CORNER.CIN_7
CELL2.IO_W8_1SERDES_CORNER.CIN_8
CELL2.IO_W9_1SERDES_CORNER.CIN_9
CELL2.IO_W10_1SERDES_CORNER.CIN_10
CELL2.IO_W11_1SERDES_CORNER.CIN_11
CELL2.IO_W12_1SERDES_CORNER.CIN_12
CELL2.IO_W14_1SERDES_CORNER.TESTCLK_MACO
CELL2.IO_E0_2SERDES_CORNER.COUT_0
CELL2.IO_E0_3SERDES_CORNER.SERDES1_BS4PAD_3
CELL2.IO_E1_2SERDES_CORNER.COUT_1
CELL2.IO_E1_3SERDES_CORNER.SERDES2_BS4PAD_0
CELL2.IO_E2_2SERDES_CORNER.COUT_2
CELL2.IO_E2_3SERDES_CORNER.SERDES2_BS4PAD_1
CELL2.IO_E3_2SERDES_CORNER.COUT_3
CELL2.IO_E3_3SERDES_CORNER.SERDES2_BS4PAD_2
CELL2.IO_E4_2SERDES_CORNER.COUT_4
CELL2.IO_E4_3SERDES_CORNER.SERDES2_BS4PAD_3
CELL2.IO_E5_2SERDES_CORNER.COUT_5
CELL2.IO_E5_3SERDES_CORNER.SERDES3_BS4PAD_0
CELL2.IO_E7_2SERDES_CORNER.TCK_FMAC_PCS
CELL2.IO_E9_2SERDES_CORNER.COUT_6
CELL2.IO_E9_3SERDES_CORNER.SERDES3_BS4PAD_1
CELL2.IO_E10_2SERDES_CORNER.COUT_7
CELL2.IO_E10_3SERDES_CORNER.SERDES3_BS4PAD_2
CELL2.IO_E11_2SERDES_CORNER.COUT_8
CELL2.IO_E11_3SERDES_CORNER.SERDES3_BS4PAD_3
CELL2.IO_E12_2SERDES_CORNER.COUT_9
CELL2.IO_E13_2SERDES_CORNER.COUT_10
CELL2.IO_E14_2SERDES_CORNER.COUT_11
CELL2.IO_E15_2SERDES_CORNER.COUT_12
CELL2.IO_E16_2SERDES_CORNER.COUT_13
CELL2.IO_E17_2SERDES_CORNER.COUT_14
CELL2.IO_E18_2SERDES_CORNER.COUT_15
CELL2.IO_E19_2SERDES_CORNER.COUT_16
CELL2.IO_E20_2SERDES_CORNER.COUT_17
CELL2.IO_E21_2SERDES_CORNER.COUT_18
CELL2.IO_E22_2SERDES_CORNER.COUT_19
CELL2.IO_E23_2SERDES_CORNER.COUT_20
CELL2.IO_E24_2SERDES_CORNER.COUT_21
CELL2.IO_E25_2SERDES_CORNER.SERDES0_BS4PAD_0
CELL2.IO_E26_2SERDES_CORNER.SERDES0_BS4PAD_1
CELL2.IO_E27_2SERDES_CORNER.SERDES0_BS4PAD_2
CELL2.IO_E28_2SERDES_CORNER.SERDES0_BS4PAD_3
CELL2.IO_E29_2SERDES_CORNER.SERDES1_BS4PAD_0
CELL2.IO_E30_2SERDES_CORNER.SERDES1_BS4PAD_1
CELL2.IO_E31_2SERDES_CORNER.SERDES1_BS4PAD_2

Tile PLL_NE

Cells: 3

Bel SERDES_CORNER

scm PLL_NE bel SERDES_CORNER
PinDirectionWires
CIN_0inputCELL2.IO_E0_1
CIN_1inputCELL2.IO_E1_1
CIN_10inputCELL2.IO_E10_1
CIN_11inputCELL2.IO_E11_1
CIN_12inputCELL2.IO_E12_1
CIN_2inputCELL2.IO_E2_1
CIN_3inputCELL2.IO_E3_1
CIN_4inputCELL2.IO_E4_1
CIN_5inputCELL2.IO_E5_1
CIN_6inputCELL2.IO_E6_1
CIN_7inputCELL2.IO_E7_1
CIN_8inputCELL2.IO_E8_1
CIN_9inputCELL2.IO_E9_1
COUT_0outputCELL2.IO_W0_2
COUT_1outputCELL2.IO_W1_2
COUT_10outputCELL2.IO_W13_2
COUT_11outputCELL2.IO_W14_2
COUT_12outputCELL2.IO_W15_2
COUT_13outputCELL2.IO_W16_2
COUT_14outputCELL2.IO_W17_2
COUT_15outputCELL2.IO_W18_2
COUT_16outputCELL2.IO_W19_2
COUT_17outputCELL2.IO_W20_2
COUT_18outputCELL2.IO_W21_2
COUT_19outputCELL2.IO_W22_2
COUT_2outputCELL2.IO_W2_2
COUT_20outputCELL2.IO_W23_2
COUT_21outputCELL2.IO_W24_2
COUT_3outputCELL2.IO_W3_2
COUT_4outputCELL2.IO_W4_2
COUT_5outputCELL2.IO_W5_2
COUT_6outputCELL2.IO_W9_2
COUT_7outputCELL2.IO_W10_2
COUT_8outputCELL2.IO_W11_2
COUT_9outputCELL2.IO_W12_2
SERDES0_BS4PAD_0outputCELL2.IO_W25_2
SERDES0_BS4PAD_1outputCELL2.IO_W26_2
SERDES0_BS4PAD_2outputCELL2.IO_W27_2
SERDES0_BS4PAD_3outputCELL2.IO_W28_2
SERDES1_BS4PAD_0outputCELL2.IO_W29_2
SERDES1_BS4PAD_1outputCELL2.IO_W30_2
SERDES1_BS4PAD_2outputCELL2.IO_W31_2
SERDES1_BS4PAD_3outputCELL2.IO_W0_3
SERDES2_BS4PAD_0outputCELL2.IO_W1_3
SERDES2_BS4PAD_1outputCELL2.IO_W2_3
SERDES2_BS4PAD_2outputCELL2.IO_W3_3
SERDES2_BS4PAD_3outputCELL2.IO_W4_3
SERDES3_BS4PAD_0outputCELL2.IO_W5_3
SERDES3_BS4PAD_1outputCELL2.IO_W9_3
SERDES3_BS4PAD_2outputCELL2.IO_W10_3
SERDES3_BS4PAD_3outputCELL2.IO_W11_3
TCK_FMAC_PCSoutputCELL2.IO_W7_2
TESTCLK_MACOinputCELL2.IO_E14_1

Bel PLL0

scm PLL_NE bel PLL0
PinDirectionWires
CLKFBinputCELL0.IMUX_CLK2
CLKIinputCELL0.IMUX_CLK3
CLKOPoutputCELL0.OUT_F6
CLKOSoutputCELL0.OUT_F7
LOCKoutputCELL0.OUT_Q4
RSTinputCELL0.IMUX_LSR3
SMIRDATAoutputCELL0.OUT_OFX6
TPFBoutputCELL0.OUT_Q2
TPREFoutputCELL0.OUT_Q3

Bel PLL1

scm PLL_NE bel PLL1
PinDirectionWires
CLKFBinputCELL0.IMUX_CLK0
CLKIinputCELL0.IMUX_CLK1
CLKOPoutputCELL0.OUT_F4
CLKOSoutputCELL0.OUT_F5
LOCKoutputCELL0.OUT_Q5
RSTinputCELL0.IMUX_LSR2
SMIRDATAoutputCELL0.OUT_OFX7
TPFBoutputCELL0.OUT_Q0
TPREFoutputCELL0.OUT_Q1

Bel PLL_SMI

scm PLL_NE bel PLL_SMI
PinDirectionWires
SMIADDR0inputCELL0.IMUX_A6
SMIADDR1inputCELL0.IMUX_A5
SMIADDR2inputCELL0.IMUX_A4
SMIADDR3inputCELL0.IMUX_A3
SMIADDR4inputCELL0.IMUX_A2
SMIADDR5inputCELL0.IMUX_A1
SMIADDR6inputCELL0.IMUX_A0
SMIADDR7inputCELL0.IMUX_B7
SMIADDR8inputCELL0.IMUX_B6
SMIADDR9inputCELL0.IMUX_B5
SMICLKinputCELL0.IMUX_B4
SMIRDinputCELL0.IMUX_B3
SMIRSTNinputCELL1.IMUX_LSR3
SMIWDATAinputCELL0.IMUX_B1
SMIWRinputCELL0.IMUX_B0

Bel DLL0

scm PLL_NE bel DLL0
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK2
CLKIinputCELL1.IMUX_CLK3
CLKOPoutputCELL0.OUT_F3
CLKOSoutputCELL0.OUT_F2
DTCCST0inputCELL0.IMUX_C5
DTCCST1inputCELL0.IMUX_C4
LOCKoutputCELL0.OUT_Q6
RSTinputCELL0.IMUX_LSR1
SMIRDATAoutputCELL0.OUT_OFX4
UDDCNTLinputCELL0.IMUX_C7

Bel DLL1

scm PLL_NE bel DLL1
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK0
CLKIinputCELL1.IMUX_CLK1
CLKOPoutputCELL0.OUT_F1
CLKOSoutputCELL0.OUT_F0
DTCCST0inputCELL0.IMUX_C3
DTCCST1inputCELL0.IMUX_C2
LOCKoutputCELL0.OUT_Q7
RSTinputCELL0.IMUX_LSR0
SMIRDATAoutputCELL0.OUT_OFX5
UDDCNTLinputCELL0.IMUX_C6

Bel DLL_DCNTL0

scm PLL_NE bel DLL_DCNTL0
PinDirectionWires
DCNTL_IN0inputCELL1.IMUX_A7
DCNTL_IN1inputCELL1.IMUX_A6
DCNTL_IN2inputCELL1.IMUX_A5
DCNTL_IN3inputCELL1.IMUX_A4
DCNTL_IN4inputCELL1.IMUX_A3
DCNTL_IN5inputCELL1.IMUX_A2
DCNTL_IN6inputCELL1.IMUX_A1
DCNTL_IN7inputCELL1.IMUX_A0
DCNTL_IN8inputCELL1.IMUX_B7
DCNTL_OUT0outputCELL1.OUT_F1
DCNTL_OUT1outputCELL1.OUT_F0
DCNTL_OUT2outputCELL1.OUT_Q7
DCNTL_OUT3outputCELL1.OUT_Q6
DCNTL_OUT4outputCELL1.OUT_Q5
DCNTL_OUT5outputCELL1.OUT_Q4
DCNTL_OUT6outputCELL1.OUT_Q3
DCNTL_OUT7outputCELL1.OUT_Q2
DCNTL_OUT8outputCELL1.OUT_Q1

Bel DLL_DCNTL1

scm PLL_NE bel DLL_DCNTL1
PinDirectionWires
DCNTL_IN0inputCELL1.IMUX_B6
DCNTL_IN1inputCELL1.IMUX_B5
DCNTL_IN2inputCELL1.IMUX_B4
DCNTL_IN3inputCELL1.IMUX_B3
DCNTL_IN4inputCELL1.IMUX_B2
DCNTL_IN5inputCELL1.IMUX_B1
DCNTL_IN6inputCELL1.IMUX_B0
DCNTL_IN7inputCELL1.IMUX_C7
DCNTL_IN8inputCELL1.IMUX_C6
DCNTL_OUT0outputCELL1.OUT_Q0
DCNTL_OUT1outputCELL1.OUT_OFX7
DCNTL_OUT2outputCELL1.OUT_OFX6
DCNTL_OUT3outputCELL1.OUT_OFX5
DCNTL_OUT4outputCELL1.OUT_OFX4
DCNTL_OUT5outputCELL1.OUT_OFX3
DCNTL_OUT6outputCELL1.OUT_OFX2
DCNTL_OUT7outputCELL1.OUT_OFX1
DCNTL_OUT8outputCELL1.OUT_OFX0

Bel CCLK

scm PLL_NE bel CCLK
PinDirectionWires
CCLKoutputCELL1.OUT_F7

Bel TCK

scm PLL_NE bel TCK
PinDirectionWires
TCKoutputCELL1.OUT_F6

Bel TMS

scm PLL_NE bel TMS
PinDirectionWires
TMSoutputCELL1.OUT_F4

Bel TDI

scm PLL_NE bel TDI
PinDirectionWires
TDIoutputCELL1.OUT_F5

Bel wires

scm PLL_NE bel wires
WirePins
CELL0.IMUX_A0PLL_SMI.SMIADDR6
CELL0.IMUX_A1PLL_SMI.SMIADDR5
CELL0.IMUX_A2PLL_SMI.SMIADDR4
CELL0.IMUX_A3PLL_SMI.SMIADDR3
CELL0.IMUX_A4PLL_SMI.SMIADDR2
CELL0.IMUX_A5PLL_SMI.SMIADDR1
CELL0.IMUX_A6PLL_SMI.SMIADDR0
CELL0.IMUX_B0PLL_SMI.SMIWR
CELL0.IMUX_B1PLL_SMI.SMIWDATA
CELL0.IMUX_B3PLL_SMI.SMIRD
CELL0.IMUX_B4PLL_SMI.SMICLK
CELL0.IMUX_B5PLL_SMI.SMIADDR9
CELL0.IMUX_B6PLL_SMI.SMIADDR8
CELL0.IMUX_B7PLL_SMI.SMIADDR7
CELL0.IMUX_C2DLL1.DTCCST1
CELL0.IMUX_C3DLL1.DTCCST0
CELL0.IMUX_C4DLL0.DTCCST1
CELL0.IMUX_C5DLL0.DTCCST0
CELL0.IMUX_C6DLL1.UDDCNTL
CELL0.IMUX_C7DLL0.UDDCNTL
CELL0.IMUX_CLK0PLL1.CLKFB
CELL0.IMUX_CLK1PLL1.CLKI
CELL0.IMUX_CLK2PLL0.CLKFB
CELL0.IMUX_CLK3PLL0.CLKI
CELL0.IMUX_LSR0DLL1.RST
CELL0.IMUX_LSR1DLL0.RST
CELL0.IMUX_LSR2PLL1.RST
CELL0.IMUX_LSR3PLL0.RST
CELL0.OUT_F0DLL1.CLKOS
CELL0.OUT_F1DLL1.CLKOP
CELL0.OUT_F2DLL0.CLKOS
CELL0.OUT_F3DLL0.CLKOP
CELL0.OUT_F4PLL1.CLKOP
CELL0.OUT_F5PLL1.CLKOS
CELL0.OUT_F6PLL0.CLKOP
CELL0.OUT_F7PLL0.CLKOS
CELL0.OUT_Q0PLL1.TPFB
CELL0.OUT_Q1PLL1.TPREF
CELL0.OUT_Q2PLL0.TPFB
CELL0.OUT_Q3PLL0.TPREF
CELL0.OUT_Q4PLL0.LOCK
CELL0.OUT_Q5PLL1.LOCK
CELL0.OUT_Q6DLL0.LOCK
CELL0.OUT_Q7DLL1.LOCK
CELL0.OUT_OFX4DLL0.SMIRDATA
CELL0.OUT_OFX5DLL1.SMIRDATA
CELL0.OUT_OFX6PLL0.SMIRDATA
CELL0.OUT_OFX7PLL1.SMIRDATA
CELL1.IMUX_A0DLL_DCNTL0.DCNTL_IN7
CELL1.IMUX_A1DLL_DCNTL0.DCNTL_IN6
CELL1.IMUX_A2DLL_DCNTL0.DCNTL_IN5
CELL1.IMUX_A3DLL_DCNTL0.DCNTL_IN4
CELL1.IMUX_A4DLL_DCNTL0.DCNTL_IN3
CELL1.IMUX_A5DLL_DCNTL0.DCNTL_IN2
CELL1.IMUX_A6DLL_DCNTL0.DCNTL_IN1
CELL1.IMUX_A7DLL_DCNTL0.DCNTL_IN0
CELL1.IMUX_B0DLL_DCNTL1.DCNTL_IN6
CELL1.IMUX_B1DLL_DCNTL1.DCNTL_IN5
CELL1.IMUX_B2DLL_DCNTL1.DCNTL_IN4
CELL1.IMUX_B3DLL_DCNTL1.DCNTL_IN3
CELL1.IMUX_B4DLL_DCNTL1.DCNTL_IN2
CELL1.IMUX_B5DLL_DCNTL1.DCNTL_IN1
CELL1.IMUX_B6DLL_DCNTL1.DCNTL_IN0
CELL1.IMUX_B7DLL_DCNTL0.DCNTL_IN8
CELL1.IMUX_C6DLL_DCNTL1.DCNTL_IN8
CELL1.IMUX_C7DLL_DCNTL1.DCNTL_IN7
CELL1.IMUX_CLK0DLL1.CLKFB
CELL1.IMUX_CLK1DLL1.CLKI
CELL1.IMUX_CLK2DLL0.CLKFB
CELL1.IMUX_CLK3DLL0.CLKI
CELL1.IMUX_LSR3PLL_SMI.SMIRSTN
CELL1.OUT_F0DLL_DCNTL0.DCNTL_OUT1
CELL1.OUT_F1DLL_DCNTL0.DCNTL_OUT0
CELL1.OUT_F4TMS.TMS
CELL1.OUT_F5TDI.TDI
CELL1.OUT_F6TCK.TCK
CELL1.OUT_F7CCLK.CCLK
CELL1.OUT_Q0DLL_DCNTL1.DCNTL_OUT0
CELL1.OUT_Q1DLL_DCNTL0.DCNTL_OUT8
CELL1.OUT_Q2DLL_DCNTL0.DCNTL_OUT7
CELL1.OUT_Q3DLL_DCNTL0.DCNTL_OUT6
CELL1.OUT_Q4DLL_DCNTL0.DCNTL_OUT5
CELL1.OUT_Q5DLL_DCNTL0.DCNTL_OUT4
CELL1.OUT_Q6DLL_DCNTL0.DCNTL_OUT3
CELL1.OUT_Q7DLL_DCNTL0.DCNTL_OUT2
CELL1.OUT_OFX0DLL_DCNTL1.DCNTL_OUT8
CELL1.OUT_OFX1DLL_DCNTL1.DCNTL_OUT7
CELL1.OUT_OFX2DLL_DCNTL1.DCNTL_OUT6
CELL1.OUT_OFX3DLL_DCNTL1.DCNTL_OUT5
CELL1.OUT_OFX4DLL_DCNTL1.DCNTL_OUT4
CELL1.OUT_OFX5DLL_DCNTL1.DCNTL_OUT3
CELL1.OUT_OFX6DLL_DCNTL1.DCNTL_OUT2
CELL1.OUT_OFX7DLL_DCNTL1.DCNTL_OUT1
CELL2.IO_W0_2SERDES_CORNER.COUT_0
CELL2.IO_W0_3SERDES_CORNER.SERDES1_BS4PAD_3
CELL2.IO_W1_2SERDES_CORNER.COUT_1
CELL2.IO_W1_3SERDES_CORNER.SERDES2_BS4PAD_0
CELL2.IO_W2_2SERDES_CORNER.COUT_2
CELL2.IO_W2_3SERDES_CORNER.SERDES2_BS4PAD_1
CELL2.IO_W3_2SERDES_CORNER.COUT_3
CELL2.IO_W3_3SERDES_CORNER.SERDES2_BS4PAD_2
CELL2.IO_W4_2SERDES_CORNER.COUT_4
CELL2.IO_W4_3SERDES_CORNER.SERDES2_BS4PAD_3
CELL2.IO_W5_2SERDES_CORNER.COUT_5
CELL2.IO_W5_3SERDES_CORNER.SERDES3_BS4PAD_0
CELL2.IO_W7_2SERDES_CORNER.TCK_FMAC_PCS
CELL2.IO_W9_2SERDES_CORNER.COUT_6
CELL2.IO_W9_3SERDES_CORNER.SERDES3_BS4PAD_1
CELL2.IO_W10_2SERDES_CORNER.COUT_7
CELL2.IO_W10_3SERDES_CORNER.SERDES3_BS4PAD_2
CELL2.IO_W11_2SERDES_CORNER.COUT_8
CELL2.IO_W11_3SERDES_CORNER.SERDES3_BS4PAD_3
CELL2.IO_W12_2SERDES_CORNER.COUT_9
CELL2.IO_W13_2SERDES_CORNER.COUT_10
CELL2.IO_W14_2SERDES_CORNER.COUT_11
CELL2.IO_W15_2SERDES_CORNER.COUT_12
CELL2.IO_W16_2SERDES_CORNER.COUT_13
CELL2.IO_W17_2SERDES_CORNER.COUT_14
CELL2.IO_W18_2SERDES_CORNER.COUT_15
CELL2.IO_W19_2SERDES_CORNER.COUT_16
CELL2.IO_W20_2SERDES_CORNER.COUT_17
CELL2.IO_W21_2SERDES_CORNER.COUT_18
CELL2.IO_W22_2SERDES_CORNER.COUT_19
CELL2.IO_W23_2SERDES_CORNER.COUT_20
CELL2.IO_W24_2SERDES_CORNER.COUT_21
CELL2.IO_W25_2SERDES_CORNER.SERDES0_BS4PAD_0
CELL2.IO_W26_2SERDES_CORNER.SERDES0_BS4PAD_1
CELL2.IO_W27_2SERDES_CORNER.SERDES0_BS4PAD_2
CELL2.IO_W28_2SERDES_CORNER.SERDES0_BS4PAD_3
CELL2.IO_W29_2SERDES_CORNER.SERDES1_BS4PAD_0
CELL2.IO_W30_2SERDES_CORNER.SERDES1_BS4PAD_1
CELL2.IO_W31_2SERDES_CORNER.SERDES1_BS4PAD_2
CELL2.IO_E0_1SERDES_CORNER.CIN_0
CELL2.IO_E1_1SERDES_CORNER.CIN_1
CELL2.IO_E2_1SERDES_CORNER.CIN_2
CELL2.IO_E3_1SERDES_CORNER.CIN_3
CELL2.IO_E4_1SERDES_CORNER.CIN_4
CELL2.IO_E5_1SERDES_CORNER.CIN_5
CELL2.IO_E6_1SERDES_CORNER.CIN_6
CELL2.IO_E7_1SERDES_CORNER.CIN_7
CELL2.IO_E8_1SERDES_CORNER.CIN_8
CELL2.IO_E9_1SERDES_CORNER.CIN_9
CELL2.IO_E10_1SERDES_CORNER.CIN_10
CELL2.IO_E11_1SERDES_CORNER.CIN_11
CELL2.IO_E12_1SERDES_CORNER.CIN_12
CELL2.IO_E14_1SERDES_CORNER.TESTCLK_MACO