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SERDES

Tile SERDES_W

Cells: 7

Bel SERDES

scm SERDES_W bel SERDES
PinDirectionWires
BS4PAD_0outputCELL4.OUT_OFX0
BS4PAD_1outputCELL4.OUT_OFX1
BS4PAD_2outputCELL4.OUT_OFX2
BS4PAD_3outputCELL4.OUT_OFX3
FB_RXD_0_0outputCELL2.OUT_F6
FB_RXD_0_1outputCELL2.OUT_F7
FB_RXD_0_10outputCELL1.OUT_Q0
FB_RXD_0_11outputCELL1.OUT_Q1
FB_RXD_0_12outputCELL1.OUT_Q2
FB_RXD_0_13outputCELL1.OUT_Q3
FB_RXD_0_14outputCELL1.OUT_Q4
FB_RXD_0_15outputCELL1.OUT_Q5
FB_RXD_0_16outputCELL1.OUT_Q6
FB_RXD_0_17outputCELL1.OUT_Q7
FB_RXD_0_18outputCELL1.OUT_F0
FB_RXD_0_19outputCELL1.OUT_F1
FB_RXD_0_2outputCELL1.OUT_OFX0
FB_RXD_0_20outputCELL1.OUT_F2
FB_RXD_0_21outputCELL1.OUT_F3
FB_RXD_0_22outputCELL1.OUT_F4
FB_RXD_0_23outputCELL1.OUT_F5
FB_RXD_0_3outputCELL1.OUT_OFX1
FB_RXD_0_4outputCELL1.OUT_OFX2
FB_RXD_0_5outputCELL1.OUT_OFX3
FB_RXD_0_6outputCELL1.OUT_OFX4
FB_RXD_0_7outputCELL1.OUT_OFX5
FB_RXD_0_8outputCELL1.OUT_OFX6
FB_RXD_0_9outputCELL1.OUT_OFX7
FB_RXD_1_0outputCELL3.OUT_Q0
FB_RXD_1_1outputCELL3.OUT_Q1
FB_RXD_1_10outputCELL3.OUT_F2
FB_RXD_1_11outputCELL3.OUT_F3
FB_RXD_1_12outputCELL3.OUT_F4
FB_RXD_1_13outputCELL3.OUT_F5
FB_RXD_1_14outputCELL3.OUT_F6
FB_RXD_1_15outputCELL3.OUT_F7
FB_RXD_1_16outputCELL2.OUT_OFX0
FB_RXD_1_17outputCELL2.OUT_OFX1
FB_RXD_1_18outputCELL2.OUT_OFX2
FB_RXD_1_19outputCELL2.OUT_OFX3
FB_RXD_1_2outputCELL3.OUT_Q2
FB_RXD_1_20outputCELL2.OUT_OFX4
FB_RXD_1_21outputCELL2.OUT_OFX5
FB_RXD_1_22outputCELL2.OUT_OFX6
FB_RXD_1_23outputCELL2.OUT_OFX7
FB_RXD_1_3outputCELL3.OUT_Q3
FB_RXD_1_4outputCELL3.OUT_Q4
FB_RXD_1_5outputCELL3.OUT_Q5
FB_RXD_1_6outputCELL3.OUT_Q6
FB_RXD_1_7outputCELL3.OUT_Q7
FB_RXD_1_8outputCELL3.OUT_F0
FB_RXD_1_9outputCELL3.OUT_F1
FB_RXD_2_0outputCELL5.OUT_Q7
FB_RXD_2_1outputCELL5.OUT_F0
FB_RXD_2_10outputCELL4.OUT_Q0
FB_RXD_2_11outputCELL4.OUT_Q1
FB_RXD_2_12outputCELL4.OUT_Q2
FB_RXD_2_13outputCELL4.OUT_Q3
FB_RXD_2_14outputCELL4.OUT_Q4
FB_RXD_2_15outputCELL4.OUT_Q5
FB_RXD_2_16outputCELL4.OUT_Q6
FB_RXD_2_17outputCELL4.OUT_Q7
FB_RXD_2_18outputCELL4.OUT_F0
FB_RXD_2_19outputCELL4.OUT_F1
FB_RXD_2_2outputCELL5.OUT_F1
FB_RXD_2_20outputCELL4.OUT_F2
FB_RXD_2_21outputCELL4.OUT_F3
FB_RXD_2_22outputCELL4.OUT_F4
FB_RXD_2_23outputCELL4.OUT_F5
FB_RXD_2_3outputCELL5.OUT_F2
FB_RXD_2_4outputCELL5.OUT_F3
FB_RXD_2_5outputCELL5.OUT_F4
FB_RXD_2_6outputCELL5.OUT_F5
FB_RXD_2_7outputCELL5.OUT_F6
FB_RXD_2_8outputCELL5.OUT_F7
FB_RXD_2_9outputCELL4.OUT_OFX7
FB_RXD_3_0outputCELL6.OUT_OFX2
FB_RXD_3_1outputCELL6.OUT_OFX3
FB_RXD_3_10outputCELL6.OUT_Q4
FB_RXD_3_11outputCELL6.OUT_Q5
FB_RXD_3_12outputCELL6.OUT_Q6
FB_RXD_3_13outputCELL6.OUT_Q7
FB_RXD_3_14outputCELL6.OUT_F0
FB_RXD_3_15outputCELL6.OUT_F1
FB_RXD_3_16outputCELL6.OUT_F2
FB_RXD_3_17outputCELL6.OUT_F3
FB_RXD_3_18outputCELL6.OUT_F4
FB_RXD_3_19outputCELL6.OUT_F5
FB_RXD_3_2outputCELL6.OUT_OFX4
FB_RXD_3_20outputCELL5.OUT_Q3
FB_RXD_3_21outputCELL5.OUT_Q4
FB_RXD_3_22outputCELL5.OUT_Q5
FB_RXD_3_23outputCELL5.OUT_Q6
FB_RXD_3_3outputCELL6.OUT_OFX5
FB_RXD_3_4outputCELL6.OUT_OFX6
FB_RXD_3_5outputCELL6.OUT_OFX7
FB_RXD_3_6outputCELL6.OUT_Q0
FB_RXD_3_7outputCELL6.OUT_Q1
FB_RXD_3_8outputCELL6.OUT_Q2
FB_RXD_3_9outputCELL6.OUT_Q3
FFC_AB_RESETinputCELL1.IMUX_CE0
FFC_ALIGN_EN_0inputCELL1.IMUX_D4
FFC_ALIGN_EN_1inputCELL2.IMUX_D4
FFC_ALIGN_EN_2inputCELL5.IMUX_D4
FFC_ALIGN_EN_3inputCELL6.IMUX_D4
FFC_CD_RESETinputCELL6.IMUX_CE0
FFC_CK_CORE_RXinputCELL4.IMUX_CLK2
FFC_EN_CGA_0inputCELL1.IMUX_D5
FFC_EN_CGA_1inputCELL2.IMUX_D5
FFC_EN_CGA_2inputCELL5.IMUX_D5
FFC_EN_CGA_3inputCELL6.IMUX_D5
FFC_FB_LB_0inputCELL1.IMUX_D3
FFC_FB_LB_1inputCELL2.IMUX_D3
FFC_FB_LB_2inputCELL5.IMUX_D3
FFC_FB_LB_3inputCELL6.IMUX_D3
FFC_LANE_RX_RST0inputCELL1.IMUX_CE1
FFC_LANE_RX_RST1inputCELL2.IMUX_CE1
FFC_LANE_RX_RST2inputCELL5.IMUX_CE1
FFC_LANE_RX_RST3inputCELL6.IMUX_CE1
FFC_LANE_TX_RST0inputCELL1.IMUX_CE2
FFC_LANE_TX_RST1inputCELL2.IMUX_CE2
FFC_LANE_TX_RST2inputCELL5.IMUX_CE2
FFC_LANE_TX_RST3inputCELL6.IMUX_CE2
FFC_MACRO_RSTinputCELL4.IMUX_CE0
FFC_PCIE_CT_0inputCELL1.IMUX_D1
FFC_PCIE_CT_1inputCELL2.IMUX_D1
FFC_PCIE_CT_2inputCELL5.IMUX_D1
FFC_PCIE_CT_3inputCELL6.IMUX_D1
FFC_PCIE_EI_EN_0inputCELL1.IMUX_D7
FFC_PCIE_EI_EN_1inputCELL2.IMUX_D7
FFC_PCIE_EI_EN_2inputCELL5.IMUX_D7
FFC_PCIE_EI_EN_3inputCELL6.IMUX_D7
FFC_PCIE_RX_0inputCELL4.IMUX_D7
FFC_PCIE_RX_1inputCELL4.IMUX_D6
FFC_PCIE_RX_2inputCELL4.IMUX_D1
FFC_PCIE_RX_3inputCELL4.IMUX_D0
FFC_PCIE_TX_0inputCELL1.IMUX_D0
FFC_PCIE_TX_1inputCELL2.IMUX_D0
FFC_PCIE_TX_2inputCELL5.IMUX_D0
FFC_PCIE_TX_3inputCELL6.IMUX_D0
FFC_QUAD_RSTinputCELL4.IMUX_LSR3
FFC_SB_INV_RX_0inputCELL1.IMUX_D2
FFC_SB_INV_RX_1inputCELL2.IMUX_D2
FFC_SB_INV_RX_2inputCELL5.IMUX_D2
FFC_SB_INV_RX_3inputCELL6.IMUX_D2
FFC_SD_0inputCELL1.IMUX_D6
FFC_SD_1inputCELL2.IMUX_D6
FFC_SD_2inputCELL5.IMUX_D6
FFC_SD_3inputCELL6.IMUX_D6
FFS_AB_ALIGNEDoutputCELL2.OUT_Q6
FFS_AB_FAILEDoutputCELL2.OUT_Q5
FFS_AB_STATUSoutputCELL2.OUT_Q7
FFS_CC_ORUN_0outputCELL2.OUT_F1
FFS_CC_ORUN_1outputCELL3.OUT_OFX3
FFS_CC_ORUN_2outputCELL5.OUT_OFX7
FFS_CC_ORUN_3outputCELL6.OUT_OFX1
FFS_CC_URUN_0outputCELL2.OUT_F0
FFS_CC_URUN_1outputCELL3.OUT_OFX2
FFS_CC_URUN_2outputCELL5.OUT_OFX6
FFS_CC_URUN_3outputCELL6.OUT_OFX0
FFS_CD_ALIGNEDoutputCELL5.OUT_OFX4
FFS_CD_FAILEDoutputCELL5.OUT_OFX3
FFS_CD_STATUSoutputCELL5.OUT_OFX5
FFS_LS_STATUS_0outputCELL2.OUT_F3
FFS_LS_STATUS_1outputCELL3.OUT_OFX5
FFS_LS_STATUS_2outputCELL5.OUT_Q0
FFS_LS_STATUS_3outputCELL5.OUT_OFX0
FFS_PCIE_CON_0outputCELL2.OUT_F5
FFS_PCIE_CON_1outputCELL3.OUT_OFX7
FFS_PCIE_CON_2outputCELL5.OUT_Q2
FFS_PCIE_CON_3outputCELL5.OUT_OFX2
FFS_PCIE_DONE_0outputCELL2.OUT_F4
FFS_PCIE_DONE_1outputCELL3.OUT_OFX6
FFS_PCIE_DONE_2outputCELL5.OUT_Q1
FFS_PCIE_DONE_3outputCELL5.OUT_OFX1
FFS_RLOS_LO0outputCELL2.OUT_Q4
FFS_RLOS_LO1outputCELL2.OUT_Q3
FFS_RLOS_LO2outputCELL4.OUT_OFX6
FFS_RLOS_LO3outputCELL4.OUT_OFX5
FF_RCLK0inputCELL1.IMUX_CLK2
FF_RCLK1inputCELL2.IMUX_CLK2
FF_RCLK2inputCELL5.IMUX_CLK2
FF_RCLK3inputCELL6.IMUX_CLK2
FF_RXCLK0outputCELL1.OUT_F6
FF_RXCLK1outputCELL2.OUT_Q0
FF_RXCLK2outputCELL4.OUT_F6
FF_RXCLK3outputCELL6.OUT_F6
FF_SYSCLK0outputCELL1.OUT_F7
FF_SYSCLK1outputCELL2.OUT_Q1
FF_SYSCLK2outputCELL4.OUT_F7
FF_SYSCLK3outputCELL6.OUT_F7
FF_TCLK0inputCELL1.IMUX_CLK3
FF_TCLK1inputCELL2.IMUX_CLK3
FF_TCLK2inputCELL5.IMUX_CLK3
FF_TCLK3inputCELL6.IMUX_CLK3
FF_TXD_0_0inputCELL1.IMUX_C0
FF_TXD_0_1inputCELL1.IMUX_C1
FF_TXD_0_10inputCELL1.IMUX_B2
FF_TXD_0_11inputCELL1.IMUX_B3
FF_TXD_0_12inputCELL1.IMUX_B4
FF_TXD_0_13inputCELL1.IMUX_B5
FF_TXD_0_14inputCELL1.IMUX_B6
FF_TXD_0_15inputCELL1.IMUX_B7
FF_TXD_0_16inputCELL1.IMUX_A0
FF_TXD_0_17inputCELL1.IMUX_A1
FF_TXD_0_18inputCELL1.IMUX_A2
FF_TXD_0_19inputCELL1.IMUX_A3
FF_TXD_0_2inputCELL1.IMUX_C2
FF_TXD_0_20inputCELL1.IMUX_A4
FF_TXD_0_21inputCELL1.IMUX_A5
FF_TXD_0_22inputCELL1.IMUX_A6
FF_TXD_0_23inputCELL1.IMUX_A7
FF_TXD_0_3inputCELL1.IMUX_C3
FF_TXD_0_4inputCELL1.IMUX_C4
FF_TXD_0_5inputCELL1.IMUX_C5
FF_TXD_0_6inputCELL1.IMUX_C6
FF_TXD_0_7inputCELL1.IMUX_C7
FF_TXD_0_8inputCELL1.IMUX_B0
FF_TXD_0_9inputCELL1.IMUX_B1
FF_TXD_1_0inputCELL2.IMUX_C0
FF_TXD_1_1inputCELL2.IMUX_C1
FF_TXD_1_10inputCELL2.IMUX_B2
FF_TXD_1_11inputCELL2.IMUX_B3
FF_TXD_1_12inputCELL2.IMUX_B4
FF_TXD_1_13inputCELL2.IMUX_B5
FF_TXD_1_14inputCELL2.IMUX_B6
FF_TXD_1_15inputCELL2.IMUX_B7
FF_TXD_1_16inputCELL2.IMUX_A0
FF_TXD_1_17inputCELL2.IMUX_A1
FF_TXD_1_18inputCELL2.IMUX_A2
FF_TXD_1_19inputCELL2.IMUX_A3
FF_TXD_1_2inputCELL2.IMUX_C2
FF_TXD_1_20inputCELL2.IMUX_A4
FF_TXD_1_21inputCELL2.IMUX_A5
FF_TXD_1_22inputCELL2.IMUX_A6
FF_TXD_1_23inputCELL2.IMUX_A7
FF_TXD_1_3inputCELL2.IMUX_C3
FF_TXD_1_4inputCELL2.IMUX_C4
FF_TXD_1_5inputCELL2.IMUX_C5
FF_TXD_1_6inputCELL2.IMUX_C6
FF_TXD_1_7inputCELL2.IMUX_C7
FF_TXD_1_8inputCELL2.IMUX_B0
FF_TXD_1_9inputCELL2.IMUX_B1
FF_TXD_2_0inputCELL5.IMUX_C0
FF_TXD_2_1inputCELL5.IMUX_C1
FF_TXD_2_10inputCELL5.IMUX_B2
FF_TXD_2_11inputCELL5.IMUX_B3
FF_TXD_2_12inputCELL5.IMUX_B4
FF_TXD_2_13inputCELL5.IMUX_B5
FF_TXD_2_14inputCELL5.IMUX_B6
FF_TXD_2_15inputCELL5.IMUX_B7
FF_TXD_2_16inputCELL5.IMUX_A0
FF_TXD_2_17inputCELL5.IMUX_A1
FF_TXD_2_18inputCELL5.IMUX_A2
FF_TXD_2_19inputCELL5.IMUX_A3
FF_TXD_2_2inputCELL5.IMUX_C2
FF_TXD_2_20inputCELL5.IMUX_A4
FF_TXD_2_21inputCELL5.IMUX_A5
FF_TXD_2_22inputCELL5.IMUX_A6
FF_TXD_2_23inputCELL5.IMUX_A7
FF_TXD_2_3inputCELL5.IMUX_C3
FF_TXD_2_4inputCELL5.IMUX_C4
FF_TXD_2_5inputCELL5.IMUX_C5
FF_TXD_2_6inputCELL5.IMUX_C6
FF_TXD_2_7inputCELL5.IMUX_C7
FF_TXD_2_8inputCELL5.IMUX_B0
FF_TXD_2_9inputCELL5.IMUX_B1
FF_TXD_3_0inputCELL6.IMUX_C0
FF_TXD_3_1inputCELL6.IMUX_C1
FF_TXD_3_10inputCELL6.IMUX_B2
FF_TXD_3_11inputCELL6.IMUX_B3
FF_TXD_3_12inputCELL6.IMUX_B4
FF_TXD_3_13inputCELL6.IMUX_B5
FF_TXD_3_14inputCELL6.IMUX_B6
FF_TXD_3_15inputCELL6.IMUX_B7
FF_TXD_3_16inputCELL6.IMUX_A0
FF_TXD_3_17inputCELL6.IMUX_A1
FF_TXD_3_18inputCELL6.IMUX_A2
FF_TXD_3_19inputCELL6.IMUX_A3
FF_TXD_3_2inputCELL6.IMUX_C2
FF_TXD_3_20inputCELL6.IMUX_A4
FF_TXD_3_21inputCELL6.IMUX_A5
FF_TXD_3_22inputCELL6.IMUX_A6
FF_TXD_3_23inputCELL6.IMUX_A7
FF_TXD_3_3inputCELL6.IMUX_C3
FF_TXD_3_4inputCELL6.IMUX_C4
FF_TXD_3_5inputCELL6.IMUX_C5
FF_TXD_3_6inputCELL6.IMUX_C6
FF_TXD_3_7inputCELL6.IMUX_C7
FF_TXD_3_8inputCELL6.IMUX_B0
FF_TXD_3_9inputCELL6.IMUX_B1

Bel wires

scm SERDES_W bel wires
WirePins
CELL1.IMUX_A0SERDES.FF_TXD_0_16
CELL1.IMUX_A1SERDES.FF_TXD_0_17
CELL1.IMUX_A2SERDES.FF_TXD_0_18
CELL1.IMUX_A3SERDES.FF_TXD_0_19
CELL1.IMUX_A4SERDES.FF_TXD_0_20
CELL1.IMUX_A5SERDES.FF_TXD_0_21
CELL1.IMUX_A6SERDES.FF_TXD_0_22
CELL1.IMUX_A7SERDES.FF_TXD_0_23
CELL1.IMUX_B0SERDES.FF_TXD_0_8
CELL1.IMUX_B1SERDES.FF_TXD_0_9
CELL1.IMUX_B2SERDES.FF_TXD_0_10
CELL1.IMUX_B3SERDES.FF_TXD_0_11
CELL1.IMUX_B4SERDES.FF_TXD_0_12
CELL1.IMUX_B5SERDES.FF_TXD_0_13
CELL1.IMUX_B6SERDES.FF_TXD_0_14
CELL1.IMUX_B7SERDES.FF_TXD_0_15
CELL1.IMUX_C0SERDES.FF_TXD_0_0
CELL1.IMUX_C1SERDES.FF_TXD_0_1
CELL1.IMUX_C2SERDES.FF_TXD_0_2
CELL1.IMUX_C3SERDES.FF_TXD_0_3
CELL1.IMUX_C4SERDES.FF_TXD_0_4
CELL1.IMUX_C5SERDES.FF_TXD_0_5
CELL1.IMUX_C6SERDES.FF_TXD_0_6
CELL1.IMUX_C7SERDES.FF_TXD_0_7
CELL1.IMUX_D0SERDES.FFC_PCIE_TX_0
CELL1.IMUX_D1SERDES.FFC_PCIE_CT_0
CELL1.IMUX_D2SERDES.FFC_SB_INV_RX_0
CELL1.IMUX_D3SERDES.FFC_FB_LB_0
CELL1.IMUX_D4SERDES.FFC_ALIGN_EN_0
CELL1.IMUX_D5SERDES.FFC_EN_CGA_0
CELL1.IMUX_D6SERDES.FFC_SD_0
CELL1.IMUX_D7SERDES.FFC_PCIE_EI_EN_0
CELL1.IMUX_CLK2SERDES.FF_RCLK0
CELL1.IMUX_CLK3SERDES.FF_TCLK0
CELL1.IMUX_CE0SERDES.FFC_AB_RESET
CELL1.IMUX_CE1SERDES.FFC_LANE_RX_RST0
CELL1.IMUX_CE2SERDES.FFC_LANE_TX_RST0
CELL1.OUT_F0SERDES.FB_RXD_0_18
CELL1.OUT_F1SERDES.FB_RXD_0_19
CELL1.OUT_F2SERDES.FB_RXD_0_20
CELL1.OUT_F3SERDES.FB_RXD_0_21
CELL1.OUT_F4SERDES.FB_RXD_0_22
CELL1.OUT_F5SERDES.FB_RXD_0_23
CELL1.OUT_F6SERDES.FF_RXCLK0
CELL1.OUT_F7SERDES.FF_SYSCLK0
CELL1.OUT_Q0SERDES.FB_RXD_0_10
CELL1.OUT_Q1SERDES.FB_RXD_0_11
CELL1.OUT_Q2SERDES.FB_RXD_0_12
CELL1.OUT_Q3SERDES.FB_RXD_0_13
CELL1.OUT_Q4SERDES.FB_RXD_0_14
CELL1.OUT_Q5SERDES.FB_RXD_0_15
CELL1.OUT_Q6SERDES.FB_RXD_0_16
CELL1.OUT_Q7SERDES.FB_RXD_0_17
CELL1.OUT_OFX0SERDES.FB_RXD_0_2
CELL1.OUT_OFX1SERDES.FB_RXD_0_3
CELL1.OUT_OFX2SERDES.FB_RXD_0_4
CELL1.OUT_OFX3SERDES.FB_RXD_0_5
CELL1.OUT_OFX4SERDES.FB_RXD_0_6
CELL1.OUT_OFX5SERDES.FB_RXD_0_7
CELL1.OUT_OFX6SERDES.FB_RXD_0_8
CELL1.OUT_OFX7SERDES.FB_RXD_0_9
CELL2.IMUX_A0SERDES.FF_TXD_1_16
CELL2.IMUX_A1SERDES.FF_TXD_1_17
CELL2.IMUX_A2SERDES.FF_TXD_1_18
CELL2.IMUX_A3SERDES.FF_TXD_1_19
CELL2.IMUX_A4SERDES.FF_TXD_1_20
CELL2.IMUX_A5SERDES.FF_TXD_1_21
CELL2.IMUX_A6SERDES.FF_TXD_1_22
CELL2.IMUX_A7SERDES.FF_TXD_1_23
CELL2.IMUX_B0SERDES.FF_TXD_1_8
CELL2.IMUX_B1SERDES.FF_TXD_1_9
CELL2.IMUX_B2SERDES.FF_TXD_1_10
CELL2.IMUX_B3SERDES.FF_TXD_1_11
CELL2.IMUX_B4SERDES.FF_TXD_1_12
CELL2.IMUX_B5SERDES.FF_TXD_1_13
CELL2.IMUX_B6SERDES.FF_TXD_1_14
CELL2.IMUX_B7SERDES.FF_TXD_1_15
CELL2.IMUX_C0SERDES.FF_TXD_1_0
CELL2.IMUX_C1SERDES.FF_TXD_1_1
CELL2.IMUX_C2SERDES.FF_TXD_1_2
CELL2.IMUX_C3SERDES.FF_TXD_1_3
CELL2.IMUX_C4SERDES.FF_TXD_1_4
CELL2.IMUX_C5SERDES.FF_TXD_1_5
CELL2.IMUX_C6SERDES.FF_TXD_1_6
CELL2.IMUX_C7SERDES.FF_TXD_1_7
CELL2.IMUX_D0SERDES.FFC_PCIE_TX_1
CELL2.IMUX_D1SERDES.FFC_PCIE_CT_1
CELL2.IMUX_D2SERDES.FFC_SB_INV_RX_1
CELL2.IMUX_D3SERDES.FFC_FB_LB_1
CELL2.IMUX_D4SERDES.FFC_ALIGN_EN_1
CELL2.IMUX_D5SERDES.FFC_EN_CGA_1
CELL2.IMUX_D6SERDES.FFC_SD_1
CELL2.IMUX_D7SERDES.FFC_PCIE_EI_EN_1
CELL2.IMUX_CLK2SERDES.FF_RCLK1
CELL2.IMUX_CLK3SERDES.FF_TCLK1
CELL2.IMUX_CE1SERDES.FFC_LANE_RX_RST1
CELL2.IMUX_CE2SERDES.FFC_LANE_TX_RST1
CELL2.OUT_F0SERDES.FFS_CC_URUN_0
CELL2.OUT_F1SERDES.FFS_CC_ORUN_0
CELL2.OUT_F3SERDES.FFS_LS_STATUS_0
CELL2.OUT_F4SERDES.FFS_PCIE_DONE_0
CELL2.OUT_F5SERDES.FFS_PCIE_CON_0
CELL2.OUT_F6SERDES.FB_RXD_0_0
CELL2.OUT_F7SERDES.FB_RXD_0_1
CELL2.OUT_Q0SERDES.FF_RXCLK1
CELL2.OUT_Q1SERDES.FF_SYSCLK1
CELL2.OUT_Q3SERDES.FFS_RLOS_LO1
CELL2.OUT_Q4SERDES.FFS_RLOS_LO0
CELL2.OUT_Q5SERDES.FFS_AB_FAILED
CELL2.OUT_Q6SERDES.FFS_AB_ALIGNED
CELL2.OUT_Q7SERDES.FFS_AB_STATUS
CELL2.OUT_OFX0SERDES.FB_RXD_1_16
CELL2.OUT_OFX1SERDES.FB_RXD_1_17
CELL2.OUT_OFX2SERDES.FB_RXD_1_18
CELL2.OUT_OFX3SERDES.FB_RXD_1_19
CELL2.OUT_OFX4SERDES.FB_RXD_1_20
CELL2.OUT_OFX5SERDES.FB_RXD_1_21
CELL2.OUT_OFX6SERDES.FB_RXD_1_22
CELL2.OUT_OFX7SERDES.FB_RXD_1_23
CELL3.OUT_F0SERDES.FB_RXD_1_8
CELL3.OUT_F1SERDES.FB_RXD_1_9
CELL3.OUT_F2SERDES.FB_RXD_1_10
CELL3.OUT_F3SERDES.FB_RXD_1_11
CELL3.OUT_F4SERDES.FB_RXD_1_12
CELL3.OUT_F5SERDES.FB_RXD_1_13
CELL3.OUT_F6SERDES.FB_RXD_1_14
CELL3.OUT_F7SERDES.FB_RXD_1_15
CELL3.OUT_Q0SERDES.FB_RXD_1_0
CELL3.OUT_Q1SERDES.FB_RXD_1_1
CELL3.OUT_Q2SERDES.FB_RXD_1_2
CELL3.OUT_Q3SERDES.FB_RXD_1_3
CELL3.OUT_Q4SERDES.FB_RXD_1_4
CELL3.OUT_Q5SERDES.FB_RXD_1_5
CELL3.OUT_Q6SERDES.FB_RXD_1_6
CELL3.OUT_Q7SERDES.FB_RXD_1_7
CELL3.OUT_OFX2SERDES.FFS_CC_URUN_1
CELL3.OUT_OFX3SERDES.FFS_CC_ORUN_1
CELL3.OUT_OFX5SERDES.FFS_LS_STATUS_1
CELL3.OUT_OFX6SERDES.FFS_PCIE_DONE_1
CELL3.OUT_OFX7SERDES.FFS_PCIE_CON_1
CELL4.IMUX_D0SERDES.FFC_PCIE_RX_3
CELL4.IMUX_D1SERDES.FFC_PCIE_RX_2
CELL4.IMUX_D6SERDES.FFC_PCIE_RX_1
CELL4.IMUX_D7SERDES.FFC_PCIE_RX_0
CELL4.IMUX_CLK2SERDES.FFC_CK_CORE_RX
CELL4.IMUX_LSR3SERDES.FFC_QUAD_RST
CELL4.IMUX_CE0SERDES.FFC_MACRO_RST
CELL4.OUT_F0SERDES.FB_RXD_2_18
CELL4.OUT_F1SERDES.FB_RXD_2_19
CELL4.OUT_F2SERDES.FB_RXD_2_20
CELL4.OUT_F3SERDES.FB_RXD_2_21
CELL4.OUT_F4SERDES.FB_RXD_2_22
CELL4.OUT_F5SERDES.FB_RXD_2_23
CELL4.OUT_F6SERDES.FF_RXCLK2
CELL4.OUT_F7SERDES.FF_SYSCLK2
CELL4.OUT_Q0SERDES.FB_RXD_2_10
CELL4.OUT_Q1SERDES.FB_RXD_2_11
CELL4.OUT_Q2SERDES.FB_RXD_2_12
CELL4.OUT_Q3SERDES.FB_RXD_2_13
CELL4.OUT_Q4SERDES.FB_RXD_2_14
CELL4.OUT_Q5SERDES.FB_RXD_2_15
CELL4.OUT_Q6SERDES.FB_RXD_2_16
CELL4.OUT_Q7SERDES.FB_RXD_2_17
CELL4.OUT_OFX0SERDES.BS4PAD_0
CELL4.OUT_OFX1SERDES.BS4PAD_1
CELL4.OUT_OFX2SERDES.BS4PAD_2
CELL4.OUT_OFX3SERDES.BS4PAD_3
CELL4.OUT_OFX5SERDES.FFS_RLOS_LO3
CELL4.OUT_OFX6SERDES.FFS_RLOS_LO2
CELL4.OUT_OFX7SERDES.FB_RXD_2_9
CELL5.IMUX_A0SERDES.FF_TXD_2_16
CELL5.IMUX_A1SERDES.FF_TXD_2_17
CELL5.IMUX_A2SERDES.FF_TXD_2_18
CELL5.IMUX_A3SERDES.FF_TXD_2_19
CELL5.IMUX_A4SERDES.FF_TXD_2_20
CELL5.IMUX_A5SERDES.FF_TXD_2_21
CELL5.IMUX_A6SERDES.FF_TXD_2_22
CELL5.IMUX_A7SERDES.FF_TXD_2_23
CELL5.IMUX_B0SERDES.FF_TXD_2_8
CELL5.IMUX_B1SERDES.FF_TXD_2_9
CELL5.IMUX_B2SERDES.FF_TXD_2_10
CELL5.IMUX_B3SERDES.FF_TXD_2_11
CELL5.IMUX_B4SERDES.FF_TXD_2_12
CELL5.IMUX_B5SERDES.FF_TXD_2_13
CELL5.IMUX_B6SERDES.FF_TXD_2_14
CELL5.IMUX_B7SERDES.FF_TXD_2_15
CELL5.IMUX_C0SERDES.FF_TXD_2_0
CELL5.IMUX_C1SERDES.FF_TXD_2_1
CELL5.IMUX_C2SERDES.FF_TXD_2_2
CELL5.IMUX_C3SERDES.FF_TXD_2_3
CELL5.IMUX_C4SERDES.FF_TXD_2_4
CELL5.IMUX_C5SERDES.FF_TXD_2_5
CELL5.IMUX_C6SERDES.FF_TXD_2_6
CELL5.IMUX_C7SERDES.FF_TXD_2_7
CELL5.IMUX_D0SERDES.FFC_PCIE_TX_2
CELL5.IMUX_D1SERDES.FFC_PCIE_CT_2
CELL5.IMUX_D2SERDES.FFC_SB_INV_RX_2
CELL5.IMUX_D3SERDES.FFC_FB_LB_2
CELL5.IMUX_D4SERDES.FFC_ALIGN_EN_2
CELL5.IMUX_D5SERDES.FFC_EN_CGA_2
CELL5.IMUX_D6SERDES.FFC_SD_2
CELL5.IMUX_D7SERDES.FFC_PCIE_EI_EN_2
CELL5.IMUX_CLK2SERDES.FF_RCLK2
CELL5.IMUX_CLK3SERDES.FF_TCLK2
CELL5.IMUX_CE1SERDES.FFC_LANE_RX_RST2
CELL5.IMUX_CE2SERDES.FFC_LANE_TX_RST2
CELL5.OUT_F0SERDES.FB_RXD_2_1
CELL5.OUT_F1SERDES.FB_RXD_2_2
CELL5.OUT_F2SERDES.FB_RXD_2_3
CELL5.OUT_F3SERDES.FB_RXD_2_4
CELL5.OUT_F4SERDES.FB_RXD_2_5
CELL5.OUT_F5SERDES.FB_RXD_2_6
CELL5.OUT_F6SERDES.FB_RXD_2_7
CELL5.OUT_F7SERDES.FB_RXD_2_8
CELL5.OUT_Q0SERDES.FFS_LS_STATUS_2
CELL5.OUT_Q1SERDES.FFS_PCIE_DONE_2
CELL5.OUT_Q2SERDES.FFS_PCIE_CON_2
CELL5.OUT_Q3SERDES.FB_RXD_3_20
CELL5.OUT_Q4SERDES.FB_RXD_3_21
CELL5.OUT_Q5SERDES.FB_RXD_3_22
CELL5.OUT_Q6SERDES.FB_RXD_3_23
CELL5.OUT_Q7SERDES.FB_RXD_2_0
CELL5.OUT_OFX0SERDES.FFS_LS_STATUS_3
CELL5.OUT_OFX1SERDES.FFS_PCIE_DONE_3
CELL5.OUT_OFX2SERDES.FFS_PCIE_CON_3
CELL5.OUT_OFX3SERDES.FFS_CD_FAILED
CELL5.OUT_OFX4SERDES.FFS_CD_ALIGNED
CELL5.OUT_OFX5SERDES.FFS_CD_STATUS
CELL5.OUT_OFX6SERDES.FFS_CC_URUN_2
CELL5.OUT_OFX7SERDES.FFS_CC_ORUN_2
CELL6.IMUX_A0SERDES.FF_TXD_3_16
CELL6.IMUX_A1SERDES.FF_TXD_3_17
CELL6.IMUX_A2SERDES.FF_TXD_3_18
CELL6.IMUX_A3SERDES.FF_TXD_3_19
CELL6.IMUX_A4SERDES.FF_TXD_3_20
CELL6.IMUX_A5SERDES.FF_TXD_3_21
CELL6.IMUX_A6SERDES.FF_TXD_3_22
CELL6.IMUX_A7SERDES.FF_TXD_3_23
CELL6.IMUX_B0SERDES.FF_TXD_3_8
CELL6.IMUX_B1SERDES.FF_TXD_3_9
CELL6.IMUX_B2SERDES.FF_TXD_3_10
CELL6.IMUX_B3SERDES.FF_TXD_3_11
CELL6.IMUX_B4SERDES.FF_TXD_3_12
CELL6.IMUX_B5SERDES.FF_TXD_3_13
CELL6.IMUX_B6SERDES.FF_TXD_3_14
CELL6.IMUX_B7SERDES.FF_TXD_3_15
CELL6.IMUX_C0SERDES.FF_TXD_3_0
CELL6.IMUX_C1SERDES.FF_TXD_3_1
CELL6.IMUX_C2SERDES.FF_TXD_3_2
CELL6.IMUX_C3SERDES.FF_TXD_3_3
CELL6.IMUX_C4SERDES.FF_TXD_3_4
CELL6.IMUX_C5SERDES.FF_TXD_3_5
CELL6.IMUX_C6SERDES.FF_TXD_3_6
CELL6.IMUX_C7SERDES.FF_TXD_3_7
CELL6.IMUX_D0SERDES.FFC_PCIE_TX_3
CELL6.IMUX_D1SERDES.FFC_PCIE_CT_3
CELL6.IMUX_D2SERDES.FFC_SB_INV_RX_3
CELL6.IMUX_D3SERDES.FFC_FB_LB_3
CELL6.IMUX_D4SERDES.FFC_ALIGN_EN_3
CELL6.IMUX_D5SERDES.FFC_EN_CGA_3
CELL6.IMUX_D6SERDES.FFC_SD_3
CELL6.IMUX_D7SERDES.FFC_PCIE_EI_EN_3
CELL6.IMUX_CLK2SERDES.FF_RCLK3
CELL6.IMUX_CLK3SERDES.FF_TCLK3
CELL6.IMUX_CE0SERDES.FFC_CD_RESET
CELL6.IMUX_CE1SERDES.FFC_LANE_RX_RST3
CELL6.IMUX_CE2SERDES.FFC_LANE_TX_RST3
CELL6.OUT_F0SERDES.FB_RXD_3_14
CELL6.OUT_F1SERDES.FB_RXD_3_15
CELL6.OUT_F2SERDES.FB_RXD_3_16
CELL6.OUT_F3SERDES.FB_RXD_3_17
CELL6.OUT_F4SERDES.FB_RXD_3_18
CELL6.OUT_F5SERDES.FB_RXD_3_19
CELL6.OUT_F6SERDES.FF_RXCLK3
CELL6.OUT_F7SERDES.FF_SYSCLK3
CELL6.OUT_Q0SERDES.FB_RXD_3_6
CELL6.OUT_Q1SERDES.FB_RXD_3_7
CELL6.OUT_Q2SERDES.FB_RXD_3_8
CELL6.OUT_Q3SERDES.FB_RXD_3_9
CELL6.OUT_Q4SERDES.FB_RXD_3_10
CELL6.OUT_Q5SERDES.FB_RXD_3_11
CELL6.OUT_Q6SERDES.FB_RXD_3_12
CELL6.OUT_Q7SERDES.FB_RXD_3_13
CELL6.OUT_OFX0SERDES.FFS_CC_URUN_3
CELL6.OUT_OFX1SERDES.FFS_CC_ORUN_3
CELL6.OUT_OFX2SERDES.FB_RXD_3_0
CELL6.OUT_OFX3SERDES.FB_RXD_3_1
CELL6.OUT_OFX4SERDES.FB_RXD_3_2
CELL6.OUT_OFX5SERDES.FB_RXD_3_3
CELL6.OUT_OFX6SERDES.FB_RXD_3_4
CELL6.OUT_OFX7SERDES.FB_RXD_3_5

Tile SERDES_E

Cells: 7

Bel SERDES

scm SERDES_E bel SERDES
PinDirectionWires
BS4PAD_0outputCELL2.OUT_OFX7
BS4PAD_1outputCELL2.OUT_OFX6
BS4PAD_2outputCELL2.OUT_OFX5
BS4PAD_3outputCELL2.OUT_OFX4
FB_RXD_0_0outputCELL4.OUT_F1
FB_RXD_0_1outputCELL4.OUT_F0
FB_RXD_0_10outputCELL5.OUT_Q7
FB_RXD_0_11outputCELL5.OUT_Q6
FB_RXD_0_12outputCELL5.OUT_Q5
FB_RXD_0_13outputCELL5.OUT_Q4
FB_RXD_0_14outputCELL5.OUT_Q3
FB_RXD_0_15outputCELL5.OUT_Q2
FB_RXD_0_16outputCELL5.OUT_Q1
FB_RXD_0_17outputCELL5.OUT_Q0
FB_RXD_0_18outputCELL5.OUT_F7
FB_RXD_0_19outputCELL5.OUT_F6
FB_RXD_0_2outputCELL5.OUT_OFX7
FB_RXD_0_20outputCELL5.OUT_F5
FB_RXD_0_21outputCELL5.OUT_F4
FB_RXD_0_22outputCELL5.OUT_F3
FB_RXD_0_23outputCELL5.OUT_F2
FB_RXD_0_3outputCELL5.OUT_OFX6
FB_RXD_0_4outputCELL5.OUT_OFX5
FB_RXD_0_5outputCELL5.OUT_OFX4
FB_RXD_0_6outputCELL5.OUT_OFX3
FB_RXD_0_7outputCELL5.OUT_OFX2
FB_RXD_0_8outputCELL5.OUT_OFX1
FB_RXD_0_9outputCELL5.OUT_OFX0
FB_RXD_1_0outputCELL3.OUT_Q7
FB_RXD_1_1outputCELL3.OUT_Q6
FB_RXD_1_10outputCELL3.OUT_F5
FB_RXD_1_11outputCELL3.OUT_F4
FB_RXD_1_12outputCELL3.OUT_F3
FB_RXD_1_13outputCELL3.OUT_F2
FB_RXD_1_14outputCELL3.OUT_F1
FB_RXD_1_15outputCELL3.OUT_F0
FB_RXD_1_16outputCELL4.OUT_OFX7
FB_RXD_1_17outputCELL4.OUT_OFX6
FB_RXD_1_18outputCELL4.OUT_OFX5
FB_RXD_1_19outputCELL4.OUT_OFX4
FB_RXD_1_2outputCELL3.OUT_Q5
FB_RXD_1_20outputCELL4.OUT_OFX3
FB_RXD_1_21outputCELL4.OUT_OFX2
FB_RXD_1_22outputCELL4.OUT_OFX1
FB_RXD_1_23outputCELL4.OUT_OFX0
FB_RXD_1_3outputCELL3.OUT_Q4
FB_RXD_1_4outputCELL3.OUT_Q3
FB_RXD_1_5outputCELL3.OUT_Q2
FB_RXD_1_6outputCELL3.OUT_Q1
FB_RXD_1_7outputCELL3.OUT_Q0
FB_RXD_1_8outputCELL3.OUT_F7
FB_RXD_1_9outputCELL3.OUT_F6
FB_RXD_2_0outputCELL1.OUT_Q0
FB_RXD_2_1outputCELL1.OUT_F7
FB_RXD_2_10outputCELL2.OUT_Q7
FB_RXD_2_11outputCELL2.OUT_Q6
FB_RXD_2_12outputCELL2.OUT_Q5
FB_RXD_2_13outputCELL2.OUT_Q4
FB_RXD_2_14outputCELL2.OUT_Q3
FB_RXD_2_15outputCELL2.OUT_Q2
FB_RXD_2_16outputCELL2.OUT_Q1
FB_RXD_2_17outputCELL2.OUT_Q0
FB_RXD_2_18outputCELL2.OUT_F7
FB_RXD_2_19outputCELL2.OUT_F6
FB_RXD_2_2outputCELL1.OUT_F6
FB_RXD_2_20outputCELL2.OUT_F5
FB_RXD_2_21outputCELL2.OUT_F4
FB_RXD_2_22outputCELL2.OUT_F3
FB_RXD_2_23outputCELL2.OUT_F2
FB_RXD_2_3outputCELL1.OUT_F5
FB_RXD_2_4outputCELL1.OUT_F4
FB_RXD_2_5outputCELL1.OUT_F3
FB_RXD_2_6outputCELL1.OUT_F2
FB_RXD_2_7outputCELL1.OUT_F1
FB_RXD_2_8outputCELL1.OUT_F0
FB_RXD_2_9outputCELL2.OUT_OFX0
FB_RXD_3_0outputCELL0.OUT_OFX5
FB_RXD_3_1outputCELL0.OUT_OFX4
FB_RXD_3_10outputCELL0.OUT_Q3
FB_RXD_3_11outputCELL0.OUT_Q2
FB_RXD_3_12outputCELL0.OUT_Q1
FB_RXD_3_13outputCELL0.OUT_Q0
FB_RXD_3_14outputCELL0.OUT_F7
FB_RXD_3_15outputCELL0.OUT_F6
FB_RXD_3_16outputCELL0.OUT_F5
FB_RXD_3_17outputCELL0.OUT_F4
FB_RXD_3_18outputCELL0.OUT_F3
FB_RXD_3_19outputCELL0.OUT_F2
FB_RXD_3_2outputCELL0.OUT_OFX3
FB_RXD_3_20outputCELL1.OUT_Q4
FB_RXD_3_21outputCELL1.OUT_Q3
FB_RXD_3_22outputCELL1.OUT_Q2
FB_RXD_3_23outputCELL1.OUT_Q1
FB_RXD_3_3outputCELL0.OUT_OFX2
FB_RXD_3_4outputCELL0.OUT_OFX1
FB_RXD_3_5outputCELL0.OUT_OFX0
FB_RXD_3_6outputCELL0.OUT_Q7
FB_RXD_3_7outputCELL0.OUT_Q6
FB_RXD_3_8outputCELL0.OUT_Q5
FB_RXD_3_9outputCELL0.OUT_Q4
FFC_AB_RESETinputCELL5.IMUX_CE3
FFC_ALIGN_EN_0inputCELL5.IMUX_D3
FFC_ALIGN_EN_1inputCELL4.IMUX_D3
FFC_ALIGN_EN_2inputCELL1.IMUX_D3
FFC_ALIGN_EN_3inputCELL0.IMUX_D3
FFC_CD_RESETinputCELL0.IMUX_CE3
FFC_CK_CORE_RXinputCELL2.IMUX_CLK1
FFC_EN_CGA_0inputCELL5.IMUX_D2
FFC_EN_CGA_1inputCELL4.IMUX_D2
FFC_EN_CGA_2inputCELL1.IMUX_D2
FFC_EN_CGA_3inputCELL0.IMUX_D2
FFC_FB_LB_0inputCELL5.IMUX_D4
FFC_FB_LB_1inputCELL4.IMUX_D4
FFC_FB_LB_2inputCELL1.IMUX_D4
FFC_FB_LB_3inputCELL0.IMUX_D4
FFC_LANE_RX_RST0inputCELL5.IMUX_CE2
FFC_LANE_RX_RST1inputCELL4.IMUX_CE2
FFC_LANE_RX_RST2inputCELL1.IMUX_CE2
FFC_LANE_RX_RST3inputCELL0.IMUX_CE2
FFC_LANE_TX_RST0inputCELL5.IMUX_CE1
FFC_LANE_TX_RST1inputCELL4.IMUX_CE1
FFC_LANE_TX_RST2inputCELL1.IMUX_CE1
FFC_LANE_TX_RST3inputCELL0.IMUX_CE1
FFC_MACRO_RSTinputCELL2.IMUX_CE3
FFC_PCIE_CT_0inputCELL5.IMUX_D6
FFC_PCIE_CT_1inputCELL4.IMUX_D6
FFC_PCIE_CT_2inputCELL1.IMUX_D6
FFC_PCIE_CT_3inputCELL0.IMUX_D6
FFC_PCIE_EI_EN_0inputCELL5.IMUX_D0
FFC_PCIE_EI_EN_1inputCELL4.IMUX_D0
FFC_PCIE_EI_EN_2inputCELL1.IMUX_D0
FFC_PCIE_EI_EN_3inputCELL0.IMUX_D0
FFC_PCIE_RX_0inputCELL2.IMUX_D0
FFC_PCIE_RX_1inputCELL2.IMUX_D1
FFC_PCIE_RX_2inputCELL2.IMUX_D6
FFC_PCIE_RX_3inputCELL2.IMUX_D7
FFC_PCIE_TX_0inputCELL5.IMUX_D7
FFC_PCIE_TX_1inputCELL4.IMUX_D7
FFC_PCIE_TX_2inputCELL1.IMUX_D7
FFC_PCIE_TX_3inputCELL0.IMUX_D7
FFC_QUAD_RSTinputCELL2.IMUX_LSR0
FFC_SB_INV_RX_0inputCELL5.IMUX_D5
FFC_SB_INV_RX_1inputCELL4.IMUX_D5
FFC_SB_INV_RX_2inputCELL1.IMUX_D5
FFC_SB_INV_RX_3inputCELL0.IMUX_D5
FFC_SD_0inputCELL5.IMUX_D1
FFC_SD_1inputCELL4.IMUX_D1
FFC_SD_2inputCELL1.IMUX_D1
FFC_SD_3inputCELL0.IMUX_D1
FFS_AB_ALIGNEDoutputCELL4.OUT_Q1
FFS_AB_FAILEDoutputCELL4.OUT_Q2
FFS_AB_STATUSoutputCELL4.OUT_Q0
FFS_CC_ORUN_0outputCELL4.OUT_F6
FFS_CC_ORUN_1outputCELL3.OUT_OFX4
FFS_CC_ORUN_2outputCELL1.OUT_OFX0
FFS_CC_ORUN_3outputCELL0.OUT_OFX6
FFS_CC_URUN_0outputCELL4.OUT_F7
FFS_CC_URUN_1outputCELL3.OUT_OFX5
FFS_CC_URUN_2outputCELL1.OUT_OFX1
FFS_CC_URUN_3outputCELL0.OUT_OFX7
FFS_CD_ALIGNEDoutputCELL1.OUT_OFX3
FFS_CD_FAILEDoutputCELL1.OUT_OFX4
FFS_CD_STATUSoutputCELL1.OUT_OFX2
FFS_LS_STATUS_0outputCELL4.OUT_F4
FFS_LS_STATUS_1outputCELL3.OUT_OFX2
FFS_LS_STATUS_2outputCELL1.OUT_Q7
FFS_LS_STATUS_3outputCELL1.OUT_OFX7
FFS_PCIE_CON_0outputCELL4.OUT_F2
FFS_PCIE_CON_1outputCELL3.OUT_OFX0
FFS_PCIE_CON_2outputCELL1.OUT_Q5
FFS_PCIE_CON_3outputCELL1.OUT_OFX5
FFS_PCIE_DONE_0outputCELL4.OUT_F3
FFS_PCIE_DONE_1outputCELL3.OUT_OFX1
FFS_PCIE_DONE_2outputCELL1.OUT_Q6
FFS_PCIE_DONE_3outputCELL1.OUT_OFX6
FFS_RLOS_LO0outputCELL4.OUT_Q3
FFS_RLOS_LO1outputCELL4.OUT_Q4
FFS_RLOS_LO2outputCELL2.OUT_OFX1
FFS_RLOS_LO3outputCELL2.OUT_OFX2
FF_RCLK0inputCELL5.IMUX_CLK1
FF_RCLK1inputCELL4.IMUX_CLK1
FF_RCLK2inputCELL1.IMUX_CLK1
FF_RCLK3inputCELL0.IMUX_CLK1
FF_RXCLK0outputCELL5.OUT_F1
FF_RXCLK1outputCELL4.OUT_Q7
FF_RXCLK2outputCELL2.OUT_F1
FF_RXCLK3outputCELL0.OUT_F1
FF_SYSCLK0outputCELL5.OUT_F0
FF_SYSCLK1outputCELL4.OUT_Q6
FF_SYSCLK2outputCELL2.OUT_F0
FF_SYSCLK3outputCELL0.OUT_F0
FF_TCLK0inputCELL5.IMUX_CLK0
FF_TCLK1inputCELL4.IMUX_CLK0
FF_TCLK2inputCELL1.IMUX_CLK0
FF_TCLK3inputCELL0.IMUX_CLK0
FF_TXD_0_0inputCELL5.IMUX_C7
FF_TXD_0_1inputCELL5.IMUX_C6
FF_TXD_0_10inputCELL5.IMUX_B5
FF_TXD_0_11inputCELL5.IMUX_B4
FF_TXD_0_12inputCELL5.IMUX_B3
FF_TXD_0_13inputCELL5.IMUX_B2
FF_TXD_0_14inputCELL5.IMUX_B1
FF_TXD_0_15inputCELL5.IMUX_B0
FF_TXD_0_16inputCELL5.IMUX_A7
FF_TXD_0_17inputCELL5.IMUX_A6
FF_TXD_0_18inputCELL5.IMUX_A5
FF_TXD_0_19inputCELL5.IMUX_A4
FF_TXD_0_2inputCELL5.IMUX_C5
FF_TXD_0_20inputCELL5.IMUX_A3
FF_TXD_0_21inputCELL5.IMUX_A2
FF_TXD_0_22inputCELL5.IMUX_A1
FF_TXD_0_23inputCELL5.IMUX_A0
FF_TXD_0_3inputCELL5.IMUX_C4
FF_TXD_0_4inputCELL5.IMUX_C3
FF_TXD_0_5inputCELL5.IMUX_C2
FF_TXD_0_6inputCELL5.IMUX_C1
FF_TXD_0_7inputCELL5.IMUX_C0
FF_TXD_0_8inputCELL5.IMUX_B7
FF_TXD_0_9inputCELL5.IMUX_B6
FF_TXD_1_0inputCELL4.IMUX_C7
FF_TXD_1_1inputCELL4.IMUX_C6
FF_TXD_1_10inputCELL4.IMUX_B5
FF_TXD_1_11inputCELL4.IMUX_B4
FF_TXD_1_12inputCELL4.IMUX_B3
FF_TXD_1_13inputCELL4.IMUX_B2
FF_TXD_1_14inputCELL4.IMUX_B1
FF_TXD_1_15inputCELL4.IMUX_B0
FF_TXD_1_16inputCELL4.IMUX_A7
FF_TXD_1_17inputCELL4.IMUX_A6
FF_TXD_1_18inputCELL4.IMUX_A5
FF_TXD_1_19inputCELL4.IMUX_A4
FF_TXD_1_2inputCELL4.IMUX_C5
FF_TXD_1_20inputCELL4.IMUX_A3
FF_TXD_1_21inputCELL4.IMUX_A2
FF_TXD_1_22inputCELL4.IMUX_A1
FF_TXD_1_23inputCELL4.IMUX_A0
FF_TXD_1_3inputCELL4.IMUX_C4
FF_TXD_1_4inputCELL4.IMUX_C3
FF_TXD_1_5inputCELL4.IMUX_C2
FF_TXD_1_6inputCELL4.IMUX_C1
FF_TXD_1_7inputCELL4.IMUX_C0
FF_TXD_1_8inputCELL4.IMUX_B7
FF_TXD_1_9inputCELL4.IMUX_B6
FF_TXD_2_0inputCELL1.IMUX_C7
FF_TXD_2_1inputCELL1.IMUX_C6
FF_TXD_2_10inputCELL1.IMUX_B5
FF_TXD_2_11inputCELL1.IMUX_B4
FF_TXD_2_12inputCELL1.IMUX_B3
FF_TXD_2_13inputCELL1.IMUX_B2
FF_TXD_2_14inputCELL1.IMUX_B1
FF_TXD_2_15inputCELL1.IMUX_B0
FF_TXD_2_16inputCELL1.IMUX_A7
FF_TXD_2_17inputCELL1.IMUX_A6
FF_TXD_2_18inputCELL1.IMUX_A5
FF_TXD_2_19inputCELL1.IMUX_A4
FF_TXD_2_2inputCELL1.IMUX_C5
FF_TXD_2_20inputCELL1.IMUX_A3
FF_TXD_2_21inputCELL1.IMUX_A2
FF_TXD_2_22inputCELL1.IMUX_A1
FF_TXD_2_23inputCELL1.IMUX_A0
FF_TXD_2_3inputCELL1.IMUX_C4
FF_TXD_2_4inputCELL1.IMUX_C3
FF_TXD_2_5inputCELL1.IMUX_C2
FF_TXD_2_6inputCELL1.IMUX_C1
FF_TXD_2_7inputCELL1.IMUX_C0
FF_TXD_2_8inputCELL1.IMUX_B7
FF_TXD_2_9inputCELL1.IMUX_B6
FF_TXD_3_0inputCELL0.IMUX_C7
FF_TXD_3_1inputCELL0.IMUX_C6
FF_TXD_3_10inputCELL0.IMUX_B5
FF_TXD_3_11inputCELL0.IMUX_B4
FF_TXD_3_12inputCELL0.IMUX_B3
FF_TXD_3_13inputCELL0.IMUX_B2
FF_TXD_3_14inputCELL0.IMUX_B1
FF_TXD_3_15inputCELL0.IMUX_B0
FF_TXD_3_16inputCELL0.IMUX_A7
FF_TXD_3_17inputCELL0.IMUX_A6
FF_TXD_3_18inputCELL0.IMUX_A5
FF_TXD_3_19inputCELL0.IMUX_A4
FF_TXD_3_2inputCELL0.IMUX_C5
FF_TXD_3_20inputCELL0.IMUX_A3
FF_TXD_3_21inputCELL0.IMUX_A2
FF_TXD_3_22inputCELL0.IMUX_A1
FF_TXD_3_23inputCELL0.IMUX_A0
FF_TXD_3_3inputCELL0.IMUX_C4
FF_TXD_3_4inputCELL0.IMUX_C3
FF_TXD_3_5inputCELL0.IMUX_C2
FF_TXD_3_6inputCELL0.IMUX_C1
FF_TXD_3_7inputCELL0.IMUX_C0
FF_TXD_3_8inputCELL0.IMUX_B7
FF_TXD_3_9inputCELL0.IMUX_B6

Bel wires

scm SERDES_E bel wires
WirePins
CELL0.IMUX_A0SERDES.FF_TXD_3_23
CELL0.IMUX_A1SERDES.FF_TXD_3_22
CELL0.IMUX_A2SERDES.FF_TXD_3_21
CELL0.IMUX_A3SERDES.FF_TXD_3_20
CELL0.IMUX_A4SERDES.FF_TXD_3_19
CELL0.IMUX_A5SERDES.FF_TXD_3_18
CELL0.IMUX_A6SERDES.FF_TXD_3_17
CELL0.IMUX_A7SERDES.FF_TXD_3_16
CELL0.IMUX_B0SERDES.FF_TXD_3_15
CELL0.IMUX_B1SERDES.FF_TXD_3_14
CELL0.IMUX_B2SERDES.FF_TXD_3_13
CELL0.IMUX_B3SERDES.FF_TXD_3_12
CELL0.IMUX_B4SERDES.FF_TXD_3_11
CELL0.IMUX_B5SERDES.FF_TXD_3_10
CELL0.IMUX_B6SERDES.FF_TXD_3_9
CELL0.IMUX_B7SERDES.FF_TXD_3_8
CELL0.IMUX_C0SERDES.FF_TXD_3_7
CELL0.IMUX_C1SERDES.FF_TXD_3_6
CELL0.IMUX_C2SERDES.FF_TXD_3_5
CELL0.IMUX_C3SERDES.FF_TXD_3_4
CELL0.IMUX_C4SERDES.FF_TXD_3_3
CELL0.IMUX_C5SERDES.FF_TXD_3_2
CELL0.IMUX_C6SERDES.FF_TXD_3_1
CELL0.IMUX_C7SERDES.FF_TXD_3_0
CELL0.IMUX_D0SERDES.FFC_PCIE_EI_EN_3
CELL0.IMUX_D1SERDES.FFC_SD_3
CELL0.IMUX_D2SERDES.FFC_EN_CGA_3
CELL0.IMUX_D3SERDES.FFC_ALIGN_EN_3
CELL0.IMUX_D4SERDES.FFC_FB_LB_3
CELL0.IMUX_D5SERDES.FFC_SB_INV_RX_3
CELL0.IMUX_D6SERDES.FFC_PCIE_CT_3
CELL0.IMUX_D7SERDES.FFC_PCIE_TX_3
CELL0.IMUX_CLK0SERDES.FF_TCLK3
CELL0.IMUX_CLK1SERDES.FF_RCLK3
CELL0.IMUX_CE1SERDES.FFC_LANE_TX_RST3
CELL0.IMUX_CE2SERDES.FFC_LANE_RX_RST3
CELL0.IMUX_CE3SERDES.FFC_CD_RESET
CELL0.OUT_F0SERDES.FF_SYSCLK3
CELL0.OUT_F1SERDES.FF_RXCLK3
CELL0.OUT_F2SERDES.FB_RXD_3_19
CELL0.OUT_F3SERDES.FB_RXD_3_18
CELL0.OUT_F4SERDES.FB_RXD_3_17
CELL0.OUT_F5SERDES.FB_RXD_3_16
CELL0.OUT_F6SERDES.FB_RXD_3_15
CELL0.OUT_F7SERDES.FB_RXD_3_14
CELL0.OUT_Q0SERDES.FB_RXD_3_13
CELL0.OUT_Q1SERDES.FB_RXD_3_12
CELL0.OUT_Q2SERDES.FB_RXD_3_11
CELL0.OUT_Q3SERDES.FB_RXD_3_10
CELL0.OUT_Q4SERDES.FB_RXD_3_9
CELL0.OUT_Q5SERDES.FB_RXD_3_8
CELL0.OUT_Q6SERDES.FB_RXD_3_7
CELL0.OUT_Q7SERDES.FB_RXD_3_6
CELL0.OUT_OFX0SERDES.FB_RXD_3_5
CELL0.OUT_OFX1SERDES.FB_RXD_3_4
CELL0.OUT_OFX2SERDES.FB_RXD_3_3
CELL0.OUT_OFX3SERDES.FB_RXD_3_2
CELL0.OUT_OFX4SERDES.FB_RXD_3_1
CELL0.OUT_OFX5SERDES.FB_RXD_3_0
CELL0.OUT_OFX6SERDES.FFS_CC_ORUN_3
CELL0.OUT_OFX7SERDES.FFS_CC_URUN_3
CELL1.IMUX_A0SERDES.FF_TXD_2_23
CELL1.IMUX_A1SERDES.FF_TXD_2_22
CELL1.IMUX_A2SERDES.FF_TXD_2_21
CELL1.IMUX_A3SERDES.FF_TXD_2_20
CELL1.IMUX_A4SERDES.FF_TXD_2_19
CELL1.IMUX_A5SERDES.FF_TXD_2_18
CELL1.IMUX_A6SERDES.FF_TXD_2_17
CELL1.IMUX_A7SERDES.FF_TXD_2_16
CELL1.IMUX_B0SERDES.FF_TXD_2_15
CELL1.IMUX_B1SERDES.FF_TXD_2_14
CELL1.IMUX_B2SERDES.FF_TXD_2_13
CELL1.IMUX_B3SERDES.FF_TXD_2_12
CELL1.IMUX_B4SERDES.FF_TXD_2_11
CELL1.IMUX_B5SERDES.FF_TXD_2_10
CELL1.IMUX_B6SERDES.FF_TXD_2_9
CELL1.IMUX_B7SERDES.FF_TXD_2_8
CELL1.IMUX_C0SERDES.FF_TXD_2_7
CELL1.IMUX_C1SERDES.FF_TXD_2_6
CELL1.IMUX_C2SERDES.FF_TXD_2_5
CELL1.IMUX_C3SERDES.FF_TXD_2_4
CELL1.IMUX_C4SERDES.FF_TXD_2_3
CELL1.IMUX_C5SERDES.FF_TXD_2_2
CELL1.IMUX_C6SERDES.FF_TXD_2_1
CELL1.IMUX_C7SERDES.FF_TXD_2_0
CELL1.IMUX_D0SERDES.FFC_PCIE_EI_EN_2
CELL1.IMUX_D1SERDES.FFC_SD_2
CELL1.IMUX_D2SERDES.FFC_EN_CGA_2
CELL1.IMUX_D3SERDES.FFC_ALIGN_EN_2
CELL1.IMUX_D4SERDES.FFC_FB_LB_2
CELL1.IMUX_D5SERDES.FFC_SB_INV_RX_2
CELL1.IMUX_D6SERDES.FFC_PCIE_CT_2
CELL1.IMUX_D7SERDES.FFC_PCIE_TX_2
CELL1.IMUX_CLK0SERDES.FF_TCLK2
CELL1.IMUX_CLK1SERDES.FF_RCLK2
CELL1.IMUX_CE1SERDES.FFC_LANE_TX_RST2
CELL1.IMUX_CE2SERDES.FFC_LANE_RX_RST2
CELL1.OUT_F0SERDES.FB_RXD_2_8
CELL1.OUT_F1SERDES.FB_RXD_2_7
CELL1.OUT_F2SERDES.FB_RXD_2_6
CELL1.OUT_F3SERDES.FB_RXD_2_5
CELL1.OUT_F4SERDES.FB_RXD_2_4
CELL1.OUT_F5SERDES.FB_RXD_2_3
CELL1.OUT_F6SERDES.FB_RXD_2_2
CELL1.OUT_F7SERDES.FB_RXD_2_1
CELL1.OUT_Q0SERDES.FB_RXD_2_0
CELL1.OUT_Q1SERDES.FB_RXD_3_23
CELL1.OUT_Q2SERDES.FB_RXD_3_22
CELL1.OUT_Q3SERDES.FB_RXD_3_21
CELL1.OUT_Q4SERDES.FB_RXD_3_20
CELL1.OUT_Q5SERDES.FFS_PCIE_CON_2
CELL1.OUT_Q6SERDES.FFS_PCIE_DONE_2
CELL1.OUT_Q7SERDES.FFS_LS_STATUS_2
CELL1.OUT_OFX0SERDES.FFS_CC_ORUN_2
CELL1.OUT_OFX1SERDES.FFS_CC_URUN_2
CELL1.OUT_OFX2SERDES.FFS_CD_STATUS
CELL1.OUT_OFX3SERDES.FFS_CD_ALIGNED
CELL1.OUT_OFX4SERDES.FFS_CD_FAILED
CELL1.OUT_OFX5SERDES.FFS_PCIE_CON_3
CELL1.OUT_OFX6SERDES.FFS_PCIE_DONE_3
CELL1.OUT_OFX7SERDES.FFS_LS_STATUS_3
CELL2.IMUX_D0SERDES.FFC_PCIE_RX_0
CELL2.IMUX_D1SERDES.FFC_PCIE_RX_1
CELL2.IMUX_D6SERDES.FFC_PCIE_RX_2
CELL2.IMUX_D7SERDES.FFC_PCIE_RX_3
CELL2.IMUX_CLK1SERDES.FFC_CK_CORE_RX
CELL2.IMUX_LSR0SERDES.FFC_QUAD_RST
CELL2.IMUX_CE3SERDES.FFC_MACRO_RST
CELL2.OUT_F0SERDES.FF_SYSCLK2
CELL2.OUT_F1SERDES.FF_RXCLK2
CELL2.OUT_F2SERDES.FB_RXD_2_23
CELL2.OUT_F3SERDES.FB_RXD_2_22
CELL2.OUT_F4SERDES.FB_RXD_2_21
CELL2.OUT_F5SERDES.FB_RXD_2_20
CELL2.OUT_F6SERDES.FB_RXD_2_19
CELL2.OUT_F7SERDES.FB_RXD_2_18
CELL2.OUT_Q0SERDES.FB_RXD_2_17
CELL2.OUT_Q1SERDES.FB_RXD_2_16
CELL2.OUT_Q2SERDES.FB_RXD_2_15
CELL2.OUT_Q3SERDES.FB_RXD_2_14
CELL2.OUT_Q4SERDES.FB_RXD_2_13
CELL2.OUT_Q5SERDES.FB_RXD_2_12
CELL2.OUT_Q6SERDES.FB_RXD_2_11
CELL2.OUT_Q7SERDES.FB_RXD_2_10
CELL2.OUT_OFX0SERDES.FB_RXD_2_9
CELL2.OUT_OFX1SERDES.FFS_RLOS_LO2
CELL2.OUT_OFX2SERDES.FFS_RLOS_LO3
CELL2.OUT_OFX4SERDES.BS4PAD_3
CELL2.OUT_OFX5SERDES.BS4PAD_2
CELL2.OUT_OFX6SERDES.BS4PAD_1
CELL2.OUT_OFX7SERDES.BS4PAD_0
CELL3.OUT_F0SERDES.FB_RXD_1_15
CELL3.OUT_F1SERDES.FB_RXD_1_14
CELL3.OUT_F2SERDES.FB_RXD_1_13
CELL3.OUT_F3SERDES.FB_RXD_1_12
CELL3.OUT_F4SERDES.FB_RXD_1_11
CELL3.OUT_F5SERDES.FB_RXD_1_10
CELL3.OUT_F6SERDES.FB_RXD_1_9
CELL3.OUT_F7SERDES.FB_RXD_1_8
CELL3.OUT_Q0SERDES.FB_RXD_1_7
CELL3.OUT_Q1SERDES.FB_RXD_1_6
CELL3.OUT_Q2SERDES.FB_RXD_1_5
CELL3.OUT_Q3SERDES.FB_RXD_1_4
CELL3.OUT_Q4SERDES.FB_RXD_1_3
CELL3.OUT_Q5SERDES.FB_RXD_1_2
CELL3.OUT_Q6SERDES.FB_RXD_1_1
CELL3.OUT_Q7SERDES.FB_RXD_1_0
CELL3.OUT_OFX0SERDES.FFS_PCIE_CON_1
CELL3.OUT_OFX1SERDES.FFS_PCIE_DONE_1
CELL3.OUT_OFX2SERDES.FFS_LS_STATUS_1
CELL3.OUT_OFX4SERDES.FFS_CC_ORUN_1
CELL3.OUT_OFX5SERDES.FFS_CC_URUN_1
CELL4.IMUX_A0SERDES.FF_TXD_1_23
CELL4.IMUX_A1SERDES.FF_TXD_1_22
CELL4.IMUX_A2SERDES.FF_TXD_1_21
CELL4.IMUX_A3SERDES.FF_TXD_1_20
CELL4.IMUX_A4SERDES.FF_TXD_1_19
CELL4.IMUX_A5SERDES.FF_TXD_1_18
CELL4.IMUX_A6SERDES.FF_TXD_1_17
CELL4.IMUX_A7SERDES.FF_TXD_1_16
CELL4.IMUX_B0SERDES.FF_TXD_1_15
CELL4.IMUX_B1SERDES.FF_TXD_1_14
CELL4.IMUX_B2SERDES.FF_TXD_1_13
CELL4.IMUX_B3SERDES.FF_TXD_1_12
CELL4.IMUX_B4SERDES.FF_TXD_1_11
CELL4.IMUX_B5SERDES.FF_TXD_1_10
CELL4.IMUX_B6SERDES.FF_TXD_1_9
CELL4.IMUX_B7SERDES.FF_TXD_1_8
CELL4.IMUX_C0SERDES.FF_TXD_1_7
CELL4.IMUX_C1SERDES.FF_TXD_1_6
CELL4.IMUX_C2SERDES.FF_TXD_1_5
CELL4.IMUX_C3SERDES.FF_TXD_1_4
CELL4.IMUX_C4SERDES.FF_TXD_1_3
CELL4.IMUX_C5SERDES.FF_TXD_1_2
CELL4.IMUX_C6SERDES.FF_TXD_1_1
CELL4.IMUX_C7SERDES.FF_TXD_1_0
CELL4.IMUX_D0SERDES.FFC_PCIE_EI_EN_1
CELL4.IMUX_D1SERDES.FFC_SD_1
CELL4.IMUX_D2SERDES.FFC_EN_CGA_1
CELL4.IMUX_D3SERDES.FFC_ALIGN_EN_1
CELL4.IMUX_D4SERDES.FFC_FB_LB_1
CELL4.IMUX_D5SERDES.FFC_SB_INV_RX_1
CELL4.IMUX_D6SERDES.FFC_PCIE_CT_1
CELL4.IMUX_D7SERDES.FFC_PCIE_TX_1
CELL4.IMUX_CLK0SERDES.FF_TCLK1
CELL4.IMUX_CLK1SERDES.FF_RCLK1
CELL4.IMUX_CE1SERDES.FFC_LANE_TX_RST1
CELL4.IMUX_CE2SERDES.FFC_LANE_RX_RST1
CELL4.OUT_F0SERDES.FB_RXD_0_1
CELL4.OUT_F1SERDES.FB_RXD_0_0
CELL4.OUT_F2SERDES.FFS_PCIE_CON_0
CELL4.OUT_F3SERDES.FFS_PCIE_DONE_0
CELL4.OUT_F4SERDES.FFS_LS_STATUS_0
CELL4.OUT_F6SERDES.FFS_CC_ORUN_0
CELL4.OUT_F7SERDES.FFS_CC_URUN_0
CELL4.OUT_Q0SERDES.FFS_AB_STATUS
CELL4.OUT_Q1SERDES.FFS_AB_ALIGNED
CELL4.OUT_Q2SERDES.FFS_AB_FAILED
CELL4.OUT_Q3SERDES.FFS_RLOS_LO0
CELL4.OUT_Q4SERDES.FFS_RLOS_LO1
CELL4.OUT_Q6SERDES.FF_SYSCLK1
CELL4.OUT_Q7SERDES.FF_RXCLK1
CELL4.OUT_OFX0SERDES.FB_RXD_1_23
CELL4.OUT_OFX1SERDES.FB_RXD_1_22
CELL4.OUT_OFX2SERDES.FB_RXD_1_21
CELL4.OUT_OFX3SERDES.FB_RXD_1_20
CELL4.OUT_OFX4SERDES.FB_RXD_1_19
CELL4.OUT_OFX5SERDES.FB_RXD_1_18
CELL4.OUT_OFX6SERDES.FB_RXD_1_17
CELL4.OUT_OFX7SERDES.FB_RXD_1_16
CELL5.IMUX_A0SERDES.FF_TXD_0_23
CELL5.IMUX_A1SERDES.FF_TXD_0_22
CELL5.IMUX_A2SERDES.FF_TXD_0_21
CELL5.IMUX_A3SERDES.FF_TXD_0_20
CELL5.IMUX_A4SERDES.FF_TXD_0_19
CELL5.IMUX_A5SERDES.FF_TXD_0_18
CELL5.IMUX_A6SERDES.FF_TXD_0_17
CELL5.IMUX_A7SERDES.FF_TXD_0_16
CELL5.IMUX_B0SERDES.FF_TXD_0_15
CELL5.IMUX_B1SERDES.FF_TXD_0_14
CELL5.IMUX_B2SERDES.FF_TXD_0_13
CELL5.IMUX_B3SERDES.FF_TXD_0_12
CELL5.IMUX_B4SERDES.FF_TXD_0_11
CELL5.IMUX_B5SERDES.FF_TXD_0_10
CELL5.IMUX_B6SERDES.FF_TXD_0_9
CELL5.IMUX_B7SERDES.FF_TXD_0_8
CELL5.IMUX_C0SERDES.FF_TXD_0_7
CELL5.IMUX_C1SERDES.FF_TXD_0_6
CELL5.IMUX_C2SERDES.FF_TXD_0_5
CELL5.IMUX_C3SERDES.FF_TXD_0_4
CELL5.IMUX_C4SERDES.FF_TXD_0_3
CELL5.IMUX_C5SERDES.FF_TXD_0_2
CELL5.IMUX_C6SERDES.FF_TXD_0_1
CELL5.IMUX_C7SERDES.FF_TXD_0_0
CELL5.IMUX_D0SERDES.FFC_PCIE_EI_EN_0
CELL5.IMUX_D1SERDES.FFC_SD_0
CELL5.IMUX_D2SERDES.FFC_EN_CGA_0
CELL5.IMUX_D3SERDES.FFC_ALIGN_EN_0
CELL5.IMUX_D4SERDES.FFC_FB_LB_0
CELL5.IMUX_D5SERDES.FFC_SB_INV_RX_0
CELL5.IMUX_D6SERDES.FFC_PCIE_CT_0
CELL5.IMUX_D7SERDES.FFC_PCIE_TX_0
CELL5.IMUX_CLK0SERDES.FF_TCLK0
CELL5.IMUX_CLK1SERDES.FF_RCLK0
CELL5.IMUX_CE1SERDES.FFC_LANE_TX_RST0
CELL5.IMUX_CE2SERDES.FFC_LANE_RX_RST0
CELL5.IMUX_CE3SERDES.FFC_AB_RESET
CELL5.OUT_F0SERDES.FF_SYSCLK0
CELL5.OUT_F1SERDES.FF_RXCLK0
CELL5.OUT_F2SERDES.FB_RXD_0_23
CELL5.OUT_F3SERDES.FB_RXD_0_22
CELL5.OUT_F4SERDES.FB_RXD_0_21
CELL5.OUT_F5SERDES.FB_RXD_0_20
CELL5.OUT_F6SERDES.FB_RXD_0_19
CELL5.OUT_F7SERDES.FB_RXD_0_18
CELL5.OUT_Q0SERDES.FB_RXD_0_17
CELL5.OUT_Q1SERDES.FB_RXD_0_16
CELL5.OUT_Q2SERDES.FB_RXD_0_15
CELL5.OUT_Q3SERDES.FB_RXD_0_14
CELL5.OUT_Q4SERDES.FB_RXD_0_13
CELL5.OUT_Q5SERDES.FB_RXD_0_12
CELL5.OUT_Q6SERDES.FB_RXD_0_11
CELL5.OUT_Q7SERDES.FB_RXD_0_10
CELL5.OUT_OFX0SERDES.FB_RXD_0_9
CELL5.OUT_OFX1SERDES.FB_RXD_0_8
CELL5.OUT_OFX2SERDES.FB_RXD_0_7
CELL5.OUT_OFX3SERDES.FB_RXD_0_6
CELL5.OUT_OFX4SERDES.FB_RXD_0_5
CELL5.OUT_OFX5SERDES.FB_RXD_0_4
CELL5.OUT_OFX6SERDES.FB_RXD_0_3
CELL5.OUT_OFX7SERDES.FB_RXD_0_2