Cells: 7
scm SERDES_W bel SERDES
| Pin | Direction | Wires |
|---|
| BS4PAD_0 | output | TCELL4:OUT_OFX0 |
| BS4PAD_1 | output | TCELL4:OUT_OFX1 |
| BS4PAD_2 | output | TCELL4:OUT_OFX2 |
| BS4PAD_3 | output | TCELL4:OUT_OFX3 |
| FB_RXD_0_0 | output | TCELL2:OUT_F6 |
| FB_RXD_0_1 | output | TCELL2:OUT_F7 |
| FB_RXD_0_10 | output | TCELL1:OUT_Q0 |
| FB_RXD_0_11 | output | TCELL1:OUT_Q1 |
| FB_RXD_0_12 | output | TCELL1:OUT_Q2 |
| FB_RXD_0_13 | output | TCELL1:OUT_Q3 |
| FB_RXD_0_14 | output | TCELL1:OUT_Q4 |
| FB_RXD_0_15 | output | TCELL1:OUT_Q5 |
| FB_RXD_0_16 | output | TCELL1:OUT_Q6 |
| FB_RXD_0_17 | output | TCELL1:OUT_Q7 |
| FB_RXD_0_18 | output | TCELL1:OUT_F0 |
| FB_RXD_0_19 | output | TCELL1:OUT_F1 |
| FB_RXD_0_2 | output | TCELL1:OUT_OFX0 |
| FB_RXD_0_20 | output | TCELL1:OUT_F2 |
| FB_RXD_0_21 | output | TCELL1:OUT_F3 |
| FB_RXD_0_22 | output | TCELL1:OUT_F4 |
| FB_RXD_0_23 | output | TCELL1:OUT_F5 |
| FB_RXD_0_3 | output | TCELL1:OUT_OFX1 |
| FB_RXD_0_4 | output | TCELL1:OUT_OFX2 |
| FB_RXD_0_5 | output | TCELL1:OUT_OFX3 |
| FB_RXD_0_6 | output | TCELL1:OUT_OFX4 |
| FB_RXD_0_7 | output | TCELL1:OUT_OFX5 |
| FB_RXD_0_8 | output | TCELL1:OUT_OFX6 |
| FB_RXD_0_9 | output | TCELL1:OUT_OFX7 |
| FB_RXD_1_0 | output | TCELL3:OUT_Q0 |
| FB_RXD_1_1 | output | TCELL3:OUT_Q1 |
| FB_RXD_1_10 | output | TCELL3:OUT_F2 |
| FB_RXD_1_11 | output | TCELL3:OUT_F3 |
| FB_RXD_1_12 | output | TCELL3:OUT_F4 |
| FB_RXD_1_13 | output | TCELL3:OUT_F5 |
| FB_RXD_1_14 | output | TCELL3:OUT_F6 |
| FB_RXD_1_15 | output | TCELL3:OUT_F7 |
| FB_RXD_1_16 | output | TCELL2:OUT_OFX0 |
| FB_RXD_1_17 | output | TCELL2:OUT_OFX1 |
| FB_RXD_1_18 | output | TCELL2:OUT_OFX2 |
| FB_RXD_1_19 | output | TCELL2:OUT_OFX3 |
| FB_RXD_1_2 | output | TCELL3:OUT_Q2 |
| FB_RXD_1_20 | output | TCELL2:OUT_OFX4 |
| FB_RXD_1_21 | output | TCELL2:OUT_OFX5 |
| FB_RXD_1_22 | output | TCELL2:OUT_OFX6 |
| FB_RXD_1_23 | output | TCELL2:OUT_OFX7 |
| FB_RXD_1_3 | output | TCELL3:OUT_Q3 |
| FB_RXD_1_4 | output | TCELL3:OUT_Q4 |
| FB_RXD_1_5 | output | TCELL3:OUT_Q5 |
| FB_RXD_1_6 | output | TCELL3:OUT_Q6 |
| FB_RXD_1_7 | output | TCELL3:OUT_Q7 |
| FB_RXD_1_8 | output | TCELL3:OUT_F0 |
| FB_RXD_1_9 | output | TCELL3:OUT_F1 |
| FB_RXD_2_0 | output | TCELL5:OUT_Q7 |
| FB_RXD_2_1 | output | TCELL5:OUT_F0 |
| FB_RXD_2_10 | output | TCELL4:OUT_Q0 |
| FB_RXD_2_11 | output | TCELL4:OUT_Q1 |
| FB_RXD_2_12 | output | TCELL4:OUT_Q2 |
| FB_RXD_2_13 | output | TCELL4:OUT_Q3 |
| FB_RXD_2_14 | output | TCELL4:OUT_Q4 |
| FB_RXD_2_15 | output | TCELL4:OUT_Q5 |
| FB_RXD_2_16 | output | TCELL4:OUT_Q6 |
| FB_RXD_2_17 | output | TCELL4:OUT_Q7 |
| FB_RXD_2_18 | output | TCELL4:OUT_F0 |
| FB_RXD_2_19 | output | TCELL4:OUT_F1 |
| FB_RXD_2_2 | output | TCELL5:OUT_F1 |
| FB_RXD_2_20 | output | TCELL4:OUT_F2 |
| FB_RXD_2_21 | output | TCELL4:OUT_F3 |
| FB_RXD_2_22 | output | TCELL4:OUT_F4 |
| FB_RXD_2_23 | output | TCELL4:OUT_F5 |
| FB_RXD_2_3 | output | TCELL5:OUT_F2 |
| FB_RXD_2_4 | output | TCELL5:OUT_F3 |
| FB_RXD_2_5 | output | TCELL5:OUT_F4 |
| FB_RXD_2_6 | output | TCELL5:OUT_F5 |
| FB_RXD_2_7 | output | TCELL5:OUT_F6 |
| FB_RXD_2_8 | output | TCELL5:OUT_F7 |
| FB_RXD_2_9 | output | TCELL4:OUT_OFX7 |
| FB_RXD_3_0 | output | TCELL6:OUT_OFX2 |
| FB_RXD_3_1 | output | TCELL6:OUT_OFX3 |
| FB_RXD_3_10 | output | TCELL6:OUT_Q4 |
| FB_RXD_3_11 | output | TCELL6:OUT_Q5 |
| FB_RXD_3_12 | output | TCELL6:OUT_Q6 |
| FB_RXD_3_13 | output | TCELL6:OUT_Q7 |
| FB_RXD_3_14 | output | TCELL6:OUT_F0 |
| FB_RXD_3_15 | output | TCELL6:OUT_F1 |
| FB_RXD_3_16 | output | TCELL6:OUT_F2 |
| FB_RXD_3_17 | output | TCELL6:OUT_F3 |
| FB_RXD_3_18 | output | TCELL6:OUT_F4 |
| FB_RXD_3_19 | output | TCELL6:OUT_F5 |
| FB_RXD_3_2 | output | TCELL6:OUT_OFX4 |
| FB_RXD_3_20 | output | TCELL5:OUT_Q3 |
| FB_RXD_3_21 | output | TCELL5:OUT_Q4 |
| FB_RXD_3_22 | output | TCELL5:OUT_Q5 |
| FB_RXD_3_23 | output | TCELL5:OUT_Q6 |
| FB_RXD_3_3 | output | TCELL6:OUT_OFX5 |
| FB_RXD_3_4 | output | TCELL6:OUT_OFX6 |
| FB_RXD_3_5 | output | TCELL6:OUT_OFX7 |
| FB_RXD_3_6 | output | TCELL6:OUT_Q0 |
| FB_RXD_3_7 | output | TCELL6:OUT_Q1 |
| FB_RXD_3_8 | output | TCELL6:OUT_Q2 |
| FB_RXD_3_9 | output | TCELL6:OUT_Q3 |
| FFC_AB_RESET | input | TCELL1:IMUX_CE0 |
| FFC_ALIGN_EN_0 | input | TCELL1:IMUX_D4 |
| FFC_ALIGN_EN_1 | input | TCELL2:IMUX_D4 |
| FFC_ALIGN_EN_2 | input | TCELL5:IMUX_D4 |
| FFC_ALIGN_EN_3 | input | TCELL6:IMUX_D4 |
| FFC_CD_RESET | input | TCELL6:IMUX_CE0 |
| FFC_CK_CORE_RX | input | TCELL4:IMUX_CLK2 |
| FFC_EN_CGA_0 | input | TCELL1:IMUX_D5 |
| FFC_EN_CGA_1 | input | TCELL2:IMUX_D5 |
| FFC_EN_CGA_2 | input | TCELL5:IMUX_D5 |
| FFC_EN_CGA_3 | input | TCELL6:IMUX_D5 |
| FFC_FB_LB_0 | input | TCELL1:IMUX_D3 |
| FFC_FB_LB_1 | input | TCELL2:IMUX_D3 |
| FFC_FB_LB_2 | input | TCELL5:IMUX_D3 |
| FFC_FB_LB_3 | input | TCELL6:IMUX_D3 |
| FFC_LANE_RX_RST0 | input | TCELL1:IMUX_CE1 |
| FFC_LANE_RX_RST1 | input | TCELL2:IMUX_CE1 |
| FFC_LANE_RX_RST2 | input | TCELL5:IMUX_CE1 |
| FFC_LANE_RX_RST3 | input | TCELL6:IMUX_CE1 |
| FFC_LANE_TX_RST0 | input | TCELL1:IMUX_CE2 |
| FFC_LANE_TX_RST1 | input | TCELL2:IMUX_CE2 |
| FFC_LANE_TX_RST2 | input | TCELL5:IMUX_CE2 |
| FFC_LANE_TX_RST3 | input | TCELL6:IMUX_CE2 |
| FFC_MACRO_RST | input | TCELL4:IMUX_CE0 |
| FFC_PCIE_CT_0 | input | TCELL1:IMUX_D1 |
| FFC_PCIE_CT_1 | input | TCELL2:IMUX_D1 |
| FFC_PCIE_CT_2 | input | TCELL5:IMUX_D1 |
| FFC_PCIE_CT_3 | input | TCELL6:IMUX_D1 |
| FFC_PCIE_EI_EN_0 | input | TCELL1:IMUX_D7 |
| FFC_PCIE_EI_EN_1 | input | TCELL2:IMUX_D7 |
| FFC_PCIE_EI_EN_2 | input | TCELL5:IMUX_D7 |
| FFC_PCIE_EI_EN_3 | input | TCELL6:IMUX_D7 |
| FFC_PCIE_RX_0 | input | TCELL4:IMUX_D7 |
| FFC_PCIE_RX_1 | input | TCELL4:IMUX_D6 |
| FFC_PCIE_RX_2 | input | TCELL4:IMUX_D1 |
| FFC_PCIE_RX_3 | input | TCELL4:IMUX_D0 |
| FFC_PCIE_TX_0 | input | TCELL1:IMUX_D0 |
| FFC_PCIE_TX_1 | input | TCELL2:IMUX_D0 |
| FFC_PCIE_TX_2 | input | TCELL5:IMUX_D0 |
| FFC_PCIE_TX_3 | input | TCELL6:IMUX_D0 |
| FFC_QUAD_RST | input | TCELL4:IMUX_LSR3 |
| FFC_SB_INV_RX_0 | input | TCELL1:IMUX_D2 |
| FFC_SB_INV_RX_1 | input | TCELL2:IMUX_D2 |
| FFC_SB_INV_RX_2 | input | TCELL5:IMUX_D2 |
| FFC_SB_INV_RX_3 | input | TCELL6:IMUX_D2 |
| FFC_SD_0 | input | TCELL1:IMUX_D6 |
| FFC_SD_1 | input | TCELL2:IMUX_D6 |
| FFC_SD_2 | input | TCELL5:IMUX_D6 |
| FFC_SD_3 | input | TCELL6:IMUX_D6 |
| FFS_AB_ALIGNED | output | TCELL2:OUT_Q6 |
| FFS_AB_FAILED | output | TCELL2:OUT_Q5 |
| FFS_AB_STATUS | output | TCELL2:OUT_Q7 |
| FFS_CC_ORUN_0 | output | TCELL2:OUT_F1 |
| FFS_CC_ORUN_1 | output | TCELL3:OUT_OFX3 |
| FFS_CC_ORUN_2 | output | TCELL5:OUT_OFX7 |
| FFS_CC_ORUN_3 | output | TCELL6:OUT_OFX1 |
| FFS_CC_URUN_0 | output | TCELL2:OUT_F0 |
| FFS_CC_URUN_1 | output | TCELL3:OUT_OFX2 |
| FFS_CC_URUN_2 | output | TCELL5:OUT_OFX6 |
| FFS_CC_URUN_3 | output | TCELL6:OUT_OFX0 |
| FFS_CD_ALIGNED | output | TCELL5:OUT_OFX4 |
| FFS_CD_FAILED | output | TCELL5:OUT_OFX3 |
| FFS_CD_STATUS | output | TCELL5:OUT_OFX5 |
| FFS_LS_STATUS_0 | output | TCELL2:OUT_F3 |
| FFS_LS_STATUS_1 | output | TCELL3:OUT_OFX5 |
| FFS_LS_STATUS_2 | output | TCELL5:OUT_Q0 |
| FFS_LS_STATUS_3 | output | TCELL5:OUT_OFX0 |
| FFS_PCIE_CON_0 | output | TCELL2:OUT_F5 |
| FFS_PCIE_CON_1 | output | TCELL3:OUT_OFX7 |
| FFS_PCIE_CON_2 | output | TCELL5:OUT_Q2 |
| FFS_PCIE_CON_3 | output | TCELL5:OUT_OFX2 |
| FFS_PCIE_DONE_0 | output | TCELL2:OUT_F4 |
| FFS_PCIE_DONE_1 | output | TCELL3:OUT_OFX6 |
| FFS_PCIE_DONE_2 | output | TCELL5:OUT_Q1 |
| FFS_PCIE_DONE_3 | output | TCELL5:OUT_OFX1 |
| FFS_RLOS_LO0 | output | TCELL2:OUT_Q4 |
| FFS_RLOS_LO1 | output | TCELL2:OUT_Q3 |
| FFS_RLOS_LO2 | output | TCELL4:OUT_OFX6 |
| FFS_RLOS_LO3 | output | TCELL4:OUT_OFX5 |
| FF_RCLK0 | input | TCELL1:IMUX_CLK2 |
| FF_RCLK1 | input | TCELL2:IMUX_CLK2 |
| FF_RCLK2 | input | TCELL5:IMUX_CLK2 |
| FF_RCLK3 | input | TCELL6:IMUX_CLK2 |
| FF_RXCLK0 | output | TCELL1:OUT_F6 |
| FF_RXCLK1 | output | TCELL2:OUT_Q0 |
| FF_RXCLK2 | output | TCELL4:OUT_F6 |
| FF_RXCLK3 | output | TCELL6:OUT_F6 |
| FF_SYSCLK0 | output | TCELL1:OUT_F7 |
| FF_SYSCLK1 | output | TCELL2:OUT_Q1 |
| FF_SYSCLK2 | output | TCELL4:OUT_F7 |
| FF_SYSCLK3 | output | TCELL6:OUT_F7 |
| FF_TCLK0 | input | TCELL1:IMUX_CLK3 |
| FF_TCLK1 | input | TCELL2:IMUX_CLK3 |
| FF_TCLK2 | input | TCELL5:IMUX_CLK3 |
| FF_TCLK3 | input | TCELL6:IMUX_CLK3 |
| FF_TXD_0_0 | input | TCELL1:IMUX_C0 |
| FF_TXD_0_1 | input | TCELL1:IMUX_C1 |
| FF_TXD_0_10 | input | TCELL1:IMUX_B2 |
| FF_TXD_0_11 | input | TCELL1:IMUX_B3 |
| FF_TXD_0_12 | input | TCELL1:IMUX_B4 |
| FF_TXD_0_13 | input | TCELL1:IMUX_B5 |
| FF_TXD_0_14 | input | TCELL1:IMUX_B6 |
| FF_TXD_0_15 | input | TCELL1:IMUX_B7 |
| FF_TXD_0_16 | input | TCELL1:IMUX_A0 |
| FF_TXD_0_17 | input | TCELL1:IMUX_A1 |
| FF_TXD_0_18 | input | TCELL1:IMUX_A2 |
| FF_TXD_0_19 | input | TCELL1:IMUX_A3 |
| FF_TXD_0_2 | input | TCELL1:IMUX_C2 |
| FF_TXD_0_20 | input | TCELL1:IMUX_A4 |
| FF_TXD_0_21 | input | TCELL1:IMUX_A5 |
| FF_TXD_0_22 | input | TCELL1:IMUX_A6 |
| FF_TXD_0_23 | input | TCELL1:IMUX_A7 |
| FF_TXD_0_3 | input | TCELL1:IMUX_C3 |
| FF_TXD_0_4 | input | TCELL1:IMUX_C4 |
| FF_TXD_0_5 | input | TCELL1:IMUX_C5 |
| FF_TXD_0_6 | input | TCELL1:IMUX_C6 |
| FF_TXD_0_7 | input | TCELL1:IMUX_C7 |
| FF_TXD_0_8 | input | TCELL1:IMUX_B0 |
| FF_TXD_0_9 | input | TCELL1:IMUX_B1 |
| FF_TXD_1_0 | input | TCELL2:IMUX_C0 |
| FF_TXD_1_1 | input | TCELL2:IMUX_C1 |
| FF_TXD_1_10 | input | TCELL2:IMUX_B2 |
| FF_TXD_1_11 | input | TCELL2:IMUX_B3 |
| FF_TXD_1_12 | input | TCELL2:IMUX_B4 |
| FF_TXD_1_13 | input | TCELL2:IMUX_B5 |
| FF_TXD_1_14 | input | TCELL2:IMUX_B6 |
| FF_TXD_1_15 | input | TCELL2:IMUX_B7 |
| FF_TXD_1_16 | input | TCELL2:IMUX_A0 |
| FF_TXD_1_17 | input | TCELL2:IMUX_A1 |
| FF_TXD_1_18 | input | TCELL2:IMUX_A2 |
| FF_TXD_1_19 | input | TCELL2:IMUX_A3 |
| FF_TXD_1_2 | input | TCELL2:IMUX_C2 |
| FF_TXD_1_20 | input | TCELL2:IMUX_A4 |
| FF_TXD_1_21 | input | TCELL2:IMUX_A5 |
| FF_TXD_1_22 | input | TCELL2:IMUX_A6 |
| FF_TXD_1_23 | input | TCELL2:IMUX_A7 |
| FF_TXD_1_3 | input | TCELL2:IMUX_C3 |
| FF_TXD_1_4 | input | TCELL2:IMUX_C4 |
| FF_TXD_1_5 | input | TCELL2:IMUX_C5 |
| FF_TXD_1_6 | input | TCELL2:IMUX_C6 |
| FF_TXD_1_7 | input | TCELL2:IMUX_C7 |
| FF_TXD_1_8 | input | TCELL2:IMUX_B0 |
| FF_TXD_1_9 | input | TCELL2:IMUX_B1 |
| FF_TXD_2_0 | input | TCELL5:IMUX_C0 |
| FF_TXD_2_1 | input | TCELL5:IMUX_C1 |
| FF_TXD_2_10 | input | TCELL5:IMUX_B2 |
| FF_TXD_2_11 | input | TCELL5:IMUX_B3 |
| FF_TXD_2_12 | input | TCELL5:IMUX_B4 |
| FF_TXD_2_13 | input | TCELL5:IMUX_B5 |
| FF_TXD_2_14 | input | TCELL5:IMUX_B6 |
| FF_TXD_2_15 | input | TCELL5:IMUX_B7 |
| FF_TXD_2_16 | input | TCELL5:IMUX_A0 |
| FF_TXD_2_17 | input | TCELL5:IMUX_A1 |
| FF_TXD_2_18 | input | TCELL5:IMUX_A2 |
| FF_TXD_2_19 | input | TCELL5:IMUX_A3 |
| FF_TXD_2_2 | input | TCELL5:IMUX_C2 |
| FF_TXD_2_20 | input | TCELL5:IMUX_A4 |
| FF_TXD_2_21 | input | TCELL5:IMUX_A5 |
| FF_TXD_2_22 | input | TCELL5:IMUX_A6 |
| FF_TXD_2_23 | input | TCELL5:IMUX_A7 |
| FF_TXD_2_3 | input | TCELL5:IMUX_C3 |
| FF_TXD_2_4 | input | TCELL5:IMUX_C4 |
| FF_TXD_2_5 | input | TCELL5:IMUX_C5 |
| FF_TXD_2_6 | input | TCELL5:IMUX_C6 |
| FF_TXD_2_7 | input | TCELL5:IMUX_C7 |
| FF_TXD_2_8 | input | TCELL5:IMUX_B0 |
| FF_TXD_2_9 | input | TCELL5:IMUX_B1 |
| FF_TXD_3_0 | input | TCELL6:IMUX_C0 |
| FF_TXD_3_1 | input | TCELL6:IMUX_C1 |
| FF_TXD_3_10 | input | TCELL6:IMUX_B2 |
| FF_TXD_3_11 | input | TCELL6:IMUX_B3 |
| FF_TXD_3_12 | input | TCELL6:IMUX_B4 |
| FF_TXD_3_13 | input | TCELL6:IMUX_B5 |
| FF_TXD_3_14 | input | TCELL6:IMUX_B6 |
| FF_TXD_3_15 | input | TCELL6:IMUX_B7 |
| FF_TXD_3_16 | input | TCELL6:IMUX_A0 |
| FF_TXD_3_17 | input | TCELL6:IMUX_A1 |
| FF_TXD_3_18 | input | TCELL6:IMUX_A2 |
| FF_TXD_3_19 | input | TCELL6:IMUX_A3 |
| FF_TXD_3_2 | input | TCELL6:IMUX_C2 |
| FF_TXD_3_20 | input | TCELL6:IMUX_A4 |
| FF_TXD_3_21 | input | TCELL6:IMUX_A5 |
| FF_TXD_3_22 | input | TCELL6:IMUX_A6 |
| FF_TXD_3_23 | input | TCELL6:IMUX_A7 |
| FF_TXD_3_3 | input | TCELL6:IMUX_C3 |
| FF_TXD_3_4 | input | TCELL6:IMUX_C4 |
| FF_TXD_3_5 | input | TCELL6:IMUX_C5 |
| FF_TXD_3_6 | input | TCELL6:IMUX_C6 |
| FF_TXD_3_7 | input | TCELL6:IMUX_C7 |
| FF_TXD_3_8 | input | TCELL6:IMUX_B0 |
| FF_TXD_3_9 | input | TCELL6:IMUX_B1 |
scm SERDES_W bel wires
| Wire | Pins |
|---|
| TCELL1:IMUX_A0 | SERDES.FF_TXD_0_16 |
| TCELL1:IMUX_A1 | SERDES.FF_TXD_0_17 |
| TCELL1:IMUX_A2 | SERDES.FF_TXD_0_18 |
| TCELL1:IMUX_A3 | SERDES.FF_TXD_0_19 |
| TCELL1:IMUX_A4 | SERDES.FF_TXD_0_20 |
| TCELL1:IMUX_A5 | SERDES.FF_TXD_0_21 |
| TCELL1:IMUX_A6 | SERDES.FF_TXD_0_22 |
| TCELL1:IMUX_A7 | SERDES.FF_TXD_0_23 |
| TCELL1:IMUX_B0 | SERDES.FF_TXD_0_8 |
| TCELL1:IMUX_B1 | SERDES.FF_TXD_0_9 |
| TCELL1:IMUX_B2 | SERDES.FF_TXD_0_10 |
| TCELL1:IMUX_B3 | SERDES.FF_TXD_0_11 |
| TCELL1:IMUX_B4 | SERDES.FF_TXD_0_12 |
| TCELL1:IMUX_B5 | SERDES.FF_TXD_0_13 |
| TCELL1:IMUX_B6 | SERDES.FF_TXD_0_14 |
| TCELL1:IMUX_B7 | SERDES.FF_TXD_0_15 |
| TCELL1:IMUX_C0 | SERDES.FF_TXD_0_0 |
| TCELL1:IMUX_C1 | SERDES.FF_TXD_0_1 |
| TCELL1:IMUX_C2 | SERDES.FF_TXD_0_2 |
| TCELL1:IMUX_C3 | SERDES.FF_TXD_0_3 |
| TCELL1:IMUX_C4 | SERDES.FF_TXD_0_4 |
| TCELL1:IMUX_C5 | SERDES.FF_TXD_0_5 |
| TCELL1:IMUX_C6 | SERDES.FF_TXD_0_6 |
| TCELL1:IMUX_C7 | SERDES.FF_TXD_0_7 |
| TCELL1:IMUX_D0 | SERDES.FFC_PCIE_TX_0 |
| TCELL1:IMUX_D1 | SERDES.FFC_PCIE_CT_0 |
| TCELL1:IMUX_D2 | SERDES.FFC_SB_INV_RX_0 |
| TCELL1:IMUX_D3 | SERDES.FFC_FB_LB_0 |
| TCELL1:IMUX_D4 | SERDES.FFC_ALIGN_EN_0 |
| TCELL1:IMUX_D5 | SERDES.FFC_EN_CGA_0 |
| TCELL1:IMUX_D6 | SERDES.FFC_SD_0 |
| TCELL1:IMUX_D7 | SERDES.FFC_PCIE_EI_EN_0 |
| TCELL1:IMUX_CLK2 | SERDES.FF_RCLK0 |
| TCELL1:IMUX_CLK3 | SERDES.FF_TCLK0 |
| TCELL1:IMUX_CE0 | SERDES.FFC_AB_RESET |
| TCELL1:IMUX_CE1 | SERDES.FFC_LANE_RX_RST0 |
| TCELL1:IMUX_CE2 | SERDES.FFC_LANE_TX_RST0 |
| TCELL1:OUT_F0 | SERDES.FB_RXD_0_18 |
| TCELL1:OUT_F1 | SERDES.FB_RXD_0_19 |
| TCELL1:OUT_F2 | SERDES.FB_RXD_0_20 |
| TCELL1:OUT_F3 | SERDES.FB_RXD_0_21 |
| TCELL1:OUT_F4 | SERDES.FB_RXD_0_22 |
| TCELL1:OUT_F5 | SERDES.FB_RXD_0_23 |
| TCELL1:OUT_F6 | SERDES.FF_RXCLK0 |
| TCELL1:OUT_F7 | SERDES.FF_SYSCLK0 |
| TCELL1:OUT_Q0 | SERDES.FB_RXD_0_10 |
| TCELL1:OUT_Q1 | SERDES.FB_RXD_0_11 |
| TCELL1:OUT_Q2 | SERDES.FB_RXD_0_12 |
| TCELL1:OUT_Q3 | SERDES.FB_RXD_0_13 |
| TCELL1:OUT_Q4 | SERDES.FB_RXD_0_14 |
| TCELL1:OUT_Q5 | SERDES.FB_RXD_0_15 |
| TCELL1:OUT_Q6 | SERDES.FB_RXD_0_16 |
| TCELL1:OUT_Q7 | SERDES.FB_RXD_0_17 |
| TCELL1:OUT_OFX0 | SERDES.FB_RXD_0_2 |
| TCELL1:OUT_OFX1 | SERDES.FB_RXD_0_3 |
| TCELL1:OUT_OFX2 | SERDES.FB_RXD_0_4 |
| TCELL1:OUT_OFX3 | SERDES.FB_RXD_0_5 |
| TCELL1:OUT_OFX4 | SERDES.FB_RXD_0_6 |
| TCELL1:OUT_OFX5 | SERDES.FB_RXD_0_7 |
| TCELL1:OUT_OFX6 | SERDES.FB_RXD_0_8 |
| TCELL1:OUT_OFX7 | SERDES.FB_RXD_0_9 |
| TCELL2:IMUX_A0 | SERDES.FF_TXD_1_16 |
| TCELL2:IMUX_A1 | SERDES.FF_TXD_1_17 |
| TCELL2:IMUX_A2 | SERDES.FF_TXD_1_18 |
| TCELL2:IMUX_A3 | SERDES.FF_TXD_1_19 |
| TCELL2:IMUX_A4 | SERDES.FF_TXD_1_20 |
| TCELL2:IMUX_A5 | SERDES.FF_TXD_1_21 |
| TCELL2:IMUX_A6 | SERDES.FF_TXD_1_22 |
| TCELL2:IMUX_A7 | SERDES.FF_TXD_1_23 |
| TCELL2:IMUX_B0 | SERDES.FF_TXD_1_8 |
| TCELL2:IMUX_B1 | SERDES.FF_TXD_1_9 |
| TCELL2:IMUX_B2 | SERDES.FF_TXD_1_10 |
| TCELL2:IMUX_B3 | SERDES.FF_TXD_1_11 |
| TCELL2:IMUX_B4 | SERDES.FF_TXD_1_12 |
| TCELL2:IMUX_B5 | SERDES.FF_TXD_1_13 |
| TCELL2:IMUX_B6 | SERDES.FF_TXD_1_14 |
| TCELL2:IMUX_B7 | SERDES.FF_TXD_1_15 |
| TCELL2:IMUX_C0 | SERDES.FF_TXD_1_0 |
| TCELL2:IMUX_C1 | SERDES.FF_TXD_1_1 |
| TCELL2:IMUX_C2 | SERDES.FF_TXD_1_2 |
| TCELL2:IMUX_C3 | SERDES.FF_TXD_1_3 |
| TCELL2:IMUX_C4 | SERDES.FF_TXD_1_4 |
| TCELL2:IMUX_C5 | SERDES.FF_TXD_1_5 |
| TCELL2:IMUX_C6 | SERDES.FF_TXD_1_6 |
| TCELL2:IMUX_C7 | SERDES.FF_TXD_1_7 |
| TCELL2:IMUX_D0 | SERDES.FFC_PCIE_TX_1 |
| TCELL2:IMUX_D1 | SERDES.FFC_PCIE_CT_1 |
| TCELL2:IMUX_D2 | SERDES.FFC_SB_INV_RX_1 |
| TCELL2:IMUX_D3 | SERDES.FFC_FB_LB_1 |
| TCELL2:IMUX_D4 | SERDES.FFC_ALIGN_EN_1 |
| TCELL2:IMUX_D5 | SERDES.FFC_EN_CGA_1 |
| TCELL2:IMUX_D6 | SERDES.FFC_SD_1 |
| TCELL2:IMUX_D7 | SERDES.FFC_PCIE_EI_EN_1 |
| TCELL2:IMUX_CLK2 | SERDES.FF_RCLK1 |
| TCELL2:IMUX_CLK3 | SERDES.FF_TCLK1 |
| TCELL2:IMUX_CE1 | SERDES.FFC_LANE_RX_RST1 |
| TCELL2:IMUX_CE2 | SERDES.FFC_LANE_TX_RST1 |
| TCELL2:OUT_F0 | SERDES.FFS_CC_URUN_0 |
| TCELL2:OUT_F1 | SERDES.FFS_CC_ORUN_0 |
| TCELL2:OUT_F3 | SERDES.FFS_LS_STATUS_0 |
| TCELL2:OUT_F4 | SERDES.FFS_PCIE_DONE_0 |
| TCELL2:OUT_F5 | SERDES.FFS_PCIE_CON_0 |
| TCELL2:OUT_F6 | SERDES.FB_RXD_0_0 |
| TCELL2:OUT_F7 | SERDES.FB_RXD_0_1 |
| TCELL2:OUT_Q0 | SERDES.FF_RXCLK1 |
| TCELL2:OUT_Q1 | SERDES.FF_SYSCLK1 |
| TCELL2:OUT_Q3 | SERDES.FFS_RLOS_LO1 |
| TCELL2:OUT_Q4 | SERDES.FFS_RLOS_LO0 |
| TCELL2:OUT_Q5 | SERDES.FFS_AB_FAILED |
| TCELL2:OUT_Q6 | SERDES.FFS_AB_ALIGNED |
| TCELL2:OUT_Q7 | SERDES.FFS_AB_STATUS |
| TCELL2:OUT_OFX0 | SERDES.FB_RXD_1_16 |
| TCELL2:OUT_OFX1 | SERDES.FB_RXD_1_17 |
| TCELL2:OUT_OFX2 | SERDES.FB_RXD_1_18 |
| TCELL2:OUT_OFX3 | SERDES.FB_RXD_1_19 |
| TCELL2:OUT_OFX4 | SERDES.FB_RXD_1_20 |
| TCELL2:OUT_OFX5 | SERDES.FB_RXD_1_21 |
| TCELL2:OUT_OFX6 | SERDES.FB_RXD_1_22 |
| TCELL2:OUT_OFX7 | SERDES.FB_RXD_1_23 |
| TCELL3:OUT_F0 | SERDES.FB_RXD_1_8 |
| TCELL3:OUT_F1 | SERDES.FB_RXD_1_9 |
| TCELL3:OUT_F2 | SERDES.FB_RXD_1_10 |
| TCELL3:OUT_F3 | SERDES.FB_RXD_1_11 |
| TCELL3:OUT_F4 | SERDES.FB_RXD_1_12 |
| TCELL3:OUT_F5 | SERDES.FB_RXD_1_13 |
| TCELL3:OUT_F6 | SERDES.FB_RXD_1_14 |
| TCELL3:OUT_F7 | SERDES.FB_RXD_1_15 |
| TCELL3:OUT_Q0 | SERDES.FB_RXD_1_0 |
| TCELL3:OUT_Q1 | SERDES.FB_RXD_1_1 |
| TCELL3:OUT_Q2 | SERDES.FB_RXD_1_2 |
| TCELL3:OUT_Q3 | SERDES.FB_RXD_1_3 |
| TCELL3:OUT_Q4 | SERDES.FB_RXD_1_4 |
| TCELL3:OUT_Q5 | SERDES.FB_RXD_1_5 |
| TCELL3:OUT_Q6 | SERDES.FB_RXD_1_6 |
| TCELL3:OUT_Q7 | SERDES.FB_RXD_1_7 |
| TCELL3:OUT_OFX2 | SERDES.FFS_CC_URUN_1 |
| TCELL3:OUT_OFX3 | SERDES.FFS_CC_ORUN_1 |
| TCELL3:OUT_OFX5 | SERDES.FFS_LS_STATUS_1 |
| TCELL3:OUT_OFX6 | SERDES.FFS_PCIE_DONE_1 |
| TCELL3:OUT_OFX7 | SERDES.FFS_PCIE_CON_1 |
| TCELL4:IMUX_D0 | SERDES.FFC_PCIE_RX_3 |
| TCELL4:IMUX_D1 | SERDES.FFC_PCIE_RX_2 |
| TCELL4:IMUX_D6 | SERDES.FFC_PCIE_RX_1 |
| TCELL4:IMUX_D7 | SERDES.FFC_PCIE_RX_0 |
| TCELL4:IMUX_CLK2 | SERDES.FFC_CK_CORE_RX |
| TCELL4:IMUX_LSR3 | SERDES.FFC_QUAD_RST |
| TCELL4:IMUX_CE0 | SERDES.FFC_MACRO_RST |
| TCELL4:OUT_F0 | SERDES.FB_RXD_2_18 |
| TCELL4:OUT_F1 | SERDES.FB_RXD_2_19 |
| TCELL4:OUT_F2 | SERDES.FB_RXD_2_20 |
| TCELL4:OUT_F3 | SERDES.FB_RXD_2_21 |
| TCELL4:OUT_F4 | SERDES.FB_RXD_2_22 |
| TCELL4:OUT_F5 | SERDES.FB_RXD_2_23 |
| TCELL4:OUT_F6 | SERDES.FF_RXCLK2 |
| TCELL4:OUT_F7 | SERDES.FF_SYSCLK2 |
| TCELL4:OUT_Q0 | SERDES.FB_RXD_2_10 |
| TCELL4:OUT_Q1 | SERDES.FB_RXD_2_11 |
| TCELL4:OUT_Q2 | SERDES.FB_RXD_2_12 |
| TCELL4:OUT_Q3 | SERDES.FB_RXD_2_13 |
| TCELL4:OUT_Q4 | SERDES.FB_RXD_2_14 |
| TCELL4:OUT_Q5 | SERDES.FB_RXD_2_15 |
| TCELL4:OUT_Q6 | SERDES.FB_RXD_2_16 |
| TCELL4:OUT_Q7 | SERDES.FB_RXD_2_17 |
| TCELL4:OUT_OFX0 | SERDES.BS4PAD_0 |
| TCELL4:OUT_OFX1 | SERDES.BS4PAD_1 |
| TCELL4:OUT_OFX2 | SERDES.BS4PAD_2 |
| TCELL4:OUT_OFX3 | SERDES.BS4PAD_3 |
| TCELL4:OUT_OFX5 | SERDES.FFS_RLOS_LO3 |
| TCELL4:OUT_OFX6 | SERDES.FFS_RLOS_LO2 |
| TCELL4:OUT_OFX7 | SERDES.FB_RXD_2_9 |
| TCELL5:IMUX_A0 | SERDES.FF_TXD_2_16 |
| TCELL5:IMUX_A1 | SERDES.FF_TXD_2_17 |
| TCELL5:IMUX_A2 | SERDES.FF_TXD_2_18 |
| TCELL5:IMUX_A3 | SERDES.FF_TXD_2_19 |
| TCELL5:IMUX_A4 | SERDES.FF_TXD_2_20 |
| TCELL5:IMUX_A5 | SERDES.FF_TXD_2_21 |
| TCELL5:IMUX_A6 | SERDES.FF_TXD_2_22 |
| TCELL5:IMUX_A7 | SERDES.FF_TXD_2_23 |
| TCELL5:IMUX_B0 | SERDES.FF_TXD_2_8 |
| TCELL5:IMUX_B1 | SERDES.FF_TXD_2_9 |
| TCELL5:IMUX_B2 | SERDES.FF_TXD_2_10 |
| TCELL5:IMUX_B3 | SERDES.FF_TXD_2_11 |
| TCELL5:IMUX_B4 | SERDES.FF_TXD_2_12 |
| TCELL5:IMUX_B5 | SERDES.FF_TXD_2_13 |
| TCELL5:IMUX_B6 | SERDES.FF_TXD_2_14 |
| TCELL5:IMUX_B7 | SERDES.FF_TXD_2_15 |
| TCELL5:IMUX_C0 | SERDES.FF_TXD_2_0 |
| TCELL5:IMUX_C1 | SERDES.FF_TXD_2_1 |
| TCELL5:IMUX_C2 | SERDES.FF_TXD_2_2 |
| TCELL5:IMUX_C3 | SERDES.FF_TXD_2_3 |
| TCELL5:IMUX_C4 | SERDES.FF_TXD_2_4 |
| TCELL5:IMUX_C5 | SERDES.FF_TXD_2_5 |
| TCELL5:IMUX_C6 | SERDES.FF_TXD_2_6 |
| TCELL5:IMUX_C7 | SERDES.FF_TXD_2_7 |
| TCELL5:IMUX_D0 | SERDES.FFC_PCIE_TX_2 |
| TCELL5:IMUX_D1 | SERDES.FFC_PCIE_CT_2 |
| TCELL5:IMUX_D2 | SERDES.FFC_SB_INV_RX_2 |
| TCELL5:IMUX_D3 | SERDES.FFC_FB_LB_2 |
| TCELL5:IMUX_D4 | SERDES.FFC_ALIGN_EN_2 |
| TCELL5:IMUX_D5 | SERDES.FFC_EN_CGA_2 |
| TCELL5:IMUX_D6 | SERDES.FFC_SD_2 |
| TCELL5:IMUX_D7 | SERDES.FFC_PCIE_EI_EN_2 |
| TCELL5:IMUX_CLK2 | SERDES.FF_RCLK2 |
| TCELL5:IMUX_CLK3 | SERDES.FF_TCLK2 |
| TCELL5:IMUX_CE1 | SERDES.FFC_LANE_RX_RST2 |
| TCELL5:IMUX_CE2 | SERDES.FFC_LANE_TX_RST2 |
| TCELL5:OUT_F0 | SERDES.FB_RXD_2_1 |
| TCELL5:OUT_F1 | SERDES.FB_RXD_2_2 |
| TCELL5:OUT_F2 | SERDES.FB_RXD_2_3 |
| TCELL5:OUT_F3 | SERDES.FB_RXD_2_4 |
| TCELL5:OUT_F4 | SERDES.FB_RXD_2_5 |
| TCELL5:OUT_F5 | SERDES.FB_RXD_2_6 |
| TCELL5:OUT_F6 | SERDES.FB_RXD_2_7 |
| TCELL5:OUT_F7 | SERDES.FB_RXD_2_8 |
| TCELL5:OUT_Q0 | SERDES.FFS_LS_STATUS_2 |
| TCELL5:OUT_Q1 | SERDES.FFS_PCIE_DONE_2 |
| TCELL5:OUT_Q2 | SERDES.FFS_PCIE_CON_2 |
| TCELL5:OUT_Q3 | SERDES.FB_RXD_3_20 |
| TCELL5:OUT_Q4 | SERDES.FB_RXD_3_21 |
| TCELL5:OUT_Q5 | SERDES.FB_RXD_3_22 |
| TCELL5:OUT_Q6 | SERDES.FB_RXD_3_23 |
| TCELL5:OUT_Q7 | SERDES.FB_RXD_2_0 |
| TCELL5:OUT_OFX0 | SERDES.FFS_LS_STATUS_3 |
| TCELL5:OUT_OFX1 | SERDES.FFS_PCIE_DONE_3 |
| TCELL5:OUT_OFX2 | SERDES.FFS_PCIE_CON_3 |
| TCELL5:OUT_OFX3 | SERDES.FFS_CD_FAILED |
| TCELL5:OUT_OFX4 | SERDES.FFS_CD_ALIGNED |
| TCELL5:OUT_OFX5 | SERDES.FFS_CD_STATUS |
| TCELL5:OUT_OFX6 | SERDES.FFS_CC_URUN_2 |
| TCELL5:OUT_OFX7 | SERDES.FFS_CC_ORUN_2 |
| TCELL6:IMUX_A0 | SERDES.FF_TXD_3_16 |
| TCELL6:IMUX_A1 | SERDES.FF_TXD_3_17 |
| TCELL6:IMUX_A2 | SERDES.FF_TXD_3_18 |
| TCELL6:IMUX_A3 | SERDES.FF_TXD_3_19 |
| TCELL6:IMUX_A4 | SERDES.FF_TXD_3_20 |
| TCELL6:IMUX_A5 | SERDES.FF_TXD_3_21 |
| TCELL6:IMUX_A6 | SERDES.FF_TXD_3_22 |
| TCELL6:IMUX_A7 | SERDES.FF_TXD_3_23 |
| TCELL6:IMUX_B0 | SERDES.FF_TXD_3_8 |
| TCELL6:IMUX_B1 | SERDES.FF_TXD_3_9 |
| TCELL6:IMUX_B2 | SERDES.FF_TXD_3_10 |
| TCELL6:IMUX_B3 | SERDES.FF_TXD_3_11 |
| TCELL6:IMUX_B4 | SERDES.FF_TXD_3_12 |
| TCELL6:IMUX_B5 | SERDES.FF_TXD_3_13 |
| TCELL6:IMUX_B6 | SERDES.FF_TXD_3_14 |
| TCELL6:IMUX_B7 | SERDES.FF_TXD_3_15 |
| TCELL6:IMUX_C0 | SERDES.FF_TXD_3_0 |
| TCELL6:IMUX_C1 | SERDES.FF_TXD_3_1 |
| TCELL6:IMUX_C2 | SERDES.FF_TXD_3_2 |
| TCELL6:IMUX_C3 | SERDES.FF_TXD_3_3 |
| TCELL6:IMUX_C4 | SERDES.FF_TXD_3_4 |
| TCELL6:IMUX_C5 | SERDES.FF_TXD_3_5 |
| TCELL6:IMUX_C6 | SERDES.FF_TXD_3_6 |
| TCELL6:IMUX_C7 | SERDES.FF_TXD_3_7 |
| TCELL6:IMUX_D0 | SERDES.FFC_PCIE_TX_3 |
| TCELL6:IMUX_D1 | SERDES.FFC_PCIE_CT_3 |
| TCELL6:IMUX_D2 | SERDES.FFC_SB_INV_RX_3 |
| TCELL6:IMUX_D3 | SERDES.FFC_FB_LB_3 |
| TCELL6:IMUX_D4 | SERDES.FFC_ALIGN_EN_3 |
| TCELL6:IMUX_D5 | SERDES.FFC_EN_CGA_3 |
| TCELL6:IMUX_D6 | SERDES.FFC_SD_3 |
| TCELL6:IMUX_D7 | SERDES.FFC_PCIE_EI_EN_3 |
| TCELL6:IMUX_CLK2 | SERDES.FF_RCLK3 |
| TCELL6:IMUX_CLK3 | SERDES.FF_TCLK3 |
| TCELL6:IMUX_CE0 | SERDES.FFC_CD_RESET |
| TCELL6:IMUX_CE1 | SERDES.FFC_LANE_RX_RST3 |
| TCELL6:IMUX_CE2 | SERDES.FFC_LANE_TX_RST3 |
| TCELL6:OUT_F0 | SERDES.FB_RXD_3_14 |
| TCELL6:OUT_F1 | SERDES.FB_RXD_3_15 |
| TCELL6:OUT_F2 | SERDES.FB_RXD_3_16 |
| TCELL6:OUT_F3 | SERDES.FB_RXD_3_17 |
| TCELL6:OUT_F4 | SERDES.FB_RXD_3_18 |
| TCELL6:OUT_F5 | SERDES.FB_RXD_3_19 |
| TCELL6:OUT_F6 | SERDES.FF_RXCLK3 |
| TCELL6:OUT_F7 | SERDES.FF_SYSCLK3 |
| TCELL6:OUT_Q0 | SERDES.FB_RXD_3_6 |
| TCELL6:OUT_Q1 | SERDES.FB_RXD_3_7 |
| TCELL6:OUT_Q2 | SERDES.FB_RXD_3_8 |
| TCELL6:OUT_Q3 | SERDES.FB_RXD_3_9 |
| TCELL6:OUT_Q4 | SERDES.FB_RXD_3_10 |
| TCELL6:OUT_Q5 | SERDES.FB_RXD_3_11 |
| TCELL6:OUT_Q6 | SERDES.FB_RXD_3_12 |
| TCELL6:OUT_Q7 | SERDES.FB_RXD_3_13 |
| TCELL6:OUT_OFX0 | SERDES.FFS_CC_URUN_3 |
| TCELL6:OUT_OFX1 | SERDES.FFS_CC_ORUN_3 |
| TCELL6:OUT_OFX2 | SERDES.FB_RXD_3_0 |
| TCELL6:OUT_OFX3 | SERDES.FB_RXD_3_1 |
| TCELL6:OUT_OFX4 | SERDES.FB_RXD_3_2 |
| TCELL6:OUT_OFX5 | SERDES.FB_RXD_3_3 |
| TCELL6:OUT_OFX6 | SERDES.FB_RXD_3_4 |
| TCELL6:OUT_OFX7 | SERDES.FB_RXD_3_5 |
Cells: 7
scm SERDES_E bel SERDES
| Pin | Direction | Wires |
|---|
| BS4PAD_0 | output | TCELL2:OUT_OFX7 |
| BS4PAD_1 | output | TCELL2:OUT_OFX6 |
| BS4PAD_2 | output | TCELL2:OUT_OFX5 |
| BS4PAD_3 | output | TCELL2:OUT_OFX4 |
| FB_RXD_0_0 | output | TCELL4:OUT_F1 |
| FB_RXD_0_1 | output | TCELL4:OUT_F0 |
| FB_RXD_0_10 | output | TCELL5:OUT_Q7 |
| FB_RXD_0_11 | output | TCELL5:OUT_Q6 |
| FB_RXD_0_12 | output | TCELL5:OUT_Q5 |
| FB_RXD_0_13 | output | TCELL5:OUT_Q4 |
| FB_RXD_0_14 | output | TCELL5:OUT_Q3 |
| FB_RXD_0_15 | output | TCELL5:OUT_Q2 |
| FB_RXD_0_16 | output | TCELL5:OUT_Q1 |
| FB_RXD_0_17 | output | TCELL5:OUT_Q0 |
| FB_RXD_0_18 | output | TCELL5:OUT_F7 |
| FB_RXD_0_19 | output | TCELL5:OUT_F6 |
| FB_RXD_0_2 | output | TCELL5:OUT_OFX7 |
| FB_RXD_0_20 | output | TCELL5:OUT_F5 |
| FB_RXD_0_21 | output | TCELL5:OUT_F4 |
| FB_RXD_0_22 | output | TCELL5:OUT_F3 |
| FB_RXD_0_23 | output | TCELL5:OUT_F2 |
| FB_RXD_0_3 | output | TCELL5:OUT_OFX6 |
| FB_RXD_0_4 | output | TCELL5:OUT_OFX5 |
| FB_RXD_0_5 | output | TCELL5:OUT_OFX4 |
| FB_RXD_0_6 | output | TCELL5:OUT_OFX3 |
| FB_RXD_0_7 | output | TCELL5:OUT_OFX2 |
| FB_RXD_0_8 | output | TCELL5:OUT_OFX1 |
| FB_RXD_0_9 | output | TCELL5:OUT_OFX0 |
| FB_RXD_1_0 | output | TCELL3:OUT_Q7 |
| FB_RXD_1_1 | output | TCELL3:OUT_Q6 |
| FB_RXD_1_10 | output | TCELL3:OUT_F5 |
| FB_RXD_1_11 | output | TCELL3:OUT_F4 |
| FB_RXD_1_12 | output | TCELL3:OUT_F3 |
| FB_RXD_1_13 | output | TCELL3:OUT_F2 |
| FB_RXD_1_14 | output | TCELL3:OUT_F1 |
| FB_RXD_1_15 | output | TCELL3:OUT_F0 |
| FB_RXD_1_16 | output | TCELL4:OUT_OFX7 |
| FB_RXD_1_17 | output | TCELL4:OUT_OFX6 |
| FB_RXD_1_18 | output | TCELL4:OUT_OFX5 |
| FB_RXD_1_19 | output | TCELL4:OUT_OFX4 |
| FB_RXD_1_2 | output | TCELL3:OUT_Q5 |
| FB_RXD_1_20 | output | TCELL4:OUT_OFX3 |
| FB_RXD_1_21 | output | TCELL4:OUT_OFX2 |
| FB_RXD_1_22 | output | TCELL4:OUT_OFX1 |
| FB_RXD_1_23 | output | TCELL4:OUT_OFX0 |
| FB_RXD_1_3 | output | TCELL3:OUT_Q4 |
| FB_RXD_1_4 | output | TCELL3:OUT_Q3 |
| FB_RXD_1_5 | output | TCELL3:OUT_Q2 |
| FB_RXD_1_6 | output | TCELL3:OUT_Q1 |
| FB_RXD_1_7 | output | TCELL3:OUT_Q0 |
| FB_RXD_1_8 | output | TCELL3:OUT_F7 |
| FB_RXD_1_9 | output | TCELL3:OUT_F6 |
| FB_RXD_2_0 | output | TCELL1:OUT_Q0 |
| FB_RXD_2_1 | output | TCELL1:OUT_F7 |
| FB_RXD_2_10 | output | TCELL2:OUT_Q7 |
| FB_RXD_2_11 | output | TCELL2:OUT_Q6 |
| FB_RXD_2_12 | output | TCELL2:OUT_Q5 |
| FB_RXD_2_13 | output | TCELL2:OUT_Q4 |
| FB_RXD_2_14 | output | TCELL2:OUT_Q3 |
| FB_RXD_2_15 | output | TCELL2:OUT_Q2 |
| FB_RXD_2_16 | output | TCELL2:OUT_Q1 |
| FB_RXD_2_17 | output | TCELL2:OUT_Q0 |
| FB_RXD_2_18 | output | TCELL2:OUT_F7 |
| FB_RXD_2_19 | output | TCELL2:OUT_F6 |
| FB_RXD_2_2 | output | TCELL1:OUT_F6 |
| FB_RXD_2_20 | output | TCELL2:OUT_F5 |
| FB_RXD_2_21 | output | TCELL2:OUT_F4 |
| FB_RXD_2_22 | output | TCELL2:OUT_F3 |
| FB_RXD_2_23 | output | TCELL2:OUT_F2 |
| FB_RXD_2_3 | output | TCELL1:OUT_F5 |
| FB_RXD_2_4 | output | TCELL1:OUT_F4 |
| FB_RXD_2_5 | output | TCELL1:OUT_F3 |
| FB_RXD_2_6 | output | TCELL1:OUT_F2 |
| FB_RXD_2_7 | output | TCELL1:OUT_F1 |
| FB_RXD_2_8 | output | TCELL1:OUT_F0 |
| FB_RXD_2_9 | output | TCELL2:OUT_OFX0 |
| FB_RXD_3_0 | output | TCELL0:OUT_OFX5 |
| FB_RXD_3_1 | output | TCELL0:OUT_OFX4 |
| FB_RXD_3_10 | output | TCELL0:OUT_Q3 |
| FB_RXD_3_11 | output | TCELL0:OUT_Q2 |
| FB_RXD_3_12 | output | TCELL0:OUT_Q1 |
| FB_RXD_3_13 | output | TCELL0:OUT_Q0 |
| FB_RXD_3_14 | output | TCELL0:OUT_F7 |
| FB_RXD_3_15 | output | TCELL0:OUT_F6 |
| FB_RXD_3_16 | output | TCELL0:OUT_F5 |
| FB_RXD_3_17 | output | TCELL0:OUT_F4 |
| FB_RXD_3_18 | output | TCELL0:OUT_F3 |
| FB_RXD_3_19 | output | TCELL0:OUT_F2 |
| FB_RXD_3_2 | output | TCELL0:OUT_OFX3 |
| FB_RXD_3_20 | output | TCELL1:OUT_Q4 |
| FB_RXD_3_21 | output | TCELL1:OUT_Q3 |
| FB_RXD_3_22 | output | TCELL1:OUT_Q2 |
| FB_RXD_3_23 | output | TCELL1:OUT_Q1 |
| FB_RXD_3_3 | output | TCELL0:OUT_OFX2 |
| FB_RXD_3_4 | output | TCELL0:OUT_OFX1 |
| FB_RXD_3_5 | output | TCELL0:OUT_OFX0 |
| FB_RXD_3_6 | output | TCELL0:OUT_Q7 |
| FB_RXD_3_7 | output | TCELL0:OUT_Q6 |
| FB_RXD_3_8 | output | TCELL0:OUT_Q5 |
| FB_RXD_3_9 | output | TCELL0:OUT_Q4 |
| FFC_AB_RESET | input | TCELL5:IMUX_CE3 |
| FFC_ALIGN_EN_0 | input | TCELL5:IMUX_D3 |
| FFC_ALIGN_EN_1 | input | TCELL4:IMUX_D3 |
| FFC_ALIGN_EN_2 | input | TCELL1:IMUX_D3 |
| FFC_ALIGN_EN_3 | input | TCELL0:IMUX_D3 |
| FFC_CD_RESET | input | TCELL0:IMUX_CE3 |
| FFC_CK_CORE_RX | input | TCELL2:IMUX_CLK1 |
| FFC_EN_CGA_0 | input | TCELL5:IMUX_D2 |
| FFC_EN_CGA_1 | input | TCELL4:IMUX_D2 |
| FFC_EN_CGA_2 | input | TCELL1:IMUX_D2 |
| FFC_EN_CGA_3 | input | TCELL0:IMUX_D2 |
| FFC_FB_LB_0 | input | TCELL5:IMUX_D4 |
| FFC_FB_LB_1 | input | TCELL4:IMUX_D4 |
| FFC_FB_LB_2 | input | TCELL1:IMUX_D4 |
| FFC_FB_LB_3 | input | TCELL0:IMUX_D4 |
| FFC_LANE_RX_RST0 | input | TCELL5:IMUX_CE2 |
| FFC_LANE_RX_RST1 | input | TCELL4:IMUX_CE2 |
| FFC_LANE_RX_RST2 | input | TCELL1:IMUX_CE2 |
| FFC_LANE_RX_RST3 | input | TCELL0:IMUX_CE2 |
| FFC_LANE_TX_RST0 | input | TCELL5:IMUX_CE1 |
| FFC_LANE_TX_RST1 | input | TCELL4:IMUX_CE1 |
| FFC_LANE_TX_RST2 | input | TCELL1:IMUX_CE1 |
| FFC_LANE_TX_RST3 | input | TCELL0:IMUX_CE1 |
| FFC_MACRO_RST | input | TCELL2:IMUX_CE3 |
| FFC_PCIE_CT_0 | input | TCELL5:IMUX_D6 |
| FFC_PCIE_CT_1 | input | TCELL4:IMUX_D6 |
| FFC_PCIE_CT_2 | input | TCELL1:IMUX_D6 |
| FFC_PCIE_CT_3 | input | TCELL0:IMUX_D6 |
| FFC_PCIE_EI_EN_0 | input | TCELL5:IMUX_D0 |
| FFC_PCIE_EI_EN_1 | input | TCELL4:IMUX_D0 |
| FFC_PCIE_EI_EN_2 | input | TCELL1:IMUX_D0 |
| FFC_PCIE_EI_EN_3 | input | TCELL0:IMUX_D0 |
| FFC_PCIE_RX_0 | input | TCELL2:IMUX_D0 |
| FFC_PCIE_RX_1 | input | TCELL2:IMUX_D1 |
| FFC_PCIE_RX_2 | input | TCELL2:IMUX_D6 |
| FFC_PCIE_RX_3 | input | TCELL2:IMUX_D7 |
| FFC_PCIE_TX_0 | input | TCELL5:IMUX_D7 |
| FFC_PCIE_TX_1 | input | TCELL4:IMUX_D7 |
| FFC_PCIE_TX_2 | input | TCELL1:IMUX_D7 |
| FFC_PCIE_TX_3 | input | TCELL0:IMUX_D7 |
| FFC_QUAD_RST | input | TCELL2:IMUX_LSR0 |
| FFC_SB_INV_RX_0 | input | TCELL5:IMUX_D5 |
| FFC_SB_INV_RX_1 | input | TCELL4:IMUX_D5 |
| FFC_SB_INV_RX_2 | input | TCELL1:IMUX_D5 |
| FFC_SB_INV_RX_3 | input | TCELL0:IMUX_D5 |
| FFC_SD_0 | input | TCELL5:IMUX_D1 |
| FFC_SD_1 | input | TCELL4:IMUX_D1 |
| FFC_SD_2 | input | TCELL1:IMUX_D1 |
| FFC_SD_3 | input | TCELL0:IMUX_D1 |
| FFS_AB_ALIGNED | output | TCELL4:OUT_Q1 |
| FFS_AB_FAILED | output | TCELL4:OUT_Q2 |
| FFS_AB_STATUS | output | TCELL4:OUT_Q0 |
| FFS_CC_ORUN_0 | output | TCELL4:OUT_F6 |
| FFS_CC_ORUN_1 | output | TCELL3:OUT_OFX4 |
| FFS_CC_ORUN_2 | output | TCELL1:OUT_OFX0 |
| FFS_CC_ORUN_3 | output | TCELL0:OUT_OFX6 |
| FFS_CC_URUN_0 | output | TCELL4:OUT_F7 |
| FFS_CC_URUN_1 | output | TCELL3:OUT_OFX5 |
| FFS_CC_URUN_2 | output | TCELL1:OUT_OFX1 |
| FFS_CC_URUN_3 | output | TCELL0:OUT_OFX7 |
| FFS_CD_ALIGNED | output | TCELL1:OUT_OFX3 |
| FFS_CD_FAILED | output | TCELL1:OUT_OFX4 |
| FFS_CD_STATUS | output | TCELL1:OUT_OFX2 |
| FFS_LS_STATUS_0 | output | TCELL4:OUT_F4 |
| FFS_LS_STATUS_1 | output | TCELL3:OUT_OFX2 |
| FFS_LS_STATUS_2 | output | TCELL1:OUT_Q7 |
| FFS_LS_STATUS_3 | output | TCELL1:OUT_OFX7 |
| FFS_PCIE_CON_0 | output | TCELL4:OUT_F2 |
| FFS_PCIE_CON_1 | output | TCELL3:OUT_OFX0 |
| FFS_PCIE_CON_2 | output | TCELL1:OUT_Q5 |
| FFS_PCIE_CON_3 | output | TCELL1:OUT_OFX5 |
| FFS_PCIE_DONE_0 | output | TCELL4:OUT_F3 |
| FFS_PCIE_DONE_1 | output | TCELL3:OUT_OFX1 |
| FFS_PCIE_DONE_2 | output | TCELL1:OUT_Q6 |
| FFS_PCIE_DONE_3 | output | TCELL1:OUT_OFX6 |
| FFS_RLOS_LO0 | output | TCELL4:OUT_Q3 |
| FFS_RLOS_LO1 | output | TCELL4:OUT_Q4 |
| FFS_RLOS_LO2 | output | TCELL2:OUT_OFX1 |
| FFS_RLOS_LO3 | output | TCELL2:OUT_OFX2 |
| FF_RCLK0 | input | TCELL5:IMUX_CLK1 |
| FF_RCLK1 | input | TCELL4:IMUX_CLK1 |
| FF_RCLK2 | input | TCELL1:IMUX_CLK1 |
| FF_RCLK3 | input | TCELL0:IMUX_CLK1 |
| FF_RXCLK0 | output | TCELL5:OUT_F1 |
| FF_RXCLK1 | output | TCELL4:OUT_Q7 |
| FF_RXCLK2 | output | TCELL2:OUT_F1 |
| FF_RXCLK3 | output | TCELL0:OUT_F1 |
| FF_SYSCLK0 | output | TCELL5:OUT_F0 |
| FF_SYSCLK1 | output | TCELL4:OUT_Q6 |
| FF_SYSCLK2 | output | TCELL2:OUT_F0 |
| FF_SYSCLK3 | output | TCELL0:OUT_F0 |
| FF_TCLK0 | input | TCELL5:IMUX_CLK0 |
| FF_TCLK1 | input | TCELL4:IMUX_CLK0 |
| FF_TCLK2 | input | TCELL1:IMUX_CLK0 |
| FF_TCLK3 | input | TCELL0:IMUX_CLK0 |
| FF_TXD_0_0 | input | TCELL5:IMUX_C7 |
| FF_TXD_0_1 | input | TCELL5:IMUX_C6 |
| FF_TXD_0_10 | input | TCELL5:IMUX_B5 |
| FF_TXD_0_11 | input | TCELL5:IMUX_B4 |
| FF_TXD_0_12 | input | TCELL5:IMUX_B3 |
| FF_TXD_0_13 | input | TCELL5:IMUX_B2 |
| FF_TXD_0_14 | input | TCELL5:IMUX_B1 |
| FF_TXD_0_15 | input | TCELL5:IMUX_B0 |
| FF_TXD_0_16 | input | TCELL5:IMUX_A7 |
| FF_TXD_0_17 | input | TCELL5:IMUX_A6 |
| FF_TXD_0_18 | input | TCELL5:IMUX_A5 |
| FF_TXD_0_19 | input | TCELL5:IMUX_A4 |
| FF_TXD_0_2 | input | TCELL5:IMUX_C5 |
| FF_TXD_0_20 | input | TCELL5:IMUX_A3 |
| FF_TXD_0_21 | input | TCELL5:IMUX_A2 |
| FF_TXD_0_22 | input | TCELL5:IMUX_A1 |
| FF_TXD_0_23 | input | TCELL5:IMUX_A0 |
| FF_TXD_0_3 | input | TCELL5:IMUX_C4 |
| FF_TXD_0_4 | input | TCELL5:IMUX_C3 |
| FF_TXD_0_5 | input | TCELL5:IMUX_C2 |
| FF_TXD_0_6 | input | TCELL5:IMUX_C1 |
| FF_TXD_0_7 | input | TCELL5:IMUX_C0 |
| FF_TXD_0_8 | input | TCELL5:IMUX_B7 |
| FF_TXD_0_9 | input | TCELL5:IMUX_B6 |
| FF_TXD_1_0 | input | TCELL4:IMUX_C7 |
| FF_TXD_1_1 | input | TCELL4:IMUX_C6 |
| FF_TXD_1_10 | input | TCELL4:IMUX_B5 |
| FF_TXD_1_11 | input | TCELL4:IMUX_B4 |
| FF_TXD_1_12 | input | TCELL4:IMUX_B3 |
| FF_TXD_1_13 | input | TCELL4:IMUX_B2 |
| FF_TXD_1_14 | input | TCELL4:IMUX_B1 |
| FF_TXD_1_15 | input | TCELL4:IMUX_B0 |
| FF_TXD_1_16 | input | TCELL4:IMUX_A7 |
| FF_TXD_1_17 | input | TCELL4:IMUX_A6 |
| FF_TXD_1_18 | input | TCELL4:IMUX_A5 |
| FF_TXD_1_19 | input | TCELL4:IMUX_A4 |
| FF_TXD_1_2 | input | TCELL4:IMUX_C5 |
| FF_TXD_1_20 | input | TCELL4:IMUX_A3 |
| FF_TXD_1_21 | input | TCELL4:IMUX_A2 |
| FF_TXD_1_22 | input | TCELL4:IMUX_A1 |
| FF_TXD_1_23 | input | TCELL4:IMUX_A0 |
| FF_TXD_1_3 | input | TCELL4:IMUX_C4 |
| FF_TXD_1_4 | input | TCELL4:IMUX_C3 |
| FF_TXD_1_5 | input | TCELL4:IMUX_C2 |
| FF_TXD_1_6 | input | TCELL4:IMUX_C1 |
| FF_TXD_1_7 | input | TCELL4:IMUX_C0 |
| FF_TXD_1_8 | input | TCELL4:IMUX_B7 |
| FF_TXD_1_9 | input | TCELL4:IMUX_B6 |
| FF_TXD_2_0 | input | TCELL1:IMUX_C7 |
| FF_TXD_2_1 | input | TCELL1:IMUX_C6 |
| FF_TXD_2_10 | input | TCELL1:IMUX_B5 |
| FF_TXD_2_11 | input | TCELL1:IMUX_B4 |
| FF_TXD_2_12 | input | TCELL1:IMUX_B3 |
| FF_TXD_2_13 | input | TCELL1:IMUX_B2 |
| FF_TXD_2_14 | input | TCELL1:IMUX_B1 |
| FF_TXD_2_15 | input | TCELL1:IMUX_B0 |
| FF_TXD_2_16 | input | TCELL1:IMUX_A7 |
| FF_TXD_2_17 | input | TCELL1:IMUX_A6 |
| FF_TXD_2_18 | input | TCELL1:IMUX_A5 |
| FF_TXD_2_19 | input | TCELL1:IMUX_A4 |
| FF_TXD_2_2 | input | TCELL1:IMUX_C5 |
| FF_TXD_2_20 | input | TCELL1:IMUX_A3 |
| FF_TXD_2_21 | input | TCELL1:IMUX_A2 |
| FF_TXD_2_22 | input | TCELL1:IMUX_A1 |
| FF_TXD_2_23 | input | TCELL1:IMUX_A0 |
| FF_TXD_2_3 | input | TCELL1:IMUX_C4 |
| FF_TXD_2_4 | input | TCELL1:IMUX_C3 |
| FF_TXD_2_5 | input | TCELL1:IMUX_C2 |
| FF_TXD_2_6 | input | TCELL1:IMUX_C1 |
| FF_TXD_2_7 | input | TCELL1:IMUX_C0 |
| FF_TXD_2_8 | input | TCELL1:IMUX_B7 |
| FF_TXD_2_9 | input | TCELL1:IMUX_B6 |
| FF_TXD_3_0 | input | TCELL0:IMUX_C7 |
| FF_TXD_3_1 | input | TCELL0:IMUX_C6 |
| FF_TXD_3_10 | input | TCELL0:IMUX_B5 |
| FF_TXD_3_11 | input | TCELL0:IMUX_B4 |
| FF_TXD_3_12 | input | TCELL0:IMUX_B3 |
| FF_TXD_3_13 | input | TCELL0:IMUX_B2 |
| FF_TXD_3_14 | input | TCELL0:IMUX_B1 |
| FF_TXD_3_15 | input | TCELL0:IMUX_B0 |
| FF_TXD_3_16 | input | TCELL0:IMUX_A7 |
| FF_TXD_3_17 | input | TCELL0:IMUX_A6 |
| FF_TXD_3_18 | input | TCELL0:IMUX_A5 |
| FF_TXD_3_19 | input | TCELL0:IMUX_A4 |
| FF_TXD_3_2 | input | TCELL0:IMUX_C5 |
| FF_TXD_3_20 | input | TCELL0:IMUX_A3 |
| FF_TXD_3_21 | input | TCELL0:IMUX_A2 |
| FF_TXD_3_22 | input | TCELL0:IMUX_A1 |
| FF_TXD_3_23 | input | TCELL0:IMUX_A0 |
| FF_TXD_3_3 | input | TCELL0:IMUX_C4 |
| FF_TXD_3_4 | input | TCELL0:IMUX_C3 |
| FF_TXD_3_5 | input | TCELL0:IMUX_C2 |
| FF_TXD_3_6 | input | TCELL0:IMUX_C1 |
| FF_TXD_3_7 | input | TCELL0:IMUX_C0 |
| FF_TXD_3_8 | input | TCELL0:IMUX_B7 |
| FF_TXD_3_9 | input | TCELL0:IMUX_B6 |
scm SERDES_E bel wires
| Wire | Pins |
|---|
| TCELL0:IMUX_A0 | SERDES.FF_TXD_3_23 |
| TCELL0:IMUX_A1 | SERDES.FF_TXD_3_22 |
| TCELL0:IMUX_A2 | SERDES.FF_TXD_3_21 |
| TCELL0:IMUX_A3 | SERDES.FF_TXD_3_20 |
| TCELL0:IMUX_A4 | SERDES.FF_TXD_3_19 |
| TCELL0:IMUX_A5 | SERDES.FF_TXD_3_18 |
| TCELL0:IMUX_A6 | SERDES.FF_TXD_3_17 |
| TCELL0:IMUX_A7 | SERDES.FF_TXD_3_16 |
| TCELL0:IMUX_B0 | SERDES.FF_TXD_3_15 |
| TCELL0:IMUX_B1 | SERDES.FF_TXD_3_14 |
| TCELL0:IMUX_B2 | SERDES.FF_TXD_3_13 |
| TCELL0:IMUX_B3 | SERDES.FF_TXD_3_12 |
| TCELL0:IMUX_B4 | SERDES.FF_TXD_3_11 |
| TCELL0:IMUX_B5 | SERDES.FF_TXD_3_10 |
| TCELL0:IMUX_B6 | SERDES.FF_TXD_3_9 |
| TCELL0:IMUX_B7 | SERDES.FF_TXD_3_8 |
| TCELL0:IMUX_C0 | SERDES.FF_TXD_3_7 |
| TCELL0:IMUX_C1 | SERDES.FF_TXD_3_6 |
| TCELL0:IMUX_C2 | SERDES.FF_TXD_3_5 |
| TCELL0:IMUX_C3 | SERDES.FF_TXD_3_4 |
| TCELL0:IMUX_C4 | SERDES.FF_TXD_3_3 |
| TCELL0:IMUX_C5 | SERDES.FF_TXD_3_2 |
| TCELL0:IMUX_C6 | SERDES.FF_TXD_3_1 |
| TCELL0:IMUX_C7 | SERDES.FF_TXD_3_0 |
| TCELL0:IMUX_D0 | SERDES.FFC_PCIE_EI_EN_3 |
| TCELL0:IMUX_D1 | SERDES.FFC_SD_3 |
| TCELL0:IMUX_D2 | SERDES.FFC_EN_CGA_3 |
| TCELL0:IMUX_D3 | SERDES.FFC_ALIGN_EN_3 |
| TCELL0:IMUX_D4 | SERDES.FFC_FB_LB_3 |
| TCELL0:IMUX_D5 | SERDES.FFC_SB_INV_RX_3 |
| TCELL0:IMUX_D6 | SERDES.FFC_PCIE_CT_3 |
| TCELL0:IMUX_D7 | SERDES.FFC_PCIE_TX_3 |
| TCELL0:IMUX_CLK0 | SERDES.FF_TCLK3 |
| TCELL0:IMUX_CLK1 | SERDES.FF_RCLK3 |
| TCELL0:IMUX_CE1 | SERDES.FFC_LANE_TX_RST3 |
| TCELL0:IMUX_CE2 | SERDES.FFC_LANE_RX_RST3 |
| TCELL0:IMUX_CE3 | SERDES.FFC_CD_RESET |
| TCELL0:OUT_F0 | SERDES.FF_SYSCLK3 |
| TCELL0:OUT_F1 | SERDES.FF_RXCLK3 |
| TCELL0:OUT_F2 | SERDES.FB_RXD_3_19 |
| TCELL0:OUT_F3 | SERDES.FB_RXD_3_18 |
| TCELL0:OUT_F4 | SERDES.FB_RXD_3_17 |
| TCELL0:OUT_F5 | SERDES.FB_RXD_3_16 |
| TCELL0:OUT_F6 | SERDES.FB_RXD_3_15 |
| TCELL0:OUT_F7 | SERDES.FB_RXD_3_14 |
| TCELL0:OUT_Q0 | SERDES.FB_RXD_3_13 |
| TCELL0:OUT_Q1 | SERDES.FB_RXD_3_12 |
| TCELL0:OUT_Q2 | SERDES.FB_RXD_3_11 |
| TCELL0:OUT_Q3 | SERDES.FB_RXD_3_10 |
| TCELL0:OUT_Q4 | SERDES.FB_RXD_3_9 |
| TCELL0:OUT_Q5 | SERDES.FB_RXD_3_8 |
| TCELL0:OUT_Q6 | SERDES.FB_RXD_3_7 |
| TCELL0:OUT_Q7 | SERDES.FB_RXD_3_6 |
| TCELL0:OUT_OFX0 | SERDES.FB_RXD_3_5 |
| TCELL0:OUT_OFX1 | SERDES.FB_RXD_3_4 |
| TCELL0:OUT_OFX2 | SERDES.FB_RXD_3_3 |
| TCELL0:OUT_OFX3 | SERDES.FB_RXD_3_2 |
| TCELL0:OUT_OFX4 | SERDES.FB_RXD_3_1 |
| TCELL0:OUT_OFX5 | SERDES.FB_RXD_3_0 |
| TCELL0:OUT_OFX6 | SERDES.FFS_CC_ORUN_3 |
| TCELL0:OUT_OFX7 | SERDES.FFS_CC_URUN_3 |
| TCELL1:IMUX_A0 | SERDES.FF_TXD_2_23 |
| TCELL1:IMUX_A1 | SERDES.FF_TXD_2_22 |
| TCELL1:IMUX_A2 | SERDES.FF_TXD_2_21 |
| TCELL1:IMUX_A3 | SERDES.FF_TXD_2_20 |
| TCELL1:IMUX_A4 | SERDES.FF_TXD_2_19 |
| TCELL1:IMUX_A5 | SERDES.FF_TXD_2_18 |
| TCELL1:IMUX_A6 | SERDES.FF_TXD_2_17 |
| TCELL1:IMUX_A7 | SERDES.FF_TXD_2_16 |
| TCELL1:IMUX_B0 | SERDES.FF_TXD_2_15 |
| TCELL1:IMUX_B1 | SERDES.FF_TXD_2_14 |
| TCELL1:IMUX_B2 | SERDES.FF_TXD_2_13 |
| TCELL1:IMUX_B3 | SERDES.FF_TXD_2_12 |
| TCELL1:IMUX_B4 | SERDES.FF_TXD_2_11 |
| TCELL1:IMUX_B5 | SERDES.FF_TXD_2_10 |
| TCELL1:IMUX_B6 | SERDES.FF_TXD_2_9 |
| TCELL1:IMUX_B7 | SERDES.FF_TXD_2_8 |
| TCELL1:IMUX_C0 | SERDES.FF_TXD_2_7 |
| TCELL1:IMUX_C1 | SERDES.FF_TXD_2_6 |
| TCELL1:IMUX_C2 | SERDES.FF_TXD_2_5 |
| TCELL1:IMUX_C3 | SERDES.FF_TXD_2_4 |
| TCELL1:IMUX_C4 | SERDES.FF_TXD_2_3 |
| TCELL1:IMUX_C5 | SERDES.FF_TXD_2_2 |
| TCELL1:IMUX_C6 | SERDES.FF_TXD_2_1 |
| TCELL1:IMUX_C7 | SERDES.FF_TXD_2_0 |
| TCELL1:IMUX_D0 | SERDES.FFC_PCIE_EI_EN_2 |
| TCELL1:IMUX_D1 | SERDES.FFC_SD_2 |
| TCELL1:IMUX_D2 | SERDES.FFC_EN_CGA_2 |
| TCELL1:IMUX_D3 | SERDES.FFC_ALIGN_EN_2 |
| TCELL1:IMUX_D4 | SERDES.FFC_FB_LB_2 |
| TCELL1:IMUX_D5 | SERDES.FFC_SB_INV_RX_2 |
| TCELL1:IMUX_D6 | SERDES.FFC_PCIE_CT_2 |
| TCELL1:IMUX_D7 | SERDES.FFC_PCIE_TX_2 |
| TCELL1:IMUX_CLK0 | SERDES.FF_TCLK2 |
| TCELL1:IMUX_CLK1 | SERDES.FF_RCLK2 |
| TCELL1:IMUX_CE1 | SERDES.FFC_LANE_TX_RST2 |
| TCELL1:IMUX_CE2 | SERDES.FFC_LANE_RX_RST2 |
| TCELL1:OUT_F0 | SERDES.FB_RXD_2_8 |
| TCELL1:OUT_F1 | SERDES.FB_RXD_2_7 |
| TCELL1:OUT_F2 | SERDES.FB_RXD_2_6 |
| TCELL1:OUT_F3 | SERDES.FB_RXD_2_5 |
| TCELL1:OUT_F4 | SERDES.FB_RXD_2_4 |
| TCELL1:OUT_F5 | SERDES.FB_RXD_2_3 |
| TCELL1:OUT_F6 | SERDES.FB_RXD_2_2 |
| TCELL1:OUT_F7 | SERDES.FB_RXD_2_1 |
| TCELL1:OUT_Q0 | SERDES.FB_RXD_2_0 |
| TCELL1:OUT_Q1 | SERDES.FB_RXD_3_23 |
| TCELL1:OUT_Q2 | SERDES.FB_RXD_3_22 |
| TCELL1:OUT_Q3 | SERDES.FB_RXD_3_21 |
| TCELL1:OUT_Q4 | SERDES.FB_RXD_3_20 |
| TCELL1:OUT_Q5 | SERDES.FFS_PCIE_CON_2 |
| TCELL1:OUT_Q6 | SERDES.FFS_PCIE_DONE_2 |
| TCELL1:OUT_Q7 | SERDES.FFS_LS_STATUS_2 |
| TCELL1:OUT_OFX0 | SERDES.FFS_CC_ORUN_2 |
| TCELL1:OUT_OFX1 | SERDES.FFS_CC_URUN_2 |
| TCELL1:OUT_OFX2 | SERDES.FFS_CD_STATUS |
| TCELL1:OUT_OFX3 | SERDES.FFS_CD_ALIGNED |
| TCELL1:OUT_OFX4 | SERDES.FFS_CD_FAILED |
| TCELL1:OUT_OFX5 | SERDES.FFS_PCIE_CON_3 |
| TCELL1:OUT_OFX6 | SERDES.FFS_PCIE_DONE_3 |
| TCELL1:OUT_OFX7 | SERDES.FFS_LS_STATUS_3 |
| TCELL2:IMUX_D0 | SERDES.FFC_PCIE_RX_0 |
| TCELL2:IMUX_D1 | SERDES.FFC_PCIE_RX_1 |
| TCELL2:IMUX_D6 | SERDES.FFC_PCIE_RX_2 |
| TCELL2:IMUX_D7 | SERDES.FFC_PCIE_RX_3 |
| TCELL2:IMUX_CLK1 | SERDES.FFC_CK_CORE_RX |
| TCELL2:IMUX_LSR0 | SERDES.FFC_QUAD_RST |
| TCELL2:IMUX_CE3 | SERDES.FFC_MACRO_RST |
| TCELL2:OUT_F0 | SERDES.FF_SYSCLK2 |
| TCELL2:OUT_F1 | SERDES.FF_RXCLK2 |
| TCELL2:OUT_F2 | SERDES.FB_RXD_2_23 |
| TCELL2:OUT_F3 | SERDES.FB_RXD_2_22 |
| TCELL2:OUT_F4 | SERDES.FB_RXD_2_21 |
| TCELL2:OUT_F5 | SERDES.FB_RXD_2_20 |
| TCELL2:OUT_F6 | SERDES.FB_RXD_2_19 |
| TCELL2:OUT_F7 | SERDES.FB_RXD_2_18 |
| TCELL2:OUT_Q0 | SERDES.FB_RXD_2_17 |
| TCELL2:OUT_Q1 | SERDES.FB_RXD_2_16 |
| TCELL2:OUT_Q2 | SERDES.FB_RXD_2_15 |
| TCELL2:OUT_Q3 | SERDES.FB_RXD_2_14 |
| TCELL2:OUT_Q4 | SERDES.FB_RXD_2_13 |
| TCELL2:OUT_Q5 | SERDES.FB_RXD_2_12 |
| TCELL2:OUT_Q6 | SERDES.FB_RXD_2_11 |
| TCELL2:OUT_Q7 | SERDES.FB_RXD_2_10 |
| TCELL2:OUT_OFX0 | SERDES.FB_RXD_2_9 |
| TCELL2:OUT_OFX1 | SERDES.FFS_RLOS_LO2 |
| TCELL2:OUT_OFX2 | SERDES.FFS_RLOS_LO3 |
| TCELL2:OUT_OFX4 | SERDES.BS4PAD_3 |
| TCELL2:OUT_OFX5 | SERDES.BS4PAD_2 |
| TCELL2:OUT_OFX6 | SERDES.BS4PAD_1 |
| TCELL2:OUT_OFX7 | SERDES.BS4PAD_0 |
| TCELL3:OUT_F0 | SERDES.FB_RXD_1_15 |
| TCELL3:OUT_F1 | SERDES.FB_RXD_1_14 |
| TCELL3:OUT_F2 | SERDES.FB_RXD_1_13 |
| TCELL3:OUT_F3 | SERDES.FB_RXD_1_12 |
| TCELL3:OUT_F4 | SERDES.FB_RXD_1_11 |
| TCELL3:OUT_F5 | SERDES.FB_RXD_1_10 |
| TCELL3:OUT_F6 | SERDES.FB_RXD_1_9 |
| TCELL3:OUT_F7 | SERDES.FB_RXD_1_8 |
| TCELL3:OUT_Q0 | SERDES.FB_RXD_1_7 |
| TCELL3:OUT_Q1 | SERDES.FB_RXD_1_6 |
| TCELL3:OUT_Q2 | SERDES.FB_RXD_1_5 |
| TCELL3:OUT_Q3 | SERDES.FB_RXD_1_4 |
| TCELL3:OUT_Q4 | SERDES.FB_RXD_1_3 |
| TCELL3:OUT_Q5 | SERDES.FB_RXD_1_2 |
| TCELL3:OUT_Q6 | SERDES.FB_RXD_1_1 |
| TCELL3:OUT_Q7 | SERDES.FB_RXD_1_0 |
| TCELL3:OUT_OFX0 | SERDES.FFS_PCIE_CON_1 |
| TCELL3:OUT_OFX1 | SERDES.FFS_PCIE_DONE_1 |
| TCELL3:OUT_OFX2 | SERDES.FFS_LS_STATUS_1 |
| TCELL3:OUT_OFX4 | SERDES.FFS_CC_ORUN_1 |
| TCELL3:OUT_OFX5 | SERDES.FFS_CC_URUN_1 |
| TCELL4:IMUX_A0 | SERDES.FF_TXD_1_23 |
| TCELL4:IMUX_A1 | SERDES.FF_TXD_1_22 |
| TCELL4:IMUX_A2 | SERDES.FF_TXD_1_21 |
| TCELL4:IMUX_A3 | SERDES.FF_TXD_1_20 |
| TCELL4:IMUX_A4 | SERDES.FF_TXD_1_19 |
| TCELL4:IMUX_A5 | SERDES.FF_TXD_1_18 |
| TCELL4:IMUX_A6 | SERDES.FF_TXD_1_17 |
| TCELL4:IMUX_A7 | SERDES.FF_TXD_1_16 |
| TCELL4:IMUX_B0 | SERDES.FF_TXD_1_15 |
| TCELL4:IMUX_B1 | SERDES.FF_TXD_1_14 |
| TCELL4:IMUX_B2 | SERDES.FF_TXD_1_13 |
| TCELL4:IMUX_B3 | SERDES.FF_TXD_1_12 |
| TCELL4:IMUX_B4 | SERDES.FF_TXD_1_11 |
| TCELL4:IMUX_B5 | SERDES.FF_TXD_1_10 |
| TCELL4:IMUX_B6 | SERDES.FF_TXD_1_9 |
| TCELL4:IMUX_B7 | SERDES.FF_TXD_1_8 |
| TCELL4:IMUX_C0 | SERDES.FF_TXD_1_7 |
| TCELL4:IMUX_C1 | SERDES.FF_TXD_1_6 |
| TCELL4:IMUX_C2 | SERDES.FF_TXD_1_5 |
| TCELL4:IMUX_C3 | SERDES.FF_TXD_1_4 |
| TCELL4:IMUX_C4 | SERDES.FF_TXD_1_3 |
| TCELL4:IMUX_C5 | SERDES.FF_TXD_1_2 |
| TCELL4:IMUX_C6 | SERDES.FF_TXD_1_1 |
| TCELL4:IMUX_C7 | SERDES.FF_TXD_1_0 |
| TCELL4:IMUX_D0 | SERDES.FFC_PCIE_EI_EN_1 |
| TCELL4:IMUX_D1 | SERDES.FFC_SD_1 |
| TCELL4:IMUX_D2 | SERDES.FFC_EN_CGA_1 |
| TCELL4:IMUX_D3 | SERDES.FFC_ALIGN_EN_1 |
| TCELL4:IMUX_D4 | SERDES.FFC_FB_LB_1 |
| TCELL4:IMUX_D5 | SERDES.FFC_SB_INV_RX_1 |
| TCELL4:IMUX_D6 | SERDES.FFC_PCIE_CT_1 |
| TCELL4:IMUX_D7 | SERDES.FFC_PCIE_TX_1 |
| TCELL4:IMUX_CLK0 | SERDES.FF_TCLK1 |
| TCELL4:IMUX_CLK1 | SERDES.FF_RCLK1 |
| TCELL4:IMUX_CE1 | SERDES.FFC_LANE_TX_RST1 |
| TCELL4:IMUX_CE2 | SERDES.FFC_LANE_RX_RST1 |
| TCELL4:OUT_F0 | SERDES.FB_RXD_0_1 |
| TCELL4:OUT_F1 | SERDES.FB_RXD_0_0 |
| TCELL4:OUT_F2 | SERDES.FFS_PCIE_CON_0 |
| TCELL4:OUT_F3 | SERDES.FFS_PCIE_DONE_0 |
| TCELL4:OUT_F4 | SERDES.FFS_LS_STATUS_0 |
| TCELL4:OUT_F6 | SERDES.FFS_CC_ORUN_0 |
| TCELL4:OUT_F7 | SERDES.FFS_CC_URUN_0 |
| TCELL4:OUT_Q0 | SERDES.FFS_AB_STATUS |
| TCELL4:OUT_Q1 | SERDES.FFS_AB_ALIGNED |
| TCELL4:OUT_Q2 | SERDES.FFS_AB_FAILED |
| TCELL4:OUT_Q3 | SERDES.FFS_RLOS_LO0 |
| TCELL4:OUT_Q4 | SERDES.FFS_RLOS_LO1 |
| TCELL4:OUT_Q6 | SERDES.FF_SYSCLK1 |
| TCELL4:OUT_Q7 | SERDES.FF_RXCLK1 |
| TCELL4:OUT_OFX0 | SERDES.FB_RXD_1_23 |
| TCELL4:OUT_OFX1 | SERDES.FB_RXD_1_22 |
| TCELL4:OUT_OFX2 | SERDES.FB_RXD_1_21 |
| TCELL4:OUT_OFX3 | SERDES.FB_RXD_1_20 |
| TCELL4:OUT_OFX4 | SERDES.FB_RXD_1_19 |
| TCELL4:OUT_OFX5 | SERDES.FB_RXD_1_18 |
| TCELL4:OUT_OFX6 | SERDES.FB_RXD_1_17 |
| TCELL4:OUT_OFX7 | SERDES.FB_RXD_1_16 |
| TCELL5:IMUX_A0 | SERDES.FF_TXD_0_23 |
| TCELL5:IMUX_A1 | SERDES.FF_TXD_0_22 |
| TCELL5:IMUX_A2 | SERDES.FF_TXD_0_21 |
| TCELL5:IMUX_A3 | SERDES.FF_TXD_0_20 |
| TCELL5:IMUX_A4 | SERDES.FF_TXD_0_19 |
| TCELL5:IMUX_A5 | SERDES.FF_TXD_0_18 |
| TCELL5:IMUX_A6 | SERDES.FF_TXD_0_17 |
| TCELL5:IMUX_A7 | SERDES.FF_TXD_0_16 |
| TCELL5:IMUX_B0 | SERDES.FF_TXD_0_15 |
| TCELL5:IMUX_B1 | SERDES.FF_TXD_0_14 |
| TCELL5:IMUX_B2 | SERDES.FF_TXD_0_13 |
| TCELL5:IMUX_B3 | SERDES.FF_TXD_0_12 |
| TCELL5:IMUX_B4 | SERDES.FF_TXD_0_11 |
| TCELL5:IMUX_B5 | SERDES.FF_TXD_0_10 |
| TCELL5:IMUX_B6 | SERDES.FF_TXD_0_9 |
| TCELL5:IMUX_B7 | SERDES.FF_TXD_0_8 |
| TCELL5:IMUX_C0 | SERDES.FF_TXD_0_7 |
| TCELL5:IMUX_C1 | SERDES.FF_TXD_0_6 |
| TCELL5:IMUX_C2 | SERDES.FF_TXD_0_5 |
| TCELL5:IMUX_C3 | SERDES.FF_TXD_0_4 |
| TCELL5:IMUX_C4 | SERDES.FF_TXD_0_3 |
| TCELL5:IMUX_C5 | SERDES.FF_TXD_0_2 |
| TCELL5:IMUX_C6 | SERDES.FF_TXD_0_1 |
| TCELL5:IMUX_C7 | SERDES.FF_TXD_0_0 |
| TCELL5:IMUX_D0 | SERDES.FFC_PCIE_EI_EN_0 |
| TCELL5:IMUX_D1 | SERDES.FFC_SD_0 |
| TCELL5:IMUX_D2 | SERDES.FFC_EN_CGA_0 |
| TCELL5:IMUX_D3 | SERDES.FFC_ALIGN_EN_0 |
| TCELL5:IMUX_D4 | SERDES.FFC_FB_LB_0 |
| TCELL5:IMUX_D5 | SERDES.FFC_SB_INV_RX_0 |
| TCELL5:IMUX_D6 | SERDES.FFC_PCIE_CT_0 |
| TCELL5:IMUX_D7 | SERDES.FFC_PCIE_TX_0 |
| TCELL5:IMUX_CLK0 | SERDES.FF_TCLK0 |
| TCELL5:IMUX_CLK1 | SERDES.FF_RCLK0 |
| TCELL5:IMUX_CE1 | SERDES.FFC_LANE_TX_RST0 |
| TCELL5:IMUX_CE2 | SERDES.FFC_LANE_RX_RST0 |
| TCELL5:IMUX_CE3 | SERDES.FFC_AB_RESET |
| TCELL5:OUT_F0 | SERDES.FF_SYSCLK0 |
| TCELL5:OUT_F1 | SERDES.FF_RXCLK0 |
| TCELL5:OUT_F2 | SERDES.FB_RXD_0_23 |
| TCELL5:OUT_F3 | SERDES.FB_RXD_0_22 |
| TCELL5:OUT_F4 | SERDES.FB_RXD_0_21 |
| TCELL5:OUT_F5 | SERDES.FB_RXD_0_20 |
| TCELL5:OUT_F6 | SERDES.FB_RXD_0_19 |
| TCELL5:OUT_F7 | SERDES.FB_RXD_0_18 |
| TCELL5:OUT_Q0 | SERDES.FB_RXD_0_17 |
| TCELL5:OUT_Q1 | SERDES.FB_RXD_0_16 |
| TCELL5:OUT_Q2 | SERDES.FB_RXD_0_15 |
| TCELL5:OUT_Q3 | SERDES.FB_RXD_0_14 |
| TCELL5:OUT_Q4 | SERDES.FB_RXD_0_13 |
| TCELL5:OUT_Q5 | SERDES.FB_RXD_0_12 |
| TCELL5:OUT_Q6 | SERDES.FB_RXD_0_11 |
| TCELL5:OUT_Q7 | SERDES.FB_RXD_0_10 |
| TCELL5:OUT_OFX0 | SERDES.FB_RXD_0_9 |
| TCELL5:OUT_OFX1 | SERDES.FB_RXD_0_8 |
| TCELL5:OUT_OFX2 | SERDES.FB_RXD_0_7 |
| TCELL5:OUT_OFX3 | SERDES.FB_RXD_0_6 |
| TCELL5:OUT_OFX4 | SERDES.FB_RXD_0_5 |
| TCELL5:OUT_OFX5 | SERDES.FB_RXD_0_4 |
| TCELL5:OUT_OFX6 | SERDES.FB_RXD_0_3 |
| TCELL5:OUT_OFX7 | SERDES.FB_RXD_0_2 |