DSP

Tile MAC16

Cells: 5 IRIs: 0

Bel MAC16

siliconblue MAC16 bel MAC16
Pin	Direction	Wires
ADDSUBBOT	input	TCELL0:IMUX.LC3.I0
ADDSUBTOP	input	TCELL3:IMUX.LC3.I0
AHOLD	input	TCELL2:IMUX.LC0.I0
A_0	input	TCELL2:IMUX.LC0.I3
A_1	input	TCELL2:IMUX.LC1.I3
A_10	input	TCELL2:IMUX.LC2.I1
A_11	input	TCELL2:IMUX.LC3.I1
A_12	input	TCELL2:IMUX.LC4.I1
A_13	input	TCELL2:IMUX.LC5.I1
A_14	input	TCELL2:IMUX.LC6.I1
A_15	input	TCELL2:IMUX.LC7.I1
A_2	input	TCELL2:IMUX.LC2.I3
A_3	input	TCELL2:IMUX.LC3.I3
A_4	input	TCELL2:IMUX.LC4.I3
A_5	input	TCELL2:IMUX.LC5.I3
A_6	input	TCELL2:IMUX.LC6.I3
A_7	input	TCELL2:IMUX.LC7.I3
A_8	input	TCELL2:IMUX.LC0.I1
A_9	input	TCELL2:IMUX.LC1.I1
BHOLD	input	TCELL1:IMUX.LC0.I0
B_0	input	TCELL1:IMUX.LC0.I3
B_1	input	TCELL1:IMUX.LC1.I3
B_10	input	TCELL1:IMUX.LC2.I1
B_11	input	TCELL1:IMUX.LC3.I1
B_12	input	TCELL1:IMUX.LC4.I1
B_13	input	TCELL1:IMUX.LC5.I1
B_14	input	TCELL1:IMUX.LC6.I1
B_15	input	TCELL1:IMUX.LC7.I1
B_2	input	TCELL1:IMUX.LC2.I3
B_3	input	TCELL1:IMUX.LC3.I3
B_4	input	TCELL1:IMUX.LC4.I3
B_5	input	TCELL1:IMUX.LC5.I3
B_6	input	TCELL1:IMUX.LC6.I3
B_7	input	TCELL1:IMUX.LC7.I3
B_8	input	TCELL1:IMUX.LC0.I1
B_9	input	TCELL1:IMUX.LC1.I1
CE	input	TCELL2:IMUX.CE
CHOLD	input	TCELL3:IMUX.LC0.I0
CI	input	TCELL0:IMUX.LC4.I0
CLK	input	TCELL2:IMUX.CLK
CO	output	TCELL4:OUT.LC0
C_0	input	TCELL3:IMUX.LC0.I3
C_1	input	TCELL3:IMUX.LC1.I3
C_10	input	TCELL3:IMUX.LC2.I1
C_11	input	TCELL3:IMUX.LC3.I1
C_12	input	TCELL3:IMUX.LC4.I1
C_13	input	TCELL3:IMUX.LC5.I1
C_14	input	TCELL3:IMUX.LC6.I1
C_15	input	TCELL3:IMUX.LC7.I1
C_2	input	TCELL3:IMUX.LC2.I3
C_3	input	TCELL3:IMUX.LC3.I3
C_4	input	TCELL3:IMUX.LC4.I3
C_5	input	TCELL3:IMUX.LC5.I3
C_6	input	TCELL3:IMUX.LC6.I3
C_7	input	TCELL3:IMUX.LC7.I3
C_8	input	TCELL3:IMUX.LC0.I1
C_9	input	TCELL3:IMUX.LC1.I1
DHOLD	input	TCELL0:IMUX.LC0.I0
D_0	input	TCELL0:IMUX.LC0.I3
D_1	input	TCELL0:IMUX.LC1.I3
D_10	input	TCELL0:IMUX.LC2.I1
D_11	input	TCELL0:IMUX.LC3.I1
D_12	input	TCELL0:IMUX.LC4.I1
D_13	input	TCELL0:IMUX.LC5.I1
D_14	input	TCELL0:IMUX.LC6.I1
D_15	input	TCELL0:IMUX.LC7.I1
D_2	input	TCELL0:IMUX.LC2.I3
D_3	input	TCELL0:IMUX.LC3.I3
D_4	input	TCELL0:IMUX.LC4.I3
D_5	input	TCELL0:IMUX.LC5.I3
D_6	input	TCELL0:IMUX.LC6.I3
D_7	input	TCELL0:IMUX.LC7.I3
D_8	input	TCELL0:IMUX.LC0.I1
D_9	input	TCELL0:IMUX.LC1.I1
IRSTBOT	input	TCELL0:IMUX.RST
IRSTTOP	input	TCELL1:IMUX.RST
OHOLDBOT	input	TCELL0:IMUX.LC1.I0
OHOLDTOP	input	TCELL3:IMUX.LC1.I0
OLOADBOT	input	TCELL0:IMUX.LC2.I0
OLOADTOP	input	TCELL3:IMUX.LC2.I0
ORSTBOT	input	TCELL2:IMUX.RST
ORSTTOP	input	TCELL3:IMUX.RST
O_0	output	TCELL0:OUT.LC0
O_1	output	TCELL0:OUT.LC1
O_10	output	TCELL1:OUT.LC2
O_11	output	TCELL1:OUT.LC3
O_12	output	TCELL1:OUT.LC4
O_13	output	TCELL1:OUT.LC5
O_14	output	TCELL1:OUT.LC6
O_15	output	TCELL1:OUT.LC7
O_16	output	TCELL2:OUT.LC0
O_17	output	TCELL2:OUT.LC1
O_18	output	TCELL2:OUT.LC2
O_19	output	TCELL2:OUT.LC3
O_2	output	TCELL0:OUT.LC2
O_20	output	TCELL2:OUT.LC4
O_21	output	TCELL2:OUT.LC5
O_22	output	TCELL2:OUT.LC6
O_23	output	TCELL2:OUT.LC7
O_24	output	TCELL3:OUT.LC0
O_25	output	TCELL3:OUT.LC1
O_26	output	TCELL3:OUT.LC2
O_27	output	TCELL3:OUT.LC3
O_28	output	TCELL3:OUT.LC4
O_29	output	TCELL3:OUT.LC5
O_3	output	TCELL0:OUT.LC3
O_30	output	TCELL3:OUT.LC6
O_31	output	TCELL3:OUT.LC7
O_4	output	TCELL0:OUT.LC4
O_5	output	TCELL0:OUT.LC5
O_6	output	TCELL0:OUT.LC6
O_7	output	TCELL0:OUT.LC7
O_8	output	TCELL1:OUT.LC0
O_9	output	TCELL1:OUT.LC1

Bel wires

siliconblue MAC16 bel wires
Wire	Pins
TCELL0:IMUX.LC0.I0	MAC16.DHOLD
TCELL0:IMUX.LC0.I1	MAC16.D_8
TCELL0:IMUX.LC0.I3	MAC16.D_0
TCELL0:IMUX.LC1.I0	MAC16.OHOLDBOT
TCELL0:IMUX.LC1.I1	MAC16.D_9
TCELL0:IMUX.LC1.I3	MAC16.D_1
TCELL0:IMUX.LC2.I0	MAC16.OLOADBOT
TCELL0:IMUX.LC2.I1	MAC16.D_10
TCELL0:IMUX.LC2.I3	MAC16.D_2
TCELL0:IMUX.LC3.I0	MAC16.ADDSUBBOT
TCELL0:IMUX.LC3.I1	MAC16.D_11
TCELL0:IMUX.LC3.I3	MAC16.D_3
TCELL0:IMUX.LC4.I0	MAC16.CI
TCELL0:IMUX.LC4.I1	MAC16.D_12
TCELL0:IMUX.LC4.I3	MAC16.D_4
TCELL0:IMUX.LC5.I1	MAC16.D_13
TCELL0:IMUX.LC5.I3	MAC16.D_5
TCELL0:IMUX.LC6.I1	MAC16.D_14
TCELL0:IMUX.LC6.I3	MAC16.D_6
TCELL0:IMUX.LC7.I1	MAC16.D_15
TCELL0:IMUX.LC7.I3	MAC16.D_7
TCELL0:IMUX.RST	MAC16.IRSTBOT
TCELL0:OUT.LC0	MAC16.O_0
TCELL0:OUT.LC1	MAC16.O_1
TCELL0:OUT.LC2	MAC16.O_2
TCELL0:OUT.LC3	MAC16.O_3
TCELL0:OUT.LC4	MAC16.O_4
TCELL0:OUT.LC5	MAC16.O_5
TCELL0:OUT.LC6	MAC16.O_6
TCELL0:OUT.LC7	MAC16.O_7
TCELL1:IMUX.LC0.I0	MAC16.BHOLD
TCELL1:IMUX.LC0.I1	MAC16.B_8
TCELL1:IMUX.LC0.I3	MAC16.B_0
TCELL1:IMUX.LC1.I1	MAC16.B_9
TCELL1:IMUX.LC1.I3	MAC16.B_1
TCELL1:IMUX.LC2.I1	MAC16.B_10
TCELL1:IMUX.LC2.I3	MAC16.B_2
TCELL1:IMUX.LC3.I1	MAC16.B_11
TCELL1:IMUX.LC3.I3	MAC16.B_3
TCELL1:IMUX.LC4.I1	MAC16.B_12
TCELL1:IMUX.LC4.I3	MAC16.B_4
TCELL1:IMUX.LC5.I1	MAC16.B_13
TCELL1:IMUX.LC5.I3	MAC16.B_5
TCELL1:IMUX.LC6.I1	MAC16.B_14
TCELL1:IMUX.LC6.I3	MAC16.B_6
TCELL1:IMUX.LC7.I1	MAC16.B_15
TCELL1:IMUX.LC7.I3	MAC16.B_7
TCELL1:IMUX.RST	MAC16.IRSTTOP
TCELL1:OUT.LC0	MAC16.O_8
TCELL1:OUT.LC1	MAC16.O_9
TCELL1:OUT.LC2	MAC16.O_10
TCELL1:OUT.LC3	MAC16.O_11
TCELL1:OUT.LC4	MAC16.O_12
TCELL1:OUT.LC5	MAC16.O_13
TCELL1:OUT.LC6	MAC16.O_14
TCELL1:OUT.LC7	MAC16.O_15
TCELL2:IMUX.LC0.I0	MAC16.AHOLD
TCELL2:IMUX.LC0.I1	MAC16.A_8
TCELL2:IMUX.LC0.I3	MAC16.A_0
TCELL2:IMUX.LC1.I1	MAC16.A_9
TCELL2:IMUX.LC1.I3	MAC16.A_1
TCELL2:IMUX.LC2.I1	MAC16.A_10
TCELL2:IMUX.LC2.I3	MAC16.A_2
TCELL2:IMUX.LC3.I1	MAC16.A_11
TCELL2:IMUX.LC3.I3	MAC16.A_3
TCELL2:IMUX.LC4.I1	MAC16.A_12
TCELL2:IMUX.LC4.I3	MAC16.A_4
TCELL2:IMUX.LC5.I1	MAC16.A_13
TCELL2:IMUX.LC5.I3	MAC16.A_5
TCELL2:IMUX.LC6.I1	MAC16.A_14
TCELL2:IMUX.LC6.I3	MAC16.A_6
TCELL2:IMUX.LC7.I1	MAC16.A_15
TCELL2:IMUX.LC7.I3	MAC16.A_7
TCELL2:IMUX.CLK	MAC16.CLK
TCELL2:IMUX.RST	MAC16.ORSTBOT
TCELL2:IMUX.CE	MAC16.CE
TCELL2:OUT.LC0	MAC16.O_16
TCELL2:OUT.LC1	MAC16.O_17
TCELL2:OUT.LC2	MAC16.O_18
TCELL2:OUT.LC3	MAC16.O_19
TCELL2:OUT.LC4	MAC16.O_20
TCELL2:OUT.LC5	MAC16.O_21
TCELL2:OUT.LC6	MAC16.O_22
TCELL2:OUT.LC7	MAC16.O_23
TCELL3:IMUX.LC0.I0	MAC16.CHOLD
TCELL3:IMUX.LC0.I1	MAC16.C_8
TCELL3:IMUX.LC0.I3	MAC16.C_0
TCELL3:IMUX.LC1.I0	MAC16.OHOLDTOP
TCELL3:IMUX.LC1.I1	MAC16.C_9
TCELL3:IMUX.LC1.I3	MAC16.C_1
TCELL3:IMUX.LC2.I0	MAC16.OLOADTOP
TCELL3:IMUX.LC2.I1	MAC16.C_10
TCELL3:IMUX.LC2.I3	MAC16.C_2
TCELL3:IMUX.LC3.I0	MAC16.ADDSUBTOP
TCELL3:IMUX.LC3.I1	MAC16.C_11
TCELL3:IMUX.LC3.I3	MAC16.C_3
TCELL3:IMUX.LC4.I1	MAC16.C_12
TCELL3:IMUX.LC4.I3	MAC16.C_4
TCELL3:IMUX.LC5.I1	MAC16.C_13
TCELL3:IMUX.LC5.I3	MAC16.C_5
TCELL3:IMUX.LC6.I1	MAC16.C_14
TCELL3:IMUX.LC6.I3	MAC16.C_6
TCELL3:IMUX.LC7.I1	MAC16.C_15
TCELL3:IMUX.LC7.I3	MAC16.C_7
TCELL3:IMUX.RST	MAC16.ORSTTOP
TCELL3:OUT.LC0	MAC16.O_24
TCELL3:OUT.LC1	MAC16.O_25
TCELL3:OUT.LC2	MAC16.O_26
TCELL3:OUT.LC3	MAC16.O_27
TCELL3:OUT.LC4	MAC16.O_28
TCELL3:OUT.LC5	MAC16.O_29
TCELL3:OUT.LC6	MAC16.O_30
TCELL3:OUT.LC7	MAC16.O_31
TCELL4:OUT.LC0	MAC16.CO

Bitstream

siliconblue MAC16 bittile 0
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	MAC16:A_REG
1	-	-	-	-	-	-	-	MAC16:C_REG
2	-	-	-	-	-	-	-	MAC16:D_REG
3	-	-	-	-	-	-	-	MAC16:B_REG
4	-	-	-	-	-	-	-	MAC16:BOT_8x8_MULT_REG
5	-	-	-	-	-	-	-	MAC16:TOP_8x8_MULT_REG
6	-	-	-	-	-	-	-	MAC16:PIPELINE_16x16_MULT_REG2
7	-	-	-	-	-	-	-	MAC16:PIPELINE_16x16_MULT_REG1

siliconblue MAC16 bittile 1
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	MAC16:TOPOUTPUT_SELECT[1]
1	-	-	-	-	-	-	-	MAC16:TOPOUTPUT_SELECT[0]
2	-	-	-	-	-	-	-	MAC16:TOPADDSUB_LOWERINPUT[1]
3	-	-	-	-	-	-	-	MAC16:TOPADDSUB_LOWERINPUT[0]
4	-	-	-	-	-	-	-	MAC16:TOPADDSUB_CARRYSELECT[0]
5	-	-	-	-	-	-	-	MAC16:TOPADDSUB_UPPERINPUT
6	-	-	-	-	-	-	-	MAC16:BOTOUTPUT_SELECT[0]
7	-	-	-	-	-	-	-	MAC16:TOPADDSUB_CARRYSELECT[1]

siliconblue MAC16 bittile 2
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	MAC16:BOTADDSUB_LOWERINPUT[0]
1	-	-	-	-	-	-	-	MAC16:BOTOUTPUT_SELECT[1]
2	-	-	-	-	-	-	-	MAC16:BOTADDSUB_UPPERINPUT
3	-	-	-	-	-	-	-	MAC16:BOTADDSUB_LOWERINPUT[1]
4	-	-	-	-	-	-	-	MAC16:BOTADDSUB_CARRYSELECT[1]
5	-	-	-	-	-	-	-	MAC16:BOTADDSUB_CARRYSELECT[0]
6	-	-	-	-	-	-	-	MAC16:A_SIGNED
7	-	-	-	-	-	-	-	MAC16:MODE_8x8

siliconblue MAC16 bittile 3
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	MAC16:B_SIGNED

MAC16:A_REG	0.0.7
MAC16:A_SIGNED	2.6.7
MAC16:BOTADDSUB_UPPERINPUT	2.2.7
MAC16:BOT_8x8_MULT_REG	0.4.7
MAC16:B_REG	0.3.7
MAC16:B_SIGNED	3.1.7
MAC16:C_REG	0.1.7
MAC16:D_REG	0.2.7
MAC16:MODE_8x8	2.7.7
MAC16:PIPELINE_16x16_MULT_REG1	0.7.7
MAC16:PIPELINE_16x16_MULT_REG2	0.6.7
MAC16:TOPADDSUB_UPPERINPUT	1.5.7
MAC16:TOP_8x8_MULT_REG	0.5.7
non-inverted	[0]

MAC16:BOTADDSUB_CARRYSELECT	2.4.7	2.5.7
MAC16:BOTADDSUB_LOWERINPUT	2.3.7	2.0.7
MAC16:BOTOUTPUT_SELECT	2.1.7	1.6.7
MAC16:TOPADDSUB_CARRYSELECT	1.7.7	1.4.7
MAC16:TOPADDSUB_LOWERINPUT	1.2.7	1.3.7
MAC16:TOPOUTPUT_SELECT	1.0.7	1.1.7
non-inverted	[1]	[0]

Tile MAC16_TRIM

Cells: 5 IRIs: 0

Bel MAC16

siliconblue MAC16_TRIM bel MAC16
Pin	Direction	Wires
ADDSUBBOT	input	TCELL0:IMUX.LC3.I0
ADDSUBTOP	input	TCELL3:IMUX.LC3.I0
AHOLD	input	TCELL2:IMUX.LC0.I0
A_0	input	TCELL2:IMUX.LC0.I3
A_1	input	TCELL2:IMUX.LC1.I3
A_10	input	TCELL2:IMUX.LC2.I1
A_11	input	TCELL2:IMUX.LC3.I1
A_12	input	TCELL2:IMUX.LC4.I1
A_13	input	TCELL2:IMUX.LC5.I1
A_14	input	TCELL2:IMUX.LC6.I1
A_15	input	TCELL2:IMUX.LC7.I1
A_2	input	TCELL2:IMUX.LC2.I3
A_3	input	TCELL2:IMUX.LC3.I3
A_4	input	TCELL2:IMUX.LC4.I3
A_5	input	TCELL2:IMUX.LC5.I3
A_6	input	TCELL2:IMUX.LC6.I3
A_7	input	TCELL2:IMUX.LC7.I3
A_8	input	TCELL2:IMUX.LC0.I1
A_9	input	TCELL2:IMUX.LC1.I1
BHOLD	input	TCELL1:IMUX.LC0.I0
B_0	input	TCELL1:IMUX.LC0.I3
B_1	input	TCELL1:IMUX.LC1.I3
B_10	input	TCELL1:IMUX.LC2.I1
B_11	input	TCELL1:IMUX.LC3.I1
B_12	input	TCELL1:IMUX.LC4.I1
B_13	input	TCELL1:IMUX.LC5.I1
B_14	input	TCELL1:IMUX.LC6.I1
B_15	input	TCELL1:IMUX.LC7.I1
B_2	input	TCELL1:IMUX.LC2.I3
B_3	input	TCELL1:IMUX.LC3.I3
B_4	input	TCELL1:IMUX.LC4.I3
B_5	input	TCELL1:IMUX.LC5.I3
B_6	input	TCELL1:IMUX.LC6.I3
B_7	input	TCELL1:IMUX.LC7.I3
B_8	input	TCELL1:IMUX.LC0.I1
B_9	input	TCELL1:IMUX.LC1.I1
CE	input	TCELL2:IMUX.CE
CHOLD	input	TCELL3:IMUX.LC0.I0
CI	input	TCELL0:IMUX.LC4.I0
CLK	input	TCELL2:IMUX.CLK
CO	output	TCELL4:OUT.LC0
C_0	input	TCELL3:IMUX.LC0.I3
C_1	input	TCELL3:IMUX.LC1.I3
C_10	input	TCELL3:IMUX.LC2.I1
C_11	input	TCELL3:IMUX.LC3.I1
C_12	input	TCELL3:IMUX.LC4.I1
C_13	input	TCELL3:IMUX.LC5.I1
C_14	input	TCELL3:IMUX.LC6.I1
C_15	input	TCELL3:IMUX.LC7.I1
C_2	input	TCELL3:IMUX.LC2.I3
C_3	input	TCELL3:IMUX.LC3.I3
C_4	input	TCELL3:IMUX.LC4.I3
C_5	input	TCELL3:IMUX.LC5.I3
C_6	input	TCELL3:IMUX.LC6.I3
C_7	input	TCELL3:IMUX.LC7.I3
C_8	input	TCELL3:IMUX.LC0.I1
C_9	input	TCELL3:IMUX.LC1.I1
DHOLD	input	TCELL0:IMUX.LC0.I0
D_0	input	TCELL0:IMUX.LC0.I3
D_1	input	TCELL0:IMUX.LC1.I3
D_10	input	TCELL0:IMUX.LC2.I1
D_11	input	TCELL0:IMUX.LC3.I1
D_12	input	TCELL0:IMUX.LC4.I1
D_13	input	TCELL0:IMUX.LC5.I1
D_14	input	TCELL0:IMUX.LC6.I1
D_15	input	TCELL0:IMUX.LC7.I1
D_2	input	TCELL0:IMUX.LC2.I3
D_3	input	TCELL0:IMUX.LC3.I3
D_4	input	TCELL0:IMUX.LC4.I3
D_5	input	TCELL0:IMUX.LC5.I3
D_6	input	TCELL0:IMUX.LC6.I3
D_7	input	TCELL0:IMUX.LC7.I3
D_8	input	TCELL0:IMUX.LC0.I1
D_9	input	TCELL0:IMUX.LC1.I1
IRSTBOT	input	TCELL0:IMUX.RST
IRSTTOP	input	TCELL1:IMUX.RST
OHOLDBOT	input	TCELL0:IMUX.LC1.I0
OHOLDTOP	input	TCELL3:IMUX.LC1.I0
OLOADBOT	input	TCELL0:IMUX.LC2.I0
OLOADTOP	input	TCELL3:IMUX.LC2.I0
ORSTBOT	input	TCELL2:IMUX.RST
ORSTTOP	input	TCELL3:IMUX.RST
O_0	output	TCELL0:OUT.LC0
O_1	output	TCELL0:OUT.LC1
O_10	output	TCELL1:OUT.LC2
O_11	output	TCELL1:OUT.LC3
O_12	output	TCELL1:OUT.LC4
O_13	output	TCELL1:OUT.LC5
O_14	output	TCELL1:OUT.LC6
O_15	output	TCELL1:OUT.LC7
O_16	output	TCELL2:OUT.LC0
O_17	output	TCELL2:OUT.LC1
O_18	output	TCELL2:OUT.LC2
O_19	output	TCELL2:OUT.LC3
O_2	output	TCELL0:OUT.LC2
O_20	output	TCELL2:OUT.LC4
O_21	output	TCELL2:OUT.LC5
O_22	output	TCELL2:OUT.LC6
O_23	output	TCELL2:OUT.LC7
O_24	output	TCELL3:OUT.LC0
O_25	output	TCELL3:OUT.LC1
O_26	output	TCELL3:OUT.LC2
O_27	output	TCELL3:OUT.LC3
O_28	output	TCELL3:OUT.LC4
O_29	output	TCELL3:OUT.LC5
O_3	output	TCELL0:OUT.LC3
O_30	output	TCELL3:OUT.LC6
O_31	output	TCELL3:OUT.LC7
O_4	output	TCELL0:OUT.LC4
O_5	output	TCELL0:OUT.LC5
O_6	output	TCELL0:OUT.LC6
O_7	output	TCELL0:OUT.LC7
O_8	output	TCELL1:OUT.LC0
O_9	output	TCELL1:OUT.LC1

Bel wires

siliconblue MAC16_TRIM bel wires
Wire	Pins
TCELL0:IMUX.LC0.I0	MAC16.DHOLD
TCELL0:IMUX.LC0.I1	MAC16.D_8
TCELL0:IMUX.LC0.I3	MAC16.D_0
TCELL0:IMUX.LC1.I0	MAC16.OHOLDBOT
TCELL0:IMUX.LC1.I1	MAC16.D_9
TCELL0:IMUX.LC1.I3	MAC16.D_1
TCELL0:IMUX.LC2.I0	MAC16.OLOADBOT
TCELL0:IMUX.LC2.I1	MAC16.D_10
TCELL0:IMUX.LC2.I3	MAC16.D_2
TCELL0:IMUX.LC3.I0	MAC16.ADDSUBBOT
TCELL0:IMUX.LC3.I1	MAC16.D_11
TCELL0:IMUX.LC3.I3	MAC16.D_3
TCELL0:IMUX.LC4.I0	MAC16.CI
TCELL0:IMUX.LC4.I1	MAC16.D_12
TCELL0:IMUX.LC4.I3	MAC16.D_4
TCELL0:IMUX.LC5.I1	MAC16.D_13
TCELL0:IMUX.LC5.I3	MAC16.D_5
TCELL0:IMUX.LC6.I1	MAC16.D_14
TCELL0:IMUX.LC6.I3	MAC16.D_6
TCELL0:IMUX.LC7.I1	MAC16.D_15
TCELL0:IMUX.LC7.I3	MAC16.D_7
TCELL0:IMUX.RST	MAC16.IRSTBOT
TCELL0:OUT.LC0	MAC16.O_0
TCELL0:OUT.LC1	MAC16.O_1
TCELL0:OUT.LC2	MAC16.O_2
TCELL0:OUT.LC3	MAC16.O_3
TCELL0:OUT.LC4	MAC16.O_4
TCELL0:OUT.LC5	MAC16.O_5
TCELL0:OUT.LC6	MAC16.O_6
TCELL0:OUT.LC7	MAC16.O_7
TCELL1:IMUX.LC0.I0	MAC16.BHOLD
TCELL1:IMUX.LC0.I1	MAC16.B_8
TCELL1:IMUX.LC0.I3	MAC16.B_0
TCELL1:IMUX.LC1.I1	MAC16.B_9
TCELL1:IMUX.LC1.I3	MAC16.B_1
TCELL1:IMUX.LC2.I1	MAC16.B_10
TCELL1:IMUX.LC2.I3	MAC16.B_2
TCELL1:IMUX.LC3.I1	MAC16.B_11
TCELL1:IMUX.LC3.I3	MAC16.B_3
TCELL1:IMUX.LC4.I1	MAC16.B_12
TCELL1:IMUX.LC4.I3	MAC16.B_4
TCELL1:IMUX.LC5.I1	MAC16.B_13
TCELL1:IMUX.LC5.I3	MAC16.B_5
TCELL1:IMUX.LC6.I1	MAC16.B_14
TCELL1:IMUX.LC6.I3	MAC16.B_6
TCELL1:IMUX.LC7.I1	MAC16.B_15
TCELL1:IMUX.LC7.I3	MAC16.B_7
TCELL1:IMUX.RST	MAC16.IRSTTOP
TCELL1:OUT.LC0	MAC16.O_8
TCELL1:OUT.LC1	MAC16.O_9
TCELL1:OUT.LC2	MAC16.O_10
TCELL1:OUT.LC3	MAC16.O_11
TCELL1:OUT.LC4	MAC16.O_12
TCELL1:OUT.LC5	MAC16.O_13
TCELL1:OUT.LC6	MAC16.O_14
TCELL1:OUT.LC7	MAC16.O_15
TCELL2:IMUX.LC0.I0	MAC16.AHOLD
TCELL2:IMUX.LC0.I1	MAC16.A_8
TCELL2:IMUX.LC0.I3	MAC16.A_0
TCELL2:IMUX.LC1.I1	MAC16.A_9
TCELL2:IMUX.LC1.I3	MAC16.A_1
TCELL2:IMUX.LC2.I1	MAC16.A_10
TCELL2:IMUX.LC2.I3	MAC16.A_2
TCELL2:IMUX.LC3.I1	MAC16.A_11
TCELL2:IMUX.LC3.I3	MAC16.A_3
TCELL2:IMUX.LC4.I1	MAC16.A_12
TCELL2:IMUX.LC4.I3	MAC16.A_4
TCELL2:IMUX.LC5.I1	MAC16.A_13
TCELL2:IMUX.LC5.I3	MAC16.A_5
TCELL2:IMUX.LC6.I1	MAC16.A_14
TCELL2:IMUX.LC6.I3	MAC16.A_6
TCELL2:IMUX.LC7.I1	MAC16.A_15
TCELL2:IMUX.LC7.I3	MAC16.A_7
TCELL2:IMUX.CLK	MAC16.CLK
TCELL2:IMUX.RST	MAC16.ORSTBOT
TCELL2:IMUX.CE	MAC16.CE
TCELL2:OUT.LC0	MAC16.O_16
TCELL2:OUT.LC1	MAC16.O_17
TCELL2:OUT.LC2	MAC16.O_18
TCELL2:OUT.LC3	MAC16.O_19
TCELL2:OUT.LC4	MAC16.O_20
TCELL2:OUT.LC5	MAC16.O_21
TCELL2:OUT.LC6	MAC16.O_22
TCELL2:OUT.LC7	MAC16.O_23
TCELL3:IMUX.LC0.I0	MAC16.CHOLD
TCELL3:IMUX.LC0.I1	MAC16.C_8
TCELL3:IMUX.LC0.I3	MAC16.C_0
TCELL3:IMUX.LC1.I0	MAC16.OHOLDTOP
TCELL3:IMUX.LC1.I1	MAC16.C_9
TCELL3:IMUX.LC1.I3	MAC16.C_1
TCELL3:IMUX.LC2.I0	MAC16.OLOADTOP
TCELL3:IMUX.LC2.I1	MAC16.C_10
TCELL3:IMUX.LC2.I3	MAC16.C_2
TCELL3:IMUX.LC3.I0	MAC16.ADDSUBTOP
TCELL3:IMUX.LC3.I1	MAC16.C_11
TCELL3:IMUX.LC3.I3	MAC16.C_3
TCELL3:IMUX.LC4.I1	MAC16.C_12
TCELL3:IMUX.LC4.I3	MAC16.C_4
TCELL3:IMUX.LC5.I1	MAC16.C_13
TCELL3:IMUX.LC5.I3	MAC16.C_5
TCELL3:IMUX.LC6.I1	MAC16.C_14
TCELL3:IMUX.LC6.I3	MAC16.C_6
TCELL3:IMUX.LC7.I1	MAC16.C_15
TCELL3:IMUX.LC7.I3	MAC16.C_7
TCELL3:IMUX.RST	MAC16.ORSTTOP
TCELL3:OUT.LC0	MAC16.O_24
TCELL3:OUT.LC1	MAC16.O_25
TCELL3:OUT.LC2	MAC16.O_26
TCELL3:OUT.LC3	MAC16.O_27
TCELL3:OUT.LC4	MAC16.O_28
TCELL3:OUT.LC5	MAC16.O_29
TCELL3:OUT.LC6	MAC16.O_30
TCELL3:OUT.LC7	MAC16.O_31
TCELL4:OUT.LC0	MAC16.CO

Bitstream

siliconblue MAC16_TRIM bittile 0
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	MAC16:A_REG
1	-	-	-	-	-	-	-	MAC16:C_REG
2	-	-	-	-	-	-	-	MAC16:D_REG
3	-	-	-	-	-	-	-	MAC16:B_REG
4	-	-	-	-	-	-	-	MAC16:BOT_8x8_MULT_REG
5	-	-	-	-	-	-	-	MAC16:TOP_8x8_MULT_REG
6	-	-	-	-	-	-	-	MAC16:PIPELINE_16x16_MULT_REG2
7	-	-	-	-	-	-	-	MAC16:PIPELINE_16x16_MULT_REG1

siliconblue MAC16_TRIM bittile 1
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	MAC16:TOPOUTPUT_SELECT[0]
2	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-
4	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	MAC16:BOTOUTPUT_SELECT[0]
7	-	-	-	-	-	-	-	MAC16:TOPADDSUB_CARRYSELECT[1]

siliconblue MAC16_TRIM bittile 2
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	MAC16:BOTADDSUB_LOWERINPUT[0]
1	-	-	-	-	-	-	-	MAC16:BOTOUTPUT_SELECT[1]
2	-	-	-	-	-	-	-	MAC16:BOTADDSUB_UPPERINPUT
3	-	-	-	-	-	-	-	MAC16:BOTADDSUB_LOWERINPUT[1]
4	-	-	-	-	-	-	-	MAC16:BOTADDSUB_CARRYSELECT[1]
5	-	-	-	-	-	-	-	MAC16:BOTADDSUB_CARRYSELECT[0]
6	-	-	-	-	-	-	-	MAC16:A_SIGNED
7	-	-	-	-	-	-	-	MAC16:MODE_8x8

siliconblue MAC16_TRIM bittile 3
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	MAC16:B_SIGNED

siliconblue MAC16_TRIM bittile 4
Frame	Bit
Frame	0	1	2	3	4	5	6	7
0	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	MAC16:TOPOUTPUT_SELECT[1]
3	-	-	-	-	-	-	-	-
4	-	-	-	-	-	-	-	MAC16:TOPADDSUB_LOWERINPUT[1]
5	-	-	-	-	-	-	-	MAC16:TOPADDSUB_LOWERINPUT[0]
6	-	-	-	-	-	-	-	MAC16:TOPADDSUB_CARRYSELECT[0]
7	-	-	-	-	-	-	-	MAC16:TOPADDSUB_UPPERINPUT

MAC16:A_REG	0.0.7
MAC16:A_SIGNED	2.6.7
MAC16:BOTADDSUB_UPPERINPUT	2.2.7
MAC16:BOT_8x8_MULT_REG	0.4.7
MAC16:B_REG	0.3.7
MAC16:B_SIGNED	3.1.7
MAC16:C_REG	0.1.7
MAC16:D_REG	0.2.7
MAC16:MODE_8x8	2.7.7
MAC16:PIPELINE_16x16_MULT_REG1	0.7.7
MAC16:PIPELINE_16x16_MULT_REG2	0.6.7
MAC16:TOPADDSUB_UPPERINPUT	4.7.7
MAC16:TOP_8x8_MULT_REG	0.5.7
non-inverted	[0]

MAC16:BOTADDSUB_CARRYSELECT	2.4.7	2.5.7
MAC16:BOTADDSUB_LOWERINPUT	2.3.7	2.0.7
MAC16:BOTOUTPUT_SELECT	2.1.7	1.6.7
MAC16:TOPADDSUB_CARRYSELECT	1.7.7	4.6.7
MAC16:TOPADDSUB_LOWERINPUT	4.4.7	4.5.7
MAC16:TOPOUTPUT_SELECT	4.2.7	1.1.7
non-inverted	[1]	[0]

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