SPRAM
Tile SPRAM
Cells: 4 IRIs: 0
Bel SPRAM0
Pin | Direction | Wires |
---|---|---|
ADDRESS_0 | input | TCELL1:IMUX.LC0.I1 |
ADDRESS_1 | input | TCELL1:IMUX.LC1.I1 |
ADDRESS_10 | input | TCELL1:IMUX.LC2.I0 |
ADDRESS_11 | input | TCELL1:IMUX.LC3.I0 |
ADDRESS_12 | input | TCELL1:IMUX.LC4.I0 |
ADDRESS_13 | input | TCELL1:IMUX.LC5.I0 |
ADDRESS_2 | input | TCELL1:IMUX.LC2.I1 |
ADDRESS_3 | input | TCELL1:IMUX.LC3.I1 |
ADDRESS_4 | input | TCELL1:IMUX.LC4.I1 |
ADDRESS_5 | input | TCELL1:IMUX.LC5.I1 |
ADDRESS_6 | input | TCELL1:IMUX.LC6.I1 |
ADDRESS_7 | input | TCELL1:IMUX.LC7.I1 |
ADDRESS_8 | input | TCELL1:IMUX.LC0.I0 |
ADDRESS_9 | input | TCELL1:IMUX.LC1.I0 |
CHIPSELECT | input | TCELL2:IMUX.LC6.I1 |
CLOCK | input | TCELL0:IMUX.CLK |
DATAIN_0 | input | TCELL0:IMUX.LC0.I3 |
DATAIN_1 | input | TCELL0:IMUX.LC1.I3 |
DATAIN_10 | input | TCELL0:IMUX.LC2.I1 |
DATAIN_11 | input | TCELL0:IMUX.LC3.I1 |
DATAIN_12 | input | TCELL0:IMUX.LC4.I1 |
DATAIN_13 | input | TCELL0:IMUX.LC5.I1 |
DATAIN_14 | input | TCELL0:IMUX.LC6.I1 |
DATAIN_15 | input | TCELL0:IMUX.LC7.I1 |
DATAIN_2 | input | TCELL0:IMUX.LC2.I3 |
DATAIN_3 | input | TCELL0:IMUX.LC3.I3 |
DATAIN_4 | input | TCELL0:IMUX.LC4.I3 |
DATAIN_5 | input | TCELL0:IMUX.LC5.I3 |
DATAIN_6 | input | TCELL0:IMUX.LC6.I3 |
DATAIN_7 | input | TCELL0:IMUX.LC7.I3 |
DATAIN_8 | input | TCELL0:IMUX.LC0.I1 |
DATAIN_9 | input | TCELL0:IMUX.LC1.I1 |
DATAOUT_0 | output | TCELL0:OUT.LC0 |
DATAOUT_1 | output | TCELL0:OUT.LC1 |
DATAOUT_10 | output | TCELL1:OUT.LC2 |
DATAOUT_11 | output | TCELL1:OUT.LC3 |
DATAOUT_12 | output | TCELL1:OUT.LC4 |
DATAOUT_13 | output | TCELL1:OUT.LC5 |
DATAOUT_14 | output | TCELL1:OUT.LC6 |
DATAOUT_15 | output | TCELL1:OUT.LC7 |
DATAOUT_2 | output | TCELL0:OUT.LC2 |
DATAOUT_3 | output | TCELL0:OUT.LC3 |
DATAOUT_4 | output | TCELL0:OUT.LC4 |
DATAOUT_5 | output | TCELL0:OUT.LC5 |
DATAOUT_6 | output | TCELL0:OUT.LC6 |
DATAOUT_7 | output | TCELL0:OUT.LC7 |
DATAOUT_8 | output | TCELL1:OUT.LC0 |
DATAOUT_9 | output | TCELL1:OUT.LC1 |
MASKWREN_0 | input | TCELL2:IMUX.LC0.I0 |
MASKWREN_1 | input | TCELL2:IMUX.LC1.I0 |
MASKWREN_2 | input | TCELL2:IMUX.LC2.I0 |
MASKWREN_3 | input | TCELL2:IMUX.LC3.I0 |
POWEROFF | input | TCELL3:IMUX.LC4.I3 |
RDMARGINEN | input | TCELL3:IMUX.LC6.I3 |
RDMARGIN_0 | input | TCELL3:IMUX.LC7.I3 |
RDMARGIN_1 | input | TCELL3:IMUX.LC0.I1 |
RDMARGIN_2 | input | TCELL3:IMUX.LC1.I1 |
RDMARGIN_3 | input | TCELL3:IMUX.LC2.I1 |
SLEEP | input | TCELL3:IMUX.LC2.I3 |
STANDBY | input | TCELL3:IMUX.LC0.I3 |
TEST | input | TCELL3:IMUX.LC3.I1 |
WREN | input | TCELL2:IMUX.LC4.I1 |
Bel SPRAM1
Pin | Direction | Wires |
---|---|---|
ADDRESS_0 | input | TCELL1:IMUX.LC6.I0 |
ADDRESS_1 | input | TCELL1:IMUX.LC7.I0 |
ADDRESS_10 | input | TCELL2:IMUX.LC0.I1 |
ADDRESS_11 | input | TCELL2:IMUX.LC1.I1 |
ADDRESS_12 | input | TCELL2:IMUX.LC2.I1 |
ADDRESS_13 | input | TCELL2:IMUX.LC3.I1 |
ADDRESS_2 | input | TCELL2:IMUX.LC0.I3 |
ADDRESS_3 | input | TCELL2:IMUX.LC1.I3 |
ADDRESS_4 | input | TCELL2:IMUX.LC2.I3 |
ADDRESS_5 | input | TCELL2:IMUX.LC3.I3 |
ADDRESS_6 | input | TCELL2:IMUX.LC4.I3 |
ADDRESS_7 | input | TCELL2:IMUX.LC5.I3 |
ADDRESS_8 | input | TCELL2:IMUX.LC6.I3 |
ADDRESS_9 | input | TCELL2:IMUX.LC7.I3 |
CHIPSELECT | input | TCELL2:IMUX.LC7.I1 |
CLOCK | input | TCELL1:IMUX.CLK |
DATAIN_0 | input | TCELL0:IMUX.LC0.I0 |
DATAIN_1 | input | TCELL0:IMUX.LC1.I0 |
DATAIN_10 | input | TCELL1:IMUX.LC2.I3 |
DATAIN_11 | input | TCELL1:IMUX.LC3.I3 |
DATAIN_12 | input | TCELL1:IMUX.LC4.I3 |
DATAIN_13 | input | TCELL1:IMUX.LC5.I3 |
DATAIN_14 | input | TCELL1:IMUX.LC6.I3 |
DATAIN_15 | input | TCELL1:IMUX.LC7.I3 |
DATAIN_2 | input | TCELL0:IMUX.LC2.I0 |
DATAIN_3 | input | TCELL0:IMUX.LC3.I0 |
DATAIN_4 | input | TCELL0:IMUX.LC4.I0 |
DATAIN_5 | input | TCELL0:IMUX.LC5.I0 |
DATAIN_6 | input | TCELL0:IMUX.LC6.I0 |
DATAIN_7 | input | TCELL0:IMUX.LC7.I0 |
DATAIN_8 | input | TCELL1:IMUX.LC0.I3 |
DATAIN_9 | input | TCELL1:IMUX.LC1.I3 |
DATAOUT_0 | output | TCELL2:OUT.LC0 |
DATAOUT_1 | output | TCELL2:OUT.LC1 |
DATAOUT_10 | output | TCELL3:OUT.LC2 |
DATAOUT_11 | output | TCELL3:OUT.LC3 |
DATAOUT_12 | output | TCELL3:OUT.LC4 |
DATAOUT_13 | output | TCELL3:OUT.LC5 |
DATAOUT_14 | output | TCELL3:OUT.LC6 |
DATAOUT_15 | output | TCELL3:OUT.LC7 |
DATAOUT_2 | output | TCELL2:OUT.LC2 |
DATAOUT_3 | output | TCELL2:OUT.LC3 |
DATAOUT_4 | output | TCELL2:OUT.LC4 |
DATAOUT_5 | output | TCELL2:OUT.LC5 |
DATAOUT_6 | output | TCELL2:OUT.LC6 |
DATAOUT_7 | output | TCELL2:OUT.LC7 |
DATAOUT_8 | output | TCELL3:OUT.LC0 |
DATAOUT_9 | output | TCELL3:OUT.LC1 |
MASKWREN_0 | input | TCELL2:IMUX.LC4.I0 |
MASKWREN_1 | input | TCELL2:IMUX.LC5.I0 |
MASKWREN_2 | input | TCELL2:IMUX.LC6.I0 |
MASKWREN_3 | input | TCELL2:IMUX.LC7.I0 |
POWEROFF | input | TCELL3:IMUX.LC5.I3 |
RDMARGINEN | input | TCELL3:IMUX.LC6.I3 |
RDMARGIN_0 | input | TCELL3:IMUX.LC7.I3 |
RDMARGIN_1 | input | TCELL3:IMUX.LC0.I1 |
RDMARGIN_2 | input | TCELL3:IMUX.LC1.I1 |
RDMARGIN_3 | input | TCELL3:IMUX.LC2.I1 |
SLEEP | input | TCELL3:IMUX.LC3.I3 |
STANDBY | input | TCELL3:IMUX.LC1.I3 |
TEST | input | TCELL3:IMUX.LC3.I1 |
WREN | input | TCELL2:IMUX.LC5.I1 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX.LC0.I0 | SPRAM1.DATAIN_0 |
TCELL0:IMUX.LC0.I1 | SPRAM0.DATAIN_8 |
TCELL0:IMUX.LC0.I3 | SPRAM0.DATAIN_0 |
TCELL0:IMUX.LC1.I0 | SPRAM1.DATAIN_1 |
TCELL0:IMUX.LC1.I1 | SPRAM0.DATAIN_9 |
TCELL0:IMUX.LC1.I3 | SPRAM0.DATAIN_1 |
TCELL0:IMUX.LC2.I0 | SPRAM1.DATAIN_2 |
TCELL0:IMUX.LC2.I1 | SPRAM0.DATAIN_10 |
TCELL0:IMUX.LC2.I3 | SPRAM0.DATAIN_2 |
TCELL0:IMUX.LC3.I0 | SPRAM1.DATAIN_3 |
TCELL0:IMUX.LC3.I1 | SPRAM0.DATAIN_11 |
TCELL0:IMUX.LC3.I3 | SPRAM0.DATAIN_3 |
TCELL0:IMUX.LC4.I0 | SPRAM1.DATAIN_4 |
TCELL0:IMUX.LC4.I1 | SPRAM0.DATAIN_12 |
TCELL0:IMUX.LC4.I3 | SPRAM0.DATAIN_4 |
TCELL0:IMUX.LC5.I0 | SPRAM1.DATAIN_5 |
TCELL0:IMUX.LC5.I1 | SPRAM0.DATAIN_13 |
TCELL0:IMUX.LC5.I3 | SPRAM0.DATAIN_5 |
TCELL0:IMUX.LC6.I0 | SPRAM1.DATAIN_6 |
TCELL0:IMUX.LC6.I1 | SPRAM0.DATAIN_14 |
TCELL0:IMUX.LC6.I3 | SPRAM0.DATAIN_6 |
TCELL0:IMUX.LC7.I0 | SPRAM1.DATAIN_7 |
TCELL0:IMUX.LC7.I1 | SPRAM0.DATAIN_15 |
TCELL0:IMUX.LC7.I3 | SPRAM0.DATAIN_7 |
TCELL0:IMUX.CLK | SPRAM0.CLOCK |
TCELL0:OUT.LC0 | SPRAM0.DATAOUT_0 |
TCELL0:OUT.LC1 | SPRAM0.DATAOUT_1 |
TCELL0:OUT.LC2 | SPRAM0.DATAOUT_2 |
TCELL0:OUT.LC3 | SPRAM0.DATAOUT_3 |
TCELL0:OUT.LC4 | SPRAM0.DATAOUT_4 |
TCELL0:OUT.LC5 | SPRAM0.DATAOUT_5 |
TCELL0:OUT.LC6 | SPRAM0.DATAOUT_6 |
TCELL0:OUT.LC7 | SPRAM0.DATAOUT_7 |
TCELL1:IMUX.LC0.I0 | SPRAM0.ADDRESS_8 |
TCELL1:IMUX.LC0.I1 | SPRAM0.ADDRESS_0 |
TCELL1:IMUX.LC0.I3 | SPRAM1.DATAIN_8 |
TCELL1:IMUX.LC1.I0 | SPRAM0.ADDRESS_9 |
TCELL1:IMUX.LC1.I1 | SPRAM0.ADDRESS_1 |
TCELL1:IMUX.LC1.I3 | SPRAM1.DATAIN_9 |
TCELL1:IMUX.LC2.I0 | SPRAM0.ADDRESS_10 |
TCELL1:IMUX.LC2.I1 | SPRAM0.ADDRESS_2 |
TCELL1:IMUX.LC2.I3 | SPRAM1.DATAIN_10 |
TCELL1:IMUX.LC3.I0 | SPRAM0.ADDRESS_11 |
TCELL1:IMUX.LC3.I1 | SPRAM0.ADDRESS_3 |
TCELL1:IMUX.LC3.I3 | SPRAM1.DATAIN_11 |
TCELL1:IMUX.LC4.I0 | SPRAM0.ADDRESS_12 |
TCELL1:IMUX.LC4.I1 | SPRAM0.ADDRESS_4 |
TCELL1:IMUX.LC4.I3 | SPRAM1.DATAIN_12 |
TCELL1:IMUX.LC5.I0 | SPRAM0.ADDRESS_13 |
TCELL1:IMUX.LC5.I1 | SPRAM0.ADDRESS_5 |
TCELL1:IMUX.LC5.I3 | SPRAM1.DATAIN_13 |
TCELL1:IMUX.LC6.I0 | SPRAM1.ADDRESS_0 |
TCELL1:IMUX.LC6.I1 | SPRAM0.ADDRESS_6 |
TCELL1:IMUX.LC6.I3 | SPRAM1.DATAIN_14 |
TCELL1:IMUX.LC7.I0 | SPRAM1.ADDRESS_1 |
TCELL1:IMUX.LC7.I1 | SPRAM0.ADDRESS_7 |
TCELL1:IMUX.LC7.I3 | SPRAM1.DATAIN_15 |
TCELL1:IMUX.CLK | SPRAM1.CLOCK |
TCELL1:OUT.LC0 | SPRAM0.DATAOUT_8 |
TCELL1:OUT.LC1 | SPRAM0.DATAOUT_9 |
TCELL1:OUT.LC2 | SPRAM0.DATAOUT_10 |
TCELL1:OUT.LC3 | SPRAM0.DATAOUT_11 |
TCELL1:OUT.LC4 | SPRAM0.DATAOUT_12 |
TCELL1:OUT.LC5 | SPRAM0.DATAOUT_13 |
TCELL1:OUT.LC6 | SPRAM0.DATAOUT_14 |
TCELL1:OUT.LC7 | SPRAM0.DATAOUT_15 |
TCELL2:IMUX.LC0.I0 | SPRAM0.MASKWREN_0 |
TCELL2:IMUX.LC0.I1 | SPRAM1.ADDRESS_10 |
TCELL2:IMUX.LC0.I3 | SPRAM1.ADDRESS_2 |
TCELL2:IMUX.LC1.I0 | SPRAM0.MASKWREN_1 |
TCELL2:IMUX.LC1.I1 | SPRAM1.ADDRESS_11 |
TCELL2:IMUX.LC1.I3 | SPRAM1.ADDRESS_3 |
TCELL2:IMUX.LC2.I0 | SPRAM0.MASKWREN_2 |
TCELL2:IMUX.LC2.I1 | SPRAM1.ADDRESS_12 |
TCELL2:IMUX.LC2.I3 | SPRAM1.ADDRESS_4 |
TCELL2:IMUX.LC3.I0 | SPRAM0.MASKWREN_3 |
TCELL2:IMUX.LC3.I1 | SPRAM1.ADDRESS_13 |
TCELL2:IMUX.LC3.I3 | SPRAM1.ADDRESS_5 |
TCELL2:IMUX.LC4.I0 | SPRAM1.MASKWREN_0 |
TCELL2:IMUX.LC4.I1 | SPRAM0.WREN |
TCELL2:IMUX.LC4.I3 | SPRAM1.ADDRESS_6 |
TCELL2:IMUX.LC5.I0 | SPRAM1.MASKWREN_1 |
TCELL2:IMUX.LC5.I1 | SPRAM1.WREN |
TCELL2:IMUX.LC5.I3 | SPRAM1.ADDRESS_7 |
TCELL2:IMUX.LC6.I0 | SPRAM1.MASKWREN_2 |
TCELL2:IMUX.LC6.I1 | SPRAM0.CHIPSELECT |
TCELL2:IMUX.LC6.I3 | SPRAM1.ADDRESS_8 |
TCELL2:IMUX.LC7.I0 | SPRAM1.MASKWREN_3 |
TCELL2:IMUX.LC7.I1 | SPRAM1.CHIPSELECT |
TCELL2:IMUX.LC7.I3 | SPRAM1.ADDRESS_9 |
TCELL2:OUT.LC0 | SPRAM1.DATAOUT_0 |
TCELL2:OUT.LC1 | SPRAM1.DATAOUT_1 |
TCELL2:OUT.LC2 | SPRAM1.DATAOUT_2 |
TCELL2:OUT.LC3 | SPRAM1.DATAOUT_3 |
TCELL2:OUT.LC4 | SPRAM1.DATAOUT_4 |
TCELL2:OUT.LC5 | SPRAM1.DATAOUT_5 |
TCELL2:OUT.LC6 | SPRAM1.DATAOUT_6 |
TCELL2:OUT.LC7 | SPRAM1.DATAOUT_7 |
TCELL3:IMUX.LC0.I1 | SPRAM0.RDMARGIN_1, SPRAM1.RDMARGIN_1 |
TCELL3:IMUX.LC0.I3 | SPRAM0.STANDBY |
TCELL3:IMUX.LC1.I1 | SPRAM0.RDMARGIN_2, SPRAM1.RDMARGIN_2 |
TCELL3:IMUX.LC1.I3 | SPRAM1.STANDBY |
TCELL3:IMUX.LC2.I1 | SPRAM0.RDMARGIN_3, SPRAM1.RDMARGIN_3 |
TCELL3:IMUX.LC2.I3 | SPRAM0.SLEEP |
TCELL3:IMUX.LC3.I1 | SPRAM0.TEST, SPRAM1.TEST |
TCELL3:IMUX.LC3.I3 | SPRAM1.SLEEP |
TCELL3:IMUX.LC4.I3 | SPRAM0.POWEROFF |
TCELL3:IMUX.LC5.I3 | SPRAM1.POWEROFF |
TCELL3:IMUX.LC6.I3 | SPRAM0.RDMARGINEN, SPRAM1.RDMARGINEN |
TCELL3:IMUX.LC7.I3 | SPRAM0.RDMARGIN_0, SPRAM1.RDMARGIN_0 |
TCELL3:OUT.LC0 | SPRAM1.DATAOUT_8 |
TCELL3:OUT.LC1 | SPRAM1.DATAOUT_9 |
TCELL3:OUT.LC2 | SPRAM1.DATAOUT_10 |
TCELL3:OUT.LC3 | SPRAM1.DATAOUT_11 |
TCELL3:OUT.LC4 | SPRAM1.DATAOUT_12 |
TCELL3:OUT.LC5 | SPRAM1.DATAOUT_13 |
TCELL3:OUT.LC6 | SPRAM1.DATAOUT_14 |
TCELL3:OUT.LC7 | SPRAM1.DATAOUT_15 |
Bitstream
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | SPRAM1:ENABLE |
1 | - | - | - | - | - | - | - | SPRAM0:ENABLE |
SPRAM0:ENABLE | 0.1.7 |
---|---|
SPRAM1:ENABLE | 0.0.7 |
non-inverted | [0] |