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SPRAM

Tile SPRAM

Cells: 4

Bel SPRAM0

siliconblue SPRAM bel SPRAM0
PinDirectionWires
ADDRESS_0inputTCELL1:IMUX.LC0.I1
ADDRESS_1inputTCELL1:IMUX.LC1.I1
ADDRESS_10inputTCELL1:IMUX.LC2.I0
ADDRESS_11inputTCELL1:IMUX.LC3.I0
ADDRESS_12inputTCELL1:IMUX.LC4.I0
ADDRESS_13inputTCELL1:IMUX.LC5.I0
ADDRESS_2inputTCELL1:IMUX.LC2.I1
ADDRESS_3inputTCELL1:IMUX.LC3.I1
ADDRESS_4inputTCELL1:IMUX.LC4.I1
ADDRESS_5inputTCELL1:IMUX.LC5.I1
ADDRESS_6inputTCELL1:IMUX.LC6.I1
ADDRESS_7inputTCELL1:IMUX.LC7.I1
ADDRESS_8inputTCELL1:IMUX.LC0.I0
ADDRESS_9inputTCELL1:IMUX.LC1.I0
CHIPSELECTinputTCELL2:IMUX.LC6.I1
CLOCKinputTCELL0:IMUX.CLK.OPTINV
DATAIN_0inputTCELL0:IMUX.LC0.I3
DATAIN_1inputTCELL0:IMUX.LC1.I3
DATAIN_10inputTCELL0:IMUX.LC2.I1
DATAIN_11inputTCELL0:IMUX.LC3.I1
DATAIN_12inputTCELL0:IMUX.LC4.I1
DATAIN_13inputTCELL0:IMUX.LC5.I1
DATAIN_14inputTCELL0:IMUX.LC6.I1
DATAIN_15inputTCELL0:IMUX.LC7.I1
DATAIN_2inputTCELL0:IMUX.LC2.I3
DATAIN_3inputTCELL0:IMUX.LC3.I3
DATAIN_4inputTCELL0:IMUX.LC4.I3
DATAIN_5inputTCELL0:IMUX.LC5.I3
DATAIN_6inputTCELL0:IMUX.LC6.I3
DATAIN_7inputTCELL0:IMUX.LC7.I3
DATAIN_8inputTCELL0:IMUX.LC0.I1
DATAIN_9inputTCELL0:IMUX.LC1.I1
DATAOUT_0outputTCELL0:OUT.LC0
DATAOUT_1outputTCELL0:OUT.LC1
DATAOUT_10outputTCELL1:OUT.LC2
DATAOUT_11outputTCELL1:OUT.LC3
DATAOUT_12outputTCELL1:OUT.LC4
DATAOUT_13outputTCELL1:OUT.LC5
DATAOUT_14outputTCELL1:OUT.LC6
DATAOUT_15outputTCELL1:OUT.LC7
DATAOUT_2outputTCELL0:OUT.LC2
DATAOUT_3outputTCELL0:OUT.LC3
DATAOUT_4outputTCELL0:OUT.LC4
DATAOUT_5outputTCELL0:OUT.LC5
DATAOUT_6outputTCELL0:OUT.LC6
DATAOUT_7outputTCELL0:OUT.LC7
DATAOUT_8outputTCELL1:OUT.LC0
DATAOUT_9outputTCELL1:OUT.LC1
MASKWREN_0inputTCELL2:IMUX.LC0.I0
MASKWREN_1inputTCELL2:IMUX.LC1.I0
MASKWREN_2inputTCELL2:IMUX.LC2.I0
MASKWREN_3inputTCELL2:IMUX.LC3.I0
POWEROFFinputTCELL3:IMUX.LC4.I3
RDMARGINENinputTCELL3:IMUX.LC6.I3
RDMARGIN_0inputTCELL3:IMUX.LC7.I3
RDMARGIN_1inputTCELL3:IMUX.LC0.I1
RDMARGIN_2inputTCELL3:IMUX.LC1.I1
RDMARGIN_3inputTCELL3:IMUX.LC2.I1
SLEEPinputTCELL3:IMUX.LC2.I3
STANDBYinputTCELL3:IMUX.LC0.I3
TESTinputTCELL3:IMUX.LC3.I1
WRENinputTCELL2:IMUX.LC4.I1

Bel SPRAM1

siliconblue SPRAM bel SPRAM1
PinDirectionWires
ADDRESS_0inputTCELL1:IMUX.LC6.I0
ADDRESS_1inputTCELL1:IMUX.LC7.I0
ADDRESS_10inputTCELL2:IMUX.LC0.I1
ADDRESS_11inputTCELL2:IMUX.LC1.I1
ADDRESS_12inputTCELL2:IMUX.LC2.I1
ADDRESS_13inputTCELL2:IMUX.LC3.I1
ADDRESS_2inputTCELL2:IMUX.LC0.I3
ADDRESS_3inputTCELL2:IMUX.LC1.I3
ADDRESS_4inputTCELL2:IMUX.LC2.I3
ADDRESS_5inputTCELL2:IMUX.LC3.I3
ADDRESS_6inputTCELL2:IMUX.LC4.I3
ADDRESS_7inputTCELL2:IMUX.LC5.I3
ADDRESS_8inputTCELL2:IMUX.LC6.I3
ADDRESS_9inputTCELL2:IMUX.LC7.I3
CHIPSELECTinputTCELL2:IMUX.LC7.I1
CLOCKinputTCELL1:IMUX.CLK.OPTINV
DATAIN_0inputTCELL0:IMUX.LC0.I0
DATAIN_1inputTCELL0:IMUX.LC1.I0
DATAIN_10inputTCELL1:IMUX.LC2.I3
DATAIN_11inputTCELL1:IMUX.LC3.I3
DATAIN_12inputTCELL1:IMUX.LC4.I3
DATAIN_13inputTCELL1:IMUX.LC5.I3
DATAIN_14inputTCELL1:IMUX.LC6.I3
DATAIN_15inputTCELL1:IMUX.LC7.I3
DATAIN_2inputTCELL0:IMUX.LC2.I0
DATAIN_3inputTCELL0:IMUX.LC3.I0
DATAIN_4inputTCELL0:IMUX.LC4.I0
DATAIN_5inputTCELL0:IMUX.LC5.I0
DATAIN_6inputTCELL0:IMUX.LC6.I0
DATAIN_7inputTCELL0:IMUX.LC7.I0
DATAIN_8inputTCELL1:IMUX.LC0.I3
DATAIN_9inputTCELL1:IMUX.LC1.I3
DATAOUT_0outputTCELL2:OUT.LC0
DATAOUT_1outputTCELL2:OUT.LC1
DATAOUT_10outputTCELL3:OUT.LC2
DATAOUT_11outputTCELL3:OUT.LC3
DATAOUT_12outputTCELL3:OUT.LC4
DATAOUT_13outputTCELL3:OUT.LC5
DATAOUT_14outputTCELL3:OUT.LC6
DATAOUT_15outputTCELL3:OUT.LC7
DATAOUT_2outputTCELL2:OUT.LC2
DATAOUT_3outputTCELL2:OUT.LC3
DATAOUT_4outputTCELL2:OUT.LC4
DATAOUT_5outputTCELL2:OUT.LC5
DATAOUT_6outputTCELL2:OUT.LC6
DATAOUT_7outputTCELL2:OUT.LC7
DATAOUT_8outputTCELL3:OUT.LC0
DATAOUT_9outputTCELL3:OUT.LC1
MASKWREN_0inputTCELL2:IMUX.LC4.I0
MASKWREN_1inputTCELL2:IMUX.LC5.I0
MASKWREN_2inputTCELL2:IMUX.LC6.I0
MASKWREN_3inputTCELL2:IMUX.LC7.I0
POWEROFFinputTCELL3:IMUX.LC5.I3
RDMARGINENinputTCELL3:IMUX.LC6.I3
RDMARGIN_0inputTCELL3:IMUX.LC7.I3
RDMARGIN_1inputTCELL3:IMUX.LC0.I1
RDMARGIN_2inputTCELL3:IMUX.LC1.I1
RDMARGIN_3inputTCELL3:IMUX.LC2.I1
SLEEPinputTCELL3:IMUX.LC3.I3
STANDBYinputTCELL3:IMUX.LC1.I3
TESTinputTCELL3:IMUX.LC3.I1
WRENinputTCELL2:IMUX.LC5.I1

Bel wires

siliconblue SPRAM bel wires
WirePins
TCELL0:IMUX.LC0.I0SPRAM1.DATAIN_0
TCELL0:IMUX.LC0.I1SPRAM0.DATAIN_8
TCELL0:IMUX.LC0.I3SPRAM0.DATAIN_0
TCELL0:IMUX.LC1.I0SPRAM1.DATAIN_1
TCELL0:IMUX.LC1.I1SPRAM0.DATAIN_9
TCELL0:IMUX.LC1.I3SPRAM0.DATAIN_1
TCELL0:IMUX.LC2.I0SPRAM1.DATAIN_2
TCELL0:IMUX.LC2.I1SPRAM0.DATAIN_10
TCELL0:IMUX.LC2.I3SPRAM0.DATAIN_2
TCELL0:IMUX.LC3.I0SPRAM1.DATAIN_3
TCELL0:IMUX.LC3.I1SPRAM0.DATAIN_11
TCELL0:IMUX.LC3.I3SPRAM0.DATAIN_3
TCELL0:IMUX.LC4.I0SPRAM1.DATAIN_4
TCELL0:IMUX.LC4.I1SPRAM0.DATAIN_12
TCELL0:IMUX.LC4.I3SPRAM0.DATAIN_4
TCELL0:IMUX.LC5.I0SPRAM1.DATAIN_5
TCELL0:IMUX.LC5.I1SPRAM0.DATAIN_13
TCELL0:IMUX.LC5.I3SPRAM0.DATAIN_5
TCELL0:IMUX.LC6.I0SPRAM1.DATAIN_6
TCELL0:IMUX.LC6.I1SPRAM0.DATAIN_14
TCELL0:IMUX.LC6.I3SPRAM0.DATAIN_6
TCELL0:IMUX.LC7.I0SPRAM1.DATAIN_7
TCELL0:IMUX.LC7.I1SPRAM0.DATAIN_15
TCELL0:IMUX.LC7.I3SPRAM0.DATAIN_7
TCELL0:IMUX.CLK.OPTINVSPRAM0.CLOCK
TCELL0:OUT.LC0SPRAM0.DATAOUT_0
TCELL0:OUT.LC1SPRAM0.DATAOUT_1
TCELL0:OUT.LC2SPRAM0.DATAOUT_2
TCELL0:OUT.LC3SPRAM0.DATAOUT_3
TCELL0:OUT.LC4SPRAM0.DATAOUT_4
TCELL0:OUT.LC5SPRAM0.DATAOUT_5
TCELL0:OUT.LC6SPRAM0.DATAOUT_6
TCELL0:OUT.LC7SPRAM0.DATAOUT_7
TCELL1:IMUX.LC0.I0SPRAM0.ADDRESS_8
TCELL1:IMUX.LC0.I1SPRAM0.ADDRESS_0
TCELL1:IMUX.LC0.I3SPRAM1.DATAIN_8
TCELL1:IMUX.LC1.I0SPRAM0.ADDRESS_9
TCELL1:IMUX.LC1.I1SPRAM0.ADDRESS_1
TCELL1:IMUX.LC1.I3SPRAM1.DATAIN_9
TCELL1:IMUX.LC2.I0SPRAM0.ADDRESS_10
TCELL1:IMUX.LC2.I1SPRAM0.ADDRESS_2
TCELL1:IMUX.LC2.I3SPRAM1.DATAIN_10
TCELL1:IMUX.LC3.I0SPRAM0.ADDRESS_11
TCELL1:IMUX.LC3.I1SPRAM0.ADDRESS_3
TCELL1:IMUX.LC3.I3SPRAM1.DATAIN_11
TCELL1:IMUX.LC4.I0SPRAM0.ADDRESS_12
TCELL1:IMUX.LC4.I1SPRAM0.ADDRESS_4
TCELL1:IMUX.LC4.I3SPRAM1.DATAIN_12
TCELL1:IMUX.LC5.I0SPRAM0.ADDRESS_13
TCELL1:IMUX.LC5.I1SPRAM0.ADDRESS_5
TCELL1:IMUX.LC5.I3SPRAM1.DATAIN_13
TCELL1:IMUX.LC6.I0SPRAM1.ADDRESS_0
TCELL1:IMUX.LC6.I1SPRAM0.ADDRESS_6
TCELL1:IMUX.LC6.I3SPRAM1.DATAIN_14
TCELL1:IMUX.LC7.I0SPRAM1.ADDRESS_1
TCELL1:IMUX.LC7.I1SPRAM0.ADDRESS_7
TCELL1:IMUX.LC7.I3SPRAM1.DATAIN_15
TCELL1:IMUX.CLK.OPTINVSPRAM1.CLOCK
TCELL1:OUT.LC0SPRAM0.DATAOUT_8
TCELL1:OUT.LC1SPRAM0.DATAOUT_9
TCELL1:OUT.LC2SPRAM0.DATAOUT_10
TCELL1:OUT.LC3SPRAM0.DATAOUT_11
TCELL1:OUT.LC4SPRAM0.DATAOUT_12
TCELL1:OUT.LC5SPRAM0.DATAOUT_13
TCELL1:OUT.LC6SPRAM0.DATAOUT_14
TCELL1:OUT.LC7SPRAM0.DATAOUT_15
TCELL2:IMUX.LC0.I0SPRAM0.MASKWREN_0
TCELL2:IMUX.LC0.I1SPRAM1.ADDRESS_10
TCELL2:IMUX.LC0.I3SPRAM1.ADDRESS_2
TCELL2:IMUX.LC1.I0SPRAM0.MASKWREN_1
TCELL2:IMUX.LC1.I1SPRAM1.ADDRESS_11
TCELL2:IMUX.LC1.I3SPRAM1.ADDRESS_3
TCELL2:IMUX.LC2.I0SPRAM0.MASKWREN_2
TCELL2:IMUX.LC2.I1SPRAM1.ADDRESS_12
TCELL2:IMUX.LC2.I3SPRAM1.ADDRESS_4
TCELL2:IMUX.LC3.I0SPRAM0.MASKWREN_3
TCELL2:IMUX.LC3.I1SPRAM1.ADDRESS_13
TCELL2:IMUX.LC3.I3SPRAM1.ADDRESS_5
TCELL2:IMUX.LC4.I0SPRAM1.MASKWREN_0
TCELL2:IMUX.LC4.I1SPRAM0.WREN
TCELL2:IMUX.LC4.I3SPRAM1.ADDRESS_6
TCELL2:IMUX.LC5.I0SPRAM1.MASKWREN_1
TCELL2:IMUX.LC5.I1SPRAM1.WREN
TCELL2:IMUX.LC5.I3SPRAM1.ADDRESS_7
TCELL2:IMUX.LC6.I0SPRAM1.MASKWREN_2
TCELL2:IMUX.LC6.I1SPRAM0.CHIPSELECT
TCELL2:IMUX.LC6.I3SPRAM1.ADDRESS_8
TCELL2:IMUX.LC7.I0SPRAM1.MASKWREN_3
TCELL2:IMUX.LC7.I1SPRAM1.CHIPSELECT
TCELL2:IMUX.LC7.I3SPRAM1.ADDRESS_9
TCELL2:OUT.LC0SPRAM1.DATAOUT_0
TCELL2:OUT.LC1SPRAM1.DATAOUT_1
TCELL2:OUT.LC2SPRAM1.DATAOUT_2
TCELL2:OUT.LC3SPRAM1.DATAOUT_3
TCELL2:OUT.LC4SPRAM1.DATAOUT_4
TCELL2:OUT.LC5SPRAM1.DATAOUT_5
TCELL2:OUT.LC6SPRAM1.DATAOUT_6
TCELL2:OUT.LC7SPRAM1.DATAOUT_7
TCELL3:IMUX.LC0.I1SPRAM0.RDMARGIN_1, SPRAM1.RDMARGIN_1
TCELL3:IMUX.LC0.I3SPRAM0.STANDBY
TCELL3:IMUX.LC1.I1SPRAM0.RDMARGIN_2, SPRAM1.RDMARGIN_2
TCELL3:IMUX.LC1.I3SPRAM1.STANDBY
TCELL3:IMUX.LC2.I1SPRAM0.RDMARGIN_3, SPRAM1.RDMARGIN_3
TCELL3:IMUX.LC2.I3SPRAM0.SLEEP
TCELL3:IMUX.LC3.I1SPRAM0.TEST, SPRAM1.TEST
TCELL3:IMUX.LC3.I3SPRAM1.SLEEP
TCELL3:IMUX.LC4.I3SPRAM0.POWEROFF
TCELL3:IMUX.LC5.I3SPRAM1.POWEROFF
TCELL3:IMUX.LC6.I3SPRAM0.RDMARGINEN, SPRAM1.RDMARGINEN
TCELL3:IMUX.LC7.I3SPRAM0.RDMARGIN_0, SPRAM1.RDMARGIN_0
TCELL3:OUT.LC0SPRAM1.DATAOUT_8
TCELL3:OUT.LC1SPRAM1.DATAOUT_9
TCELL3:OUT.LC2SPRAM1.DATAOUT_10
TCELL3:OUT.LC3SPRAM1.DATAOUT_11
TCELL3:OUT.LC4SPRAM1.DATAOUT_12
TCELL3:OUT.LC5SPRAM1.DATAOUT_13
TCELL3:OUT.LC6SPRAM1.DATAOUT_14
TCELL3:OUT.LC7SPRAM1.DATAOUT_15

Bitstream

siliconblue SPRAM bittile 0
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - SPRAM1:ENABLE
1 - - - - - - - SPRAM0:ENABLE
SPRAM0:ENABLE 0.1.7
SPRAM1:ENABLE 0.0.7
non-inverted [0]