On most SiliconBlue devices, the global nets are not connected directly to the IMUX and GOUT multiplexers within interconnect tiles — they pass through "column buffers" instead. Such column buffers have to be enabled via bitstream bits when necessary.
Every interconnect column is partitioned into two or three "clock columns". Each clock column is further partitioned into two "clock sub-columns" around the middle. The middle row of the clock column contains two sets of column buffers, driving the GLOBAL wires in the sourthern and northern sub-columns.
The rows_colbuf field of a chip in the database describes how columns are divided into clock columns. Every clock column is defined by three rows:
the middle row M
the start row B
the end row T
Rows B..M make up the southern clock sub-column of the given clock column, and rows M..E make up the northern clock sub-column. The column buffers driving the southern sub-column are located in row M - 1, except for BRAM columns on iCE65L01 and iCE40P01 where they are located in row M - 2 instead. The column buffers driving the northern sub-column are located in row M.
The following devices do not have column buffers:
iCE65L04
iCE65L08
iCE65P04
iCE40P03
On these devices, the global nets are permanently connected to all consumers, and the column buffer enable bits don't have to be set.