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General interconnect

The SiliconBlue general interconnect structure involves the following tile types:

  • PLB and INT_BRAM: the "center" tiles of the interconnect, connecting to four neighbouring tiles
  • IOI_W, IOI_E, IOI_S, IOI_N: the "edge" tiles of the interconnect, connecting to three neighbouring tiles

GLOBAL wires

There are 8 global wires:

  • GLOBAL.[0-7]: global wires

They are driven by the global interconnect. They can directly drive IMUX.CLK, IMUX.IO.ICLK, IMUX.IO.OCLK, IMUX.CE, IMUX.RST multiplexers. In addition to that, every non-IO tile has 4 special intermediate wires that can be driven by the GLOBAL.* wires and can be used to route them further to the LOCAL.* lines:

  • GOUT.[0-3]: intermediate wires for routing GLOBAL.* to LOCAL.*; can only be driven by GLOBAL.*

OUT wires

Every tile (including the corner tiles, otherwise devoid of interconnect) has 8 output wires, which are driven by the various bels within the FPGA:

  • OUT.LC[0-7]: bel output wires; note that, depending on tile type, some of them may actually alias other OUT wires, effectively making for fewer than 8 distinct outputs per tile:

    • PLB: all 8 wires are distinct; OUT.LC{i} corresponds directly to the output of LC i
    • INT_BRAM: all 8 wires are distinct
    • IOI_*: there are 4 distinct wires; OUT.LC[4-7] are aliased to OUT.LC[0-3]:
      • OUT.LC[04] is IO0.DIN0
      • OUT.LC[15] is IO0.DIN1
      • OUT.LC[26] is IO1.DIN0
      • OUT.LC[37] is IO1.DIN1
    • corner tiles: there's only one distinct wire (all 8 wires are aliased to each other)

The OUT wires are also visible in the 8 directly neighbouring tiles:

  • OUT.LC[0-7].W: the same as OUT.LC[0-7] of tile (x + 1, y)
  • OUT.LC[0-7].E: the same as OUT.LC[0-7] of tile (x - 1, y)
  • OUT.LC[0-7].S: the same as OUT.LC[0-7] of tile (x, y + 1)
  • OUT.LC[0-7].N: the same as OUT.LC[0-7] of tile (x, y - 1)
  • OUT.LC[0-7].WS: the same as OUT.LC[0-7] of tile (x + 1, y + 1)
  • OUT.LC[0-7].WN: the same as OUT.LC[0-7] of tile (x + 1, y - 1)
  • OUT.LC[0-7].ES: the same as OUT.LC[0-7] of tile (x - 1, y + 1)
  • OUT.LC[0-7].EN: the same as OUT.LC[0-7] of tile (x - 1, y - 1)

QUAD and LONG wires

The long-distance backbone of the interconnect consists of the QUAD (span-4) and LONG (span-12) wires:

  • QUAD.H[0-11].[0-4]: horizontal length-4 wires

    • QUAD.Ha.b in tile (x, y) is the same as QUAD.Ha.(b+1) in tile (x + 1, y)
  • QUAD.V[0-11].[0-4], QUAD.V[0-11].[1-4].W: vertical length-4 wires

    • QUAD.Va.b in tile (x, y) is the same as QUAD.Va.(b+1) in tile (x, y + 1)
    • QUAD.Va.b.W in tile (x, y) is the same as QUAD.Va.b in tile (x + 1, y)
  • LONG.H[01].[0-12]: horizontal length-12 wires

    • LONG.Ha.b in tile (x, y) is the same as LONG.Ha.(b+1) in tile (x + 1, y)
  • LONG.V[01].[0-12]: vertical length-12 wires

    • LONG.Va.b in tile (x, y) is the same as LONG.Va.(b+1) in tile (x, y + 1)

The interconnect in IO tiles is special:

  • in the IOI_W and IOI_E tiles:
    • there are no vertical LONG wires
    • there are only 4 sets of vertical QUAD wires (QUAD.V[0-3].*)
  • in the IOI_S and IOI_N tiles:
    • there are no horizontal LONG wires
    • there are only 4 sets of horizontal QUAD wires (QUAD.H[0-3].*)

Further, the corner tiles are special: the QUAD.H*.* wires of the horizontally adjacent IOI_[WE] tile are connected directly to the QUAD.V*.* wires of the vertically adjacent IOI_[SN] or PLB tile.

The LONG wires can be driven:

  • at many points along the wire: from OUT wires
  • at endpoints within "center" tiles: from endpoints of other LONG wires

The QUAD wires can be driven:

  • at many points along the wire: from OUT wires
  • at endpoints within "center" tiles: from endpoints of other QUAD wires
  • at .1 (for horizontal wires) or .3 (for vertical wires): from various segments of LONG wires of the same direction
  • at IO tiles: from other QUAD wires

LOCAL wires

Every tile has 32 (PLB, INT_BRAM) or 16 (IOI_*) local wires:

  • LOCAL.[0-3].[0-7]: local wires

    • IOI_* tiles only have LOCAL.[0-1].[0-7]

The LOCAL wires are an intermediate step between IMUX.* wires and other interconnect — every signal routed to IMUX.* must first pass through a LOCAL wire, except for some multiplexers that can also be directly driven by GLOBAL wires. They can be driven by:

  • QUAD wires
  • LONG wires
  • OUT wires (including ones of the 8 immediately neighbouring tiles)
  • GOUT wires (not in IO tiles)

IMUX wires

IMUX wires directly drive bel inputs. PLB and INT_BRAM tiles contain the following wires:

  • IMUX.LC[0-7].I[0-3]: "normal" inputs; in PLB tiles, they correspond to LCs in the obvious way
  • IMUX.CLK: a clock input; freely invertible, can be driven directly by all GLOBAL wires
  • IMUX.CE: a clock enable input; gates the IMUX.CLK input, can be driven directly by some GLOBAL wires
  • IMUX.RST: a reset input; can be driven directly by some GLOBAL wires

IOI_* tiles contain the following wires:

  • IMUX.IO[0-1].DOUT[0-1]: "normal" inputs, I/O data
  • IMUX.IO[0-1].OE: "normal" inputs, I/O output enable
  • IMUX.IO.EXTRA: "normal" input, used for various irregularly placed bels (such as PLLs)
  • IMUX.IO.ICLK and IMUX.IO.OCLK: clock inputs; freely invertible, can be driven directly by all GLOBAL wires
  • IMUX.CE: a clock enable input; gates the IMUX.IO.ICLK and IMUX.IO.OCLK inputs, can be driven directly by some GLOBAL wires

The IMUX wires can be driven by LOCAL wires. Some of them can also be driven by GLOBAL wires.

If an IMUX wire is not driven at all (the MUX field in the bitstream is set to NONE), it takes on a default value. The default value is 1 for IMUX.CE, 0 for all other IMUX wires.

Tile slots

siliconblue tile slots
SlotTilesBel slots
MAINPLB_L04, INT_BRAM, IOI_W_L04, IOI_E_L04, IOI_S_L04, IOI_N_L04, PLB_L08, IOI_W_L08, IOI_E_L08, IOI_S_L08, IOI_N_L08, PLB_P01, IOI_S_T04, IOI_N_T04LC0, LC1, LC2, LC3, LC4, LC5, LC6, LC7, IO0, IO1
COLBUFCOLBUF_L01, COLBUF_IO_W, COLBUF_IO_E, COLBUF_P08
GB_ROOTGB_ROOT_L04, GB_ROOT_L08GB_ROOT
BELBRAM_L04, IO_LATCH, GB_FABRIC, PLL_S_P04, BRAM_P01, PLL_S_P01, BRAM_P08, PLL_S_P08, PLL_N_P08, SPI_R04, I2C_R04, PLL_S_R04, PLL_N_R04, MAC16, SPI_T04, I2C_T04, MAC16_TRIM, SPI_T05, I3C, SPRAM, I2C_FIFO, PLL_S_T01BRAM, IO_LATCH, GB_FABRIC, PLL, MAC16, SPI, I2C, I2C_FIFO, IO0_I3C, IO1_I3C, SPRAM0, SPRAM1, FILTER0, FILTER1
IOBIOB_W_L04, IOB_E_L04, IOB_S_L04, IOB_N_L04, IOB_W_P04, IOB_E_P04, IOB_S_P04, IOB_N_P04, IOB_W_L08, IOB_E_L08, IOB_S_L08, IOB_N_L08, IOB_W_L01, IOB_E_L01, IOB_S_L01, IOB_N_L01, IOB_W_P01, IOB_E_P01, IOB_S_P01, IOB_N_P01, IOB_W_P08, IOB_E_P08, IOB_S_P08, IOB_N_P08, IOB_W_P03, IOB_E_P03, IOB_S_P03, IOB_N_P03, IOB_S_R04, IOB_N_R04, IOB_S_T04, IOB_N_T04, IOB_S_T05, IOB_N_T05, IOB_S_T01, IOB_N_T01
OSCHSOSC, LSOSC, HFOSC_T04, LFOSC_T04, HFOSC_T01, LFOSC_T01HSOSC, LSOSC, HFOSC, LFOSC
TRIMTRIM_T04, TRIM_T01
LED_DRVRGB_DRV, IR_DRV, RGBA_DRV_T05, RGBA_DRV_T01, IR500_DRVRGB_DRV, IR_DRV, RGBA_DRV, IR400_DRV, BARCODE_DRV
LED_IPLEDD_IP, LEDDA_IP_T05, LEDDA_IP_T01, IR_IPLEDD_IP, LEDDA_IP, IR_IP
LED_DRV_CURLED_DRV_CUR_T04, LED_DRV_CUR_T05, LED_DRV_CUR_T01LED_DRV_CUR
PLL_STUBPLL_STUB_S
SMCCLKSMCCLK_T04, SMCCLK_T05, SMCCLK_T01SMCCLK
WARMBOOTWARMBOOT, WARMBOOT_T01WARMBOOT

Bel slots

siliconblue bel slots
SlotTile slotTiles
LC0MAINPLB_L04, PLB_L08, PLB_P01
LC1MAINPLB_L04, PLB_L08, PLB_P01
LC2MAINPLB_L04, PLB_L08, PLB_P01
LC3MAINPLB_L04, PLB_L08, PLB_P01
LC4MAINPLB_L04, PLB_L08, PLB_P01
LC5MAINPLB_L04, PLB_L08, PLB_P01
LC6MAINPLB_L04, PLB_L08, PLB_P01
LC7MAINPLB_L04, PLB_L08, PLB_P01
IO0MAINIOI_W_L04, IOI_E_L04, IOI_S_L04, IOI_N_L04, IOI_W_L08, IOI_E_L08, IOI_S_L08, IOI_N_L08, IOI_S_T04, IOI_N_T04
IO1MAINIOI_W_L04, IOI_E_L04, IOI_S_L04, IOI_N_L04, IOI_W_L08, IOI_E_L08, IOI_S_L08, IOI_N_L08, IOI_S_T04, IOI_N_T04
BRAMBELBRAM_L04, BRAM_P01, BRAM_P08
IO_LATCHBELIO_LATCH
GB_FABRICBELGB_FABRIC
GB_ROOTGB_ROOTGB_ROOT_L04, GB_ROOT_L08
WARMBOOTWARMBOOTWARMBOOT, WARMBOOT_T01
PLLBELPLL_S_P04, PLL_S_P01, PLL_S_P08, PLL_N_P08, PLL_S_R04, PLL_N_R04, PLL_S_T01
MAC16BELMAC16, MAC16_TRIM
SPIBELSPI_R04, SPI_T04, SPI_T05
I2CBELI2C_R04, I2C_T04
I2C_FIFOBELI2C_FIFO
HSOSCOSCHSOSC
LSOSCOSCLSOSC
HFOSCOSCHFOSC_T04, HFOSC_T01
LFOSCOSCLFOSC_T04, LFOSC_T01
LEDD_IPLED_IPLEDD_IP
LEDDA_IPLED_IPLEDDA_IP_T05, LEDDA_IP_T01
IR_IPLED_IPIR_IP
IO0_I3CBELI3C
IO1_I3CBELI3C
RGB_DRVLED_DRVRGB_DRV
IR_DRVLED_DRVIR_DRV
RGBA_DRVLED_DRVRGBA_DRV_T05, RGBA_DRV_T01
IR400_DRVLED_DRVIR500_DRV
BARCODE_DRVLED_DRVIR500_DRV
LED_DRV_CURLED_DRV_CURLED_DRV_CUR_T04, LED_DRV_CUR_T05, LED_DRV_CUR_T01
SPRAM0BELSPRAM
SPRAM1BELSPRAM
FILTER0BELI3C
FILTER1BELI3C
SMCCLKSMCCLKSMCCLK_T04, SMCCLK_T05, SMCCLK_T01

Connector slots

siliconblue connector slots
SlotOppositeConnectors
WEPASS_W
EWPASS_E
SNPASS_S
NSPASS_N

Region slots

siliconblue region slots
SlotWires
GLOBALGLOBAL.0, GLOBAL.1, GLOBAL.2, GLOBAL.3, GLOBAL.4, GLOBAL.5, GLOBAL.6, GLOBAL.7
COLBUF

Wires

siliconblue wires
WireKind
GLOBAL.0REGIONAL:GLOBAL
GLOBAL.1REGIONAL:GLOBAL
GLOBAL.2REGIONAL:GLOBAL
GLOBAL.3REGIONAL:GLOBAL
GLOBAL.4REGIONAL:GLOBAL
GLOBAL.5REGIONAL:GLOBAL
GLOBAL.6REGIONAL:GLOBAL
GLOBAL.7REGIONAL:GLOBAL
GOUT.0MUX_OUT
GOUT.1MUX_OUT
GOUT.2MUX_OUT
GOUT.3MUX_OUT
QUAD.H0.0MULTI_OUT
QUAD.H0.1MULTI_BRANCH:W
QUAD.H0.2MULTI_BRANCH:W
QUAD.H0.3MULTI_BRANCH:W
QUAD.H0.4MULTI_BRANCH:W
QUAD.H1.0MULTI_OUT
QUAD.H1.1MULTI_BRANCH:W
QUAD.H1.2MULTI_BRANCH:W
QUAD.H1.3MULTI_BRANCH:W
QUAD.H1.4MULTI_BRANCH:W
QUAD.H2.0MULTI_OUT
QUAD.H2.1MULTI_BRANCH:W
QUAD.H2.2MULTI_BRANCH:W
QUAD.H2.3MULTI_BRANCH:W
QUAD.H2.4MULTI_BRANCH:W
QUAD.H3.0MULTI_OUT
QUAD.H3.1MULTI_BRANCH:W
QUAD.H3.2MULTI_BRANCH:W
QUAD.H3.3MULTI_BRANCH:W
QUAD.H3.4MULTI_BRANCH:W
QUAD.H4.0MULTI_OUT
QUAD.H4.1MULTI_BRANCH:W
QUAD.H4.2MULTI_BRANCH:W
QUAD.H4.3MULTI_BRANCH:W
QUAD.H4.4MULTI_BRANCH:W
QUAD.H5.0MULTI_OUT
QUAD.H5.1MULTI_BRANCH:W
QUAD.H5.2MULTI_BRANCH:W
QUAD.H5.3MULTI_BRANCH:W
QUAD.H5.4MULTI_BRANCH:W
QUAD.H6.0MULTI_OUT
QUAD.H6.1MULTI_BRANCH:W
QUAD.H6.2MULTI_BRANCH:W
QUAD.H6.3MULTI_BRANCH:W
QUAD.H6.4MULTI_BRANCH:W
QUAD.H7.0MULTI_OUT
QUAD.H7.1MULTI_BRANCH:W
QUAD.H7.2MULTI_BRANCH:W
QUAD.H7.3MULTI_BRANCH:W
QUAD.H7.4MULTI_BRANCH:W
QUAD.H8.0MULTI_OUT
QUAD.H8.1MULTI_BRANCH:W
QUAD.H8.2MULTI_BRANCH:W
QUAD.H8.3MULTI_BRANCH:W
QUAD.H8.4MULTI_BRANCH:W
QUAD.H9.0MULTI_OUT
QUAD.H9.1MULTI_BRANCH:W
QUAD.H9.2MULTI_BRANCH:W
QUAD.H9.3MULTI_BRANCH:W
QUAD.H9.4MULTI_BRANCH:W
QUAD.H10.0MULTI_OUT
QUAD.H10.1MULTI_BRANCH:W
QUAD.H10.2MULTI_BRANCH:W
QUAD.H10.3MULTI_BRANCH:W
QUAD.H10.4MULTI_BRANCH:W
QUAD.H11.0MULTI_OUT
QUAD.H11.1MULTI_BRANCH:W
QUAD.H11.2MULTI_BRANCH:W
QUAD.H11.3MULTI_BRANCH:W
QUAD.H11.4MULTI_BRANCH:W
QUAD.V0.0MULTI_OUT
QUAD.V0.1MULTI_BRANCH:S
QUAD.V0.1.WMULTI_BRANCH:E
QUAD.V0.2MULTI_BRANCH:S
QUAD.V0.2.WMULTI_BRANCH:E
QUAD.V0.3MULTI_BRANCH:S
QUAD.V0.3.WMULTI_BRANCH:E
QUAD.V0.4MULTI_BRANCH:S
QUAD.V0.4.WMULTI_BRANCH:E
QUAD.V1.0MULTI_OUT
QUAD.V1.1MULTI_BRANCH:S
QUAD.V1.1.WMULTI_BRANCH:E
QUAD.V1.2MULTI_BRANCH:S
QUAD.V1.2.WMULTI_BRANCH:E
QUAD.V1.3MULTI_BRANCH:S
QUAD.V1.3.WMULTI_BRANCH:E
QUAD.V1.4MULTI_BRANCH:S
QUAD.V1.4.WMULTI_BRANCH:E
QUAD.V2.0MULTI_OUT
QUAD.V2.1MULTI_BRANCH:S
QUAD.V2.1.WMULTI_BRANCH:E
QUAD.V2.2MULTI_BRANCH:S
QUAD.V2.2.WMULTI_BRANCH:E
QUAD.V2.3MULTI_BRANCH:S
QUAD.V2.3.WMULTI_BRANCH:E
QUAD.V2.4MULTI_BRANCH:S
QUAD.V2.4.WMULTI_BRANCH:E
QUAD.V3.0MULTI_OUT
QUAD.V3.1MULTI_BRANCH:S
QUAD.V3.1.WMULTI_BRANCH:E
QUAD.V3.2MULTI_BRANCH:S
QUAD.V3.2.WMULTI_BRANCH:E
QUAD.V3.3MULTI_BRANCH:S
QUAD.V3.3.WMULTI_BRANCH:E
QUAD.V3.4MULTI_BRANCH:S
QUAD.V3.4.WMULTI_BRANCH:E
QUAD.V4.0MULTI_OUT
QUAD.V4.1MULTI_BRANCH:S
QUAD.V4.1.WMULTI_BRANCH:E
QUAD.V4.2MULTI_BRANCH:S
QUAD.V4.2.WMULTI_BRANCH:E
QUAD.V4.3MULTI_BRANCH:S
QUAD.V4.3.WMULTI_BRANCH:E
QUAD.V4.4MULTI_BRANCH:S
QUAD.V4.4.WMULTI_BRANCH:E
QUAD.V5.0MULTI_OUT
QUAD.V5.1MULTI_BRANCH:S
QUAD.V5.1.WMULTI_BRANCH:E
QUAD.V5.2MULTI_BRANCH:S
QUAD.V5.2.WMULTI_BRANCH:E
QUAD.V5.3MULTI_BRANCH:S
QUAD.V5.3.WMULTI_BRANCH:E
QUAD.V5.4MULTI_BRANCH:S
QUAD.V5.4.WMULTI_BRANCH:E
QUAD.V6.0MULTI_OUT
QUAD.V6.1MULTI_BRANCH:S
QUAD.V6.1.WMULTI_BRANCH:E
QUAD.V6.2MULTI_BRANCH:S
QUAD.V6.2.WMULTI_BRANCH:E
QUAD.V6.3MULTI_BRANCH:S
QUAD.V6.3.WMULTI_BRANCH:E
QUAD.V6.4MULTI_BRANCH:S
QUAD.V6.4.WMULTI_BRANCH:E
QUAD.V7.0MULTI_OUT
QUAD.V7.1MULTI_BRANCH:S
QUAD.V7.1.WMULTI_BRANCH:E
QUAD.V7.2MULTI_BRANCH:S
QUAD.V7.2.WMULTI_BRANCH:E
QUAD.V7.3MULTI_BRANCH:S
QUAD.V7.3.WMULTI_BRANCH:E
QUAD.V7.4MULTI_BRANCH:S
QUAD.V7.4.WMULTI_BRANCH:E
QUAD.V8.0MULTI_OUT
QUAD.V8.1MULTI_BRANCH:S
QUAD.V8.1.WMULTI_BRANCH:E
QUAD.V8.2MULTI_BRANCH:S
QUAD.V8.2.WMULTI_BRANCH:E
QUAD.V8.3MULTI_BRANCH:S
QUAD.V8.3.WMULTI_BRANCH:E
QUAD.V8.4MULTI_BRANCH:S
QUAD.V8.4.WMULTI_BRANCH:E
QUAD.V9.0MULTI_OUT
QUAD.V9.1MULTI_BRANCH:S
QUAD.V9.1.WMULTI_BRANCH:E
QUAD.V9.2MULTI_BRANCH:S
QUAD.V9.2.WMULTI_BRANCH:E
QUAD.V9.3MULTI_BRANCH:S
QUAD.V9.3.WMULTI_BRANCH:E
QUAD.V9.4MULTI_BRANCH:S
QUAD.V9.4.WMULTI_BRANCH:E
QUAD.V10.0MULTI_OUT
QUAD.V10.1MULTI_BRANCH:S
QUAD.V10.1.WMULTI_BRANCH:E
QUAD.V10.2MULTI_BRANCH:S
QUAD.V10.2.WMULTI_BRANCH:E
QUAD.V10.3MULTI_BRANCH:S
QUAD.V10.3.WMULTI_BRANCH:E
QUAD.V10.4MULTI_BRANCH:S
QUAD.V10.4.WMULTI_BRANCH:E
QUAD.V11.0MULTI_OUT
QUAD.V11.1MULTI_BRANCH:S
QUAD.V11.1.WMULTI_BRANCH:E
QUAD.V11.2MULTI_BRANCH:S
QUAD.V11.2.WMULTI_BRANCH:E
QUAD.V11.3MULTI_BRANCH:S
QUAD.V11.3.WMULTI_BRANCH:E
QUAD.V11.4MULTI_BRANCH:S
QUAD.V11.4.WMULTI_BRANCH:E
LONG.H0.0MULTI_OUT
LONG.H0.1MULTI_BRANCH:W
LONG.H0.2MULTI_BRANCH:W
LONG.H0.3MULTI_BRANCH:W
LONG.H0.4MULTI_BRANCH:W
LONG.H0.5MULTI_BRANCH:W
LONG.H0.6MULTI_BRANCH:W
LONG.H0.7MULTI_BRANCH:W
LONG.H0.8MULTI_BRANCH:W
LONG.H0.9MULTI_BRANCH:W
LONG.H0.10MULTI_BRANCH:W
LONG.H0.11MULTI_BRANCH:W
LONG.H0.12MULTI_BRANCH:W
LONG.H1.0MULTI_OUT
LONG.H1.1MULTI_BRANCH:W
LONG.H1.2MULTI_BRANCH:W
LONG.H1.3MULTI_BRANCH:W
LONG.H1.4MULTI_BRANCH:W
LONG.H1.5MULTI_BRANCH:W
LONG.H1.6MULTI_BRANCH:W
LONG.H1.7MULTI_BRANCH:W
LONG.H1.8MULTI_BRANCH:W
LONG.H1.9MULTI_BRANCH:W
LONG.H1.10MULTI_BRANCH:W
LONG.H1.11MULTI_BRANCH:W
LONG.H1.12MULTI_BRANCH:W
LONG.V0.0MULTI_OUT
LONG.V0.1MULTI_BRANCH:S
LONG.V0.2MULTI_BRANCH:S
LONG.V0.3MULTI_BRANCH:S
LONG.V0.4MULTI_BRANCH:S
LONG.V0.5MULTI_BRANCH:S
LONG.V0.6MULTI_BRANCH:S
LONG.V0.7MULTI_BRANCH:S
LONG.V0.8MULTI_BRANCH:S
LONG.V0.9MULTI_BRANCH:S
LONG.V0.10MULTI_BRANCH:S
LONG.V0.11MULTI_BRANCH:S
LONG.V0.12MULTI_BRANCH:S
LONG.V1.0MULTI_OUT
LONG.V1.1MULTI_BRANCH:S
LONG.V1.2MULTI_BRANCH:S
LONG.V1.3MULTI_BRANCH:S
LONG.V1.4MULTI_BRANCH:S
LONG.V1.5MULTI_BRANCH:S
LONG.V1.6MULTI_BRANCH:S
LONG.V1.7MULTI_BRANCH:S
LONG.V1.8MULTI_BRANCH:S
LONG.V1.9MULTI_BRANCH:S
LONG.V1.10MULTI_BRANCH:S
LONG.V1.11MULTI_BRANCH:S
LONG.V1.12MULTI_BRANCH:S
LOCAL.0.0MUX_OUT
LOCAL.0.1MUX_OUT
LOCAL.0.2MUX_OUT
LOCAL.0.3MUX_OUT
LOCAL.0.4MUX_OUT
LOCAL.0.5MUX_OUT
LOCAL.0.6MUX_OUT
LOCAL.0.7MUX_OUT
LOCAL.1.0MUX_OUT
LOCAL.1.1MUX_OUT
LOCAL.1.2MUX_OUT
LOCAL.1.3MUX_OUT
LOCAL.1.4MUX_OUT
LOCAL.1.5MUX_OUT
LOCAL.1.6MUX_OUT
LOCAL.1.7MUX_OUT
LOCAL.2.0MUX_OUT
LOCAL.2.1MUX_OUT
LOCAL.2.2MUX_OUT
LOCAL.2.3MUX_OUT
LOCAL.2.4MUX_OUT
LOCAL.2.5MUX_OUT
LOCAL.2.6MUX_OUT
LOCAL.2.7MUX_OUT
LOCAL.3.0MUX_OUT
LOCAL.3.1MUX_OUT
LOCAL.3.2MUX_OUT
LOCAL.3.3MUX_OUT
LOCAL.3.4MUX_OUT
LOCAL.3.5MUX_OUT
LOCAL.3.6MUX_OUT
LOCAL.3.7MUX_OUT
IMUX.LC0.I0MUX_OUT
IMUX.LC0.I1MUX_OUT
IMUX.LC0.I2MUX_OUT
IMUX.LC0.I3MUX_OUT
IMUX.LC1.I0MUX_OUT
IMUX.LC1.I1MUX_OUT
IMUX.LC1.I2MUX_OUT
IMUX.LC1.I3MUX_OUT
IMUX.LC2.I0MUX_OUT
IMUX.LC2.I1MUX_OUT
IMUX.LC2.I2MUX_OUT
IMUX.LC2.I3MUX_OUT
IMUX.LC3.I0MUX_OUT
IMUX.LC3.I1MUX_OUT
IMUX.LC3.I2MUX_OUT
IMUX.LC3.I3MUX_OUT
IMUX.LC4.I0MUX_OUT
IMUX.LC4.I1MUX_OUT
IMUX.LC4.I2MUX_OUT
IMUX.LC4.I3MUX_OUT
IMUX.LC5.I0MUX_OUT
IMUX.LC5.I1MUX_OUT
IMUX.LC5.I2MUX_OUT
IMUX.LC5.I3MUX_OUT
IMUX.LC6.I0MUX_OUT
IMUX.LC6.I1MUX_OUT
IMUX.LC6.I2MUX_OUT
IMUX.LC6.I3MUX_OUT
IMUX.LC7.I0MUX_OUT
IMUX.LC7.I1MUX_OUT
IMUX.LC7.I2MUX_OUT
IMUX.LC7.I3MUX_OUT
IMUX.CLKMUX_OUT
IMUX.RSTMUX_OUT
IMUX.CEMUX_OUT
IMUX.IO0.DOUT0MUX_OUT
IMUX.IO0.DOUT1MUX_OUT
IMUX.IO0.OEMUX_OUT
IMUX.IO1.DOUT0MUX_OUT
IMUX.IO1.DOUT1MUX_OUT
IMUX.IO1.OEMUX_OUT
IMUX.IO.ICLKMUX_OUT
IMUX.IO.OCLKMUX_OUT
IMUX.IO.EXTRAMUX_OUT
OUT.LC0LOGIC_OUT
OUT.LC0.NBRANCH:S
OUT.LC0.SBRANCH:N
OUT.LC0.EBRANCH:W
OUT.LC0.ENBRANCH:S
OUT.LC0.ESBRANCH:N
OUT.LC0.WBRANCH:E
OUT.LC0.WNBRANCH:S
OUT.LC0.WSBRANCH:N
OUT.LC1LOGIC_OUT
OUT.LC1.NBRANCH:S
OUT.LC1.SBRANCH:N
OUT.LC1.EBRANCH:W
OUT.LC1.ENBRANCH:S
OUT.LC1.ESBRANCH:N
OUT.LC1.WBRANCH:E
OUT.LC1.WNBRANCH:S
OUT.LC1.WSBRANCH:N
OUT.LC2LOGIC_OUT
OUT.LC2.NBRANCH:S
OUT.LC2.SBRANCH:N
OUT.LC2.EBRANCH:W
OUT.LC2.ENBRANCH:S
OUT.LC2.ESBRANCH:N
OUT.LC2.WBRANCH:E
OUT.LC2.WNBRANCH:S
OUT.LC2.WSBRANCH:N
OUT.LC3LOGIC_OUT
OUT.LC3.NBRANCH:S
OUT.LC3.SBRANCH:N
OUT.LC3.EBRANCH:W
OUT.LC3.ENBRANCH:S
OUT.LC3.ESBRANCH:N
OUT.LC3.WBRANCH:E
OUT.LC3.WNBRANCH:S
OUT.LC3.WSBRANCH:N
OUT.LC4LOGIC_OUT
OUT.LC4.NBRANCH:S
OUT.LC4.SBRANCH:N
OUT.LC4.EBRANCH:W
OUT.LC4.ENBRANCH:S
OUT.LC4.ESBRANCH:N
OUT.LC4.WBRANCH:E
OUT.LC4.WNBRANCH:S
OUT.LC4.WSBRANCH:N
OUT.LC5LOGIC_OUT
OUT.LC5.NBRANCH:S
OUT.LC5.SBRANCH:N
OUT.LC5.EBRANCH:W
OUT.LC5.ENBRANCH:S
OUT.LC5.ESBRANCH:N
OUT.LC5.WBRANCH:E
OUT.LC5.WNBRANCH:S
OUT.LC5.WSBRANCH:N
OUT.LC6LOGIC_OUT
OUT.LC6.NBRANCH:S
OUT.LC6.SBRANCH:N
OUT.LC6.EBRANCH:W
OUT.LC6.ENBRANCH:S
OUT.LC6.ESBRANCH:N
OUT.LC6.WBRANCH:E
OUT.LC6.WNBRANCH:S
OUT.LC6.WSBRANCH:N
OUT.LC7LOGIC_OUT
OUT.LC7.NBRANCH:S
OUT.LC7.SBRANCH:N
OUT.LC7.EBRANCH:W
OUT.LC7.ENBRANCH:S
OUT.LC7.ESBRANCH:N
OUT.LC7.WBRANCH:E
OUT.LC7.WNBRANCH:S
OUT.LC7.WSBRANCH:N

Connectors — W

siliconblue wires
Wire PASS_W
QUAD.H0.1 → QUAD.H0.0
QUAD.H0.2 → QUAD.H0.1
QUAD.H0.3 → QUAD.H0.2
QUAD.H0.4 → QUAD.H0.3
QUAD.H1.1 → QUAD.H1.0
QUAD.H1.2 → QUAD.H1.1
QUAD.H1.3 → QUAD.H1.2
QUAD.H1.4 → QUAD.H1.3
QUAD.H2.1 → QUAD.H2.0
QUAD.H2.2 → QUAD.H2.1
QUAD.H2.3 → QUAD.H2.2
QUAD.H2.4 → QUAD.H2.3
QUAD.H3.1 → QUAD.H3.0
QUAD.H3.2 → QUAD.H3.1
QUAD.H3.3 → QUAD.H3.2
QUAD.H3.4 → QUAD.H3.3
QUAD.H4.1 → QUAD.H4.0
QUAD.H4.2 → QUAD.H4.1
QUAD.H4.3 → QUAD.H4.2
QUAD.H4.4 → QUAD.H4.3
QUAD.H5.1 → QUAD.H5.0
QUAD.H5.2 → QUAD.H5.1
QUAD.H5.3 → QUAD.H5.2
QUAD.H5.4 → QUAD.H5.3
QUAD.H6.1 → QUAD.H6.0
QUAD.H6.2 → QUAD.H6.1
QUAD.H6.3 → QUAD.H6.2
QUAD.H6.4 → QUAD.H6.3
QUAD.H7.1 → QUAD.H7.0
QUAD.H7.2 → QUAD.H7.1
QUAD.H7.3 → QUAD.H7.2
QUAD.H7.4 → QUAD.H7.3
QUAD.H8.1 → QUAD.H8.0
QUAD.H8.2 → QUAD.H8.1
QUAD.H8.3 → QUAD.H8.2
QUAD.H8.4 → QUAD.H8.3
QUAD.H9.1 → QUAD.H9.0
QUAD.H9.2 → QUAD.H9.1
QUAD.H9.3 → QUAD.H9.2
QUAD.H9.4 → QUAD.H9.3
QUAD.H10.1 → QUAD.H10.0
QUAD.H10.2 → QUAD.H10.1
QUAD.H10.3 → QUAD.H10.2
QUAD.H10.4 → QUAD.H10.3
QUAD.H11.1 → QUAD.H11.0
QUAD.H11.2 → QUAD.H11.1
QUAD.H11.3 → QUAD.H11.2
QUAD.H11.4 → QUAD.H11.3
LONG.H0.1 → LONG.H0.0
LONG.H0.2 → LONG.H0.1
LONG.H0.3 → LONG.H0.2
LONG.H0.4 → LONG.H0.3
LONG.H0.5 → LONG.H0.4
LONG.H0.6 → LONG.H0.5
LONG.H0.7 → LONG.H0.6
LONG.H0.8 → LONG.H0.7
LONG.H0.9 → LONG.H0.8
LONG.H0.10 → LONG.H0.9
LONG.H0.11 → LONG.H0.10
LONG.H0.12 → LONG.H0.11
LONG.H1.1 → LONG.H1.0
LONG.H1.2 → LONG.H1.1
LONG.H1.3 → LONG.H1.2
LONG.H1.4 → LONG.H1.3
LONG.H1.5 → LONG.H1.4
LONG.H1.6 → LONG.H1.5
LONG.H1.7 → LONG.H1.6
LONG.H1.8 → LONG.H1.7
LONG.H1.9 → LONG.H1.8
LONG.H1.10 → LONG.H1.9
LONG.H1.11 → LONG.H1.10
LONG.H1.12 → LONG.H1.11
OUT.LC0.E → OUT.LC0
OUT.LC1.E → OUT.LC1
OUT.LC2.E → OUT.LC2
OUT.LC3.E → OUT.LC3
OUT.LC4.E → OUT.LC4
OUT.LC5.E → OUT.LC5
OUT.LC6.E → OUT.LC6
OUT.LC7.E → OUT.LC7

Connectors — E

siliconblue wires
Wire PASS_E
QUAD.V0.1.W → QUAD.V0.1
QUAD.V0.2.W → QUAD.V0.2
QUAD.V0.3.W → QUAD.V0.3
QUAD.V0.4.W → QUAD.V0.4
QUAD.V1.1.W → QUAD.V1.1
QUAD.V1.2.W → QUAD.V1.2
QUAD.V1.3.W → QUAD.V1.3
QUAD.V1.4.W → QUAD.V1.4
QUAD.V2.1.W → QUAD.V2.1
QUAD.V2.2.W → QUAD.V2.2
QUAD.V2.3.W → QUAD.V2.3
QUAD.V2.4.W → QUAD.V2.4
QUAD.V3.1.W → QUAD.V3.1
QUAD.V3.2.W → QUAD.V3.2
QUAD.V3.3.W → QUAD.V3.3
QUAD.V3.4.W → QUAD.V3.4
QUAD.V4.1.W → QUAD.V4.1
QUAD.V4.2.W → QUAD.V4.2
QUAD.V4.3.W → QUAD.V4.3
QUAD.V4.4.W → QUAD.V4.4
QUAD.V5.1.W → QUAD.V5.1
QUAD.V5.2.W → QUAD.V5.2
QUAD.V5.3.W → QUAD.V5.3
QUAD.V5.4.W → QUAD.V5.4
QUAD.V6.1.W → QUAD.V6.1
QUAD.V6.2.W → QUAD.V6.2
QUAD.V6.3.W → QUAD.V6.3
QUAD.V6.4.W → QUAD.V6.4
QUAD.V7.1.W → QUAD.V7.1
QUAD.V7.2.W → QUAD.V7.2
QUAD.V7.3.W → QUAD.V7.3
QUAD.V7.4.W → QUAD.V7.4
QUAD.V8.1.W → QUAD.V8.1
QUAD.V8.2.W → QUAD.V8.2
QUAD.V8.3.W → QUAD.V8.3
QUAD.V8.4.W → QUAD.V8.4
QUAD.V9.1.W → QUAD.V9.1
QUAD.V9.2.W → QUAD.V9.2
QUAD.V9.3.W → QUAD.V9.3
QUAD.V9.4.W → QUAD.V9.4
QUAD.V10.1.W → QUAD.V10.1
QUAD.V10.2.W → QUAD.V10.2
QUAD.V10.3.W → QUAD.V10.3
QUAD.V10.4.W → QUAD.V10.4
QUAD.V11.1.W → QUAD.V11.1
QUAD.V11.2.W → QUAD.V11.2
QUAD.V11.3.W → QUAD.V11.3
QUAD.V11.4.W → QUAD.V11.4
OUT.LC0.W → OUT.LC0
OUT.LC1.W → OUT.LC1
OUT.LC2.W → OUT.LC2
OUT.LC3.W → OUT.LC3
OUT.LC4.W → OUT.LC4
OUT.LC5.W → OUT.LC5
OUT.LC6.W → OUT.LC6
OUT.LC7.W → OUT.LC7

Connectors — S

siliconblue wires
Wire PASS_S
QUAD.V0.1 → QUAD.V0.0
QUAD.V0.2 → QUAD.V0.1
QUAD.V0.3 → QUAD.V0.2
QUAD.V0.4 → QUAD.V0.3
QUAD.V1.1 → QUAD.V1.0
QUAD.V1.2 → QUAD.V1.1
QUAD.V1.3 → QUAD.V1.2
QUAD.V1.4 → QUAD.V1.3
QUAD.V2.1 → QUAD.V2.0
QUAD.V2.2 → QUAD.V2.1
QUAD.V2.3 → QUAD.V2.2
QUAD.V2.4 → QUAD.V2.3
QUAD.V3.1 → QUAD.V3.0
QUAD.V3.2 → QUAD.V3.1
QUAD.V3.3 → QUAD.V3.2
QUAD.V3.4 → QUAD.V3.3
QUAD.V4.1 → QUAD.V4.0
QUAD.V4.2 → QUAD.V4.1
QUAD.V4.3 → QUAD.V4.2
QUAD.V4.4 → QUAD.V4.3
QUAD.V5.1 → QUAD.V5.0
QUAD.V5.2 → QUAD.V5.1
QUAD.V5.3 → QUAD.V5.2
QUAD.V5.4 → QUAD.V5.3
QUAD.V6.1 → QUAD.V6.0
QUAD.V6.2 → QUAD.V6.1
QUAD.V6.3 → QUAD.V6.2
QUAD.V6.4 → QUAD.V6.3
QUAD.V7.1 → QUAD.V7.0
QUAD.V7.2 → QUAD.V7.1
QUAD.V7.3 → QUAD.V7.2
QUAD.V7.4 → QUAD.V7.3
QUAD.V8.1 → QUAD.V8.0
QUAD.V8.2 → QUAD.V8.1
QUAD.V8.3 → QUAD.V8.2
QUAD.V8.4 → QUAD.V8.3
QUAD.V9.1 → QUAD.V9.0
QUAD.V9.2 → QUAD.V9.1
QUAD.V9.3 → QUAD.V9.2
QUAD.V9.4 → QUAD.V9.3
QUAD.V10.1 → QUAD.V10.0
QUAD.V10.2 → QUAD.V10.1
QUAD.V10.3 → QUAD.V10.2
QUAD.V10.4 → QUAD.V10.3
QUAD.V11.1 → QUAD.V11.0
QUAD.V11.2 → QUAD.V11.1
QUAD.V11.3 → QUAD.V11.2
QUAD.V11.4 → QUAD.V11.3
LONG.V0.1 → LONG.V0.0
LONG.V0.2 → LONG.V0.1
LONG.V0.3 → LONG.V0.2
LONG.V0.4 → LONG.V0.3
LONG.V0.5 → LONG.V0.4
LONG.V0.6 → LONG.V0.5
LONG.V0.7 → LONG.V0.6
LONG.V0.8 → LONG.V0.7
LONG.V0.9 → LONG.V0.8
LONG.V0.10 → LONG.V0.9
LONG.V0.11 → LONG.V0.10
LONG.V0.12 → LONG.V0.11
LONG.V1.1 → LONG.V1.0
LONG.V1.2 → LONG.V1.1
LONG.V1.3 → LONG.V1.2
LONG.V1.4 → LONG.V1.3
LONG.V1.5 → LONG.V1.4
LONG.V1.6 → LONG.V1.5
LONG.V1.7 → LONG.V1.6
LONG.V1.8 → LONG.V1.7
LONG.V1.9 → LONG.V1.8
LONG.V1.10 → LONG.V1.9
LONG.V1.11 → LONG.V1.10
LONG.V1.12 → LONG.V1.11
OUT.LC0.N → OUT.LC0
OUT.LC0.EN → OUT.LC0.E
OUT.LC0.WN → OUT.LC0.W
OUT.LC1.N → OUT.LC1
OUT.LC1.EN → OUT.LC1.E
OUT.LC1.WN → OUT.LC1.W
OUT.LC2.N → OUT.LC2
OUT.LC2.EN → OUT.LC2.E
OUT.LC2.WN → OUT.LC2.W
OUT.LC3.N → OUT.LC3
OUT.LC3.EN → OUT.LC3.E
OUT.LC3.WN → OUT.LC3.W
OUT.LC4.N → OUT.LC4
OUT.LC4.EN → OUT.LC4.E
OUT.LC4.WN → OUT.LC4.W
OUT.LC5.N → OUT.LC5
OUT.LC5.EN → OUT.LC5.E
OUT.LC5.WN → OUT.LC5.W
OUT.LC6.N → OUT.LC6
OUT.LC6.EN → OUT.LC6.E
OUT.LC6.WN → OUT.LC6.W
OUT.LC7.N → OUT.LC7
OUT.LC7.EN → OUT.LC7.E
OUT.LC7.WN → OUT.LC7.W

Connectors — N

siliconblue wires
Wire PASS_N
OUT.LC0.S → OUT.LC0
OUT.LC0.ES → OUT.LC0.E
OUT.LC0.WS → OUT.LC0.W
OUT.LC1.S → OUT.LC1
OUT.LC1.ES → OUT.LC1.E
OUT.LC1.WS → OUT.LC1.W
OUT.LC2.S → OUT.LC2
OUT.LC2.ES → OUT.LC2.E
OUT.LC2.WS → OUT.LC2.W
OUT.LC3.S → OUT.LC3
OUT.LC3.ES → OUT.LC3.E
OUT.LC3.WS → OUT.LC3.W
OUT.LC4.S → OUT.LC4
OUT.LC4.ES → OUT.LC4.E
OUT.LC4.WS → OUT.LC4.W
OUT.LC5.S → OUT.LC5
OUT.LC5.ES → OUT.LC5.E
OUT.LC5.WS → OUT.LC5.W
OUT.LC6.S → OUT.LC6
OUT.LC6.ES → OUT.LC6.E
OUT.LC6.WS → OUT.LC6.W
OUT.LC7.S → OUT.LC7
OUT.LC7.ES → OUT.LC7.E
OUT.LC7.WS → OUT.LC7.W