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Primary global buffers

TODO: document

Bitstream — bottom tiles

The CLKB.* tiles use two bitstream tiles:

  • tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the bottom interconnect row
  • tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the low special area (used for bottom IOB tiles and clock rows in normal columns)

On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH.CLKB.S3A tile.

CLKB.S3

This tile is used on Spartan 3.

Tile CLKB.S3

Cells: 1 IRIs: 0

Muxes

spartan3 CLKB.S3 muxes
DestinationSources
OMUX10.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX11.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX12.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX15.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
CLK.IMUX.SEL0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.SEL1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.SEL2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.SEL3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1
CLK.IMUX.CLK0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.CLK1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.CLK2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.CLK3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1

Bel BUFGMUX0

spartan3 CLKB.S3 bel BUFGMUX0
PinDirectionWires
CLKinputCLK.IMUX.CLK0
OoutputCLK.OUT.0
SinputCLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKB.S3 bel BUFGMUX1
PinDirectionWires
CLKinputCLK.IMUX.CLK1
OoutputCLK.OUT.1
SinputCLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKB.S3 bel BUFGMUX2
PinDirectionWires
CLKinputCLK.IMUX.CLK2
OoutputCLK.OUT.2
SinputCLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKB.S3 bel BUFGMUX3
PinDirectionWires
CLKinputCLK.IMUX.CLK3
OoutputCLK.OUT.3
SinputCLK.IMUX.SEL3

Bel GLOBALSIG_S

spartan3 CLKB.S3 bel GLOBALSIG_S
PinDirectionWires

Bel wires

spartan3 CLKB.S3 bel wires
WirePins
CLK.IMUX.SEL0BUFGMUX0.S
CLK.IMUX.SEL1BUFGMUX1.S
CLK.IMUX.SEL2BUFGMUX2.S
CLK.IMUX.SEL3BUFGMUX3.S
CLK.IMUX.CLK0BUFGMUX0.CLK
CLK.IMUX.CLK1BUFGMUX1.CLK
CLK.IMUX.CLK2BUFGMUX2.CLK
CLK.IMUX.CLK3BUFGMUX3.CLK
CLK.OUT.0BUFGMUX0.O
CLK.OUT.1BUFGMUX1.O
CLK.OUT.2BUFGMUX2.O
CLK.OUT.3BUFGMUX3.O

Bitstream

spartan3 CLKB.S3 bittile 0
BitFrame
0
62 BUFGMUX0:DISABLE_ATTR[0]
61 ~INT:INV.0.CLK.IMUX.SEL3
60 INT:MUX.CLK.IMUX.SEL3[2]
59 INT:MUX.CLK.IMUX.SEL3[3]
58 INT:MUX.CLK.IMUX.SEL3[1]
57 INT:MUX.CLK.IMUX.CLK3[1]
56 INT:MUX.CLK.IMUX.CLK3[0]
55 INT:MUX.CLK.IMUX.SEL3[0]
54 INT:MUX.CLK.IMUX.CLK3[3]
53 INT:MUX.CLK.IMUX.CLK3[2]
52 BUFGMUX3:DISABLE_ATTR[0]
51 BUFGMUX3:MUX.CLK[1]
50 BUFGMUX3:MUX.CLK[2]
49 BUFGMUX3:MUX.CLK[3]
48 BUFGMUX3:MUX.CLK[0]
47 INT:MUX.OMUX15.N[2]
46 INT:MUX.OMUX15.N[1]
45 INT:MUX.OMUX12.N[1]
44 INT:MUX.OMUX12.N[2]
43 INT:MUX.OMUX15.N[0]
42 INT:MUX.OMUX12.N[0]
41 ~INT:INV.0.CLK.IMUX.SEL2
40 INT:MUX.CLK.IMUX.SEL2[2]
39 INT:MUX.CLK.IMUX.SEL2[3]
38 INT:MUX.CLK.IMUX.SEL2[1]
37 INT:MUX.CLK.IMUX.CLK2[1]
36 INT:MUX.CLK.IMUX.CLK2[0]
35 INT:MUX.CLK.IMUX.SEL2[0]
34 INT:MUX.CLK.IMUX.CLK2[3]
33 INT:MUX.CLK.IMUX.CLK2[2]
32 BUFGMUX2:DISABLE_ATTR[0]
31 BUFGMUX2:MUX.CLK[1]
30 BUFGMUX2:MUX.CLK[2]
29 BUFGMUX2:MUX.CLK[3]
28 BUFGMUX2:MUX.CLK[0]
27 ~INT:INV.0.CLK.IMUX.SEL1
26 INT:MUX.CLK.IMUX.SEL1[2]
25 INT:MUX.CLK.IMUX.SEL1[3]
24 INT:MUX.CLK.IMUX.SEL1[1]
23 INT:MUX.CLK.IMUX.CLK1[1]
22 INT:MUX.CLK.IMUX.CLK1[0]
21 INT:MUX.CLK.IMUX.SEL1[0]
20 INT:MUX.CLK.IMUX.CLK1[3]
19 INT:MUX.CLK.IMUX.CLK1[2]
18 BUFGMUX1:DISABLE_ATTR[0]
17 BUFGMUX1:MUX.CLK[1]
16 BUFGMUX1:MUX.CLK[2]
15 BUFGMUX1:MUX.CLK[3]
14 BUFGMUX1:MUX.CLK[0]
13 BUFGMUX0:MUX.CLK[1]
12 BUFGMUX0:MUX.CLK[2]
11 BUFGMUX0:MUX.CLK[3]
10 BUFGMUX0:MUX.CLK[0]
9 INT:MUX.CLK.IMUX.CLK0[3]
8 INT:MUX.CLK.IMUX.CLK0[2]
7 INT:MUX.CLK.IMUX.SEL0[1]
6 INT:MUX.CLK.IMUX.CLK0[1]
5 INT:MUX.CLK.IMUX.CLK0[0]
4 INT:MUX.CLK.IMUX.SEL0[0]
3 INT:MUX.CLK.IMUX.SEL0[2]
2 INT:MUX.CLK.IMUX.SEL0[3]
1 ~INT:INV.0.CLK.IMUX.SEL0
0 INT:MUX.OMUX10.N[0]
spartan3 CLKB.S3 bittile 1
BitFrame
0
11 INT:MUX.OMUX11.N[2]
10 INT:MUX.OMUX11.N[0]
9 INT:MUX.OMUX10.N[1]
8 INT:MUX.OMUX10.N[2]
7 INT:MUX.OMUX11.N[1]
6 -
5 -
4 -
3 -
2 -
1 -
0 -
BUFGMUX0:DISABLE_ATTR 0.0.62
BUFGMUX1:DISABLE_ATTR 0.0.18
BUFGMUX2:DISABLE_ATTR 0.0.32
BUFGMUX3:DISABLE_ATTR 0.0.52
LOW 0
HIGH 1
BUFGMUX0:MUX.CLK 0.0.11 0.0.12 0.0.13 0.0.10
BUFGMUX1:MUX.CLK 0.0.15 0.0.16 0.0.17 0.0.14
BUFGMUX2:MUX.CLK 0.0.29 0.0.30 0.0.31 0.0.28
BUFGMUX3:MUX.CLK 0.0.49 0.0.50 0.0.51 0.0.48
INT 0 0 0 1
CKI 0 0 1 0
DCM_OUT_L 0 1 0 0
DCM_OUT_R 1 0 0 0
INT:INV.0.CLK.IMUX.SEL0 0.0.1
INT:INV.0.CLK.IMUX.SEL1 0.0.27
INT:INV.0.CLK.IMUX.SEL2 0.0.41
INT:INV.0.CLK.IMUX.SEL3 0.0.61
inverted ~[0]
INT:MUX.CLK.IMUX.CLK0 0.0.9 0.0.8 0.0.6 0.0.5
INT:MUX.CLK.IMUX.SEL0 0.0.2 0.0.3 0.0.7 0.0.4
PULLUP 0 0 0 0
DBL.W0.2 0 0 0 1
DBL.W1.2 0 0 1 0
DBL.W0.1 0 1 0 1
DBL.W1.1 0 1 1 0
DBL.E0.1 1 0 0 1
DBL.E1.1 1 0 1 0
DBL.E0.0 1 1 0 1
DBL.E1.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK1 0.0.20 0.0.19 0.0.23 0.0.22
INT:MUX.CLK.IMUX.SEL1 0.0.25 0.0.26 0.0.24 0.0.21
PULLUP 0 0 0 0
DBL.W2.2 0 0 0 1
DBL.W3.2 0 0 1 0
DBL.W2.1 0 1 0 1
DBL.W3.1 0 1 1 0
DBL.E2.1 1 0 0 1
DBL.E3.1 1 0 1 0
DBL.E2.0 1 1 0 1
DBL.E3.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK2 0.0.34 0.0.33 0.0.37 0.0.36
INT:MUX.CLK.IMUX.SEL2 0.0.39 0.0.40 0.0.38 0.0.35
PULLUP 0 0 0 0
DBL.W4.2 0 0 0 1
DBL.W5.2 0 0 1 0
DBL.W4.1 0 1 0 1
DBL.W5.1 0 1 1 0
DBL.E4.1 1 0 0 1
DBL.E5.1 1 0 1 0
DBL.E4.0 1 1 0 1
DBL.E5.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK3 0.0.54 0.0.53 0.0.57 0.0.56
INT:MUX.CLK.IMUX.SEL3 0.0.59 0.0.60 0.0.58 0.0.55
PULLUP 0 0 0 0
DBL.W6.2 0 0 0 1
DBL.W7.2 0 0 1 0
DBL.W6.1 0 1 0 1
DBL.W7.1 0 1 1 0
DBL.E6.1 1 0 0 1
DBL.E7.1 1 0 1 0
DBL.E6.0 1 1 0 1
DBL.E7.0 1 1 1 0
INT:MUX.OMUX10.N 1.0.8 1.0.9 0.0.0
INT:MUX.OMUX11.N 1.0.11 1.0.7 1.0.10
INT:MUX.OMUX12.N 0.0.44 0.0.45 0.0.42
INT:MUX.OMUX15.N 0.0.47 0.0.46 0.0.43
NONE 0 0 0
CLK.OUT.2 0 0 1
CLK.OUT.3 0 1 0
CLK.OUT.0 1 0 1
CLK.OUT.1 1 1 0

CLKB.S3E

This tile is used on Spartan 3E.

Tile CLKB.S3E

Cells: 1 IRIs: 0

Muxes

spartan3 CLKB.S3E muxes
DestinationSources
OMUX10.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX11.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX12.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX15.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
CLK.IMUX.SEL0PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1
CLK.IMUX.SEL1PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.SEL2PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.SEL3PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.CLK0PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1
CLK.IMUX.CLK1PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.CLK2PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.CLK3PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1

Bel BUFGMUX0

spartan3 CLKB.S3E bel BUFGMUX0
PinDirectionWires
CLKinputCLK.IMUX.CLK0
OoutputCLK.OUT.0
SinputCLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKB.S3E bel BUFGMUX1
PinDirectionWires
CLKinputCLK.IMUX.CLK1
OoutputCLK.OUT.1
SinputCLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKB.S3E bel BUFGMUX2
PinDirectionWires
CLKinputCLK.IMUX.CLK2
OoutputCLK.OUT.2
SinputCLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKB.S3E bel BUFGMUX3
PinDirectionWires
CLKinputCLK.IMUX.CLK3
OoutputCLK.OUT.3
SinputCLK.IMUX.SEL3

Bel GLOBALSIG_S

spartan3 CLKB.S3E bel GLOBALSIG_S
PinDirectionWires

Bel wires

spartan3 CLKB.S3E bel wires
WirePins
CLK.IMUX.SEL0BUFGMUX0.S
CLK.IMUX.SEL1BUFGMUX1.S
CLK.IMUX.SEL2BUFGMUX2.S
CLK.IMUX.SEL3BUFGMUX3.S
CLK.IMUX.CLK0BUFGMUX0.CLK
CLK.IMUX.CLK1BUFGMUX1.CLK
CLK.IMUX.CLK2BUFGMUX2.CLK
CLK.IMUX.CLK3BUFGMUX3.CLK
CLK.OUT.0BUFGMUX0.O
CLK.OUT.1BUFGMUX1.O
CLK.OUT.2BUFGMUX2.O
CLK.OUT.3BUFGMUX3.O

Bitstream

spartan3 CLKB.S3E bittile 0
BitFrame
0
62 BUFGMUX3:DISABLE_ATTR[0]
61 ~INT:INV.0.CLK.IMUX.SEL0
60 INT:MUX.CLK.IMUX.SEL0[3]
59 INT:MUX.CLK.IMUX.SEL0[2]
58 INT:MUX.CLK.IMUX.SEL0[0]
57 INT:MUX.CLK.IMUX.CLK0[0]
56 INT:MUX.CLK.IMUX.CLK0[1]
55 INT:MUX.CLK.IMUX.SEL0[1]
54 INT:MUX.CLK.IMUX.CLK0[2]
53 INT:MUX.CLK.IMUX.CLK0[3]
52 BUFGMUX0:DISABLE_ATTR[0]
51 BUFGMUX0:MUX.CLK[2]
50 BUFGMUX0:MUX.CLK[1]
49 BUFGMUX0:MUX.CLK[3]
48 BUFGMUX0:MUX.CLK[4]
47 BUFGMUX0:MUX.CLK[0]
46 INT:MUX.OMUX15.N[2]
45 INT:MUX.OMUX15.N[1]
44 INT:MUX.OMUX12.N[1]
43 INT:MUX.OMUX12.N[2]
42 INT:MUX.OMUX15.N[0]
41 INT:MUX.OMUX12.N[0]
40 ~INT:INV.0.CLK.IMUX.SEL1
39 INT:MUX.CLK.IMUX.SEL1[3]
38 INT:MUX.CLK.IMUX.SEL1[2]
37 INT:MUX.CLK.IMUX.SEL1[0]
36 INT:MUX.CLK.IMUX.CLK1[0]
35 INT:MUX.CLK.IMUX.CLK1[1]
34 INT:MUX.CLK.IMUX.SEL1[1]
33 INT:MUX.CLK.IMUX.CLK1[2]
32 INT:MUX.CLK.IMUX.CLK1[3]
31 BUFGMUX1:DISABLE_ATTR[0]
30 BUFGMUX1:MUX.CLK[2]
29 BUFGMUX1:MUX.CLK[1]
28 BUFGMUX1:MUX.CLK[3]
27 BUFGMUX1:MUX.CLK[4]
26 BUFGMUX1:MUX.CLK[0]
25 BUFGMUX2:DISABLE_ATTR[0]
24 ~INT:INV.0.CLK.IMUX.SEL2
23 INT:MUX.CLK.IMUX.SEL2[3]
22 INT:MUX.CLK.IMUX.SEL2[2]
21 INT:MUX.CLK.IMUX.SEL2[0]
20 INT:MUX.CLK.IMUX.CLK2[0]
19 INT:MUX.CLK.IMUX.CLK2[1]
18 INT:MUX.CLK.IMUX.SEL2[1]
17 INT:MUX.CLK.IMUX.CLK2[2]
16 INT:MUX.CLK.IMUX.CLK2[3]
15 BUFGMUX2:MUX.CLK[2]
14 BUFGMUX2:MUX.CLK[1]
13 BUFGMUX2:MUX.CLK[3]
12 BUFGMUX2:MUX.CLK[4]
11 BUFGMUX2:MUX.CLK[0]
10 BUFGMUX3:MUX.CLK[2]
9 BUFGMUX3:MUX.CLK[1]
8 BUFGMUX3:MUX.CLK[3]
7 BUFGMUX3:MUX.CLK[4]
6 BUFGMUX3:MUX.CLK[0]
5 INT:MUX.CLK.IMUX.CLK3[3]
4 INT:MUX.CLK.IMUX.CLK3[2]
3 INT:MUX.CLK.IMUX.SEL3[0]
2 INT:MUX.CLK.IMUX.CLK3[0]
1 INT:MUX.CLK.IMUX.CLK3[1]
0 INT:MUX.CLK.IMUX.SEL3[1]
spartan3 CLKB.S3E bittile 1
BitFrame
0
15 INT:MUX.OMUX11.N[0]
14 INT:MUX.OMUX11.N[1]
13 INT:MUX.OMUX10.N[1]
12 INT:MUX.OMUX10.N[2]
11 INT:MUX.CLK.IMUX.SEL3[2]
10 INT:MUX.CLK.IMUX.SEL3[3]
9 ~INT:INV.0.CLK.IMUX.SEL3
8 INT:MUX.OMUX10.N[0]
7 INT:MUX.OMUX11.N[2]
6 -
5 -
4 -
3 -
2 -
1 -
0 -
BUFGMUX0:DISABLE_ATTR 0.0.52
BUFGMUX1:DISABLE_ATTR 0.0.31
BUFGMUX2:DISABLE_ATTR 0.0.25
BUFGMUX3:DISABLE_ATTR 0.0.62
LOW 0
HIGH 1
BUFGMUX0:MUX.CLK 0.0.48 0.0.49 0.0.51 0.0.50 0.0.47
BUFGMUX1:MUX.CLK 0.0.27 0.0.28 0.0.30 0.0.29 0.0.26
BUFGMUX2:MUX.CLK 0.0.12 0.0.13 0.0.15 0.0.14 0.0.11
BUFGMUX3:MUX.CLK 0.0.7 0.0.8 0.0.10 0.0.9 0.0.6
INT 0 0 0 0 1
CKIL 0 0 0 1 0
CKIR 0 0 1 0 0
DCM_OUT_L 0 1 0 0 0
DCM_OUT_R 1 0 0 0 0
INT:INV.0.CLK.IMUX.SEL0 0.0.61
INT:INV.0.CLK.IMUX.SEL1 0.0.40
INT:INV.0.CLK.IMUX.SEL2 0.0.24
INT:INV.0.CLK.IMUX.SEL3 1.0.9
inverted ~[0]
INT:MUX.CLK.IMUX.CLK0 0.0.53 0.0.54 0.0.56 0.0.57
INT:MUX.CLK.IMUX.SEL0 0.0.60 0.0.59 0.0.55 0.0.58
PULLUP 0 0 0 0
DBL.W6.2 0 0 0 1
DBL.W7.2 0 0 1 0
DBL.W6.1 0 1 0 1
DBL.W7.1 0 1 1 0
DBL.E6.1 1 0 0 1
DBL.E7.1 1 0 1 0
DBL.E6.0 1 1 0 1
DBL.E7.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK1 0.0.32 0.0.33 0.0.35 0.0.36
INT:MUX.CLK.IMUX.SEL1 0.0.39 0.0.38 0.0.34 0.0.37
PULLUP 0 0 0 0
DBL.W4.2 0 0 0 1
DBL.W5.2 0 0 1 0
DBL.W4.1 0 1 0 1
DBL.W5.1 0 1 1 0
DBL.E4.1 1 0 0 1
DBL.E5.1 1 0 1 0
DBL.E4.0 1 1 0 1
DBL.E5.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK2 0.0.16 0.0.17 0.0.19 0.0.20
INT:MUX.CLK.IMUX.SEL2 0.0.23 0.0.22 0.0.18 0.0.21
PULLUP 0 0 0 0
DBL.W2.2 0 0 0 1
DBL.W3.2 0 0 1 0
DBL.W2.1 0 1 0 1
DBL.W3.1 0 1 1 0
DBL.E2.1 1 0 0 1
DBL.E3.1 1 0 1 0
DBL.E2.0 1 1 0 1
DBL.E3.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK3 0.0.5 0.0.4 0.0.1 0.0.2
INT:MUX.CLK.IMUX.SEL3 1.0.10 1.0.11 0.0.0 0.0.3
PULLUP 0 0 0 0
DBL.W0.2 0 0 0 1
DBL.W1.2 0 0 1 0
DBL.W0.1 0 1 0 1
DBL.W1.1 0 1 1 0
DBL.E0.1 1 0 0 1
DBL.E1.1 1 0 1 0
DBL.E0.0 1 1 0 1
DBL.E1.0 1 1 1 0
INT:MUX.OMUX10.N 1.0.12 1.0.13 1.0.8
INT:MUX.OMUX11.N 1.0.7 1.0.14 1.0.15
INT:MUX.OMUX12.N 0.0.43 0.0.44 0.0.41
INT:MUX.OMUX15.N 0.0.46 0.0.45 0.0.42
NONE 0 0 0
CLK.OUT.2 0 0 1
CLK.OUT.3 0 1 0
CLK.OUT.0 1 0 1
CLK.OUT.1 1 1 0

CLKB.S3A

This tile is used on Spartan 3A and 3A DSP.

Tile CLKB.S3A

Cells: 1 IRIs: 0

Muxes

spartan3 CLKB.S3A muxes
DestinationSources
OMUX10.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX11.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX12.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX15.NCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
CLK.IMUX.SEL0PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1
CLK.IMUX.SEL1PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.SEL2PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.SEL3PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.CLK0PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1
CLK.IMUX.CLK1PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.CLK2PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.CLK3PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1

Bel BUFGMUX0

spartan3 CLKB.S3A bel BUFGMUX0
PinDirectionWires
CLKinputCLK.IMUX.CLK0
OoutputCLK.OUT.0
SinputCLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKB.S3A bel BUFGMUX1
PinDirectionWires
CLKinputCLK.IMUX.CLK1
OoutputCLK.OUT.1
SinputCLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKB.S3A bel BUFGMUX2
PinDirectionWires
CLKinputCLK.IMUX.CLK2
OoutputCLK.OUT.2
SinputCLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKB.S3A bel BUFGMUX3
PinDirectionWires
CLKinputCLK.IMUX.CLK3
OoutputCLK.OUT.3
SinputCLK.IMUX.SEL3

Bel GLOBALSIG_S

spartan3 CLKB.S3A bel GLOBALSIG_S
PinDirectionWires

Bel wires

spartan3 CLKB.S3A bel wires
WirePins
CLK.IMUX.SEL0BUFGMUX0.S
CLK.IMUX.SEL1BUFGMUX1.S
CLK.IMUX.SEL2BUFGMUX2.S
CLK.IMUX.SEL3BUFGMUX3.S
CLK.IMUX.CLK0BUFGMUX0.CLK
CLK.IMUX.CLK1BUFGMUX1.CLK
CLK.IMUX.CLK2BUFGMUX2.CLK
CLK.IMUX.CLK3BUFGMUX3.CLK
CLK.OUT.0BUFGMUX0.O
CLK.OUT.1BUFGMUX1.O
CLK.OUT.2BUFGMUX2.O
CLK.OUT.3BUFGMUX3.O

Bitstream

spartan3 CLKB.S3A bittile 0
BitFrame
0
62 BUFGMUX3:DISABLE_ATTR[0]
61 ~INT:INV.0.CLK.IMUX.SEL0
60 INT:MUX.CLK.IMUX.SEL0[3]
59 INT:MUX.CLK.IMUX.SEL0[2]
58 INT:MUX.CLK.IMUX.SEL0[0]
57 INT:MUX.CLK.IMUX.CLK0[0]
56 INT:MUX.CLK.IMUX.CLK0[1]
55 INT:MUX.CLK.IMUX.SEL0[1]
54 INT:MUX.CLK.IMUX.CLK0[2]
53 INT:MUX.CLK.IMUX.CLK0[3]
52 BUFGMUX0:DISABLE_ATTR[0]
51 BUFGMUX0:MUX.CLK[2]
50 BUFGMUX0:MUX.CLK[1]
49 BUFGMUX0:MUX.CLK[3]
48 BUFGMUX0:MUX.CLK[4]
47 BUFGMUX0:MUX.CLK[0]
46 INT:MUX.OMUX15.N[2]
45 INT:MUX.OMUX15.N[1]
44 INT:MUX.OMUX12.N[1]
43 INT:MUX.OMUX12.N[2]
42 INT:MUX.OMUX15.N[0]
41 INT:MUX.OMUX12.N[0]
40 ~INT:INV.0.CLK.IMUX.SEL1
39 INT:MUX.CLK.IMUX.SEL1[3]
38 INT:MUX.CLK.IMUX.SEL1[2]
37 INT:MUX.CLK.IMUX.SEL1[0]
36 INT:MUX.CLK.IMUX.CLK1[0]
35 INT:MUX.CLK.IMUX.CLK1[1]
34 INT:MUX.CLK.IMUX.SEL1[1]
33 INT:MUX.CLK.IMUX.CLK1[2]
32 INT:MUX.CLK.IMUX.CLK1[3]
31 BUFGMUX1:DISABLE_ATTR[0]
30 BUFGMUX1:MUX.CLK[2]
29 BUFGMUX1:MUX.CLK[1]
28 BUFGMUX1:MUX.CLK[3]
27 BUFGMUX1:MUX.CLK[4]
26 BUFGMUX1:MUX.CLK[0]
25 BUFGMUX2:DISABLE_ATTR[0]
24 ~INT:INV.0.CLK.IMUX.SEL2
23 INT:MUX.CLK.IMUX.SEL2[3]
22 INT:MUX.CLK.IMUX.SEL2[2]
21 INT:MUX.CLK.IMUX.SEL2[0]
20 INT:MUX.CLK.IMUX.CLK2[0]
19 INT:MUX.CLK.IMUX.CLK2[1]
18 INT:MUX.CLK.IMUX.SEL2[1]
17 INT:MUX.CLK.IMUX.CLK2[2]
16 INT:MUX.CLK.IMUX.CLK2[3]
15 BUFGMUX2:MUX.CLK[2]
14 BUFGMUX2:MUX.CLK[1]
13 BUFGMUX2:MUX.CLK[3]
12 BUFGMUX2:MUX.CLK[4]
11 BUFGMUX2:MUX.CLK[0]
10 BUFGMUX3:MUX.CLK[2]
9 BUFGMUX3:MUX.CLK[1]
8 BUFGMUX3:MUX.CLK[3]
7 BUFGMUX3:MUX.CLK[4]
6 BUFGMUX3:MUX.CLK[0]
5 INT:MUX.CLK.IMUX.CLK3[3]
4 INT:MUX.CLK.IMUX.CLK3[2]
3 INT:MUX.CLK.IMUX.SEL3[0]
2 INT:MUX.CLK.IMUX.CLK3[0]
1 INT:MUX.CLK.IMUX.CLK3[1]
0 INT:MUX.CLK.IMUX.SEL3[1]
spartan3 CLKB.S3A bittile 1
BitFrame
0 1
5 - INT:MUX.OMUX10.N[2]
4 INT:MUX.CLK.IMUX.SEL3[2] INT:MUX.OMUX11.N[0]
3 INT:MUX.CLK.IMUX.SEL3[3] INT:MUX.OMUX11.N[1]
2 ~INT:INV.0.CLK.IMUX.SEL3 INT:MUX.OMUX10.N[1]
1 - INT:MUX.OMUX10.N[0]
0 - INT:MUX.OMUX11.N[2]
BUFGMUX0:DISABLE_ATTR 0.0.52
BUFGMUX1:DISABLE_ATTR 0.0.31
BUFGMUX2:DISABLE_ATTR 0.0.25
BUFGMUX3:DISABLE_ATTR 0.0.62
LOW 0
HIGH 1
BUFGMUX0:MUX.CLK 0.0.48 0.0.49 0.0.51 0.0.50 0.0.47
BUFGMUX1:MUX.CLK 0.0.27 0.0.28 0.0.30 0.0.29 0.0.26
BUFGMUX2:MUX.CLK 0.0.12 0.0.13 0.0.15 0.0.14 0.0.11
BUFGMUX3:MUX.CLK 0.0.7 0.0.8 0.0.10 0.0.9 0.0.6
INT 0 0 0 0 1
CKIL 0 0 0 1 0
CKIR 0 0 1 0 0
DCM_OUT_L 0 1 0 0 0
DCM_OUT_R 1 0 0 0 0
INT:INV.0.CLK.IMUX.SEL0 0.0.61
INT:INV.0.CLK.IMUX.SEL1 0.0.40
INT:INV.0.CLK.IMUX.SEL2 0.0.24
INT:INV.0.CLK.IMUX.SEL3 1.0.2
inverted ~[0]
INT:MUX.CLK.IMUX.CLK0 0.0.53 0.0.54 0.0.56 0.0.57
INT:MUX.CLK.IMUX.SEL0 0.0.60 0.0.59 0.0.55 0.0.58
PULLUP 0 0 0 0
DBL.W6.2 0 0 0 1
DBL.W7.2 0 0 1 0
DBL.W6.1 0 1 0 1
DBL.W7.1 0 1 1 0
DBL.E6.1 1 0 0 1
DBL.E7.1 1 0 1 0
DBL.E6.0 1 1 0 1
DBL.E7.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK1 0.0.32 0.0.33 0.0.35 0.0.36
INT:MUX.CLK.IMUX.SEL1 0.0.39 0.0.38 0.0.34 0.0.37
PULLUP 0 0 0 0
DBL.W4.2 0 0 0 1
DBL.W5.2 0 0 1 0
DBL.W4.1 0 1 0 1
DBL.W5.1 0 1 1 0
DBL.E4.1 1 0 0 1
DBL.E5.1 1 0 1 0
DBL.E4.0 1 1 0 1
DBL.E5.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK2 0.0.16 0.0.17 0.0.19 0.0.20
INT:MUX.CLK.IMUX.SEL2 0.0.23 0.0.22 0.0.18 0.0.21
PULLUP 0 0 0 0
DBL.W2.2 0 0 0 1
DBL.W3.2 0 0 1 0
DBL.W2.1 0 1 0 1
DBL.W3.1 0 1 1 0
DBL.E2.1 1 0 0 1
DBL.E3.1 1 0 1 0
DBL.E2.0 1 1 0 1
DBL.E3.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK3 0.0.5 0.0.4 0.0.1 0.0.2
INT:MUX.CLK.IMUX.SEL3 1.0.3 1.0.4 0.0.0 0.0.3
PULLUP 0 0 0 0
DBL.W0.2 0 0 0 1
DBL.W1.2 0 0 1 0
DBL.W0.1 0 1 0 1
DBL.W1.1 0 1 1 0
DBL.E0.1 1 0 0 1
DBL.E1.1 1 0 1 0
DBL.E0.0 1 1 0 1
DBL.E1.0 1 1 1 0
INT:MUX.OMUX10.N 1.1.5 1.1.2 1.1.1
INT:MUX.OMUX11.N 1.1.0 1.1.3 1.1.4
INT:MUX.OMUX12.N 0.0.43 0.0.44 0.0.41
INT:MUX.OMUX15.N 0.0.46 0.0.45 0.0.42
NONE 0 0 0
CLK.OUT.2 0 0 1
CLK.OUT.3 0 1 0
CLK.OUT.0 1 0 1
CLK.OUT.1 1 1 0

Bitstream — top tiles

The CLKT.* tiles use two bitstream tiles:

  • tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the top interconnect row
  • tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the high special area (used for top IOB tiles and clock rows in normal columns)

On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH.CLKT.S3A tile.

CLKT.S3

This tile is used on Spartan 3.

Tile CLKT.S3

Cells: 1 IRIs: 0

Muxes

spartan3 CLKT.S3 muxes
DestinationSources
OMUX0.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX3.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX4.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX5.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
CLK.IMUX.SEL0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.SEL1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.SEL2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.SEL3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1
CLK.IMUX.CLK0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.CLK1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.CLK2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.CLK3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1

Bel BUFGMUX0

spartan3 CLKT.S3 bel BUFGMUX0
PinDirectionWires
CLKinputCLK.IMUX.CLK0
OoutputCLK.OUT.0
SinputCLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKT.S3 bel BUFGMUX1
PinDirectionWires
CLKinputCLK.IMUX.CLK1
OoutputCLK.OUT.1
SinputCLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKT.S3 bel BUFGMUX2
PinDirectionWires
CLKinputCLK.IMUX.CLK2
OoutputCLK.OUT.2
SinputCLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKT.S3 bel BUFGMUX3
PinDirectionWires
CLKinputCLK.IMUX.CLK3
OoutputCLK.OUT.3
SinputCLK.IMUX.SEL3

Bel GLOBALSIG_N

spartan3 CLKT.S3 bel GLOBALSIG_N
PinDirectionWires

Bel wires

spartan3 CLKT.S3 bel wires
WirePins
CLK.IMUX.SEL0BUFGMUX0.S
CLK.IMUX.SEL1BUFGMUX1.S
CLK.IMUX.SEL2BUFGMUX2.S
CLK.IMUX.SEL3BUFGMUX3.S
CLK.IMUX.CLK0BUFGMUX0.CLK
CLK.IMUX.CLK1BUFGMUX1.CLK
CLK.IMUX.CLK2BUFGMUX2.CLK
CLK.IMUX.CLK3BUFGMUX3.CLK
CLK.OUT.0BUFGMUX0.O
CLK.OUT.1BUFGMUX1.O
CLK.OUT.2BUFGMUX2.O
CLK.OUT.3BUFGMUX3.O

Bitstream

spartan3 CLKT.S3 bittile 0
BitFrame
0
63 INT:MUX.OMUX0.S[0]
62 ~INT:INV.0.CLK.IMUX.SEL3
61 INT:MUX.CLK.IMUX.SEL3[3]
60 INT:MUX.CLK.IMUX.SEL3[2]
59 INT:MUX.CLK.IMUX.SEL3[1]
58 INT:MUX.CLK.IMUX.CLK3[1]
57 INT:MUX.CLK.IMUX.CLK3[0]
56 INT:MUX.CLK.IMUX.SEL3[0]
55 INT:MUX.CLK.IMUX.CLK3[2]
54 INT:MUX.CLK.IMUX.CLK3[3]
53 BUFGMUX3:MUX.CLK[0]
52 BUFGMUX3:MUX.CLK[3]
51 BUFGMUX3:MUX.CLK[2]
50 BUFGMUX3:MUX.CLK[1]
49 BUFGMUX2:MUX.CLK[0]
48 BUFGMUX2:MUX.CLK[3]
47 BUFGMUX2:MUX.CLK[2]
46 BUFGMUX2:MUX.CLK[1]
45 BUFGMUX2:DISABLE_ATTR[0]
44 INT:MUX.CLK.IMUX.CLK2[2]
43 INT:MUX.CLK.IMUX.CLK2[3]
42 INT:MUX.CLK.IMUX.SEL2[1]
41 INT:MUX.CLK.IMUX.CLK2[1]
40 INT:MUX.CLK.IMUX.CLK2[0]
39 INT:MUX.CLK.IMUX.SEL2[0]
38 INT:MUX.CLK.IMUX.SEL2[3]
37 INT:MUX.CLK.IMUX.SEL2[2]
36 ~INT:INV.0.CLK.IMUX.SEL2
35 BUFGMUX1:MUX.CLK[0]
34 BUFGMUX1:MUX.CLK[3]
33 BUFGMUX1:MUX.CLK[2]
32 BUFGMUX1:MUX.CLK[1]
31 BUFGMUX1:DISABLE_ATTR[0]
30 INT:MUX.CLK.IMUX.CLK1[2]
29 INT:MUX.CLK.IMUX.CLK1[3]
28 INT:MUX.CLK.IMUX.SEL1[1]
27 INT:MUX.CLK.IMUX.CLK1[1]
26 INT:MUX.CLK.IMUX.CLK1[0]
25 INT:MUX.CLK.IMUX.SEL1[0]
24 INT:MUX.CLK.IMUX.SEL1[3]
23 INT:MUX.CLK.IMUX.SEL1[2]
22 ~INT:INV.0.CLK.IMUX.SEL1
21 INT:MUX.OMUX4.S[0]
20 INT:MUX.OMUX5.S[0]
19 INT:MUX.OMUX4.S[2]
18 INT:MUX.OMUX4.S[1]
17 INT:MUX.OMUX5.S[1]
16 INT:MUX.OMUX5.S[2]
15 BUFGMUX0:MUX.CLK[0]
14 BUFGMUX0:MUX.CLK[3]
13 BUFGMUX0:MUX.CLK[2]
12 BUFGMUX0:MUX.CLK[1]
11 BUFGMUX0:DISABLE_ATTR[0]
10 INT:MUX.CLK.IMUX.CLK0[2]
9 INT:MUX.CLK.IMUX.CLK0[3]
8 INT:MUX.CLK.IMUX.SEL0[1]
7 INT:MUX.CLK.IMUX.CLK0[1]
6 INT:MUX.CLK.IMUX.CLK0[0]
5 INT:MUX.CLK.IMUX.SEL0[0]
4 INT:MUX.CLK.IMUX.SEL0[3]
3 INT:MUX.CLK.IMUX.SEL0[2]
2 ~INT:INV.0.CLK.IMUX.SEL0
1 BUFGMUX3:DISABLE_ATTR[0]
0 -
spartan3 CLKT.S3 bittile 1
BitFrame
0
4 INT:MUX.OMUX3.S[1]
3 INT:MUX.OMUX0.S[2]
2 INT:MUX.OMUX0.S[1]
1 INT:MUX.OMUX3.S[0]
0 INT:MUX.OMUX3.S[2]
BUFGMUX0:DISABLE_ATTR 0.0.11
BUFGMUX1:DISABLE_ATTR 0.0.31
BUFGMUX2:DISABLE_ATTR 0.0.45
BUFGMUX3:DISABLE_ATTR 0.0.1
LOW 0
HIGH 1
BUFGMUX0:MUX.CLK 0.0.14 0.0.13 0.0.12 0.0.15
BUFGMUX1:MUX.CLK 0.0.34 0.0.33 0.0.32 0.0.35
BUFGMUX2:MUX.CLK 0.0.48 0.0.47 0.0.46 0.0.49
BUFGMUX3:MUX.CLK 0.0.52 0.0.51 0.0.50 0.0.53
INT 0 0 0 1
CKI 0 0 1 0
DCM_OUT_L 0 1 0 0
DCM_OUT_R 1 0 0 0
INT:INV.0.CLK.IMUX.SEL0 0.0.2
INT:INV.0.CLK.IMUX.SEL1 0.0.22
INT:INV.0.CLK.IMUX.SEL2 0.0.36
INT:INV.0.CLK.IMUX.SEL3 0.0.62
inverted ~[0]
INT:MUX.CLK.IMUX.CLK0 0.0.9 0.0.10 0.0.7 0.0.6
INT:MUX.CLK.IMUX.SEL0 0.0.4 0.0.3 0.0.8 0.0.5
PULLUP 0 0 0 0
DBL.W0.2 0 0 0 1
DBL.W1.2 0 0 1 0
DBL.W0.1 0 1 0 1
DBL.W1.1 0 1 1 0
DBL.E0.1 1 0 0 1
DBL.E1.1 1 0 1 0
DBL.E0.0 1 1 0 1
DBL.E1.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK1 0.0.29 0.0.30 0.0.27 0.0.26
INT:MUX.CLK.IMUX.SEL1 0.0.24 0.0.23 0.0.28 0.0.25
PULLUP 0 0 0 0
DBL.W2.2 0 0 0 1
DBL.W3.2 0 0 1 0
DBL.W2.1 0 1 0 1
DBL.W3.1 0 1 1 0
DBL.E2.1 1 0 0 1
DBL.E3.1 1 0 1 0
DBL.E2.0 1 1 0 1
DBL.E3.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK2 0.0.43 0.0.44 0.0.41 0.0.40
INT:MUX.CLK.IMUX.SEL2 0.0.38 0.0.37 0.0.42 0.0.39
PULLUP 0 0 0 0
DBL.W4.2 0 0 0 1
DBL.W5.2 0 0 1 0
DBL.W4.1 0 1 0 1
DBL.W5.1 0 1 1 0
DBL.E4.1 1 0 0 1
DBL.E5.1 1 0 1 0
DBL.E4.0 1 1 0 1
DBL.E5.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK3 0.0.54 0.0.55 0.0.58 0.0.57
INT:MUX.CLK.IMUX.SEL3 0.0.61 0.0.60 0.0.59 0.0.56
PULLUP 0 0 0 0
DBL.W6.2 0 0 0 1
DBL.W7.2 0 0 1 0
DBL.W6.1 0 1 0 1
DBL.W7.1 0 1 1 0
DBL.E6.1 1 0 0 1
DBL.E7.1 1 0 1 0
DBL.E6.0 1 1 0 1
DBL.E7.0 1 1 1 0
INT:MUX.OMUX0.S 1.0.3 1.0.2 0.0.63
INT:MUX.OMUX3.S 1.0.0 1.0.4 1.0.1
INT:MUX.OMUX4.S 0.0.19 0.0.18 0.0.21
INT:MUX.OMUX5.S 0.0.16 0.0.17 0.0.20
NONE 0 0 0
CLK.OUT.2 0 0 1
CLK.OUT.3 0 1 0
CLK.OUT.0 1 0 1
CLK.OUT.1 1 1 0

CLKT.S3E

This tile is used on Spartan 3E.

Tile CLKT.S3E

Cells: 1 IRIs: 0

Muxes

spartan3 CLKT.S3E muxes
DestinationSources
OMUX0.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX3.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX4.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX5.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
CLK.IMUX.SEL0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.SEL1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.SEL2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.SEL3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1
CLK.IMUX.CLK0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.CLK1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.CLK2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.CLK3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1

Bel BUFGMUX0

spartan3 CLKT.S3E bel BUFGMUX0
PinDirectionWires
CLKinputCLK.IMUX.CLK0
OoutputCLK.OUT.0
SinputCLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKT.S3E bel BUFGMUX1
PinDirectionWires
CLKinputCLK.IMUX.CLK1
OoutputCLK.OUT.1
SinputCLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKT.S3E bel BUFGMUX2
PinDirectionWires
CLKinputCLK.IMUX.CLK2
OoutputCLK.OUT.2
SinputCLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKT.S3E bel BUFGMUX3
PinDirectionWires
CLKinputCLK.IMUX.CLK3
OoutputCLK.OUT.3
SinputCLK.IMUX.SEL3

Bel GLOBALSIG_N

spartan3 CLKT.S3E bel GLOBALSIG_N
PinDirectionWires

Bel wires

spartan3 CLKT.S3E bel wires
WirePins
CLK.IMUX.SEL0BUFGMUX0.S
CLK.IMUX.SEL1BUFGMUX1.S
CLK.IMUX.SEL2BUFGMUX2.S
CLK.IMUX.SEL3BUFGMUX3.S
CLK.IMUX.CLK0BUFGMUX0.CLK
CLK.IMUX.CLK1BUFGMUX1.CLK
CLK.IMUX.CLK2BUFGMUX2.CLK
CLK.IMUX.CLK3BUFGMUX3.CLK
CLK.OUT.0BUFGMUX0.O
CLK.OUT.1BUFGMUX1.O
CLK.OUT.2BUFGMUX2.O
CLK.OUT.3BUFGMUX3.O

Bitstream

spartan3 CLKT.S3E bittile 0
BitFrame
0
63 INT:MUX.CLK.IMUX.SEL3[1]
62 INT:MUX.CLK.IMUX.CLK3[1]
61 INT:MUX.CLK.IMUX.CLK3[0]
60 INT:MUX.CLK.IMUX.SEL3[0]
59 INT:MUX.CLK.IMUX.CLK3[2]
58 INT:MUX.CLK.IMUX.CLK3[3]
57 BUFGMUX3:MUX.CLK[0]
56 BUFGMUX3:MUX.CLK[4]
55 BUFGMUX3:MUX.CLK[3]
54 BUFGMUX3:MUX.CLK[1]
53 BUFGMUX3:MUX.CLK[2]
52 BUFGMUX2:MUX.CLK[0]
51 BUFGMUX2:MUX.CLK[4]
50 BUFGMUX2:MUX.CLK[3]
49 BUFGMUX2:MUX.CLK[1]
48 BUFGMUX2:MUX.CLK[2]
47 INT:MUX.CLK.IMUX.CLK2[3]
46 INT:MUX.CLK.IMUX.CLK2[2]
45 INT:MUX.CLK.IMUX.SEL2[1]
44 INT:MUX.CLK.IMUX.CLK2[1]
43 INT:MUX.CLK.IMUX.CLK2[0]
42 INT:MUX.CLK.IMUX.SEL2[0]
41 INT:MUX.CLK.IMUX.SEL2[2]
40 INT:MUX.CLK.IMUX.SEL2[3]
39 ~INT:INV.0.CLK.IMUX.SEL2
38 BUFGMUX2:DISABLE_ATTR[0]
37 BUFGMUX1:MUX.CLK[0]
36 BUFGMUX1:MUX.CLK[4]
35 BUFGMUX1:MUX.CLK[3]
34 BUFGMUX1:MUX.CLK[1]
33 BUFGMUX1:MUX.CLK[2]
32 BUFGMUX1:DISABLE_ATTR[0]
31 INT:MUX.CLK.IMUX.CLK1[3]
30 INT:MUX.CLK.IMUX.CLK1[2]
29 INT:MUX.CLK.IMUX.SEL1[1]
28 INT:MUX.CLK.IMUX.CLK1[1]
27 INT:MUX.CLK.IMUX.CLK1[0]
26 INT:MUX.CLK.IMUX.SEL1[0]
25 INT:MUX.CLK.IMUX.SEL1[2]
24 INT:MUX.CLK.IMUX.SEL1[3]
23 ~INT:INV.0.CLK.IMUX.SEL1
22 INT:MUX.OMUX4.S[0]
21 INT:MUX.OMUX5.S[0]
20 INT:MUX.OMUX4.S[2]
19 INT:MUX.OMUX4.S[1]
18 INT:MUX.OMUX5.S[1]
17 INT:MUX.OMUX5.S[2]
16 BUFGMUX0:MUX.CLK[0]
15 BUFGMUX0:MUX.CLK[4]
14 BUFGMUX0:MUX.CLK[3]
13 BUFGMUX0:MUX.CLK[1]
12 BUFGMUX0:MUX.CLK[2]
11 BUFGMUX0:DISABLE_ATTR[0]
10 INT:MUX.CLK.IMUX.CLK0[3]
9 INT:MUX.CLK.IMUX.CLK0[2]
8 INT:MUX.CLK.IMUX.SEL0[1]
7 INT:MUX.CLK.IMUX.CLK0[1]
6 INT:MUX.CLK.IMUX.CLK0[0]
5 INT:MUX.CLK.IMUX.SEL0[0]
4 INT:MUX.CLK.IMUX.SEL0[2]
3 INT:MUX.CLK.IMUX.SEL0[3]
2 ~INT:INV.0.CLK.IMUX.SEL0
1 BUFGMUX3:DISABLE_ATTR[0]
0 -
spartan3 CLKT.S3E bittile 1
BitFrame
0
8 INT:MUX.OMUX3.S[0]
7 INT:MUX.OMUX0.S[1]
6 INT:MUX.OMUX0.S[2]
5 INT:MUX.OMUX3.S[1]
4 INT:MUX.OMUX3.S[2]
3 INT:MUX.OMUX0.S[0]
2 ~INT:INV.0.CLK.IMUX.SEL3
1 INT:MUX.CLK.IMUX.SEL3[3]
0 INT:MUX.CLK.IMUX.SEL3[2]
BUFGMUX0:DISABLE_ATTR 0.0.11
BUFGMUX1:DISABLE_ATTR 0.0.32
BUFGMUX2:DISABLE_ATTR 0.0.38
BUFGMUX3:DISABLE_ATTR 0.0.1
LOW 0
HIGH 1
BUFGMUX0:MUX.CLK 0.0.15 0.0.14 0.0.12 0.0.13 0.0.16
BUFGMUX1:MUX.CLK 0.0.36 0.0.35 0.0.33 0.0.34 0.0.37
BUFGMUX2:MUX.CLK 0.0.51 0.0.50 0.0.48 0.0.49 0.0.52
BUFGMUX3:MUX.CLK 0.0.56 0.0.55 0.0.53 0.0.54 0.0.57
INT 0 0 0 0 1
CKIL 0 0 0 1 0
CKIR 0 0 1 0 0
DCM_OUT_L 0 1 0 0 0
DCM_OUT_R 1 0 0 0 0
INT:INV.0.CLK.IMUX.SEL0 0.0.2
INT:INV.0.CLK.IMUX.SEL1 0.0.23
INT:INV.0.CLK.IMUX.SEL2 0.0.39
INT:INV.0.CLK.IMUX.SEL3 1.0.2
inverted ~[0]
INT:MUX.CLK.IMUX.CLK0 0.0.10 0.0.9 0.0.7 0.0.6
INT:MUX.CLK.IMUX.SEL0 0.0.3 0.0.4 0.0.8 0.0.5
PULLUP 0 0 0 0
DBL.W0.2 0 0 0 1
DBL.W1.2 0 0 1 0
DBL.W0.1 0 1 0 1
DBL.W1.1 0 1 1 0
DBL.E0.1 1 0 0 1
DBL.E1.1 1 0 1 0
DBL.E0.0 1 1 0 1
DBL.E1.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK1 0.0.31 0.0.30 0.0.28 0.0.27
INT:MUX.CLK.IMUX.SEL1 0.0.24 0.0.25 0.0.29 0.0.26
PULLUP 0 0 0 0
DBL.W2.2 0 0 0 1
DBL.W3.2 0 0 1 0
DBL.W2.1 0 1 0 1
DBL.W3.1 0 1 1 0
DBL.E2.1 1 0 0 1
DBL.E3.1 1 0 1 0
DBL.E2.0 1 1 0 1
DBL.E3.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK2 0.0.47 0.0.46 0.0.44 0.0.43
INT:MUX.CLK.IMUX.SEL2 0.0.40 0.0.41 0.0.45 0.0.42
PULLUP 0 0 0 0
DBL.W4.2 0 0 0 1
DBL.W5.2 0 0 1 0
DBL.W4.1 0 1 0 1
DBL.W5.1 0 1 1 0
DBL.E4.1 1 0 0 1
DBL.E5.1 1 0 1 0
DBL.E4.0 1 1 0 1
DBL.E5.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK3 0.0.58 0.0.59 0.0.62 0.0.61
INT:MUX.CLK.IMUX.SEL3 1.0.1 1.0.0 0.0.63 0.0.60
PULLUP 0 0 0 0
DBL.W6.2 0 0 0 1
DBL.W7.2 0 0 1 0
DBL.W6.1 0 1 0 1
DBL.W7.1 0 1 1 0
DBL.E6.1 1 0 0 1
DBL.E7.1 1 0 1 0
DBL.E6.0 1 1 0 1
DBL.E7.0 1 1 1 0
INT:MUX.OMUX0.S 1.0.6 1.0.7 1.0.3
INT:MUX.OMUX3.S 1.0.4 1.0.5 1.0.8
INT:MUX.OMUX4.S 0.0.20 0.0.19 0.0.22
INT:MUX.OMUX5.S 0.0.17 0.0.18 0.0.21
NONE 0 0 0
CLK.OUT.2 0 0 1
CLK.OUT.3 0 1 0
CLK.OUT.0 1 0 1
CLK.OUT.1 1 1 0

CLKT.S3A

This tile is used on Spartan 3A and 3A DSP.

Tile CLKT.S3A

Cells: 1 IRIs: 0

Muxes

spartan3 CLKT.S3A muxes
DestinationSources
OMUX0.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX3.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX4.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
OMUX5.SCLK.OUT.0, CLK.OUT.1, CLK.OUT.2, CLK.OUT.3
CLK.IMUX.SEL0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.SEL1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.SEL2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.SEL3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1
CLK.IMUX.CLK0PULLUP, DBL.W0.1, DBL.W0.2, DBL.W1.1, DBL.W1.2, DBL.E0.0, DBL.E0.1, DBL.E1.0, DBL.E1.1
CLK.IMUX.CLK1PULLUP, DBL.W2.1, DBL.W2.2, DBL.W3.1, DBL.W3.2, DBL.E2.0, DBL.E2.1, DBL.E3.0, DBL.E3.1
CLK.IMUX.CLK2PULLUP, DBL.W4.1, DBL.W4.2, DBL.W5.1, DBL.W5.2, DBL.E4.0, DBL.E4.1, DBL.E5.0, DBL.E5.1
CLK.IMUX.CLK3PULLUP, DBL.W6.1, DBL.W6.2, DBL.W7.1, DBL.W7.2, DBL.E6.0, DBL.E6.1, DBL.E7.0, DBL.E7.1

Bel BUFGMUX0

spartan3 CLKT.S3A bel BUFGMUX0
PinDirectionWires
CLKinputCLK.IMUX.CLK0
OoutputCLK.OUT.0
SinputCLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKT.S3A bel BUFGMUX1
PinDirectionWires
CLKinputCLK.IMUX.CLK1
OoutputCLK.OUT.1
SinputCLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKT.S3A bel BUFGMUX2
PinDirectionWires
CLKinputCLK.IMUX.CLK2
OoutputCLK.OUT.2
SinputCLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKT.S3A bel BUFGMUX3
PinDirectionWires
CLKinputCLK.IMUX.CLK3
OoutputCLK.OUT.3
SinputCLK.IMUX.SEL3

Bel GLOBALSIG_N

spartan3 CLKT.S3A bel GLOBALSIG_N
PinDirectionWires

Bel wires

spartan3 CLKT.S3A bel wires
WirePins
CLK.IMUX.SEL0BUFGMUX0.S
CLK.IMUX.SEL1BUFGMUX1.S
CLK.IMUX.SEL2BUFGMUX2.S
CLK.IMUX.SEL3BUFGMUX3.S
CLK.IMUX.CLK0BUFGMUX0.CLK
CLK.IMUX.CLK1BUFGMUX1.CLK
CLK.IMUX.CLK2BUFGMUX2.CLK
CLK.IMUX.CLK3BUFGMUX3.CLK
CLK.OUT.0BUFGMUX0.O
CLK.OUT.1BUFGMUX1.O
CLK.OUT.2BUFGMUX2.O
CLK.OUT.3BUFGMUX3.O

Bitstream

spartan3 CLKT.S3A bittile 0
BitFrame
0
63 INT:MUX.CLK.IMUX.SEL3[1]
62 INT:MUX.CLK.IMUX.CLK3[1]
61 INT:MUX.CLK.IMUX.CLK3[0]
60 INT:MUX.CLK.IMUX.SEL3[0]
59 INT:MUX.CLK.IMUX.CLK3[2]
58 INT:MUX.CLK.IMUX.CLK3[3]
57 BUFGMUX3:MUX.CLK[0]
56 BUFGMUX3:MUX.CLK[4]
55 BUFGMUX3:MUX.CLK[3]
54 BUFGMUX3:MUX.CLK[1]
53 BUFGMUX3:MUX.CLK[2]
52 BUFGMUX2:MUX.CLK[0]
51 BUFGMUX2:MUX.CLK[4]
50 BUFGMUX2:MUX.CLK[3]
49 BUFGMUX2:MUX.CLK[1]
48 BUFGMUX2:MUX.CLK[2]
47 INT:MUX.CLK.IMUX.CLK2[3]
46 INT:MUX.CLK.IMUX.CLK2[2]
45 INT:MUX.CLK.IMUX.SEL2[0]
44 INT:MUX.CLK.IMUX.CLK2[0]
43 INT:MUX.CLK.IMUX.CLK2[1]
42 INT:MUX.CLK.IMUX.SEL2[1]
41 INT:MUX.CLK.IMUX.SEL2[2]
40 INT:MUX.CLK.IMUX.SEL2[3]
39 ~INT:INV.0.CLK.IMUX.SEL2
38 BUFGMUX2:DISABLE_ATTR[0]
37 BUFGMUX1:MUX.CLK[0]
36 BUFGMUX1:MUX.CLK[4]
35 BUFGMUX1:MUX.CLK[3]
34 BUFGMUX1:MUX.CLK[1]
33 BUFGMUX1:MUX.CLK[2]
32 BUFGMUX1:DISABLE_ATTR[0]
31 INT:MUX.CLK.IMUX.CLK1[3]
30 INT:MUX.CLK.IMUX.CLK1[2]
29 INT:MUX.CLK.IMUX.SEL1[0]
28 INT:MUX.CLK.IMUX.CLK1[0]
27 INT:MUX.CLK.IMUX.CLK1[1]
26 INT:MUX.CLK.IMUX.SEL1[1]
25 INT:MUX.CLK.IMUX.SEL1[2]
24 INT:MUX.CLK.IMUX.SEL1[3]
23 ~INT:INV.0.CLK.IMUX.SEL1
22 INT:MUX.OMUX4.S[0]
21 INT:MUX.OMUX5.S[0]
20 INT:MUX.OMUX4.S[2]
19 INT:MUX.OMUX4.S[1]
18 INT:MUX.OMUX5.S[1]
17 INT:MUX.OMUX5.S[2]
16 BUFGMUX0:MUX.CLK[0]
15 BUFGMUX0:MUX.CLK[4]
14 BUFGMUX0:MUX.CLK[3]
13 BUFGMUX0:MUX.CLK[1]
12 BUFGMUX0:MUX.CLK[2]
11 BUFGMUX0:DISABLE_ATTR[0]
10 INT:MUX.CLK.IMUX.CLK0[3]
9 INT:MUX.CLK.IMUX.CLK0[2]
8 INT:MUX.CLK.IMUX.SEL0[1]
7 INT:MUX.CLK.IMUX.CLK0[1]
6 INT:MUX.CLK.IMUX.CLK0[0]
5 INT:MUX.CLK.IMUX.SEL0[0]
4 INT:MUX.CLK.IMUX.SEL0[2]
3 INT:MUX.CLK.IMUX.SEL0[3]
2 ~INT:INV.0.CLK.IMUX.SEL0
1 BUFGMUX3:DISABLE_ATTR[0]
0 -
spartan3 CLKT.S3A bittile 1
BitFrame
0 1
5 - INT:MUX.OMUX3.S[1]
4 - INT:MUX.OMUX3.S[2]
3 - INT:MUX.OMUX0.S[0]
2 ~INT:INV.0.CLK.IMUX.SEL3 INT:MUX.OMUX0.S[2]
1 INT:MUX.CLK.IMUX.SEL3[3] INT:MUX.OMUX3.S[0]
0 INT:MUX.CLK.IMUX.SEL3[2] INT:MUX.OMUX0.S[1]
BUFGMUX0:DISABLE_ATTR 0.0.11
BUFGMUX1:DISABLE_ATTR 0.0.32
BUFGMUX2:DISABLE_ATTR 0.0.38
BUFGMUX3:DISABLE_ATTR 0.0.1
LOW 0
HIGH 1
BUFGMUX0:MUX.CLK 0.0.15 0.0.14 0.0.12 0.0.13 0.0.16
BUFGMUX1:MUX.CLK 0.0.36 0.0.35 0.0.33 0.0.34 0.0.37
BUFGMUX2:MUX.CLK 0.0.51 0.0.50 0.0.48 0.0.49 0.0.52
BUFGMUX3:MUX.CLK 0.0.56 0.0.55 0.0.53 0.0.54 0.0.57
INT 0 0 0 0 1
CKIL 0 0 0 1 0
CKIR 0 0 1 0 0
DCM_OUT_L 0 1 0 0 0
DCM_OUT_R 1 0 0 0 0
INT:INV.0.CLK.IMUX.SEL0 0.0.2
INT:INV.0.CLK.IMUX.SEL1 0.0.23
INT:INV.0.CLK.IMUX.SEL2 0.0.39
INT:INV.0.CLK.IMUX.SEL3 1.0.2
inverted ~[0]
INT:MUX.CLK.IMUX.CLK0 0.0.10 0.0.9 0.0.7 0.0.6
INT:MUX.CLK.IMUX.SEL0 0.0.3 0.0.4 0.0.8 0.0.5
PULLUP 0 0 0 0
DBL.W0.2 0 0 0 1
DBL.W1.2 0 0 1 0
DBL.W0.1 0 1 0 1
DBL.W1.1 0 1 1 0
DBL.E0.1 1 0 0 1
DBL.E1.1 1 0 1 0
DBL.E0.0 1 1 0 1
DBL.E1.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK1 0.0.31 0.0.30 0.0.27 0.0.28
INT:MUX.CLK.IMUX.SEL1 0.0.24 0.0.25 0.0.26 0.0.29
PULLUP 0 0 0 0
DBL.W2.2 0 0 0 1
DBL.W3.2 0 0 1 0
DBL.W2.1 0 1 0 1
DBL.W3.1 0 1 1 0
DBL.E2.1 1 0 0 1
DBL.E3.1 1 0 1 0
DBL.E2.0 1 1 0 1
DBL.E3.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK2 0.0.47 0.0.46 0.0.43 0.0.44
INT:MUX.CLK.IMUX.SEL2 0.0.40 0.0.41 0.0.42 0.0.45
PULLUP 0 0 0 0
DBL.W4.2 0 0 0 1
DBL.W5.2 0 0 1 0
DBL.W4.1 0 1 0 1
DBL.W5.1 0 1 1 0
DBL.E4.1 1 0 0 1
DBL.E5.1 1 0 1 0
DBL.E4.0 1 1 0 1
DBL.E5.0 1 1 1 0
INT:MUX.CLK.IMUX.CLK3 0.0.58 0.0.59 0.0.62 0.0.61
INT:MUX.CLK.IMUX.SEL3 1.0.1 1.0.0 0.0.63 0.0.60
PULLUP 0 0 0 0
DBL.W6.2 0 0 0 1
DBL.W7.2 0 0 1 0
DBL.W6.1 0 1 0 1
DBL.W7.1 0 1 1 0
DBL.E6.1 1 0 0 1
DBL.E7.1 1 0 1 0
DBL.E6.0 1 1 0 1
DBL.E7.0 1 1 1 0
INT:MUX.OMUX0.S 1.1.2 1.1.0 1.1.3
INT:MUX.OMUX3.S 1.1.4 1.1.5 1.1.1
INT:MUX.OMUX4.S 0.0.20 0.0.19 0.0.22
INT:MUX.OMUX5.S 0.0.17 0.0.18 0.0.21
NONE 0 0 0
CLK.OUT.2 0 0 1
CLK.OUT.3 0 1 0
CLK.OUT.0 1 0 1
CLK.OUT.1 1 1 0