Primary global buffers

TODO: document

Bitstream — bottom tiles

The CLKB.* tiles use two bitstream tiles:

tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the bottom interconnect row
tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the low special area (used for bottom IOB tiles and clock rows in normal columns)

On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH.CLKB.S3A tile.

`CLKB.S3`

This tile is used on Spartan 3.

Tile CLKB.S3

Cells: 1

Bel CLK_INT

Switchbox CLK_INT

spartan3 CLKB.S3 switchbox CLK_INT
Destination	Source	Kind
OMUX10.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX11.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX12.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX15.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
CLK.IMUX.SEL0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.SEL1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.SEL2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.SEL3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux
CLK.IMUX.CLK0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.CLK1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.CLK2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.CLK3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux

Bel BUFGMUX0

spartan3 CLKB.S3 bel BUFGMUX0
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK0
O	output	CLK.OUT.0
S	input	CLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKB.S3 bel BUFGMUX1
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK1
O	output	CLK.OUT.1
S	input	CLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKB.S3 bel BUFGMUX2
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK2
O	output	CLK.OUT.2
S	input	CLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKB.S3 bel BUFGMUX3
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK3
O	output	CLK.OUT.3
S	input	CLK.IMUX.SEL3

Bel GLOBALSIG_S

spartan3 CLKB.S3 bel GLOBALSIG_S
Pin	Direction	Wires

Bel wires

spartan3 CLKB.S3 bel wires
Wire	Pins
CLK.IMUX.SEL0	BUFGMUX0.S
CLK.IMUX.SEL1	BUFGMUX1.S
CLK.IMUX.SEL2	BUFGMUX2.S
CLK.IMUX.SEL3	BUFGMUX3.S
CLK.IMUX.CLK0	BUFGMUX0.CLK
CLK.IMUX.CLK1	BUFGMUX1.CLK
CLK.IMUX.CLK2	BUFGMUX2.CLK
CLK.IMUX.CLK3	BUFGMUX3.CLK
CLK.OUT.0	BUFGMUX0.O
CLK.OUT.1	BUFGMUX1.O
CLK.OUT.2	BUFGMUX2.O
CLK.OUT.3	BUFGMUX3.O

Bitstream

spartan3 CLKB.S3 bittile 0
Bit	Frame
Bit	0
62	BUFGMUX0:DISABLE_ATTR[0]
61	~CLK_INT:INV.0.CLK.IMUX.SEL3
60	CLK_INT:MUX.CLK.IMUX.SEL3[2]
59	CLK_INT:MUX.CLK.IMUX.SEL3[3]
58	CLK_INT:MUX.CLK.IMUX.SEL3[1]
57	CLK_INT:MUX.CLK.IMUX.CLK3[1]
56	CLK_INT:MUX.CLK.IMUX.CLK3[0]
55	CLK_INT:MUX.CLK.IMUX.SEL3[0]
54	CLK_INT:MUX.CLK.IMUX.CLK3[3]
53	CLK_INT:MUX.CLK.IMUX.CLK3[2]
52	BUFGMUX3:DISABLE_ATTR[0]
51	BUFGMUX3:MUX.CLK[1]
50	BUFGMUX3:MUX.CLK[2]
49	BUFGMUX3:MUX.CLK[3]
48	BUFGMUX3:MUX.CLK[0]
47	CLK_INT:MUX.OMUX15.N[2]
46	CLK_INT:MUX.OMUX15.N[1]
45	CLK_INT:MUX.OMUX12.N[1]
44	CLK_INT:MUX.OMUX12.N[2]
43	CLK_INT:MUX.OMUX15.N[0]
42	CLK_INT:MUX.OMUX12.N[0]
41	~CLK_INT:INV.0.CLK.IMUX.SEL2
40	CLK_INT:MUX.CLK.IMUX.SEL2[2]
39	CLK_INT:MUX.CLK.IMUX.SEL2[3]
38	CLK_INT:MUX.CLK.IMUX.SEL2[1]
37	CLK_INT:MUX.CLK.IMUX.CLK2[1]
36	CLK_INT:MUX.CLK.IMUX.CLK2[0]
35	CLK_INT:MUX.CLK.IMUX.SEL2[0]
34	CLK_INT:MUX.CLK.IMUX.CLK2[3]
33	CLK_INT:MUX.CLK.IMUX.CLK2[2]
32	BUFGMUX2:DISABLE_ATTR[0]
31	BUFGMUX2:MUX.CLK[1]
30	BUFGMUX2:MUX.CLK[2]
29	BUFGMUX2:MUX.CLK[3]
28	BUFGMUX2:MUX.CLK[0]
27	~CLK_INT:INV.0.CLK.IMUX.SEL1
26	CLK_INT:MUX.CLK.IMUX.SEL1[2]
25	CLK_INT:MUX.CLK.IMUX.SEL1[3]
24	CLK_INT:MUX.CLK.IMUX.SEL1[1]
23	CLK_INT:MUX.CLK.IMUX.CLK1[1]
22	CLK_INT:MUX.CLK.IMUX.CLK1[0]
21	CLK_INT:MUX.CLK.IMUX.SEL1[0]
20	CLK_INT:MUX.CLK.IMUX.CLK1[3]
19	CLK_INT:MUX.CLK.IMUX.CLK1[2]
18	BUFGMUX1:DISABLE_ATTR[0]
17	BUFGMUX1:MUX.CLK[1]
16	BUFGMUX1:MUX.CLK[2]
15	BUFGMUX1:MUX.CLK[3]
14	BUFGMUX1:MUX.CLK[0]
13	BUFGMUX0:MUX.CLK[1]
12	BUFGMUX0:MUX.CLK[2]
11	BUFGMUX0:MUX.CLK[3]
10	BUFGMUX0:MUX.CLK[0]
9	CLK_INT:MUX.CLK.IMUX.CLK0[3]
8	CLK_INT:MUX.CLK.IMUX.CLK0[2]
7	CLK_INT:MUX.CLK.IMUX.SEL0[1]
6	CLK_INT:MUX.CLK.IMUX.CLK0[1]
5	CLK_INT:MUX.CLK.IMUX.CLK0[0]
4	CLK_INT:MUX.CLK.IMUX.SEL0[0]
3	CLK_INT:MUX.CLK.IMUX.SEL0[2]
2	CLK_INT:MUX.CLK.IMUX.SEL0[3]
1	~CLK_INT:INV.0.CLK.IMUX.SEL0
0	CLK_INT:MUX.OMUX10.N[0]

spartan3 CLKB.S3 bittile 1
Bit	Frame
Bit	0
11	CLK_INT:MUX.OMUX11.N[2]
10	CLK_INT:MUX.OMUX11.N[0]
9	CLK_INT:MUX.OMUX10.N[1]
8	CLK_INT:MUX.OMUX10.N[2]
7	CLK_INT:MUX.OMUX11.N[1]
6	-
5	-
4	-
3	-
2	-
1	-
0	-

BUFGMUX0:DISABLE_ATTR	0.0.62
BUFGMUX1:DISABLE_ATTR	0.0.18
BUFGMUX2:DISABLE_ATTR	0.0.32
BUFGMUX3:DISABLE_ATTR	0.0.52
LOW	0
HIGH	1

BUFGMUX0:MUX.CLK	0.0.11	0.0.12	0.0.13	0.0.10
BUFGMUX1:MUX.CLK	0.0.15	0.0.16	0.0.17	0.0.14
BUFGMUX2:MUX.CLK	0.0.29	0.0.30	0.0.31	0.0.28
BUFGMUX3:MUX.CLK	0.0.49	0.0.50	0.0.51	0.0.48
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.CLK.IMUX.SEL0	0.0.1
CLK_INT:INV.0.CLK.IMUX.SEL1	0.0.27
CLK_INT:INV.0.CLK.IMUX.SEL2	0.0.41
CLK_INT:INV.0.CLK.IMUX.SEL3	0.0.61
inverted	~[0]

CLK_INT:MUX.CLK.IMUX.CLK0	0.0.9	0.0.8	0.0.6	0.0.5
CLK_INT:MUX.CLK.IMUX.SEL0	0.0.2	0.0.3	0.0.7	0.0.4
PULLUP	0	0	0	0
DBL.W0.2	0	0	0	1
DBL.W1.2	0	0	1	0
DBL.W0.1	0	1	0	1
DBL.W1.1	0	1	1	0
DBL.E0.1	1	0	0	1
DBL.E1.1	1	0	1	0
DBL.E0.0	1	1	0	1
DBL.E1.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK1	0.0.20	0.0.19	0.0.23	0.0.22
CLK_INT:MUX.CLK.IMUX.SEL1	0.0.25	0.0.26	0.0.24	0.0.21
PULLUP	0	0	0	0
DBL.W2.2	0	0	0	1
DBL.W3.2	0	0	1	0
DBL.W2.1	0	1	0	1
DBL.W3.1	0	1	1	0
DBL.E2.1	1	0	0	1
DBL.E3.1	1	0	1	0
DBL.E2.0	1	1	0	1
DBL.E3.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK2	0.0.34	0.0.33	0.0.37	0.0.36
CLK_INT:MUX.CLK.IMUX.SEL2	0.0.39	0.0.40	0.0.38	0.0.35
PULLUP	0	0	0	0
DBL.W4.2	0	0	0	1
DBL.W5.2	0	0	1	0
DBL.W4.1	0	1	0	1
DBL.W5.1	0	1	1	0
DBL.E4.1	1	0	0	1
DBL.E5.1	1	0	1	0
DBL.E4.0	1	1	0	1
DBL.E5.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK3	0.0.54	0.0.53	0.0.57	0.0.56
CLK_INT:MUX.CLK.IMUX.SEL3	0.0.59	0.0.60	0.0.58	0.0.55
PULLUP	0	0	0	0
DBL.W6.2	0	0	0	1
DBL.W7.2	0	0	1	0
DBL.W6.1	0	1	0	1
DBL.W7.1	0	1	1	0
DBL.E6.1	1	0	0	1
DBL.E7.1	1	0	1	0
DBL.E6.0	1	1	0	1
DBL.E7.0	1	1	1	0

CLK_INT:MUX.OMUX10.N	1.0.8	1.0.9	0.0.0
CLK_INT:MUX.OMUX11.N	1.0.11	1.0.7	1.0.10
CLK_INT:MUX.OMUX12.N	0.0.44	0.0.45	0.0.42
CLK_INT:MUX.OMUX15.N	0.0.47	0.0.46	0.0.43
NONE	0	0	0
CLK.OUT.2	0	0	1
CLK.OUT.3	0	1	0
CLK.OUT.0	1	0	1
CLK.OUT.1	1	1	0

`CLKB.S3E`

This tile is used on Spartan 3E.

Tile CLKB.S3E

Cells: 1

Bel CLK_INT

Switchbox CLK_INT

spartan3 CLKB.S3E switchbox CLK_INT
Destination	Source	Kind
OMUX10.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX11.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX12.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX15.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
CLK.IMUX.SEL0	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux
CLK.IMUX.SEL1	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.SEL2	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.SEL3	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.CLK0	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux
CLK.IMUX.CLK1	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.CLK2	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.CLK3	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux

Bel BUFGMUX0

spartan3 CLKB.S3E bel BUFGMUX0
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK0
O	output	CLK.OUT.0
S	input	CLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKB.S3E bel BUFGMUX1
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK1
O	output	CLK.OUT.1
S	input	CLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKB.S3E bel BUFGMUX2
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK2
O	output	CLK.OUT.2
S	input	CLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKB.S3E bel BUFGMUX3
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK3
O	output	CLK.OUT.3
S	input	CLK.IMUX.SEL3

Bel GLOBALSIG_S

spartan3 CLKB.S3E bel GLOBALSIG_S
Pin	Direction	Wires

Bel wires

spartan3 CLKB.S3E bel wires
Wire	Pins
CLK.IMUX.SEL0	BUFGMUX0.S
CLK.IMUX.SEL1	BUFGMUX1.S
CLK.IMUX.SEL2	BUFGMUX2.S
CLK.IMUX.SEL3	BUFGMUX3.S
CLK.IMUX.CLK0	BUFGMUX0.CLK
CLK.IMUX.CLK1	BUFGMUX1.CLK
CLK.IMUX.CLK2	BUFGMUX2.CLK
CLK.IMUX.CLK3	BUFGMUX3.CLK
CLK.OUT.0	BUFGMUX0.O
CLK.OUT.1	BUFGMUX1.O
CLK.OUT.2	BUFGMUX2.O
CLK.OUT.3	BUFGMUX3.O

Bitstream

spartan3 CLKB.S3E bittile 0
Bit	Frame
Bit	0
62	BUFGMUX3:DISABLE_ATTR[0]
61	~CLK_INT:INV.0.CLK.IMUX.SEL0
60	CLK_INT:MUX.CLK.IMUX.SEL0[3]
59	CLK_INT:MUX.CLK.IMUX.SEL0[2]
58	CLK_INT:MUX.CLK.IMUX.SEL0[0]
57	CLK_INT:MUX.CLK.IMUX.CLK0[0]
56	CLK_INT:MUX.CLK.IMUX.CLK0[1]
55	CLK_INT:MUX.CLK.IMUX.SEL0[1]
54	CLK_INT:MUX.CLK.IMUX.CLK0[2]
53	CLK_INT:MUX.CLK.IMUX.CLK0[3]
52	BUFGMUX0:DISABLE_ATTR[0]
51	BUFGMUX0:MUX.CLK[2]
50	BUFGMUX0:MUX.CLK[1]
49	BUFGMUX0:MUX.CLK[3]
48	BUFGMUX0:MUX.CLK[4]
47	BUFGMUX0:MUX.CLK[0]
46	CLK_INT:MUX.OMUX15.N[2]
45	CLK_INT:MUX.OMUX15.N[1]
44	CLK_INT:MUX.OMUX12.N[1]
43	CLK_INT:MUX.OMUX12.N[2]
42	CLK_INT:MUX.OMUX15.N[0]
41	CLK_INT:MUX.OMUX12.N[0]
40	~CLK_INT:INV.0.CLK.IMUX.SEL1
39	CLK_INT:MUX.CLK.IMUX.SEL1[3]
38	CLK_INT:MUX.CLK.IMUX.SEL1[2]
37	CLK_INT:MUX.CLK.IMUX.SEL1[0]
36	CLK_INT:MUX.CLK.IMUX.CLK1[0]
35	CLK_INT:MUX.CLK.IMUX.CLK1[1]
34	CLK_INT:MUX.CLK.IMUX.SEL1[1]
33	CLK_INT:MUX.CLK.IMUX.CLK1[2]
32	CLK_INT:MUX.CLK.IMUX.CLK1[3]
31	BUFGMUX1:DISABLE_ATTR[0]
30	BUFGMUX1:MUX.CLK[2]
29	BUFGMUX1:MUX.CLK[1]
28	BUFGMUX1:MUX.CLK[3]
27	BUFGMUX1:MUX.CLK[4]
26	BUFGMUX1:MUX.CLK[0]
25	BUFGMUX2:DISABLE_ATTR[0]
24	~CLK_INT:INV.0.CLK.IMUX.SEL2
23	CLK_INT:MUX.CLK.IMUX.SEL2[3]
22	CLK_INT:MUX.CLK.IMUX.SEL2[2]
21	CLK_INT:MUX.CLK.IMUX.SEL2[0]
20	CLK_INT:MUX.CLK.IMUX.CLK2[0]
19	CLK_INT:MUX.CLK.IMUX.CLK2[1]
18	CLK_INT:MUX.CLK.IMUX.SEL2[1]
17	CLK_INT:MUX.CLK.IMUX.CLK2[2]
16	CLK_INT:MUX.CLK.IMUX.CLK2[3]
15	BUFGMUX2:MUX.CLK[2]
14	BUFGMUX2:MUX.CLK[1]
13	BUFGMUX2:MUX.CLK[3]
12	BUFGMUX2:MUX.CLK[4]
11	BUFGMUX2:MUX.CLK[0]
10	BUFGMUX3:MUX.CLK[2]
9	BUFGMUX3:MUX.CLK[1]
8	BUFGMUX3:MUX.CLK[3]
7	BUFGMUX3:MUX.CLK[4]
6	BUFGMUX3:MUX.CLK[0]
5	CLK_INT:MUX.CLK.IMUX.CLK3[3]
4	CLK_INT:MUX.CLK.IMUX.CLK3[2]
3	CLK_INT:MUX.CLK.IMUX.SEL3[0]
2	CLK_INT:MUX.CLK.IMUX.CLK3[0]
1	CLK_INT:MUX.CLK.IMUX.CLK3[1]
0	CLK_INT:MUX.CLK.IMUX.SEL3[1]

spartan3 CLKB.S3E bittile 1
Bit	Frame
Bit	0
15	CLK_INT:MUX.OMUX11.N[0]
14	CLK_INT:MUX.OMUX11.N[1]
13	CLK_INT:MUX.OMUX10.N[1]
12	CLK_INT:MUX.OMUX10.N[2]
11	CLK_INT:MUX.CLK.IMUX.SEL3[2]
10	CLK_INT:MUX.CLK.IMUX.SEL3[3]
9	~CLK_INT:INV.0.CLK.IMUX.SEL3
8	CLK_INT:MUX.OMUX10.N[0]
7	CLK_INT:MUX.OMUX11.N[2]
6	-
5	-
4	-
3	-
2	-
1	-
0	-

BUFGMUX0:DISABLE_ATTR	0.0.52
BUFGMUX1:DISABLE_ATTR	0.0.31
BUFGMUX2:DISABLE_ATTR	0.0.25
BUFGMUX3:DISABLE_ATTR	0.0.62
LOW	0
HIGH	1

BUFGMUX0:MUX.CLK	0.0.48	0.0.49	0.0.51	0.0.50	0.0.47
BUFGMUX1:MUX.CLK	0.0.27	0.0.28	0.0.30	0.0.29	0.0.26
BUFGMUX2:MUX.CLK	0.0.12	0.0.13	0.0.15	0.0.14	0.0.11
BUFGMUX3:MUX.CLK	0.0.7	0.0.8	0.0.10	0.0.9	0.0.6
INT	0	0	0	0	1
CKIL	0	0	0	1	0
CKIR	0	0	1	0	0
DCM_OUT_L	0	1	0	0	0
DCM_OUT_R	1	0	0	0	0

CLK_INT:INV.0.CLK.IMUX.SEL0	0.0.61
CLK_INT:INV.0.CLK.IMUX.SEL1	0.0.40
CLK_INT:INV.0.CLK.IMUX.SEL2	0.0.24
CLK_INT:INV.0.CLK.IMUX.SEL3	1.0.9
inverted	~[0]

CLK_INT:MUX.CLK.IMUX.CLK0	0.0.53	0.0.54	0.0.56	0.0.57
CLK_INT:MUX.CLK.IMUX.SEL0	0.0.60	0.0.59	0.0.55	0.0.58
PULLUP	0	0	0	0
DBL.W6.2	0	0	0	1
DBL.W7.2	0	0	1	0
DBL.W6.1	0	1	0	1
DBL.W7.1	0	1	1	0
DBL.E6.1	1	0	0	1
DBL.E7.1	1	0	1	0
DBL.E6.0	1	1	0	1
DBL.E7.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK1	0.0.32	0.0.33	0.0.35	0.0.36
CLK_INT:MUX.CLK.IMUX.SEL1	0.0.39	0.0.38	0.0.34	0.0.37
PULLUP	0	0	0	0
DBL.W4.2	0	0	0	1
DBL.W5.2	0	0	1	0
DBL.W4.1	0	1	0	1
DBL.W5.1	0	1	1	0
DBL.E4.1	1	0	0	1
DBL.E5.1	1	0	1	0
DBL.E4.0	1	1	0	1
DBL.E5.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK2	0.0.16	0.0.17	0.0.19	0.0.20
CLK_INT:MUX.CLK.IMUX.SEL2	0.0.23	0.0.22	0.0.18	0.0.21
PULLUP	0	0	0	0
DBL.W2.2	0	0	0	1
DBL.W3.2	0	0	1	0
DBL.W2.1	0	1	0	1
DBL.W3.1	0	1	1	0
DBL.E2.1	1	0	0	1
DBL.E3.1	1	0	1	0
DBL.E2.0	1	1	0	1
DBL.E3.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK3	0.0.5	0.0.4	0.0.1	0.0.2
CLK_INT:MUX.CLK.IMUX.SEL3	1.0.10	1.0.11	0.0.0	0.0.3
PULLUP	0	0	0	0
DBL.W0.2	0	0	0	1
DBL.W1.2	0	0	1	0
DBL.W0.1	0	1	0	1
DBL.W1.1	0	1	1	0
DBL.E0.1	1	0	0	1
DBL.E1.1	1	0	1	0
DBL.E0.0	1	1	0	1
DBL.E1.0	1	1	1	0

CLK_INT:MUX.OMUX10.N	1.0.12	1.0.13	1.0.8
CLK_INT:MUX.OMUX11.N	1.0.7	1.0.14	1.0.15
CLK_INT:MUX.OMUX12.N	0.0.43	0.0.44	0.0.41
CLK_INT:MUX.OMUX15.N	0.0.46	0.0.45	0.0.42
NONE	0	0	0
CLK.OUT.2	0	0	1
CLK.OUT.3	0	1	0
CLK.OUT.0	1	0	1
CLK.OUT.1	1	1	0

`CLKB.S3A`

This tile is used on Spartan 3A and 3A DSP.

Tile CLKB.S3A

Cells: 1

Bel CLK_INT

Switchbox CLK_INT

spartan3 CLKB.S3A switchbox CLK_INT
Destination	Source	Kind
OMUX10.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX11.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX12.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX15.N	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
CLK.IMUX.SEL0	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux
CLK.IMUX.SEL1	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.SEL2	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.SEL3	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.CLK0	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux
CLK.IMUX.CLK1	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.CLK2	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.CLK3	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux

Bel BUFGMUX0

spartan3 CLKB.S3A bel BUFGMUX0
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK0
O	output	CLK.OUT.0
S	input	CLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKB.S3A bel BUFGMUX1
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK1
O	output	CLK.OUT.1
S	input	CLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKB.S3A bel BUFGMUX2
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK2
O	output	CLK.OUT.2
S	input	CLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKB.S3A bel BUFGMUX3
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK3
O	output	CLK.OUT.3
S	input	CLK.IMUX.SEL3

Bel GLOBALSIG_S

spartan3 CLKB.S3A bel GLOBALSIG_S
Pin	Direction	Wires

Bel wires

spartan3 CLKB.S3A bel wires
Wire	Pins
CLK.IMUX.SEL0	BUFGMUX0.S
CLK.IMUX.SEL1	BUFGMUX1.S
CLK.IMUX.SEL2	BUFGMUX2.S
CLK.IMUX.SEL3	BUFGMUX3.S
CLK.IMUX.CLK0	BUFGMUX0.CLK
CLK.IMUX.CLK1	BUFGMUX1.CLK
CLK.IMUX.CLK2	BUFGMUX2.CLK
CLK.IMUX.CLK3	BUFGMUX3.CLK
CLK.OUT.0	BUFGMUX0.O
CLK.OUT.1	BUFGMUX1.O
CLK.OUT.2	BUFGMUX2.O
CLK.OUT.3	BUFGMUX3.O

Bitstream

spartan3 CLKB.S3A bittile 0
Bit	Frame
Bit	0
62	BUFGMUX3:DISABLE_ATTR[0]
61	~CLK_INT:INV.0.CLK.IMUX.SEL0
60	CLK_INT:MUX.CLK.IMUX.SEL0[3]
59	CLK_INT:MUX.CLK.IMUX.SEL0[2]
58	CLK_INT:MUX.CLK.IMUX.SEL0[0]
57	CLK_INT:MUX.CLK.IMUX.CLK0[0]
56	CLK_INT:MUX.CLK.IMUX.CLK0[1]
55	CLK_INT:MUX.CLK.IMUX.SEL0[1]
54	CLK_INT:MUX.CLK.IMUX.CLK0[2]
53	CLK_INT:MUX.CLK.IMUX.CLK0[3]
52	BUFGMUX0:DISABLE_ATTR[0]
51	BUFGMUX0:MUX.CLK[2]
50	BUFGMUX0:MUX.CLK[1]
49	BUFGMUX0:MUX.CLK[3]
48	BUFGMUX0:MUX.CLK[4]
47	BUFGMUX0:MUX.CLK[0]
46	CLK_INT:MUX.OMUX15.N[2]
45	CLK_INT:MUX.OMUX15.N[1]
44	CLK_INT:MUX.OMUX12.N[1]
43	CLK_INT:MUX.OMUX12.N[2]
42	CLK_INT:MUX.OMUX15.N[0]
41	CLK_INT:MUX.OMUX12.N[0]
40	~CLK_INT:INV.0.CLK.IMUX.SEL1
39	CLK_INT:MUX.CLK.IMUX.SEL1[3]
38	CLK_INT:MUX.CLK.IMUX.SEL1[2]
37	CLK_INT:MUX.CLK.IMUX.SEL1[0]
36	CLK_INT:MUX.CLK.IMUX.CLK1[0]
35	CLK_INT:MUX.CLK.IMUX.CLK1[1]
34	CLK_INT:MUX.CLK.IMUX.SEL1[1]
33	CLK_INT:MUX.CLK.IMUX.CLK1[2]
32	CLK_INT:MUX.CLK.IMUX.CLK1[3]
31	BUFGMUX1:DISABLE_ATTR[0]
30	BUFGMUX1:MUX.CLK[2]
29	BUFGMUX1:MUX.CLK[1]
28	BUFGMUX1:MUX.CLK[3]
27	BUFGMUX1:MUX.CLK[4]
26	BUFGMUX1:MUX.CLK[0]
25	BUFGMUX2:DISABLE_ATTR[0]
24	~CLK_INT:INV.0.CLK.IMUX.SEL2
23	CLK_INT:MUX.CLK.IMUX.SEL2[3]
22	CLK_INT:MUX.CLK.IMUX.SEL2[2]
21	CLK_INT:MUX.CLK.IMUX.SEL2[0]
20	CLK_INT:MUX.CLK.IMUX.CLK2[0]
19	CLK_INT:MUX.CLK.IMUX.CLK2[1]
18	CLK_INT:MUX.CLK.IMUX.SEL2[1]
17	CLK_INT:MUX.CLK.IMUX.CLK2[2]
16	CLK_INT:MUX.CLK.IMUX.CLK2[3]
15	BUFGMUX2:MUX.CLK[2]
14	BUFGMUX2:MUX.CLK[1]
13	BUFGMUX2:MUX.CLK[3]
12	BUFGMUX2:MUX.CLK[4]
11	BUFGMUX2:MUX.CLK[0]
10	BUFGMUX3:MUX.CLK[2]
9	BUFGMUX3:MUX.CLK[1]
8	BUFGMUX3:MUX.CLK[3]
7	BUFGMUX3:MUX.CLK[4]
6	BUFGMUX3:MUX.CLK[0]
5	CLK_INT:MUX.CLK.IMUX.CLK3[3]
4	CLK_INT:MUX.CLK.IMUX.CLK3[2]
3	CLK_INT:MUX.CLK.IMUX.SEL3[0]
2	CLK_INT:MUX.CLK.IMUX.CLK3[0]
1	CLK_INT:MUX.CLK.IMUX.CLK3[1]
0	CLK_INT:MUX.CLK.IMUX.SEL3[1]

spartan3 CLKB.S3A bittile 1
Bit	Frame
Bit	0	1
5	-	CLK_INT:MUX.OMUX10.N[2]
4	CLK_INT:MUX.CLK.IMUX.SEL3[2]	CLK_INT:MUX.OMUX11.N[0]
3	CLK_INT:MUX.CLK.IMUX.SEL3[3]	CLK_INT:MUX.OMUX11.N[1]
2	~CLK_INT:INV.0.CLK.IMUX.SEL3	CLK_INT:MUX.OMUX10.N[1]
1	-	CLK_INT:MUX.OMUX10.N[0]
0	-	CLK_INT:MUX.OMUX11.N[2]

BUFGMUX0:DISABLE_ATTR	0.0.52
BUFGMUX1:DISABLE_ATTR	0.0.31
BUFGMUX2:DISABLE_ATTR	0.0.25
BUFGMUX3:DISABLE_ATTR	0.0.62
LOW	0
HIGH	1

BUFGMUX0:MUX.CLK	0.0.48	0.0.49	0.0.51	0.0.50	0.0.47
BUFGMUX1:MUX.CLK	0.0.27	0.0.28	0.0.30	0.0.29	0.0.26
BUFGMUX2:MUX.CLK	0.0.12	0.0.13	0.0.15	0.0.14	0.0.11
BUFGMUX3:MUX.CLK	0.0.7	0.0.8	0.0.10	0.0.9	0.0.6
INT	0	0	0	0	1
CKIL	0	0	0	1	0
CKIR	0	0	1	0	0
DCM_OUT_L	0	1	0	0	0
DCM_OUT_R	1	0	0	0	0

CLK_INT:INV.0.CLK.IMUX.SEL0	0.0.61
CLK_INT:INV.0.CLK.IMUX.SEL1	0.0.40
CLK_INT:INV.0.CLK.IMUX.SEL2	0.0.24
CLK_INT:INV.0.CLK.IMUX.SEL3	1.0.2
inverted	~[0]

CLK_INT:MUX.CLK.IMUX.CLK0	0.0.53	0.0.54	0.0.56	0.0.57
CLK_INT:MUX.CLK.IMUX.SEL0	0.0.60	0.0.59	0.0.55	0.0.58
PULLUP	0	0	0	0
DBL.W6.2	0	0	0	1
DBL.W7.2	0	0	1	0
DBL.W6.1	0	1	0	1
DBL.W7.1	0	1	1	0
DBL.E6.1	1	0	0	1
DBL.E7.1	1	0	1	0
DBL.E6.0	1	1	0	1
DBL.E7.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK1	0.0.32	0.0.33	0.0.35	0.0.36
CLK_INT:MUX.CLK.IMUX.SEL1	0.0.39	0.0.38	0.0.34	0.0.37
PULLUP	0	0	0	0
DBL.W4.2	0	0	0	1
DBL.W5.2	0	0	1	0
DBL.W4.1	0	1	0	1
DBL.W5.1	0	1	1	0
DBL.E4.1	1	0	0	1
DBL.E5.1	1	0	1	0
DBL.E4.0	1	1	0	1
DBL.E5.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK2	0.0.16	0.0.17	0.0.19	0.0.20
CLK_INT:MUX.CLK.IMUX.SEL2	0.0.23	0.0.22	0.0.18	0.0.21
PULLUP	0	0	0	0
DBL.W2.2	0	0	0	1
DBL.W3.2	0	0	1	0
DBL.W2.1	0	1	0	1
DBL.W3.1	0	1	1	0
DBL.E2.1	1	0	0	1
DBL.E3.1	1	0	1	0
DBL.E2.0	1	1	0	1
DBL.E3.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK3	0.0.5	0.0.4	0.0.1	0.0.2
CLK_INT:MUX.CLK.IMUX.SEL3	1.0.3	1.0.4	0.0.0	0.0.3
PULLUP	0	0	0	0
DBL.W0.2	0	0	0	1
DBL.W1.2	0	0	1	0
DBL.W0.1	0	1	0	1
DBL.W1.1	0	1	1	0
DBL.E0.1	1	0	0	1
DBL.E1.1	1	0	1	0
DBL.E0.0	1	1	0	1
DBL.E1.0	1	1	1	0

CLK_INT:MUX.OMUX10.N	1.1.5	1.1.2	1.1.1
CLK_INT:MUX.OMUX11.N	1.1.0	1.1.3	1.1.4
CLK_INT:MUX.OMUX12.N	0.0.43	0.0.44	0.0.41
CLK_INT:MUX.OMUX15.N	0.0.46	0.0.45	0.0.42
NONE	0	0	0
CLK.OUT.2	0	0	1
CLK.OUT.3	0	1	0
CLK.OUT.0	1	0	1
CLK.OUT.1	1	1	0

Bitstream — top tiles

The CLKT.* tiles use two bitstream tiles:

tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the top interconnect row
tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the high special area (used for top IOB tiles and clock rows in normal columns)

On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH.CLKT.S3A tile.

`CLKT.S3`

This tile is used on Spartan 3.

Tile CLKT.S3

Cells: 1

Bel CLK_INT

Switchbox CLK_INT

spartan3 CLKT.S3 switchbox CLK_INT
Destination	Source	Kind
OMUX0.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX3.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX4.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX5.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
CLK.IMUX.SEL0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.SEL1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.SEL2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.SEL3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux
CLK.IMUX.CLK0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.CLK1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.CLK2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.CLK3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux

Bel BUFGMUX0

spartan3 CLKT.S3 bel BUFGMUX0
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK0
O	output	CLK.OUT.0
S	input	CLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKT.S3 bel BUFGMUX1
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK1
O	output	CLK.OUT.1
S	input	CLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKT.S3 bel BUFGMUX2
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK2
O	output	CLK.OUT.2
S	input	CLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKT.S3 bel BUFGMUX3
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK3
O	output	CLK.OUT.3
S	input	CLK.IMUX.SEL3

Bel GLOBALSIG_N

spartan3 CLKT.S3 bel GLOBALSIG_N
Pin	Direction	Wires

Bel wires

spartan3 CLKT.S3 bel wires
Wire	Pins
CLK.IMUX.SEL0	BUFGMUX0.S
CLK.IMUX.SEL1	BUFGMUX1.S
CLK.IMUX.SEL2	BUFGMUX2.S
CLK.IMUX.SEL3	BUFGMUX3.S
CLK.IMUX.CLK0	BUFGMUX0.CLK
CLK.IMUX.CLK1	BUFGMUX1.CLK
CLK.IMUX.CLK2	BUFGMUX2.CLK
CLK.IMUX.CLK3	BUFGMUX3.CLK
CLK.OUT.0	BUFGMUX0.O
CLK.OUT.1	BUFGMUX1.O
CLK.OUT.2	BUFGMUX2.O
CLK.OUT.3	BUFGMUX3.O

Bitstream

spartan3 CLKT.S3 bittile 0
Bit	Frame
Bit	0
63	CLK_INT:MUX.OMUX0.S[0]
62	~CLK_INT:INV.0.CLK.IMUX.SEL3
61	CLK_INT:MUX.CLK.IMUX.SEL3[3]
60	CLK_INT:MUX.CLK.IMUX.SEL3[2]
59	CLK_INT:MUX.CLK.IMUX.SEL3[1]
58	CLK_INT:MUX.CLK.IMUX.CLK3[1]
57	CLK_INT:MUX.CLK.IMUX.CLK3[0]
56	CLK_INT:MUX.CLK.IMUX.SEL3[0]
55	CLK_INT:MUX.CLK.IMUX.CLK3[2]
54	CLK_INT:MUX.CLK.IMUX.CLK3[3]
53	BUFGMUX3:MUX.CLK[0]
52	BUFGMUX3:MUX.CLK[3]
51	BUFGMUX3:MUX.CLK[2]
50	BUFGMUX3:MUX.CLK[1]
49	BUFGMUX2:MUX.CLK[0]
48	BUFGMUX2:MUX.CLK[3]
47	BUFGMUX2:MUX.CLK[2]
46	BUFGMUX2:MUX.CLK[1]
45	BUFGMUX2:DISABLE_ATTR[0]
44	CLK_INT:MUX.CLK.IMUX.CLK2[2]
43	CLK_INT:MUX.CLK.IMUX.CLK2[3]
42	CLK_INT:MUX.CLK.IMUX.SEL2[1]
41	CLK_INT:MUX.CLK.IMUX.CLK2[1]
40	CLK_INT:MUX.CLK.IMUX.CLK2[0]
39	CLK_INT:MUX.CLK.IMUX.SEL2[0]
38	CLK_INT:MUX.CLK.IMUX.SEL2[3]
37	CLK_INT:MUX.CLK.IMUX.SEL2[2]
36	~CLK_INT:INV.0.CLK.IMUX.SEL2
35	BUFGMUX1:MUX.CLK[0]
34	BUFGMUX1:MUX.CLK[3]
33	BUFGMUX1:MUX.CLK[2]
32	BUFGMUX1:MUX.CLK[1]
31	BUFGMUX1:DISABLE_ATTR[0]
30	CLK_INT:MUX.CLK.IMUX.CLK1[2]
29	CLK_INT:MUX.CLK.IMUX.CLK1[3]
28	CLK_INT:MUX.CLK.IMUX.SEL1[1]
27	CLK_INT:MUX.CLK.IMUX.CLK1[1]
26	CLK_INT:MUX.CLK.IMUX.CLK1[0]
25	CLK_INT:MUX.CLK.IMUX.SEL1[0]
24	CLK_INT:MUX.CLK.IMUX.SEL1[3]
23	CLK_INT:MUX.CLK.IMUX.SEL1[2]
22	~CLK_INT:INV.0.CLK.IMUX.SEL1
21	CLK_INT:MUX.OMUX4.S[0]
20	CLK_INT:MUX.OMUX5.S[0]
19	CLK_INT:MUX.OMUX4.S[2]
18	CLK_INT:MUX.OMUX4.S[1]
17	CLK_INT:MUX.OMUX5.S[1]
16	CLK_INT:MUX.OMUX5.S[2]
15	BUFGMUX0:MUX.CLK[0]
14	BUFGMUX0:MUX.CLK[3]
13	BUFGMUX0:MUX.CLK[2]
12	BUFGMUX0:MUX.CLK[1]
11	BUFGMUX0:DISABLE_ATTR[0]
10	CLK_INT:MUX.CLK.IMUX.CLK0[2]
9	CLK_INT:MUX.CLK.IMUX.CLK0[3]
8	CLK_INT:MUX.CLK.IMUX.SEL0[1]
7	CLK_INT:MUX.CLK.IMUX.CLK0[1]
6	CLK_INT:MUX.CLK.IMUX.CLK0[0]
5	CLK_INT:MUX.CLK.IMUX.SEL0[0]
4	CLK_INT:MUX.CLK.IMUX.SEL0[3]
3	CLK_INT:MUX.CLK.IMUX.SEL0[2]
2	~CLK_INT:INV.0.CLK.IMUX.SEL0
1	BUFGMUX3:DISABLE_ATTR[0]
0	-

spartan3 CLKT.S3 bittile 1
Bit	Frame
Bit	0
4	CLK_INT:MUX.OMUX3.S[1]
3	CLK_INT:MUX.OMUX0.S[2]
2	CLK_INT:MUX.OMUX0.S[1]
1	CLK_INT:MUX.OMUX3.S[0]
0	CLK_INT:MUX.OMUX3.S[2]

BUFGMUX0:DISABLE_ATTR	0.0.11
BUFGMUX1:DISABLE_ATTR	0.0.31
BUFGMUX2:DISABLE_ATTR	0.0.45
BUFGMUX3:DISABLE_ATTR	0.0.1
LOW	0
HIGH	1

BUFGMUX0:MUX.CLK	0.0.14	0.0.13	0.0.12	0.0.15
BUFGMUX1:MUX.CLK	0.0.34	0.0.33	0.0.32	0.0.35
BUFGMUX2:MUX.CLK	0.0.48	0.0.47	0.0.46	0.0.49
BUFGMUX3:MUX.CLK	0.0.52	0.0.51	0.0.50	0.0.53
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.CLK.IMUX.SEL0	0.0.2
CLK_INT:INV.0.CLK.IMUX.SEL1	0.0.22
CLK_INT:INV.0.CLK.IMUX.SEL2	0.0.36
CLK_INT:INV.0.CLK.IMUX.SEL3	0.0.62
inverted	~[0]

CLK_INT:MUX.CLK.IMUX.CLK0	0.0.9	0.0.10	0.0.7	0.0.6
CLK_INT:MUX.CLK.IMUX.SEL0	0.0.4	0.0.3	0.0.8	0.0.5
PULLUP	0	0	0	0
DBL.W0.2	0	0	0	1
DBL.W1.2	0	0	1	0
DBL.W0.1	0	1	0	1
DBL.W1.1	0	1	1	0
DBL.E0.1	1	0	0	1
DBL.E1.1	1	0	1	0
DBL.E0.0	1	1	0	1
DBL.E1.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK1	0.0.29	0.0.30	0.0.27	0.0.26
CLK_INT:MUX.CLK.IMUX.SEL1	0.0.24	0.0.23	0.0.28	0.0.25
PULLUP	0	0	0	0
DBL.W2.2	0	0	0	1
DBL.W3.2	0	0	1	0
DBL.W2.1	0	1	0	1
DBL.W3.1	0	1	1	0
DBL.E2.1	1	0	0	1
DBL.E3.1	1	0	1	0
DBL.E2.0	1	1	0	1
DBL.E3.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK2	0.0.43	0.0.44	0.0.41	0.0.40
CLK_INT:MUX.CLK.IMUX.SEL2	0.0.38	0.0.37	0.0.42	0.0.39
PULLUP	0	0	0	0
DBL.W4.2	0	0	0	1
DBL.W5.2	0	0	1	0
DBL.W4.1	0	1	0	1
DBL.W5.1	0	1	1	0
DBL.E4.1	1	0	0	1
DBL.E5.1	1	0	1	0
DBL.E4.0	1	1	0	1
DBL.E5.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK3	0.0.54	0.0.55	0.0.58	0.0.57
CLK_INT:MUX.CLK.IMUX.SEL3	0.0.61	0.0.60	0.0.59	0.0.56
PULLUP	0	0	0	0
DBL.W6.2	0	0	0	1
DBL.W7.2	0	0	1	0
DBL.W6.1	0	1	0	1
DBL.W7.1	0	1	1	0
DBL.E6.1	1	0	0	1
DBL.E7.1	1	0	1	0
DBL.E6.0	1	1	0	1
DBL.E7.0	1	1	1	0

CLK_INT:MUX.OMUX0.S	1.0.3	1.0.2	0.0.63
CLK_INT:MUX.OMUX3.S	1.0.0	1.0.4	1.0.1
CLK_INT:MUX.OMUX4.S	0.0.19	0.0.18	0.0.21
CLK_INT:MUX.OMUX5.S	0.0.16	0.0.17	0.0.20
NONE	0	0	0
CLK.OUT.2	0	0	1
CLK.OUT.3	0	1	0
CLK.OUT.0	1	0	1
CLK.OUT.1	1	1	0

`CLKT.S3E`

This tile is used on Spartan 3E.

Tile CLKT.S3E

Cells: 1

Bel CLK_INT

Switchbox CLK_INT

spartan3 CLKT.S3E switchbox CLK_INT
Destination	Source	Kind
OMUX0.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX3.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX4.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX5.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
CLK.IMUX.SEL0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.SEL1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.SEL2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.SEL3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux
CLK.IMUX.CLK0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.CLK1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.CLK2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.CLK3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux

Bel BUFGMUX0

spartan3 CLKT.S3E bel BUFGMUX0
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK0
O	output	CLK.OUT.0
S	input	CLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKT.S3E bel BUFGMUX1
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK1
O	output	CLK.OUT.1
S	input	CLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKT.S3E bel BUFGMUX2
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK2
O	output	CLK.OUT.2
S	input	CLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKT.S3E bel BUFGMUX3
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK3
O	output	CLK.OUT.3
S	input	CLK.IMUX.SEL3

Bel GLOBALSIG_N

spartan3 CLKT.S3E bel GLOBALSIG_N
Pin	Direction	Wires

Bel wires

spartan3 CLKT.S3E bel wires
Wire	Pins
CLK.IMUX.SEL0	BUFGMUX0.S
CLK.IMUX.SEL1	BUFGMUX1.S
CLK.IMUX.SEL2	BUFGMUX2.S
CLK.IMUX.SEL3	BUFGMUX3.S
CLK.IMUX.CLK0	BUFGMUX0.CLK
CLK.IMUX.CLK1	BUFGMUX1.CLK
CLK.IMUX.CLK2	BUFGMUX2.CLK
CLK.IMUX.CLK3	BUFGMUX3.CLK
CLK.OUT.0	BUFGMUX0.O
CLK.OUT.1	BUFGMUX1.O
CLK.OUT.2	BUFGMUX2.O
CLK.OUT.3	BUFGMUX3.O

Bitstream

spartan3 CLKT.S3E bittile 0
Bit	Frame
Bit	0
63	CLK_INT:MUX.CLK.IMUX.SEL3[1]
62	CLK_INT:MUX.CLK.IMUX.CLK3[1]
61	CLK_INT:MUX.CLK.IMUX.CLK3[0]
60	CLK_INT:MUX.CLK.IMUX.SEL3[0]
59	CLK_INT:MUX.CLK.IMUX.CLK3[2]
58	CLK_INT:MUX.CLK.IMUX.CLK3[3]
57	BUFGMUX3:MUX.CLK[0]
56	BUFGMUX3:MUX.CLK[4]
55	BUFGMUX3:MUX.CLK[3]
54	BUFGMUX3:MUX.CLK[1]
53	BUFGMUX3:MUX.CLK[2]
52	BUFGMUX2:MUX.CLK[0]
51	BUFGMUX2:MUX.CLK[4]
50	BUFGMUX2:MUX.CLK[3]
49	BUFGMUX2:MUX.CLK[1]
48	BUFGMUX2:MUX.CLK[2]
47	CLK_INT:MUX.CLK.IMUX.CLK2[3]
46	CLK_INT:MUX.CLK.IMUX.CLK2[2]
45	CLK_INT:MUX.CLK.IMUX.SEL2[1]
44	CLK_INT:MUX.CLK.IMUX.CLK2[1]
43	CLK_INT:MUX.CLK.IMUX.CLK2[0]
42	CLK_INT:MUX.CLK.IMUX.SEL2[0]
41	CLK_INT:MUX.CLK.IMUX.SEL2[2]
40	CLK_INT:MUX.CLK.IMUX.SEL2[3]
39	~CLK_INT:INV.0.CLK.IMUX.SEL2
38	BUFGMUX2:DISABLE_ATTR[0]
37	BUFGMUX1:MUX.CLK[0]
36	BUFGMUX1:MUX.CLK[4]
35	BUFGMUX1:MUX.CLK[3]
34	BUFGMUX1:MUX.CLK[1]
33	BUFGMUX1:MUX.CLK[2]
32	BUFGMUX1:DISABLE_ATTR[0]
31	CLK_INT:MUX.CLK.IMUX.CLK1[3]
30	CLK_INT:MUX.CLK.IMUX.CLK1[2]
29	CLK_INT:MUX.CLK.IMUX.SEL1[1]
28	CLK_INT:MUX.CLK.IMUX.CLK1[1]
27	CLK_INT:MUX.CLK.IMUX.CLK1[0]
26	CLK_INT:MUX.CLK.IMUX.SEL1[0]
25	CLK_INT:MUX.CLK.IMUX.SEL1[2]
24	CLK_INT:MUX.CLK.IMUX.SEL1[3]
23	~CLK_INT:INV.0.CLK.IMUX.SEL1
22	CLK_INT:MUX.OMUX4.S[0]
21	CLK_INT:MUX.OMUX5.S[0]
20	CLK_INT:MUX.OMUX4.S[2]
19	CLK_INT:MUX.OMUX4.S[1]
18	CLK_INT:MUX.OMUX5.S[1]
17	CLK_INT:MUX.OMUX5.S[2]
16	BUFGMUX0:MUX.CLK[0]
15	BUFGMUX0:MUX.CLK[4]
14	BUFGMUX0:MUX.CLK[3]
13	BUFGMUX0:MUX.CLK[1]
12	BUFGMUX0:MUX.CLK[2]
11	BUFGMUX0:DISABLE_ATTR[0]
10	CLK_INT:MUX.CLK.IMUX.CLK0[3]
9	CLK_INT:MUX.CLK.IMUX.CLK0[2]
8	CLK_INT:MUX.CLK.IMUX.SEL0[1]
7	CLK_INT:MUX.CLK.IMUX.CLK0[1]
6	CLK_INT:MUX.CLK.IMUX.CLK0[0]
5	CLK_INT:MUX.CLK.IMUX.SEL0[0]
4	CLK_INT:MUX.CLK.IMUX.SEL0[2]
3	CLK_INT:MUX.CLK.IMUX.SEL0[3]
2	~CLK_INT:INV.0.CLK.IMUX.SEL0
1	BUFGMUX3:DISABLE_ATTR[0]
0	-

spartan3 CLKT.S3E bittile 1
Bit	Frame
Bit	0
8	CLK_INT:MUX.OMUX3.S[0]
7	CLK_INT:MUX.OMUX0.S[1]
6	CLK_INT:MUX.OMUX0.S[2]
5	CLK_INT:MUX.OMUX3.S[1]
4	CLK_INT:MUX.OMUX3.S[2]
3	CLK_INT:MUX.OMUX0.S[0]
2	~CLK_INT:INV.0.CLK.IMUX.SEL3
1	CLK_INT:MUX.CLK.IMUX.SEL3[3]
0	CLK_INT:MUX.CLK.IMUX.SEL3[2]

BUFGMUX0:DISABLE_ATTR	0.0.11
BUFGMUX1:DISABLE_ATTR	0.0.32
BUFGMUX2:DISABLE_ATTR	0.0.38
BUFGMUX3:DISABLE_ATTR	0.0.1
LOW	0
HIGH	1

BUFGMUX0:MUX.CLK	0.0.15	0.0.14	0.0.12	0.0.13	0.0.16
BUFGMUX1:MUX.CLK	0.0.36	0.0.35	0.0.33	0.0.34	0.0.37
BUFGMUX2:MUX.CLK	0.0.51	0.0.50	0.0.48	0.0.49	0.0.52
BUFGMUX3:MUX.CLK	0.0.56	0.0.55	0.0.53	0.0.54	0.0.57
INT	0	0	0	0	1
CKIL	0	0	0	1	0
CKIR	0	0	1	0	0
DCM_OUT_L	0	1	0	0	0
DCM_OUT_R	1	0	0	0	0

CLK_INT:INV.0.CLK.IMUX.SEL0	0.0.2
CLK_INT:INV.0.CLK.IMUX.SEL1	0.0.23
CLK_INT:INV.0.CLK.IMUX.SEL2	0.0.39
CLK_INT:INV.0.CLK.IMUX.SEL3	1.0.2
inverted	~[0]

CLK_INT:MUX.CLK.IMUX.CLK0	0.0.10	0.0.9	0.0.7	0.0.6
CLK_INT:MUX.CLK.IMUX.SEL0	0.0.3	0.0.4	0.0.8	0.0.5
PULLUP	0	0	0	0
DBL.W0.2	0	0	0	1
DBL.W1.2	0	0	1	0
DBL.W0.1	0	1	0	1
DBL.W1.1	0	1	1	0
DBL.E0.1	1	0	0	1
DBL.E1.1	1	0	1	0
DBL.E0.0	1	1	0	1
DBL.E1.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK1	0.0.31	0.0.30	0.0.28	0.0.27
CLK_INT:MUX.CLK.IMUX.SEL1	0.0.24	0.0.25	0.0.29	0.0.26
PULLUP	0	0	0	0
DBL.W2.2	0	0	0	1
DBL.W3.2	0	0	1	0
DBL.W2.1	0	1	0	1
DBL.W3.1	0	1	1	0
DBL.E2.1	1	0	0	1
DBL.E3.1	1	0	1	0
DBL.E2.0	1	1	0	1
DBL.E3.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK2	0.0.47	0.0.46	0.0.44	0.0.43
CLK_INT:MUX.CLK.IMUX.SEL2	0.0.40	0.0.41	0.0.45	0.0.42
PULLUP	0	0	0	0
DBL.W4.2	0	0	0	1
DBL.W5.2	0	0	1	0
DBL.W4.1	0	1	0	1
DBL.W5.1	0	1	1	0
DBL.E4.1	1	0	0	1
DBL.E5.1	1	0	1	0
DBL.E4.0	1	1	0	1
DBL.E5.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK3	0.0.58	0.0.59	0.0.62	0.0.61
CLK_INT:MUX.CLK.IMUX.SEL3	1.0.1	1.0.0	0.0.63	0.0.60
PULLUP	0	0	0	0
DBL.W6.2	0	0	0	1
DBL.W7.2	0	0	1	0
DBL.W6.1	0	1	0	1
DBL.W7.1	0	1	1	0
DBL.E6.1	1	0	0	1
DBL.E7.1	1	0	1	0
DBL.E6.0	1	1	0	1
DBL.E7.0	1	1	1	0

CLK_INT:MUX.OMUX0.S	1.0.6	1.0.7	1.0.3
CLK_INT:MUX.OMUX3.S	1.0.4	1.0.5	1.0.8
CLK_INT:MUX.OMUX4.S	0.0.20	0.0.19	0.0.22
CLK_INT:MUX.OMUX5.S	0.0.17	0.0.18	0.0.21
NONE	0	0	0
CLK.OUT.2	0	0	1
CLK.OUT.3	0	1	0
CLK.OUT.0	1	0	1
CLK.OUT.1	1	1	0

`CLKT.S3A`

This tile is used on Spartan 3A and 3A DSP.

Tile CLKT.S3A

Cells: 1

Bel CLK_INT

Switchbox CLK_INT

spartan3 CLKT.S3A switchbox CLK_INT
Destination	Source	Kind
OMUX0.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX3.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX4.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
OMUX5.S	CLK.OUT.0	mux
	CLK.OUT.1	mux
	CLK.OUT.2	mux
	CLK.OUT.3	mux
CLK.IMUX.SEL0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.SEL1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.SEL2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.SEL3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux
CLK.IMUX.CLK0	PULLUP	mux
	DBL.W0.1	mux
	DBL.W0.2	mux
	DBL.W1.1	mux
	DBL.W1.2	mux
	DBL.E0.0	mux
	DBL.E0.1	mux
	DBL.E1.0	mux
	DBL.E1.1	mux
CLK.IMUX.CLK1	PULLUP	mux
	DBL.W2.1	mux
	DBL.W2.2	mux
	DBL.W3.1	mux
	DBL.W3.2	mux
	DBL.E2.0	mux
	DBL.E2.1	mux
	DBL.E3.0	mux
	DBL.E3.1	mux
CLK.IMUX.CLK2	PULLUP	mux
	DBL.W4.1	mux
	DBL.W4.2	mux
	DBL.W5.1	mux
	DBL.W5.2	mux
	DBL.E4.0	mux
	DBL.E4.1	mux
	DBL.E5.0	mux
	DBL.E5.1	mux
CLK.IMUX.CLK3	PULLUP	mux
	DBL.W6.1	mux
	DBL.W6.2	mux
	DBL.W7.1	mux
	DBL.W7.2	mux
	DBL.E6.0	mux
	DBL.E6.1	mux
	DBL.E7.0	mux
	DBL.E7.1	mux

Bel BUFGMUX0

spartan3 CLKT.S3A bel BUFGMUX0
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK0
O	output	CLK.OUT.0
S	input	CLK.IMUX.SEL0

Bel BUFGMUX1

spartan3 CLKT.S3A bel BUFGMUX1
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK1
O	output	CLK.OUT.1
S	input	CLK.IMUX.SEL1

Bel BUFGMUX2

spartan3 CLKT.S3A bel BUFGMUX2
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK2
O	output	CLK.OUT.2
S	input	CLK.IMUX.SEL2

Bel BUFGMUX3

spartan3 CLKT.S3A bel BUFGMUX3
Pin	Direction	Wires
CLK	input	CLK.IMUX.CLK3
O	output	CLK.OUT.3
S	input	CLK.IMUX.SEL3

Bel GLOBALSIG_N

spartan3 CLKT.S3A bel GLOBALSIG_N
Pin	Direction	Wires

Bel wires

spartan3 CLKT.S3A bel wires
Wire	Pins
CLK.IMUX.SEL0	BUFGMUX0.S
CLK.IMUX.SEL1	BUFGMUX1.S
CLK.IMUX.SEL2	BUFGMUX2.S
CLK.IMUX.SEL3	BUFGMUX3.S
CLK.IMUX.CLK0	BUFGMUX0.CLK
CLK.IMUX.CLK1	BUFGMUX1.CLK
CLK.IMUX.CLK2	BUFGMUX2.CLK
CLK.IMUX.CLK3	BUFGMUX3.CLK
CLK.OUT.0	BUFGMUX0.O
CLK.OUT.1	BUFGMUX1.O
CLK.OUT.2	BUFGMUX2.O
CLK.OUT.3	BUFGMUX3.O

Bitstream

spartan3 CLKT.S3A bittile 0
Bit	Frame
Bit	0
63	CLK_INT:MUX.CLK.IMUX.SEL3[1]
62	CLK_INT:MUX.CLK.IMUX.CLK3[1]
61	CLK_INT:MUX.CLK.IMUX.CLK3[0]
60	CLK_INT:MUX.CLK.IMUX.SEL3[0]
59	CLK_INT:MUX.CLK.IMUX.CLK3[2]
58	CLK_INT:MUX.CLK.IMUX.CLK3[3]
57	BUFGMUX3:MUX.CLK[0]
56	BUFGMUX3:MUX.CLK[4]
55	BUFGMUX3:MUX.CLK[3]
54	BUFGMUX3:MUX.CLK[1]
53	BUFGMUX3:MUX.CLK[2]
52	BUFGMUX2:MUX.CLK[0]
51	BUFGMUX2:MUX.CLK[4]
50	BUFGMUX2:MUX.CLK[3]
49	BUFGMUX2:MUX.CLK[1]
48	BUFGMUX2:MUX.CLK[2]
47	CLK_INT:MUX.CLK.IMUX.CLK2[3]
46	CLK_INT:MUX.CLK.IMUX.CLK2[2]
45	CLK_INT:MUX.CLK.IMUX.SEL2[0]
44	CLK_INT:MUX.CLK.IMUX.CLK2[0]
43	CLK_INT:MUX.CLK.IMUX.CLK2[1]
42	CLK_INT:MUX.CLK.IMUX.SEL2[1]
41	CLK_INT:MUX.CLK.IMUX.SEL2[2]
40	CLK_INT:MUX.CLK.IMUX.SEL2[3]
39	~CLK_INT:INV.0.CLK.IMUX.SEL2
38	BUFGMUX2:DISABLE_ATTR[0]
37	BUFGMUX1:MUX.CLK[0]
36	BUFGMUX1:MUX.CLK[4]
35	BUFGMUX1:MUX.CLK[3]
34	BUFGMUX1:MUX.CLK[1]
33	BUFGMUX1:MUX.CLK[2]
32	BUFGMUX1:DISABLE_ATTR[0]
31	CLK_INT:MUX.CLK.IMUX.CLK1[3]
30	CLK_INT:MUX.CLK.IMUX.CLK1[2]
29	CLK_INT:MUX.CLK.IMUX.SEL1[0]
28	CLK_INT:MUX.CLK.IMUX.CLK1[0]
27	CLK_INT:MUX.CLK.IMUX.CLK1[1]
26	CLK_INT:MUX.CLK.IMUX.SEL1[1]
25	CLK_INT:MUX.CLK.IMUX.SEL1[2]
24	CLK_INT:MUX.CLK.IMUX.SEL1[3]
23	~CLK_INT:INV.0.CLK.IMUX.SEL1
22	CLK_INT:MUX.OMUX4.S[0]
21	CLK_INT:MUX.OMUX5.S[0]
20	CLK_INT:MUX.OMUX4.S[2]
19	CLK_INT:MUX.OMUX4.S[1]
18	CLK_INT:MUX.OMUX5.S[1]
17	CLK_INT:MUX.OMUX5.S[2]
16	BUFGMUX0:MUX.CLK[0]
15	BUFGMUX0:MUX.CLK[4]
14	BUFGMUX0:MUX.CLK[3]
13	BUFGMUX0:MUX.CLK[1]
12	BUFGMUX0:MUX.CLK[2]
11	BUFGMUX0:DISABLE_ATTR[0]
10	CLK_INT:MUX.CLK.IMUX.CLK0[3]
9	CLK_INT:MUX.CLK.IMUX.CLK0[2]
8	CLK_INT:MUX.CLK.IMUX.SEL0[1]
7	CLK_INT:MUX.CLK.IMUX.CLK0[1]
6	CLK_INT:MUX.CLK.IMUX.CLK0[0]
5	CLK_INT:MUX.CLK.IMUX.SEL0[0]
4	CLK_INT:MUX.CLK.IMUX.SEL0[2]
3	CLK_INT:MUX.CLK.IMUX.SEL0[3]
2	~CLK_INT:INV.0.CLK.IMUX.SEL0
1	BUFGMUX3:DISABLE_ATTR[0]
0	-

spartan3 CLKT.S3A bittile 1
Bit	Frame
Bit	0	1
5	-	CLK_INT:MUX.OMUX3.S[1]
4	-	CLK_INT:MUX.OMUX3.S[2]
3	-	CLK_INT:MUX.OMUX0.S[0]
2	~CLK_INT:INV.0.CLK.IMUX.SEL3	CLK_INT:MUX.OMUX0.S[2]
1	CLK_INT:MUX.CLK.IMUX.SEL3[3]	CLK_INT:MUX.OMUX3.S[0]
0	CLK_INT:MUX.CLK.IMUX.SEL3[2]	CLK_INT:MUX.OMUX0.S[1]

BUFGMUX0:DISABLE_ATTR	0.0.11
BUFGMUX1:DISABLE_ATTR	0.0.32
BUFGMUX2:DISABLE_ATTR	0.0.38
BUFGMUX3:DISABLE_ATTR	0.0.1
LOW	0
HIGH	1

BUFGMUX0:MUX.CLK	0.0.15	0.0.14	0.0.12	0.0.13	0.0.16
BUFGMUX1:MUX.CLK	0.0.36	0.0.35	0.0.33	0.0.34	0.0.37
BUFGMUX2:MUX.CLK	0.0.51	0.0.50	0.0.48	0.0.49	0.0.52
BUFGMUX3:MUX.CLK	0.0.56	0.0.55	0.0.53	0.0.54	0.0.57
INT	0	0	0	0	1
CKIL	0	0	0	1	0
CKIR	0	0	1	0	0
DCM_OUT_L	0	1	0	0	0
DCM_OUT_R	1	0	0	0	0

CLK_INT:INV.0.CLK.IMUX.SEL0	0.0.2
CLK_INT:INV.0.CLK.IMUX.SEL1	0.0.23
CLK_INT:INV.0.CLK.IMUX.SEL2	0.0.39
CLK_INT:INV.0.CLK.IMUX.SEL3	1.0.2
inverted	~[0]

CLK_INT:MUX.CLK.IMUX.CLK0	0.0.10	0.0.9	0.0.7	0.0.6
CLK_INT:MUX.CLK.IMUX.SEL0	0.0.3	0.0.4	0.0.8	0.0.5
PULLUP	0	0	0	0
DBL.W0.2	0	0	0	1
DBL.W1.2	0	0	1	0
DBL.W0.1	0	1	0	1
DBL.W1.1	0	1	1	0
DBL.E0.1	1	0	0	1
DBL.E1.1	1	0	1	0
DBL.E0.0	1	1	0	1
DBL.E1.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK1	0.0.31	0.0.30	0.0.27	0.0.28
CLK_INT:MUX.CLK.IMUX.SEL1	0.0.24	0.0.25	0.0.26	0.0.29
PULLUP	0	0	0	0
DBL.W2.2	0	0	0	1
DBL.W3.2	0	0	1	0
DBL.W2.1	0	1	0	1
DBL.W3.1	0	1	1	0
DBL.E2.1	1	0	0	1
DBL.E3.1	1	0	1	0
DBL.E2.0	1	1	0	1
DBL.E3.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK2	0.0.47	0.0.46	0.0.43	0.0.44
CLK_INT:MUX.CLK.IMUX.SEL2	0.0.40	0.0.41	0.0.42	0.0.45
PULLUP	0	0	0	0
DBL.W4.2	0	0	0	1
DBL.W5.2	0	0	1	0
DBL.W4.1	0	1	0	1
DBL.W5.1	0	1	1	0
DBL.E4.1	1	0	0	1
DBL.E5.1	1	0	1	0
DBL.E4.0	1	1	0	1
DBL.E5.0	1	1	1	0

CLK_INT:MUX.CLK.IMUX.CLK3	0.0.58	0.0.59	0.0.62	0.0.61
CLK_INT:MUX.CLK.IMUX.SEL3	1.0.1	1.0.0	0.0.63	0.0.60
PULLUP	0	0	0	0
DBL.W6.2	0	0	0	1
DBL.W7.2	0	0	1	0
DBL.W6.1	0	1	0	1
DBL.W7.1	0	1	1	0
DBL.E6.1	1	0	0	1
DBL.E7.1	1	0	1	0
DBL.E6.0	1	1	0	1
DBL.E7.0	1	1	1	0

CLK_INT:MUX.OMUX0.S	1.1.2	1.1.0	1.1.3
CLK_INT:MUX.OMUX3.S	1.1.4	1.1.5	1.1.1
CLK_INT:MUX.OMUX4.S	0.0.20	0.0.19	0.0.22
CLK_INT:MUX.OMUX5.S	0.0.17	0.0.18	0.0.21
NONE	0	0	0
CLK.OUT.2	0	0	1
CLK.OUT.3	0	1	0
CLK.OUT.0	1	0	1
CLK.OUT.1	1	1	0

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