Primary global buffers

TODO: document

Bitstream — south tiles

The CLK_S_* tiles use two bitstream tiles:

tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the bottom interconnect row
tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the low special area (used for bottom IOB tiles and clock rows in normal columns)

On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH_S_S3A tile.

`CLK_S_S3`

This tile is used on Spartan 3.

Tile CLK_S_S3

Cells: 1

Switchbox CLK_INT

spartan3 CLK_S_S3 switchbox CLK_INT muxes OMUX_N10
Bits	Destination
OMUX_N10
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes OMUX_N11
Bits	Destination
OMUX_N11
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes OMUX_N12
Bits	Destination
OMUX_N12
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes OMUX_N15
Bits	Destination
OMUX_N15
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
IMUX_BUFG_CLK[0]
	Source
DBL_E1[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
IMUX_BUFG_CLK[1]
	Source
DBL_E1[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
IMUX_BUFG_CLK[2]
	Source
DBL_E1[5]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
IMUX_BUFG_CLK[3]
	Source
DBL_E1[7]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
IMUX_BUFG_SEL[0]
	Source
DBL_E1[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
IMUX_BUFG_SEL[1]
	Source
DBL_E1[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
IMUX_BUFG_SEL[2]
	Source
DBL_E1[5]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
IMUX_BUFG_SEL[3]
	Source
DBL_E1[7]

Bel BUFGMUX[0]

spartan3 CLK_S_S3 bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[0]
O	output	OUT_BUFG[0]
S	input	IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

spartan3 CLK_S_S3 bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[1]
O	output	OUT_BUFG[1]
S	input	IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

spartan3 CLK_S_S3 bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[2]
O	output	OUT_BUFG[2]
S	input	IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

spartan3 CLK_S_S3 bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[3]
O	output	OUT_BUFG[3]
S	input	IMUX_BUFG_SEL[3]

Bel GLOBALSIG_S[0]

spartan3 CLK_S_S3 bel GLOBALSIG_S[0]
Pin	Direction	Wires

Bel wires

spartan3 CLK_S_S3 bel wires
Wire	Pins
IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
IMUX_BUFG_SEL[0]	BUFGMUX[0].S
IMUX_BUFG_SEL[1]	BUFGMUX[1].S
IMUX_BUFG_SEL[2]	BUFGMUX[2].S
IMUX_BUFG_SEL[3]	BUFGMUX[3].S
OUT_BUFG[0]	BUFGMUX[0].O
OUT_BUFG[1]	BUFGMUX[1].O
OUT_BUFG[2]	BUFGMUX[2].O
OUT_BUFG[3]	BUFGMUX[3].O

Bitstream

spartan3 CLK_S_S3 rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_S_S3 rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

spartan3 CLK_S_S3 rect R0
Bit	Frame
Bit	F0
B62	BUFGMUX[0]:DISABLE_ATTR[0]
B61	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]
B60	CLK_INT:MUX.IMUX_BUFG_SEL[3][2]
B59	CLK_INT:MUX.IMUX_BUFG_SEL[3][3]
B58	CLK_INT:MUX.IMUX_BUFG_SEL[3][1]
B57	CLK_INT:MUX.IMUX_BUFG_CLK[3][1]
B56	CLK_INT:MUX.IMUX_BUFG_CLK[3][0]
B55	CLK_INT:MUX.IMUX_BUFG_SEL[3][0]
B54	CLK_INT:MUX.IMUX_BUFG_CLK[3][3]
B53	CLK_INT:MUX.IMUX_BUFG_CLK[3][2]
B52	BUFGMUX[3]:DISABLE_ATTR[0]
B51	BUFGMUX[3]:MUX.CLK[1]
B50	BUFGMUX[3]:MUX.CLK[2]
B49	BUFGMUX[3]:MUX.CLK[3]
B48	BUFGMUX[3]:MUX.CLK[0]
B47	CLK_INT:MUX.OMUX_N15[2]
B46	CLK_INT:MUX.OMUX_N15[1]
B45	CLK_INT:MUX.OMUX_N12[1]
B44	CLK_INT:MUX.OMUX_N12[2]
B43	CLK_INT:MUX.OMUX_N15[0]
B42	CLK_INT:MUX.OMUX_N12[0]
B41	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]
B40	CLK_INT:MUX.IMUX_BUFG_SEL[2][2]
B39	CLK_INT:MUX.IMUX_BUFG_SEL[2][3]
B38	CLK_INT:MUX.IMUX_BUFG_SEL[2][1]
B37	CLK_INT:MUX.IMUX_BUFG_CLK[2][1]
B36	CLK_INT:MUX.IMUX_BUFG_CLK[2][0]
B35	CLK_INT:MUX.IMUX_BUFG_SEL[2][0]
B34	CLK_INT:MUX.IMUX_BUFG_CLK[2][3]
B33	CLK_INT:MUX.IMUX_BUFG_CLK[2][2]
B32	BUFGMUX[2]:DISABLE_ATTR[0]
B31	BUFGMUX[2]:MUX.CLK[1]
B30	BUFGMUX[2]:MUX.CLK[2]
B29	BUFGMUX[2]:MUX.CLK[3]
B28	BUFGMUX[2]:MUX.CLK[0]
B27	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]
B26	CLK_INT:MUX.IMUX_BUFG_SEL[1][2]
B25	CLK_INT:MUX.IMUX_BUFG_SEL[1][3]
B24	CLK_INT:MUX.IMUX_BUFG_SEL[1][1]
B23	CLK_INT:MUX.IMUX_BUFG_CLK[1][1]
B22	CLK_INT:MUX.IMUX_BUFG_CLK[1][0]
B21	CLK_INT:MUX.IMUX_BUFG_SEL[1][0]
B20	CLK_INT:MUX.IMUX_BUFG_CLK[1][3]
B19	CLK_INT:MUX.IMUX_BUFG_CLK[1][2]
B18	BUFGMUX[1]:DISABLE_ATTR[0]
B17	BUFGMUX[1]:MUX.CLK[1]
B16	BUFGMUX[1]:MUX.CLK[2]
B15	BUFGMUX[1]:MUX.CLK[3]
B14	BUFGMUX[1]:MUX.CLK[0]
B13	BUFGMUX[0]:MUX.CLK[1]
B12	BUFGMUX[0]:MUX.CLK[2]
B11	BUFGMUX[0]:MUX.CLK[3]
B10	BUFGMUX[0]:MUX.CLK[0]
B9	CLK_INT:MUX.IMUX_BUFG_CLK[0][3]
B8	CLK_INT:MUX.IMUX_BUFG_CLK[0][2]
B7	CLK_INT:MUX.IMUX_BUFG_SEL[0][1]
B6	CLK_INT:MUX.IMUX_BUFG_CLK[0][1]
B5	CLK_INT:MUX.IMUX_BUFG_CLK[0][0]
B4	CLK_INT:MUX.IMUX_BUFG_SEL[0][0]
B3	CLK_INT:MUX.IMUX_BUFG_SEL[0][2]
B2	CLK_INT:MUX.IMUX_BUFG_SEL[0][3]
B1	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]
B0	CLK_INT:MUX.OMUX_N10[0]

spartan3 CLK_S_S3 rect R1
Bit	Frame
Bit	F0
B11	CLK_INT:MUX.OMUX_N11[2]
B10	CLK_INT:MUX.OMUX_N11[0]
B9	CLK_INT:MUX.OMUX_N10[1]
B8	CLK_INT:MUX.OMUX_N10[2]
B7	CLK_INT:MUX.OMUX_N11[1]
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

BUFGMUX[0]:DISABLE_ATTR	0.F0.B62
BUFGMUX[1]:DISABLE_ATTR	0.F0.B18
BUFGMUX[2]:DISABLE_ATTR	0.F0.B32
BUFGMUX[3]:DISABLE_ATTR	0.F0.B52
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B11	0.F0.B12	0.F0.B13	0.F0.B10
BUFGMUX[1]:MUX.CLK	0.F0.B15	0.F0.B16	0.F0.B17	0.F0.B14
BUFGMUX[2]:MUX.CLK	0.F0.B29	0.F0.B30	0.F0.B31	0.F0.B28
BUFGMUX[3]:MUX.CLK	0.F0.B49	0.F0.B50	0.F0.B51	0.F0.B48
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F0.B1
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F0.B27
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F0.B41
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	0.F0.B61
inverted	~[0]

CLK_INT:MUX.IMUX_BUFG_CLK[0]	0.F0.B9	0.F0.B8	0.F0.B6	0.F0.B5
CLK_INT:MUX.IMUX_BUFG_SEL[0]	0.F0.B2	0.F0.B3	0.F0.B7	0.F0.B4
PULLUP	0	0	0	0
DBL_W2[0]	0	0	0	1
DBL_W2[1]	0	0	1	0
DBL_W1[0]	0	1	0	1
DBL_W1[1]	0	1	1	0
DBL_E1[0]	1	0	0	1
DBL_E1[1]	1	0	1	0
DBL_E0[0]	1	1	0	1
DBL_E0[1]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[1]	0.F0.B20	0.F0.B19	0.F0.B23	0.F0.B22
CLK_INT:MUX.IMUX_BUFG_SEL[1]	0.F0.B25	0.F0.B26	0.F0.B24	0.F0.B21
PULLUP	0	0	0	0
DBL_W2[2]	0	0	0	1
DBL_W2[3]	0	0	1	0
DBL_W1[2]	0	1	0	1
DBL_W1[3]	0	1	1	0
DBL_E1[2]	1	0	0	1
DBL_E1[3]	1	0	1	0
DBL_E0[2]	1	1	0	1
DBL_E0[3]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[2]	0.F0.B34	0.F0.B33	0.F0.B37	0.F0.B36
CLK_INT:MUX.IMUX_BUFG_SEL[2]	0.F0.B39	0.F0.B40	0.F0.B38	0.F0.B35
PULLUP	0	0	0	0
DBL_W2[4]	0	0	0	1
DBL_W2[5]	0	0	1	0
DBL_W1[4]	0	1	0	1
DBL_W1[5]	0	1	1	0
DBL_E1[4]	1	0	0	1
DBL_E1[5]	1	0	1	0
DBL_E0[4]	1	1	0	1
DBL_E0[5]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[3]	0.F0.B54	0.F0.B53	0.F0.B57	0.F0.B56
CLK_INT:MUX.IMUX_BUFG_SEL[3]	0.F0.B59	0.F0.B60	0.F0.B58	0.F0.B55
PULLUP	0	0	0	0
DBL_W2[6]	0	0	0	1
DBL_W2[7]	0	0	1	0
DBL_W1[6]	0	1	0	1
DBL_W1[7]	0	1	1	0
DBL_E1[6]	1	0	0	1
DBL_E1[7]	1	0	1	0
DBL_E0[6]	1	1	0	1
DBL_E0[7]	1	1	1	0

CLK_INT:MUX.OMUX_N10	1.F0.B8	1.F0.B9	0.F0.B0
CLK_INT:MUX.OMUX_N11	1.F0.B11	1.F0.B7	1.F0.B10
CLK_INT:MUX.OMUX_N12	0.F0.B44	0.F0.B45	0.F0.B42
CLK_INT:MUX.OMUX_N15	0.F0.B47	0.F0.B46	0.F0.B43
NONE	0	0	0
OUT_BUFG[2]	0	0	1
OUT_BUFG[3]	0	1	0
OUT_BUFG[0]	1	0	1
OUT_BUFG[1]	1	1	0

`CLK_S_FC`

This tile is used on FPGAcore.

Tile CLK_S_FC

Cells: 1

Switchbox CLK_INT

spartan3 CLK_S_FC switchbox CLK_INT muxes OMUX_N10
Bits	Destination
OMUX_N10
	Source
OUT_BUFG[3]

spartan3 CLK_S_FC switchbox CLK_INT muxes OMUX_N11
Bits	Destination
OMUX_N11
	Source
OUT_BUFG[3]

spartan3 CLK_S_FC switchbox CLK_INT muxes OMUX_N12
Bits	Destination
OMUX_N12
	Source
OUT_BUFG[3]

spartan3 CLK_S_FC switchbox CLK_INT muxes OMUX_N15
Bits	Destination
OMUX_N15
	Source
OUT_BUFG[3]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
IMUX_BUFG_CLK[0]
	Source
DBL_E1[1]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
IMUX_BUFG_CLK[1]
	Source
DBL_E1[3]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
IMUX_BUFG_CLK[2]
	Source
DBL_E1[5]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
IMUX_BUFG_CLK[3]
	Source
DBL_E1[7]

Bel BUFGMUX[0]

spartan3 CLK_S_FC bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[0]
O	output	OUT_BUFG[0]

Bel BUFGMUX[1]

spartan3 CLK_S_FC bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[1]
O	output	OUT_BUFG[1]

Bel BUFGMUX[2]

spartan3 CLK_S_FC bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[2]
O	output	OUT_BUFG[2]

Bel BUFGMUX[3]

spartan3 CLK_S_FC bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[3]
O	output	OUT_BUFG[3]

Bel GLOBALSIG_S[0]

spartan3 CLK_S_FC bel GLOBALSIG_S[0]
Pin	Direction	Wires

Bel wires

spartan3 CLK_S_FC bel wires
Wire	Pins
IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
OUT_BUFG[0]	BUFGMUX[0].O
OUT_BUFG[1]	BUFGMUX[1].O
OUT_BUFG[2]	BUFGMUX[2].O
OUT_BUFG[3]	BUFGMUX[3].O

Bitstream

spartan3 CLK_S_FC rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_S_FC rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

spartan3 CLK_S_FC rect R0
Bit	Frame
Bit	F0
B57	CLK_INT:MUX.IMUX_BUFG_CLK[3][1]
B56	CLK_INT:MUX.IMUX_BUFG_CLK[3][0]
B55	-
B54	CLK_INT:MUX.IMUX_BUFG_CLK[3][3]
B53	CLK_INT:MUX.IMUX_BUFG_CLK[3][2]
B52	-
B51	BUFGMUX[3]:MUX.CLK[1]
B50	-
B49	-
B48	BUFGMUX[3]:MUX.CLK[0]
B47	CLK_INT:MUX.OMUX_N15[2]
B46	CLK_INT:MUX.OMUX_N15[1]
B45	CLK_INT:MUX.OMUX_N12[1]
B44	CLK_INT:MUX.OMUX_N12[2]
B43	CLK_INT:MUX.OMUX_N15[0]
B42	CLK_INT:MUX.OMUX_N12[0]
B41	-
B40	-
B39	-
B38	-
B37	CLK_INT:MUX.IMUX_BUFG_CLK[2][1]
B36	CLK_INT:MUX.IMUX_BUFG_CLK[2][0]
B35	-
B34	CLK_INT:MUX.IMUX_BUFG_CLK[2][3]
B33	CLK_INT:MUX.IMUX_BUFG_CLK[2][2]
B32	-
B31	BUFGMUX[2]:MUX.CLK[1]
B30	-
B29	-
B28	BUFGMUX[2]:MUX.CLK[0]
B27	-
B26	-
B25	-
B24	-
B23	CLK_INT:MUX.IMUX_BUFG_CLK[1][1]
B22	CLK_INT:MUX.IMUX_BUFG_CLK[1][0]
B21	-
B20	CLK_INT:MUX.IMUX_BUFG_CLK[1][3]
B19	CLK_INT:MUX.IMUX_BUFG_CLK[1][2]
B18	-
B17	BUFGMUX[1]:MUX.CLK[1]
B16	-
B15	-
B14	BUFGMUX[1]:MUX.CLK[0]
B13	BUFGMUX[0]:MUX.CLK[1]
B12	-
B11	-
B10	BUFGMUX[0]:MUX.CLK[0]
B9	CLK_INT:MUX.IMUX_BUFG_CLK[0][3]
B8	CLK_INT:MUX.IMUX_BUFG_CLK[0][2]
B7	-
B6	CLK_INT:MUX.IMUX_BUFG_CLK[0][1]
B5	CLK_INT:MUX.IMUX_BUFG_CLK[0][0]
B4	-
B3	-
B2	-
B1	-
B0	CLK_INT:MUX.OMUX_N10[0]

spartan3 CLK_S_FC rect R1
Bit	Frame
Bit	F0
B11	CLK_INT:MUX.OMUX_N11[2]
B10	CLK_INT:MUX.OMUX_N11[0]
B9	CLK_INT:MUX.OMUX_N10[1]
B8	CLK_INT:MUX.OMUX_N10[2]
B7	CLK_INT:MUX.OMUX_N11[1]
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

BUFGMUX[0]:MUX.CLK	0.F0.B13	0.F0.B10
BUFGMUX[1]:MUX.CLK	0.F0.B17	0.F0.B14
BUFGMUX[2]:MUX.CLK	0.F0.B31	0.F0.B28
BUFGMUX[3]:MUX.CLK	0.F0.B51	0.F0.B48
INT	0	1
CKI	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[0]	0.F0.B9	0.F0.B8	0.F0.B6	0.F0.B5
PULLUP	0	0	0	0
DBL_W2[0]	0	0	0	1
DBL_W2[1]	0	0	1	0
DBL_W1[0]	0	1	0	1
DBL_W1[1]	0	1	1	0
DBL_E1[0]	1	0	0	1
DBL_E1[1]	1	0	1	0
DBL_E0[0]	1	1	0	1
DBL_E0[1]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[1]	0.F0.B20	0.F0.B19	0.F0.B23	0.F0.B22
PULLUP	0	0	0	0
DBL_W2[2]	0	0	0	1
DBL_W2[3]	0	0	1	0
DBL_W1[2]	0	1	0	1
DBL_W1[3]	0	1	1	0
DBL_E1[2]	1	0	0	1
DBL_E1[3]	1	0	1	0
DBL_E0[2]	1	1	0	1
DBL_E0[3]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[2]	0.F0.B34	0.F0.B33	0.F0.B37	0.F0.B36
PULLUP	0	0	0	0
DBL_W2[4]	0	0	0	1
DBL_W2[5]	0	0	1	0
DBL_W1[4]	0	1	0	1
DBL_W1[5]	0	1	1	0
DBL_E1[4]	1	0	0	1
DBL_E1[5]	1	0	1	0
DBL_E0[4]	1	1	0	1
DBL_E0[5]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[3]	0.F0.B54	0.F0.B53	0.F0.B57	0.F0.B56
PULLUP	0	0	0	0
DBL_W2[6]	0	0	0	1
DBL_W2[7]	0	0	1	0
DBL_W1[6]	0	1	0	1
DBL_W1[7]	0	1	1	0
DBL_E1[6]	1	0	0	1
DBL_E1[7]	1	0	1	0
DBL_E0[6]	1	1	0	1
DBL_E0[7]	1	1	1	0

CLK_INT:MUX.OMUX_N10	1.F0.B8	1.F0.B9	0.F0.B0
CLK_INT:MUX.OMUX_N11	1.F0.B11	1.F0.B7	1.F0.B10
CLK_INT:MUX.OMUX_N12	0.F0.B44	0.F0.B45	0.F0.B42
CLK_INT:MUX.OMUX_N15	0.F0.B47	0.F0.B46	0.F0.B43
NONE	0	0	0
OUT_BUFG[2]	0	0	1
OUT_BUFG[3]	0	1	0
OUT_BUFG[0]	1	0	1
OUT_BUFG[1]	1	1	0

`CLK_S_S3E`

This tile is used on Spartan 3E.

Tile CLK_S_S3E

Cells: 1

Switchbox CLK_INT

spartan3 CLK_S_S3E switchbox CLK_INT muxes OMUX_N10
Bits	Destination
OMUX_N10
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3E switchbox CLK_INT muxes OMUX_N11
Bits	Destination
OMUX_N11
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3E switchbox CLK_INT muxes OMUX_N12
Bits	Destination
OMUX_N12
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3E switchbox CLK_INT muxes OMUX_N15
Bits	Destination
OMUX_N15
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
IMUX_BUFG_CLK[0]
	Source
DBL_E1[7]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
IMUX_BUFG_CLK[1]
	Source
DBL_E1[5]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
IMUX_BUFG_CLK[2]
	Source
DBL_E1[3]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
IMUX_BUFG_CLK[3]
	Source
DBL_E1[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
IMUX_BUFG_SEL[0]
	Source
DBL_E1[7]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
IMUX_BUFG_SEL[1]
	Source
DBL_E1[5]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
IMUX_BUFG_SEL[2]
	Source
DBL_E1[3]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
IMUX_BUFG_SEL[3]
	Source
DBL_E1[1]

Bel BUFGMUX[0]

spartan3 CLK_S_S3E bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[0]
O	output	OUT_BUFG[0]
S	input	IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

spartan3 CLK_S_S3E bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[1]
O	output	OUT_BUFG[1]
S	input	IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

spartan3 CLK_S_S3E bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[2]
O	output	OUT_BUFG[2]
S	input	IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

spartan3 CLK_S_S3E bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[3]
O	output	OUT_BUFG[3]
S	input	IMUX_BUFG_SEL[3]

Bel GLOBALSIG_S[0]

spartan3 CLK_S_S3E bel GLOBALSIG_S[0]
Pin	Direction	Wires

Bel wires

spartan3 CLK_S_S3E bel wires
Wire	Pins
IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
IMUX_BUFG_SEL[0]	BUFGMUX[0].S
IMUX_BUFG_SEL[1]	BUFGMUX[1].S
IMUX_BUFG_SEL[2]	BUFGMUX[2].S
IMUX_BUFG_SEL[3]	BUFGMUX[3].S
OUT_BUFG[0]	BUFGMUX[0].O
OUT_BUFG[1]	BUFGMUX[1].O
OUT_BUFG[2]	BUFGMUX[2].O
OUT_BUFG[3]	BUFGMUX[3].O

Bitstream

spartan3 CLK_S_S3E rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_S_S3E rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

spartan3 CLK_S_S3E rect R0
Bit	Frame
Bit	F0
B62	BUFGMUX[3]:DISABLE_ATTR[0]
B61	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]
B60	CLK_INT:MUX.IMUX_BUFG_SEL[0][3]
B59	CLK_INT:MUX.IMUX_BUFG_SEL[0][2]
B58	CLK_INT:MUX.IMUX_BUFG_SEL[0][0]
B57	CLK_INT:MUX.IMUX_BUFG_CLK[0][0]
B56	CLK_INT:MUX.IMUX_BUFG_CLK[0][1]
B55	CLK_INT:MUX.IMUX_BUFG_SEL[0][1]
B54	CLK_INT:MUX.IMUX_BUFG_CLK[0][2]
B53	CLK_INT:MUX.IMUX_BUFG_CLK[0][3]
B52	BUFGMUX[0]:DISABLE_ATTR[0]
B51	BUFGMUX[0]:MUX.CLK[2]
B50	BUFGMUX[0]:MUX.CLK[1]
B49	BUFGMUX[0]:MUX.CLK[3]
B48	BUFGMUX[0]:MUX.CLK[4]
B47	BUFGMUX[0]:MUX.CLK[0]
B46	CLK_INT:MUX.OMUX_N15[2]
B45	CLK_INT:MUX.OMUX_N15[1]
B44	CLK_INT:MUX.OMUX_N12[1]
B43	CLK_INT:MUX.OMUX_N12[2]
B42	CLK_INT:MUX.OMUX_N15[0]
B41	CLK_INT:MUX.OMUX_N12[0]
B40	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]
B39	CLK_INT:MUX.IMUX_BUFG_SEL[1][3]
B38	CLK_INT:MUX.IMUX_BUFG_SEL[1][2]
B37	CLK_INT:MUX.IMUX_BUFG_SEL[1][0]
B36	CLK_INT:MUX.IMUX_BUFG_CLK[1][0]
B35	CLK_INT:MUX.IMUX_BUFG_CLK[1][1]
B34	CLK_INT:MUX.IMUX_BUFG_SEL[1][1]
B33	CLK_INT:MUX.IMUX_BUFG_CLK[1][2]
B32	CLK_INT:MUX.IMUX_BUFG_CLK[1][3]
B31	BUFGMUX[1]:DISABLE_ATTR[0]
B30	BUFGMUX[1]:MUX.CLK[2]
B29	BUFGMUX[1]:MUX.CLK[1]
B28	BUFGMUX[1]:MUX.CLK[3]
B27	BUFGMUX[1]:MUX.CLK[4]
B26	BUFGMUX[1]:MUX.CLK[0]
B25	BUFGMUX[2]:DISABLE_ATTR[0]
B24	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]
B23	CLK_INT:MUX.IMUX_BUFG_SEL[2][3]
B22	CLK_INT:MUX.IMUX_BUFG_SEL[2][2]
B21	CLK_INT:MUX.IMUX_BUFG_SEL[2][0]
B20	CLK_INT:MUX.IMUX_BUFG_CLK[2][0]
B19	CLK_INT:MUX.IMUX_BUFG_CLK[2][1]
B18	CLK_INT:MUX.IMUX_BUFG_SEL[2][1]
B17	CLK_INT:MUX.IMUX_BUFG_CLK[2][2]
B16	CLK_INT:MUX.IMUX_BUFG_CLK[2][3]
B15	BUFGMUX[2]:MUX.CLK[2]
B14	BUFGMUX[2]:MUX.CLK[1]
B13	BUFGMUX[2]:MUX.CLK[3]
B12	BUFGMUX[2]:MUX.CLK[4]
B11	BUFGMUX[2]:MUX.CLK[0]
B10	BUFGMUX[3]:MUX.CLK[2]
B9	BUFGMUX[3]:MUX.CLK[1]
B8	BUFGMUX[3]:MUX.CLK[3]
B7	BUFGMUX[3]:MUX.CLK[4]
B6	BUFGMUX[3]:MUX.CLK[0]
B5	CLK_INT:MUX.IMUX_BUFG_CLK[3][3]
B4	CLK_INT:MUX.IMUX_BUFG_CLK[3][2]
B3	CLK_INT:MUX.IMUX_BUFG_SEL[3][0]
B2	CLK_INT:MUX.IMUX_BUFG_CLK[3][0]
B1	CLK_INT:MUX.IMUX_BUFG_CLK[3][1]
B0	CLK_INT:MUX.IMUX_BUFG_SEL[3][1]

spartan3 CLK_S_S3E rect R1
Bit	Frame
Bit	F0
B15	CLK_INT:MUX.OMUX_N11[0]
B14	CLK_INT:MUX.OMUX_N11[1]
B13	CLK_INT:MUX.OMUX_N10[1]
B12	CLK_INT:MUX.OMUX_N10[2]
B11	CLK_INT:MUX.IMUX_BUFG_SEL[3][2]
B10	CLK_INT:MUX.IMUX_BUFG_SEL[3][3]
B9	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]
B8	CLK_INT:MUX.OMUX_N10[0]
B7	CLK_INT:MUX.OMUX_N11[2]
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

BUFGMUX[0]:DISABLE_ATTR	0.F0.B52
BUFGMUX[1]:DISABLE_ATTR	0.F0.B31
BUFGMUX[2]:DISABLE_ATTR	0.F0.B25
BUFGMUX[3]:DISABLE_ATTR	0.F0.B62
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B48	0.F0.B49	0.F0.B51	0.F0.B50	0.F0.B47
BUFGMUX[1]:MUX.CLK	0.F0.B27	0.F0.B28	0.F0.B30	0.F0.B29	0.F0.B26
BUFGMUX[2]:MUX.CLK	0.F0.B12	0.F0.B13	0.F0.B15	0.F0.B14	0.F0.B11
BUFGMUX[3]:MUX.CLK	0.F0.B7	0.F0.B8	0.F0.B10	0.F0.B9	0.F0.B6
INT	0	0	0	0	1
CKIL	0	0	0	1	0
CKIR	0	0	1	0	0
DCM_OUT_L	0	1	0	0	0
DCM_OUT_R	1	0	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F0.B61
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F0.B40
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F0.B24
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	1.F0.B9
inverted	~[0]

CLK_INT:MUX.IMUX_BUFG_CLK[0]	0.F0.B53	0.F0.B54	0.F0.B56	0.F0.B57
CLK_INT:MUX.IMUX_BUFG_SEL[0]	0.F0.B60	0.F0.B59	0.F0.B55	0.F0.B58
PULLUP	0	0	0	0
DBL_W2[6]	0	0	0	1
DBL_W2[7]	0	0	1	0
DBL_W1[6]	0	1	0	1
DBL_W1[7]	0	1	1	0
DBL_E1[6]	1	0	0	1
DBL_E1[7]	1	0	1	0
DBL_E0[6]	1	1	0	1
DBL_E0[7]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[1]	0.F0.B32	0.F0.B33	0.F0.B35	0.F0.B36
CLK_INT:MUX.IMUX_BUFG_SEL[1]	0.F0.B39	0.F0.B38	0.F0.B34	0.F0.B37
PULLUP	0	0	0	0
DBL_W2[4]	0	0	0	1
DBL_W2[5]	0	0	1	0
DBL_W1[4]	0	1	0	1
DBL_W1[5]	0	1	1	0
DBL_E1[4]	1	0	0	1
DBL_E1[5]	1	0	1	0
DBL_E0[4]	1	1	0	1
DBL_E0[5]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[2]	0.F0.B16	0.F0.B17	0.F0.B19	0.F0.B20
CLK_INT:MUX.IMUX_BUFG_SEL[2]	0.F0.B23	0.F0.B22	0.F0.B18	0.F0.B21
PULLUP	0	0	0	0
DBL_W2[2]	0	0	0	1
DBL_W2[3]	0	0	1	0
DBL_W1[2]	0	1	0	1
DBL_W1[3]	0	1	1	0
DBL_E1[2]	1	0	0	1
DBL_E1[3]	1	0	1	0
DBL_E0[2]	1	1	0	1
DBL_E0[3]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[3]	0.F0.B5	0.F0.B4	0.F0.B1	0.F0.B2
CLK_INT:MUX.IMUX_BUFG_SEL[3]	1.F0.B10	1.F0.B11	0.F0.B0	0.F0.B3
PULLUP	0	0	0	0
DBL_W2[0]	0	0	0	1
DBL_W2[1]	0	0	1	0
DBL_W1[0]	0	1	0	1
DBL_W1[1]	0	1	1	0
DBL_E1[0]	1	0	0	1
DBL_E1[1]	1	0	1	0
DBL_E0[0]	1	1	0	1
DBL_E0[1]	1	1	1	0

CLK_INT:MUX.OMUX_N10	1.F0.B12	1.F0.B13	1.F0.B8
CLK_INT:MUX.OMUX_N11	1.F0.B7	1.F0.B14	1.F0.B15
CLK_INT:MUX.OMUX_N12	0.F0.B43	0.F0.B44	0.F0.B41
CLK_INT:MUX.OMUX_N15	0.F0.B46	0.F0.B45	0.F0.B42
NONE	0	0	0
OUT_BUFG[2]	0	0	1
OUT_BUFG[3]	0	1	0
OUT_BUFG[0]	1	0	1
OUT_BUFG[1]	1	1	0

`CLK_S_S3A`

This tile is used on Spartan 3A and 3A DSP.

Tile CLK_S_S3A

Cells: 1

Switchbox CLK_INT

spartan3 CLK_S_S3A switchbox CLK_INT muxes OMUX_N10
Bits	Destination
OMUX_N10
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3A switchbox CLK_INT muxes OMUX_N11
Bits	Destination
OMUX_N11
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3A switchbox CLK_INT muxes OMUX_N12
Bits	Destination
OMUX_N12
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3A switchbox CLK_INT muxes OMUX_N15
Bits	Destination
OMUX_N15
	Source
OUT_BUFG[3]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
IMUX_BUFG_CLK[0]
	Source
DBL_E1[7]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
IMUX_BUFG_CLK[1]
	Source
DBL_E1[5]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
IMUX_BUFG_CLK[2]
	Source
DBL_E1[3]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
IMUX_BUFG_CLK[3]
	Source
DBL_E1[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
IMUX_BUFG_SEL[0]
	Source
DBL_E1[7]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
IMUX_BUFG_SEL[1]
	Source
DBL_E1[5]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
IMUX_BUFG_SEL[2]
	Source
DBL_E1[3]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
IMUX_BUFG_SEL[3]
	Source
DBL_E1[1]

Bel BUFGMUX[0]

spartan3 CLK_S_S3A bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[0]
O	output	OUT_BUFG[0]
S	input	IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

spartan3 CLK_S_S3A bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[1]
O	output	OUT_BUFG[1]
S	input	IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

spartan3 CLK_S_S3A bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[2]
O	output	OUT_BUFG[2]
S	input	IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

spartan3 CLK_S_S3A bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[3]
O	output	OUT_BUFG[3]
S	input	IMUX_BUFG_SEL[3]

Bel GLOBALSIG_S[0]

spartan3 CLK_S_S3A bel GLOBALSIG_S[0]
Pin	Direction	Wires

Bel wires

spartan3 CLK_S_S3A bel wires
Wire	Pins
IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
IMUX_BUFG_SEL[0]	BUFGMUX[0].S
IMUX_BUFG_SEL[1]	BUFGMUX[1].S
IMUX_BUFG_SEL[2]	BUFGMUX[2].S
IMUX_BUFG_SEL[3]	BUFGMUX[3].S
OUT_BUFG[0]	BUFGMUX[0].O
OUT_BUFG[1]	BUFGMUX[1].O
OUT_BUFG[2]	BUFGMUX[2].O
OUT_BUFG[3]	BUFGMUX[3].O

Bitstream

spartan3 CLK_S_S3A rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_S_S3A rect TERM
Bit	Frame
Bit	F0	F1
B15	-	-
B14	-	-
B13	-	-
B12	-	-
B11	-	-
B10	-	-
B9	-	-
B8	-	-
B7	-	-
B6	-	-
B5	-	-
B4	-	-
B3	-	-
B2	-	-
B1	-	-
B0	-	-

### Bitstream

spartan3 CLK_S_S3A rect R0
Bit	Frame
Bit	F0
B62	BUFGMUX[3]:DISABLE_ATTR[0]
B61	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]
B60	CLK_INT:MUX.IMUX_BUFG_SEL[0][3]
B59	CLK_INT:MUX.IMUX_BUFG_SEL[0][2]
B58	CLK_INT:MUX.IMUX_BUFG_SEL[0][0]
B57	CLK_INT:MUX.IMUX_BUFG_CLK[0][0]
B56	CLK_INT:MUX.IMUX_BUFG_CLK[0][1]
B55	CLK_INT:MUX.IMUX_BUFG_SEL[0][1]
B54	CLK_INT:MUX.IMUX_BUFG_CLK[0][2]
B53	CLK_INT:MUX.IMUX_BUFG_CLK[0][3]
B52	BUFGMUX[0]:DISABLE_ATTR[0]
B51	BUFGMUX[0]:MUX.CLK[2]
B50	BUFGMUX[0]:MUX.CLK[1]
B49	BUFGMUX[0]:MUX.CLK[3]
B48	BUFGMUX[0]:MUX.CLK[4]
B47	BUFGMUX[0]:MUX.CLK[0]
B46	CLK_INT:MUX.OMUX_N15[2]
B45	CLK_INT:MUX.OMUX_N15[1]
B44	CLK_INT:MUX.OMUX_N12[1]
B43	CLK_INT:MUX.OMUX_N12[2]
B42	CLK_INT:MUX.OMUX_N15[0]
B41	CLK_INT:MUX.OMUX_N12[0]
B40	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]
B39	CLK_INT:MUX.IMUX_BUFG_SEL[1][3]
B38	CLK_INT:MUX.IMUX_BUFG_SEL[1][2]
B37	CLK_INT:MUX.IMUX_BUFG_SEL[1][0]
B36	CLK_INT:MUX.IMUX_BUFG_CLK[1][0]
B35	CLK_INT:MUX.IMUX_BUFG_CLK[1][1]
B34	CLK_INT:MUX.IMUX_BUFG_SEL[1][1]
B33	CLK_INT:MUX.IMUX_BUFG_CLK[1][2]
B32	CLK_INT:MUX.IMUX_BUFG_CLK[1][3]
B31	BUFGMUX[1]:DISABLE_ATTR[0]
B30	BUFGMUX[1]:MUX.CLK[2]
B29	BUFGMUX[1]:MUX.CLK[1]
B28	BUFGMUX[1]:MUX.CLK[3]
B27	BUFGMUX[1]:MUX.CLK[4]
B26	BUFGMUX[1]:MUX.CLK[0]
B25	BUFGMUX[2]:DISABLE_ATTR[0]
B24	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]
B23	CLK_INT:MUX.IMUX_BUFG_SEL[2][3]
B22	CLK_INT:MUX.IMUX_BUFG_SEL[2][2]
B21	CLK_INT:MUX.IMUX_BUFG_SEL[2][0]
B20	CLK_INT:MUX.IMUX_BUFG_CLK[2][0]
B19	CLK_INT:MUX.IMUX_BUFG_CLK[2][1]
B18	CLK_INT:MUX.IMUX_BUFG_SEL[2][1]
B17	CLK_INT:MUX.IMUX_BUFG_CLK[2][2]
B16	CLK_INT:MUX.IMUX_BUFG_CLK[2][3]
B15	BUFGMUX[2]:MUX.CLK[2]
B14	BUFGMUX[2]:MUX.CLK[1]
B13	BUFGMUX[2]:MUX.CLK[3]
B12	BUFGMUX[2]:MUX.CLK[4]
B11	BUFGMUX[2]:MUX.CLK[0]
B10	BUFGMUX[3]:MUX.CLK[2]
B9	BUFGMUX[3]:MUX.CLK[1]
B8	BUFGMUX[3]:MUX.CLK[3]
B7	BUFGMUX[3]:MUX.CLK[4]
B6	BUFGMUX[3]:MUX.CLK[0]
B5	CLK_INT:MUX.IMUX_BUFG_CLK[3][3]
B4	CLK_INT:MUX.IMUX_BUFG_CLK[3][2]
B3	CLK_INT:MUX.IMUX_BUFG_SEL[3][0]
B2	CLK_INT:MUX.IMUX_BUFG_CLK[3][0]
B1	CLK_INT:MUX.IMUX_BUFG_CLK[3][1]
B0	CLK_INT:MUX.IMUX_BUFG_SEL[3][1]

spartan3 CLK_S_S3A rect R1
Bit	Frame
Bit	F0	F1
B5	-	CLK_INT:MUX.OMUX_N10[2]
B4	CLK_INT:MUX.IMUX_BUFG_SEL[3][2]	CLK_INT:MUX.OMUX_N11[0]
B3	CLK_INT:MUX.IMUX_BUFG_SEL[3][3]	CLK_INT:MUX.OMUX_N11[1]
B2	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]	CLK_INT:MUX.OMUX_N10[1]
B1	-	CLK_INT:MUX.OMUX_N10[0]
B0	-	CLK_INT:MUX.OMUX_N11[2]

BUFGMUX[0]:DISABLE_ATTR	0.F0.B52
BUFGMUX[1]:DISABLE_ATTR	0.F0.B31
BUFGMUX[2]:DISABLE_ATTR	0.F0.B25
BUFGMUX[3]:DISABLE_ATTR	0.F0.B62
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B48	0.F0.B49	0.F0.B51	0.F0.B50	0.F0.B47
BUFGMUX[1]:MUX.CLK	0.F0.B27	0.F0.B28	0.F0.B30	0.F0.B29	0.F0.B26
BUFGMUX[2]:MUX.CLK	0.F0.B12	0.F0.B13	0.F0.B15	0.F0.B14	0.F0.B11
BUFGMUX[3]:MUX.CLK	0.F0.B7	0.F0.B8	0.F0.B10	0.F0.B9	0.F0.B6
INT	0	0	0	0	1
CKIL	0	0	0	1	0
CKIR	0	0	1	0	0
DCM_OUT_L	0	1	0	0	0
DCM_OUT_R	1	0	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F0.B61
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F0.B40
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F0.B24
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	1.F0.B2
inverted	~[0]

CLK_INT:MUX.IMUX_BUFG_CLK[0]	0.F0.B53	0.F0.B54	0.F0.B56	0.F0.B57
CLK_INT:MUX.IMUX_BUFG_SEL[0]	0.F0.B60	0.F0.B59	0.F0.B55	0.F0.B58
PULLUP	0	0	0	0
DBL_W2[6]	0	0	0	1
DBL_W2[7]	0	0	1	0
DBL_W1[6]	0	1	0	1
DBL_W1[7]	0	1	1	0
DBL_E1[6]	1	0	0	1
DBL_E1[7]	1	0	1	0
DBL_E0[6]	1	1	0	1
DBL_E0[7]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[1]	0.F0.B32	0.F0.B33	0.F0.B35	0.F0.B36
CLK_INT:MUX.IMUX_BUFG_SEL[1]	0.F0.B39	0.F0.B38	0.F0.B34	0.F0.B37
PULLUP	0	0	0	0
DBL_W2[4]	0	0	0	1
DBL_W2[5]	0	0	1	0
DBL_W1[4]	0	1	0	1
DBL_W1[5]	0	1	1	0
DBL_E1[4]	1	0	0	1
DBL_E1[5]	1	0	1	0
DBL_E0[4]	1	1	0	1
DBL_E0[5]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[2]	0.F0.B16	0.F0.B17	0.F0.B19	0.F0.B20
CLK_INT:MUX.IMUX_BUFG_SEL[2]	0.F0.B23	0.F0.B22	0.F0.B18	0.F0.B21
PULLUP	0	0	0	0
DBL_W2[2]	0	0	0	1
DBL_W2[3]	0	0	1	0
DBL_W1[2]	0	1	0	1
DBL_W1[3]	0	1	1	0
DBL_E1[2]	1	0	0	1
DBL_E1[3]	1	0	1	0
DBL_E0[2]	1	1	0	1
DBL_E0[3]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[3]	0.F0.B5	0.F0.B4	0.F0.B1	0.F0.B2
CLK_INT:MUX.IMUX_BUFG_SEL[3]	1.F0.B3	1.F0.B4	0.F0.B0	0.F0.B3
PULLUP	0	0	0	0
DBL_W2[0]	0	0	0	1
DBL_W2[1]	0	0	1	0
DBL_W1[0]	0	1	0	1
DBL_W1[1]	0	1	1	0
DBL_E1[0]	1	0	0	1
DBL_E1[1]	1	0	1	0
DBL_E0[0]	1	1	0	1
DBL_E0[1]	1	1	1	0

CLK_INT:MUX.OMUX_N10	1.F1.B5	1.F1.B2	1.F1.B1
CLK_INT:MUX.OMUX_N11	1.F1.B0	1.F1.B3	1.F1.B4
CLK_INT:MUX.OMUX_N12	0.F0.B43	0.F0.B44	0.F0.B41
CLK_INT:MUX.OMUX_N15	0.F0.B46	0.F0.B45	0.F0.B42
NONE	0	0	0
OUT_BUFG[2]	0	0	1
OUT_BUFG[3]	0	1	0
OUT_BUFG[0]	1	0	1
OUT_BUFG[1]	1	1	0

Bitstream — north tiles

The CLK_N_* tiles use two bitstream tiles:

tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the top interconnect row
tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the high special area (used for top IOB tiles and clock rows in normal columns)

On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH_N_S3A tile.

`CLK_N_S3`

This tile is used on Spartan 3.

Tile CLK_N_S3

Cells: 1

Switchbox CLK_INT

spartan3 CLK_N_S3 switchbox CLK_INT muxes OMUX_S0
Bits	Destination
OMUX_S0
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes OMUX_S3
Bits	Destination
OMUX_S3
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes OMUX_S4
Bits	Destination
OMUX_S4
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes OMUX_S5
Bits	Destination
OMUX_S5
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
IMUX_BUFG_CLK[0]
	Source
DBL_E1[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
IMUX_BUFG_CLK[1]
	Source
DBL_E1[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
IMUX_BUFG_CLK[2]
	Source
DBL_E1[5]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
IMUX_BUFG_CLK[3]
	Source
DBL_E1[7]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
IMUX_BUFG_SEL[0]
	Source
DBL_E1[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
IMUX_BUFG_SEL[1]
	Source
DBL_E1[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
IMUX_BUFG_SEL[2]
	Source
DBL_E1[5]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
IMUX_BUFG_SEL[3]
	Source
DBL_E1[7]

Bel BUFGMUX[0]

spartan3 CLK_N_S3 bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[0]
O	output	OUT_BUFG[0]
S	input	IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

spartan3 CLK_N_S3 bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[1]
O	output	OUT_BUFG[1]
S	input	IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

spartan3 CLK_N_S3 bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[2]
O	output	OUT_BUFG[2]
S	input	IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

spartan3 CLK_N_S3 bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[3]
O	output	OUT_BUFG[3]
S	input	IMUX_BUFG_SEL[3]

Bel GLOBALSIG_N[0]

spartan3 CLK_N_S3 bel GLOBALSIG_N[0]
Pin	Direction	Wires

Bel wires

spartan3 CLK_N_S3 bel wires
Wire	Pins
IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
IMUX_BUFG_SEL[0]	BUFGMUX[0].S
IMUX_BUFG_SEL[1]	BUFGMUX[1].S
IMUX_BUFG_SEL[2]	BUFGMUX[2].S
IMUX_BUFG_SEL[3]	BUFGMUX[3].S
OUT_BUFG[0]	BUFGMUX[0].O
OUT_BUFG[1]	BUFGMUX[1].O
OUT_BUFG[2]	BUFGMUX[2].O
OUT_BUFG[3]	BUFGMUX[3].O

Bitstream

spartan3 CLK_N_S3 rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_N_S3 rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

spartan3 CLK_N_S3 rect R0
Bit	Frame
Bit	F0
B63	CLK_INT:MUX.OMUX_S0[0]
B62	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]
B61	CLK_INT:MUX.IMUX_BUFG_SEL[3][3]
B60	CLK_INT:MUX.IMUX_BUFG_SEL[3][2]
B59	CLK_INT:MUX.IMUX_BUFG_SEL[3][1]
B58	CLK_INT:MUX.IMUX_BUFG_CLK[3][1]
B57	CLK_INT:MUX.IMUX_BUFG_CLK[3][0]
B56	CLK_INT:MUX.IMUX_BUFG_SEL[3][0]
B55	CLK_INT:MUX.IMUX_BUFG_CLK[3][2]
B54	CLK_INT:MUX.IMUX_BUFG_CLK[3][3]
B53	BUFGMUX[3]:MUX.CLK[0]
B52	BUFGMUX[3]:MUX.CLK[3]
B51	BUFGMUX[3]:MUX.CLK[2]
B50	BUFGMUX[3]:MUX.CLK[1]
B49	BUFGMUX[2]:MUX.CLK[0]
B48	BUFGMUX[2]:MUX.CLK[3]
B47	BUFGMUX[2]:MUX.CLK[2]
B46	BUFGMUX[2]:MUX.CLK[1]
B45	BUFGMUX[2]:DISABLE_ATTR[0]
B44	CLK_INT:MUX.IMUX_BUFG_CLK[2][2]
B43	CLK_INT:MUX.IMUX_BUFG_CLK[2][3]
B42	CLK_INT:MUX.IMUX_BUFG_SEL[2][1]
B41	CLK_INT:MUX.IMUX_BUFG_CLK[2][1]
B40	CLK_INT:MUX.IMUX_BUFG_CLK[2][0]
B39	CLK_INT:MUX.IMUX_BUFG_SEL[2][0]
B38	CLK_INT:MUX.IMUX_BUFG_SEL[2][3]
B37	CLK_INT:MUX.IMUX_BUFG_SEL[2][2]
B36	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]
B35	BUFGMUX[1]:MUX.CLK[0]
B34	BUFGMUX[1]:MUX.CLK[3]
B33	BUFGMUX[1]:MUX.CLK[2]
B32	BUFGMUX[1]:MUX.CLK[1]
B31	BUFGMUX[1]:DISABLE_ATTR[0]
B30	CLK_INT:MUX.IMUX_BUFG_CLK[1][2]
B29	CLK_INT:MUX.IMUX_BUFG_CLK[1][3]
B28	CLK_INT:MUX.IMUX_BUFG_SEL[1][1]
B27	CLK_INT:MUX.IMUX_BUFG_CLK[1][1]
B26	CLK_INT:MUX.IMUX_BUFG_CLK[1][0]
B25	CLK_INT:MUX.IMUX_BUFG_SEL[1][0]
B24	CLK_INT:MUX.IMUX_BUFG_SEL[1][3]
B23	CLK_INT:MUX.IMUX_BUFG_SEL[1][2]
B22	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]
B21	CLK_INT:MUX.OMUX_S4[0]
B20	CLK_INT:MUX.OMUX_S5[0]
B19	CLK_INT:MUX.OMUX_S4[2]
B18	CLK_INT:MUX.OMUX_S4[1]
B17	CLK_INT:MUX.OMUX_S5[1]
B16	CLK_INT:MUX.OMUX_S5[2]
B15	BUFGMUX[0]:MUX.CLK[0]
B14	BUFGMUX[0]:MUX.CLK[3]
B13	BUFGMUX[0]:MUX.CLK[2]
B12	BUFGMUX[0]:MUX.CLK[1]
B11	BUFGMUX[0]:DISABLE_ATTR[0]
B10	CLK_INT:MUX.IMUX_BUFG_CLK[0][2]
B9	CLK_INT:MUX.IMUX_BUFG_CLK[0][3]
B8	CLK_INT:MUX.IMUX_BUFG_SEL[0][1]
B7	CLK_INT:MUX.IMUX_BUFG_CLK[0][1]
B6	CLK_INT:MUX.IMUX_BUFG_CLK[0][0]
B5	CLK_INT:MUX.IMUX_BUFG_SEL[0][0]
B4	CLK_INT:MUX.IMUX_BUFG_SEL[0][3]
B3	CLK_INT:MUX.IMUX_BUFG_SEL[0][2]
B2	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]
B1	BUFGMUX[3]:DISABLE_ATTR[0]
B0	-

spartan3 CLK_N_S3 rect R1
Bit	Frame
Bit	F0
B4	CLK_INT:MUX.OMUX_S3[1]
B3	CLK_INT:MUX.OMUX_S0[2]
B2	CLK_INT:MUX.OMUX_S0[1]
B1	CLK_INT:MUX.OMUX_S3[0]
B0	CLK_INT:MUX.OMUX_S3[2]

BUFGMUX[0]:DISABLE_ATTR	0.F0.B11
BUFGMUX[1]:DISABLE_ATTR	0.F0.B31
BUFGMUX[2]:DISABLE_ATTR	0.F0.B45
BUFGMUX[3]:DISABLE_ATTR	0.F0.B1
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B14	0.F0.B13	0.F0.B12	0.F0.B15
BUFGMUX[1]:MUX.CLK	0.F0.B34	0.F0.B33	0.F0.B32	0.F0.B35
BUFGMUX[2]:MUX.CLK	0.F0.B48	0.F0.B47	0.F0.B46	0.F0.B49
BUFGMUX[3]:MUX.CLK	0.F0.B52	0.F0.B51	0.F0.B50	0.F0.B53
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F0.B2
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F0.B22
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F0.B36
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	0.F0.B62
inverted	~[0]

CLK_INT:MUX.IMUX_BUFG_CLK[0]	0.F0.B9	0.F0.B10	0.F0.B7	0.F0.B6
CLK_INT:MUX.IMUX_BUFG_SEL[0]	0.F0.B4	0.F0.B3	0.F0.B8	0.F0.B5
PULLUP	0	0	0	0
DBL_W2[0]	0	0	0	1
DBL_W2[1]	0	0	1	0
DBL_W1[0]	0	1	0	1
DBL_W1[1]	0	1	1	0
DBL_E1[0]	1	0	0	1
DBL_E1[1]	1	0	1	0
DBL_E0[0]	1	1	0	1
DBL_E0[1]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[1]	0.F0.B29	0.F0.B30	0.F0.B27	0.F0.B26
CLK_INT:MUX.IMUX_BUFG_SEL[1]	0.F0.B24	0.F0.B23	0.F0.B28	0.F0.B25
PULLUP	0	0	0	0
DBL_W2[2]	0	0	0	1
DBL_W2[3]	0	0	1	0
DBL_W1[2]	0	1	0	1
DBL_W1[3]	0	1	1	0
DBL_E1[2]	1	0	0	1
DBL_E1[3]	1	0	1	0
DBL_E0[2]	1	1	0	1
DBL_E0[3]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[2]	0.F0.B43	0.F0.B44	0.F0.B41	0.F0.B40
CLK_INT:MUX.IMUX_BUFG_SEL[2]	0.F0.B38	0.F0.B37	0.F0.B42	0.F0.B39
PULLUP	0	0	0	0
DBL_W2[4]	0	0	0	1
DBL_W2[5]	0	0	1	0
DBL_W1[4]	0	1	0	1
DBL_W1[5]	0	1	1	0
DBL_E1[4]	1	0	0	1
DBL_E1[5]	1	0	1	0
DBL_E0[4]	1	1	0	1
DBL_E0[5]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[3]	0.F0.B54	0.F0.B55	0.F0.B58	0.F0.B57
CLK_INT:MUX.IMUX_BUFG_SEL[3]	0.F0.B61	0.F0.B60	0.F0.B59	0.F0.B56
PULLUP	0	0	0	0
DBL_W2[6]	0	0	0	1
DBL_W2[7]	0	0	1	0
DBL_W1[6]	0	1	0	1
DBL_W1[7]	0	1	1	0
DBL_E1[6]	1	0	0	1
DBL_E1[7]	1	0	1	0
DBL_E0[6]	1	1	0	1
DBL_E0[7]	1	1	1	0

CLK_INT:MUX.OMUX_S0	1.F0.B3	1.F0.B2	0.F0.B63
CLK_INT:MUX.OMUX_S3	1.F0.B0	1.F0.B4	1.F0.B1
CLK_INT:MUX.OMUX_S4	0.F0.B19	0.F0.B18	0.F0.B21
CLK_INT:MUX.OMUX_S5	0.F0.B16	0.F0.B17	0.F0.B20
NONE	0	0	0
OUT_BUFG[2]	0	0	1
OUT_BUFG[3]	0	1	0
OUT_BUFG[0]	1	0	1
OUT_BUFG[1]	1	1	0

`CLK_N_FC`

This tile is used on FPGAcore.

Tile CLK_N_FC

Cells: 1

Switchbox CLK_INT

spartan3 CLK_N_FC switchbox CLK_INT muxes OMUX_S0
Bits	Destination
OMUX_S0
	Source
OUT_BUFG[3]

spartan3 CLK_N_FC switchbox CLK_INT muxes OMUX_S3
Bits	Destination
OMUX_S3
	Source
OUT_BUFG[3]

spartan3 CLK_N_FC switchbox CLK_INT muxes OMUX_S4
Bits	Destination
OMUX_S4
	Source
OUT_BUFG[3]

spartan3 CLK_N_FC switchbox CLK_INT muxes OMUX_S5
Bits	Destination
OMUX_S5
	Source
OUT_BUFG[3]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
IMUX_BUFG_CLK[0]
	Source
DBL_E1[1]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
IMUX_BUFG_CLK[1]
	Source
DBL_E1[3]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
IMUX_BUFG_CLK[2]
	Source
DBL_E1[5]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
IMUX_BUFG_CLK[3]
	Source
DBL_E1[7]

Bel BUFGMUX[0]

spartan3 CLK_N_FC bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[0]
O	output	OUT_BUFG[0]

Bel BUFGMUX[1]

spartan3 CLK_N_FC bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[1]
O	output	OUT_BUFG[1]

Bel BUFGMUX[2]

spartan3 CLK_N_FC bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[2]
O	output	OUT_BUFG[2]

Bel BUFGMUX[3]

spartan3 CLK_N_FC bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[3]
O	output	OUT_BUFG[3]

Bel GLOBALSIG_N[0]

spartan3 CLK_N_FC bel GLOBALSIG_N[0]
Pin	Direction	Wires

Bel wires

spartan3 CLK_N_FC bel wires
Wire	Pins
IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
OUT_BUFG[0]	BUFGMUX[0].O
OUT_BUFG[1]	BUFGMUX[1].O
OUT_BUFG[2]	BUFGMUX[2].O
OUT_BUFG[3]	BUFGMUX[3].O

Bitstream

spartan3 CLK_N_FC rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_N_FC rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

spartan3 CLK_N_FC rect R0
Bit	Frame
Bit	F0
B63	CLK_INT:MUX.OMUX_S0[0]
B62	-
B61	-
B60	-
B59	-
B58	CLK_INT:MUX.IMUX_BUFG_CLK[3][1]
B57	CLK_INT:MUX.IMUX_BUFG_CLK[3][0]
B56	-
B55	CLK_INT:MUX.IMUX_BUFG_CLK[3][2]
B54	CLK_INT:MUX.IMUX_BUFG_CLK[3][3]
B53	BUFGMUX[3]:MUX.CLK[0]
B52	-
B51	-
B50	BUFGMUX[3]:MUX.CLK[1]
B49	BUFGMUX[2]:MUX.CLK[0]
B48	-
B47	-
B46	BUFGMUX[2]:MUX.CLK[1]
B45	-
B44	CLK_INT:MUX.IMUX_BUFG_CLK[2][2]
B43	CLK_INT:MUX.IMUX_BUFG_CLK[2][3]
B42	-
B41	CLK_INT:MUX.IMUX_BUFG_CLK[2][1]
B40	CLK_INT:MUX.IMUX_BUFG_CLK[2][0]
B39	-
B38	-
B37	-
B36	-
B35	BUFGMUX[1]:MUX.CLK[0]
B34	-
B33	-
B32	BUFGMUX[1]:MUX.CLK[1]
B31	-
B30	CLK_INT:MUX.IMUX_BUFG_CLK[1][2]
B29	CLK_INT:MUX.IMUX_BUFG_CLK[1][3]
B28	-
B27	CLK_INT:MUX.IMUX_BUFG_CLK[1][1]
B26	CLK_INT:MUX.IMUX_BUFG_CLK[1][0]
B25	-
B24	-
B23	-
B22	-
B21	CLK_INT:MUX.OMUX_S4[0]
B20	CLK_INT:MUX.OMUX_S5[0]
B19	CLK_INT:MUX.OMUX_S4[2]
B18	CLK_INT:MUX.OMUX_S4[1]
B17	CLK_INT:MUX.OMUX_S5[1]
B16	CLK_INT:MUX.OMUX_S5[2]
B15	BUFGMUX[0]:MUX.CLK[0]
B14	-
B13	-
B12	BUFGMUX[0]:MUX.CLK[1]
B11	-
B10	CLK_INT:MUX.IMUX_BUFG_CLK[0][2]
B9	CLK_INT:MUX.IMUX_BUFG_CLK[0][3]
B8	-
B7	CLK_INT:MUX.IMUX_BUFG_CLK[0][1]
B6	CLK_INT:MUX.IMUX_BUFG_CLK[0][0]
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_N_FC rect R1
Bit	Frame
Bit	F0
B4	CLK_INT:MUX.OMUX_S3[1]
B3	CLK_INT:MUX.OMUX_S0[2]
B2	CLK_INT:MUX.OMUX_S0[1]
B1	CLK_INT:MUX.OMUX_S3[0]
B0	CLK_INT:MUX.OMUX_S3[2]

BUFGMUX[0]:MUX.CLK	0.F0.B12	0.F0.B15
BUFGMUX[1]:MUX.CLK	0.F0.B32	0.F0.B35
BUFGMUX[2]:MUX.CLK	0.F0.B46	0.F0.B49
BUFGMUX[3]:MUX.CLK	0.F0.B50	0.F0.B53
INT	0	1
CKI	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[0]	0.F0.B9	0.F0.B10	0.F0.B7	0.F0.B6
PULLUP	0	0	0	0
DBL_W2[0]	0	0	0	1
DBL_W2[1]	0	0	1	0
DBL_W1[0]	0	1	0	1
DBL_W1[1]	0	1	1	0
DBL_E1[0]	1	0	0	1
DBL_E1[1]	1	0	1	0
DBL_E0[0]	1	1	0	1
DBL_E0[1]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[1]	0.F0.B29	0.F0.B30	0.F0.B27	0.F0.B26
PULLUP	0	0	0	0
DBL_W2[2]	0	0	0	1
DBL_W2[3]	0	0	1	0
DBL_W1[2]	0	1	0	1
DBL_W1[3]	0	1	1	0
DBL_E1[2]	1	0	0	1
DBL_E1[3]	1	0	1	0
DBL_E0[2]	1	1	0	1
DBL_E0[3]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[2]	0.F0.B43	0.F0.B44	0.F0.B41	0.F0.B40
PULLUP	0	0	0	0
DBL_W2[4]	0	0	0	1
DBL_W2[5]	0	0	1	0
DBL_W1[4]	0	1	0	1
DBL_W1[5]	0	1	1	0
DBL_E1[4]	1	0	0	1
DBL_E1[5]	1	0	1	0
DBL_E0[4]	1	1	0	1
DBL_E0[5]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[3]	0.F0.B54	0.F0.B55	0.F0.B58	0.F0.B57
PULLUP	0	0	0	0
DBL_W2[6]	0	0	0	1
DBL_W2[7]	0	0	1	0
DBL_W1[6]	0	1	0	1
DBL_W1[7]	0	1	1	0
DBL_E1[6]	1	0	0	1
DBL_E1[7]	1	0	1	0
DBL_E0[6]	1	1	0	1
DBL_E0[7]	1	1	1	0

CLK_INT:MUX.OMUX_S0	1.F0.B3	1.F0.B2	0.F0.B63
CLK_INT:MUX.OMUX_S3	1.F0.B0	1.F0.B4	1.F0.B1
CLK_INT:MUX.OMUX_S4	0.F0.B19	0.F0.B18	0.F0.B21
CLK_INT:MUX.OMUX_S5	0.F0.B16	0.F0.B17	0.F0.B20
NONE	0	0	0
OUT_BUFG[2]	0	0	1
OUT_BUFG[3]	0	1	0
OUT_BUFG[0]	1	0	1
OUT_BUFG[1]	1	1	0

`CLK_N_S3E`

This tile is used on Spartan 3E.

Tile CLK_N_S3E

Cells: 1

Switchbox CLK_INT

spartan3 CLK_N_S3E switchbox CLK_INT muxes OMUX_S0
Bits	Destination
OMUX_S0
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes OMUX_S3
Bits	Destination
OMUX_S3
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes OMUX_S4
Bits	Destination
OMUX_S4
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes OMUX_S5
Bits	Destination
OMUX_S5
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
IMUX_BUFG_CLK[0]
	Source
DBL_E1[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
IMUX_BUFG_CLK[1]
	Source
DBL_E1[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
IMUX_BUFG_CLK[2]
	Source
DBL_E1[5]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
IMUX_BUFG_CLK[3]
	Source
DBL_E1[7]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
IMUX_BUFG_SEL[0]
	Source
DBL_E1[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
IMUX_BUFG_SEL[1]
	Source
DBL_E1[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
IMUX_BUFG_SEL[2]
	Source
DBL_E1[5]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
IMUX_BUFG_SEL[3]
	Source
DBL_E1[7]

Bel BUFGMUX[0]

spartan3 CLK_N_S3E bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[0]
O	output	OUT_BUFG[0]
S	input	IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

spartan3 CLK_N_S3E bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[1]
O	output	OUT_BUFG[1]
S	input	IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

spartan3 CLK_N_S3E bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[2]
O	output	OUT_BUFG[2]
S	input	IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

spartan3 CLK_N_S3E bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[3]
O	output	OUT_BUFG[3]
S	input	IMUX_BUFG_SEL[3]

Bel GLOBALSIG_N[0]

spartan3 CLK_N_S3E bel GLOBALSIG_N[0]
Pin	Direction	Wires

Bel wires

spartan3 CLK_N_S3E bel wires
Wire	Pins
IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
IMUX_BUFG_SEL[0]	BUFGMUX[0].S
IMUX_BUFG_SEL[1]	BUFGMUX[1].S
IMUX_BUFG_SEL[2]	BUFGMUX[2].S
IMUX_BUFG_SEL[3]	BUFGMUX[3].S
OUT_BUFG[0]	BUFGMUX[0].O
OUT_BUFG[1]	BUFGMUX[1].O
OUT_BUFG[2]	BUFGMUX[2].O
OUT_BUFG[3]	BUFGMUX[3].O

Bitstream

spartan3 CLK_N_S3E rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_N_S3E rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

spartan3 CLK_N_S3E rect R0
Bit	Frame
Bit	F0
B63	CLK_INT:MUX.IMUX_BUFG_SEL[3][1]
B62	CLK_INT:MUX.IMUX_BUFG_CLK[3][1]
B61	CLK_INT:MUX.IMUX_BUFG_CLK[3][0]
B60	CLK_INT:MUX.IMUX_BUFG_SEL[3][0]
B59	CLK_INT:MUX.IMUX_BUFG_CLK[3][2]
B58	CLK_INT:MUX.IMUX_BUFG_CLK[3][3]
B57	BUFGMUX[3]:MUX.CLK[0]
B56	BUFGMUX[3]:MUX.CLK[4]
B55	BUFGMUX[3]:MUX.CLK[3]
B54	BUFGMUX[3]:MUX.CLK[1]
B53	BUFGMUX[3]:MUX.CLK[2]
B52	BUFGMUX[2]:MUX.CLK[0]
B51	BUFGMUX[2]:MUX.CLK[4]
B50	BUFGMUX[2]:MUX.CLK[3]
B49	BUFGMUX[2]:MUX.CLK[1]
B48	BUFGMUX[2]:MUX.CLK[2]
B47	CLK_INT:MUX.IMUX_BUFG_CLK[2][3]
B46	CLK_INT:MUX.IMUX_BUFG_CLK[2][2]
B45	CLK_INT:MUX.IMUX_BUFG_SEL[2][1]
B44	CLK_INT:MUX.IMUX_BUFG_CLK[2][1]
B43	CLK_INT:MUX.IMUX_BUFG_CLK[2][0]
B42	CLK_INT:MUX.IMUX_BUFG_SEL[2][0]
B41	CLK_INT:MUX.IMUX_BUFG_SEL[2][2]
B40	CLK_INT:MUX.IMUX_BUFG_SEL[2][3]
B39	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]
B38	BUFGMUX[2]:DISABLE_ATTR[0]
B37	BUFGMUX[1]:MUX.CLK[0]
B36	BUFGMUX[1]:MUX.CLK[4]
B35	BUFGMUX[1]:MUX.CLK[3]
B34	BUFGMUX[1]:MUX.CLK[1]
B33	BUFGMUX[1]:MUX.CLK[2]
B32	BUFGMUX[1]:DISABLE_ATTR[0]
B31	CLK_INT:MUX.IMUX_BUFG_CLK[1][3]
B30	CLK_INT:MUX.IMUX_BUFG_CLK[1][2]
B29	CLK_INT:MUX.IMUX_BUFG_SEL[1][1]
B28	CLK_INT:MUX.IMUX_BUFG_CLK[1][1]
B27	CLK_INT:MUX.IMUX_BUFG_CLK[1][0]
B26	CLK_INT:MUX.IMUX_BUFG_SEL[1][0]
B25	CLK_INT:MUX.IMUX_BUFG_SEL[1][2]
B24	CLK_INT:MUX.IMUX_BUFG_SEL[1][3]
B23	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]
B22	CLK_INT:MUX.OMUX_S4[0]
B21	CLK_INT:MUX.OMUX_S5[0]
B20	CLK_INT:MUX.OMUX_S4[2]
B19	CLK_INT:MUX.OMUX_S4[1]
B18	CLK_INT:MUX.OMUX_S5[1]
B17	CLK_INT:MUX.OMUX_S5[2]
B16	BUFGMUX[0]:MUX.CLK[0]
B15	BUFGMUX[0]:MUX.CLK[4]
B14	BUFGMUX[0]:MUX.CLK[3]
B13	BUFGMUX[0]:MUX.CLK[1]
B12	BUFGMUX[0]:MUX.CLK[2]
B11	BUFGMUX[0]:DISABLE_ATTR[0]
B10	CLK_INT:MUX.IMUX_BUFG_CLK[0][3]
B9	CLK_INT:MUX.IMUX_BUFG_CLK[0][2]
B8	CLK_INT:MUX.IMUX_BUFG_SEL[0][1]
B7	CLK_INT:MUX.IMUX_BUFG_CLK[0][1]
B6	CLK_INT:MUX.IMUX_BUFG_CLK[0][0]
B5	CLK_INT:MUX.IMUX_BUFG_SEL[0][0]
B4	CLK_INT:MUX.IMUX_BUFG_SEL[0][2]
B3	CLK_INT:MUX.IMUX_BUFG_SEL[0][3]
B2	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]
B1	BUFGMUX[3]:DISABLE_ATTR[0]
B0	-

spartan3 CLK_N_S3E rect R1
Bit	Frame
Bit	F0
B8	CLK_INT:MUX.OMUX_S3[0]
B7	CLK_INT:MUX.OMUX_S0[1]
B6	CLK_INT:MUX.OMUX_S0[2]
B5	CLK_INT:MUX.OMUX_S3[1]
B4	CLK_INT:MUX.OMUX_S3[2]
B3	CLK_INT:MUX.OMUX_S0[0]
B2	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]
B1	CLK_INT:MUX.IMUX_BUFG_SEL[3][3]
B0	CLK_INT:MUX.IMUX_BUFG_SEL[3][2]

BUFGMUX[0]:DISABLE_ATTR	0.F0.B11
BUFGMUX[1]:DISABLE_ATTR	0.F0.B32
BUFGMUX[2]:DISABLE_ATTR	0.F0.B38
BUFGMUX[3]:DISABLE_ATTR	0.F0.B1
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B15	0.F0.B14	0.F0.B12	0.F0.B13	0.F0.B16
BUFGMUX[1]:MUX.CLK	0.F0.B36	0.F0.B35	0.F0.B33	0.F0.B34	0.F0.B37
BUFGMUX[2]:MUX.CLK	0.F0.B51	0.F0.B50	0.F0.B48	0.F0.B49	0.F0.B52
BUFGMUX[3]:MUX.CLK	0.F0.B56	0.F0.B55	0.F0.B53	0.F0.B54	0.F0.B57
INT	0	0	0	0	1
CKIL	0	0	0	1	0
CKIR	0	0	1	0	0
DCM_OUT_L	0	1	0	0	0
DCM_OUT_R	1	0	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F0.B2
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F0.B23
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F0.B39
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	1.F0.B2
inverted	~[0]

CLK_INT:MUX.IMUX_BUFG_CLK[0]	0.F0.B10	0.F0.B9	0.F0.B7	0.F0.B6
CLK_INT:MUX.IMUX_BUFG_SEL[0]	0.F0.B3	0.F0.B4	0.F0.B8	0.F0.B5
PULLUP	0	0	0	0
DBL_W2[0]	0	0	0	1
DBL_W2[1]	0	0	1	0
DBL_W1[0]	0	1	0	1
DBL_W1[1]	0	1	1	0
DBL_E1[0]	1	0	0	1
DBL_E1[1]	1	0	1	0
DBL_E0[0]	1	1	0	1
DBL_E0[1]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[1]	0.F0.B31	0.F0.B30	0.F0.B28	0.F0.B27
CLK_INT:MUX.IMUX_BUFG_SEL[1]	0.F0.B24	0.F0.B25	0.F0.B29	0.F0.B26
PULLUP	0	0	0	0
DBL_W2[2]	0	0	0	1
DBL_W2[3]	0	0	1	0
DBL_W1[2]	0	1	0	1
DBL_W1[3]	0	1	1	0
DBL_E1[2]	1	0	0	1
DBL_E1[3]	1	0	1	0
DBL_E0[2]	1	1	0	1
DBL_E0[3]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[2]	0.F0.B47	0.F0.B46	0.F0.B44	0.F0.B43
CLK_INT:MUX.IMUX_BUFG_SEL[2]	0.F0.B40	0.F0.B41	0.F0.B45	0.F0.B42
PULLUP	0	0	0	0
DBL_W2[4]	0	0	0	1
DBL_W2[5]	0	0	1	0
DBL_W1[4]	0	1	0	1
DBL_W1[5]	0	1	1	0
DBL_E1[4]	1	0	0	1
DBL_E1[5]	1	0	1	0
DBL_E0[4]	1	1	0	1
DBL_E0[5]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[3]	0.F0.B58	0.F0.B59	0.F0.B62	0.F0.B61
CLK_INT:MUX.IMUX_BUFG_SEL[3]	1.F0.B1	1.F0.B0	0.F0.B63	0.F0.B60
PULLUP	0	0	0	0
DBL_W2[6]	0	0	0	1
DBL_W2[7]	0	0	1	0
DBL_W1[6]	0	1	0	1
DBL_W1[7]	0	1	1	0
DBL_E1[6]	1	0	0	1
DBL_E1[7]	1	0	1	0
DBL_E0[6]	1	1	0	1
DBL_E0[7]	1	1	1	0

CLK_INT:MUX.OMUX_S0	1.F0.B6	1.F0.B7	1.F0.B3
CLK_INT:MUX.OMUX_S3	1.F0.B4	1.F0.B5	1.F0.B8
CLK_INT:MUX.OMUX_S4	0.F0.B20	0.F0.B19	0.F0.B22
CLK_INT:MUX.OMUX_S5	0.F0.B17	0.F0.B18	0.F0.B21
NONE	0	0	0
OUT_BUFG[2]	0	0	1
OUT_BUFG[3]	0	1	0
OUT_BUFG[0]	1	0	1
OUT_BUFG[1]	1	1	0

`CLK_N_S3A`

This tile is used on Spartan 3A and 3A DSP.

Tile CLK_N_S3A

Cells: 1

Switchbox CLK_INT

spartan3 CLK_N_S3A switchbox CLK_INT muxes OMUX_S0
Bits	Destination
OMUX_S0
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes OMUX_S3
Bits	Destination
OMUX_S3
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes OMUX_S4
Bits	Destination
OMUX_S4
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes OMUX_S5
Bits	Destination
OMUX_S5
	Source
OUT_BUFG[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
IMUX_BUFG_CLK[0]
	Source
DBL_E1[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
IMUX_BUFG_CLK[1]
	Source
DBL_E1[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
IMUX_BUFG_CLK[2]
	Source
DBL_E1[5]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
IMUX_BUFG_CLK[3]
	Source
DBL_E1[7]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
IMUX_BUFG_SEL[0]
	Source
DBL_E1[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
IMUX_BUFG_SEL[1]
	Source
DBL_E1[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
IMUX_BUFG_SEL[2]
	Source
DBL_E1[5]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
IMUX_BUFG_SEL[3]
	Source
DBL_E1[7]

Bel BUFGMUX[0]

spartan3 CLK_N_S3A bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[0]
O	output	OUT_BUFG[0]
S	input	IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

spartan3 CLK_N_S3A bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[1]
O	output	OUT_BUFG[1]
S	input	IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

spartan3 CLK_N_S3A bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[2]
O	output	OUT_BUFG[2]
S	input	IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

spartan3 CLK_N_S3A bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	IMUX_BUFG_CLK[3]
O	output	OUT_BUFG[3]
S	input	IMUX_BUFG_SEL[3]

Bel GLOBALSIG_N[0]

spartan3 CLK_N_S3A bel GLOBALSIG_N[0]
Pin	Direction	Wires

Bel wires

spartan3 CLK_N_S3A bel wires
Wire	Pins
IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
IMUX_BUFG_SEL[0]	BUFGMUX[0].S
IMUX_BUFG_SEL[1]	BUFGMUX[1].S
IMUX_BUFG_SEL[2]	BUFGMUX[2].S
IMUX_BUFG_SEL[3]	BUFGMUX[3].S
OUT_BUFG[0]	BUFGMUX[0].O
OUT_BUFG[1]	BUFGMUX[1].O
OUT_BUFG[2]	BUFGMUX[2].O
OUT_BUFG[3]	BUFGMUX[3].O

Bitstream

spartan3 CLK_N_S3A rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLK_N_S3A rect TERM
Bit	Frame
Bit	F0	F1
B15	-	-
B14	-	-
B13	-	-
B12	-	-
B11	-	-
B10	-	-
B9	-	-
B8	-	-
B7	-	-
B6	-	-
B5	-	-
B4	-	-
B3	-	-
B2	-	-
B1	-	-
B0	-	-

### Bitstream

spartan3 CLK_N_S3A rect R0
Bit	Frame
Bit	F0
B63	CLK_INT:MUX.IMUX_BUFG_SEL[3][1]
B62	CLK_INT:MUX.IMUX_BUFG_CLK[3][1]
B61	CLK_INT:MUX.IMUX_BUFG_CLK[3][0]
B60	CLK_INT:MUX.IMUX_BUFG_SEL[3][0]
B59	CLK_INT:MUX.IMUX_BUFG_CLK[3][2]
B58	CLK_INT:MUX.IMUX_BUFG_CLK[3][3]
B57	BUFGMUX[3]:MUX.CLK[0]
B56	BUFGMUX[3]:MUX.CLK[4]
B55	BUFGMUX[3]:MUX.CLK[3]
B54	BUFGMUX[3]:MUX.CLK[1]
B53	BUFGMUX[3]:MUX.CLK[2]
B52	BUFGMUX[2]:MUX.CLK[0]
B51	BUFGMUX[2]:MUX.CLK[4]
B50	BUFGMUX[2]:MUX.CLK[3]
B49	BUFGMUX[2]:MUX.CLK[1]
B48	BUFGMUX[2]:MUX.CLK[2]
B47	CLK_INT:MUX.IMUX_BUFG_CLK[2][3]
B46	CLK_INT:MUX.IMUX_BUFG_CLK[2][2]
B45	CLK_INT:MUX.IMUX_BUFG_SEL[2][0]
B44	CLK_INT:MUX.IMUX_BUFG_CLK[2][0]
B43	CLK_INT:MUX.IMUX_BUFG_CLK[2][1]
B42	CLK_INT:MUX.IMUX_BUFG_SEL[2][1]
B41	CLK_INT:MUX.IMUX_BUFG_SEL[2][2]
B40	CLK_INT:MUX.IMUX_BUFG_SEL[2][3]
B39	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]
B38	BUFGMUX[2]:DISABLE_ATTR[0]
B37	BUFGMUX[1]:MUX.CLK[0]
B36	BUFGMUX[1]:MUX.CLK[4]
B35	BUFGMUX[1]:MUX.CLK[3]
B34	BUFGMUX[1]:MUX.CLK[1]
B33	BUFGMUX[1]:MUX.CLK[2]
B32	BUFGMUX[1]:DISABLE_ATTR[0]
B31	CLK_INT:MUX.IMUX_BUFG_CLK[1][3]
B30	CLK_INT:MUX.IMUX_BUFG_CLK[1][2]
B29	CLK_INT:MUX.IMUX_BUFG_SEL[1][0]
B28	CLK_INT:MUX.IMUX_BUFG_CLK[1][0]
B27	CLK_INT:MUX.IMUX_BUFG_CLK[1][1]
B26	CLK_INT:MUX.IMUX_BUFG_SEL[1][1]
B25	CLK_INT:MUX.IMUX_BUFG_SEL[1][2]
B24	CLK_INT:MUX.IMUX_BUFG_SEL[1][3]
B23	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]
B22	CLK_INT:MUX.OMUX_S4[0]
B21	CLK_INT:MUX.OMUX_S5[0]
B20	CLK_INT:MUX.OMUX_S4[2]
B19	CLK_INT:MUX.OMUX_S4[1]
B18	CLK_INT:MUX.OMUX_S5[1]
B17	CLK_INT:MUX.OMUX_S5[2]
B16	BUFGMUX[0]:MUX.CLK[0]
B15	BUFGMUX[0]:MUX.CLK[4]
B14	BUFGMUX[0]:MUX.CLK[3]
B13	BUFGMUX[0]:MUX.CLK[1]
B12	BUFGMUX[0]:MUX.CLK[2]
B11	BUFGMUX[0]:DISABLE_ATTR[0]
B10	CLK_INT:MUX.IMUX_BUFG_CLK[0][3]
B9	CLK_INT:MUX.IMUX_BUFG_CLK[0][2]
B8	CLK_INT:MUX.IMUX_BUFG_SEL[0][1]
B7	CLK_INT:MUX.IMUX_BUFG_CLK[0][1]
B6	CLK_INT:MUX.IMUX_BUFG_CLK[0][0]
B5	CLK_INT:MUX.IMUX_BUFG_SEL[0][0]
B4	CLK_INT:MUX.IMUX_BUFG_SEL[0][2]
B3	CLK_INT:MUX.IMUX_BUFG_SEL[0][3]
B2	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]
B1	BUFGMUX[3]:DISABLE_ATTR[0]
B0	-

spartan3 CLK_N_S3A rect R1
Bit	Frame
Bit	F0	F1
B5	-	CLK_INT:MUX.OMUX_S3[1]
B4	-	CLK_INT:MUX.OMUX_S3[2]
B3	-	CLK_INT:MUX.OMUX_S0[0]
B2	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]	CLK_INT:MUX.OMUX_S0[2]
B1	CLK_INT:MUX.IMUX_BUFG_SEL[3][3]	CLK_INT:MUX.OMUX_S3[0]
B0	CLK_INT:MUX.IMUX_BUFG_SEL[3][2]	CLK_INT:MUX.OMUX_S0[1]

BUFGMUX[0]:DISABLE_ATTR	0.F0.B11
BUFGMUX[1]:DISABLE_ATTR	0.F0.B32
BUFGMUX[2]:DISABLE_ATTR	0.F0.B38
BUFGMUX[3]:DISABLE_ATTR	0.F0.B1
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B15	0.F0.B14	0.F0.B12	0.F0.B13	0.F0.B16
BUFGMUX[1]:MUX.CLK	0.F0.B36	0.F0.B35	0.F0.B33	0.F0.B34	0.F0.B37
BUFGMUX[2]:MUX.CLK	0.F0.B51	0.F0.B50	0.F0.B48	0.F0.B49	0.F0.B52
BUFGMUX[3]:MUX.CLK	0.F0.B56	0.F0.B55	0.F0.B53	0.F0.B54	0.F0.B57
INT	0	0	0	0	1
CKIL	0	0	0	1	0
CKIR	0	0	1	0	0
DCM_OUT_L	0	1	0	0	0
DCM_OUT_R	1	0	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F0.B2
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F0.B23
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F0.B39
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	1.F0.B2
inverted	~[0]

CLK_INT:MUX.IMUX_BUFG_CLK[0]	0.F0.B10	0.F0.B9	0.F0.B7	0.F0.B6
CLK_INT:MUX.IMUX_BUFG_SEL[0]	0.F0.B3	0.F0.B4	0.F0.B8	0.F0.B5
PULLUP	0	0	0	0
DBL_W2[0]	0	0	0	1
DBL_W2[1]	0	0	1	0
DBL_W1[0]	0	1	0	1
DBL_W1[1]	0	1	1	0
DBL_E1[0]	1	0	0	1
DBL_E1[1]	1	0	1	0
DBL_E0[0]	1	1	0	1
DBL_E0[1]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[1]	0.F0.B31	0.F0.B30	0.F0.B27	0.F0.B28
CLK_INT:MUX.IMUX_BUFG_SEL[1]	0.F0.B24	0.F0.B25	0.F0.B26	0.F0.B29
PULLUP	0	0	0	0
DBL_W2[2]	0	0	0	1
DBL_W2[3]	0	0	1	0
DBL_W1[2]	0	1	0	1
DBL_W1[3]	0	1	1	0
DBL_E1[2]	1	0	0	1
DBL_E1[3]	1	0	1	0
DBL_E0[2]	1	1	0	1
DBL_E0[3]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[2]	0.F0.B47	0.F0.B46	0.F0.B43	0.F0.B44
CLK_INT:MUX.IMUX_BUFG_SEL[2]	0.F0.B40	0.F0.B41	0.F0.B42	0.F0.B45
PULLUP	0	0	0	0
DBL_W2[4]	0	0	0	1
DBL_W2[5]	0	0	1	0
DBL_W1[4]	0	1	0	1
DBL_W1[5]	0	1	1	0
DBL_E1[4]	1	0	0	1
DBL_E1[5]	1	0	1	0
DBL_E0[4]	1	1	0	1
DBL_E0[5]	1	1	1	0

CLK_INT:MUX.IMUX_BUFG_CLK[3]	0.F0.B58	0.F0.B59	0.F0.B62	0.F0.B61
CLK_INT:MUX.IMUX_BUFG_SEL[3]	1.F0.B1	1.F0.B0	0.F0.B63	0.F0.B60
PULLUP	0	0	0	0
DBL_W2[6]	0	0	0	1
DBL_W2[7]	0	0	1	0
DBL_W1[6]	0	1	0	1
DBL_W1[7]	0	1	1	0
DBL_E1[6]	1	0	0	1
DBL_E1[7]	1	0	1	0
DBL_E0[6]	1	1	0	1
DBL_E0[7]	1	1	1	0

CLK_INT:MUX.OMUX_S0	1.F1.B2	1.F1.B0	1.F1.B3
CLK_INT:MUX.OMUX_S3	1.F1.B4	1.F1.B5	1.F1.B1
CLK_INT:MUX.OMUX_S4	0.F0.B20	0.F0.B19	0.F0.B22
CLK_INT:MUX.OMUX_S5	0.F0.B17	0.F0.B18	0.F0.B21
NONE	0	0	0
OUT_BUFG[2]	0	0	1
OUT_BUFG[3]	0	1	0
OUT_BUFG[0]	1	0	1
OUT_BUFG[1]	1	1	0

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