Primary global buffers

TODO: document

Bitstream — south tiles

The CLK_S_* tiles use two bitstream tiles:

tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the bottom interconnect row
tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the low special area (used for bottom IOB tiles and clock rows in normal columns)

On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH_S_S3A tile.

`CLK_S_S3`

This tile is used on Spartan 3.

Tile CLK_S_S3

Cells: 2

Switchbox CLK_INT

spartan3 CLK_S_S3 switchbox CLK_INT permanent buffers
Destination	Source
CELL[1].DCM_CLKPAD[0]	CELL[1].OUT_CLKPAD[0]
CELL[1].DCM_CLKPAD[1]	CELL[1].OUT_CLKPAD[1]
CELL[1].DCM_CLKPAD[2]	CELL[0].OUT_CLKPAD[0]
CELL[1].DCM_CLKPAD[3]	CELL[0].OUT_CLKPAD[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes OMUX_N10
Bits			Destination
TERM[0][8]	TERM[0][9]	MAIN[0][0]	CELL[0].OMUX_N10
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_S[2]
0	1	0	CELL[1].GCLK_S[3]
1	0	1	CELL[1].GCLK_S[0]
1	1	0	CELL[1].GCLK_S[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes OMUX_N11
Bits			Destination
TERM[0][11]	TERM[0][7]	TERM[0][10]	CELL[0].OMUX_N11
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_S[2]
0	1	0	CELL[1].GCLK_S[3]
1	0	1	CELL[1].GCLK_S[0]
1	1	0	CELL[1].GCLK_S[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes OMUX_N12
Bits			Destination
MAIN[0][44]	MAIN[0][45]	MAIN[0][42]	CELL[0].OMUX_N12
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_S[2]
0	1	0	CELL[1].GCLK_S[3]
1	0	1	CELL[1].GCLK_S[0]
1	1	0	CELL[1].GCLK_S[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes OMUX_N15
Bits			Destination
MAIN[0][47]	MAIN[0][46]	MAIN[0][43]	CELL[0].OMUX_N15
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_S[2]
0	1	0	CELL[1].GCLK_S[3]
1	0	1	CELL[1].GCLK_S[0]
1	1	0	CELL[1].GCLK_S[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits				Destination
MAIN[0][9]	MAIN[0][8]	MAIN[0][6]	MAIN[0][5]	CELL[1].IMUX_BUFG_CLK_INT[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[0]
0	0	1	0	CELL[0].DBL_W2[1]
0	1	0	1	CELL[0].DBL_W1[0]
0	1	1	0	CELL[0].DBL_W1[1]
1	0	0	1	CELL[0].DBL_E1[0]
1	0	1	0	CELL[0].DBL_E1[1]
1	1	0	1	CELL[0].DBL_E0[0]
1	1	1	0	CELL[0].DBL_E0[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits				Destination
MAIN[0][20]	MAIN[0][19]	MAIN[0][23]	MAIN[0][22]	CELL[1].IMUX_BUFG_CLK_INT[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[2]
0	0	1	0	CELL[0].DBL_W2[3]
0	1	0	1	CELL[0].DBL_W1[2]
0	1	1	0	CELL[0].DBL_W1[3]
1	0	0	1	CELL[0].DBL_E1[2]
1	0	1	0	CELL[0].DBL_E1[3]
1	1	0	1	CELL[0].DBL_E0[2]
1	1	1	0	CELL[0].DBL_E0[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits				Destination
MAIN[0][34]	MAIN[0][33]	MAIN[0][37]	MAIN[0][36]	CELL[1].IMUX_BUFG_CLK_INT[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[4]
0	0	1	0	CELL[0].DBL_W2[5]
0	1	0	1	CELL[0].DBL_W1[4]
0	1	1	0	CELL[0].DBL_W1[5]
1	0	0	1	CELL[0].DBL_E1[4]
1	0	1	0	CELL[0].DBL_E1[5]
1	1	0	1	CELL[0].DBL_E0[4]
1	1	1	0	CELL[0].DBL_E0[5]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits				Destination
MAIN[0][54]	MAIN[0][53]	MAIN[0][57]	MAIN[0][56]	CELL[1].IMUX_BUFG_CLK_INT[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[6]
0	0	1	0	CELL[0].DBL_W2[7]
0	1	0	1	CELL[0].DBL_W1[6]
0	1	1	0	CELL[0].DBL_W1[7]
1	0	0	1	CELL[0].DBL_E1[6]
1	0	1	0	CELL[0].DBL_E1[7]
1	1	0	1	CELL[0].DBL_E0[6]
1	1	1	0	CELL[0].DBL_E0[7]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits				Destination
MAIN[0][10]	MAIN[0][11]	MAIN[0][13]	MAIN[0][12]	CELL[1].IMUX_BUFG_CLK[0]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[0]
0	0	1	0	CELL[1].OUT_CLKPAD[0]
0	1	0	0	CELL[1].DCM_BUS[0]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[0]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits				Destination
MAIN[0][14]	MAIN[0][15]	MAIN[0][17]	MAIN[0][16]	CELL[1].IMUX_BUFG_CLK[1]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[1]
0	0	1	0	CELL[1].OUT_CLKPAD[1]
0	1	0	0	CELL[1].DCM_BUS[1]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits				Destination
MAIN[0][28]	MAIN[0][29]	MAIN[0][30]	MAIN[0][31]	CELL[1].IMUX_BUFG_CLK[2]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[0]
0	0	1	0	CELL[0].DCM_BUS[2]
0	1	0	0	CELL[1].DCM_BUS[2]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[2]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits				Destination
MAIN[0][48]	MAIN[0][49]	MAIN[0][50]	MAIN[0][51]	CELL[1].IMUX_BUFG_CLK[3]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[1]
0	0	1	0	CELL[0].DCM_BUS[3]
0	1	0	0	CELL[1].DCM_BUS[3]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits				Destination
MAIN[0][2]	MAIN[0][3]	MAIN[0][7]	MAIN[0][4]	CELL[1].IMUX_BUFG_SEL[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[0]
0	0	1	0	CELL[0].DBL_W2[1]
0	1	0	1	CELL[0].DBL_W1[0]
0	1	1	0	CELL[0].DBL_W1[1]
1	0	0	1	CELL[0].DBL_E1[0]
1	0	1	0	CELL[0].DBL_E1[1]
1	1	0	1	CELL[0].DBL_E0[0]
1	1	1	0	CELL[0].DBL_E0[1]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits				Destination
MAIN[0][25]	MAIN[0][26]	MAIN[0][24]	MAIN[0][21]	CELL[1].IMUX_BUFG_SEL[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[2]
0	0	1	0	CELL[0].DBL_W2[3]
0	1	0	1	CELL[0].DBL_W1[2]
0	1	1	0	CELL[0].DBL_W1[3]
1	0	0	1	CELL[0].DBL_E1[2]
1	0	1	0	CELL[0].DBL_E1[3]
1	1	0	1	CELL[0].DBL_E0[2]
1	1	1	0	CELL[0].DBL_E0[3]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits				Destination
MAIN[0][39]	MAIN[0][40]	MAIN[0][38]	MAIN[0][35]	CELL[1].IMUX_BUFG_SEL[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[4]
0	0	1	0	CELL[0].DBL_W2[5]
0	1	0	1	CELL[0].DBL_W1[4]
0	1	1	0	CELL[0].DBL_W1[5]
1	0	0	1	CELL[0].DBL_E1[4]
1	0	1	0	CELL[0].DBL_E1[5]
1	1	0	1	CELL[0].DBL_E0[4]
1	1	1	0	CELL[0].DBL_E0[5]

spartan3 CLK_S_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits				Destination
MAIN[0][59]	MAIN[0][60]	MAIN[0][58]	MAIN[0][55]	CELL[1].IMUX_BUFG_SEL[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[6]
0	0	1	0	CELL[0].DBL_W2[7]
0	1	0	1	CELL[0].DBL_W1[6]
0	1	1	0	CELL[0].DBL_W1[7]
1	0	0	1	CELL[0].DBL_E1[6]
1	0	1	0	CELL[0].DBL_E1[7]
1	1	0	1	CELL[0].DBL_E0[6]
1	1	1	0	CELL[0].DBL_E0[7]

Bels BUFGMUX

spartan3 CLK_S_S3 bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
I0	in	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[2]	CELL[1].IMUX_BUFG_CLK[3]
I1	in	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[3]	CELL[1].IMUX_BUFG_CLK[2]
S	in	CELL[1].IMUX_BUFG_SEL[0] invert by !MAIN[0][1]	CELL[1].IMUX_BUFG_SEL[1] invert by !MAIN[0][27]	CELL[1].IMUX_BUFG_SEL[2] invert by !MAIN[0][41]	CELL[1].IMUX_BUFG_SEL[3] invert by !MAIN[0][61]
O	out	CELL[1].GCLK_S[0]	CELL[1].GCLK_S[1]	CELL[1].GCLK_S[2]	CELL[1].GCLK_S[3]

spartan3 CLK_S_S3 bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
INIT_OUT bit 0	MAIN[0][62]	MAIN[0][18]	MAIN[0][32]	MAIN[0][52]

Bels GLOBALSIG_BUFG

spartan3 CLK_S_S3 bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]

spartan3 CLK_S_S3 bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]
GWE_ENABLE	!MAIN[0][63]

Bel wires

spartan3 CLK_S_S3 bel wires
Wire	Pins
CELL[1].GCLK_S[0]	BUFGMUX[0].O
CELL[1].GCLK_S[1]	BUFGMUX[1].O
CELL[1].GCLK_S[2]	BUFGMUX[2].O
CELL[1].GCLK_S[3]	BUFGMUX[3].O
CELL[1].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0, BUFGMUX[1].I1
CELL[1].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0, BUFGMUX[0].I1
CELL[1].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0, BUFGMUX[3].I1
CELL[1].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0, BUFGMUX[2].I1
CELL[1].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[1].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[1].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[1].IMUX_BUFG_SEL[3]	BUFGMUX[3].S

Bitstream

spartan3 CLK_S_S3 rect MAIN
Bit	Frame
Bit	F0
B63	GLOBALSIG_BUFG[0]: ! GWE_ENABLE
B62	BUFGMUX[0]: INIT_OUT bit 0
B61	BUFGMUX[3]: !invert S
B60	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 2
B59	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 3
B58	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 1
B57	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 1
B56	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 0
B55	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 0
B54	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 3
B53	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 2
B52	BUFGMUX[3]: INIT_OUT bit 0
B51	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 0
B50	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 1
B49	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 2
B48	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 3
B47	CLK_INT: mux CELL[0].OMUX_N15 bit 2
B46	CLK_INT: mux CELL[0].OMUX_N15 bit 1
B45	CLK_INT: mux CELL[0].OMUX_N12 bit 1
B44	CLK_INT: mux CELL[0].OMUX_N12 bit 2
B43	CLK_INT: mux CELL[0].OMUX_N15 bit 0
B42	CLK_INT: mux CELL[0].OMUX_N12 bit 0
B41	BUFGMUX[2]: !invert S
B40	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 2
B39	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 3
B38	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 1
B37	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 1
B36	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 0
B35	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 0
B34	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 3
B33	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 2
B32	BUFGMUX[2]: INIT_OUT bit 0
B31	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 0
B30	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 1
B29	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 2
B28	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 3
B27	BUFGMUX[1]: !invert S
B26	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 2
B25	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 3
B24	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 1
B23	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 1
B22	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 0
B21	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 0
B20	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 3
B19	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 2
B18	BUFGMUX[1]: INIT_OUT bit 0
B17	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 1
B16	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 0
B15	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 2
B14	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 3
B13	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 1
B12	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 0
B11	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 2
B10	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 3
B9	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 3
B8	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 2
B7	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 1
B6	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 1
B5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 0
B4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 0
B3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 2
B2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 3
B1	BUFGMUX[0]: !invert S
B0	CLK_INT: mux CELL[0].OMUX_N10 bit 0

spartan3 CLK_S_S3 rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	CLK_INT: mux CELL[0].OMUX_N11 bit 2
B10	CLK_INT: mux CELL[0].OMUX_N11 bit 0
B9	CLK_INT: mux CELL[0].OMUX_N10 bit 1
B8	CLK_INT: mux CELL[0].OMUX_N10 bit 2
B7	CLK_INT: mux CELL[0].OMUX_N11 bit 1
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

`CLK_S_FC`

This tile is used on FPGAcore.

Tile CLK_S_FC

Cells: 2

Switchbox CLK_INT

spartan3 CLK_S_FC switchbox CLK_INT muxes OMUX_N10
Bits			Destination
TERM[0][8]	TERM[0][9]	MAIN[0][0]	CELL[0].OMUX_N10
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_S[2]
0	1	0	CELL[1].GCLK_S[3]
1	0	1	CELL[1].GCLK_S[0]
1	1	0	CELL[1].GCLK_S[1]

spartan3 CLK_S_FC switchbox CLK_INT muxes OMUX_N11
Bits			Destination
TERM[0][11]	TERM[0][7]	TERM[0][10]	CELL[0].OMUX_N11
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_S[2]
0	1	0	CELL[1].GCLK_S[3]
1	0	1	CELL[1].GCLK_S[0]
1	1	0	CELL[1].GCLK_S[1]

spartan3 CLK_S_FC switchbox CLK_INT muxes OMUX_N12
Bits			Destination
MAIN[0][44]	MAIN[0][45]	MAIN[0][42]	CELL[0].OMUX_N12
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_S[2]
0	1	0	CELL[1].GCLK_S[3]
1	0	1	CELL[1].GCLK_S[0]
1	1	0	CELL[1].GCLK_S[1]

spartan3 CLK_S_FC switchbox CLK_INT muxes OMUX_N15
Bits			Destination
MAIN[0][47]	MAIN[0][46]	MAIN[0][43]	CELL[0].OMUX_N15
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_S[2]
0	1	0	CELL[1].GCLK_S[3]
1	0	1	CELL[1].GCLK_S[0]
1	1	0	CELL[1].GCLK_S[1]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits				Destination
MAIN[0][9]	MAIN[0][8]	MAIN[0][6]	MAIN[0][5]	CELL[1].IMUX_BUFG_CLK_INT[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[0]
0	0	1	0	CELL[0].DBL_W2[1]
0	1	0	1	CELL[0].DBL_W1[0]
0	1	1	0	CELL[0].DBL_W1[1]
1	0	0	1	CELL[0].DBL_E1[0]
1	0	1	0	CELL[0].DBL_E1[1]
1	1	0	1	CELL[0].DBL_E0[0]
1	1	1	0	CELL[0].DBL_E0[1]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits				Destination
MAIN[0][20]	MAIN[0][19]	MAIN[0][23]	MAIN[0][22]	CELL[1].IMUX_BUFG_CLK_INT[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[2]
0	0	1	0	CELL[0].DBL_W2[3]
0	1	0	1	CELL[0].DBL_W1[2]
0	1	1	0	CELL[0].DBL_W1[3]
1	0	0	1	CELL[0].DBL_E1[2]
1	0	1	0	CELL[0].DBL_E1[3]
1	1	0	1	CELL[0].DBL_E0[2]
1	1	1	0	CELL[0].DBL_E0[3]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits				Destination
MAIN[0][34]	MAIN[0][33]	MAIN[0][37]	MAIN[0][36]	CELL[1].IMUX_BUFG_CLK_INT[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[4]
0	0	1	0	CELL[0].DBL_W2[5]
0	1	0	1	CELL[0].DBL_W1[4]
0	1	1	0	CELL[0].DBL_W1[5]
1	0	0	1	CELL[0].DBL_E1[4]
1	0	1	0	CELL[0].DBL_E1[5]
1	1	0	1	CELL[0].DBL_E0[4]
1	1	1	0	CELL[0].DBL_E0[5]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits				Destination
MAIN[0][54]	MAIN[0][53]	MAIN[0][57]	MAIN[0][56]	CELL[1].IMUX_BUFG_CLK_INT[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[6]
0	0	1	0	CELL[0].DBL_W2[7]
0	1	0	1	CELL[0].DBL_W1[6]
0	1	1	0	CELL[0].DBL_W1[7]
1	0	0	1	CELL[0].DBL_E1[6]
1	0	1	0	CELL[0].DBL_E1[7]
1	1	0	1	CELL[0].DBL_E0[6]
1	1	1	0	CELL[0].DBL_E0[7]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits		Destination
MAIN[0][10]	MAIN[0][13]	CELL[1].IMUX_BUFG_CLK[0]
		Source
0	0	off
0	1	CELL[1].OUT_CLKPAD[0]
1	0	CELL[1].IMUX_BUFG_CLK_INT[0]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits		Destination
MAIN[0][14]	MAIN[0][17]	CELL[1].IMUX_BUFG_CLK[1]
		Source
0	0	off
0	1	CELL[1].OUT_CLKPAD[1]
1	0	CELL[1].IMUX_BUFG_CLK_INT[1]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits		Destination
MAIN[0][28]	MAIN[0][31]	CELL[1].IMUX_BUFG_CLK[2]
		Source
0	0	off
0	1	CELL[0].OUT_CLKPAD[0]
1	0	CELL[1].IMUX_BUFG_CLK_INT[2]

spartan3 CLK_S_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits		Destination
MAIN[0][48]	MAIN[0][51]	CELL[1].IMUX_BUFG_CLK[3]
		Source
0	0	off
0	1	CELL[0].OUT_CLKPAD[1]
1	0	CELL[1].IMUX_BUFG_CLK_INT[3]

Bels BUFGMUX

spartan3 CLK_S_FC bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
I0	in	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[2]	CELL[1].IMUX_BUFG_CLK[3]
O	out	CELL[1].GCLK_S[0]	CELL[1].GCLK_S[1]	CELL[1].GCLK_S[2]	CELL[1].GCLK_S[3]

spartan3 CLK_S_FC bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]

Bels GLOBALSIG_BUFG

spartan3 CLK_S_FC bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]

spartan3 CLK_S_FC bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]
GWE_ENABLE	!MAIN[0][63]

Bel wires

spartan3 CLK_S_FC bel wires
Wire	Pins
CELL[1].GCLK_S[0]	BUFGMUX[0].O
CELL[1].GCLK_S[1]	BUFGMUX[1].O
CELL[1].GCLK_S[2]	BUFGMUX[2].O
CELL[1].GCLK_S[3]	BUFGMUX[3].O
CELL[1].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0
CELL[1].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0
CELL[1].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0
CELL[1].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0

Bitstream

spartan3 CLK_S_FC rect MAIN
Bit	Frame
Bit	F0
B63	GLOBALSIG_BUFG[0]: ! GWE_ENABLE
B62	-
B61	-
B60	-
B59	-
B58	-
B57	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 1
B56	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 0
B55	-
B54	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 3
B53	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 2
B52	-
B51	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 0
B50	-
B49	-
B48	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 1
B47	CLK_INT: mux CELL[0].OMUX_N15 bit 2
B46	CLK_INT: mux CELL[0].OMUX_N15 bit 1
B45	CLK_INT: mux CELL[0].OMUX_N12 bit 1
B44	CLK_INT: mux CELL[0].OMUX_N12 bit 2
B43	CLK_INT: mux CELL[0].OMUX_N15 bit 0
B42	CLK_INT: mux CELL[0].OMUX_N12 bit 0
B41	-
B40	-
B39	-
B38	-
B37	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 1
B36	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 0
B35	-
B34	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 3
B33	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 2
B32	-
B31	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 0
B30	-
B29	-
B28	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 1
B27	-
B26	-
B25	-
B24	-
B23	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 1
B22	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 0
B21	-
B20	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 3
B19	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 2
B18	-
B17	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 0
B16	-
B15	-
B14	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 1
B13	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 0
B12	-
B11	-
B10	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 1
B9	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 3
B8	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 2
B7	-
B6	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 1
B5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 0
B4	-
B3	-
B2	-
B1	-
B0	CLK_INT: mux CELL[0].OMUX_N10 bit 0

spartan3 CLK_S_FC rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	CLK_INT: mux CELL[0].OMUX_N11 bit 2
B10	CLK_INT: mux CELL[0].OMUX_N11 bit 0
B9	CLK_INT: mux CELL[0].OMUX_N10 bit 1
B8	CLK_INT: mux CELL[0].OMUX_N10 bit 2
B7	CLK_INT: mux CELL[0].OMUX_N11 bit 1
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

`CLK_S_S3E`

This tile is used on Spartan 3E.

Tile CLK_S_S3E

Cells: 8

Switchbox CLK_INT

spartan3 CLK_S_S3E switchbox CLK_INT permanent buffers
Destination	Source
CELL[3].DCM_CLKPAD[0]	CELL[3].OUT_CLKPAD[1]
CELL[3].DCM_CLKPAD[1]	CELL[3].OUT_CLKPAD[0]
CELL[3].DCM_CLKPAD[2]	CELL[1].OUT_CLKPAD[1]
CELL[3].DCM_CLKPAD[3]	CELL[1].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[0]	CELL[4].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[1]	CELL[4].OUT_CLKPAD[1]
CELL[4].DCM_CLKPAD[2]	CELL[5].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[3]	CELL[5].OUT_CLKPAD[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes OMUX_N10
Bits			Destination
TERM[0][12]	TERM[0][13]	TERM[0][8]	CELL[3].OMUX_N10
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_S[2]
0	1	0	CELL[4].GCLK_S[3]
1	0	1	CELL[4].GCLK_S[0]
1	1	0	CELL[4].GCLK_S[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes OMUX_N11
Bits			Destination
TERM[0][7]	TERM[0][14]	TERM[0][15]	CELL[3].OMUX_N11
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_S[2]
0	1	0	CELL[4].GCLK_S[3]
1	0	1	CELL[4].GCLK_S[0]
1	1	0	CELL[4].GCLK_S[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes OMUX_N12
Bits			Destination
MAIN[0][43]	MAIN[0][44]	MAIN[0][41]	CELL[3].OMUX_N12
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_S[2]
0	1	0	CELL[4].GCLK_S[3]
1	0	1	CELL[4].GCLK_S[0]
1	1	0	CELL[4].GCLK_S[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes OMUX_N15
Bits			Destination
MAIN[0][46]	MAIN[0][45]	MAIN[0][42]	CELL[3].OMUX_N15
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_S[2]
0	1	0	CELL[4].GCLK_S[3]
1	0	1	CELL[4].GCLK_S[0]
1	1	0	CELL[4].GCLK_S[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits				Destination
MAIN[0][54]	MAIN[0][53]	MAIN[0][56]	MAIN[0][57]	CELL[4].IMUX_BUFG_CLK_INT[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[6]
0	0	1	0	CELL[5].DBL_W0[7]
0	1	0	1	CELL[2].DBL_E0[6]
0	1	1	0	CELL[2].DBL_E0[7]
1	0	0	1	CELL[4].DBL_W0[6]
1	0	1	0	CELL[4].DBL_W0[7]
1	1	0	1	CELL[3].DBL_E0[6]
1	1	1	0	CELL[3].DBL_E0[7]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits				Destination
MAIN[0][33]	MAIN[0][32]	MAIN[0][35]	MAIN[0][36]	CELL[4].IMUX_BUFG_CLK_INT[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[4]
0	0	1	0	CELL[5].DBL_W0[5]
0	1	0	1	CELL[2].DBL_E0[4]
0	1	1	0	CELL[2].DBL_E0[5]
1	0	0	1	CELL[4].DBL_W0[4]
1	0	1	0	CELL[4].DBL_W0[5]
1	1	0	1	CELL[3].DBL_E0[4]
1	1	1	0	CELL[3].DBL_E0[5]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits				Destination
MAIN[0][17]	MAIN[0][16]	MAIN[0][19]	MAIN[0][20]	CELL[4].IMUX_BUFG_CLK_INT[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[2]
0	0	1	0	CELL[5].DBL_W0[3]
0	1	0	1	CELL[2].DBL_E0[2]
0	1	1	0	CELL[2].DBL_E0[3]
1	0	0	1	CELL[4].DBL_W0[2]
1	0	1	0	CELL[4].DBL_W0[3]
1	1	0	1	CELL[3].DBL_E0[2]
1	1	1	0	CELL[3].DBL_E0[3]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits				Destination
MAIN[0][4]	MAIN[0][5]	MAIN[0][1]	MAIN[0][2]	CELL[4].IMUX_BUFG_CLK_INT[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[0]
0	0	1	0	CELL[5].DBL_W0[1]
0	1	0	1	CELL[2].DBL_E0[0]
0	1	1	0	CELL[2].DBL_E0[1]
1	0	0	1	CELL[4].DBL_W0[0]
1	0	1	0	CELL[4].DBL_W0[1]
1	1	0	1	CELL[3].DBL_E0[0]
1	1	1	0	CELL[3].DBL_E0[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits					Destination
MAIN[0][47]	MAIN[0][48]	MAIN[0][51]	MAIN[0][49]	MAIN[0][50]	CELL[4].IMUX_BUFG_CLK[0]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[1].OUT_CLKPAD[0]
0	0	0	1	0	CELL[3].DCM_BUS[0]
0	0	1	0	0	CELL[4].OUT_CLKPAD[0]
0	1	0	0	0	CELL[4].DCM_BUS[0]
1	0	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[0]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits					Destination
MAIN[0][26]	MAIN[0][27]	MAIN[0][30]	MAIN[0][28]	MAIN[0][29]	CELL[4].IMUX_BUFG_CLK[1]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[1].OUT_CLKPAD[1]
0	0	0	1	0	CELL[3].DCM_BUS[1]
0	0	1	0	0	CELL[4].OUT_CLKPAD[1]
0	1	0	0	0	CELL[4].DCM_BUS[1]
1	0	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits					Destination
MAIN[0][15]	MAIN[0][11]	MAIN[0][12]	MAIN[0][13]	MAIN[0][14]	CELL[4].IMUX_BUFG_CLK[2]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[3].OUT_CLKPAD[0]
0	0	0	1	0	CELL[3].DCM_BUS[2]
0	0	1	0	0	CELL[4].DCM_BUS[2]
0	1	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[2]
1	0	0	0	0	CELL[5].OUT_CLKPAD[0]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits					Destination
MAIN[0][10]	MAIN[0][6]	MAIN[0][7]	MAIN[0][8]	MAIN[0][9]	CELL[4].IMUX_BUFG_CLK[3]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[3].OUT_CLKPAD[1]
0	0	0	1	0	CELL[3].DCM_BUS[3]
0	0	1	0	0	CELL[4].DCM_BUS[3]
0	1	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[3]
1	0	0	0	0	CELL[5].OUT_CLKPAD[1]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits				Destination
MAIN[0][59]	MAIN[0][60]	MAIN[0][55]	MAIN[0][58]	CELL[4].IMUX_BUFG_SEL[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[6]
0	0	1	0	CELL[5].DBL_W0[7]
0	1	0	1	CELL[2].DBL_E0[6]
0	1	1	0	CELL[2].DBL_E0[7]
1	0	0	1	CELL[4].DBL_W0[6]
1	0	1	0	CELL[4].DBL_W0[7]
1	1	0	1	CELL[3].DBL_E0[6]
1	1	1	0	CELL[3].DBL_E0[7]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits				Destination
MAIN[0][38]	MAIN[0][39]	MAIN[0][34]	MAIN[0][37]	CELL[4].IMUX_BUFG_SEL[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[4]
0	0	1	0	CELL[5].DBL_W0[5]
0	1	0	1	CELL[2].DBL_E0[4]
0	1	1	0	CELL[2].DBL_E0[5]
1	0	0	1	CELL[4].DBL_W0[4]
1	0	1	0	CELL[4].DBL_W0[5]
1	1	0	1	CELL[3].DBL_E0[4]
1	1	1	0	CELL[3].DBL_E0[5]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits				Destination
MAIN[0][22]	MAIN[0][23]	MAIN[0][18]	MAIN[0][21]	CELL[4].IMUX_BUFG_SEL[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[2]
0	0	1	0	CELL[5].DBL_W0[3]
0	1	0	1	CELL[2].DBL_E0[2]
0	1	1	0	CELL[2].DBL_E0[3]
1	0	0	1	CELL[4].DBL_W0[2]
1	0	1	0	CELL[4].DBL_W0[3]
1	1	0	1	CELL[3].DBL_E0[2]
1	1	1	0	CELL[3].DBL_E0[3]

spartan3 CLK_S_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits				Destination
TERM[0][11]	TERM[0][10]	MAIN[0][0]	MAIN[0][3]	CELL[4].IMUX_BUFG_SEL[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[0]
0	0	1	0	CELL[5].DBL_W0[1]
0	1	0	1	CELL[2].DBL_E0[0]
0	1	1	0	CELL[2].DBL_E0[1]
1	0	0	1	CELL[4].DBL_W0[0]
1	0	1	0	CELL[4].DBL_W0[1]
1	1	0	1	CELL[3].DBL_E0[0]
1	1	1	0	CELL[3].DBL_E0[1]

Bels BUFGMUX

spartan3 CLK_S_S3E bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
I0	in	CELL[4].IMUX_BUFG_CLK[0]	CELL[4].IMUX_BUFG_CLK[1]	CELL[4].IMUX_BUFG_CLK[2]	CELL[4].IMUX_BUFG_CLK[3]
I1	in	CELL[4].IMUX_BUFG_CLK[1]	CELL[4].IMUX_BUFG_CLK[0]	CELL[4].IMUX_BUFG_CLK[3]	CELL[4].IMUX_BUFG_CLK[2]
S	in	CELL[4].IMUX_BUFG_SEL[0] invert by !MAIN[0][61]	CELL[4].IMUX_BUFG_SEL[1] invert by !MAIN[0][40]	CELL[4].IMUX_BUFG_SEL[2] invert by !MAIN[0][24]	CELL[4].IMUX_BUFG_SEL[3] invert by !TERM[0][9]
O	out	CELL[4].GCLK_S[0]	CELL[4].GCLK_S[1]	CELL[4].GCLK_S[2]	CELL[4].GCLK_S[3]

spartan3 CLK_S_S3E bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
INIT_OUT bit 0	MAIN[0][52]	MAIN[0][31]	MAIN[0][25]	MAIN[0][62]

Bels GLOBALSIG_BUFG

spartan3 CLK_S_S3E bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]

spartan3 CLK_S_S3E bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]
GWE_ENABLE	!MAIN[0][63]

Bel wires

spartan3 CLK_S_S3E bel wires
Wire	Pins
CELL[4].GCLK_S[0]	BUFGMUX[0].O
CELL[4].GCLK_S[1]	BUFGMUX[1].O
CELL[4].GCLK_S[2]	BUFGMUX[2].O
CELL[4].GCLK_S[3]	BUFGMUX[3].O
CELL[4].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0, BUFGMUX[1].I1
CELL[4].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0, BUFGMUX[0].I1
CELL[4].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0, BUFGMUX[3].I1
CELL[4].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0, BUFGMUX[2].I1
CELL[4].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[4].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[4].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[4].IMUX_BUFG_SEL[3]	BUFGMUX[3].S

Bitstream

spartan3 CLK_S_S3E rect MAIN
Bit	Frame
Bit	F0
B63	GLOBALSIG_BUFG[0]: ! GWE_ENABLE
B62	BUFGMUX[3]: INIT_OUT bit 0
B61	BUFGMUX[0]: !invert S
B60	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 2
B59	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 3
B58	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 0
B57	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 0
B56	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 1
B55	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 1
B54	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 3
B53	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 2
B52	BUFGMUX[0]: INIT_OUT bit 0
B51	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 2
B50	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 0
B49	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 1
B48	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 3
B47	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 4
B46	CLK_INT: mux CELL[3].OMUX_N15 bit 2
B45	CLK_INT: mux CELL[3].OMUX_N15 bit 1
B44	CLK_INT: mux CELL[3].OMUX_N12 bit 1
B43	CLK_INT: mux CELL[3].OMUX_N12 bit 2
B42	CLK_INT: mux CELL[3].OMUX_N15 bit 0
B41	CLK_INT: mux CELL[3].OMUX_N12 bit 0
B40	BUFGMUX[1]: !invert S
B39	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 2
B38	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 3
B37	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 0
B36	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 0
B35	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 1
B34	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 1
B33	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 3
B32	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 2
B31	BUFGMUX[1]: INIT_OUT bit 0
B30	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 2
B29	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 0
B28	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 1
B27	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 3
B26	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 4
B25	BUFGMUX[2]: INIT_OUT bit 0
B24	BUFGMUX[2]: !invert S
B23	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 2
B22	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 3
B21	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 0
B20	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 0
B19	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 1
B18	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 1
B17	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 3
B16	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 2
B15	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 4
B14	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 0
B13	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 1
B12	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 2
B11	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 3
B10	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 4
B9	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 0
B8	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 1
B7	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 2
B6	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 3
B5	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 2
B4	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 3
B3	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 0
B2	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 0
B1	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 1
B0	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 1

spartan3 CLK_S_S3E rect TERM
Bit	Frame
Bit	F0
B15	CLK_INT: mux CELL[3].OMUX_N11 bit 0
B14	CLK_INT: mux CELL[3].OMUX_N11 bit 1
B13	CLK_INT: mux CELL[3].OMUX_N10 bit 1
B12	CLK_INT: mux CELL[3].OMUX_N10 bit 2
B11	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 3
B10	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 2
B9	BUFGMUX[3]: !invert S
B8	CLK_INT: mux CELL[3].OMUX_N10 bit 0
B7	CLK_INT: mux CELL[3].OMUX_N11 bit 2
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

`CLK_S_S3A`

This tile is used on Spartan 3A and 3A DSP.

Tile CLK_S_S3A

Cells: 8

Switchbox CLK_INT

spartan3 CLK_S_S3A switchbox CLK_INT permanent buffers
Destination	Source
CELL[3].DCM_CLKPAD[0]	CELL[3].OUT_CLKPAD[1]
CELL[3].DCM_CLKPAD[1]	CELL[3].OUT_CLKPAD[0]
CELL[3].DCM_CLKPAD[2]	CELL[2].OUT_CLKPAD[1]
CELL[3].DCM_CLKPAD[3]	CELL[2].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[0]	CELL[4].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[1]	CELL[4].OUT_CLKPAD[1]
CELL[4].DCM_CLKPAD[2]	CELL[5].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[3]	CELL[5].OUT_CLKPAD[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes OMUX_N10
Bits			Destination
TERM[1][5]	TERM[1][2]	TERM[1][1]	CELL[3].OMUX_N10
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_S[2]
0	1	0	CELL[4].GCLK_S[3]
1	0	1	CELL[4].GCLK_S[0]
1	1	0	CELL[4].GCLK_S[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes OMUX_N11
Bits			Destination
TERM[1][0]	TERM[1][3]	TERM[1][4]	CELL[3].OMUX_N11
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_S[2]
0	1	0	CELL[4].GCLK_S[3]
1	0	1	CELL[4].GCLK_S[0]
1	1	0	CELL[4].GCLK_S[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes OMUX_N12
Bits			Destination
MAIN[0][43]	MAIN[0][44]	MAIN[0][41]	CELL[3].OMUX_N12
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_S[2]
0	1	0	CELL[4].GCLK_S[3]
1	0	1	CELL[4].GCLK_S[0]
1	1	0	CELL[4].GCLK_S[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes OMUX_N15
Bits			Destination
MAIN[0][46]	MAIN[0][45]	MAIN[0][42]	CELL[3].OMUX_N15
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_S[2]
0	1	0	CELL[4].GCLK_S[3]
1	0	1	CELL[4].GCLK_S[0]
1	1	0	CELL[4].GCLK_S[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits				Destination
MAIN[0][54]	MAIN[0][53]	MAIN[0][56]	MAIN[0][57]	CELL[4].IMUX_BUFG_CLK_INT[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[6]
0	0	1	0	CELL[5].DBL_W0[7]
0	1	0	1	CELL[2].DBL_E0[6]
0	1	1	0	CELL[2].DBL_E0[7]
1	0	0	1	CELL[4].DBL_W0[6]
1	0	1	0	CELL[4].DBL_W0[7]
1	1	0	1	CELL[3].DBL_E0[6]
1	1	1	0	CELL[3].DBL_E0[7]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits				Destination
MAIN[0][33]	MAIN[0][32]	MAIN[0][35]	MAIN[0][36]	CELL[4].IMUX_BUFG_CLK_INT[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[4]
0	0	1	0	CELL[5].DBL_W0[5]
0	1	0	1	CELL[2].DBL_E0[4]
0	1	1	0	CELL[2].DBL_E0[5]
1	0	0	1	CELL[4].DBL_W0[4]
1	0	1	0	CELL[4].DBL_W0[5]
1	1	0	1	CELL[3].DBL_E0[4]
1	1	1	0	CELL[3].DBL_E0[5]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits				Destination
MAIN[0][17]	MAIN[0][16]	MAIN[0][19]	MAIN[0][20]	CELL[4].IMUX_BUFG_CLK_INT[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[2]
0	0	1	0	CELL[5].DBL_W0[3]
0	1	0	1	CELL[2].DBL_E0[2]
0	1	1	0	CELL[2].DBL_E0[3]
1	0	0	1	CELL[4].DBL_W0[2]
1	0	1	0	CELL[4].DBL_W0[3]
1	1	0	1	CELL[3].DBL_E0[2]
1	1	1	0	CELL[3].DBL_E0[3]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits				Destination
MAIN[0][4]	MAIN[0][5]	MAIN[0][1]	MAIN[0][2]	CELL[4].IMUX_BUFG_CLK_INT[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[0]
0	0	1	0	CELL[5].DBL_W0[1]
0	1	0	1	CELL[2].DBL_E0[0]
0	1	1	0	CELL[2].DBL_E0[1]
1	0	0	1	CELL[4].DBL_W0[0]
1	0	1	0	CELL[4].DBL_W0[1]
1	1	0	1	CELL[3].DBL_E0[0]
1	1	1	0	CELL[3].DBL_E0[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits					Destination
MAIN[0][47]	MAIN[0][48]	MAIN[0][51]	MAIN[0][49]	MAIN[0][50]	CELL[4].IMUX_BUFG_CLK[0]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[2].OUT_CLKPAD[0]
0	0	0	1	0	CELL[3].DCM_BUS[0]
0	0	1	0	0	CELL[4].OUT_CLKPAD[0]
0	1	0	0	0	CELL[4].DCM_BUS[0]
1	0	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[0]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits					Destination
MAIN[0][26]	MAIN[0][27]	MAIN[0][30]	MAIN[0][28]	MAIN[0][29]	CELL[4].IMUX_BUFG_CLK[1]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[2].OUT_CLKPAD[1]
0	0	0	1	0	CELL[3].DCM_BUS[1]
0	0	1	0	0	CELL[4].OUT_CLKPAD[1]
0	1	0	0	0	CELL[4].DCM_BUS[1]
1	0	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits					Destination
MAIN[0][15]	MAIN[0][11]	MAIN[0][12]	MAIN[0][13]	MAIN[0][14]	CELL[4].IMUX_BUFG_CLK[2]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[3].OUT_CLKPAD[0]
0	0	0	1	0	CELL[3].DCM_BUS[2]
0	0	1	0	0	CELL[4].DCM_BUS[2]
0	1	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[2]
1	0	0	0	0	CELL[5].OUT_CLKPAD[0]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits					Destination
MAIN[0][10]	MAIN[0][6]	MAIN[0][7]	MAIN[0][8]	MAIN[0][9]	CELL[4].IMUX_BUFG_CLK[3]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[3].OUT_CLKPAD[1]
0	0	0	1	0	CELL[3].DCM_BUS[3]
0	0	1	0	0	CELL[4].DCM_BUS[3]
0	1	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[3]
1	0	0	0	0	CELL[5].OUT_CLKPAD[1]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits				Destination
MAIN[0][59]	MAIN[0][60]	MAIN[0][55]	MAIN[0][58]	CELL[4].IMUX_BUFG_SEL[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[6]
0	0	1	0	CELL[5].DBL_W0[7]
0	1	0	1	CELL[2].DBL_E0[6]
0	1	1	0	CELL[2].DBL_E0[7]
1	0	0	1	CELL[4].DBL_W0[6]
1	0	1	0	CELL[4].DBL_W0[7]
1	1	0	1	CELL[3].DBL_E0[6]
1	1	1	0	CELL[3].DBL_E0[7]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits				Destination
MAIN[0][38]	MAIN[0][39]	MAIN[0][34]	MAIN[0][37]	CELL[4].IMUX_BUFG_SEL[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[4]
0	0	1	0	CELL[5].DBL_W0[5]
0	1	0	1	CELL[2].DBL_E0[4]
0	1	1	0	CELL[2].DBL_E0[5]
1	0	0	1	CELL[4].DBL_W0[4]
1	0	1	0	CELL[4].DBL_W0[5]
1	1	0	1	CELL[3].DBL_E0[4]
1	1	1	0	CELL[3].DBL_E0[5]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits				Destination
MAIN[0][22]	MAIN[0][23]	MAIN[0][18]	MAIN[0][21]	CELL[4].IMUX_BUFG_SEL[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[2]
0	0	1	0	CELL[5].DBL_W0[3]
0	1	0	1	CELL[2].DBL_E0[2]
0	1	1	0	CELL[2].DBL_E0[3]
1	0	0	1	CELL[4].DBL_W0[2]
1	0	1	0	CELL[4].DBL_W0[3]
1	1	0	1	CELL[3].DBL_E0[2]
1	1	1	0	CELL[3].DBL_E0[3]

spartan3 CLK_S_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits				Destination
TERM[0][4]	TERM[0][3]	MAIN[0][0]	MAIN[0][3]	CELL[4].IMUX_BUFG_SEL[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[0]
0	0	1	0	CELL[5].DBL_W0[1]
0	1	0	1	CELL[2].DBL_E0[0]
0	1	1	0	CELL[2].DBL_E0[1]
1	0	0	1	CELL[4].DBL_W0[0]
1	0	1	0	CELL[4].DBL_W0[1]
1	1	0	1	CELL[3].DBL_E0[0]
1	1	1	0	CELL[3].DBL_E0[1]

Bels BUFGMUX

spartan3 CLK_S_S3A bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
I0	in	CELL[4].IMUX_BUFG_CLK[0]	CELL[4].IMUX_BUFG_CLK[1]	CELL[4].IMUX_BUFG_CLK[2]	CELL[4].IMUX_BUFG_CLK[3]
I1	in	CELL[4].IMUX_BUFG_CLK[1]	CELL[4].IMUX_BUFG_CLK[0]	CELL[4].IMUX_BUFG_CLK[3]	CELL[4].IMUX_BUFG_CLK[2]
S	in	CELL[4].IMUX_BUFG_SEL[0] invert by !MAIN[0][61]	CELL[4].IMUX_BUFG_SEL[1] invert by !MAIN[0][40]	CELL[4].IMUX_BUFG_SEL[2] invert by !MAIN[0][24]	CELL[4].IMUX_BUFG_SEL[3] invert by !TERM[0][2]
O	out	CELL[4].GCLK_S[0]	CELL[4].GCLK_S[1]	CELL[4].GCLK_S[2]	CELL[4].GCLK_S[3]

spartan3 CLK_S_S3A bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
INIT_OUT bit 0	MAIN[0][52]	MAIN[0][31]	MAIN[0][25]	MAIN[0][62]

Bels GLOBALSIG_BUFG

spartan3 CLK_S_S3A bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]

spartan3 CLK_S_S3A bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]
GWE_ENABLE	!MAIN[0][63]

Bel wires

spartan3 CLK_S_S3A bel wires
Wire	Pins
CELL[4].GCLK_S[0]	BUFGMUX[0].O
CELL[4].GCLK_S[1]	BUFGMUX[1].O
CELL[4].GCLK_S[2]	BUFGMUX[2].O
CELL[4].GCLK_S[3]	BUFGMUX[3].O
CELL[4].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0, BUFGMUX[1].I1
CELL[4].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0, BUFGMUX[0].I1
CELL[4].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0, BUFGMUX[3].I1
CELL[4].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0, BUFGMUX[2].I1
CELL[4].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[4].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[4].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[4].IMUX_BUFG_SEL[3]	BUFGMUX[3].S

Bitstream

spartan3 CLK_S_S3A rect MAIN
Bit	Frame
Bit	F0
B63	GLOBALSIG_BUFG[0]: ! GWE_ENABLE
B62	BUFGMUX[3]: INIT_OUT bit 0
B61	BUFGMUX[0]: !invert S
B60	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 2
B59	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 3
B58	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 0
B57	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 0
B56	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 1
B55	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 1
B54	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 3
B53	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 2
B52	BUFGMUX[0]: INIT_OUT bit 0
B51	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 2
B50	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 0
B49	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 1
B48	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 3
B47	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 4
B46	CLK_INT: mux CELL[3].OMUX_N15 bit 2
B45	CLK_INT: mux CELL[3].OMUX_N15 bit 1
B44	CLK_INT: mux CELL[3].OMUX_N12 bit 1
B43	CLK_INT: mux CELL[3].OMUX_N12 bit 2
B42	CLK_INT: mux CELL[3].OMUX_N15 bit 0
B41	CLK_INT: mux CELL[3].OMUX_N12 bit 0
B40	BUFGMUX[1]: !invert S
B39	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 2
B38	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 3
B37	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 0
B36	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 0
B35	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 1
B34	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 1
B33	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 3
B32	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 2
B31	BUFGMUX[1]: INIT_OUT bit 0
B30	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 2
B29	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 0
B28	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 1
B27	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 3
B26	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 4
B25	BUFGMUX[2]: INIT_OUT bit 0
B24	BUFGMUX[2]: !invert S
B23	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 2
B22	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 3
B21	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 0
B20	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 0
B19	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 1
B18	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 1
B17	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 3
B16	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 2
B15	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 4
B14	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 0
B13	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 1
B12	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 2
B11	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 3
B10	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 4
B9	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 0
B8	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 1
B7	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 2
B6	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 3
B5	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 2
B4	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 3
B3	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 0
B2	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 0
B1	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 1
B0	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 1

spartan3 CLK_S_S3A rect TERM
Bit	Frame
Bit	F1	F0
B15	-	-
B14	-	-
B13	-	-
B12	-	-
B11	-	-
B10	-	-
B9	-	-
B8	-	-
B7	-	-
B6	-	-
B5	CLK_INT: mux CELL[3].OMUX_N10 bit 2	-
B4	CLK_INT: mux CELL[3].OMUX_N11 bit 0	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 3
B3	CLK_INT: mux CELL[3].OMUX_N11 bit 1	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 2
B2	CLK_INT: mux CELL[3].OMUX_N10 bit 1	BUFGMUX[3]: !invert S
B1	CLK_INT: mux CELL[3].OMUX_N10 bit 0	-
B0	CLK_INT: mux CELL[3].OMUX_N11 bit 2	-

Bitstream — north tiles

The CLK_N_* tiles use two bitstream tiles:

tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the top interconnect row
tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the high special area (used for top IOB tiles and clock rows in normal columns)

On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH_N_S3A tile.

`CLK_N_S3`

This tile is used on Spartan 3.

Tile CLK_N_S3

Cells: 2

Switchbox CLK_INT

spartan3 CLK_N_S3 switchbox CLK_INT permanent buffers
Destination	Source
CELL[1].DCM_CLKPAD[0]	CELL[1].OUT_CLKPAD[0]
CELL[1].DCM_CLKPAD[1]	CELL[1].OUT_CLKPAD[1]
CELL[1].DCM_CLKPAD[2]	CELL[0].OUT_CLKPAD[0]
CELL[1].DCM_CLKPAD[3]	CELL[0].OUT_CLKPAD[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes OMUX_S0
Bits			Destination
TERM[0][3]	TERM[0][2]	MAIN[0][63]	CELL[0].OMUX_S0
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_N[2]
0	1	0	CELL[1].GCLK_N[3]
1	0	1	CELL[1].GCLK_N[0]
1	1	0	CELL[1].GCLK_N[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes OMUX_S3
Bits			Destination
TERM[0][0]	TERM[0][4]	TERM[0][1]	CELL[0].OMUX_S3
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_N[2]
0	1	0	CELL[1].GCLK_N[3]
1	0	1	CELL[1].GCLK_N[0]
1	1	0	CELL[1].GCLK_N[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes OMUX_S4
Bits			Destination
MAIN[0][19]	MAIN[0][18]	MAIN[0][21]	CELL[0].OMUX_S4
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_N[2]
0	1	0	CELL[1].GCLK_N[3]
1	0	1	CELL[1].GCLK_N[0]
1	1	0	CELL[1].GCLK_N[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes OMUX_S5
Bits			Destination
MAIN[0][16]	MAIN[0][17]	MAIN[0][20]	CELL[0].OMUX_S5
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_N[2]
0	1	0	CELL[1].GCLK_N[3]
1	0	1	CELL[1].GCLK_N[0]
1	1	0	CELL[1].GCLK_N[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits				Destination
MAIN[0][9]	MAIN[0][10]	MAIN[0][7]	MAIN[0][6]	CELL[1].IMUX_BUFG_CLK_INT[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[0]
0	0	1	0	CELL[0].DBL_W2[1]
0	1	0	1	CELL[0].DBL_W1[0]
0	1	1	0	CELL[0].DBL_W1[1]
1	0	0	1	CELL[0].DBL_E1[0]
1	0	1	0	CELL[0].DBL_E1[1]
1	1	0	1	CELL[0].DBL_E0[0]
1	1	1	0	CELL[0].DBL_E0[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits				Destination
MAIN[0][29]	MAIN[0][30]	MAIN[0][27]	MAIN[0][26]	CELL[1].IMUX_BUFG_CLK_INT[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[2]
0	0	1	0	CELL[0].DBL_W2[3]
0	1	0	1	CELL[0].DBL_W1[2]
0	1	1	0	CELL[0].DBL_W1[3]
1	0	0	1	CELL[0].DBL_E1[2]
1	0	1	0	CELL[0].DBL_E1[3]
1	1	0	1	CELL[0].DBL_E0[2]
1	1	1	0	CELL[0].DBL_E0[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits				Destination
MAIN[0][43]	MAIN[0][44]	MAIN[0][41]	MAIN[0][40]	CELL[1].IMUX_BUFG_CLK_INT[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[4]
0	0	1	0	CELL[0].DBL_W2[5]
0	1	0	1	CELL[0].DBL_W1[4]
0	1	1	0	CELL[0].DBL_W1[5]
1	0	0	1	CELL[0].DBL_E1[4]
1	0	1	0	CELL[0].DBL_E1[5]
1	1	0	1	CELL[0].DBL_E0[4]
1	1	1	0	CELL[0].DBL_E0[5]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits				Destination
MAIN[0][54]	MAIN[0][55]	MAIN[0][58]	MAIN[0][57]	CELL[1].IMUX_BUFG_CLK_INT[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[6]
0	0	1	0	CELL[0].DBL_W2[7]
0	1	0	1	CELL[0].DBL_W1[6]
0	1	1	0	CELL[0].DBL_W1[7]
1	0	0	1	CELL[0].DBL_E1[6]
1	0	1	0	CELL[0].DBL_E1[7]
1	1	0	1	CELL[0].DBL_E0[6]
1	1	1	0	CELL[0].DBL_E0[7]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits				Destination
MAIN[0][15]	MAIN[0][14]	MAIN[0][12]	MAIN[0][13]	CELL[1].IMUX_BUFG_CLK[0]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[0]
0	0	1	0	CELL[1].OUT_CLKPAD[0]
0	1	0	0	CELL[1].DCM_BUS[0]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[0]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits				Destination
MAIN[0][35]	MAIN[0][34]	MAIN[0][32]	MAIN[0][33]	CELL[1].IMUX_BUFG_CLK[1]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[1]
0	0	1	0	CELL[1].OUT_CLKPAD[1]
0	1	0	0	CELL[1].DCM_BUS[1]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits				Destination
MAIN[0][49]	MAIN[0][48]	MAIN[0][47]	MAIN[0][46]	CELL[1].IMUX_BUFG_CLK[2]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[0]
0	0	1	0	CELL[0].DCM_BUS[2]
0	1	0	0	CELL[1].DCM_BUS[2]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[2]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits				Destination
MAIN[0][53]	MAIN[0][52]	MAIN[0][51]	MAIN[0][50]	CELL[1].IMUX_BUFG_CLK[3]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[1]
0	0	1	0	CELL[0].DCM_BUS[3]
0	1	0	0	CELL[1].DCM_BUS[3]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits				Destination
MAIN[0][4]	MAIN[0][3]	MAIN[0][8]	MAIN[0][5]	CELL[1].IMUX_BUFG_SEL[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[0]
0	0	1	0	CELL[0].DBL_W2[1]
0	1	0	1	CELL[0].DBL_W1[0]
0	1	1	0	CELL[0].DBL_W1[1]
1	0	0	1	CELL[0].DBL_E1[0]
1	0	1	0	CELL[0].DBL_E1[1]
1	1	0	1	CELL[0].DBL_E0[0]
1	1	1	0	CELL[0].DBL_E0[1]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits				Destination
MAIN[0][24]	MAIN[0][23]	MAIN[0][28]	MAIN[0][25]	CELL[1].IMUX_BUFG_SEL[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[2]
0	0	1	0	CELL[0].DBL_W2[3]
0	1	0	1	CELL[0].DBL_W1[2]
0	1	1	0	CELL[0].DBL_W1[3]
1	0	0	1	CELL[0].DBL_E1[2]
1	0	1	0	CELL[0].DBL_E1[3]
1	1	0	1	CELL[0].DBL_E0[2]
1	1	1	0	CELL[0].DBL_E0[3]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits				Destination
MAIN[0][38]	MAIN[0][37]	MAIN[0][42]	MAIN[0][39]	CELL[1].IMUX_BUFG_SEL[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[4]
0	0	1	0	CELL[0].DBL_W2[5]
0	1	0	1	CELL[0].DBL_W1[4]
0	1	1	0	CELL[0].DBL_W1[5]
1	0	0	1	CELL[0].DBL_E1[4]
1	0	1	0	CELL[0].DBL_E1[5]
1	1	0	1	CELL[0].DBL_E0[4]
1	1	1	0	CELL[0].DBL_E0[5]

spartan3 CLK_N_S3 switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits				Destination
MAIN[0][61]	MAIN[0][60]	MAIN[0][59]	MAIN[0][56]	CELL[1].IMUX_BUFG_SEL[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[6]
0	0	1	0	CELL[0].DBL_W2[7]
0	1	0	1	CELL[0].DBL_W1[6]
0	1	1	0	CELL[0].DBL_W1[7]
1	0	0	1	CELL[0].DBL_E1[6]
1	0	1	0	CELL[0].DBL_E1[7]
1	1	0	1	CELL[0].DBL_E0[6]
1	1	1	0	CELL[0].DBL_E0[7]

Bels BUFGMUX

spartan3 CLK_N_S3 bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
I0	in	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[2]	CELL[1].IMUX_BUFG_CLK[3]
I1	in	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[3]	CELL[1].IMUX_BUFG_CLK[2]
S	in	CELL[1].IMUX_BUFG_SEL[0] invert by !MAIN[0][2]	CELL[1].IMUX_BUFG_SEL[1] invert by !MAIN[0][22]	CELL[1].IMUX_BUFG_SEL[2] invert by !MAIN[0][36]	CELL[1].IMUX_BUFG_SEL[3] invert by !MAIN[0][62]
O	out	CELL[1].GCLK_N[0]	CELL[1].GCLK_N[1]	CELL[1].GCLK_N[2]	CELL[1].GCLK_N[3]

spartan3 CLK_N_S3 bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
INIT_OUT bit 0	MAIN[0][11]	MAIN[0][31]	MAIN[0][45]	MAIN[0][1]

Bels GLOBALSIG_BUFG

spartan3 CLK_N_S3 bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]

spartan3 CLK_N_S3 bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]
GWE_ENABLE	!MAIN[0][0]

Bel wires

spartan3 CLK_N_S3 bel wires
Wire	Pins
CELL[1].GCLK_N[0]	BUFGMUX[0].O
CELL[1].GCLK_N[1]	BUFGMUX[1].O
CELL[1].GCLK_N[2]	BUFGMUX[2].O
CELL[1].GCLK_N[3]	BUFGMUX[3].O
CELL[1].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0, BUFGMUX[1].I1
CELL[1].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0, BUFGMUX[0].I1
CELL[1].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0, BUFGMUX[3].I1
CELL[1].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0, BUFGMUX[2].I1
CELL[1].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[1].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[1].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[1].IMUX_BUFG_SEL[3]	BUFGMUX[3].S

Bitstream

spartan3 CLK_N_S3 rect MAIN
Bit	Frame
Bit	F0
B63	CLK_INT: mux CELL[0].OMUX_S0 bit 0
B62	BUFGMUX[3]: !invert S
B61	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 3
B60	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 2
B59	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 1
B58	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 1
B57	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 0
B56	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 0
B55	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 2
B54	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 3
B53	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 3
B52	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 2
B51	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 1
B50	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 0
B49	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 3
B48	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 2
B47	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 1
B46	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 0
B45	BUFGMUX[2]: INIT_OUT bit 0
B44	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 2
B43	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 3
B42	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 1
B41	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 1
B40	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 0
B39	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 0
B38	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 3
B37	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 2
B36	BUFGMUX[2]: !invert S
B35	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 3
B34	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 2
B33	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 0
B32	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 1
B31	BUFGMUX[1]: INIT_OUT bit 0
B30	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 2
B29	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 3
B28	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 1
B27	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 1
B26	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 0
B25	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 0
B24	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 3
B23	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 2
B22	BUFGMUX[1]: !invert S
B21	CLK_INT: mux CELL[0].OMUX_S4 bit 0
B20	CLK_INT: mux CELL[0].OMUX_S5 bit 0
B19	CLK_INT: mux CELL[0].OMUX_S4 bit 2
B18	CLK_INT: mux CELL[0].OMUX_S4 bit 1
B17	CLK_INT: mux CELL[0].OMUX_S5 bit 1
B16	CLK_INT: mux CELL[0].OMUX_S5 bit 2
B15	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 3
B14	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 2
B13	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 0
B12	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 1
B11	BUFGMUX[0]: INIT_OUT bit 0
B10	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 2
B9	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 3
B8	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 1
B7	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 1
B6	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 0
B5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 0
B4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 3
B3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 2
B2	BUFGMUX[0]: !invert S
B1	BUFGMUX[3]: INIT_OUT bit 0
B0	GLOBALSIG_BUFG[0]: ! GWE_ENABLE

spartan3 CLK_N_S3 rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	CLK_INT: mux CELL[0].OMUX_S3 bit 1
B3	CLK_INT: mux CELL[0].OMUX_S0 bit 2
B2	CLK_INT: mux CELL[0].OMUX_S0 bit 1
B1	CLK_INT: mux CELL[0].OMUX_S3 bit 0
B0	CLK_INT: mux CELL[0].OMUX_S3 bit 2

`CLK_N_FC`

This tile is used on FPGAcore.

Tile CLK_N_FC

Cells: 2

Switchbox CLK_INT

spartan3 CLK_N_FC switchbox CLK_INT muxes OMUX_S0
Bits			Destination
TERM[0][3]	TERM[0][2]	MAIN[0][63]	CELL[0].OMUX_S0
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_N[2]
0	1	0	CELL[1].GCLK_N[3]
1	0	1	CELL[1].GCLK_N[0]
1	1	0	CELL[1].GCLK_N[1]

spartan3 CLK_N_FC switchbox CLK_INT muxes OMUX_S3
Bits			Destination
TERM[0][0]	TERM[0][4]	TERM[0][1]	CELL[0].OMUX_S3
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_N[2]
0	1	0	CELL[1].GCLK_N[3]
1	0	1	CELL[1].GCLK_N[0]
1	1	0	CELL[1].GCLK_N[1]

spartan3 CLK_N_FC switchbox CLK_INT muxes OMUX_S4
Bits			Destination
MAIN[0][19]	MAIN[0][18]	MAIN[0][21]	CELL[0].OMUX_S4
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_N[2]
0	1	0	CELL[1].GCLK_N[3]
1	0	1	CELL[1].GCLK_N[0]
1	1	0	CELL[1].GCLK_N[1]

spartan3 CLK_N_FC switchbox CLK_INT muxes OMUX_S5
Bits			Destination
MAIN[0][16]	MAIN[0][17]	MAIN[0][20]	CELL[0].OMUX_S5
			Source
0	0	0	off
0	0	1	CELL[1].GCLK_N[2]
0	1	0	CELL[1].GCLK_N[3]
1	0	1	CELL[1].GCLK_N[0]
1	1	0	CELL[1].GCLK_N[1]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits				Destination
MAIN[0][9]	MAIN[0][10]	MAIN[0][7]	MAIN[0][6]	CELL[1].IMUX_BUFG_CLK_INT[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[0]
0	0	1	0	CELL[0].DBL_W2[1]
0	1	0	1	CELL[0].DBL_W1[0]
0	1	1	0	CELL[0].DBL_W1[1]
1	0	0	1	CELL[0].DBL_E1[0]
1	0	1	0	CELL[0].DBL_E1[1]
1	1	0	1	CELL[0].DBL_E0[0]
1	1	1	0	CELL[0].DBL_E0[1]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits				Destination
MAIN[0][29]	MAIN[0][30]	MAIN[0][27]	MAIN[0][26]	CELL[1].IMUX_BUFG_CLK_INT[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[2]
0	0	1	0	CELL[0].DBL_W2[3]
0	1	0	1	CELL[0].DBL_W1[2]
0	1	1	0	CELL[0].DBL_W1[3]
1	0	0	1	CELL[0].DBL_E1[2]
1	0	1	0	CELL[0].DBL_E1[3]
1	1	0	1	CELL[0].DBL_E0[2]
1	1	1	0	CELL[0].DBL_E0[3]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits				Destination
MAIN[0][43]	MAIN[0][44]	MAIN[0][41]	MAIN[0][40]	CELL[1].IMUX_BUFG_CLK_INT[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[4]
0	0	1	0	CELL[0].DBL_W2[5]
0	1	0	1	CELL[0].DBL_W1[4]
0	1	1	0	CELL[0].DBL_W1[5]
1	0	0	1	CELL[0].DBL_E1[4]
1	0	1	0	CELL[0].DBL_E1[5]
1	1	0	1	CELL[0].DBL_E0[4]
1	1	1	0	CELL[0].DBL_E0[5]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits				Destination
MAIN[0][54]	MAIN[0][55]	MAIN[0][58]	MAIN[0][57]	CELL[1].IMUX_BUFG_CLK_INT[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[0].DBL_W2[6]
0	0	1	0	CELL[0].DBL_W2[7]
0	1	0	1	CELL[0].DBL_W1[6]
0	1	1	0	CELL[0].DBL_W1[7]
1	0	0	1	CELL[0].DBL_E1[6]
1	0	1	0	CELL[0].DBL_E1[7]
1	1	0	1	CELL[0].DBL_E0[6]
1	1	1	0	CELL[0].DBL_E0[7]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits		Destination
MAIN[0][15]	MAIN[0][12]	CELL[1].IMUX_BUFG_CLK[0]
		Source
0	0	off
0	1	CELL[1].OUT_CLKPAD[0]
1	0	CELL[1].IMUX_BUFG_CLK_INT[0]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits		Destination
MAIN[0][35]	MAIN[0][32]	CELL[1].IMUX_BUFG_CLK[1]
		Source
0	0	off
0	1	CELL[1].OUT_CLKPAD[1]
1	0	CELL[1].IMUX_BUFG_CLK_INT[1]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits		Destination
MAIN[0][49]	MAIN[0][46]	CELL[1].IMUX_BUFG_CLK[2]
		Source
0	0	off
0	1	CELL[0].OUT_CLKPAD[0]
1	0	CELL[1].IMUX_BUFG_CLK_INT[2]

spartan3 CLK_N_FC switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits		Destination
MAIN[0][53]	MAIN[0][50]	CELL[1].IMUX_BUFG_CLK[3]
		Source
0	0	off
0	1	CELL[0].OUT_CLKPAD[1]
1	0	CELL[1].IMUX_BUFG_CLK_INT[3]

Bels BUFGMUX

spartan3 CLK_N_FC bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
I0	in	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[2]	CELL[1].IMUX_BUFG_CLK[3]
O	out	CELL[1].GCLK_N[0]	CELL[1].GCLK_N[1]	CELL[1].GCLK_N[2]	CELL[1].GCLK_N[3]

spartan3 CLK_N_FC bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]

Bels GLOBALSIG_BUFG

spartan3 CLK_N_FC bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]

spartan3 CLK_N_FC bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]
GWE_ENABLE	!MAIN[0][0]

Bel wires

spartan3 CLK_N_FC bel wires
Wire	Pins
CELL[1].GCLK_N[0]	BUFGMUX[0].O
CELL[1].GCLK_N[1]	BUFGMUX[1].O
CELL[1].GCLK_N[2]	BUFGMUX[2].O
CELL[1].GCLK_N[3]	BUFGMUX[3].O
CELL[1].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0
CELL[1].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0
CELL[1].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0
CELL[1].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0

Bitstream

spartan3 CLK_N_FC rect MAIN
Bit	Frame
Bit	F0
B63	CLK_INT: mux CELL[0].OMUX_S0 bit 0
B62	-
B61	-
B60	-
B59	-
B58	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 1
B57	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 0
B56	-
B55	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 2
B54	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 3
B53	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 1
B52	-
B51	-
B50	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 0
B49	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 1
B48	-
B47	-
B46	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 0
B45	-
B44	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 2
B43	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 3
B42	-
B41	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 1
B40	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 0
B39	-
B38	-
B37	-
B36	-
B35	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 1
B34	-
B33	-
B32	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 0
B31	-
B30	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 2
B29	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 3
B28	-
B27	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 1
B26	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 0
B25	-
B24	-
B23	-
B22	-
B21	CLK_INT: mux CELL[0].OMUX_S4 bit 0
B20	CLK_INT: mux CELL[0].OMUX_S5 bit 0
B19	CLK_INT: mux CELL[0].OMUX_S4 bit 2
B18	CLK_INT: mux CELL[0].OMUX_S4 bit 1
B17	CLK_INT: mux CELL[0].OMUX_S5 bit 1
B16	CLK_INT: mux CELL[0].OMUX_S5 bit 2
B15	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 1
B14	-
B13	-
B12	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 0
B11	-
B10	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 2
B9	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 3
B8	-
B7	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 1
B6	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 0
B5	-
B4	-
B3	-
B2	-
B1	-
B0	GLOBALSIG_BUFG[0]: ! GWE_ENABLE

spartan3 CLK_N_FC rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	CLK_INT: mux CELL[0].OMUX_S3 bit 1
B3	CLK_INT: mux CELL[0].OMUX_S0 bit 2
B2	CLK_INT: mux CELL[0].OMUX_S0 bit 1
B1	CLK_INT: mux CELL[0].OMUX_S3 bit 0
B0	CLK_INT: mux CELL[0].OMUX_S3 bit 2

`CLK_N_S3E`

This tile is used on Spartan 3E.

Tile CLK_N_S3E

Cells: 8

Switchbox CLK_INT

spartan3 CLK_N_S3E switchbox CLK_INT permanent buffers
Destination	Source
CELL[3].DCM_CLKPAD[0]	CELL[3].OUT_CLKPAD[0]
CELL[3].DCM_CLKPAD[1]	CELL[3].OUT_CLKPAD[1]
CELL[3].DCM_CLKPAD[2]	CELL[2].OUT_CLKPAD[0]
CELL[3].DCM_CLKPAD[3]	CELL[2].OUT_CLKPAD[1]
CELL[4].DCM_CLKPAD[0]	CELL[4].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[1]	CELL[4].OUT_CLKPAD[1]
CELL[4].DCM_CLKPAD[2]	CELL[6].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[3]	CELL[6].OUT_CLKPAD[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes OMUX_S0
Bits			Destination
TERM[0][6]	TERM[0][7]	TERM[0][3]	CELL[3].OMUX_S0
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_N[2]
0	1	0	CELL[4].GCLK_N[3]
1	0	1	CELL[4].GCLK_N[0]
1	1	0	CELL[4].GCLK_N[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes OMUX_S3
Bits			Destination
TERM[0][4]	TERM[0][5]	TERM[0][8]	CELL[3].OMUX_S3
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_N[2]
0	1	0	CELL[4].GCLK_N[3]
1	0	1	CELL[4].GCLK_N[0]
1	1	0	CELL[4].GCLK_N[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes OMUX_S4
Bits			Destination
MAIN[0][20]	MAIN[0][19]	MAIN[0][22]	CELL[3].OMUX_S4
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_N[2]
0	1	0	CELL[4].GCLK_N[3]
1	0	1	CELL[4].GCLK_N[0]
1	1	0	CELL[4].GCLK_N[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes OMUX_S5
Bits			Destination
MAIN[0][17]	MAIN[0][18]	MAIN[0][21]	CELL[3].OMUX_S5
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_N[2]
0	1	0	CELL[4].GCLK_N[3]
1	0	1	CELL[4].GCLK_N[0]
1	1	0	CELL[4].GCLK_N[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits				Destination
MAIN[0][9]	MAIN[0][10]	MAIN[0][7]	MAIN[0][6]	CELL[4].IMUX_BUFG_CLK_INT[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[0]
0	0	1	0	CELL[5].DBL_W0[1]
0	1	0	1	CELL[2].DBL_E0[0]
0	1	1	0	CELL[2].DBL_E0[1]
1	0	0	1	CELL[4].DBL_W0[0]
1	0	1	0	CELL[4].DBL_W0[1]
1	1	0	1	CELL[3].DBL_E0[0]
1	1	1	0	CELL[3].DBL_E0[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits				Destination
MAIN[0][30]	MAIN[0][31]	MAIN[0][28]	MAIN[0][27]	CELL[4].IMUX_BUFG_CLK_INT[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[2]
0	0	1	0	CELL[5].DBL_W0[3]
0	1	0	1	CELL[2].DBL_E0[2]
0	1	1	0	CELL[2].DBL_E0[3]
1	0	0	1	CELL[4].DBL_W0[2]
1	0	1	0	CELL[4].DBL_W0[3]
1	1	0	1	CELL[3].DBL_E0[2]
1	1	1	0	CELL[3].DBL_E0[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits				Destination
MAIN[0][46]	MAIN[0][47]	MAIN[0][44]	MAIN[0][43]	CELL[4].IMUX_BUFG_CLK_INT[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[4]
0	0	1	0	CELL[5].DBL_W0[5]
0	1	0	1	CELL[2].DBL_E0[4]
0	1	1	0	CELL[2].DBL_E0[5]
1	0	0	1	CELL[4].DBL_W0[4]
1	0	1	0	CELL[4].DBL_W0[5]
1	1	0	1	CELL[3].DBL_E0[4]
1	1	1	0	CELL[3].DBL_E0[5]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits				Destination
MAIN[0][59]	MAIN[0][58]	MAIN[0][62]	MAIN[0][61]	CELL[4].IMUX_BUFG_CLK_INT[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[6]
0	0	1	0	CELL[5].DBL_W0[7]
0	1	0	1	CELL[2].DBL_E0[6]
0	1	1	0	CELL[2].DBL_E0[7]
1	0	0	1	CELL[4].DBL_W0[6]
1	0	1	0	CELL[4].DBL_W0[7]
1	1	0	1	CELL[3].DBL_E0[6]
1	1	1	0	CELL[3].DBL_E0[7]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits					Destination
MAIN[0][12]	MAIN[0][16]	MAIN[0][15]	MAIN[0][14]	MAIN[0][13]	CELL[4].IMUX_BUFG_CLK[0]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[3].OUT_CLKPAD[0]
0	0	0	1	0	CELL[3].DCM_BUS[0]
0	0	1	0	0	CELL[4].DCM_BUS[0]
0	1	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[0]
1	0	0	0	0	CELL[6].OUT_CLKPAD[0]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits					Destination
MAIN[0][33]	MAIN[0][37]	MAIN[0][36]	MAIN[0][35]	MAIN[0][34]	CELL[4].IMUX_BUFG_CLK[1]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[3].OUT_CLKPAD[1]
0	0	0	1	0	CELL[3].DCM_BUS[1]
0	0	1	0	0	CELL[4].DCM_BUS[1]
0	1	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[1]
1	0	0	0	0	CELL[6].OUT_CLKPAD[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits					Destination
MAIN[0][52]	MAIN[0][51]	MAIN[0][48]	MAIN[0][50]	MAIN[0][49]	CELL[4].IMUX_BUFG_CLK[2]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[2].OUT_CLKPAD[0]
0	0	0	1	0	CELL[3].DCM_BUS[2]
0	0	1	0	0	CELL[4].OUT_CLKPAD[0]
0	1	0	0	0	CELL[4].DCM_BUS[2]
1	0	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[2]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits					Destination
MAIN[0][57]	MAIN[0][56]	MAIN[0][53]	MAIN[0][55]	MAIN[0][54]	CELL[4].IMUX_BUFG_CLK[3]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[2].OUT_CLKPAD[1]
0	0	0	1	0	CELL[3].DCM_BUS[3]
0	0	1	0	0	CELL[4].OUT_CLKPAD[1]
0	1	0	0	0	CELL[4].DCM_BUS[3]
1	0	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits				Destination
MAIN[0][4]	MAIN[0][3]	MAIN[0][8]	MAIN[0][5]	CELL[4].IMUX_BUFG_SEL[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[0]
0	0	1	0	CELL[5].DBL_W0[1]
0	1	0	1	CELL[2].DBL_E0[0]
0	1	1	0	CELL[2].DBL_E0[1]
1	0	0	1	CELL[4].DBL_W0[0]
1	0	1	0	CELL[4].DBL_W0[1]
1	1	0	1	CELL[3].DBL_E0[0]
1	1	1	0	CELL[3].DBL_E0[1]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits				Destination
MAIN[0][25]	MAIN[0][24]	MAIN[0][29]	MAIN[0][26]	CELL[4].IMUX_BUFG_SEL[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[2]
0	0	1	0	CELL[5].DBL_W0[3]
0	1	0	1	CELL[2].DBL_E0[2]
0	1	1	0	CELL[2].DBL_E0[3]
1	0	0	1	CELL[4].DBL_W0[2]
1	0	1	0	CELL[4].DBL_W0[3]
1	1	0	1	CELL[3].DBL_E0[2]
1	1	1	0	CELL[3].DBL_E0[3]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits				Destination
MAIN[0][41]	MAIN[0][40]	MAIN[0][45]	MAIN[0][42]	CELL[4].IMUX_BUFG_SEL[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[4]
0	0	1	0	CELL[5].DBL_W0[5]
0	1	0	1	CELL[2].DBL_E0[4]
0	1	1	0	CELL[2].DBL_E0[5]
1	0	0	1	CELL[4].DBL_W0[4]
1	0	1	0	CELL[4].DBL_W0[5]
1	1	0	1	CELL[3].DBL_E0[4]
1	1	1	0	CELL[3].DBL_E0[5]

spartan3 CLK_N_S3E switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits				Destination
TERM[0][0]	TERM[0][1]	MAIN[0][63]	MAIN[0][60]	CELL[4].IMUX_BUFG_SEL[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[6]
0	0	1	0	CELL[5].DBL_W0[7]
0	1	0	1	CELL[2].DBL_E0[6]
0	1	1	0	CELL[2].DBL_E0[7]
1	0	0	1	CELL[4].DBL_W0[6]
1	0	1	0	CELL[4].DBL_W0[7]
1	1	0	1	CELL[3].DBL_E0[6]
1	1	1	0	CELL[3].DBL_E0[7]

Bels BUFGMUX

spartan3 CLK_N_S3E bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
I0	in	CELL[4].IMUX_BUFG_CLK[0]	CELL[4].IMUX_BUFG_CLK[1]	CELL[4].IMUX_BUFG_CLK[2]	CELL[4].IMUX_BUFG_CLK[3]
I1	in	CELL[4].IMUX_BUFG_CLK[1]	CELL[4].IMUX_BUFG_CLK[0]	CELL[4].IMUX_BUFG_CLK[3]	CELL[4].IMUX_BUFG_CLK[2]
S	in	CELL[4].IMUX_BUFG_SEL[0] invert by !MAIN[0][2]	CELL[4].IMUX_BUFG_SEL[1] invert by !MAIN[0][23]	CELL[4].IMUX_BUFG_SEL[2] invert by !MAIN[0][39]	CELL[4].IMUX_BUFG_SEL[3] invert by !TERM[0][2]
O	out	CELL[4].GCLK_N[0]	CELL[4].GCLK_N[1]	CELL[4].GCLK_N[2]	CELL[4].GCLK_N[3]

spartan3 CLK_N_S3E bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
INIT_OUT bit 0	MAIN[0][11]	MAIN[0][32]	MAIN[0][38]	MAIN[0][1]

Bels GLOBALSIG_BUFG

spartan3 CLK_N_S3E bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]

spartan3 CLK_N_S3E bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]
GWE_ENABLE	!MAIN[0][0]

Bel wires

spartan3 CLK_N_S3E bel wires
Wire	Pins
CELL[4].GCLK_N[0]	BUFGMUX[0].O
CELL[4].GCLK_N[1]	BUFGMUX[1].O
CELL[4].GCLK_N[2]	BUFGMUX[2].O
CELL[4].GCLK_N[3]	BUFGMUX[3].O
CELL[4].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0, BUFGMUX[1].I1
CELL[4].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0, BUFGMUX[0].I1
CELL[4].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0, BUFGMUX[3].I1
CELL[4].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0, BUFGMUX[2].I1
CELL[4].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[4].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[4].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[4].IMUX_BUFG_SEL[3]	BUFGMUX[3].S

Bitstream

spartan3 CLK_N_S3E rect MAIN
Bit	Frame
Bit	F0
B63	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 1
B62	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 1
B61	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 0
B60	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 0
B59	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 3
B58	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 2
B57	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 4
B56	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 3
B55	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 1
B54	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 0
B53	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 2
B52	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 4
B51	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 3
B50	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 1
B49	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 0
B48	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 2
B47	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 2
B46	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 3
B45	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 1
B44	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 1
B43	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 0
B42	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 0
B41	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 3
B40	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 2
B39	BUFGMUX[2]: !invert S
B38	BUFGMUX[2]: INIT_OUT bit 0
B37	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 3
B36	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 2
B35	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 1
B34	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 0
B33	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 4
B32	BUFGMUX[1]: INIT_OUT bit 0
B31	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 2
B30	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 3
B29	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 1
B28	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 1
B27	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 0
B26	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 0
B25	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 3
B24	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 2
B23	BUFGMUX[1]: !invert S
B22	CLK_INT: mux CELL[3].OMUX_S4 bit 0
B21	CLK_INT: mux CELL[3].OMUX_S5 bit 0
B20	CLK_INT: mux CELL[3].OMUX_S4 bit 2
B19	CLK_INT: mux CELL[3].OMUX_S4 bit 1
B18	CLK_INT: mux CELL[3].OMUX_S5 bit 1
B17	CLK_INT: mux CELL[3].OMUX_S5 bit 2
B16	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 3
B15	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 2
B14	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 1
B13	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 0
B12	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 4
B11	BUFGMUX[0]: INIT_OUT bit 0
B10	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 2
B9	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 3
B8	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 1
B7	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 1
B6	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 0
B5	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 0
B4	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 3
B3	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 2
B2	BUFGMUX[0]: !invert S
B1	BUFGMUX[3]: INIT_OUT bit 0
B0	GLOBALSIG_BUFG[0]: ! GWE_ENABLE

spartan3 CLK_N_S3E rect TERM
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	CLK_INT: mux CELL[3].OMUX_S3 bit 0
B7	CLK_INT: mux CELL[3].OMUX_S0 bit 1
B6	CLK_INT: mux CELL[3].OMUX_S0 bit 2
B5	CLK_INT: mux CELL[3].OMUX_S3 bit 1
B4	CLK_INT: mux CELL[3].OMUX_S3 bit 2
B3	CLK_INT: mux CELL[3].OMUX_S0 bit 0
B2	BUFGMUX[3]: !invert S
B1	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 2
B0	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 3

`CLK_N_S3A`

This tile is used on Spartan 3A and 3A DSP.

Tile CLK_N_S3A

Cells: 8

Switchbox CLK_INT

spartan3 CLK_N_S3A switchbox CLK_INT permanent buffers
Destination	Source
CELL[3].DCM_CLKPAD[0]	CELL[3].OUT_CLKPAD[0]
CELL[3].DCM_CLKPAD[1]	CELL[3].OUT_CLKPAD[1]
CELL[3].DCM_CLKPAD[2]	CELL[2].OUT_CLKPAD[0]
CELL[3].DCM_CLKPAD[3]	CELL[2].OUT_CLKPAD[1]
CELL[4].DCM_CLKPAD[0]	CELL[4].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[1]	CELL[4].OUT_CLKPAD[1]
CELL[4].DCM_CLKPAD[2]	CELL[5].OUT_CLKPAD[0]
CELL[4].DCM_CLKPAD[3]	CELL[5].OUT_CLKPAD[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes OMUX_S0
Bits			Destination
TERM[1][2]	TERM[1][0]	TERM[1][3]	CELL[3].OMUX_S0
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_N[2]
0	1	0	CELL[4].GCLK_N[3]
1	0	1	CELL[4].GCLK_N[0]
1	1	0	CELL[4].GCLK_N[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes OMUX_S3
Bits			Destination
TERM[1][4]	TERM[1][5]	TERM[1][1]	CELL[3].OMUX_S3
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_N[2]
0	1	0	CELL[4].GCLK_N[3]
1	0	1	CELL[4].GCLK_N[0]
1	1	0	CELL[4].GCLK_N[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes OMUX_S4
Bits			Destination
MAIN[0][20]	MAIN[0][19]	MAIN[0][22]	CELL[3].OMUX_S4
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_N[2]
0	1	0	CELL[4].GCLK_N[3]
1	0	1	CELL[4].GCLK_N[0]
1	1	0	CELL[4].GCLK_N[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes OMUX_S5
Bits			Destination
MAIN[0][17]	MAIN[0][18]	MAIN[0][21]	CELL[3].OMUX_S5
			Source
0	0	0	off
0	0	1	CELL[4].GCLK_N[2]
0	1	0	CELL[4].GCLK_N[3]
1	0	1	CELL[4].GCLK_N[0]
1	1	0	CELL[4].GCLK_N[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits				Destination
MAIN[0][9]	MAIN[0][10]	MAIN[0][7]	MAIN[0][6]	CELL[4].IMUX_BUFG_CLK_INT[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[0]
0	0	1	0	CELL[5].DBL_W0[1]
0	1	0	1	CELL[2].DBL_E0[0]
0	1	1	0	CELL[2].DBL_E0[1]
1	0	0	1	CELL[4].DBL_W0[0]
1	0	1	0	CELL[4].DBL_W0[1]
1	1	0	1	CELL[3].DBL_E0[0]
1	1	1	0	CELL[3].DBL_E0[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits				Destination
MAIN[0][30]	MAIN[0][31]	MAIN[0][27]	MAIN[0][28]	CELL[4].IMUX_BUFG_CLK_INT[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[2]
0	0	1	0	CELL[5].DBL_W0[3]
0	1	0	1	CELL[2].DBL_E0[2]
0	1	1	0	CELL[2].DBL_E0[3]
1	0	0	1	CELL[4].DBL_W0[2]
1	0	1	0	CELL[4].DBL_W0[3]
1	1	0	1	CELL[3].DBL_E0[2]
1	1	1	0	CELL[3].DBL_E0[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits				Destination
MAIN[0][46]	MAIN[0][47]	MAIN[0][43]	MAIN[0][44]	CELL[4].IMUX_BUFG_CLK_INT[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[4]
0	0	1	0	CELL[5].DBL_W0[5]
0	1	0	1	CELL[2].DBL_E0[4]
0	1	1	0	CELL[2].DBL_E0[5]
1	0	0	1	CELL[4].DBL_W0[4]
1	0	1	0	CELL[4].DBL_W0[5]
1	1	0	1	CELL[3].DBL_E0[4]
1	1	1	0	CELL[3].DBL_E0[5]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits				Destination
MAIN[0][59]	MAIN[0][58]	MAIN[0][62]	MAIN[0][61]	CELL[4].IMUX_BUFG_CLK_INT[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[6]
0	0	1	0	CELL[5].DBL_W0[7]
0	1	0	1	CELL[2].DBL_E0[6]
0	1	1	0	CELL[2].DBL_E0[7]
1	0	0	1	CELL[4].DBL_W0[6]
1	0	1	0	CELL[4].DBL_W0[7]
1	1	0	1	CELL[3].DBL_E0[6]
1	1	1	0	CELL[3].DBL_E0[7]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits					Destination
MAIN[0][12]	MAIN[0][16]	MAIN[0][15]	MAIN[0][14]	MAIN[0][13]	CELL[4].IMUX_BUFG_CLK[0]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[3].OUT_CLKPAD[0]
0	0	0	1	0	CELL[3].DCM_BUS[0]
0	0	1	0	0	CELL[4].DCM_BUS[0]
0	1	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[0]
1	0	0	0	0	CELL[5].OUT_CLKPAD[0]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits					Destination
MAIN[0][33]	MAIN[0][37]	MAIN[0][36]	MAIN[0][35]	MAIN[0][34]	CELL[4].IMUX_BUFG_CLK[1]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[3].OUT_CLKPAD[1]
0	0	0	1	0	CELL[3].DCM_BUS[1]
0	0	1	0	0	CELL[4].DCM_BUS[1]
0	1	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[1]
1	0	0	0	0	CELL[5].OUT_CLKPAD[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits					Destination
MAIN[0][52]	MAIN[0][51]	MAIN[0][48]	MAIN[0][50]	MAIN[0][49]	CELL[4].IMUX_BUFG_CLK[2]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[2].OUT_CLKPAD[0]
0	0	0	1	0	CELL[3].DCM_BUS[2]
0	0	1	0	0	CELL[4].OUT_CLKPAD[0]
0	1	0	0	0	CELL[4].DCM_BUS[2]
1	0	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[2]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits					Destination
MAIN[0][57]	MAIN[0][56]	MAIN[0][53]	MAIN[0][55]	MAIN[0][54]	CELL[4].IMUX_BUFG_CLK[3]
					Source
0	0	0	0	0	off
0	0	0	0	1	CELL[2].OUT_CLKPAD[1]
0	0	0	1	0	CELL[3].DCM_BUS[3]
0	0	1	0	0	CELL[4].OUT_CLKPAD[1]
0	1	0	0	0	CELL[4].DCM_BUS[3]
1	0	0	0	0	CELL[4].IMUX_BUFG_CLK_INT[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits				Destination
MAIN[0][4]	MAIN[0][3]	MAIN[0][8]	MAIN[0][5]	CELL[4].IMUX_BUFG_SEL[0]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[0]
0	0	1	0	CELL[5].DBL_W0[1]
0	1	0	1	CELL[2].DBL_E0[0]
0	1	1	0	CELL[2].DBL_E0[1]
1	0	0	1	CELL[4].DBL_W0[0]
1	0	1	0	CELL[4].DBL_W0[1]
1	1	0	1	CELL[3].DBL_E0[0]
1	1	1	0	CELL[3].DBL_E0[1]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits				Destination
MAIN[0][25]	MAIN[0][24]	MAIN[0][26]	MAIN[0][29]	CELL[4].IMUX_BUFG_SEL[1]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[2]
0	0	1	0	CELL[5].DBL_W0[3]
0	1	0	1	CELL[2].DBL_E0[2]
0	1	1	0	CELL[2].DBL_E0[3]
1	0	0	1	CELL[4].DBL_W0[2]
1	0	1	0	CELL[4].DBL_W0[3]
1	1	0	1	CELL[3].DBL_E0[2]
1	1	1	0	CELL[3].DBL_E0[3]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits				Destination
MAIN[0][41]	MAIN[0][40]	MAIN[0][42]	MAIN[0][45]	CELL[4].IMUX_BUFG_SEL[2]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[4]
0	0	1	0	CELL[5].DBL_W0[5]
0	1	0	1	CELL[2].DBL_E0[4]
0	1	1	0	CELL[2].DBL_E0[5]
1	0	0	1	CELL[4].DBL_W0[4]
1	0	1	0	CELL[4].DBL_W0[5]
1	1	0	1	CELL[3].DBL_E0[4]
1	1	1	0	CELL[3].DBL_E0[5]

spartan3 CLK_N_S3A switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits				Destination
TERM[0][0]	TERM[0][1]	MAIN[0][63]	MAIN[0][60]	CELL[4].IMUX_BUFG_SEL[3]
				Source
0	0	0	0	CELL[0].PULLUP
0	0	0	1	CELL[5].DBL_W0[6]
0	0	1	0	CELL[5].DBL_W0[7]
0	1	0	1	CELL[2].DBL_E0[6]
0	1	1	0	CELL[2].DBL_E0[7]
1	0	0	1	CELL[4].DBL_W0[6]
1	0	1	0	CELL[4].DBL_W0[7]
1	1	0	1	CELL[3].DBL_E0[6]
1	1	1	0	CELL[3].DBL_E0[7]

Bels BUFGMUX

spartan3 CLK_N_S3A bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
I0	in	CELL[4].IMUX_BUFG_CLK[0]	CELL[4].IMUX_BUFG_CLK[1]	CELL[4].IMUX_BUFG_CLK[2]	CELL[4].IMUX_BUFG_CLK[3]
I1	in	CELL[4].IMUX_BUFG_CLK[1]	CELL[4].IMUX_BUFG_CLK[0]	CELL[4].IMUX_BUFG_CLK[3]	CELL[4].IMUX_BUFG_CLK[2]
S	in	CELL[4].IMUX_BUFG_SEL[0] invert by !MAIN[0][2]	CELL[4].IMUX_BUFG_SEL[1] invert by !MAIN[0][23]	CELL[4].IMUX_BUFG_SEL[2] invert by !MAIN[0][39]	CELL[4].IMUX_BUFG_SEL[3] invert by !TERM[0][2]
O	out	CELL[4].GCLK_N[0]	CELL[4].GCLK_N[1]	CELL[4].GCLK_N[2]	CELL[4].GCLK_N[3]

spartan3 CLK_N_S3A bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]
INIT_OUT bit 0	MAIN[0][11]	MAIN[0][32]	MAIN[0][38]	MAIN[0][1]

Bels GLOBALSIG_BUFG

spartan3 CLK_N_S3A bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]

spartan3 CLK_N_S3A bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]
GWE_ENABLE	!MAIN[0][0]

Bel wires

spartan3 CLK_N_S3A bel wires
Wire	Pins
CELL[4].GCLK_N[0]	BUFGMUX[0].O
CELL[4].GCLK_N[1]	BUFGMUX[1].O
CELL[4].GCLK_N[2]	BUFGMUX[2].O
CELL[4].GCLK_N[3]	BUFGMUX[3].O
CELL[4].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0, BUFGMUX[1].I1
CELL[4].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0, BUFGMUX[0].I1
CELL[4].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0, BUFGMUX[3].I1
CELL[4].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0, BUFGMUX[2].I1
CELL[4].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[4].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[4].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[4].IMUX_BUFG_SEL[3]	BUFGMUX[3].S

Bitstream

spartan3 CLK_N_S3A rect MAIN
Bit	Frame
Bit	F0
B63	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 1
B62	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 1
B61	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 0
B60	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 0
B59	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 3
B58	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[3] bit 2
B57	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 4
B56	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 3
B55	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 1
B54	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 0
B53	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[3] bit 2
B52	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 4
B51	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 3
B50	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 1
B49	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 0
B48	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[2] bit 2
B47	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 2
B46	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 3
B45	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 0
B44	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 0
B43	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[2] bit 1
B42	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 1
B41	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 3
B40	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[2] bit 2
B39	BUFGMUX[2]: !invert S
B38	BUFGMUX[2]: INIT_OUT bit 0
B37	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 3
B36	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 2
B35	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 1
B34	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 0
B33	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[1] bit 4
B32	BUFGMUX[1]: INIT_OUT bit 0
B31	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 2
B30	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 3
B29	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 0
B28	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 0
B27	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[1] bit 1
B26	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 1
B25	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 3
B24	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[1] bit 2
B23	BUFGMUX[1]: !invert S
B22	CLK_INT: mux CELL[3].OMUX_S4 bit 0
B21	CLK_INT: mux CELL[3].OMUX_S5 bit 0
B20	CLK_INT: mux CELL[3].OMUX_S4 bit 2
B19	CLK_INT: mux CELL[3].OMUX_S4 bit 1
B18	CLK_INT: mux CELL[3].OMUX_S5 bit 1
B17	CLK_INT: mux CELL[3].OMUX_S5 bit 2
B16	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 3
B15	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 2
B14	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 1
B13	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 0
B12	CLK_INT: mux CELL[4].IMUX_BUFG_CLK[0] bit 4
B11	BUFGMUX[0]: INIT_OUT bit 0
B10	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 2
B9	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 3
B8	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 1
B7	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 1
B6	CLK_INT: mux CELL[4].IMUX_BUFG_CLK_INT[0] bit 0
B5	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 0
B4	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 3
B3	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[0] bit 2
B2	BUFGMUX[0]: !invert S
B1	BUFGMUX[3]: INIT_OUT bit 0
B0	GLOBALSIG_BUFG[0]: ! GWE_ENABLE

spartan3 CLK_N_S3A rect TERM
Bit	Frame
Bit	F1	F0
B15	-	-
B14	-	-
B13	-	-
B12	-	-
B11	-	-
B10	-	-
B9	-	-
B8	-	-
B7	-	-
B6	-	-
B5	CLK_INT: mux CELL[3].OMUX_S3 bit 1	-
B4	CLK_INT: mux CELL[3].OMUX_S3 bit 2	-
B3	CLK_INT: mux CELL[3].OMUX_S0 bit 0	-
B2	CLK_INT: mux CELL[3].OMUX_S0 bit 2	BUFGMUX[3]: !invert S
B1	CLK_INT: mux CELL[3].OMUX_S3 bit 0	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 2
B0	CLK_INT: mux CELL[3].OMUX_S0 bit 1	CLK_INT: mux CELL[4].IMUX_BUFG_SEL[3] bit 3

Keyboard shortcuts

Project Combine