TODO: document
The CLKB.*
tiles use two bitstream tiles:
tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the bottom interconnect row
tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the low special area (used for bottom IOB
tiles and clock rows in normal columns)
On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH.CLKB.S3A
tile.
This tile is used on Spartan 3.
BUFGMUX0:DISABLE_ATTR
0.0.62
BUFGMUX1:DISABLE_ATTR
0.0.18
BUFGMUX2:DISABLE_ATTR
0.0.32
BUFGMUX3:DISABLE_ATTR
0.0.52
LOW
0
HIGH
1
BUFGMUX0:MUX.CLK
0.0.11
0.0.12
0.0.13
0.0.10
BUFGMUX1:MUX.CLK
0.0.15
0.0.16
0.0.17
0.0.14
BUFGMUX2:MUX.CLK
0.0.29
0.0.30
0.0.31
0.0.28
BUFGMUX3:MUX.CLK
0.0.49
0.0.50
0.0.51
0.0.48
INT
0
0
0
1
CKI
0
0
1
0
DCM_OUT_L
0
1
0
0
DCM_OUT_R
1
0
0
0
INT:INV.0.CLK.IMUX.SEL0
0.0.1
INT:INV.0.CLK.IMUX.SEL1
0.0.27
INT:INV.0.CLK.IMUX.SEL2
0.0.41
INT:INV.0.CLK.IMUX.SEL3
0.0.61
inverted
~[0]
INT:MUX.CLK.IMUX.CLK0
0.0.9
0.0.8
0.0.6
0.0.5
INT:MUX.CLK.IMUX.SEL0
0.0.2
0.0.3
0.0.7
0.0.4
PULLUP
0
0
0
0
DBL.W0.2
0
0
0
1
DBL.W1.2
0
0
1
0
DBL.W0.1
0
1
0
1
DBL.W1.1
0
1
1
0
DBL.E0.1
1
0
0
1
DBL.E1.1
1
0
1
0
DBL.E0.0
1
1
0
1
DBL.E1.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK1
0.0.20
0.0.19
0.0.23
0.0.22
INT:MUX.CLK.IMUX.SEL1
0.0.25
0.0.26
0.0.24
0.0.21
PULLUP
0
0
0
0
DBL.W2.2
0
0
0
1
DBL.W3.2
0
0
1
0
DBL.W2.1
0
1
0
1
DBL.W3.1
0
1
1
0
DBL.E2.1
1
0
0
1
DBL.E3.1
1
0
1
0
DBL.E2.0
1
1
0
1
DBL.E3.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK2
0.0.34
0.0.33
0.0.37
0.0.36
INT:MUX.CLK.IMUX.SEL2
0.0.39
0.0.40
0.0.38
0.0.35
PULLUP
0
0
0
0
DBL.W4.2
0
0
0
1
DBL.W5.2
0
0
1
0
DBL.W4.1
0
1
0
1
DBL.W5.1
0
1
1
0
DBL.E4.1
1
0
0
1
DBL.E5.1
1
0
1
0
DBL.E4.0
1
1
0
1
DBL.E5.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK3
0.0.54
0.0.53
0.0.57
0.0.56
INT:MUX.CLK.IMUX.SEL3
0.0.59
0.0.60
0.0.58
0.0.55
PULLUP
0
0
0
0
DBL.W6.2
0
0
0
1
DBL.W7.2
0
0
1
0
DBL.W6.1
0
1
0
1
DBL.W7.1
0
1
1
0
DBL.E6.1
1
0
0
1
DBL.E7.1
1
0
1
0
DBL.E6.0
1
1
0
1
DBL.E7.0
1
1
1
0
INT:MUX.OMUX10.N
1.0.8
1.0.9
0.0.0
INT:MUX.OMUX11.N
1.0.11
1.0.7
1.0.10
INT:MUX.OMUX12.N
0.0.44
0.0.45
0.0.42
INT:MUX.OMUX15.N
0.0.47
0.0.46
0.0.43
NONE
0
0
0
CLK.OUT.2
0
0
1
CLK.OUT.3
0
1
0
CLK.OUT.0
1
0
1
CLK.OUT.1
1
1
0
This tile is used on Spartan 3E.
BUFGMUX0:DISABLE_ATTR
0.0.52
BUFGMUX1:DISABLE_ATTR
0.0.31
BUFGMUX2:DISABLE_ATTR
0.0.25
BUFGMUX3:DISABLE_ATTR
0.0.62
LOW
0
HIGH
1
BUFGMUX0:MUX.CLK
0.0.48
0.0.49
0.0.51
0.0.50
0.0.47
BUFGMUX1:MUX.CLK
0.0.27
0.0.28
0.0.30
0.0.29
0.0.26
BUFGMUX2:MUX.CLK
0.0.12
0.0.13
0.0.15
0.0.14
0.0.11
BUFGMUX3:MUX.CLK
0.0.7
0.0.8
0.0.10
0.0.9
0.0.6
INT
0
0
0
0
1
CKIL
0
0
0
1
0
CKIR
0
0
1
0
0
DCM_OUT_L
0
1
0
0
0
DCM_OUT_R
1
0
0
0
0
INT:INV.0.CLK.IMUX.SEL0
0.0.61
INT:INV.0.CLK.IMUX.SEL1
0.0.40
INT:INV.0.CLK.IMUX.SEL2
0.0.24
INT:INV.0.CLK.IMUX.SEL3
1.0.9
inverted
~[0]
INT:MUX.CLK.IMUX.CLK0
0.0.53
0.0.54
0.0.56
0.0.57
INT:MUX.CLK.IMUX.SEL0
0.0.60
0.0.59
0.0.55
0.0.58
PULLUP
0
0
0
0
DBL.W6.2
0
0
0
1
DBL.W7.2
0
0
1
0
DBL.W6.1
0
1
0
1
DBL.W7.1
0
1
1
0
DBL.E6.1
1
0
0
1
DBL.E7.1
1
0
1
0
DBL.E6.0
1
1
0
1
DBL.E7.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK1
0.0.32
0.0.33
0.0.35
0.0.36
INT:MUX.CLK.IMUX.SEL1
0.0.39
0.0.38
0.0.34
0.0.37
PULLUP
0
0
0
0
DBL.W4.2
0
0
0
1
DBL.W5.2
0
0
1
0
DBL.W4.1
0
1
0
1
DBL.W5.1
0
1
1
0
DBL.E4.1
1
0
0
1
DBL.E5.1
1
0
1
0
DBL.E4.0
1
1
0
1
DBL.E5.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK2
0.0.16
0.0.17
0.0.19
0.0.20
INT:MUX.CLK.IMUX.SEL2
0.0.23
0.0.22
0.0.18
0.0.21
PULLUP
0
0
0
0
DBL.W2.2
0
0
0
1
DBL.W3.2
0
0
1
0
DBL.W2.1
0
1
0
1
DBL.W3.1
0
1
1
0
DBL.E2.1
1
0
0
1
DBL.E3.1
1
0
1
0
DBL.E2.0
1
1
0
1
DBL.E3.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK3
0.0.5
0.0.4
0.0.1
0.0.2
INT:MUX.CLK.IMUX.SEL3
1.0.10
1.0.11
0.0.0
0.0.3
PULLUP
0
0
0
0
DBL.W0.2
0
0
0
1
DBL.W1.2
0
0
1
0
DBL.W0.1
0
1
0
1
DBL.W1.1
0
1
1
0
DBL.E0.1
1
0
0
1
DBL.E1.1
1
0
1
0
DBL.E0.0
1
1
0
1
DBL.E1.0
1
1
1
0
INT:MUX.OMUX10.N
1.0.12
1.0.13
1.0.8
INT:MUX.OMUX11.N
1.0.7
1.0.14
1.0.15
INT:MUX.OMUX12.N
0.0.43
0.0.44
0.0.41
INT:MUX.OMUX15.N
0.0.46
0.0.45
0.0.42
NONE
0
0
0
CLK.OUT.2
0
0
1
CLK.OUT.3
0
1
0
CLK.OUT.0
1
0
1
CLK.OUT.1
1
1
0
This tile is used on Spartan 3A and 3A DSP.
BUFGMUX0:DISABLE_ATTR
0.0.52
BUFGMUX1:DISABLE_ATTR
0.0.31
BUFGMUX2:DISABLE_ATTR
0.0.25
BUFGMUX3:DISABLE_ATTR
0.0.62
LOW
0
HIGH
1
BUFGMUX0:MUX.CLK
0.0.48
0.0.49
0.0.51
0.0.50
0.0.47
BUFGMUX1:MUX.CLK
0.0.27
0.0.28
0.0.30
0.0.29
0.0.26
BUFGMUX2:MUX.CLK
0.0.12
0.0.13
0.0.15
0.0.14
0.0.11
BUFGMUX3:MUX.CLK
0.0.7
0.0.8
0.0.10
0.0.9
0.0.6
INT
0
0
0
0
1
CKIL
0
0
0
1
0
CKIR
0
0
1
0
0
DCM_OUT_L
0
1
0
0
0
DCM_OUT_R
1
0
0
0
0
INT:INV.0.CLK.IMUX.SEL0
0.0.61
INT:INV.0.CLK.IMUX.SEL1
0.0.40
INT:INV.0.CLK.IMUX.SEL2
0.0.24
INT:INV.0.CLK.IMUX.SEL3
1.0.2
inverted
~[0]
INT:MUX.CLK.IMUX.CLK0
0.0.53
0.0.54
0.0.56
0.0.57
INT:MUX.CLK.IMUX.SEL0
0.0.60
0.0.59
0.0.55
0.0.58
PULLUP
0
0
0
0
DBL.W6.2
0
0
0
1
DBL.W7.2
0
0
1
0
DBL.W6.1
0
1
0
1
DBL.W7.1
0
1
1
0
DBL.E6.1
1
0
0
1
DBL.E7.1
1
0
1
0
DBL.E6.0
1
1
0
1
DBL.E7.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK1
0.0.32
0.0.33
0.0.35
0.0.36
INT:MUX.CLK.IMUX.SEL1
0.0.39
0.0.38
0.0.34
0.0.37
PULLUP
0
0
0
0
DBL.W4.2
0
0
0
1
DBL.W5.2
0
0
1
0
DBL.W4.1
0
1
0
1
DBL.W5.1
0
1
1
0
DBL.E4.1
1
0
0
1
DBL.E5.1
1
0
1
0
DBL.E4.0
1
1
0
1
DBL.E5.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK2
0.0.16
0.0.17
0.0.19
0.0.20
INT:MUX.CLK.IMUX.SEL2
0.0.23
0.0.22
0.0.18
0.0.21
PULLUP
0
0
0
0
DBL.W2.2
0
0
0
1
DBL.W3.2
0
0
1
0
DBL.W2.1
0
1
0
1
DBL.W3.1
0
1
1
0
DBL.E2.1
1
0
0
1
DBL.E3.1
1
0
1
0
DBL.E2.0
1
1
0
1
DBL.E3.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK3
0.0.5
0.0.4
0.0.1
0.0.2
INT:MUX.CLK.IMUX.SEL3
1.0.3
1.0.4
0.0.0
0.0.3
PULLUP
0
0
0
0
DBL.W0.2
0
0
0
1
DBL.W1.2
0
0
1
0
DBL.W0.1
0
1
0
1
DBL.W1.1
0
1
1
0
DBL.E0.1
1
0
0
1
DBL.E1.1
1
0
1
0
DBL.E0.0
1
1
0
1
DBL.E1.0
1
1
1
0
INT:MUX.OMUX10.N
1.1.5
1.1.2
1.1.1
INT:MUX.OMUX11.N
1.1.0
1.1.3
1.1.4
INT:MUX.OMUX12.N
0.0.43
0.0.44
0.0.41
INT:MUX.OMUX15.N
0.0.46
0.0.45
0.0.42
NONE
0
0
0
CLK.OUT.2
0
0
1
CLK.OUT.3
0
1
0
CLK.OUT.0
1
0
1
CLK.OUT.1
1
1
0
The CLKT.*
tiles use two bitstream tiles:
tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the top interconnect row
tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the high special area (used for top IOB
tiles and clock rows in normal columns)
On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the LLH.CLKT.S3A
tile.
This tile is used on Spartan 3.
BUFGMUX0:DISABLE_ATTR
0.0.11
BUFGMUX1:DISABLE_ATTR
0.0.31
BUFGMUX2:DISABLE_ATTR
0.0.45
BUFGMUX3:DISABLE_ATTR
0.0.1
LOW
0
HIGH
1
BUFGMUX0:MUX.CLK
0.0.14
0.0.13
0.0.12
0.0.15
BUFGMUX1:MUX.CLK
0.0.34
0.0.33
0.0.32
0.0.35
BUFGMUX2:MUX.CLK
0.0.48
0.0.47
0.0.46
0.0.49
BUFGMUX3:MUX.CLK
0.0.52
0.0.51
0.0.50
0.0.53
INT
0
0
0
1
CKI
0
0
1
0
DCM_OUT_L
0
1
0
0
DCM_OUT_R
1
0
0
0
INT:INV.0.CLK.IMUX.SEL0
0.0.2
INT:INV.0.CLK.IMUX.SEL1
0.0.22
INT:INV.0.CLK.IMUX.SEL2
0.0.36
INT:INV.0.CLK.IMUX.SEL3
0.0.62
inverted
~[0]
INT:MUX.CLK.IMUX.CLK0
0.0.9
0.0.10
0.0.7
0.0.6
INT:MUX.CLK.IMUX.SEL0
0.0.4
0.0.3
0.0.8
0.0.5
PULLUP
0
0
0
0
DBL.W0.2
0
0
0
1
DBL.W1.2
0
0
1
0
DBL.W0.1
0
1
0
1
DBL.W1.1
0
1
1
0
DBL.E0.1
1
0
0
1
DBL.E1.1
1
0
1
0
DBL.E0.0
1
1
0
1
DBL.E1.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK1
0.0.29
0.0.30
0.0.27
0.0.26
INT:MUX.CLK.IMUX.SEL1
0.0.24
0.0.23
0.0.28
0.0.25
PULLUP
0
0
0
0
DBL.W2.2
0
0
0
1
DBL.W3.2
0
0
1
0
DBL.W2.1
0
1
0
1
DBL.W3.1
0
1
1
0
DBL.E2.1
1
0
0
1
DBL.E3.1
1
0
1
0
DBL.E2.0
1
1
0
1
DBL.E3.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK2
0.0.43
0.0.44
0.0.41
0.0.40
INT:MUX.CLK.IMUX.SEL2
0.0.38
0.0.37
0.0.42
0.0.39
PULLUP
0
0
0
0
DBL.W4.2
0
0
0
1
DBL.W5.2
0
0
1
0
DBL.W4.1
0
1
0
1
DBL.W5.1
0
1
1
0
DBL.E4.1
1
0
0
1
DBL.E5.1
1
0
1
0
DBL.E4.0
1
1
0
1
DBL.E5.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK3
0.0.54
0.0.55
0.0.58
0.0.57
INT:MUX.CLK.IMUX.SEL3
0.0.61
0.0.60
0.0.59
0.0.56
PULLUP
0
0
0
0
DBL.W6.2
0
0
0
1
DBL.W7.2
0
0
1
0
DBL.W6.1
0
1
0
1
DBL.W7.1
0
1
1
0
DBL.E6.1
1
0
0
1
DBL.E7.1
1
0
1
0
DBL.E6.0
1
1
0
1
DBL.E7.0
1
1
1
0
INT:MUX.OMUX0.S
1.0.3
1.0.2
0.0.63
INT:MUX.OMUX3.S
1.0.0
1.0.4
1.0.1
INT:MUX.OMUX4.S
0.0.19
0.0.18
0.0.21
INT:MUX.OMUX5.S
0.0.16
0.0.17
0.0.20
NONE
0
0
0
CLK.OUT.2
0
0
1
CLK.OUT.3
0
1
0
CLK.OUT.0
1
0
1
CLK.OUT.1
1
1
0
This tile is used on Spartan 3E.
BUFGMUX0:DISABLE_ATTR
0.0.11
BUFGMUX1:DISABLE_ATTR
0.0.32
BUFGMUX2:DISABLE_ATTR
0.0.38
BUFGMUX3:DISABLE_ATTR
0.0.1
LOW
0
HIGH
1
BUFGMUX0:MUX.CLK
0.0.15
0.0.14
0.0.12
0.0.13
0.0.16
BUFGMUX1:MUX.CLK
0.0.36
0.0.35
0.0.33
0.0.34
0.0.37
BUFGMUX2:MUX.CLK
0.0.51
0.0.50
0.0.48
0.0.49
0.0.52
BUFGMUX3:MUX.CLK
0.0.56
0.0.55
0.0.53
0.0.54
0.0.57
INT
0
0
0
0
1
CKIL
0
0
0
1
0
CKIR
0
0
1
0
0
DCM_OUT_L
0
1
0
0
0
DCM_OUT_R
1
0
0
0
0
INT:INV.0.CLK.IMUX.SEL0
0.0.2
INT:INV.0.CLK.IMUX.SEL1
0.0.23
INT:INV.0.CLK.IMUX.SEL2
0.0.39
INT:INV.0.CLK.IMUX.SEL3
1.0.2
inverted
~[0]
INT:MUX.CLK.IMUX.CLK0
0.0.10
0.0.9
0.0.7
0.0.6
INT:MUX.CLK.IMUX.SEL0
0.0.3
0.0.4
0.0.8
0.0.5
PULLUP
0
0
0
0
DBL.W0.2
0
0
0
1
DBL.W1.2
0
0
1
0
DBL.W0.1
0
1
0
1
DBL.W1.1
0
1
1
0
DBL.E0.1
1
0
0
1
DBL.E1.1
1
0
1
0
DBL.E0.0
1
1
0
1
DBL.E1.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK1
0.0.31
0.0.30
0.0.28
0.0.27
INT:MUX.CLK.IMUX.SEL1
0.0.24
0.0.25
0.0.29
0.0.26
PULLUP
0
0
0
0
DBL.W2.2
0
0
0
1
DBL.W3.2
0
0
1
0
DBL.W2.1
0
1
0
1
DBL.W3.1
0
1
1
0
DBL.E2.1
1
0
0
1
DBL.E3.1
1
0
1
0
DBL.E2.0
1
1
0
1
DBL.E3.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK2
0.0.47
0.0.46
0.0.44
0.0.43
INT:MUX.CLK.IMUX.SEL2
0.0.40
0.0.41
0.0.45
0.0.42
PULLUP
0
0
0
0
DBL.W4.2
0
0
0
1
DBL.W5.2
0
0
1
0
DBL.W4.1
0
1
0
1
DBL.W5.1
0
1
1
0
DBL.E4.1
1
0
0
1
DBL.E5.1
1
0
1
0
DBL.E4.0
1
1
0
1
DBL.E5.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK3
0.0.58
0.0.59
0.0.62
0.0.61
INT:MUX.CLK.IMUX.SEL3
1.0.1
1.0.0
0.0.63
0.0.60
PULLUP
0
0
0
0
DBL.W6.2
0
0
0
1
DBL.W7.2
0
0
1
0
DBL.W6.1
0
1
0
1
DBL.W7.1
0
1
1
0
DBL.E6.1
1
0
0
1
DBL.E7.1
1
0
1
0
DBL.E6.0
1
1
0
1
DBL.E7.0
1
1
1
0
INT:MUX.OMUX0.S
1.0.6
1.0.7
1.0.3
INT:MUX.OMUX3.S
1.0.4
1.0.5
1.0.8
INT:MUX.OMUX4.S
0.0.20
0.0.19
0.0.22
INT:MUX.OMUX5.S
0.0.17
0.0.18
0.0.21
NONE
0
0
0
CLK.OUT.2
0
0
1
CLK.OUT.3
0
1
0
CLK.OUT.0
1
0
1
CLK.OUT.1
1
1
0
This tile is used on Spartan 3A and 3A DSP.
BUFGMUX0:DISABLE_ATTR
0.0.11
BUFGMUX1:DISABLE_ATTR
0.0.32
BUFGMUX2:DISABLE_ATTR
0.0.38
BUFGMUX3:DISABLE_ATTR
0.0.1
LOW
0
HIGH
1
BUFGMUX0:MUX.CLK
0.0.15
0.0.14
0.0.12
0.0.13
0.0.16
BUFGMUX1:MUX.CLK
0.0.36
0.0.35
0.0.33
0.0.34
0.0.37
BUFGMUX2:MUX.CLK
0.0.51
0.0.50
0.0.48
0.0.49
0.0.52
BUFGMUX3:MUX.CLK
0.0.56
0.0.55
0.0.53
0.0.54
0.0.57
INT
0
0
0
0
1
CKIL
0
0
0
1
0
CKIR
0
0
1
0
0
DCM_OUT_L
0
1
0
0
0
DCM_OUT_R
1
0
0
0
0
INT:INV.0.CLK.IMUX.SEL0
0.0.2
INT:INV.0.CLK.IMUX.SEL1
0.0.23
INT:INV.0.CLK.IMUX.SEL2
0.0.39
INT:INV.0.CLK.IMUX.SEL3
1.0.2
inverted
~[0]
INT:MUX.CLK.IMUX.CLK0
0.0.10
0.0.9
0.0.7
0.0.6
INT:MUX.CLK.IMUX.SEL0
0.0.3
0.0.4
0.0.8
0.0.5
PULLUP
0
0
0
0
DBL.W0.2
0
0
0
1
DBL.W1.2
0
0
1
0
DBL.W0.1
0
1
0
1
DBL.W1.1
0
1
1
0
DBL.E0.1
1
0
0
1
DBL.E1.1
1
0
1
0
DBL.E0.0
1
1
0
1
DBL.E1.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK1
0.0.31
0.0.30
0.0.27
0.0.28
INT:MUX.CLK.IMUX.SEL1
0.0.24
0.0.25
0.0.26
0.0.29
PULLUP
0
0
0
0
DBL.W2.2
0
0
0
1
DBL.W3.2
0
0
1
0
DBL.W2.1
0
1
0
1
DBL.W3.1
0
1
1
0
DBL.E2.1
1
0
0
1
DBL.E3.1
1
0
1
0
DBL.E2.0
1
1
0
1
DBL.E3.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK2
0.0.47
0.0.46
0.0.43
0.0.44
INT:MUX.CLK.IMUX.SEL2
0.0.40
0.0.41
0.0.42
0.0.45
PULLUP
0
0
0
0
DBL.W4.2
0
0
0
1
DBL.W5.2
0
0
1
0
DBL.W4.1
0
1
0
1
DBL.W5.1
0
1
1
0
DBL.E4.1
1
0
0
1
DBL.E5.1
1
0
1
0
DBL.E4.0
1
1
0
1
DBL.E5.0
1
1
1
0
INT:MUX.CLK.IMUX.CLK3
0.0.58
0.0.59
0.0.62
0.0.61
INT:MUX.CLK.IMUX.SEL3
1.0.1
1.0.0
0.0.63
0.0.60
PULLUP
0
0
0
0
DBL.W6.2
0
0
0
1
DBL.W7.2
0
0
1
0
DBL.W6.1
0
1
0
1
DBL.W7.1
0
1
1
0
DBL.E6.1
1
0
0
1
DBL.E7.1
1
0
1
0
DBL.E6.0
1
1
0
1
DBL.E7.0
1
1
1
0
INT:MUX.OMUX0.S
1.1.2
1.1.0
1.1.3
INT:MUX.OMUX3.S
1.1.4
1.1.5
1.1.1
INT:MUX.OMUX4.S
0.0.20
0.0.19
0.0.22
INT:MUX.OMUX5.S
0.0.17
0.0.18
0.0.21
NONE
0
0
0
CLK.OUT.2
0
0
1
CLK.OUT.3
0
1
0
CLK.OUT.0
1
0
1
CLK.OUT.1
1
1
0