Clock quadrant distribution

The `CLKC` clock center tile

The CLKC tile is located in the center of the FPGA (intersection of primary vertical and horizontal clock spines) of all devices except xc3s50a. It has permanent buffers forwarding the clock signals from CLKB and CLKT to GCLKVM. It has no configuration.

TODO: describe exact forwarding

Tile CLKC

Cells: 0

Bel CLKC

spartan3 CLKC bel CLKC
Pin	Direction	Wires

The `CLKC_50A` clock center tile

TODO: document

Tile CLKC_50A

Cells: 0

Bel CLKC_50A

spartan3 CLKC_50A bel CLKC_50A
Pin	Direction	Wires

Bitstream

spartan3 CLKC_50A rect MAIN
Bit	Frame
Bit	F0	F1
B63	-	-
B62	-	-
B61	-	-
B60	-	-
B59	-	-
B58	-	-
B57	-	-
B56	-	-
B55	-	-
B54	-	-
B53	-	-
B52	-	-
B51	-	-
B50	-	-
B49	-	-
B48	-	-
B47	-	-
B46	-	-
B45	-	-
B44	-	-
B43	-	-
B42	-	-
B41	-	-
B40	-	-
B39	-	-
B38	-	-
B37	-	-
B36	-	-
B35	-	-
B34	-	-
B33	-	-
B32	-	-
B31	-	-
B30	-	-
B29	-	-
B28	-	-
B27	-	-
B26	-	-
B25	-	-
B24	-	-
B23	-	-
B22	-	-
B21	-	-
B20	-	-
B19	-	-
B18	-	-
B17	-	-
B16	-	-
B15	-	-
B14	-	-
B13	-	-
B12	-	-
B11	-	-
B10	-	-
B9	-	-
B8	-	-
B7	-	-
B6	-	-
B5	-	-
B4	-	-
B3	-	-
B2	-	-
B1	-	-
B0	-	-

### Bitstream

spartan3 CLKC_50A rect R0
Bit	Frame
Bit	F0	F1
B15	-	CLKC_50A:MUX.OUT_R7[0]
B14	-	CLKC_50A:MUX.OUT_R6[0]
B13	-	CLKC_50A:MUX.OUT_R5[0]
B12	-	CLKC_50A:MUX.OUT_R4[0]
B11	-	CLKC_50A:MUX.OUT_R3[0]
B10	-	CLKC_50A:MUX.OUT_R2[0]
B9	-	CLKC_50A:MUX.OUT_R1[0]
B8	-	CLKC_50A:MUX.OUT_R0[0]
B7	-	CLKC_50A:MUX.OUT_L7[0]
B6	-	CLKC_50A:MUX.OUT_L6[0]
B5	-	CLKC_50A:MUX.OUT_L5[0]
B4	-	CLKC_50A:MUX.OUT_L4[0]
B3	-	CLKC_50A:MUX.OUT_L3[0]
B2	-	CLKC_50A:MUX.OUT_L2[0]
B1	-	CLKC_50A:MUX.OUT_L1[0]
B0	-	CLKC_50A:MUX.OUT_L0[0]

CLKC_50A:MUX.OUT_L0	0.F1.B0
IN_B0	0
IN_L0	1

CLKC_50A:MUX.OUT_L1	0.F1.B1
IN_B1	0
IN_L1	1

CLKC_50A:MUX.OUT_L2	0.F1.B2
IN_B2	0
IN_L2	1

CLKC_50A:MUX.OUT_L3	0.F1.B3
IN_B3	0
IN_L3	1

CLKC_50A:MUX.OUT_L4	0.F1.B4
IN_T0	0
IN_L4	1

CLKC_50A:MUX.OUT_L5	0.F1.B5
IN_T1	0
IN_L5	1

CLKC_50A:MUX.OUT_L6	0.F1.B6
IN_T2	0
IN_L6	1

CLKC_50A:MUX.OUT_L7	0.F1.B7
IN_T3	0
IN_L7	1

CLKC_50A:MUX.OUT_R0	0.F1.B8
IN_B0	0
IN_R0	1

CLKC_50A:MUX.OUT_R1	0.F1.B9
IN_B1	0
IN_R1	1

CLKC_50A:MUX.OUT_R2	0.F1.B10
IN_B2	0
IN_R2	1

CLKC_50A:MUX.OUT_R3	0.F1.B11
IN_B3	0
IN_R3	1

CLKC_50A:MUX.OUT_R4	0.F1.B12
IN_T0	0
IN_R4	1

CLKC_50A:MUX.OUT_R5	0.F1.B13
IN_T1	0
IN_R5	1

CLKC_50A:MUX.OUT_R6	0.F1.B14
IN_T2	0
IN_R6	1

CLKC_50A:MUX.OUT_R7	0.F1.B15
IN_T3	0
IN_R7	1

The `CLKQC` secondary clock center tiles

The CLKQC tiles are located on the intersection of secondary vertical clock spines and the horizontal clock spine.

TODO: document

Tile CLKQC_S3

Cells: 0

Bel CLKQC

spartan3 CLKQC_S3 bel CLKQC
Pin	Direction	Wires

Bitstream

spartan3 CLKQC_S3 rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

spartan3 CLKQC_S3 rect R0
Bit	Frame
Bit	F0
B38	CLKQC:BUF.OUT_B0
B37	-
B36	CLKQC:BUF.OUT_B1
B35	CLKQC:BUF.OUT_B7
B34	CLKQC:BUF.OUT_B2
B33	CLKQC:BUF.OUT_B6
B32	CLKQC:BUF.OUT_B5
B31	CLKQC:BUF.OUT_B4
B30	CLKQC:BUF.OUT_B3
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLKQC_S3 rect R1
Bit	Frame
Bit	F0
B33	CLKQC:BUF.OUT_T3
B32	CLKQC:BUF.OUT_T4
B31	CLKQC:BUF.OUT_T5
B30	CLKQC:BUF.OUT_T6
B29	CLKQC:BUF.OUT_T2
B28	CLKQC:BUF.OUT_T7
B27	CLKQC:BUF.OUT_T1
B26	-
B25	CLKQC:BUF.OUT_T0
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

CLKQC:BUF.OUT_B0	0.F0.B38
CLKQC:BUF.OUT_B1	0.F0.B36
CLKQC:BUF.OUT_B2	0.F0.B34
CLKQC:BUF.OUT_B3	0.F0.B30
CLKQC:BUF.OUT_B4	0.F0.B31
CLKQC:BUF.OUT_B5	0.F0.B32
CLKQC:BUF.OUT_B6	0.F0.B33
CLKQC:BUF.OUT_B7	0.F0.B35
CLKQC:BUF.OUT_T0	1.F0.B25
CLKQC:BUF.OUT_T1	1.F0.B27
CLKQC:BUF.OUT_T2	1.F0.B29
CLKQC:BUF.OUT_T3	1.F0.B33
CLKQC:BUF.OUT_T4	1.F0.B32
CLKQC:BUF.OUT_T5	1.F0.B31
CLKQC:BUF.OUT_T6	1.F0.B30
CLKQC:BUF.OUT_T7	1.F0.B28
non-inverted	[0]

Tile CLKQC_S3E

Cells: 0

Bel CLKQC

spartan3 CLKQC_S3E bel CLKQC
Pin	Direction	Wires

Bitstream

spartan3 CLKQC_S3E rect MAIN
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

### Bitstream

spartan3 CLKQC_S3E rect R0
Bit	Frame
Bit	F0
B57	CLKQC:MUX.OUT_B0[0]
B56	-
B55	CLKQC:MUX.OUT_B0[1]
B54	CLKQC:MUX.OUT_B1[0]
B53	CLKQC:MUX.OUT_B1[1]
B52	CLKQC:MUX.OUT_B2[0]
B51	CLKQC:MUX.OUT_B2[1]
B50	CLKQC:MUX.OUT_B3[0]
B49	CLKQC:MUX.OUT_B3[1]
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	CLKQC:MUX.OUT_B4[0]
B27	-
B26	CLKQC:MUX.OUT_B4[1]
B25	CLKQC:MUX.OUT_B5[0]
B24	CLKQC:MUX.OUT_B5[1]
B23	CLKQC:MUX.OUT_B6[0]
B22	CLKQC:MUX.OUT_B6[1]
B21	CLKQC:MUX.OUT_B7[0]
B20	CLKQC:MUX.OUT_B7[1]
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLKQC_S3E rect R1
Bit	Frame
Bit	F0
B42	CLKQC:MUX.OUT_T0[0]
B41	CLKQC:MUX.OUT_T0[1]
B40	CLKQC:MUX.OUT_T1[0]
B39	CLKQC:MUX.OUT_T1[1]
B38	CLKQC:MUX.OUT_T2[0]
B37	CLKQC:MUX.OUT_T2[1]
B36	CLKQC:MUX.OUT_T3[0]
B35	-
B34	CLKQC:MUX.OUT_T3[1]
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	CLKQC:MUX.OUT_T4[0]
B13	-
B12	CLKQC:MUX.OUT_T4[1]
B11	CLKQC:MUX.OUT_T5[0]
B10	CLKQC:MUX.OUT_T5[1]
B9	CLKQC:MUX.OUT_T6[0]
B8	CLKQC:MUX.OUT_T6[1]
B7	CLKQC:MUX.OUT_T7[0]
B6	CLKQC:MUX.OUT_T7[1]
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

CLKQC:MUX.OUT_B0	0.F0.B55	0.F0.B57
CLKQC:MUX.OUT_T0	1.F0.B41	1.F0.B42
NONE	0	0
IN_LR0	0	1
IN_CORE0	1	0

CLKQC:MUX.OUT_B1	0.F0.B53	0.F0.B54
CLKQC:MUX.OUT_T1	1.F0.B39	1.F0.B40
NONE	0	0
IN_LR1	0	1
IN_CORE1	1	0

CLKQC:MUX.OUT_B2	0.F0.B51	0.F0.B52
CLKQC:MUX.OUT_T2	1.F0.B37	1.F0.B38
NONE	0	0
IN_LR2	0	1
IN_CORE2	1	0

CLKQC:MUX.OUT_B3	0.F0.B49	0.F0.B50
CLKQC:MUX.OUT_T3	1.F0.B34	1.F0.B36
NONE	0	0
IN_LR3	0	1
IN_CORE3	1	0

CLKQC:MUX.OUT_B4	0.F0.B26	0.F0.B28
CLKQC:MUX.OUT_T4	1.F0.B12	1.F0.B14
NONE	0	0
IN_LR4	0	1
IN_CORE4	1	0

CLKQC:MUX.OUT_B5	0.F0.B24	0.F0.B25
CLKQC:MUX.OUT_T5	1.F0.B10	1.F0.B11
NONE	0	0
IN_LR5	0	1
IN_CORE5	1	0

CLKQC:MUX.OUT_B6	0.F0.B22	0.F0.B23
CLKQC:MUX.OUT_T6	1.F0.B8	1.F0.B9
NONE	0	0
IN_LR6	0	1
IN_CORE6	1	0

CLKQC:MUX.OUT_B7	0.F0.B20	0.F0.B21
CLKQC:MUX.OUT_T7	1.F0.B6	1.F0.B7
NONE	0	0
IN_LR7	0	1
IN_CORE7	1	0

The `HROW` clock spine distribution tiles

TODO: document

Tile HROW

Cells: 0

Bel HROW

spartan3 HROW bel HROW
Pin	Direction	Wires

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