Clock quadrant distribution

The `CLKC_50A` clock center tile

TODO: document

Tile CLKC_50A

Cells: 2

Switchbox HROW

spartan3 CLKC_50A switchbox HROW muxes GCLK_QUAD[0]
Bits	Destination
MAIN[1][0]	CELL_W.GCLK_QUAD[0]	-
MAIN[1][8]	-	CELL_E.GCLK_QUAD[0]
	Source
0	CELL_E.GCLK_S[0]	CELL_E.GCLK_S[0]
1	CELL_W.GCLK_WE[0]	CELL_E.GCLK_WE[0]

spartan3 CLKC_50A switchbox HROW muxes GCLK_QUAD[1]
Bits	Destination
MAIN[1][1]	CELL_W.GCLK_QUAD[1]	-
MAIN[1][9]	-	CELL_E.GCLK_QUAD[1]
	Source
0	CELL_E.GCLK_S[1]	CELL_E.GCLK_S[1]
1	CELL_W.GCLK_WE[1]	CELL_E.GCLK_WE[1]

spartan3 CLKC_50A switchbox HROW muxes GCLK_QUAD[2]
Bits	Destination
MAIN[1][2]	CELL_W.GCLK_QUAD[2]	-
MAIN[1][10]	-	CELL_E.GCLK_QUAD[2]
	Source
0	CELL_E.GCLK_S[2]	CELL_E.GCLK_S[2]
1	CELL_W.GCLK_WE[2]	CELL_E.GCLK_WE[2]

spartan3 CLKC_50A switchbox HROW muxes GCLK_QUAD[3]
Bits	Destination
MAIN[1][3]	CELL_W.GCLK_QUAD[3]	-
MAIN[1][11]	-	CELL_E.GCLK_QUAD[3]
	Source
0	CELL_E.GCLK_S[3]	CELL_E.GCLK_S[3]
1	CELL_W.GCLK_WE[3]	CELL_E.GCLK_WE[3]

spartan3 CLKC_50A switchbox HROW muxes GCLK_QUAD[4]
Bits	Destination
MAIN[1][4]	CELL_W.GCLK_QUAD[4]	-
MAIN[1][12]	-	CELL_E.GCLK_QUAD[4]
	Source
0	CELL_E.GCLK_N[0]	CELL_E.GCLK_N[0]
1	CELL_W.GCLK_WE[4]	CELL_E.GCLK_WE[4]

spartan3 CLKC_50A switchbox HROW muxes GCLK_QUAD[5]
Bits	Destination
MAIN[1][5]	CELL_W.GCLK_QUAD[5]	-
MAIN[1][13]	-	CELL_E.GCLK_QUAD[5]
	Source
0	CELL_E.GCLK_N[1]	CELL_E.GCLK_N[1]
1	CELL_W.GCLK_WE[5]	CELL_E.GCLK_WE[5]

spartan3 CLKC_50A switchbox HROW muxes GCLK_QUAD[6]
Bits	Destination
MAIN[1][6]	CELL_W.GCLK_QUAD[6]	-
MAIN[1][14]	-	CELL_E.GCLK_QUAD[6]
	Source
0	CELL_E.GCLK_N[2]	CELL_E.GCLK_N[2]
1	CELL_W.GCLK_WE[6]	CELL_E.GCLK_WE[6]

spartan3 CLKC_50A switchbox HROW muxes GCLK_QUAD[7]
Bits	Destination
MAIN[1][7]	CELL_W.GCLK_QUAD[7]	-
MAIN[1][15]	-	CELL_E.GCLK_QUAD[7]
	Source
0	CELL_E.GCLK_N[3]	CELL_E.GCLK_N[3]
1	CELL_W.GCLK_WE[7]	CELL_E.GCLK_WE[7]

Bitstream

spartan3 CLKC_50A rect MAIN
Bit	Frame
Bit	F1	F0
B63	-	-
B62	-	-
B61	-	-
B60	-	-
B59	-	-
B58	-	-
B57	-	-
B56	-	-
B55	-	-
B54	-	-
B53	-	-
B52	-	-
B51	-	-
B50	-	-
B49	-	-
B48	-	-
B47	-	-
B46	-	-
B45	-	-
B44	-	-
B43	-	-
B42	-	-
B41	-	-
B40	-	-
B39	-	-
B38	-	-
B37	-	-
B36	-	-
B35	-	-
B34	-	-
B33	-	-
B32	-	-
B31	-	-
B30	-	-
B29	-	-
B28	-	-
B27	-	-
B26	-	-
B25	-	-
B24	-	-
B23	-	-
B22	-	-
B21	-	-
B20	-	-
B19	-	-
B18	-	-
B17	-	-
B16	-	-
B15	HROW: mux CELL_E.GCLK_QUAD[7] bit 0	-
B14	HROW: mux CELL_E.GCLK_QUAD[6] bit 0	-
B13	HROW: mux CELL_E.GCLK_QUAD[5] bit 0	-
B12	HROW: mux CELL_E.GCLK_QUAD[4] bit 0	-
B11	HROW: mux CELL_E.GCLK_QUAD[3] bit 0	-
B10	HROW: mux CELL_E.GCLK_QUAD[2] bit 0	-
B9	HROW: mux CELL_E.GCLK_QUAD[1] bit 0	-
B8	HROW: mux CELL_E.GCLK_QUAD[0] bit 0	-
B7	HROW: mux CELL_W.GCLK_QUAD[7] bit 0	-
B6	HROW: mux CELL_W.GCLK_QUAD[6] bit 0	-
B5	HROW: mux CELL_W.GCLK_QUAD[5] bit 0	-
B4	HROW: mux CELL_W.GCLK_QUAD[4] bit 0	-
B3	HROW: mux CELL_W.GCLK_QUAD[3] bit 0	-
B2	HROW: mux CELL_W.GCLK_QUAD[2] bit 0	-
B1	HROW: mux CELL_W.GCLK_QUAD[1] bit 0	-
B0	HROW: mux CELL_W.GCLK_QUAD[0] bit 0	-

The `CLKQC` secondary clock center tiles

The CLKQC tiles are located on the intersection of secondary vertical clock spines and the horizontal clock spine.

TODO: document

Tile CLKQC_S3

Cells: 2

Switchbox HROW

spartan3 CLKQC_S3 switchbox HROW programmable buffers
Destination	Source	Bit
CELL_S.GCLK_QUAD[0]	CELL_N.GCLK_S[0]	CLK_S[0][38]
CELL_S.GCLK_QUAD[1]	CELL_N.GCLK_S[1]	CLK_S[0][36]
CELL_S.GCLK_QUAD[2]	CELL_N.GCLK_S[2]	CLK_S[0][34]
CELL_S.GCLK_QUAD[3]	CELL_N.GCLK_S[3]	CLK_S[0][30]
CELL_S.GCLK_QUAD[4]	CELL_N.GCLK_N[0]	CLK_S[0][31]
CELL_S.GCLK_QUAD[5]	CELL_N.GCLK_N[1]	CLK_S[0][32]
CELL_S.GCLK_QUAD[6]	CELL_N.GCLK_N[2]	CLK_S[0][33]
CELL_S.GCLK_QUAD[7]	CELL_N.GCLK_N[3]	CLK_S[0][35]
CELL_N.GCLK_QUAD[0]	CELL_N.GCLK_S[0]	CLK_N[0][25]
CELL_N.GCLK_QUAD[1]	CELL_N.GCLK_S[1]	CLK_N[0][27]
CELL_N.GCLK_QUAD[2]	CELL_N.GCLK_S[2]	CLK_N[0][29]
CELL_N.GCLK_QUAD[3]	CELL_N.GCLK_S[3]	CLK_N[0][33]
CELL_N.GCLK_QUAD[4]	CELL_N.GCLK_N[0]	CLK_N[0][32]
CELL_N.GCLK_QUAD[5]	CELL_N.GCLK_N[1]	CLK_N[0][31]
CELL_N.GCLK_QUAD[6]	CELL_N.GCLK_N[2]	CLK_N[0][30]
CELL_N.GCLK_QUAD[7]	CELL_N.GCLK_N[3]	CLK_N[0][28]

Bitstream

spartan3 CLKQC_S3 rect CLK_S
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	HROW: buffer CELL_S.GCLK_QUAD[0] ← CELL_N.GCLK_S[0]
B37	-
B36	HROW: buffer CELL_S.GCLK_QUAD[1] ← CELL_N.GCLK_S[1]
B35	HROW: buffer CELL_S.GCLK_QUAD[7] ← CELL_N.GCLK_N[3]
B34	HROW: buffer CELL_S.GCLK_QUAD[2] ← CELL_N.GCLK_S[2]
B33	HROW: buffer CELL_S.GCLK_QUAD[6] ← CELL_N.GCLK_N[2]
B32	HROW: buffer CELL_S.GCLK_QUAD[5] ← CELL_N.GCLK_N[1]
B31	HROW: buffer CELL_S.GCLK_QUAD[4] ← CELL_N.GCLK_N[0]
B30	HROW: buffer CELL_S.GCLK_QUAD[3] ← CELL_N.GCLK_S[3]
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLKQC_S3 rect CLK_N
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	HROW: buffer CELL_N.GCLK_QUAD[3] ← CELL_N.GCLK_S[3]
B32	HROW: buffer CELL_N.GCLK_QUAD[4] ← CELL_N.GCLK_N[0]
B31	HROW: buffer CELL_N.GCLK_QUAD[5] ← CELL_N.GCLK_N[1]
B30	HROW: buffer CELL_N.GCLK_QUAD[6] ← CELL_N.GCLK_N[2]
B29	HROW: buffer CELL_N.GCLK_QUAD[2] ← CELL_N.GCLK_S[2]
B28	HROW: buffer CELL_N.GCLK_QUAD[7] ← CELL_N.GCLK_N[3]
B27	HROW: buffer CELL_N.GCLK_QUAD[1] ← CELL_N.GCLK_S[1]
B26	-
B25	HROW: buffer CELL_N.GCLK_QUAD[0] ← CELL_N.GCLK_S[0]
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

Tile CLKQC_S3E

Cells: 2

Switchbox HROW

spartan3 CLKQC_S3E switchbox HROW muxes GCLK_QUAD[0]
Bits		Destination
CLK_S[0][57]	CLK_S[0][55]	CELL_S.GCLK_QUAD[0]
CLK_N[0][42]	CLK_N[0][41]	CELL_N.GCLK_QUAD[0]
		Source
0	0	off
0	1	CELL_N.GCLK_S[0]
1	0	CELL_N.GCLK_WE[0]

spartan3 CLKQC_S3E switchbox HROW muxes GCLK_QUAD[1]
Bits		Destination
CLK_S[0][54]	CLK_S[0][53]	CELL_S.GCLK_QUAD[1]
CLK_N[0][40]	CLK_N[0][39]	CELL_N.GCLK_QUAD[1]
		Source
0	0	off
0	1	CELL_N.GCLK_S[1]
1	0	CELL_N.GCLK_WE[1]

spartan3 CLKQC_S3E switchbox HROW muxes GCLK_QUAD[2]
Bits		Destination
CLK_S[0][52]	CLK_S[0][51]	CELL_S.GCLK_QUAD[2]
CLK_N[0][38]	CLK_N[0][37]	CELL_N.GCLK_QUAD[2]
		Source
0	0	off
0	1	CELL_N.GCLK_S[2]
1	0	CELL_N.GCLK_WE[2]

spartan3 CLKQC_S3E switchbox HROW muxes GCLK_QUAD[3]
Bits		Destination
CLK_S[0][50]	CLK_S[0][49]	CELL_S.GCLK_QUAD[3]
CLK_N[0][36]	CLK_N[0][34]	CELL_N.GCLK_QUAD[3]
		Source
0	0	off
0	1	CELL_N.GCLK_S[3]
1	0	CELL_N.GCLK_WE[3]

spartan3 CLKQC_S3E switchbox HROW muxes GCLK_QUAD[4]
Bits		Destination
CLK_S[0][28]	CLK_S[0][26]	CELL_S.GCLK_QUAD[4]
CLK_N[0][14]	CLK_N[0][12]	CELL_N.GCLK_QUAD[4]
		Source
0	0	off
0	1	CELL_N.GCLK_N[0]
1	0	CELL_N.GCLK_WE[4]

spartan3 CLKQC_S3E switchbox HROW muxes GCLK_QUAD[5]
Bits		Destination
CLK_S[0][25]	CLK_S[0][24]	CELL_S.GCLK_QUAD[5]
CLK_N[0][11]	CLK_N[0][10]	CELL_N.GCLK_QUAD[5]
		Source
0	0	off
0	1	CELL_N.GCLK_N[1]
1	0	CELL_N.GCLK_WE[5]

spartan3 CLKQC_S3E switchbox HROW muxes GCLK_QUAD[6]
Bits		Destination
CLK_S[0][23]	CLK_S[0][22]	CELL_S.GCLK_QUAD[6]
CLK_N[0][9]	CLK_N[0][8]	CELL_N.GCLK_QUAD[6]
		Source
0	0	off
0	1	CELL_N.GCLK_N[2]
1	0	CELL_N.GCLK_WE[6]

spartan3 CLKQC_S3E switchbox HROW muxes GCLK_QUAD[7]
Bits		Destination
CLK_S[0][21]	CLK_S[0][20]	CELL_S.GCLK_QUAD[7]
CLK_N[0][7]	CLK_N[0][6]	CELL_N.GCLK_QUAD[7]
		Source
0	0	off
0	1	CELL_N.GCLK_N[3]
1	0	CELL_N.GCLK_WE[7]

Bitstream

spartan3 CLKQC_S3E rect CLK_S
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	HROW: mux CELL_S.GCLK_QUAD[0] bit 1
B56	-
B55	HROW: mux CELL_S.GCLK_QUAD[0] bit 0
B54	HROW: mux CELL_S.GCLK_QUAD[1] bit 1
B53	HROW: mux CELL_S.GCLK_QUAD[1] bit 0
B52	HROW: mux CELL_S.GCLK_QUAD[2] bit 1
B51	HROW: mux CELL_S.GCLK_QUAD[2] bit 0
B50	HROW: mux CELL_S.GCLK_QUAD[3] bit 1
B49	HROW: mux CELL_S.GCLK_QUAD[3] bit 0
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	-
B37	-
B36	-
B35	-
B34	-
B33	-
B32	-
B31	-
B30	-
B29	-
B28	HROW: mux CELL_S.GCLK_QUAD[4] bit 1
B27	-
B26	HROW: mux CELL_S.GCLK_QUAD[4] bit 0
B25	HROW: mux CELL_S.GCLK_QUAD[5] bit 1
B24	HROW: mux CELL_S.GCLK_QUAD[5] bit 0
B23	HROW: mux CELL_S.GCLK_QUAD[6] bit 1
B22	HROW: mux CELL_S.GCLK_QUAD[6] bit 0
B21	HROW: mux CELL_S.GCLK_QUAD[7] bit 1
B20	HROW: mux CELL_S.GCLK_QUAD[7] bit 0
B19	-
B18	-
B17	-
B16	-
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

spartan3 CLKQC_S3E rect CLK_N
Bit	Frame
Bit	F0
B63	-
B62	-
B61	-
B60	-
B59	-
B58	-
B57	-
B56	-
B55	-
B54	-
B53	-
B52	-
B51	-
B50	-
B49	-
B48	-
B47	-
B46	-
B45	-
B44	-
B43	-
B42	HROW: mux CELL_N.GCLK_QUAD[0] bit 1
B41	HROW: mux CELL_N.GCLK_QUAD[0] bit 0
B40	HROW: mux CELL_N.GCLK_QUAD[1] bit 1
B39	HROW: mux CELL_N.GCLK_QUAD[1] bit 0
B38	HROW: mux CELL_N.GCLK_QUAD[2] bit 1
B37	HROW: mux CELL_N.GCLK_QUAD[2] bit 0
B36	HROW: mux CELL_N.GCLK_QUAD[3] bit 1
B35	-
B34	HROW: mux CELL_N.GCLK_QUAD[3] bit 0
B33	-
B32	-
B31	-
B30	-
B29	-
B28	-
B27	-
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	-
B19	-
B18	-
B17	-
B16	-
B15	-
B14	HROW: mux CELL_N.GCLK_QUAD[4] bit 1
B13	-
B12	HROW: mux CELL_N.GCLK_QUAD[4] bit 0
B11	HROW: mux CELL_N.GCLK_QUAD[5] bit 1
B10	HROW: mux CELL_N.GCLK_QUAD[5] bit 0
B9	HROW: mux CELL_N.GCLK_QUAD[6] bit 1
B8	HROW: mux CELL_N.GCLK_QUAD[6] bit 0
B7	HROW: mux CELL_N.GCLK_QUAD[7] bit 1
B6	HROW: mux CELL_N.GCLK_QUAD[7] bit 0
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-