Clock quadrant distribution
The CLKC clock center tile
The CLKC tile is located in the center of the FPGA (intersection of primary vertical and horizontal clock spines) of all devices except xc3s50a. It has permanent buffers forwarding the clock signals from CLKB and CLKT to GCLKVM. It has no configuration.
TODO: describe exact forwarding
The CLKC_50A clock center tile
TODO: document
| Bit | Frame | |
|---|---|---|
| 0 | 1 | |
| 15 | - | CLKC_50A:MUX.OUT_R7[0] |
| 14 | - | CLKC_50A:MUX.OUT_R6[0] |
| 13 | - | CLKC_50A:MUX.OUT_R5[0] |
| 12 | - | CLKC_50A:MUX.OUT_R4[0] |
| 11 | - | CLKC_50A:MUX.OUT_R3[0] |
| 10 | - | CLKC_50A:MUX.OUT_R2[0] |
| 9 | - | CLKC_50A:MUX.OUT_R1[0] |
| 8 | - | CLKC_50A:MUX.OUT_R0[0] |
| 7 | - | CLKC_50A:MUX.OUT_L7[0] |
| 6 | - | CLKC_50A:MUX.OUT_L6[0] |
| 5 | - | CLKC_50A:MUX.OUT_L5[0] |
| 4 | - | CLKC_50A:MUX.OUT_L4[0] |
| 3 | - | CLKC_50A:MUX.OUT_L3[0] |
| 2 | - | CLKC_50A:MUX.OUT_L2[0] |
| 1 | - | CLKC_50A:MUX.OUT_L1[0] |
| 0 | - | CLKC_50A:MUX.OUT_L0[0] |
| CLKC_50A:MUX.OUT_L0 | 0.1.0 |
|---|---|
| IN_B0 | 0 |
| IN_L0 | 1 |
| CLKC_50A:MUX.OUT_L1 | 0.1.1 |
|---|---|
| IN_B1 | 0 |
| IN_L1 | 1 |
| CLKC_50A:MUX.OUT_L2 | 0.1.2 |
|---|---|
| IN_B2 | 0 |
| IN_L2 | 1 |
| CLKC_50A:MUX.OUT_L3 | 0.1.3 |
|---|---|
| IN_B3 | 0 |
| IN_L3 | 1 |
| CLKC_50A:MUX.OUT_L4 | 0.1.4 |
|---|---|
| IN_T0 | 0 |
| IN_L4 | 1 |
| CLKC_50A:MUX.OUT_L5 | 0.1.5 |
|---|---|
| IN_T1 | 0 |
| IN_L5 | 1 |
| CLKC_50A:MUX.OUT_L6 | 0.1.6 |
|---|---|
| IN_T2 | 0 |
| IN_L6 | 1 |
| CLKC_50A:MUX.OUT_L7 | 0.1.7 |
|---|---|
| IN_T3 | 0 |
| IN_L7 | 1 |
| CLKC_50A:MUX.OUT_R0 | 0.1.8 |
|---|---|
| IN_B0 | 0 |
| IN_R0 | 1 |
| CLKC_50A:MUX.OUT_R1 | 0.1.9 |
|---|---|
| IN_B1 | 0 |
| IN_R1 | 1 |
| CLKC_50A:MUX.OUT_R2 | 0.1.10 |
|---|---|
| IN_B2 | 0 |
| IN_R2 | 1 |
| CLKC_50A:MUX.OUT_R3 | 0.1.11 |
|---|---|
| IN_B3 | 0 |
| IN_R3 | 1 |
| CLKC_50A:MUX.OUT_R4 | 0.1.12 |
|---|---|
| IN_T0 | 0 |
| IN_R4 | 1 |
| CLKC_50A:MUX.OUT_R5 | 0.1.13 |
|---|---|
| IN_T1 | 0 |
| IN_R5 | 1 |
| CLKC_50A:MUX.OUT_R6 | 0.1.14 |
|---|---|
| IN_T2 | 0 |
| IN_R6 | 1 |
| CLKC_50A:MUX.OUT_R7 | 0.1.15 |
|---|---|
| IN_T3 | 0 |
| IN_R7 | 1 |
The GCLKVM secondary clock center tiles
The GCLKVM tiles are located on the intersection of secondary vertical clock spines and the horizontal clock spine.
TODO: document
GCLKVM.S3
| Bit | Frame |
|---|---|
| 0 | |
| 38 | GCLKVM:BUF.OUT_B0 |
| 37 | - |
| 36 | GCLKVM:BUF.OUT_B1 |
| 35 | GCLKVM:BUF.OUT_B7 |
| 34 | GCLKVM:BUF.OUT_B2 |
| 33 | GCLKVM:BUF.OUT_B6 |
| 32 | GCLKVM:BUF.OUT_B5 |
| 31 | GCLKVM:BUF.OUT_B4 |
| 30 | GCLKVM:BUF.OUT_B3 |
| 29 | - |
| 28 | - |
| 27 | - |
| 26 | - |
| 25 | - |
| 24 | - |
| 23 | - |
| 22 | - |
| 21 | - |
| 20 | - |
| 19 | - |
| 18 | - |
| 17 | - |
| 16 | - |
| 15 | - |
| 14 | - |
| 13 | - |
| 12 | - |
| 11 | - |
| 10 | - |
| 9 | - |
| 8 | - |
| 7 | - |
| 6 | - |
| 5 | - |
| 4 | - |
| 3 | - |
| 2 | - |
| 1 | - |
| 0 | - |
| Bit | Frame |
|---|---|
| 0 | |
| 33 | GCLKVM:BUF.OUT_T3 |
| 32 | GCLKVM:BUF.OUT_T4 |
| 31 | GCLKVM:BUF.OUT_T5 |
| 30 | GCLKVM:BUF.OUT_T6 |
| 29 | GCLKVM:BUF.OUT_T2 |
| 28 | GCLKVM:BUF.OUT_T7 |
| 27 | GCLKVM:BUF.OUT_T1 |
| 26 | - |
| 25 | GCLKVM:BUF.OUT_T0 |
| 24 | - |
| 23 | - |
| 22 | - |
| 21 | - |
| 20 | - |
| 19 | - |
| 18 | - |
| 17 | - |
| 16 | - |
| 15 | - |
| 14 | - |
| 13 | - |
| 12 | - |
| 11 | - |
| 10 | - |
| 9 | - |
| 8 | - |
| 7 | - |
| 6 | - |
| 5 | - |
| 4 | - |
| 3 | - |
| 2 | - |
| 1 | - |
| 0 | - |
| GCLKVM:BUF.OUT_B0 | 0.0.38 |
|---|---|
| GCLKVM:BUF.OUT_B1 | 0.0.36 |
| GCLKVM:BUF.OUT_B2 | 0.0.34 |
| GCLKVM:BUF.OUT_B3 | 0.0.30 |
| GCLKVM:BUF.OUT_B4 | 0.0.31 |
| GCLKVM:BUF.OUT_B5 | 0.0.32 |
| GCLKVM:BUF.OUT_B6 | 0.0.33 |
| GCLKVM:BUF.OUT_B7 | 0.0.35 |
| GCLKVM:BUF.OUT_T0 | 1.0.25 |
| GCLKVM:BUF.OUT_T1 | 1.0.27 |
| GCLKVM:BUF.OUT_T2 | 1.0.29 |
| GCLKVM:BUF.OUT_T3 | 1.0.33 |
| GCLKVM:BUF.OUT_T4 | 1.0.32 |
| GCLKVM:BUF.OUT_T5 | 1.0.31 |
| GCLKVM:BUF.OUT_T6 | 1.0.30 |
| GCLKVM:BUF.OUT_T7 | 1.0.28 |
| non-inverted | [0] |
GCLKVM.S3E
| Bit | Frame |
|---|---|
| 0 | |
| 57 | GCLKVM:MUX.OUT_B0[0] |
| 56 | - |
| 55 | GCLKVM:MUX.OUT_B0[1] |
| 54 | GCLKVM:MUX.OUT_B1[0] |
| 53 | GCLKVM:MUX.OUT_B1[1] |
| 52 | GCLKVM:MUX.OUT_B2[0] |
| 51 | GCLKVM:MUX.OUT_B2[1] |
| 50 | GCLKVM:MUX.OUT_B3[0] |
| 49 | GCLKVM:MUX.OUT_B3[1] |
| 48 | - |
| 47 | - |
| 46 | - |
| 45 | - |
| 44 | - |
| 43 | - |
| 42 | - |
| 41 | - |
| 40 | - |
| 39 | - |
| 38 | - |
| 37 | - |
| 36 | - |
| 35 | - |
| 34 | - |
| 33 | - |
| 32 | - |
| 31 | - |
| 30 | - |
| 29 | - |
| 28 | GCLKVM:MUX.OUT_B4[0] |
| 27 | - |
| 26 | GCLKVM:MUX.OUT_B4[1] |
| 25 | GCLKVM:MUX.OUT_B5[0] |
| 24 | GCLKVM:MUX.OUT_B5[1] |
| 23 | GCLKVM:MUX.OUT_B6[0] |
| 22 | GCLKVM:MUX.OUT_B6[1] |
| 21 | GCLKVM:MUX.OUT_B7[0] |
| 20 | GCLKVM:MUX.OUT_B7[1] |
| 19 | - |
| 18 | - |
| 17 | - |
| 16 | - |
| 15 | - |
| 14 | - |
| 13 | - |
| 12 | - |
| 11 | - |
| 10 | - |
| 9 | - |
| 8 | - |
| 7 | - |
| 6 | - |
| 5 | - |
| 4 | - |
| 3 | - |
| 2 | - |
| 1 | - |
| 0 | - |
| Bit | Frame |
|---|---|
| 0 | |
| 42 | GCLKVM:MUX.OUT_T0[0] |
| 41 | GCLKVM:MUX.OUT_T0[1] |
| 40 | GCLKVM:MUX.OUT_T1[0] |
| 39 | GCLKVM:MUX.OUT_T1[1] |
| 38 | GCLKVM:MUX.OUT_T2[0] |
| 37 | GCLKVM:MUX.OUT_T2[1] |
| 36 | GCLKVM:MUX.OUT_T3[0] |
| 35 | - |
| 34 | GCLKVM:MUX.OUT_T3[1] |
| 33 | - |
| 32 | - |
| 31 | - |
| 30 | - |
| 29 | - |
| 28 | - |
| 27 | - |
| 26 | - |
| 25 | - |
| 24 | - |
| 23 | - |
| 22 | - |
| 21 | - |
| 20 | - |
| 19 | - |
| 18 | - |
| 17 | - |
| 16 | - |
| 15 | - |
| 14 | GCLKVM:MUX.OUT_T4[0] |
| 13 | - |
| 12 | GCLKVM:MUX.OUT_T4[1] |
| 11 | GCLKVM:MUX.OUT_T5[0] |
| 10 | GCLKVM:MUX.OUT_T5[1] |
| 9 | GCLKVM:MUX.OUT_T6[0] |
| 8 | GCLKVM:MUX.OUT_T6[1] |
| 7 | GCLKVM:MUX.OUT_T7[0] |
| 6 | GCLKVM:MUX.OUT_T7[1] |
| 5 | - |
| 4 | - |
| 3 | - |
| 2 | - |
| 1 | - |
| 0 | - |
| GCLKVM:MUX.OUT_B0 | 0.0.55 | 0.0.57 |
|---|---|---|
| GCLKVM:MUX.OUT_T0 | 1.0.41 | 1.0.42 |
| NONE | 0 | 0 |
| IN_LR0 | 0 | 1 |
| IN_CORE0 | 1 | 0 |
| GCLKVM:MUX.OUT_B1 | 0.0.53 | 0.0.54 |
|---|---|---|
| GCLKVM:MUX.OUT_T1 | 1.0.39 | 1.0.40 |
| NONE | 0 | 0 |
| IN_LR1 | 0 | 1 |
| IN_CORE1 | 1 | 0 |
| GCLKVM:MUX.OUT_B2 | 0.0.51 | 0.0.52 |
|---|---|---|
| GCLKVM:MUX.OUT_T2 | 1.0.37 | 1.0.38 |
| NONE | 0 | 0 |
| IN_LR2 | 0 | 1 |
| IN_CORE2 | 1 | 0 |
| GCLKVM:MUX.OUT_B3 | 0.0.49 | 0.0.50 |
|---|---|---|
| GCLKVM:MUX.OUT_T3 | 1.0.34 | 1.0.36 |
| NONE | 0 | 0 |
| IN_LR3 | 0 | 1 |
| IN_CORE3 | 1 | 0 |
| GCLKVM:MUX.OUT_B4 | 0.0.26 | 0.0.28 |
|---|---|---|
| GCLKVM:MUX.OUT_T4 | 1.0.12 | 1.0.14 |
| NONE | 0 | 0 |
| IN_LR4 | 0 | 1 |
| IN_CORE4 | 1 | 0 |
| GCLKVM:MUX.OUT_B5 | 0.0.24 | 0.0.25 |
|---|---|---|
| GCLKVM:MUX.OUT_T5 | 1.0.10 | 1.0.11 |
| NONE | 0 | 0 |
| IN_LR5 | 0 | 1 |
| IN_CORE5 | 1 | 0 |
| GCLKVM:MUX.OUT_B6 | 0.0.22 | 0.0.23 |
|---|---|---|
| GCLKVM:MUX.OUT_T6 | 1.0.8 | 1.0.9 |
| NONE | 0 | 0 |
| IN_LR6 | 0 | 1 |
| IN_CORE6 | 1 | 0 |
| GCLKVM:MUX.OUT_B7 | 0.0.20 | 0.0.21 |
|---|---|---|
| GCLKVM:MUX.OUT_T7 | 1.0.6 | 1.0.7 |
| NONE | 0 | 0 |
| IN_LR7 | 0 | 1 |
| IN_CORE7 | 1 | 0 |
The GCLKVC clock spine distribution tiles
TODO: document