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Configuration registers (Spartan 3A)

TODO: document

COR1.S3A

This is the Spartan 3A version of COR1.

spartan3 REG.COR1.S3A rect R0
BitFrame
F0
B0 STARTUP:STARTUPCLK[0]
B1 STARTUP:STARTUPCLK[1]
B2 STARTUP:DRIVE_DONE
B3 STARTUP:DONE_PIPE
B4 ~STARTUP:CRC
B5 STARTUP:VRDSEL[0]
B6 STARTUP:VRDSEL[1]
B7 STARTUP:VRDSEL[2]
B8 MISC:SEND_VGG[0]
B9 MISC:SEND_VGG[1]
B10 MISC:SEND_VGG[2]
B11 MISC:SEND_VGG[3]
B12 ~MISC:VGG_SENDMAX
B13 ~MISC:VGG_ENABLE_OFFCHIP
B14 -
B15 STARTUP:DRIVE_AWAKE
MISC:SEND_VGG 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8
non-inverted [3] [2] [1] [0]
MISC:VGG_ENABLE_OFFCHIP 0.F0.B13
MISC:VGG_SENDMAX 0.F0.B12
STARTUP:CRC 0.F0.B4
inverted ~[0]
STARTUP:DONE_PIPE 0.F0.B3
STARTUP:DRIVE_AWAKE 0.F0.B15
STARTUP:DRIVE_DONE 0.F0.B2
non-inverted [0]
STARTUP:STARTUPCLK 0.F0.B1 0.F0.B0
CCLK 0 0
USERCLK 0 1
JTAGCLK 1 0
STARTUP:VRDSEL 0.F0.B7 0.F0.B6 0.F0.B5
non-inverted [2] [1] [0]

COR2.S3A

This is the Spartan 3A version of COR2.

spartan3 REG.COR2.S3A rect R0
BitFrame
F0
B0 STARTUP:GWE_CYCLE[0]
B1 STARTUP:GWE_CYCLE[1]
B2 STARTUP:GWE_CYCLE[2]
B3 STARTUP:GTS_CYCLE[0]
B4 STARTUP:GTS_CYCLE[1]
B5 STARTUP:GTS_CYCLE[2]
B6 STARTUP:LCK_CYCLE[0]
B7 STARTUP:LCK_CYCLE[1]
B8 STARTUP:LCK_CYCLE[2]
B9 STARTUP:DONE_CYCLE[0]
B10 STARTUP:DONE_CYCLE[1]
B11 STARTUP:DONE_CYCLE[2]
B12 CAPTURE:ONESHOT
B13 STARTUP:BPI_DIV8
B14 ICAP:BYPASS
B15 STARTUP:RESET_ON_ERR
CAPTURE:ONESHOT 0.F0.B12
ICAP:BYPASS 0.F0.B14
STARTUP:BPI_DIV8 0.F0.B13
STARTUP:RESET_ON_ERR 0.F0.B15
non-inverted [0]
STARTUP:DONE_CYCLE 0.F0.B11 0.F0.B10 0.F0.B9
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
STARTUP:GTS_CYCLE 0.F0.B5 0.F0.B4 0.F0.B3
STARTUP:GWE_CYCLE 0.F0.B2 0.F0.B1 0.F0.B0
KEEP 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
DONE 1 1 1
STARTUP:LCK_CYCLE 0.F0.B8 0.F0.B7 0.F0.B6
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
NOWAIT 1 1 1

CTL.S3A

This is the Spartan 3A version of CTL.

spartan3 REG.CTL.S3A rect R0
BitFrame
F0
B0 MISC:GTS_USR_B
B1 MISC:VGG_TEST
B2 ICAP:ENABLE
B3 MISC:PERSIST
B4 MISC:SECURITY[0]
B5 MISC:SECURITY[1]
B6 -
B7 MISC:MULTIBOOT_ENABLE
ICAP:ENABLE 0.F0.B2
MISC:GTS_USR_B 0.F0.B0
MISC:MULTIBOOT_ENABLE 0.F0.B7
MISC:PERSIST 0.F0.B3
MISC:VGG_TEST 0.F0.B1
non-inverted [0]
MISC:SECURITY 0.F0.B5 0.F0.B4
NONE 0 0
LEVEL1 0 1
LEVEL2 1 0
LEVEL3 1 1

CCLK_FREQ

spartan3 REG.CCLK_FREQ rect R0
BitFrame
F0
B0 STARTUP:CONFIG_RATE[0]
B1 STARTUP:CONFIG_RATE[1]
B2 STARTUP:CONFIG_RATE[2]
B3 STARTUP:CONFIG_RATE[3]
B4 STARTUP:CONFIG_RATE[4]
B5 STARTUP:CONFIG_RATE[5]
B6 STARTUP:CONFIG_RATE[6]
B7 STARTUP:CONFIG_RATE[7]
B8 STARTUP:CONFIG_RATE[8]
B9 STARTUP:CONFIG_RATE[9]
B10 STARTUP:CCLK_DLY[0]
B11 STARTUP:CCLK_DLY[1]
B12 STARTUP:CCLK_SEP[0]
B13 STARTUP:CCLK_SEP[1]
B14 STARTUP:CLK_SWITCH_OPT[0]
B15 STARTUP:CLK_SWITCH_OPT[1]
STARTUP:CCLK_DLY 0.F0.B11 0.F0.B10
STARTUP:CCLK_SEP 0.F0.B13 0.F0.B12
STARTUP:CLK_SWITCH_OPT 0.F0.B15 0.F0.B14
non-inverted [1] [0]
STARTUP:CONFIG_RATE 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
100 0 0 0 0 0 0 0 0 1 1
50 0 0 0 0 0 0 0 1 1 1
44 0 0 0 0 0 0 1 0 0 0
33 0 0 0 0 0 0 1 0 1 1
27 0 0 0 0 0 0 1 1 1 0
25 0 0 0 0 0 0 1 1 1 1
22 0 0 0 0 0 1 0 0 0 1
17 0 0 0 0 0 1 0 1 1 1
13 0 0 0 0 0 1 1 1 1 0
12 0 0 0 0 1 0 0 0 0 0
10 0 0 0 0 1 0 0 1 1 1
8 0 0 0 0 1 1 0 0 0 1
7 0 0 0 0 1 1 1 0 0 0
6 0 0 0 1 0 0 0 0 1 0
3 0 0 1 0 0 0 0 1 0 0
1 0 1 1 0 0 0 1 1 1 1

HC_OPT

spartan3 REG.HC_OPT rect R0
BitFrame
F0
B0 MISC:HC_CYCLE[0]
B1 MISC:HC_CYCLE[1]
B2 MISC:HC_CYCLE[2]
B3 MISC:HC_CYCLE[3]
B4 MISC:TWO_ROUND
B5 MISC:BRAM_SKIP
MISC:BRAM_SKIP 0.F0.B5
MISC:TWO_ROUND 0.F0.B4
non-inverted [0]
MISC:HC_CYCLE 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [3] [2] [1] [0]

POWERDOWN

spartan3 REG.POWERDOWN rect R0
BitFrame
F0
B0 MISC:SW_CLK[0]
B1 ~MISC:EN_PORB
B2 MISC:EN_SUSPEND
B3 -
B4 MISC:EN_SW_GSR
B5 ~MISC:SUSPEND_FILTER
B6 MISC:WAKE_DELAY1[0]
B7 MISC:WAKE_DELAY1[1]
B8 MISC:WAKE_DELAY1[2]
B9 MISC:WAKE_DELAY2[0]
B10 MISC:WAKE_DELAY2[1]
B11 MISC:WAKE_DELAY2[2]
B12 MISC:WAKE_DELAY2[3]
B13 MISC:WAKE_DELAY2[4]
MISC:EN_PORB 0.F0.B1
MISC:SUSPEND_FILTER 0.F0.B5
inverted ~[0]
MISC:EN_SUSPEND 0.F0.B2
MISC:EN_SW_GSR 0.F0.B4
non-inverted [0]
MISC:SW_CLK 0.F0.B0
INTERNALCLK 0
STARTUPCLK 1
MISC:WAKE_DELAY1 0.F0.B8 0.F0.B7 0.F0.B6
non-inverted [2] [1] [0]
MISC:WAKE_DELAY2 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9
non-inverted [4] [3] [2] [1] [0]

PU_GWE

spartan3 REG.PU_GWE rect R0
BitFrame
F0
B0 MISC:SW_GWE_CYCLE[0]
B1 MISC:SW_GWE_CYCLE[1]
B2 MISC:SW_GWE_CYCLE[2]
B3 MISC:SW_GWE_CYCLE[3]
B4 MISC:SW_GWE_CYCLE[4]
B5 MISC:SW_GWE_CYCLE[5]
B6 MISC:SW_GWE_CYCLE[6]
B7 MISC:SW_GWE_CYCLE[7]
B8 MISC:SW_GWE_CYCLE[8]
B9 MISC:SW_GWE_CYCLE[9]
MISC:SW_GWE_CYCLE 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

PU_GTS

spartan3 REG.PU_GTS rect R0
BitFrame
F0
B0 MISC:SW_GTS_CYCLE[0]
B1 MISC:SW_GTS_CYCLE[1]
B2 MISC:SW_GTS_CYCLE[2]
B3 MISC:SW_GTS_CYCLE[3]
B4 MISC:SW_GTS_CYCLE[4]
B5 MISC:SW_GTS_CYCLE[5]
B6 MISC:SW_GTS_CYCLE[6]
B7 MISC:SW_GTS_CYCLE[7]
B8 MISC:SW_GTS_CYCLE[8]
B9 MISC:SW_GTS_CYCLE[9]
MISC:SW_GTS_CYCLE 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

MODE

spartan3 REG.MODE rect R0
BitFrame
F0
B0 MISC:BOOTVSEL[0]
B1 MISC:BOOTVSEL[1]
B2 MISC:BOOTVSEL[2]
B3 MISC:NEXT_CONFIG_BOOT_MODE[0]
B4 MISC:NEXT_CONFIG_BOOT_MODE[1]
B5 MISC:NEXT_CONFIG_BOOT_MODE[2]
B6 MISC:NEXT_CONFIG_NEW_MODE
B7 MISC:TESTMODE_EN
MISC:BOOTVSEL 0.F0.B2 0.F0.B1 0.F0.B0
MISC:NEXT_CONFIG_BOOT_MODE 0.F0.B5 0.F0.B4 0.F0.B3
non-inverted [2] [1] [0]
MISC:NEXT_CONFIG_NEW_MODE 0.F0.B6
MISC:TESTMODE_EN 0.F0.B7
non-inverted [0]

GENERAL[12]

spartan3 REG.GENERAL rect R0
BitFrame
F0
B0 MISC:NEXT_CONFIG_ADDR[0]
B1 MISC:NEXT_CONFIG_ADDR[1]
B2 MISC:NEXT_CONFIG_ADDR[2]
B3 MISC:NEXT_CONFIG_ADDR[3]
B4 MISC:NEXT_CONFIG_ADDR[4]
B5 MISC:NEXT_CONFIG_ADDR[5]
B6 MISC:NEXT_CONFIG_ADDR[6]
B7 MISC:NEXT_CONFIG_ADDR[7]
B8 MISC:NEXT_CONFIG_ADDR[8]
B9 MISC:NEXT_CONFIG_ADDR[9]
B10 MISC:NEXT_CONFIG_ADDR[10]
B11 MISC:NEXT_CONFIG_ADDR[11]
B12 MISC:NEXT_CONFIG_ADDR[12]
B13 MISC:NEXT_CONFIG_ADDR[13]
B14 MISC:NEXT_CONFIG_ADDR[14]
B15 MISC:NEXT_CONFIG_ADDR[15]
spartan3 REG.GENERAL rect R1
BitFrame
F0
B0 MISC:NEXT_CONFIG_ADDR[16]
B1 MISC:NEXT_CONFIG_ADDR[17]
B2 MISC:NEXT_CONFIG_ADDR[18]
B3 MISC:NEXT_CONFIG_ADDR[19]
B4 MISC:NEXT_CONFIG_ADDR[20]
B5 MISC:NEXT_CONFIG_ADDR[21]
B6 MISC:NEXT_CONFIG_ADDR[22]
B7 MISC:NEXT_CONFIG_ADDR[23]
B8 MISC:NEXT_CONFIG_ADDR[24]
B9 MISC:NEXT_CONFIG_ADDR[25]
B10 MISC:NEXT_CONFIG_ADDR[26]
B11 MISC:NEXT_CONFIG_ADDR[27]
B12 MISC:NEXT_CONFIG_ADDR[28]
B13 MISC:NEXT_CONFIG_ADDR[29]
B14 MISC:NEXT_CONFIG_ADDR[30]
B15 MISC:NEXT_CONFIG_ADDR[31]
MISC:NEXT_CONFIG_ADDR 1.F0.B15 1.F0.B14 1.F0.B13 1.F0.B12 1.F0.B11 1.F0.B10 1.F0.B9 1.F0.B8 1.F0.B7 1.F0.B6 1.F0.B5 1.F0.B4 1.F0.B3 1.F0.B2 1.F0.B1 1.F0.B0 0.F0.B15 0.F0.B14 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

SEU_OPT

spartan3 REG.SEU_OPT rect R0
BitFrame
F0
B0 MISC:POST_CRC_EN
B1 MISC:GLUTMASK
B2 -
B3 MISC:POST_CRC_KEEP
B4 MISC:POST_CRC_FREQ[0]
B5 MISC:POST_CRC_FREQ[1]
B6 MISC:POST_CRC_FREQ[2]
B7 MISC:POST_CRC_FREQ[3]
B8 MISC:POST_CRC_FREQ[4]
B9 MISC:POST_CRC_FREQ[5]
B10 MISC:POST_CRC_FREQ[6]
B11 MISC:POST_CRC_FREQ[7]
B12 MISC:POST_CRC_FREQ[8]
B13 MISC:POST_CRC_FREQ[9]
MISC:GLUTMASK 0.F0.B1
MISC:POST_CRC_EN 0.F0.B0
MISC:POST_CRC_KEEP 0.F0.B3
non-inverted [0]
MISC:POST_CRC_FREQ 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4
100 0 0 0 0 0 0 0 0 1 1
50 0 0 0 0 0 0 0 1 1 1
44 0 0 0 0 0 0 1 0 0 0
33 0 0 0 0 0 0 1 0 1 1
27 0 0 0 0 0 0 1 1 1 0
25 0 0 0 0 0 0 1 1 1 1
22 0 0 0 0 0 1 0 0 0 1
17 0 0 0 0 0 1 0 1 1 1
13 0 0 0 0 0 1 1 1 1 0
12 0 0 0 0 1 0 0 0 0 0
10 0 0 0 0 1 0 0 1 1 1
8 0 0 0 0 1 1 0 0 0 1
7 0 0 0 0 1 1 1 0 0 0
6 0 0 0 1 0 0 0 0 1 0
3 0 0 1 0 0 0 0 1 0 0
1 0 1 1 0 0 0 1 1 1 1

Device data

Device MISC:SEND_VGG_DEFAULT MISC:VGG_SENDMAX_DEFAULT
[3] [2] [1] [0] [0]
xc3s50 1 0 0 0 1
xa3s50 1 0 0 0 1
xc3s200 1 0 0 0 1
xa3s200 1 0 0 0 1
xc3s400 1 0 0 0 1
xa3s400 1 0 0 0 1
xc3s1000 1 0 0 0 1
xa3s1000 1 0 0 0 1
xc3s1000l 1 0 0 0 1
xc3s1500 1 0 0 0 1
xa3s1500 1 0 0 0 1
xc3s1500l 1 0 0 0 1
xc3s2000 1 0 0 0 1
xc3s4000 1 0 0 0 1
xc3s4000l 1 0 0 0 1
xc3s5000 1 0 0 0 1
xcexf10 0 0 0 0 1
xcexf20 0 0 0 0 1
xcexf40 0 0 0 0 1
xc3s100e 1 0 0 0 1
xa3s100e 1 0 0 0 1
xc3s250e 1 0 0 0 1
xa3s250e 1 0 0 0 1
xc3s500e 1 0 0 0 1
xa3s500e 1 0 0 0 1
xc3s1200e 1 0 0 0 1
xa3s1200e 1 0 0 0 1
xc3s1600e 1 0 0 0 1
xa3s1600e 1 0 0 0 1
xc3s50a 1 1 1 1 1
xc3s50an 1 1 1 1 1
xc3s200a 1 1 1 1 1
xa3s200a 1 1 1 1 1
xc3s200an 1 1 1 1 1
xc3s400a 1 1 1 1 1
xa3s400a 1 1 1 1 1
xc3s400an 1 1 1 1 1
xc3s700a 1 1 1 1 1
xa3s700a 1 1 1 1 1
xc3s700an 1 1 1 1 1
xc3s1400a 1 1 1 1 1
xa3s1400a 1 1 1 1 1
xc3s1400an 1 1 1 1 1
xc3sd1800a 1 1 1 1 1
xa3sd1800a 1 1 1 1 1
xc3sd3400a 1 1 1 1 1
xa3sd3400a 1 1 1 1 1